| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright 2023 Advanced Micro Devices, Inc. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the "Software"), |
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| 7 | * to deal in the Software without restriction, including without limitation |
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 10 | * Software is furnished to do so, subject to the following conditions: |
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| 11 | * |
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| 12 | * The above copyright notice and this permission notice shall be included in |
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| 13 | * all copies or substantial portions of the Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: AMD |
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| 24 | * |
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| 25 | */ |
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| 26 | |
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| 27 | #ifndef _DCN35_RESOURCE_H_ |
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| 28 | #define _DCN35_RESOURCE_H_ |
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| 29 | |
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| 30 | #include "core_types.h" |
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| 31 | |
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| 32 | #define DCN3_5_VMIN_DISPCLK_HZ 717000000 |
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| 33 | #define TO_DCN35_RES_POOL(pool)\ |
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| 34 | container_of(pool, struct dcn35_resource_pool, base) |
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| 35 | |
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| 36 | extern struct _vcs_dpi_ip_params_st dcn3_5_ip; |
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| 37 | extern struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc; |
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| 38 | |
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| 39 | struct dcn35_resource_pool { |
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| 40 | struct resource_pool base; |
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| 41 | }; |
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| 42 | |
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| 43 | struct resource_pool *dcn35_create_resource_pool( |
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| 44 | const struct dc_init_data *init_data, |
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| 45 | struct dc *dc); |
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| 46 | |
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| 47 | /* Defs for runtime init of registers */ |
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| 48 | |
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| 49 | #define OPP_REG_LIST_DCN20_RI(id) \ |
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| 50 | OPP_REG_LIST_DCN10_RI(id), \ |
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| 51 | OPP_DPG_REG_LIST_RI(id), \ |
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| 52 | SRI_ARR(FMT_422_CONTROL, FMT, id), \ |
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| 53 | SRI_ARR(OPPBUF_CONTROL1, OPPBUF, id) |
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| 54 | |
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| 55 | #define OPP_REG_LIST_DCN35_RI(id) \ |
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| 56 | OPP_REG_LIST_DCN20_RI(id), \ |
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| 57 | SRI2_ARR(OPP_TOP_CLK_CONTROL, OPP, id) |
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| 58 | |
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| 59 | #define VPG_DCN31_REG_LIST_RI(id) \ |
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| 60 | SRI_ARR(VPG_GENERIC_STATUS, VPG, id), \ |
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| 61 | SRI_ARR(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \ |
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| 62 | SRI_ARR(VPG_GENERIC_PACKET_DATA, VPG, id), \ |
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| 63 | SRI_ARR(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \ |
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| 64 | SRI_ARR(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \ |
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| 65 | SRI_ARR(VPG_MEM_PWR, VPG, id) |
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| 66 | |
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| 67 | #define AFMT_DCN31_REG_LIST_RI(id) \ |
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| 68 | SRI_ARR(AFMT_INFOFRAME_CONTROL0, AFMT, id), \ |
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| 69 | SRI_ARR(AFMT_VBI_PACKET_CONTROL, AFMT, id), \ |
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| 70 | SRI_ARR(AFMT_AUDIO_PACKET_CONTROL, AFMT, id), \ |
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| 71 | SRI_ARR(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id), \ |
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| 72 | SRI_ARR(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \ |
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| 73 | SRI_ARR(AFMT_60958_0, AFMT, id), \ |
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| 74 | SRI_ARR(AFMT_60958_1, AFMT, id), \ |
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| 75 | SRI_ARR(AFMT_60958_2, AFMT, id), \ |
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| 76 | SRI_ARR(AFMT_MEM_PWR, AFMT, id) |
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| 77 | |
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| 78 | /* Stream encoder */ |
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| 79 | #define SE_DCN35_REG_LIST_RI(id) \ |
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| 80 | SRI_ARR(AFMT_CNTL, DIG, id), \ |
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| 81 | SRI_ARR(DIG_FE_CNTL, DIG, id), \ |
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| 82 | SRI_ARR(HDMI_CONTROL, DIG, id), \ |
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| 83 | SRI_ARR(HDMI_DB_CONTROL, DIG, id), \ |
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| 84 | SRI_ARR(HDMI_GC, DIG, id), \ |
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| 85 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \ |
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| 86 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \ |
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| 87 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \ |
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| 88 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \ |
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| 89 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \ |
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| 90 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \ |
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| 91 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \ |
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| 92 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \ |
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| 93 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \ |
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| 94 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \ |
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| 95 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \ |
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| 96 | SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \ |
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| 97 | SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id), \ |
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| 98 | SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \ |
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| 99 | SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\ |
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| 100 | SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id),\ |
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| 101 | SRI_ARR(HDMI_ACR_32_0, DIG, id),\ |
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| 102 | SRI_ARR(HDMI_ACR_32_1, DIG, id),\ |
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| 103 | SRI_ARR(HDMI_ACR_44_0, DIG, id),\ |
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| 104 | SRI_ARR(HDMI_ACR_44_1, DIG, id),\ |
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| 105 | SRI_ARR(HDMI_ACR_48_0, DIG, id),\ |
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| 106 | SRI_ARR(HDMI_ACR_48_1, DIG, id),\ |
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| 107 | SRI_ARR(DP_DB_CNTL, DP, id), \ |
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| 108 | SRI_ARR(DP_MSA_MISC, DP, id), \ |
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| 109 | SRI_ARR(DP_MSA_VBID_MISC, DP, id), \ |
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| 110 | SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \ |
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| 111 | SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \ |
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| 112 | SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \ |
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| 113 | SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \ |
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| 114 | SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \ |
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| 115 | SRI_ARR(DP_MSE_RATE_CNTL, DP, id), \ |
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| 116 | SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \ |
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| 117 | SRI_ARR(DP_PIXEL_FORMAT, DP, id), \ |
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| 118 | SRI_ARR(DP_SEC_CNTL, DP, id), \ |
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| 119 | SRI_ARR(DP_SEC_CNTL1, DP, id), \ |
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| 120 | SRI_ARR(DP_SEC_CNTL2, DP, id), \ |
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| 121 | SRI_ARR(DP_SEC_CNTL5, DP, id), \ |
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| 122 | SRI_ARR(DP_SEC_CNTL6, DP, id), \ |
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| 123 | SRI_ARR(DP_STEER_FIFO, DP, id), \ |
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| 124 | SRI_ARR(DP_VID_M, DP, id), \ |
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| 125 | SRI_ARR(DP_VID_N, DP, id), \ |
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| 126 | SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \ |
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| 127 | SRI_ARR(DP_VID_TIMING, DP, id), \ |
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| 128 | SRI_ARR(DP_SEC_AUD_N, DP, id), \ |
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| 129 | SRI_ARR(DP_SEC_TIMESTAMP, DP, id), \ |
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| 130 | SRI_ARR(DP_DSC_CNTL, DP, id), \ |
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| 131 | SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \ |
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| 132 | SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ |
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| 133 | SRI_ARR(DP_SEC_FRAMING4, DP, id), \ |
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| 134 | SRI_ARR(DP_GSP11_CNTL, DP, id), \ |
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| 135 | SRI_ARR(DME_CONTROL, DME, id),\ |
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| 136 | SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \ |
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| 137 | SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ |
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| 138 | SRI_ARR(DIG_FE_CNTL, DIG, id), \ |
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| 139 | SRI_ARR(DIG_FE_EN_CNTL, DIG, id), \ |
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| 140 | SRI_ARR(DIG_FE_CLK_CNTL, DIG, id), \ |
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| 141 | SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \ |
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| 142 | SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \ |
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| 143 | SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id) |
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| 144 | |
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| 145 | #define LE_DCN35_REG_LIST_RI(id)\ |
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| 146 | LE_DCN3_REG_LIST_RI(id),\ |
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| 147 | SRI_ARR(DP_DPHY_INTERNAL_CTRL, DP, id), \ |
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| 148 | SR_ARR(DIO_LINKA_CNTL, id), \ |
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| 149 | SR_ARR(DIO_LINKB_CNTL, id), \ |
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| 150 | SR_ARR(DIO_LINKC_CNTL, id), \ |
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| 151 | SR_ARR(DIO_LINKD_CNTL, id), \ |
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| 152 | SR_ARR(DIO_LINKE_CNTL, id), \ |
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| 153 | SR_ARR(DIO_LINKF_CNTL, id),\ |
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| 154 | SRI_ARR(DIG_BE_CLK_CNTL, DIG, id),\ |
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| 155 | SR_ARR(DIO_CLK_CNTL, id) |
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| 156 | |
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| 157 | #define MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(inst) \ |
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| 158 | MCIF_WB_COMMON_REG_LIST_DCN32_RI(inst), \ |
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| 159 | SRI2_ARR(MMHUBBUB_CLOCK_CNTL, MMHUBBUB, inst) |
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| 160 | |
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| 161 | #define HWSEQ_DCN35_REG_LIST()\ |
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| 162 | SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ |
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| 163 | SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ |
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| 164 | SR(DIO_MEM_PWR_CTRL), \ |
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| 165 | SR(ODM_MEM_PWR_CTRL3), \ |
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| 166 | SR(MMHUBBUB_MEM_PWR_CNTL), \ |
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| 167 | SR(DCCG_GATE_DISABLE_CNTL), \ |
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| 168 | SR(DCCG_GATE_DISABLE_CNTL2), \ |
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| 169 | SR(DCCG_GATE_DISABLE_CNTL4), \ |
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| 170 | SR(DCCG_GATE_DISABLE_CNTL5), \ |
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| 171 | SR(DCFCLK_CNTL),\ |
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| 172 | SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ |
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| 173 | SRII(PIXEL_RATE_CNTL, OTG, 0), \ |
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| 174 | SRII(PIXEL_RATE_CNTL, OTG, 1),\ |
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| 175 | SRII(PIXEL_RATE_CNTL, OTG, 2),\ |
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| 176 | SRII(PIXEL_RATE_CNTL, OTG, 3),\ |
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| 177 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ |
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| 178 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ |
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| 179 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ |
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| 180 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ |
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| 181 | SR(MICROSECOND_TIME_BASE_DIV), \ |
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| 182 | SR(MILLISECOND_TIME_BASE_DIV), \ |
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| 183 | SR(DISPCLK_FREQ_CHANGE_CNTL), \ |
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| 184 | SR(RBBMIF_TIMEOUT_DIS), \ |
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| 185 | SR(RBBMIF_TIMEOUT_DIS_2), \ |
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| 186 | SR(DCHUBBUB_CRC_CTRL), \ |
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| 187 | SR(DPP_TOP0_DPP_CRC_CTRL), \ |
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| 188 | SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ |
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| 189 | SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ |
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| 190 | SR(MPC_CRC_CTRL), \ |
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| 191 | SR(MPC_CRC_RESULT_GB), \ |
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| 192 | SR(MPC_CRC_RESULT_C), \ |
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| 193 | SR(MPC_CRC_RESULT_AR), \ |
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| 194 | SR(DOMAIN0_PG_CONFIG), \ |
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| 195 | SR(DOMAIN1_PG_CONFIG), \ |
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| 196 | SR(DOMAIN2_PG_CONFIG), \ |
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| 197 | SR(DOMAIN3_PG_CONFIG), \ |
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| 198 | SR(DOMAIN16_PG_CONFIG), \ |
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| 199 | SR(DOMAIN17_PG_CONFIG), \ |
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| 200 | SR(DOMAIN18_PG_CONFIG), \ |
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| 201 | SR(DOMAIN19_PG_CONFIG), \ |
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| 202 | SR(DOMAIN0_PG_STATUS), \ |
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| 203 | SR(DOMAIN1_PG_STATUS), \ |
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| 204 | SR(DOMAIN2_PG_STATUS), \ |
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| 205 | SR(DOMAIN3_PG_STATUS), \ |
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| 206 | SR(DOMAIN16_PG_STATUS), \ |
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| 207 | SR(DOMAIN17_PG_STATUS), \ |
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| 208 | SR(DOMAIN18_PG_STATUS), \ |
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| 209 | SR(DOMAIN19_PG_STATUS), \ |
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| 210 | SR(DC_IP_REQUEST_CNTL), \ |
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| 211 | SR(AZALIA_AUDIO_DTO), \ |
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| 212 | SR(AZALIA_CONTROLLER_CLOCK_GATING), \ |
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| 213 | SR(HPO_TOP_HW_CONTROL),\ |
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| 214 | SR(DMU_CLK_CNTL) |
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| 215 | |
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| 216 | /* OPTC */ |
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| 217 | #define OPTC_COMMON_REG_LIST_DCN3_5_RI(inst) \ |
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| 218 | SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst),\ |
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| 219 | SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst),\ |
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| 220 | SRI_ARR(OTG_VREADY_PARAM, OTG, inst),\ |
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| 221 | SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst),\ |
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| 222 | SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst),\ |
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| 223 | SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),\ |
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| 224 | SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),\ |
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| 225 | SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst),\ |
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| 226 | SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\ |
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| 227 | SRI_ARR(OTG_H_TOTAL, OTG, inst),\ |
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| 228 | SRI_ARR(OTG_H_BLANK_START_END, OTG, inst),\ |
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| 229 | SRI_ARR(OTG_H_SYNC_A, OTG, inst),\ |
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| 230 | SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst),\ |
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| 231 | SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst),\ |
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| 232 | SRI_ARR(OTG_V_TOTAL, OTG, inst),\ |
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| 233 | SRI_ARR(OTG_V_BLANK_START_END, OTG, inst),\ |
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| 234 | SRI_ARR(OTG_V_SYNC_A, OTG, inst),\ |
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| 235 | SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst),\ |
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| 236 | SRI_ARR(OTG_CONTROL, OTG, inst),\ |
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| 237 | SRI_ARR(OTG_STEREO_CONTROL, OTG, inst),\ |
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| 238 | SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\ |
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| 239 | SRI_ARR(OTG_STEREO_STATUS, OTG, inst),\ |
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| 240 | SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst),\ |
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| 241 | SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst),\ |
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| 242 | SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst),\ |
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| 243 | SRI_ARR(OTG_TRIGA_CNTL, OTG, inst),\ |
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| 244 | SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\ |
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| 245 | SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\ |
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| 246 | SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst),\ |
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| 247 | SRI_ARR(OTG_STATUS, OTG, inst),\ |
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| 248 | SRI_ARR(OTG_STATUS_POSITION, OTG, inst),\ |
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| 249 | SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst),\ |
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| 250 | SRI_ARR(OTG_M_CONST_DTO0, OTG, inst),\ |
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| 251 | SRI_ARR(OTG_M_CONST_DTO1, OTG, inst),\ |
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| 252 | SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst),\ |
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| 253 | SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\ |
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| 254 | SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\ |
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| 255 | SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\ |
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| 256 | SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\ |
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| 257 | SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\ |
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| 258 | SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\ |
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| 259 | SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\ |
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| 260 | SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst),\ |
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| 261 | SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ |
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| 262 | SRI_ARR(CONTROL, VTG, inst),\ |
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| 263 | SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst),\ |
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| 264 | SRI_ARR(OTG_GSL_CONTROL, OTG, inst),\ |
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| 265 | SRI_ARR(OTG_CRC_CNTL, OTG, inst),\ |
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| 266 | SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst),\ |
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| 267 | SRI_ARR(OTG_CRC0_DATA_B, OTG, inst),\ |
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| 268 | SRI_ARR(OTG_CRC1_DATA_RG, OTG, inst),\ |
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| 269 | SRI_ARR(OTG_CRC1_DATA_B, OTG, inst),\ |
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| 270 | SRI_ARR(OTG_CRC2_DATA_RG, OTG, inst),\ |
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| 271 | SRI_ARR(OTG_CRC2_DATA_B, OTG, inst),\ |
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| 272 | SRI_ARR(OTG_CRC3_DATA_RG, OTG, inst),\ |
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| 273 | SRI_ARR(OTG_CRC3_DATA_B, OTG, inst),\ |
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| 274 | SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\ |
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| 275 | SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\ |
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| 276 | SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\ |
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| 277 | SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\ |
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| 278 | SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\ |
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| 279 | SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\ |
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| 280 | SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\ |
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| 281 | SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\ |
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| 282 | SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG, inst),\ |
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| 283 | SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\ |
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| 284 | SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG, inst),\ |
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| 285 | SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\ |
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| 286 | SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG, inst),\ |
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| 287 | SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\ |
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| 288 | SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG, inst),\ |
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| 289 | SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\ |
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| 290 | SR_ARR(GSL_SOURCE_SELECT, inst),\ |
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| 291 | SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\ |
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| 292 | SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),\ |
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| 293 | SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),\ |
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| 294 | SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst),\ |
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| 295 | SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst),\ |
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| 296 | SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst),\ |
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| 297 | SRI_ARR(OTG_DSC_START_POSITION, OTG, inst),\ |
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| 298 | SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\ |
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| 299 | SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\ |
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| 300 | SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\ |
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| 301 | SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst),\ |
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| 302 | SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst),\ |
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| 303 | SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),\ |
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| 304 | SRI_ARR(OTG_DRR_CONTROL, OTG, inst),\ |
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| 305 | SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst) |
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| 306 | |
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| 307 | /* DPP */ |
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| 308 | #define DPP_REG_LIST_DCN35_RI(id)\ |
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| 309 | DPP_REG_LIST_DCN30_COMMON_RI(id) |
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| 310 | |
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| 311 | #endif /* _DCN35_RESOURCE_H_ */ |
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| 312 | |
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