Warning: This file is not a C or C++ file. It does not have highlighting.
| 1 | /* |
|---|---|
| 2 | * BIF_5_0 Register documentation |
| 3 | * |
| 4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included |
| 14 | * in all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #ifndef BIF_5_0_SH_MASK_H |
| 25 | #define BIF_5_0_SH_MASK_H |
| 26 | |
| 27 | #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff |
| 28 | #define MM_INDEX__MM_OFFSET__SHIFT 0x0 |
| 29 | #define MM_INDEX__MM_APER_MASK 0x80000000 |
| 30 | #define MM_INDEX__MM_APER__SHIFT 0x1f |
| 31 | #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff |
| 32 | #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
| 33 | #define MM_DATA__MM_DATA_MASK 0xffffffff |
| 34 | #define MM_DATA__MM_DATA__SHIFT 0x0 |
| 35 | #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2 |
| 36 | #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1 |
| 37 | #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2 |
| 38 | #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 |
| 39 | #define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x1 |
| 40 | #define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
| 41 | #define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1 |
| 42 | #define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0 |
| 43 | #define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2 |
| 44 | #define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1 |
| 45 | #define BUS_CNTL__PMI_IO_DIS_MASK 0x4 |
| 46 | #define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 |
| 47 | #define BUS_CNTL__PMI_MEM_DIS_MASK 0x8 |
| 48 | #define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 |
| 49 | #define BUS_CNTL__PMI_BM_DIS_MASK 0x10 |
| 50 | #define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 |
| 51 | #define BUS_CNTL__PMI_INT_DIS_MASK 0x20 |
| 52 | #define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5 |
| 53 | #define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40 |
| 54 | #define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 |
| 55 | #define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80 |
| 56 | #define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 |
| 57 | #define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100 |
| 58 | #define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8 |
| 59 | #define BUS_CNTL__SET_AZ_TC_MASK 0x1c00 |
| 60 | #define BUS_CNTL__SET_AZ_TC__SHIFT 0xa |
| 61 | #define BUS_CNTL__SET_MC_TC_MASK 0xe000 |
| 62 | #define BUS_CNTL__SET_MC_TC__SHIFT 0xd |
| 63 | #define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000 |
| 64 | #define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 |
| 65 | #define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000 |
| 66 | #define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 |
| 67 | #define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000 |
| 68 | #define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 |
| 69 | #define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1 |
| 70 | #define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 |
| 71 | #define CONFIG_CNTL__VGA_DIS_MASK 0x2 |
| 72 | #define CONFIG_CNTL__VGA_DIS__SHIFT 0x1 |
| 73 | #define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4 |
| 74 | #define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 |
| 75 | #define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18 |
| 76 | #define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 |
| 77 | #define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff |
| 78 | #define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
| 79 | #define CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xffffffff |
| 80 | #define CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
| 81 | #define BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x1 |
| 82 | #define BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
| 83 | #define BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000 |
| 84 | #define BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
| 85 | #define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff |
| 86 | #define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 |
| 87 | #define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff |
| 88 | #define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 |
| 89 | #define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff |
| 90 | #define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 |
| 91 | #define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff |
| 92 | #define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 |
| 93 | #define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff |
| 94 | #define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 |
| 95 | #define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT_MASK 0x1 |
| 96 | #define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT__SHIFT 0x0 |
| 97 | #define BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT_MASK 0x100 |
| 98 | #define BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT__SHIFT 0x8 |
| 99 | #define BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x1 |
| 100 | #define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
| 101 | #define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x10000 |
| 102 | #define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
| 103 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x1 |
| 104 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
| 105 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x2 |
| 106 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
| 107 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x10000 |
| 108 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
| 109 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x20000 |
| 110 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
| 111 | #define BX_RESET_EN__COR_RESET_EN_MASK 0x1 |
| 112 | #define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 |
| 113 | #define BX_RESET_EN__REG_RESET_EN_MASK 0x2 |
| 114 | #define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 |
| 115 | #define BX_RESET_EN__STY_RESET_EN_MASK 0x4 |
| 116 | #define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 |
| 117 | #define BX_RESET_EN__FLR_TWICE_EN_MASK 0x100 |
| 118 | #define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8 |
| 119 | #define BX_RESET_EN__FLR_TIMER_SEL_MASK 0x600 |
| 120 | #define BX_RESET_EN__FLR_TIMER_SEL__SHIFT 0x9 |
| 121 | #define BX_RESET_EN__DB_APER_RESET_EN_MASK 0x8000 |
| 122 | #define BX_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf |
| 123 | #define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x10000 |
| 124 | #define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 |
| 125 | #define BX_RESET_EN__PF_FLR_NEWHDL_EN_MASK 0x20000 |
| 126 | #define BX_RESET_EN__PF_FLR_NEWHDL_EN__SHIFT 0x11 |
| 127 | #define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7 |
| 128 | #define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 |
| 129 | #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8 |
| 130 | #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3 |
| 131 | #define HW_DEBUG__HW_00_DEBUG_MASK 0x1 |
| 132 | #define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 |
| 133 | #define HW_DEBUG__HW_01_DEBUG_MASK 0x2 |
| 134 | #define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 |
| 135 | #define HW_DEBUG__HW_02_DEBUG_MASK 0x4 |
| 136 | #define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 |
| 137 | #define HW_DEBUG__HW_03_DEBUG_MASK 0x8 |
| 138 | #define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 |
| 139 | #define HW_DEBUG__HW_04_DEBUG_MASK 0x10 |
| 140 | #define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 |
| 141 | #define HW_DEBUG__HW_05_DEBUG_MASK 0x20 |
| 142 | #define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 |
| 143 | #define HW_DEBUG__HW_06_DEBUG_MASK 0x40 |
| 144 | #define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 |
| 145 | #define HW_DEBUG__HW_07_DEBUG_MASK 0x80 |
| 146 | #define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 |
| 147 | #define HW_DEBUG__HW_08_DEBUG_MASK 0x100 |
| 148 | #define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 |
| 149 | #define HW_DEBUG__HW_09_DEBUG_MASK 0x200 |
| 150 | #define HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 |
| 151 | #define HW_DEBUG__HW_10_DEBUG_MASK 0x400 |
| 152 | #define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa |
| 153 | #define HW_DEBUG__HW_11_DEBUG_MASK 0x800 |
| 154 | #define HW_DEBUG__HW_11_DEBUG__SHIFT 0xb |
| 155 | #define HW_DEBUG__HW_12_DEBUG_MASK 0x1000 |
| 156 | #define HW_DEBUG__HW_12_DEBUG__SHIFT 0xc |
| 157 | #define HW_DEBUG__HW_13_DEBUG_MASK 0x2000 |
| 158 | #define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd |
| 159 | #define HW_DEBUG__HW_14_DEBUG_MASK 0x4000 |
| 160 | #define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe |
| 161 | #define HW_DEBUG__HW_15_DEBUG_MASK 0x8000 |
| 162 | #define HW_DEBUG__HW_15_DEBUG__SHIFT 0xf |
| 163 | #define HW_DEBUG__HW_16_DEBUG_MASK 0x10000 |
| 164 | #define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10 |
| 165 | #define HW_DEBUG__HW_17_DEBUG_MASK 0x20000 |
| 166 | #define HW_DEBUG__HW_17_DEBUG__SHIFT 0x11 |
| 167 | #define HW_DEBUG__HW_18_DEBUG_MASK 0x40000 |
| 168 | #define HW_DEBUG__HW_18_DEBUG__SHIFT 0x12 |
| 169 | #define HW_DEBUG__HW_19_DEBUG_MASK 0x80000 |
| 170 | #define HW_DEBUG__HW_19_DEBUG__SHIFT 0x13 |
| 171 | #define HW_DEBUG__HW_20_DEBUG_MASK 0x100000 |
| 172 | #define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14 |
| 173 | #define HW_DEBUG__HW_21_DEBUG_MASK 0x200000 |
| 174 | #define HW_DEBUG__HW_21_DEBUG__SHIFT 0x15 |
| 175 | #define HW_DEBUG__HW_22_DEBUG_MASK 0x400000 |
| 176 | #define HW_DEBUG__HW_22_DEBUG__SHIFT 0x16 |
| 177 | #define HW_DEBUG__HW_23_DEBUG_MASK 0x800000 |
| 178 | #define HW_DEBUG__HW_23_DEBUG__SHIFT 0x17 |
| 179 | #define HW_DEBUG__HW_24_DEBUG_MASK 0x1000000 |
| 180 | #define HW_DEBUG__HW_24_DEBUG__SHIFT 0x18 |
| 181 | #define HW_DEBUG__HW_25_DEBUG_MASK 0x2000000 |
| 182 | #define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19 |
| 183 | #define HW_DEBUG__HW_26_DEBUG_MASK 0x4000000 |
| 184 | #define HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a |
| 185 | #define HW_DEBUG__HW_27_DEBUG_MASK 0x8000000 |
| 186 | #define HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b |
| 187 | #define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000 |
| 188 | #define HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c |
| 189 | #define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000 |
| 190 | #define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d |
| 191 | #define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000 |
| 192 | #define HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e |
| 193 | #define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000 |
| 194 | #define HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f |
| 195 | #define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x7f |
| 196 | #define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x0 |
| 197 | #define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000 |
| 198 | #define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10 |
| 199 | #define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x1f |
| 200 | #define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x0 |
| 201 | #define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x1e0 |
| 202 | #define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x5 |
| 203 | #define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x7c00 |
| 204 | #define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa |
| 205 | #define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x8000 |
| 206 | #define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0xf |
| 207 | #define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x100000 |
| 208 | #define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14 |
| 209 | #define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000 |
| 210 | #define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19 |
| 211 | #define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x1 |
| 212 | #define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 |
| 213 | #define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x1 |
| 214 | #define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 |
| 215 | #define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2 |
| 216 | #define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 |
| 217 | #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8 |
| 218 | #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 |
| 219 | #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0xf0 |
| 220 | #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 |
| 221 | #define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100 |
| 222 | #define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 |
| 223 | #define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x1e00 |
| 224 | #define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x9 |
| 225 | #define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x6000 |
| 226 | #define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd |
| 227 | #define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000 |
| 228 | #define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf |
| 229 | #define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffff |
| 230 | #define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 |
| 231 | #define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x1 |
| 232 | #define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x0 |
| 233 | #define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2 |
| 234 | #define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x1 |
| 235 | #define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4 |
| 236 | #define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2 |
| 237 | #define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8 |
| 238 | #define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x3 |
| 239 | #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10 |
| 240 | #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4 |
| 241 | #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x20 |
| 242 | #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x5 |
| 243 | #define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x40 |
| 244 | #define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x6 |
| 245 | #define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x80 |
| 246 | #define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x7 |
| 247 | #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x1f00 |
| 248 | #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8 |
| 249 | #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x1f0000 |
| 250 | #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10 |
| 251 | #define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x1000000 |
| 252 | #define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x18 |
| 253 | #define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000 |
| 254 | #define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x1e |
| 255 | #define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x3f |
| 256 | #define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x0 |
| 257 | #define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x3f00 |
| 258 | #define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8 |
| 259 | #define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x1ffff |
| 260 | #define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x0 |
| 261 | #define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x1 |
| 262 | #define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
| 263 | #define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x1 |
| 264 | #define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
| 265 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x1 |
| 266 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 |
| 267 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2 |
| 268 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 |
| 269 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4 |
| 270 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 |
| 271 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x18 |
| 272 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 |
| 273 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x20 |
| 274 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 |
| 275 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40 |
| 276 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 |
| 277 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x80 |
| 278 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 |
| 279 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100 |
| 280 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 |
| 281 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200 |
| 282 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 |
| 283 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x400 |
| 284 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa |
| 285 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800 |
| 286 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb |
| 287 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x1000 |
| 288 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc |
| 289 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x2000 |
| 290 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd |
| 291 | #define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER_MASK 0xff000000 |
| 292 | #define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__SHIFT 0x18 |
| 293 | #define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER_MASK 0xffffffff |
| 294 | #define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__SHIFT 0x0 |
| 295 | #define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff |
| 296 | #define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 |
| 297 | #define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000 |
| 298 | #define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f |
| 299 | #define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff |
| 300 | #define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 |
| 301 | #define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x1 |
| 302 | #define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 |
| 303 | #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2 |
| 304 | #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 |
| 305 | #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x4 |
| 306 | #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 |
| 307 | #define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x8 |
| 308 | #define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 |
| 309 | #define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10 |
| 310 | #define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 |
| 311 | #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20 |
| 312 | #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 |
| 313 | #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40 |
| 314 | #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 |
| 315 | #define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80 |
| 316 | #define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7 |
| 317 | #define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100 |
| 318 | #define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8 |
| 319 | #define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200 |
| 320 | #define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9 |
| 321 | #define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400 |
| 322 | #define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa |
| 323 | #define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800 |
| 324 | #define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb |
| 325 | #define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000 |
| 326 | #define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc |
| 327 | #define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x2000 |
| 328 | #define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd |
| 329 | #define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x8000 |
| 330 | #define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf |
| 331 | #define BIF_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x10000 |
| 332 | #define BIF_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x10 |
| 333 | #define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x20000 |
| 334 | #define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11 |
| 335 | #define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x40000 |
| 336 | #define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12 |
| 337 | #define BIF_FEATURES_CONTROL_MISC__SOFT_PF_FLR_UR_CFG_EN_MASK 0x80000 |
| 338 | #define BIF_FEATURES_CONTROL_MISC__SOFT_PF_FLR_UR_CFG_EN__SHIFT 0x13 |
| 339 | #define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_UR_DIS_MASK 0x100000 |
| 340 | #define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_UR_DIS__SHIFT 0x14 |
| 341 | #define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_HDL_DIS_MASK 0x200000 |
| 342 | #define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_HDL_DIS__SHIFT 0x15 |
| 343 | #define BIF_FEATURES_CONTROL_MISC__FLR_NEWREQ_HDL_DIS_MASK 0x400000 |
| 344 | #define BIF_FEATURES_CONTROL_MISC__FLR_NEWREQ_HDL_DIS__SHIFT 0x16 |
| 345 | #define BIF_FEATURES_CONTROL_MISC__FLR_CRS_CFG_DIS_MASK 0x800000 |
| 346 | #define BIF_FEATURES_CONTROL_MISC__FLR_CRS_CFG_DIS__SHIFT 0x17 |
| 347 | #define BIF_FEATURES_CONTROL_MISC__DUMMY_TRANS_CPL_RET_DIS_MASK 0x1000000 |
| 348 | #define BIF_FEATURES_CONTROL_MISC__DUMMY_TRANS_CPL_RET_DIS__SHIFT 0x18 |
| 349 | #define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x1 |
| 350 | #define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 |
| 351 | #define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2 |
| 352 | #define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 |
| 353 | #define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x4 |
| 354 | #define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 |
| 355 | #define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8 |
| 356 | #define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 |
| 357 | #define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x10 |
| 358 | #define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 |
| 359 | #define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x20 |
| 360 | #define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5 |
| 361 | #define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000 |
| 362 | #define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 |
| 363 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x1000000 |
| 364 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 |
| 365 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x2000000 |
| 366 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 |
| 367 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x4000000 |
| 368 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a |
| 369 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x8000000 |
| 370 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b |
| 371 | #define BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x3 |
| 372 | #define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0 |
| 373 | #define BIF_CLK_CTRL__BIF_XSTCLK_READY_MASK 0x1 |
| 374 | #define BIF_CLK_CTRL__BIF_XSTCLK_READY__SHIFT 0x0 |
| 375 | #define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS_MASK 0x2 |
| 376 | #define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__SHIFT 0x1 |
| 377 | #define BIF_FB_EN__FB_READ_EN_MASK 0x1 |
| 378 | #define BIF_FB_EN__FB_READ_EN__SHIFT 0x0 |
| 379 | #define BIF_FB_EN__FB_WRITE_EN_MASK 0x2 |
| 380 | #define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 |
| 381 | #define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0xff |
| 382 | #define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 |
| 383 | #define BIF_BUSNUM_LIST0__ID0_MASK 0xff |
| 384 | #define BIF_BUSNUM_LIST0__ID0__SHIFT 0x0 |
| 385 | #define BIF_BUSNUM_LIST0__ID1_MASK 0xff00 |
| 386 | #define BIF_BUSNUM_LIST0__ID1__SHIFT 0x8 |
| 387 | #define BIF_BUSNUM_LIST0__ID2_MASK 0xff0000 |
| 388 | #define BIF_BUSNUM_LIST0__ID2__SHIFT 0x10 |
| 389 | #define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000 |
| 390 | #define BIF_BUSNUM_LIST0__ID3__SHIFT 0x18 |
| 391 | #define BIF_BUSNUM_LIST1__ID4_MASK 0xff |
| 392 | #define BIF_BUSNUM_LIST1__ID4__SHIFT 0x0 |
| 393 | #define BIF_BUSNUM_LIST1__ID5_MASK 0xff00 |
| 394 | #define BIF_BUSNUM_LIST1__ID5__SHIFT 0x8 |
| 395 | #define BIF_BUSNUM_LIST1__ID6_MASK 0xff0000 |
| 396 | #define BIF_BUSNUM_LIST1__ID6__SHIFT 0x10 |
| 397 | #define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000 |
| 398 | #define BIF_BUSNUM_LIST1__ID7__SHIFT 0x18 |
| 399 | #define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0xff |
| 400 | #define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 |
| 401 | #define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100 |
| 402 | #define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 |
| 403 | #define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x10000 |
| 404 | #define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 |
| 405 | #define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000 |
| 406 | #define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 |
| 407 | #define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x3f |
| 408 | #define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 |
| 409 | #define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x1 |
| 410 | #define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0 |
| 411 | #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2 |
| 412 | #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1 |
| 413 | #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x4 |
| 414 | #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2 |
| 415 | #define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x1f00 |
| 416 | #define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8 |
| 417 | #define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x3e000 |
| 418 | #define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd |
| 419 | #define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff |
| 420 | #define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 |
| 421 | #define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff |
| 422 | #define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 |
| 423 | #define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe |
| 424 | #define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1 |
| 425 | #define GPU_HDP_FLUSH_REQ__CP0_MASK 0x1 |
| 426 | #define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
| 427 | #define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2 |
| 428 | #define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
| 429 | #define GPU_HDP_FLUSH_REQ__CP2_MASK 0x4 |
| 430 | #define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
| 431 | #define GPU_HDP_FLUSH_REQ__CP3_MASK 0x8 |
| 432 | #define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
| 433 | #define GPU_HDP_FLUSH_REQ__CP4_MASK 0x10 |
| 434 | #define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
| 435 | #define GPU_HDP_FLUSH_REQ__CP5_MASK 0x20 |
| 436 | #define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
| 437 | #define GPU_HDP_FLUSH_REQ__CP6_MASK 0x40 |
| 438 | #define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
| 439 | #define GPU_HDP_FLUSH_REQ__CP7_MASK 0x80 |
| 440 | #define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
| 441 | #define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100 |
| 442 | #define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
| 443 | #define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200 |
| 444 | #define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
| 445 | #define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x400 |
| 446 | #define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
| 447 | #define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800 |
| 448 | #define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
| 449 | #define GPU_HDP_FLUSH_DONE__CP0_MASK 0x1 |
| 450 | #define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
| 451 | #define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2 |
| 452 | #define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
| 453 | #define GPU_HDP_FLUSH_DONE__CP2_MASK 0x4 |
| 454 | #define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
| 455 | #define GPU_HDP_FLUSH_DONE__CP3_MASK 0x8 |
| 456 | #define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
| 457 | #define GPU_HDP_FLUSH_DONE__CP4_MASK 0x10 |
| 458 | #define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
| 459 | #define GPU_HDP_FLUSH_DONE__CP5_MASK 0x20 |
| 460 | #define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
| 461 | #define GPU_HDP_FLUSH_DONE__CP6_MASK 0x40 |
| 462 | #define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
| 463 | #define GPU_HDP_FLUSH_DONE__CP7_MASK 0x80 |
| 464 | #define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
| 465 | #define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100 |
| 466 | #define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
| 467 | #define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200 |
| 468 | #define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
| 469 | #define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x400 |
| 470 | #define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
| 471 | #define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800 |
| 472 | #define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
| 473 | #define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x1 |
| 474 | #define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x0 |
| 475 | #define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2 |
| 476 | #define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x1 |
| 477 | #define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x4 |
| 478 | #define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2 |
| 479 | #define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x8 |
| 480 | #define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x3 |
| 481 | #define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x10 |
| 482 | #define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x4 |
| 483 | #define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x20 |
| 484 | #define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x5 |
| 485 | #define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK 0x80 |
| 486 | #define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT 0x7 |
| 487 | #define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK 0x100 |
| 488 | #define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT 0x8 |
| 489 | #define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200 |
| 490 | #define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT 0x9 |
| 491 | #define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x1 |
| 492 | #define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 |
| 493 | #define HOST_BUSNUM__HOST_ID_MASK 0xffff |
| 494 | #define HOST_BUSNUM__HOST_ID__SHIFT 0x0 |
| 495 | #define PEER_REG_RANGE0__START_ADDR_MASK 0xffff |
| 496 | #define PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 |
| 497 | #define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000 |
| 498 | #define PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 |
| 499 | #define PEER_REG_RANGE1__START_ADDR_MASK 0xffff |
| 500 | #define PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 |
| 501 | #define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000 |
| 502 | #define PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 |
| 503 | #define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0xfffff |
| 504 | #define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 |
| 505 | #define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0xfffff |
| 506 | #define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 |
| 507 | #define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000 |
| 508 | #define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f |
| 509 | #define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0xfffff |
| 510 | #define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 |
| 511 | #define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0xfffff |
| 512 | #define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 |
| 513 | #define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000 |
| 514 | #define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f |
| 515 | #define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0xfffff |
| 516 | #define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 |
| 517 | #define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0xfffff |
| 518 | #define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 |
| 519 | #define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000 |
| 520 | #define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f |
| 521 | #define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0xfffff |
| 522 | #define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 |
| 523 | #define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0xfffff |
| 524 | #define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 |
| 525 | #define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000 |
| 526 | #define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f |
| 527 | #define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN_MASK 0x1 |
| 528 | #define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN__SHIFT 0x0 |
| 529 | #define BIF_MST_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0xffffffff |
| 530 | #define BIF_MST_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
| 531 | #define BIF_SLV_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0xffffffff |
| 532 | #define BIF_SLV_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x0 |
| 533 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0xff |
| 534 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 |
| 535 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0xff00 |
| 536 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 |
| 537 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0xff0000 |
| 538 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 |
| 539 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000 |
| 540 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 |
| 541 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0xff |
| 542 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 |
| 543 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0xff00 |
| 544 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 |
| 545 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0xff0000 |
| 546 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 |
| 547 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000 |
| 548 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 |
| 549 | #define BACO_CNTL__BACO_EN_MASK 0x1 |
| 550 | #define BACO_CNTL__BACO_EN__SHIFT 0x0 |
| 551 | #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2 |
| 552 | #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x1 |
| 553 | #define BACO_CNTL__BACO_ISO_DIS_MASK 0x4 |
| 554 | #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2 |
| 555 | #define BACO_CNTL__BACO_POWER_OFF_MASK 0x8 |
| 556 | #define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 |
| 557 | #define BACO_CNTL__BACO_RESET_EN_MASK 0x10 |
| 558 | #define BACO_CNTL__BACO_RESET_EN__SHIFT 0x4 |
| 559 | #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x20 |
| 560 | #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x5 |
| 561 | #define BACO_CNTL__BACO_MODE_MASK 0x40 |
| 562 | #define BACO_CNTL__BACO_MODE__SHIFT 0x6 |
| 563 | #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x80 |
| 564 | #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x7 |
| 565 | #define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x100 |
| 566 | #define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x8 |
| 567 | #define BACO_CNTL__PWRGOOD_BF_MASK 0x200 |
| 568 | #define BACO_CNTL__PWRGOOD_BF__SHIFT 0x9 |
| 569 | #define BACO_CNTL__PWRGOOD_GPIO_MASK 0x400 |
| 570 | #define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa |
| 571 | #define BACO_CNTL__PWRGOOD_MEM_MASK 0x800 |
| 572 | #define BACO_CNTL__PWRGOOD_MEM__SHIFT 0xb |
| 573 | #define BACO_CNTL__PWRGOOD_DVO_MASK 0x1000 |
| 574 | #define BACO_CNTL__PWRGOOD_DVO__SHIFT 0xc |
| 575 | #define BACO_CNTL__PWRGOOD_IDSC_MASK 0x2000 |
| 576 | #define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd |
| 577 | #define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK 0x10000 |
| 578 | #define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT 0x10 |
| 579 | #define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000 |
| 580 | #define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11 |
| 581 | #define BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK 0x40000 |
| 582 | #define BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT 0x12 |
| 583 | #define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x1 |
| 584 | #define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x0 |
| 585 | #define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2 |
| 586 | #define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1 |
| 587 | #define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x1 |
| 588 | #define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 |
| 589 | #define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x1 |
| 590 | #define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0 |
| 591 | #define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x1 |
| 592 | #define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x0 |
| 593 | #define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x1 |
| 594 | #define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 |
| 595 | #define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2 |
| 596 | #define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 |
| 597 | #define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK 0xc |
| 598 | #define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2 |
| 599 | #define BACO_CNTL_MISC__BACO_REFCLK_SEL_MASK 0x10 |
| 600 | #define BACO_CNTL_MISC__BACO_REFCLK_SEL__SHIFT 0x4 |
| 601 | #define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x1 |
| 602 | #define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 |
| 603 | #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc |
| 604 | #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 |
| 605 | #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000 |
| 606 | #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e |
| 607 | #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000 |
| 608 | #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f |
| 609 | #define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc |
| 610 | #define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 |
| 611 | #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc |
| 612 | #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 |
| 613 | #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000 |
| 614 | #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e |
| 615 | #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000 |
| 616 | #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f |
| 617 | #define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc |
| 618 | #define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 |
| 619 | #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc |
| 620 | #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 |
| 621 | #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000 |
| 622 | #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e |
| 623 | #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000 |
| 624 | #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f |
| 625 | #define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc |
| 626 | #define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 |
| 627 | #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc |
| 628 | #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 |
| 629 | #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000 |
| 630 | #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e |
| 631 | #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000 |
| 632 | #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f |
| 633 | #define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc |
| 634 | #define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 |
| 635 | #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc |
| 636 | #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 |
| 637 | #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000 |
| 638 | #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e |
| 639 | #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000 |
| 640 | #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f |
| 641 | #define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc |
| 642 | #define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 |
| 643 | #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc |
| 644 | #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 |
| 645 | #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000 |
| 646 | #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e |
| 647 | #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000 |
| 648 | #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f |
| 649 | #define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc |
| 650 | #define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 |
| 651 | #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc |
| 652 | #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 |
| 653 | #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000 |
| 654 | #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e |
| 655 | #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000 |
| 656 | #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f |
| 657 | #define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc |
| 658 | #define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 |
| 659 | #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc |
| 660 | #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 |
| 661 | #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000 |
| 662 | #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e |
| 663 | #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000 |
| 664 | #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f |
| 665 | #define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc |
| 666 | #define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 |
| 667 | #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc |
| 668 | #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 |
| 669 | #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000 |
| 670 | #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e |
| 671 | #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000 |
| 672 | #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f |
| 673 | #define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc |
| 674 | #define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 |
| 675 | #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc |
| 676 | #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 |
| 677 | #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000 |
| 678 | #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e |
| 679 | #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000 |
| 680 | #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f |
| 681 | #define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc |
| 682 | #define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 |
| 683 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x1 |
| 684 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 |
| 685 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x2 |
| 686 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 |
| 687 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4 |
| 688 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 |
| 689 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8 |
| 690 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 |
| 691 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x10 |
| 692 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 |
| 693 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x20 |
| 694 | #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 |
| 695 | #define BIF_SMU_INDEX__BIF_SMU_INDEX_MASK 0x7fffc |
| 696 | #define BIF_SMU_INDEX__BIF_SMU_INDEX__SHIFT 0x2 |
| 697 | #define BIF_SMU_DATA__BIF_SMU_DATA_MASK 0x7fffc |
| 698 | #define BIF_SMU_DATA__BIF_SMU_DATA__SHIFT 0x2 |
| 699 | #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0xffc |
| 700 | #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 |
| 701 | #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000 |
| 702 | #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f |
| 703 | #define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0xffc |
| 704 | #define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 |
| 705 | #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0xffc |
| 706 | #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 |
| 707 | #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000 |
| 708 | #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f |
| 709 | #define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0xffc |
| 710 | #define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 |
| 711 | #define IMPCTL_RESET__IMP_SW_RESET_MASK 0x1 |
| 712 | #define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x0 |
| 713 | #define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK 0x1 |
| 714 | #define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT 0x0 |
| 715 | #define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2 |
| 716 | #define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT 0x1 |
| 717 | #define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK 0x4 |
| 718 | #define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2 |
| 719 | #define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK 0x8 |
| 720 | #define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT 0x3 |
| 721 | #define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK 0x10 |
| 722 | #define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4 |
| 723 | #define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK 0x20 |
| 724 | #define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT 0x5 |
| 725 | #define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK 0x40 |
| 726 | #define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT 0x6 |
| 727 | #define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK 0x80 |
| 728 | #define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT 0x7 |
| 729 | #define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK 0x100 |
| 730 | #define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT 0x8 |
| 731 | #define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200 |
| 732 | #define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT 0x9 |
| 733 | #define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK 0x400 |
| 734 | #define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa |
| 735 | #define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800 |
| 736 | #define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT 0xb |
| 737 | #define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK 0x1000 |
| 738 | #define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT 0xc |
| 739 | #define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK 0x2000 |
| 740 | #define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd |
| 741 | #define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK 0x4000 |
| 742 | #define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe |
| 743 | #define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND_MASK 0x8000 |
| 744 | #define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND__SHIFT 0xf |
| 745 | #define GARLIC_FLUSH_CNTL__DISPLAY_MASK 0x10000 |
| 746 | #define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT 0x10 |
| 747 | #define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR_MASK 0x20000 |
| 748 | #define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR__SHIFT 0x11 |
| 749 | #define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR_MASK 0x40000 |
| 750 | #define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR__SHIFT 0x12 |
| 751 | #define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK 0x40000000 |
| 752 | #define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT 0x1e |
| 753 | #define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK 0x80000000 |
| 754 | #define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT 0x1f |
| 755 | #define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK 0x1 |
| 756 | #define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT 0x0 |
| 757 | #define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2 |
| 758 | #define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT 0x1 |
| 759 | #define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK 0xfffffffc |
| 760 | #define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2 |
| 761 | #define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK 0x1 |
| 762 | #define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT 0x0 |
| 763 | #define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2 |
| 764 | #define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT 0x1 |
| 765 | #define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK 0xfffffffc |
| 766 | #define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2 |
| 767 | #define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK 0x1 |
| 768 | #define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT 0x0 |
| 769 | #define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2 |
| 770 | #define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT 0x1 |
| 771 | #define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK 0xfffffffc |
| 772 | #define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2 |
| 773 | #define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK 0x1 |
| 774 | #define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT 0x0 |
| 775 | #define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2 |
| 776 | #define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT 0x1 |
| 777 | #define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK 0xfffffffc |
| 778 | #define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2 |
| 779 | #define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK 0x1 |
| 780 | #define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT 0x0 |
| 781 | #define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2 |
| 782 | #define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT 0x1 |
| 783 | #define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK 0xfffffffc |
| 784 | #define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2 |
| 785 | #define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK 0x1 |
| 786 | #define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT 0x0 |
| 787 | #define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2 |
| 788 | #define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT 0x1 |
| 789 | #define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK 0xfffffffc |
| 790 | #define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2 |
| 791 | #define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK 0x1 |
| 792 | #define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT 0x0 |
| 793 | #define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2 |
| 794 | #define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT 0x1 |
| 795 | #define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK 0xfffffffc |
| 796 | #define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2 |
| 797 | #define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK 0x1 |
| 798 | #define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT 0x0 |
| 799 | #define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2 |
| 800 | #define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT 0x1 |
| 801 | #define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK 0xfffffffc |
| 802 | #define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2 |
| 803 | #define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK 0xfffffffc |
| 804 | #define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2 |
| 805 | #define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK 0xfffffffc |
| 806 | #define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2 |
| 807 | #define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK 0xfffffffc |
| 808 | #define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2 |
| 809 | #define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK 0xfffffffc |
| 810 | #define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2 |
| 811 | #define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK 0xfffffffc |
| 812 | #define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2 |
| 813 | #define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK 0xfffffffc |
| 814 | #define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2 |
| 815 | #define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK 0xfffffffc |
| 816 | #define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2 |
| 817 | #define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK 0xfffffffc |
| 818 | #define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2 |
| 819 | #define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK 0x1 |
| 820 | #define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT 0x0 |
| 821 | #define GPU_GARLIC_FLUSH_REQ__CP0_MASK 0x1 |
| 822 | #define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT 0x0 |
| 823 | #define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2 |
| 824 | #define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT 0x1 |
| 825 | #define GPU_GARLIC_FLUSH_REQ__CP2_MASK 0x4 |
| 826 | #define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2 |
| 827 | #define GPU_GARLIC_FLUSH_REQ__CP3_MASK 0x8 |
| 828 | #define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT 0x3 |
| 829 | #define GPU_GARLIC_FLUSH_REQ__CP4_MASK 0x10 |
| 830 | #define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT 0x4 |
| 831 | #define GPU_GARLIC_FLUSH_REQ__CP5_MASK 0x20 |
| 832 | #define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT 0x5 |
| 833 | #define GPU_GARLIC_FLUSH_REQ__CP6_MASK 0x40 |
| 834 | #define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT 0x6 |
| 835 | #define GPU_GARLIC_FLUSH_REQ__CP7_MASK 0x80 |
| 836 | #define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT 0x7 |
| 837 | #define GPU_GARLIC_FLUSH_REQ__CP8_MASK 0x100 |
| 838 | #define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT 0x8 |
| 839 | #define GPU_GARLIC_FLUSH_REQ__CP9_MASK 0x200 |
| 840 | #define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT 0x9 |
| 841 | #define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK 0x400 |
| 842 | #define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa |
| 843 | #define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800 |
| 844 | #define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT 0xb |
| 845 | #define GPU_GARLIC_FLUSH_REQ__SDMA2_MASK 0x1000 |
| 846 | #define GPU_GARLIC_FLUSH_REQ__SDMA2__SHIFT 0xc |
| 847 | #define GPU_GARLIC_FLUSH_REQ__SDMA3_MASK 0x2000 |
| 848 | #define GPU_GARLIC_FLUSH_REQ__SDMA3__SHIFT 0xd |
| 849 | #define GPU_GARLIC_FLUSH_DONE__CP0_MASK 0x1 |
| 850 | #define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT 0x0 |
| 851 | #define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2 |
| 852 | #define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT 0x1 |
| 853 | #define GPU_GARLIC_FLUSH_DONE__CP2_MASK 0x4 |
| 854 | #define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2 |
| 855 | #define GPU_GARLIC_FLUSH_DONE__CP3_MASK 0x8 |
| 856 | #define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT 0x3 |
| 857 | #define GPU_GARLIC_FLUSH_DONE__CP4_MASK 0x10 |
| 858 | #define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT 0x4 |
| 859 | #define GPU_GARLIC_FLUSH_DONE__CP5_MASK 0x20 |
| 860 | #define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT 0x5 |
| 861 | #define GPU_GARLIC_FLUSH_DONE__CP6_MASK 0x40 |
| 862 | #define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT 0x6 |
| 863 | #define GPU_GARLIC_FLUSH_DONE__CP7_MASK 0x80 |
| 864 | #define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT 0x7 |
| 865 | #define GPU_GARLIC_FLUSH_DONE__CP8_MASK 0x100 |
| 866 | #define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT 0x8 |
| 867 | #define GPU_GARLIC_FLUSH_DONE__CP9_MASK 0x200 |
| 868 | #define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT 0x9 |
| 869 | #define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK 0x400 |
| 870 | #define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT 0xa |
| 871 | #define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800 |
| 872 | #define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT 0xb |
| 873 | #define GPU_GARLIC_FLUSH_DONE__SDMA2_MASK 0x1000 |
| 874 | #define GPU_GARLIC_FLUSH_DONE__SDMA2__SHIFT 0xc |
| 875 | #define GPU_GARLIC_FLUSH_DONE__SDMA3_MASK 0x2000 |
| 876 | #define GPU_GARLIC_FLUSH_DONE__SDMA3__SHIFT 0xd |
| 877 | #define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x7fffc |
| 878 | #define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
| 879 | #define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x7fffc |
| 880 | #define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
| 881 | #define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffff |
| 882 | #define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 |
| 883 | #define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffff |
| 884 | #define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 |
| 885 | #define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffff |
| 886 | #define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 |
| 887 | #define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffff |
| 888 | #define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 |
| 889 | #define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffff |
| 890 | #define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 |
| 891 | #define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffff |
| 892 | #define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 |
| 893 | #define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffff |
| 894 | #define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 |
| 895 | #define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffff |
| 896 | #define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 |
| 897 | #define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffff |
| 898 | #define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 |
| 899 | #define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffff |
| 900 | #define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 |
| 901 | #define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffff |
| 902 | #define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 |
| 903 | #define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffff |
| 904 | #define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 |
| 905 | #define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffff |
| 906 | #define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 |
| 907 | #define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffff |
| 908 | #define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 |
| 909 | #define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffff |
| 910 | #define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 |
| 911 | #define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffff |
| 912 | #define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 |
| 913 | #define BIF_RB_CNTL__RB_ENABLE_MASK 0x1 |
| 914 | #define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
| 915 | #define BIF_RB_CNTL__RB_SIZE_MASK 0x3e |
| 916 | #define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 |
| 917 | #define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100 |
| 918 | #define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 |
| 919 | #define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00 |
| 920 | #define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 |
| 921 | #define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x20000 |
| 922 | #define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 |
| 923 | #define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 |
| 924 | #define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f |
| 925 | #define BIF_RB_BASE__ADDR_MASK 0xffffffff |
| 926 | #define BIF_RB_BASE__ADDR__SHIFT 0x0 |
| 927 | #define BIF_RB_RPTR__OFFSET_MASK 0x3fffc |
| 928 | #define BIF_RB_RPTR__OFFSET__SHIFT 0x2 |
| 929 | #define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x1 |
| 930 | #define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 |
| 931 | #define BIF_RB_WPTR__OFFSET_MASK 0x3fffc |
| 932 | #define BIF_RB_WPTR__OFFSET__SHIFT 0x2 |
| 933 | #define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0xff |
| 934 | #define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 |
| 935 | #define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc |
| 936 | #define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 |
| 937 | #define MAILBOX_INDEX__MAILBOX_INDEX_MASK 0xf |
| 938 | #define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 |
| 939 | #define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xffffffff |
| 940 | #define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
| 941 | #define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xffffffff |
| 942 | #define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
| 943 | #define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xffffffff |
| 944 | #define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
| 945 | #define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xffffffff |
| 946 | #define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
| 947 | #define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xffffffff |
| 948 | #define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
| 949 | #define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xffffffff |
| 950 | #define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
| 951 | #define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xffffffff |
| 952 | #define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
| 953 | #define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xffffffff |
| 954 | #define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
| 955 | #define MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x1 |
| 956 | #define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
| 957 | #define MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x2 |
| 958 | #define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
| 959 | #define MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x100 |
| 960 | #define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
| 961 | #define MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x200 |
| 962 | #define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
| 963 | #define MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x1 |
| 964 | #define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
| 965 | #define MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x2 |
| 966 | #define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
| 967 | #define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF_MASK 0xffff |
| 968 | #define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF__SHIFT 0x0 |
| 969 | #define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF_MASK 0x80000000 |
| 970 | #define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF__SHIFT 0x1f |
| 971 | #define VM_INIT_STATUS__VM_INIT_STATUS_MASK 0x1 |
| 972 | #define VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0 |
| 973 | #define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK 0xffffffff |
| 974 | #define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0 |
| 975 | #define BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS_MASK 0xffffffff |
| 976 | #define BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0 |
| 977 | #define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE_MASK 0xffff |
| 978 | #define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE__SHIFT 0x0 |
| 979 | #define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED_MASK 0xffff0000 |
| 980 | #define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED__SHIFT 0x10 |
| 981 | #define BIF_GPUIOV_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY_MASK 0xffffffff |
| 982 | #define BIF_GPUIOV_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY__SHIFT 0x0 |
| 983 | #define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER_MASK 0xffff |
| 984 | #define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER__SHIFT 0x0 |
| 985 | #define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER_MASK 0xffff0000 |
| 986 | #define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER__SHIFT 0x10 |
| 987 | #define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER_MASK 0xffff |
| 988 | #define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER__SHIFT 0x0 |
| 989 | #define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER_MASK 0xffff0000 |
| 990 | #define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER__SHIFT 0x10 |
| 991 | #define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER_MASK 0xffff |
| 992 | #define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER__SHIFT 0x0 |
| 993 | #define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER_MASK 0xffff0000 |
| 994 | #define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER__SHIFT 0x10 |
| 995 | #define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER_MASK 0xffff |
| 996 | #define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER__SHIFT 0x0 |
| 997 | #define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER_MASK 0xffff0000 |
| 998 | #define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER__SHIFT 0x10 |
| 999 | #define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER_MASK 0xffff |
| 1000 | #define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER__SHIFT 0x0 |
| 1001 | #define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER_MASK 0xffff0000 |
| 1002 | #define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER__SHIFT 0x10 |
| 1003 | #define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER_MASK 0xffff |
| 1004 | #define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER__SHIFT 0x0 |
| 1005 | #define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER_MASK 0xffff0000 |
| 1006 | #define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER__SHIFT 0x10 |
| 1007 | #define BIF_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY_MASK 0xffffffff |
| 1008 | #define BIF_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY__SHIFT 0x0 |
| 1009 | #define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER_MASK 0xffff |
| 1010 | #define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER__SHIFT 0x0 |
| 1011 | #define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER_MASK 0xffff0000 |
| 1012 | #define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER__SHIFT 0x10 |
| 1013 | #define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER_MASK 0xffff |
| 1014 | #define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER__SHIFT 0x0 |
| 1015 | #define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER_MASK 0xffff0000 |
| 1016 | #define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER__SHIFT 0x10 |
| 1017 | #define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER_MASK 0xffff |
| 1018 | #define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER__SHIFT 0x0 |
| 1019 | #define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER_MASK 0xffff0000 |
| 1020 | #define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER__SHIFT 0x10 |
| 1021 | #define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER_MASK 0xffff |
| 1022 | #define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER__SHIFT 0x0 |
| 1023 | #define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER_MASK 0xffff0000 |
| 1024 | #define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER__SHIFT 0x10 |
| 1025 | #define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER_MASK 0xffff |
| 1026 | #define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER__SHIFT 0x0 |
| 1027 | #define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER_MASK 0xffff0000 |
| 1028 | #define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER__SHIFT 0x10 |
| 1029 | #define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER_MASK 0xffff |
| 1030 | #define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER__SHIFT 0x0 |
| 1031 | #define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER_MASK 0xffff0000 |
| 1032 | #define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER__SHIFT 0x10 |
| 1033 | #define VENDOR_ID__VENDOR_ID_MASK 0xffff |
| 1034 | #define VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
| 1035 | #define DEVICE_ID__DEVICE_ID_MASK 0xffff |
| 1036 | #define DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
| 1037 | #define COMMAND__IO_ACCESS_EN_MASK 0x1 |
| 1038 | #define COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
| 1039 | #define COMMAND__MEM_ACCESS_EN_MASK 0x2 |
| 1040 | #define COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
| 1041 | #define COMMAND__BUS_MASTER_EN_MASK 0x4 |
| 1042 | #define COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
| 1043 | #define COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 |
| 1044 | #define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
| 1045 | #define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 |
| 1046 | #define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
| 1047 | #define COMMAND__PAL_SNOOP_EN_MASK 0x20 |
| 1048 | #define COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
| 1049 | #define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 |
| 1050 | #define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
| 1051 | #define COMMAND__AD_STEPPING_MASK 0x80 |
| 1052 | #define COMMAND__AD_STEPPING__SHIFT 0x7 |
| 1053 | #define COMMAND__SERR_EN_MASK 0x100 |
| 1054 | #define COMMAND__SERR_EN__SHIFT 0x8 |
| 1055 | #define COMMAND__FAST_B2B_EN_MASK 0x200 |
| 1056 | #define COMMAND__FAST_B2B_EN__SHIFT 0x9 |
| 1057 | #define COMMAND__INT_DIS_MASK 0x400 |
| 1058 | #define COMMAND__INT_DIS__SHIFT 0xa |
| 1059 | #define STATUS__INT_STATUS_MASK 0x8 |
| 1060 | #define STATUS__INT_STATUS__SHIFT 0x3 |
| 1061 | #define STATUS__CAP_LIST_MASK 0x10 |
| 1062 | #define STATUS__CAP_LIST__SHIFT 0x4 |
| 1063 | #define STATUS__PCI_66_EN_MASK 0x20 |
| 1064 | #define STATUS__PCI_66_EN__SHIFT 0x5 |
| 1065 | #define STATUS__FAST_BACK_CAPABLE_MASK 0x80 |
| 1066 | #define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
| 1067 | #define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x100 |
| 1068 | #define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
| 1069 | #define STATUS__DEVSEL_TIMING_MASK 0x600 |
| 1070 | #define STATUS__DEVSEL_TIMING__SHIFT 0x9 |
| 1071 | #define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800 |
| 1072 | #define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
| 1073 | #define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000 |
| 1074 | #define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
| 1075 | #define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000 |
| 1076 | #define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
| 1077 | #define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000 |
| 1078 | #define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
| 1079 | #define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000 |
| 1080 | #define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
| 1081 | #define REVISION_ID__MINOR_REV_ID_MASK 0xf |
| 1082 | #define REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
| 1083 | #define REVISION_ID__MAJOR_REV_ID_MASK 0xf0 |
| 1084 | #define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
| 1085 | #define PROG_INTERFACE__PROG_INTERFACE_MASK 0xff |
| 1086 | #define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
| 1087 | #define SUB_CLASS__SUB_CLASS_MASK 0xff |
| 1088 | #define SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
| 1089 | #define BASE_CLASS__BASE_CLASS_MASK 0xff |
| 1090 | #define BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
| 1091 | #define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff |
| 1092 | #define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
| 1093 | #define LATENCY__LATENCY_TIMER_MASK 0xff |
| 1094 | #define LATENCY__LATENCY_TIMER__SHIFT 0x0 |
| 1095 | #define HEADER__HEADER_TYPE_MASK 0x7f |
| 1096 | #define HEADER__HEADER_TYPE__SHIFT 0x0 |
| 1097 | #define HEADER__DEVICE_TYPE_MASK 0x80 |
| 1098 | #define HEADER__DEVICE_TYPE__SHIFT 0x7 |
| 1099 | #define BIST__BIST_COMP_MASK 0xf |
| 1100 | #define BIST__BIST_COMP__SHIFT 0x0 |
| 1101 | #define BIST__BIST_STRT_MASK 0x40 |
| 1102 | #define BIST__BIST_STRT__SHIFT 0x6 |
| 1103 | #define BIST__BIST_CAP_MASK 0x80 |
| 1104 | #define BIST__BIST_CAP__SHIFT 0x7 |
| 1105 | #define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffff |
| 1106 | #define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
| 1107 | #define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffff |
| 1108 | #define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
| 1109 | #define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffff |
| 1110 | #define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
| 1111 | #define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffff |
| 1112 | #define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
| 1113 | #define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffff |
| 1114 | #define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
| 1115 | #define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffff |
| 1116 | #define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
| 1117 | #define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffff |
| 1118 | #define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
| 1119 | #define CAP_PTR__CAP_PTR_MASK 0xff |
| 1120 | #define CAP_PTR__CAP_PTR__SHIFT 0x0 |
| 1121 | #define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff |
| 1122 | #define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
| 1123 | #define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff |
| 1124 | #define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
| 1125 | #define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0xffff |
| 1126 | #define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
| 1127 | #define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000 |
| 1128 | #define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
| 1129 | #define MIN_GRANT__MIN_GNT_MASK 0xff |
| 1130 | #define MIN_GRANT__MIN_GNT__SHIFT 0x0 |
| 1131 | #define MAX_LATENCY__MAX_LAT_MASK 0xff |
| 1132 | #define MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
| 1133 | #define VENDOR_CAP_LIST__CAP_ID_MASK 0xff |
| 1134 | #define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 1135 | #define VENDOR_CAP_LIST__NEXT_PTR_MASK 0xff00 |
| 1136 | #define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
| 1137 | #define VENDOR_CAP_LIST__LENGTH_MASK 0xff0000 |
| 1138 | #define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
| 1139 | #define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0xffff |
| 1140 | #define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
| 1141 | #define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000 |
| 1142 | #define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
| 1143 | #define PMI_CAP_LIST__CAP_ID_MASK 0xff |
| 1144 | #define PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 1145 | #define PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 |
| 1146 | #define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
| 1147 | #define PMI_CAP__VERSION_MASK 0x7 |
| 1148 | #define PMI_CAP__VERSION__SHIFT 0x0 |
| 1149 | #define PMI_CAP__PME_CLOCK_MASK 0x8 |
| 1150 | #define PMI_CAP__PME_CLOCK__SHIFT 0x3 |
| 1151 | #define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x20 |
| 1152 | #define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
| 1153 | #define PMI_CAP__AUX_CURRENT_MASK 0x1c0 |
| 1154 | #define PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
| 1155 | #define PMI_CAP__D1_SUPPORT_MASK 0x200 |
| 1156 | #define PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
| 1157 | #define PMI_CAP__D2_SUPPORT_MASK 0x400 |
| 1158 | #define PMI_CAP__D2_SUPPORT__SHIFT 0xa |
| 1159 | #define PMI_CAP__PME_SUPPORT_MASK 0xf800 |
| 1160 | #define PMI_CAP__PME_SUPPORT__SHIFT 0xb |
| 1161 | #define PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 |
| 1162 | #define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
| 1163 | #define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 |
| 1164 | #define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
| 1165 | #define PMI_STATUS_CNTL__PME_EN_MASK 0x100 |
| 1166 | #define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
| 1167 | #define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 |
| 1168 | #define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
| 1169 | #define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 |
| 1170 | #define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
| 1171 | #define PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 |
| 1172 | #define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
| 1173 | #define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 |
| 1174 | #define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
| 1175 | #define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 |
| 1176 | #define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
| 1177 | #define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 |
| 1178 | #define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
| 1179 | #define PCIE_CAP_LIST__CAP_ID_MASK 0xff |
| 1180 | #define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 1181 | #define PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 |
| 1182 | #define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
| 1183 | #define PCIE_CAP__VERSION_MASK 0xf |
| 1184 | #define PCIE_CAP__VERSION__SHIFT 0x0 |
| 1185 | #define PCIE_CAP__DEVICE_TYPE_MASK 0xf0 |
| 1186 | #define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
| 1187 | #define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x100 |
| 1188 | #define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
| 1189 | #define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e00 |
| 1190 | #define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
| 1191 | #define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 |
| 1192 | #define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
| 1193 | #define DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 |
| 1194 | #define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
| 1195 | #define DEVICE_CAP__EXTENDED_TAG_MASK 0x20 |
| 1196 | #define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
| 1197 | #define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 |
| 1198 | #define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
| 1199 | #define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 |
| 1200 | #define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
| 1201 | #define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 |
| 1202 | #define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
| 1203 | #define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 |
| 1204 | #define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
| 1205 | #define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 |
| 1206 | #define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
| 1207 | #define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 |
| 1208 | #define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
| 1209 | #define DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 |
| 1210 | #define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
| 1211 | #define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 |
| 1212 | #define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
| 1213 | #define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 |
| 1214 | #define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
| 1215 | #define DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 |
| 1216 | #define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
| 1217 | #define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 |
| 1218 | #define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
| 1219 | #define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 |
| 1220 | #define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
| 1221 | #define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 |
| 1222 | #define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
| 1223 | #define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 |
| 1224 | #define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
| 1225 | #define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 |
| 1226 | #define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
| 1227 | #define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 |
| 1228 | #define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
| 1229 | #define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 |
| 1230 | #define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
| 1231 | #define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000 |
| 1232 | #define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
| 1233 | #define DEVICE_STATUS__CORR_ERR_MASK 0x1 |
| 1234 | #define DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
| 1235 | #define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2 |
| 1236 | #define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
| 1237 | #define DEVICE_STATUS__FATAL_ERR_MASK 0x4 |
| 1238 | #define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
| 1239 | #define DEVICE_STATUS__USR_DETECTED_MASK 0x8 |
| 1240 | #define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
| 1241 | #define DEVICE_STATUS__AUX_PWR_MASK 0x10 |
| 1242 | #define DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
| 1243 | #define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x20 |
| 1244 | #define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
| 1245 | #define LINK_CAP__LINK_SPEED_MASK 0xf |
| 1246 | #define LINK_CAP__LINK_SPEED__SHIFT 0x0 |
| 1247 | #define LINK_CAP__LINK_WIDTH_MASK 0x3f0 |
| 1248 | #define LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
| 1249 | #define LINK_CAP__PM_SUPPORT_MASK 0xc00 |
| 1250 | #define LINK_CAP__PM_SUPPORT__SHIFT 0xa |
| 1251 | #define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 |
| 1252 | #define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
| 1253 | #define LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 |
| 1254 | #define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
| 1255 | #define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 |
| 1256 | #define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
| 1257 | #define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 |
| 1258 | #define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
| 1259 | #define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 |
| 1260 | #define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
| 1261 | #define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 |
| 1262 | #define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
| 1263 | #define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 |
| 1264 | #define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
| 1265 | #define LINK_CAP__PORT_NUMBER_MASK 0xff000000 |
| 1266 | #define LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
| 1267 | #define LINK_CNTL__PM_CONTROL_MASK 0x3 |
| 1268 | #define LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
| 1269 | #define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 |
| 1270 | #define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
| 1271 | #define LINK_CNTL__LINK_DIS_MASK 0x10 |
| 1272 | #define LINK_CNTL__LINK_DIS__SHIFT 0x4 |
| 1273 | #define LINK_CNTL__RETRAIN_LINK_MASK 0x20 |
| 1274 | #define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
| 1275 | #define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 |
| 1276 | #define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
| 1277 | #define LINK_CNTL__EXTENDED_SYNC_MASK 0x80 |
| 1278 | #define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
| 1279 | #define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 |
| 1280 | #define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
| 1281 | #define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 |
| 1282 | #define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
| 1283 | #define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 |
| 1284 | #define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
| 1285 | #define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 |
| 1286 | #define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
| 1287 | #define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf |
| 1288 | #define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
| 1289 | #define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f0 |
| 1290 | #define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
| 1291 | #define LINK_STATUS__LINK_TRAINING_MASK 0x800 |
| 1292 | #define LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
| 1293 | #define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000 |
| 1294 | #define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
| 1295 | #define LINK_STATUS__DL_ACTIVE_MASK 0x2000 |
| 1296 | #define LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
| 1297 | #define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000 |
| 1298 | #define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
| 1299 | #define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000 |
| 1300 | #define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
| 1301 | #define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf |
| 1302 | #define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
| 1303 | #define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 |
| 1304 | #define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
| 1305 | #define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 |
| 1306 | #define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
| 1307 | #define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 |
| 1308 | #define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
| 1309 | #define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 |
| 1310 | #define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
| 1311 | #define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 |
| 1312 | #define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
| 1313 | #define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 |
| 1314 | #define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
| 1315 | #define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 |
| 1316 | #define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
| 1317 | #define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 |
| 1318 | #define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
| 1319 | #define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 |
| 1320 | #define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
| 1321 | #define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 |
| 1322 | #define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
| 1323 | #define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 |
| 1324 | #define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
| 1325 | #define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 |
| 1326 | #define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
| 1327 | #define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 |
| 1328 | #define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
| 1329 | #define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf |
| 1330 | #define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
| 1331 | #define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 |
| 1332 | #define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
| 1333 | #define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 |
| 1334 | #define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
| 1335 | #define DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 |
| 1336 | #define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
| 1337 | #define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 |
| 1338 | #define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
| 1339 | #define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 |
| 1340 | #define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
| 1341 | #define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 |
| 1342 | #define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
| 1343 | #define DEVICE_CNTL2__LTR_EN_MASK 0x400 |
| 1344 | #define DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
| 1345 | #define DEVICE_CNTL2__OBFF_EN_MASK 0x6000 |
| 1346 | #define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
| 1347 | #define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 |
| 1348 | #define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
| 1349 | #define DEVICE_STATUS2__RESERVED_MASK 0xffff |
| 1350 | #define DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
| 1351 | #define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe |
| 1352 | #define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
| 1353 | #define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 |
| 1354 | #define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
| 1355 | #define LINK_CAP2__RESERVED_MASK 0xfffffe00 |
| 1356 | #define LINK_CAP2__RESERVED__SHIFT 0x9 |
| 1357 | #define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf |
| 1358 | #define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
| 1359 | #define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 |
| 1360 | #define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
| 1361 | #define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 |
| 1362 | #define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
| 1363 | #define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 |
| 1364 | #define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
| 1365 | #define LINK_CNTL2__XMIT_MARGIN_MASK 0x380 |
| 1366 | #define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
| 1367 | #define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 |
| 1368 | #define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
| 1369 | #define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 |
| 1370 | #define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
| 1371 | #define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 |
| 1372 | #define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
| 1373 | #define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x1 |
| 1374 | #define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
| 1375 | #define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2 |
| 1376 | #define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
| 1377 | #define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x4 |
| 1378 | #define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
| 1379 | #define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x8 |
| 1380 | #define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
| 1381 | #define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x10 |
| 1382 | #define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
| 1383 | #define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x20 |
| 1384 | #define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
| 1385 | #define MSI_CAP_LIST__CAP_ID_MASK 0xff |
| 1386 | #define MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 1387 | #define MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 |
| 1388 | #define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
| 1389 | #define MSI_MSG_CNTL__MSI_EN_MASK 0x1 |
| 1390 | #define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
| 1391 | #define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe |
| 1392 | #define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
| 1393 | #define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x70 |
| 1394 | #define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
| 1395 | #define MSI_MSG_CNTL__MSI_64BIT_MASK 0x80 |
| 1396 | #define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
| 1397 | #define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x100 |
| 1398 | #define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
| 1399 | #define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc |
| 1400 | #define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
| 1401 | #define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff |
| 1402 | #define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
| 1403 | #define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff |
| 1404 | #define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
| 1405 | #define MSI_MSG_DATA__MSI_DATA_MASK 0xffff |
| 1406 | #define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
| 1407 | #define MSI_MASK__MSI_MASK_MASK 0xffffffff |
| 1408 | #define MSI_MASK__MSI_MASK__SHIFT 0x0 |
| 1409 | #define MSI_PENDING__MSI_PENDING_MASK 0xffffffff |
| 1410 | #define MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
| 1411 | #define MSI_MASK_64__MSI_MASK_64_MASK 0xffffffff |
| 1412 | #define MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
| 1413 | #define MSI_PENDING_64__MSI_PENDING_64_MASK 0xffffffff |
| 1414 | #define MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
| 1415 | #define MSIX_CAP_LIST__CAP_ID_MASK 0xff |
| 1416 | #define MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 1417 | #define MSIX_CAP_LIST__NEXT_PTR_MASK 0xff00 |
| 1418 | #define MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
| 1419 | #define MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x7ff |
| 1420 | #define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
| 1421 | #define MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000 |
| 1422 | #define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
| 1423 | #define MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000 |
| 1424 | #define MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
| 1425 | #define MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x7 |
| 1426 | #define MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
| 1427 | #define MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xfffffff8 |
| 1428 | #define MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
| 1429 | #define MSIX_PBA__MSIX_PBA_BIR_MASK 0x7 |
| 1430 | #define MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
| 1431 | #define MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xfffffff8 |
| 1432 | #define MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
| 1433 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 1434 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 1435 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 1436 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 1437 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 1438 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 1439 | #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff |
| 1440 | #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
| 1441 | #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 |
| 1442 | #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
| 1443 | #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 |
| 1444 | #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
| 1445 | #define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff |
| 1446 | #define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
| 1447 | #define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff |
| 1448 | #define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
| 1449 | #define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 1450 | #define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 1451 | #define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 1452 | #define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 1453 | #define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 1454 | #define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 1455 | #define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 |
| 1456 | #define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
| 1457 | #define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 |
| 1458 | #define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
| 1459 | #define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 |
| 1460 | #define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
| 1461 | #define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 |
| 1462 | #define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
| 1463 | #define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff |
| 1464 | #define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
| 1465 | #define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 |
| 1466 | #define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
| 1467 | #define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 |
| 1468 | #define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
| 1469 | #define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe |
| 1470 | #define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
| 1471 | #define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x1 |
| 1472 | #define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
| 1473 | #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff |
| 1474 | #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
| 1475 | #define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 |
| 1476 | #define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
| 1477 | #define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 |
| 1478 | #define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
| 1479 | #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 |
| 1480 | #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
| 1481 | #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 |
| 1482 | #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
| 1483 | #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe |
| 1484 | #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
| 1485 | #define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 |
| 1486 | #define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
| 1487 | #define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 |
| 1488 | #define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
| 1489 | #define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 |
| 1490 | #define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
| 1491 | #define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 |
| 1492 | #define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
| 1493 | #define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1 |
| 1494 | #define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
| 1495 | #define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2 |
| 1496 | #define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
| 1497 | #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff |
| 1498 | #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
| 1499 | #define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 |
| 1500 | #define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
| 1501 | #define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 |
| 1502 | #define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
| 1503 | #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 |
| 1504 | #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
| 1505 | #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 |
| 1506 | #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
| 1507 | #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe |
| 1508 | #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
| 1509 | #define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 |
| 1510 | #define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
| 1511 | #define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 |
| 1512 | #define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
| 1513 | #define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 |
| 1514 | #define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
| 1515 | #define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 |
| 1516 | #define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
| 1517 | #define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1 |
| 1518 | #define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
| 1519 | #define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2 |
| 1520 | #define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
| 1521 | #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 1522 | #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 1523 | #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 1524 | #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 1525 | #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 1526 | #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 1527 | #define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff |
| 1528 | #define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
| 1529 | #define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff |
| 1530 | #define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
| 1531 | #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 1532 | #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 1533 | #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 1534 | #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 1535 | #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 1536 | #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 1537 | #define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 |
| 1538 | #define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
| 1539 | #define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 |
| 1540 | #define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
| 1541 | #define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 |
| 1542 | #define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
| 1543 | #define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 |
| 1544 | #define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
| 1545 | #define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 |
| 1546 | #define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
| 1547 | #define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 |
| 1548 | #define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
| 1549 | #define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 |
| 1550 | #define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
| 1551 | #define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 |
| 1552 | #define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
| 1553 | #define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 |
| 1554 | #define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
| 1555 | #define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 |
| 1556 | #define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
| 1557 | #define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 |
| 1558 | #define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
| 1559 | #define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 |
| 1560 | #define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
| 1561 | #define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 |
| 1562 | #define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
| 1563 | #define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 |
| 1564 | #define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
| 1565 | #define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 |
| 1566 | #define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
| 1567 | #define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 |
| 1568 | #define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
| 1569 | #define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 |
| 1570 | #define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
| 1571 | #define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 |
| 1572 | #define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
| 1573 | #define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 |
| 1574 | #define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
| 1575 | #define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 |
| 1576 | #define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
| 1577 | #define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 |
| 1578 | #define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
| 1579 | #define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 |
| 1580 | #define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
| 1581 | #define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 |
| 1582 | #define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
| 1583 | #define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 |
| 1584 | #define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
| 1585 | #define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 |
| 1586 | #define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
| 1587 | #define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 |
| 1588 | #define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
| 1589 | #define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 |
| 1590 | #define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
| 1591 | #define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 |
| 1592 | #define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
| 1593 | #define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 |
| 1594 | #define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
| 1595 | #define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 |
| 1596 | #define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
| 1597 | #define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 |
| 1598 | #define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
| 1599 | #define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 |
| 1600 | #define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
| 1601 | #define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 |
| 1602 | #define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
| 1603 | #define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 |
| 1604 | #define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
| 1605 | #define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 |
| 1606 | #define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
| 1607 | #define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 |
| 1608 | #define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
| 1609 | #define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 |
| 1610 | #define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
| 1611 | #define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 |
| 1612 | #define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
| 1613 | #define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 |
| 1614 | #define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
| 1615 | #define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 |
| 1616 | #define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
| 1617 | #define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 |
| 1618 | #define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
| 1619 | #define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 |
| 1620 | #define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
| 1621 | #define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 |
| 1622 | #define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
| 1623 | #define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 |
| 1624 | #define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
| 1625 | #define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 |
| 1626 | #define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
| 1627 | #define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 |
| 1628 | #define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
| 1629 | #define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 |
| 1630 | #define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
| 1631 | #define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 |
| 1632 | #define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
| 1633 | #define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 |
| 1634 | #define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
| 1635 | #define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 |
| 1636 | #define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
| 1637 | #define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 |
| 1638 | #define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
| 1639 | #define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 |
| 1640 | #define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
| 1641 | #define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 |
| 1642 | #define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
| 1643 | #define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 |
| 1644 | #define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
| 1645 | #define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 |
| 1646 | #define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
| 1647 | #define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 |
| 1648 | #define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
| 1649 | #define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 |
| 1650 | #define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
| 1651 | #define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 |
| 1652 | #define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
| 1653 | #define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 |
| 1654 | #define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
| 1655 | #define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 |
| 1656 | #define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
| 1657 | #define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 |
| 1658 | #define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
| 1659 | #define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 |
| 1660 | #define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
| 1661 | #define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 |
| 1662 | #define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
| 1663 | #define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 |
| 1664 | #define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
| 1665 | #define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f |
| 1666 | #define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
| 1667 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 |
| 1668 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
| 1669 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 |
| 1670 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
| 1671 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 |
| 1672 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
| 1673 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 |
| 1674 | #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
| 1675 | #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 |
| 1676 | #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
| 1677 | #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 |
| 1678 | #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
| 1679 | #define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 |
| 1680 | #define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
| 1681 | #define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff |
| 1682 | #define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
| 1683 | #define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff |
| 1684 | #define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
| 1685 | #define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff |
| 1686 | #define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
| 1687 | #define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff |
| 1688 | #define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
| 1689 | #define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff |
| 1690 | #define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
| 1691 | #define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff |
| 1692 | #define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
| 1693 | #define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff |
| 1694 | #define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
| 1695 | #define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff |
| 1696 | #define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
| 1697 | #define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 1698 | #define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 1699 | #define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 1700 | #define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 1701 | #define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 1702 | #define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 1703 | #define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 |
| 1704 | #define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
| 1705 | #define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x7 |
| 1706 | #define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
| 1707 | #define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0xe0 |
| 1708 | #define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
| 1709 | #define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1f00 |
| 1710 | #define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
| 1711 | #define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 |
| 1712 | #define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
| 1713 | #define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x7 |
| 1714 | #define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
| 1715 | #define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0xe0 |
| 1716 | #define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
| 1717 | #define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1f00 |
| 1718 | #define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
| 1719 | #define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 |
| 1720 | #define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
| 1721 | #define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x7 |
| 1722 | #define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
| 1723 | #define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0xe0 |
| 1724 | #define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
| 1725 | #define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1f00 |
| 1726 | #define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
| 1727 | #define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 |
| 1728 | #define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
| 1729 | #define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x7 |
| 1730 | #define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
| 1731 | #define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0xe0 |
| 1732 | #define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
| 1733 | #define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1f00 |
| 1734 | #define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
| 1735 | #define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 |
| 1736 | #define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
| 1737 | #define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x7 |
| 1738 | #define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
| 1739 | #define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0xe0 |
| 1740 | #define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
| 1741 | #define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1f00 |
| 1742 | #define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
| 1743 | #define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 |
| 1744 | #define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
| 1745 | #define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x7 |
| 1746 | #define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
| 1747 | #define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0xe0 |
| 1748 | #define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
| 1749 | #define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1f00 |
| 1750 | #define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
| 1751 | #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 1752 | #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 1753 | #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 1754 | #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 1755 | #define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 1756 | #define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 1757 | #define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xff |
| 1758 | #define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
| 1759 | #define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0xff |
| 1760 | #define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
| 1761 | #define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x300 |
| 1762 | #define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
| 1763 | #define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x1c00 |
| 1764 | #define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
| 1765 | #define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x6000 |
| 1766 | #define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
| 1767 | #define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x38000 |
| 1768 | #define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
| 1769 | #define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x1c0000 |
| 1770 | #define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
| 1771 | #define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x1 |
| 1772 | #define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
| 1773 | #define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 1774 | #define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 1775 | #define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 1776 | #define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 1777 | #define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 1778 | #define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 1779 | #define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x1f |
| 1780 | #define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
| 1781 | #define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300 |
| 1782 | #define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
| 1783 | #define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000 |
| 1784 | #define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
| 1785 | #define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000 |
| 1786 | #define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
| 1787 | #define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000 |
| 1788 | #define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
| 1789 | #define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff |
| 1790 | #define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
| 1791 | #define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x1f |
| 1792 | #define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
| 1793 | #define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x100 |
| 1794 | #define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
| 1795 | #define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1f |
| 1796 | #define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
| 1797 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 1798 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 1799 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 1800 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 1801 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 1802 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 1803 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 1804 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 1805 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 1806 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 1807 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 1808 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 1809 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 1810 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 1811 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 1812 | #define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 1813 | #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 1814 | #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 1815 | #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 1816 | #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 1817 | #define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 1818 | #define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 1819 | #define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 |
| 1820 | #define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
| 1821 | #define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 |
| 1822 | #define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
| 1823 | #define PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc |
| 1824 | #define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
| 1825 | #define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff |
| 1826 | #define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
| 1827 | #define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 |
| 1828 | #define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
| 1829 | #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1830 | #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1831 | #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1832 | #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1833 | #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1834 | #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1835 | #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1836 | #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1837 | #define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1838 | #define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1839 | #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1840 | #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1841 | #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1842 | #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1843 | #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1844 | #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1845 | #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1846 | #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1847 | #define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1848 | #define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1849 | #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1850 | #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1851 | #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1852 | #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1853 | #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1854 | #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1855 | #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1856 | #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1857 | #define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1858 | #define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1859 | #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1860 | #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1861 | #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1862 | #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1863 | #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1864 | #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1865 | #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1866 | #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1867 | #define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1868 | #define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1869 | #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1870 | #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1871 | #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1872 | #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1873 | #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1874 | #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1875 | #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1876 | #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1877 | #define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1878 | #define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1879 | #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1880 | #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1881 | #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1882 | #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1883 | #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1884 | #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1885 | #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1886 | #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1887 | #define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1888 | #define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1889 | #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1890 | #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1891 | #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1892 | #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1893 | #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1894 | #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1895 | #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1896 | #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1897 | #define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1898 | #define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1899 | #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1900 | #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1901 | #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1902 | #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1903 | #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1904 | #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1905 | #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1906 | #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1907 | #define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1908 | #define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1909 | #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1910 | #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1911 | #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1912 | #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1913 | #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1914 | #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1915 | #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1916 | #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1917 | #define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1918 | #define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1919 | #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1920 | #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1921 | #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1922 | #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1923 | #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1924 | #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1925 | #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1926 | #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1927 | #define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1928 | #define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1929 | #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1930 | #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1931 | #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1932 | #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1933 | #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1934 | #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1935 | #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1936 | #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1937 | #define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1938 | #define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1939 | #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1940 | #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1941 | #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1942 | #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1943 | #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1944 | #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1945 | #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1946 | #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1947 | #define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1948 | #define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1949 | #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1950 | #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1951 | #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1952 | #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1953 | #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1954 | #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1955 | #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1956 | #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1957 | #define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1958 | #define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1959 | #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1960 | #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1961 | #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1962 | #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1963 | #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1964 | #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1965 | #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1966 | #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1967 | #define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1968 | #define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1969 | #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1970 | #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1971 | #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1972 | #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1973 | #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1974 | #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1975 | #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1976 | #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1977 | #define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1978 | #define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1979 | #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf |
| 1980 | #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
| 1981 | #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 |
| 1982 | #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
| 1983 | #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 |
| 1984 | #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
| 1985 | #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 |
| 1986 | #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
| 1987 | #define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 |
| 1988 | #define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
| 1989 | #define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 1990 | #define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 1991 | #define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 1992 | #define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 1993 | #define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 1994 | #define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 1995 | #define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 |
| 1996 | #define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
| 1997 | #define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 |
| 1998 | #define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
| 1999 | #define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 |
| 2000 | #define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
| 2001 | #define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 |
| 2002 | #define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
| 2003 | #define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 |
| 2004 | #define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
| 2005 | #define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 |
| 2006 | #define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
| 2007 | #define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 |
| 2008 | #define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
| 2009 | #define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 |
| 2010 | #define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
| 2011 | #define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x1 |
| 2012 | #define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
| 2013 | #define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2 |
| 2014 | #define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
| 2015 | #define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x4 |
| 2016 | #define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
| 2017 | #define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x8 |
| 2018 | #define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
| 2019 | #define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x10 |
| 2020 | #define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
| 2021 | #define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x20 |
| 2022 | #define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
| 2023 | #define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x40 |
| 2024 | #define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
| 2025 | #define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 2026 | #define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 2027 | #define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 2028 | #define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 2029 | #define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 2030 | #define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 2031 | #define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x1f |
| 2032 | #define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
| 2033 | #define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x20 |
| 2034 | #define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
| 2035 | #define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x40 |
| 2036 | #define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
| 2037 | #define PCIE_ATS_CNTL__STU_MASK 0x1f |
| 2038 | #define PCIE_ATS_CNTL__STU__SHIFT 0x0 |
| 2039 | #define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000 |
| 2040 | #define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
| 2041 | #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 2042 | #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 2043 | #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 2044 | #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 2045 | #define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 2046 | #define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 2047 | #define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x1 |
| 2048 | #define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
| 2049 | #define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2 |
| 2050 | #define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
| 2051 | #define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x1 |
| 2052 | #define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
| 2053 | #define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2 |
| 2054 | #define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
| 2055 | #define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x100 |
| 2056 | #define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
| 2057 | #define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000 |
| 2058 | #define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
| 2059 | #define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffff |
| 2060 | #define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
| 2061 | #define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffff |
| 2062 | #define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
| 2063 | #define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 2064 | #define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 2065 | #define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 2066 | #define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 2067 | #define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 2068 | #define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 2069 | #define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2 |
| 2070 | #define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
| 2071 | #define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x4 |
| 2072 | #define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
| 2073 | #define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1f00 |
| 2074 | #define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
| 2075 | #define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x1 |
| 2076 | #define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
| 2077 | #define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2 |
| 2078 | #define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
| 2079 | #define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x4 |
| 2080 | #define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
| 2081 | #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 2082 | #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 2083 | #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 2084 | #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 2085 | #define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 2086 | #define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 2087 | #define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x1 |
| 2088 | #define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
| 2089 | #define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2 |
| 2090 | #define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
| 2091 | #define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x4 |
| 2092 | #define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
| 2093 | #define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x100 |
| 2094 | #define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
| 2095 | #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x600 |
| 2096 | #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
| 2097 | #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x7ff0000 |
| 2098 | #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
| 2099 | #define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x7 |
| 2100 | #define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
| 2101 | #define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x300 |
| 2102 | #define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
| 2103 | #define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 2104 | #define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 2105 | #define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 2106 | #define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 2107 | #define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 2108 | #define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 2109 | #define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f |
| 2110 | #define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
| 2111 | #define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3f00 |
| 2112 | #define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
| 2113 | #define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 |
| 2114 | #define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
| 2115 | #define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f |
| 2116 | #define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
| 2117 | #define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000 |
| 2118 | #define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
| 2119 | #define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f |
| 2120 | #define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
| 2121 | #define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 |
| 2122 | #define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
| 2123 | #define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff |
| 2124 | #define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
| 2125 | #define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff |
| 2126 | #define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
| 2127 | #define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff |
| 2128 | #define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
| 2129 | #define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff |
| 2130 | #define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
| 2131 | #define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff |
| 2132 | #define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
| 2133 | #define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff |
| 2134 | #define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
| 2135 | #define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff |
| 2136 | #define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
| 2137 | #define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 2138 | #define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 2139 | #define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 2140 | #define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 2141 | #define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 2142 | #define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 2143 | #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x3ff |
| 2144 | #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
| 2145 | #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x1c00 |
| 2146 | #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
| 2147 | #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x3ff0000 |
| 2148 | #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
| 2149 | #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000 |
| 2150 | #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
| 2151 | #define PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 2152 | #define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 2153 | #define PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 2154 | #define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 2155 | #define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 2156 | #define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 2157 | #define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x1 |
| 2158 | #define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
| 2159 | #define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x2 |
| 2160 | #define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
| 2161 | #define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xff00 |
| 2162 | #define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
| 2163 | #define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x1 |
| 2164 | #define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
| 2165 | #define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x2 |
| 2166 | #define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
| 2167 | #define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x70 |
| 2168 | #define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
| 2169 | #define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0xffff |
| 2170 | #define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
| 2171 | #define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 |
| 2172 | #define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
| 2173 | #define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 |
| 2174 | #define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
| 2175 | #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x1 |
| 2176 | #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 |
| 2177 | #define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x2 |
| 2178 | #define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
| 2179 | #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xffe00000 |
| 2180 | #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 |
| 2181 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x1 |
| 2182 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
| 2183 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x2 |
| 2184 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 |
| 2185 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x4 |
| 2186 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 |
| 2187 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x8 |
| 2188 | #define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
| 2189 | #define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x10 |
| 2190 | #define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
| 2191 | #define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x1 |
| 2192 | #define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 |
| 2193 | #define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xffff |
| 2194 | #define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
| 2195 | #define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xffff |
| 2196 | #define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
| 2197 | #define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xffff |
| 2198 | #define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
| 2199 | #define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xff |
| 2200 | #define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
| 2201 | #define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xffff |
| 2202 | #define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
| 2203 | #define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xffff |
| 2204 | #define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
| 2205 | #define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xffff |
| 2206 | #define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
| 2207 | #define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xffffffff |
| 2208 | #define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
| 2209 | #define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xffffffff |
| 2210 | #define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
| 2211 | #define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xffffffff |
| 2212 | #define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
| 2213 | #define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xffffffff |
| 2214 | #define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
| 2215 | #define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xffffffff |
| 2216 | #define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
| 2217 | #define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xffffffff |
| 2218 | #define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
| 2219 | #define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xffffffff |
| 2220 | #define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
| 2221 | #define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xffffffff |
| 2222 | #define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
| 2223 | #define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xffffffff |
| 2224 | #define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x0 |
| 2225 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0xffff |
| 2226 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
| 2227 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0xf0000 |
| 2228 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
| 2229 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xfff00000 |
| 2230 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
| 2231 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0xffff |
| 2232 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 |
| 2233 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0xf0000 |
| 2234 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 |
| 2235 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xfff00000 |
| 2236 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 |
| 2237 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x1 |
| 2238 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 |
| 2239 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xffff0000 |
| 2240 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 |
| 2241 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__CMD_CONTROL_MASK 0xff |
| 2242 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__CMD_CONTROL__SHIFT 0x0 |
| 2243 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__FCN_ID_MASK 0xff00 |
| 2244 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__FCN_ID__SHIFT 0x8 |
| 2245 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__NXT_FCN_ID_MASK 0xff0000 |
| 2246 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__NXT_FCN_ID__SHIFT 0x10 |
| 2247 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS__CMD_STATUS_MASK 0xff |
| 2248 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS__CMD_STATUS__SHIFT 0x0 |
| 2249 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x1 |
| 2250 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 |
| 2251 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK 0xffffffff |
| 2252 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0 |
| 2253 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS_MASK 0xffffffff |
| 2254 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0 |
| 2255 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_SIZE_MASK 0x7f |
| 2256 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_SIZE__SHIFT 0x0 |
| 2257 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x80 |
| 2258 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 |
| 2259 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_OFFSET_MASK 0xfffc0000 |
| 2260 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_OFFSET__SHIFT 0x12 |
| 2261 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xffff |
| 2262 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x0 |
| 2263 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0xffff0000 |
| 2264 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x10 |
| 2265 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff |
| 2266 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
| 2267 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GPU_INFO_OFFSET_MASK 0xff00 |
| 2268 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GPU_INFO_OFFSET__SHIFT 0x8 |
| 2269 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__AUTO_SCH_OFFSET_MASK 0xff0000 |
| 2270 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__AUTO_SCH_OFFSET__SHIFT 0x10 |
| 2271 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__DISP_OFFSET_MASK 0xff000000 |
| 2272 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__DISP_OFFSET__SHIFT 0x18 |
| 2273 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_OFFSET_MASK 0xffff |
| 2274 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_OFFSET__SHIFT 0x0 |
| 2275 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_SIZE_MASK 0xffff0000 |
| 2276 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_SIZE__SHIFT 0x10 |
| 2277 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_OFFSET_MASK 0xffff |
| 2278 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_OFFSET__SHIFT 0x0 |
| 2279 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_SIZE_MASK 0xffff0000 |
| 2280 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_SIZE__SHIFT 0x10 |
| 2281 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_OFFSET_MASK 0xffff |
| 2282 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_OFFSET__SHIFT 0x0 |
| 2283 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_SIZE_MASK 0xffff0000 |
| 2284 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_SIZE__SHIFT 0x10 |
| 2285 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_OFFSET_MASK 0xffff |
| 2286 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_OFFSET__SHIFT 0x0 |
| 2287 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_SIZE_MASK 0xffff0000 |
| 2288 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_SIZE__SHIFT 0x10 |
| 2289 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_OFFSET_MASK 0xffff |
| 2290 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_OFFSET__SHIFT 0x0 |
| 2291 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_SIZE_MASK 0xffff0000 |
| 2292 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_SIZE__SHIFT 0x10 |
| 2293 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_OFFSET_MASK 0xffff |
| 2294 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_OFFSET__SHIFT 0x0 |
| 2295 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_SIZE_MASK 0xffff0000 |
| 2296 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_SIZE__SHIFT 0x10 |
| 2297 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_OFFSET_MASK 0xffff |
| 2298 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_OFFSET__SHIFT 0x0 |
| 2299 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_SIZE_MASK 0xffff0000 |
| 2300 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_SIZE__SHIFT 0x10 |
| 2301 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_OFFSET_MASK 0xffff |
| 2302 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_OFFSET__SHIFT 0x0 |
| 2303 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_SIZE_MASK 0xffff0000 |
| 2304 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_SIZE__SHIFT 0x10 |
| 2305 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_OFFSET_MASK 0xffff |
| 2306 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_OFFSET__SHIFT 0x0 |
| 2307 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_SIZE_MASK 0xffff0000 |
| 2308 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_SIZE__SHIFT 0x10 |
| 2309 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_OFFSET_MASK 0xffff |
| 2310 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_OFFSET__SHIFT 0x0 |
| 2311 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_SIZE_MASK 0xffff0000 |
| 2312 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_SIZE__SHIFT 0x10 |
| 2313 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_OFFSET_MASK 0xffff |
| 2314 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_OFFSET__SHIFT 0x0 |
| 2315 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_SIZE_MASK 0xffff0000 |
| 2316 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_SIZE__SHIFT 0x10 |
| 2317 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_OFFSET_MASK 0xffff |
| 2318 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_OFFSET__SHIFT 0x0 |
| 2319 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_SIZE_MASK 0xffff0000 |
| 2320 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_SIZE__SHIFT 0x10 |
| 2321 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_OFFSET_MASK 0xffff |
| 2322 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_OFFSET__SHIFT 0x0 |
| 2323 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_SIZE_MASK 0xffff0000 |
| 2324 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_SIZE__SHIFT 0x10 |
| 2325 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_OFFSET_MASK 0xffff |
| 2326 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_OFFSET__SHIFT 0x0 |
| 2327 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_SIZE_MASK 0xffff0000 |
| 2328 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_SIZE__SHIFT 0x10 |
| 2329 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_OFFSET_MASK 0xffff |
| 2330 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_OFFSET__SHIFT 0x0 |
| 2331 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_SIZE_MASK 0xffff0000 |
| 2332 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_SIZE__SHIFT 0x10 |
| 2333 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_OFFSET_MASK 0xffff |
| 2334 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_OFFSET__SHIFT 0x0 |
| 2335 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_SIZE_MASK 0xffff0000 |
| 2336 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_SIZE__SHIFT 0x10 |
| 2337 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT__GPU_IDLE_LATENCY_MASK 0xffffffff |
| 2338 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT__GPU_IDLE_LATENCY__SHIFT 0x0 |
| 2339 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__LOWER_MASK 0xffff |
| 2340 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__LOWER__SHIFT 0x0 |
| 2341 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__UPPER_MASK 0xffff0000 |
| 2342 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__UPPER__SHIFT 0x10 |
| 2343 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__LOWER_MASK 0xffff |
| 2344 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__LOWER__SHIFT 0x0 |
| 2345 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__UPPER_MASK 0xffff0000 |
| 2346 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__UPPER__SHIFT 0x10 |
| 2347 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__LOWER_MASK 0xffff |
| 2348 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__LOWER__SHIFT 0x0 |
| 2349 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__UPPER_MASK 0xffff0000 |
| 2350 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__UPPER__SHIFT 0x10 |
| 2351 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__LOWER_MASK 0xffff |
| 2352 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__LOWER__SHIFT 0x0 |
| 2353 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__UPPER_MASK 0xffff0000 |
| 2354 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__UPPER__SHIFT 0x10 |
| 2355 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__LOWER_MASK 0xffff |
| 2356 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__LOWER__SHIFT 0x0 |
| 2357 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__UPPER_MASK 0xffff0000 |
| 2358 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__UPPER__SHIFT 0x10 |
| 2359 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__LOWER_MASK 0xffff |
| 2360 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__LOWER__SHIFT 0x0 |
| 2361 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__UPPER_MASK 0xffff0000 |
| 2362 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__UPPER__SHIFT 0x10 |
| 2363 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0__DATA_MASK 0xffffffff |
| 2364 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0__DATA__SHIFT 0x0 |
| 2365 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1__DATA_MASK 0xffffffff |
| 2366 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1__DATA__SHIFT 0x0 |
| 2367 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2__DATA_MASK 0xffffffff |
| 2368 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2__DATA__SHIFT 0x0 |
| 2369 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3__DATA_MASK 0xffffffff |
| 2370 | #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3__DATA__SHIFT 0x0 |
| 2371 | #define PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff |
| 2372 | #define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 |
| 2373 | #define PCIE_DATA__PCIE_DATA_MASK 0xffffffff |
| 2374 | #define PCIE_DATA__PCIE_DATA__SHIFT 0x0 |
| 2375 | #define PCIE_INDEX_2__PCIE_INDEX_MASK 0xffffffff |
| 2376 | #define PCIE_INDEX_2__PCIE_INDEX__SHIFT 0x0 |
| 2377 | #define PCIE_DATA_2__PCIE_DATA_MASK 0xffffffff |
| 2378 | #define PCIE_DATA_2__PCIE_DATA__SHIFT 0x0 |
| 2379 | #define PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A_MASK 0x1 |
| 2380 | #define PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A__SHIFT 0x0 |
| 2381 | #define LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1 |
| 2382 | #define LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0 |
| 2383 | #define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2 |
| 2384 | #define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1 |
| 2385 | #define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4 |
| 2386 | #define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2 |
| 2387 | #define LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8 |
| 2388 | #define LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3 |
| 2389 | #define LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10 |
| 2390 | #define LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4 |
| 2391 | #define CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff |
| 2392 | #define CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0 |
| 2393 | #define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7 |
| 2394 | #define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0 |
| 2395 | #define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70 |
| 2396 | #define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4 |
| 2397 | #define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff |
| 2398 | #define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0 |
| 2399 | #define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000 |
| 2400 | #define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10 |
| 2401 | #define LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff |
| 2402 | #define LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0 |
| 2403 | #define LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff |
| 2404 | #define LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0 |
| 2405 | #define LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff |
| 2406 | #define LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0 |
| 2407 | #define PCIE_EFUSE__PCIE_EFUSE_VALID_MASK 0x2 |
| 2408 | #define PCIE_EFUSE__PCIE_EFUSE_VALID__SHIFT 0x1 |
| 2409 | #define PCIE_EFUSE__PPHY_EFUSE_VALID_MASK 0x4 |
| 2410 | #define PCIE_EFUSE__PPHY_EFUSE_VALID__SHIFT 0x2 |
| 2411 | #define PCIE_EFUSE__SPARE_5_3_EFUSE0_MASK 0x38 |
| 2412 | #define PCIE_EFUSE__SPARE_5_3_EFUSE0__SHIFT 0x3 |
| 2413 | #define PCIE_EFUSE__ISTRAP_ARBEN0_MASK 0x40 |
| 2414 | #define PCIE_EFUSE__ISTRAP_ARBEN0__SHIFT 0x6 |
| 2415 | #define PCIE_EFUSE__SPARE_26_7_EFUSE0_MASK 0x7ffff80 |
| 2416 | #define PCIE_EFUSE__SPARE_26_7_EFUSE0__SHIFT 0x7 |
| 2417 | #define PCIE_EFUSE__CHIP_BIF_MODE_MASK 0x8000000 |
| 2418 | #define PCIE_EFUSE__CHIP_BIF_MODE__SHIFT 0x1b |
| 2419 | #define PCIE_EFUSE__SPARE_31_28_EFUSE0_MASK 0xf0000000 |
| 2420 | #define PCIE_EFUSE__SPARE_31_28_EFUSE0__SHIFT 0x1c |
| 2421 | #define PCIE_EFUSE2__SPARE_31_1_EFUSE2_MASK 0xfffffffe |
| 2422 | #define PCIE_EFUSE2__SPARE_31_1_EFUSE2__SHIFT 0x1 |
| 2423 | #define PCIE_EFUSE3__STRAP_CEC_ID_MASK 0x1fffe |
| 2424 | #define PCIE_EFUSE3__STRAP_CEC_ID__SHIFT 0x1 |
| 2425 | #define PCIE_EFUSE3__STRAP_BIF_KILL_GEN3_MASK 0x20000 |
| 2426 | #define PCIE_EFUSE3__STRAP_BIF_KILL_GEN3__SHIFT 0x11 |
| 2427 | #define PCIE_EFUSE3__SPARE_14_PCIEFUSE3_MASK 0xfffc0000 |
| 2428 | #define PCIE_EFUSE3__SPARE_14_PCIEFUSE3__SHIFT 0x12 |
| 2429 | #define PCIE_EFUSE4__CC_WRITE_DISABLE_MASK 0x1 |
| 2430 | #define PCIE_EFUSE4__CC_WRITE_DISABLE__SHIFT 0x0 |
| 2431 | #define PCIE_EFUSE4__SPARE_3_PCIEFUSE4_MASK 0xe |
| 2432 | #define PCIE_EFUSE4__SPARE_3_PCIEFUSE4__SHIFT 0x1 |
| 2433 | #define PCIE_EFUSE4__STRAP_BIF_F0_DEVICE_ID_MASK 0xffff0 |
| 2434 | #define PCIE_EFUSE4__STRAP_BIF_F0_DEVICE_ID__SHIFT 0x4 |
| 2435 | #define PCIE_EFUSE4__STRAP_BIF_F0_MAJOR_REV_ID_MASK 0xf00000 |
| 2436 | #define PCIE_EFUSE4__STRAP_BIF_F0_MAJOR_REV_ID__SHIFT 0x14 |
| 2437 | #define PCIE_EFUSE4__STRAP_BIF_F0_MINOR_REV_ID_MASK 0xf000000 |
| 2438 | #define PCIE_EFUSE4__STRAP_BIF_F0_MINOR_REV_ID__SHIFT 0x18 |
| 2439 | #define PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK 0xf0000000 |
| 2440 | #define PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT 0x1c |
| 2441 | #define PCIE_EFUSE5__STRAP_AZALIA_DID_MASK 0x1fffe |
| 2442 | #define PCIE_EFUSE5__STRAP_AZALIA_DID__SHIFT 0x1 |
| 2443 | #define PCIE_EFUSE5__SPARE_16_PCIEFUSE5_MASK 0xfffe0000 |
| 2444 | #define PCIE_EFUSE5__SPARE_16_PCIEFUSE5__SHIFT 0x11 |
| 2445 | #define PCIE_EFUSE6__STRAP_BIF_F0_SUPPORTED_PAGE_SIZES_MASK 0x1fffe |
| 2446 | #define PCIE_EFUSE6__STRAP_BIF_F0_SUPPORTED_PAGE_SIZES__SHIFT 0x1 |
| 2447 | #define PCIE_EFUSE6__SPARE_15_PCIEFUSE6_MASK 0xfffe0000 |
| 2448 | #define PCIE_EFUSE6__SPARE_15_PCIEFUSE6__SHIFT 0x11 |
| 2449 | #define PCIE_EFUSE7__STRAP_BIF_F0_SRIOV_VF_DEVICE_ID_MASK 0x1fffe |
| 2450 | #define PCIE_EFUSE7__STRAP_BIF_F0_SRIOV_VF_DEVICE_ID__SHIFT 0x1 |
| 2451 | #define PCIE_EFUSE7__SPARE_15_PCIEFUSE7_MASK 0xfffe0000 |
| 2452 | #define PCIE_EFUSE7__SPARE_15_PCIEFUSE7__SHIFT 0x11 |
| 2453 | #define PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff |
| 2454 | #define PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0 |
| 2455 | #define PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff |
| 2456 | #define PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0 |
| 2457 | #define PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1 |
| 2458 | #define PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0 |
| 2459 | #define PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1 |
| 2460 | #define PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0 |
| 2461 | #define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1 |
| 2462 | #define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0 |
| 2463 | #define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2 |
| 2464 | #define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1 |
| 2465 | #define PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY_MASK 0x2 |
| 2466 | #define PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY__SHIFT 0x1 |
| 2467 | #define PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4 |
| 2468 | #define PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2 |
| 2469 | #define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7 |
| 2470 | #define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0 |
| 2471 | #define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70 |
| 2472 | #define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4 |
| 2473 | #define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80 |
| 2474 | #define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7 |
| 2475 | #define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100 |
| 2476 | #define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8 |
| 2477 | #define PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xffff |
| 2478 | #define PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0 |
| 2479 | #define PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000 |
| 2480 | #define PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10 |
| 2481 | #define REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1 |
| 2482 | #define REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0 |
| 2483 | #define REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1 |
| 2484 | #define REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0 |
| 2485 | #define REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1 |
| 2486 | #define REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0 |
| 2487 | #define REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1 |
| 2488 | #define REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0 |
| 2489 | #define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff |
| 2490 | #define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
| 2491 | #define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff |
| 2492 | #define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
| 2493 | #define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1 |
| 2494 | #define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 |
| 2495 | #define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2 |
| 2496 | #define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 |
| 2497 | #define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4 |
| 2498 | #define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 |
| 2499 | #define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8 |
| 2500 | #define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 |
| 2501 | #define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10 |
| 2502 | #define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 |
| 2503 | #define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20 |
| 2504 | #define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 |
| 2505 | #define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40 |
| 2506 | #define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 |
| 2507 | #define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80 |
| 2508 | #define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 |
| 2509 | #define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100 |
| 2510 | #define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 |
| 2511 | #define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200 |
| 2512 | #define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 |
| 2513 | #define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400 |
| 2514 | #define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa |
| 2515 | #define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800 |
| 2516 | #define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb |
| 2517 | #define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 |
| 2518 | #define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc |
| 2519 | #define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 |
| 2520 | #define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd |
| 2521 | #define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 |
| 2522 | #define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe |
| 2523 | #define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 |
| 2524 | #define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf |
| 2525 | #define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff |
| 2526 | #define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0 |
| 2527 | #define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff |
| 2528 | #define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0 |
| 2529 | #define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1 |
| 2530 | #define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
| 2531 | #define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe |
| 2532 | #define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1 |
| 2533 | #define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80 |
| 2534 | #define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
| 2535 | #define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100 |
| 2536 | #define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
| 2537 | #define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200 |
| 2538 | #define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9 |
| 2539 | #define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00 |
| 2540 | #define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa |
| 2541 | #define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000 |
| 2542 | #define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf |
| 2543 | #define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000 |
| 2544 | #define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10 |
| 2545 | #define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000 |
| 2546 | #define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11 |
| 2547 | #define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000 |
| 2548 | #define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12 |
| 2549 | #define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000 |
| 2550 | #define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13 |
| 2551 | #define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000 |
| 2552 | #define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14 |
| 2553 | #define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000 |
| 2554 | #define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15 |
| 2555 | #define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000 |
| 2556 | #define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16 |
| 2557 | #define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000 |
| 2558 | #define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17 |
| 2559 | #define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000 |
| 2560 | #define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18 |
| 2561 | #define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000 |
| 2562 | #define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
| 2563 | #define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000 |
| 2564 | #define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f |
| 2565 | #define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf |
| 2566 | #define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0 |
| 2567 | #define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000 |
| 2568 | #define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10 |
| 2569 | #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000 |
| 2570 | #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11 |
| 2571 | #define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000 |
| 2572 | #define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14 |
| 2573 | #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000 |
| 2574 | #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15 |
| 2575 | #define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000 |
| 2576 | #define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18 |
| 2577 | #define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000 |
| 2578 | #define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
| 2579 | #define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff |
| 2580 | #define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0 |
| 2581 | #define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100 |
| 2582 | #define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8 |
| 2583 | #define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000 |
| 2584 | #define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10 |
| 2585 | #define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x1 |
| 2586 | #define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 |
| 2587 | #define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2 |
| 2588 | #define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 |
| 2589 | #define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x4 |
| 2590 | #define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 |
| 2591 | #define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x8 |
| 2592 | #define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 |
| 2593 | #define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x10 |
| 2594 | #define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 |
| 2595 | #define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x40 |
| 2596 | #define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 |
| 2597 | #define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x80 |
| 2598 | #define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x7 |
| 2599 | #define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x100 |
| 2600 | #define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x8 |
| 2601 | #define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x1 |
| 2602 | #define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 |
| 2603 | #define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2 |
| 2604 | #define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 |
| 2605 | #define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x4 |
| 2606 | #define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 |
| 2607 | #define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x8 |
| 2608 | #define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 |
| 2609 | #define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x10 |
| 2610 | #define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 |
| 2611 | #define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x40 |
| 2612 | #define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 |
| 2613 | #define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x80 |
| 2614 | #define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x7 |
| 2615 | #define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x100 |
| 2616 | #define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x8 |
| 2617 | #define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1 |
| 2618 | #define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0 |
| 2619 | #define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e |
| 2620 | #define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1 |
| 2621 | #define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0 |
| 2622 | #define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6 |
| 2623 | #define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800 |
| 2624 | #define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb |
| 2625 | #define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000 |
| 2626 | #define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc |
| 2627 | #define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000 |
| 2628 | #define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd |
| 2629 | #define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000 |
| 2630 | #define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe |
| 2631 | #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 |
| 2632 | #define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10 |
| 2633 | #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000 |
| 2634 | #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11 |
| 2635 | #define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000 |
| 2636 | #define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12 |
| 2637 | #define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000 |
| 2638 | #define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13 |
| 2639 | #define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000 |
| 2640 | #define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14 |
| 2641 | #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000 |
| 2642 | #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15 |
| 2643 | #define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000 |
| 2644 | #define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16 |
| 2645 | #define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000 |
| 2646 | #define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17 |
| 2647 | #define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000 |
| 2648 | #define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18 |
| 2649 | #define PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000 |
| 2650 | #define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d |
| 2651 | #define PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000 |
| 2652 | #define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e |
| 2653 | #define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000 |
| 2654 | #define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f |
| 2655 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1 |
| 2656 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
| 2657 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2 |
| 2658 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1 |
| 2659 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4 |
| 2660 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2 |
| 2661 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8 |
| 2662 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3 |
| 2663 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10 |
| 2664 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4 |
| 2665 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20 |
| 2666 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5 |
| 2667 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100 |
| 2668 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8 |
| 2669 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00 |
| 2670 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9 |
| 2671 | #define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000 |
| 2672 | #define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc |
| 2673 | #define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000 |
| 2674 | #define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd |
| 2675 | #define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000 |
| 2676 | #define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe |
| 2677 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000 |
| 2678 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10 |
| 2679 | #define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000 |
| 2680 | #define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
| 2681 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3 |
| 2682 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0 |
| 2683 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc |
| 2684 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2 |
| 2685 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30 |
| 2686 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4 |
| 2687 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0 |
| 2688 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6 |
| 2689 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300 |
| 2690 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8 |
| 2691 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00 |
| 2692 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa |
| 2693 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000 |
| 2694 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc |
| 2695 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK 0x3 |
| 2696 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT 0x0 |
| 2697 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK 0xc |
| 2698 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2 |
| 2699 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK 0x30 |
| 2700 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT 0x4 |
| 2701 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK 0xc0 |
| 2702 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT 0x6 |
| 2703 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK 0x300 |
| 2704 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT 0x8 |
| 2705 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK 0xc00 |
| 2706 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT 0xa |
| 2707 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK 0x3000 |
| 2708 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT 0xc |
| 2709 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK 0x30000 |
| 2710 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT 0x10 |
| 2711 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK 0xc0000 |
| 2712 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT 0x12 |
| 2713 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK 0x300000 |
| 2714 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT 0x14 |
| 2715 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK 0xc00000 |
| 2716 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT 0x16 |
| 2717 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK 0x3000000 |
| 2718 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT 0x18 |
| 2719 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK 0xc000000 |
| 2720 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT 0x1a |
| 2721 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK 0x30000000 |
| 2722 | #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT 0x1c |
| 2723 | #define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4 |
| 2724 | #define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2 |
| 2725 | #define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8 |
| 2726 | #define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3 |
| 2727 | #define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10 |
| 2728 | #define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4 |
| 2729 | #define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0 |
| 2730 | #define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6 |
| 2731 | #define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100 |
| 2732 | #define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8 |
| 2733 | #define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200 |
| 2734 | #define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9 |
| 2735 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400 |
| 2736 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa |
| 2737 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800 |
| 2738 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb |
| 2739 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000 |
| 2740 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc |
| 2741 | #define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x2000 |
| 2742 | #define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0xd |
| 2743 | #define PCIE_CI_CNTL__CI_MST_ATOMIC_ADDR_HASH_MASK 0x70000 |
| 2744 | #define PCIE_CI_CNTL__CI_MST_ATOMIC_ADDR_HASH__SHIFT 0x10 |
| 2745 | #define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40 |
| 2746 | #define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6 |
| 2747 | #define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80 |
| 2748 | #define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
| 2749 | #define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000 |
| 2750 | #define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc |
| 2751 | #define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f |
| 2752 | #define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0 |
| 2753 | #define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00 |
| 2754 | #define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8 |
| 2755 | #define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000 |
| 2756 | #define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10 |
| 2757 | #define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000 |
| 2758 | #define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18 |
| 2759 | #define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f |
| 2760 | #define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0 |
| 2761 | #define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00 |
| 2762 | #define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8 |
| 2763 | #define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000 |
| 2764 | #define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10 |
| 2765 | #define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000 |
| 2766 | #define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18 |
| 2767 | #define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f |
| 2768 | #define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0 |
| 2769 | #define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00 |
| 2770 | #define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8 |
| 2771 | #define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000 |
| 2772 | #define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10 |
| 2773 | #define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000 |
| 2774 | #define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18 |
| 2775 | #define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f |
| 2776 | #define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0 |
| 2777 | #define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00 |
| 2778 | #define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8 |
| 2779 | #define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000 |
| 2780 | #define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10 |
| 2781 | #define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000 |
| 2782 | #define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18 |
| 2783 | #define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f |
| 2784 | #define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0 |
| 2785 | #define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00 |
| 2786 | #define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8 |
| 2787 | #define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000 |
| 2788 | #define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10 |
| 2789 | #define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000 |
| 2790 | #define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18 |
| 2791 | #define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f |
| 2792 | #define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0 |
| 2793 | #define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00 |
| 2794 | #define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8 |
| 2795 | #define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000 |
| 2796 | #define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10 |
| 2797 | #define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000 |
| 2798 | #define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18 |
| 2799 | #define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1 |
| 2800 | #define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0 |
| 2801 | #define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2 |
| 2802 | #define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1 |
| 2803 | #define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c |
| 2804 | #define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2 |
| 2805 | #define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0 |
| 2806 | #define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5 |
| 2807 | #define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff |
| 2808 | #define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0 |
| 2809 | #define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000 |
| 2810 | #define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10 |
| 2811 | #define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1 |
| 2812 | #define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0 |
| 2813 | #define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2 |
| 2814 | #define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1 |
| 2815 | #define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4 |
| 2816 | #define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2 |
| 2817 | #define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8 |
| 2818 | #define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3 |
| 2819 | #define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10 |
| 2820 | #define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4 |
| 2821 | #define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20 |
| 2822 | #define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5 |
| 2823 | #define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40 |
| 2824 | #define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6 |
| 2825 | #define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff |
| 2826 | #define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0 |
| 2827 | #define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff |
| 2828 | #define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0 |
| 2829 | #define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff |
| 2830 | #define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0 |
| 2831 | #define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff |
| 2832 | #define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0 |
| 2833 | #define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff |
| 2834 | #define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0 |
| 2835 | #define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff |
| 2836 | #define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0 |
| 2837 | #define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff |
| 2838 | #define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0 |
| 2839 | #define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff |
| 2840 | #define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0 |
| 2841 | #define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff |
| 2842 | #define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0 |
| 2843 | #define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff |
| 2844 | #define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0 |
| 2845 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1 |
| 2846 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
| 2847 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2 |
| 2848 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
| 2849 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4 |
| 2850 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
| 2851 | #define PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1 |
| 2852 | #define PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0 |
| 2853 | #define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1 |
| 2854 | #define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0 |
| 2855 | #define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2 |
| 2856 | #define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1 |
| 2857 | #define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4 |
| 2858 | #define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2 |
| 2859 | #define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8 |
| 2860 | #define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3 |
| 2861 | #define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10 |
| 2862 | #define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4 |
| 2863 | #define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20 |
| 2864 | #define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5 |
| 2865 | #define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40 |
| 2866 | #define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6 |
| 2867 | #define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80 |
| 2868 | #define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7 |
| 2869 | #define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100 |
| 2870 | #define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8 |
| 2871 | #define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000 |
| 2872 | #define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc |
| 2873 | #define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000 |
| 2874 | #define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd |
| 2875 | #define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000 |
| 2876 | #define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe |
| 2877 | #define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000 |
| 2878 | #define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10 |
| 2879 | #define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff |
| 2880 | #define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0 |
| 2881 | #define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000 |
| 2882 | #define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10 |
| 2883 | #define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff |
| 2884 | #define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0 |
| 2885 | #define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff |
| 2886 | #define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0 |
| 2887 | #define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000 |
| 2888 | #define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10 |
| 2889 | #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff |
| 2890 | #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0 |
| 2891 | #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00 |
| 2892 | #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8 |
| 2893 | #define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x1 |
| 2894 | #define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0 |
| 2895 | #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2 |
| 2896 | #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1 |
| 2897 | #define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x4 |
| 2898 | #define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2 |
| 2899 | #define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x8 |
| 2900 | #define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3 |
| 2901 | #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0xf0 |
| 2902 | #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4 |
| 2903 | #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0xf00 |
| 2904 | #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8 |
| 2905 | #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0xf000 |
| 2906 | #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc |
| 2907 | #define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x10000 |
| 2908 | #define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10 |
| 2909 | #define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x20000 |
| 2910 | #define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11 |
| 2911 | #define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x40000 |
| 2912 | #define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12 |
| 2913 | #define PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0_MASK 0x80000 |
| 2914 | #define PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__SHIFT 0x13 |
| 2915 | #define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0xf00000 |
| 2916 | #define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14 |
| 2917 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x7 |
| 2918 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 |
| 2919 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x38 |
| 2920 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 |
| 2921 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x40 |
| 2922 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 |
| 2923 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x380 |
| 2924 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 |
| 2925 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x1c00 |
| 2926 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa |
| 2927 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x2000 |
| 2928 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd |
| 2929 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x4000 |
| 2930 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe |
| 2931 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x8000 |
| 2932 | #define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf |
| 2933 | #define PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x10000 |
| 2934 | #define PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 |
| 2935 | #define PCIE_IDLE_STATUS__PCIE_ALL_IDLE_STATUS_MASK 0x1 |
| 2936 | #define PCIE_IDLE_STATUS__PCIE_ALL_IDLE_STATUS__SHIFT 0x0 |
| 2937 | #define PCIE_IDLE_STATUS__TX_TXDL_IDLE_STATUS_MASK 0x2 |
| 2938 | #define PCIE_IDLE_STATUS__TX_TXDL_IDLE_STATUS__SHIFT 0x1 |
| 2939 | #define PCIE_IDLE_STATUS__TX_RBUF_IDLE_STATUS_MASK 0x4 |
| 2940 | #define PCIE_IDLE_STATUS__TX_RBUF_IDLE_STATUS__SHIFT 0x2 |
| 2941 | #define PCIE_IDLE_STATUS__TX_RCVD_FC_CREDITS_IDLE_MASK 0x8 |
| 2942 | #define PCIE_IDLE_STATUS__TX_RCVD_FC_CREDITS_IDLE__SHIFT 0x3 |
| 2943 | #define PCIE_IDLE_STATUS__TX_RPL_CREDITS_IDLE_MASK 0x10 |
| 2944 | #define PCIE_IDLE_STATUS__TX_RPL_CREDITS_IDLE__SHIFT 0x4 |
| 2945 | #define PCIE_IDLE_STATUS__TX_PBUF_IDLE_MASK 0x20 |
| 2946 | #define PCIE_IDLE_STATUS__TX_PBUF_IDLE__SHIFT 0x5 |
| 2947 | #define PCIE_IDLE_STATUS__TX_NPBUF_IDLE_MASK 0x40 |
| 2948 | #define PCIE_IDLE_STATUS__TX_NPBUF_IDLE__SHIFT 0x6 |
| 2949 | #define PCIE_IDLE_STATUS__TX_CPLBUF_IDLE_MASK 0x80 |
| 2950 | #define PCIE_IDLE_STATUS__TX_CPLBUF_IDLE__SHIFT 0x7 |
| 2951 | #define PCIE_IDLE_STATUS__TX_MSGBUF_IDLE_MASK 0x100 |
| 2952 | #define PCIE_IDLE_STATUS__TX_MSGBUF_IDLE__SHIFT 0x8 |
| 2953 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1 |
| 2954 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0 |
| 2955 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2 |
| 2956 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1 |
| 2957 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4 |
| 2958 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2 |
| 2959 | #define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff |
| 2960 | #define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0 |
| 2961 | #define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00 |
| 2962 | #define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8 |
| 2963 | #define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000 |
| 2964 | #define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10 |
| 2965 | #define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000 |
| 2966 | #define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18 |
| 2967 | #define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff |
| 2968 | #define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0 |
| 2969 | #define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff |
| 2970 | #define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0 |
| 2971 | #define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff |
| 2972 | #define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0 |
| 2973 | #define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00 |
| 2974 | #define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8 |
| 2975 | #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000 |
| 2976 | #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10 |
| 2977 | #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000 |
| 2978 | #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18 |
| 2979 | #define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff |
| 2980 | #define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0 |
| 2981 | #define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff |
| 2982 | #define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0 |
| 2983 | #define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff |
| 2984 | #define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0 |
| 2985 | #define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00 |
| 2986 | #define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8 |
| 2987 | #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000 |
| 2988 | #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10 |
| 2989 | #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000 |
| 2990 | #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18 |
| 2991 | #define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff |
| 2992 | #define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0 |
| 2993 | #define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff |
| 2994 | #define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0 |
| 2995 | #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff |
| 2996 | #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0 |
| 2997 | #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00 |
| 2998 | #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8 |
| 2999 | #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000 |
| 3000 | #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10 |
| 3001 | #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000 |
| 3002 | #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18 |
| 3003 | #define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff |
| 3004 | #define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0 |
| 3005 | #define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff |
| 3006 | #define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0 |
| 3007 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff |
| 3008 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0 |
| 3009 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00 |
| 3010 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8 |
| 3011 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000 |
| 3012 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10 |
| 3013 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000 |
| 3014 | #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18 |
| 3015 | #define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff |
| 3016 | #define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0 |
| 3017 | #define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff |
| 3018 | #define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0 |
| 3019 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff |
| 3020 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0 |
| 3021 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00 |
| 3022 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8 |
| 3023 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000 |
| 3024 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10 |
| 3025 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000 |
| 3026 | #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18 |
| 3027 | #define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff |
| 3028 | #define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0 |
| 3029 | #define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff |
| 3030 | #define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0 |
| 3031 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf |
| 3032 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0 |
| 3033 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0 |
| 3034 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4 |
| 3035 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00 |
| 3036 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8 |
| 3037 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000 |
| 3038 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc |
| 3039 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 |
| 3040 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 |
| 3041 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 |
| 3042 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 |
| 3043 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000 |
| 3044 | #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18 |
| 3045 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf |
| 3046 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0 |
| 3047 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0 |
| 3048 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4 |
| 3049 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00 |
| 3050 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8 |
| 3051 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000 |
| 3052 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc |
| 3053 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 |
| 3054 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 |
| 3055 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 |
| 3056 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 |
| 3057 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000 |
| 3058 | #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18 |
| 3059 | #define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff |
| 3060 | #define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0 |
| 3061 | #define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00 |
| 3062 | #define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8 |
| 3063 | #define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000 |
| 3064 | #define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10 |
| 3065 | #define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000 |
| 3066 | #define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18 |
| 3067 | #define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff |
| 3068 | #define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0 |
| 3069 | #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff |
| 3070 | #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 |
| 3071 | #define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1 |
| 3072 | #define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 |
| 3073 | #define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2 |
| 3074 | #define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 |
| 3075 | #define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4 |
| 3076 | #define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2 |
| 3077 | #define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8 |
| 3078 | #define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3 |
| 3079 | #define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10 |
| 3080 | #define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4 |
| 3081 | #define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20 |
| 3082 | #define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5 |
| 3083 | #define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40 |
| 3084 | #define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6 |
| 3085 | #define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80 |
| 3086 | #define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7 |
| 3087 | #define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100 |
| 3088 | #define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8 |
| 3089 | #define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200 |
| 3090 | #define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9 |
| 3091 | #define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400 |
| 3092 | #define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa |
| 3093 | #define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800 |
| 3094 | #define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb |
| 3095 | #define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000 |
| 3096 | #define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc |
| 3097 | #define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000 |
| 3098 | #define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd |
| 3099 | #define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000 |
| 3100 | #define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe |
| 3101 | #define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000 |
| 3102 | #define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf |
| 3103 | #define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000 |
| 3104 | #define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 |
| 3105 | #define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000 |
| 3106 | #define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 |
| 3107 | #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000 |
| 3108 | #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12 |
| 3109 | #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000 |
| 3110 | #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13 |
| 3111 | #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000 |
| 3112 | #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14 |
| 3113 | #define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000 |
| 3114 | #define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 |
| 3115 | #define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000 |
| 3116 | #define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18 |
| 3117 | #define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000 |
| 3118 | #define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b |
| 3119 | #define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000 |
| 3120 | #define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c |
| 3121 | #define PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000 |
| 3122 | #define PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d |
| 3123 | #define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000 |
| 3124 | #define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e |
| 3125 | #define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2 |
| 3126 | #define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 |
| 3127 | #define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x4 |
| 3128 | #define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2 |
| 3129 | #define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x8 |
| 3130 | #define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x3 |
| 3131 | #define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x10 |
| 3132 | #define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x4 |
| 3133 | #define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x20 |
| 3134 | #define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x5 |
| 3135 | #define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x40 |
| 3136 | #define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x6 |
| 3137 | #define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x80 |
| 3138 | #define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x7 |
| 3139 | #define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x100 |
| 3140 | #define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x8 |
| 3141 | #define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x200 |
| 3142 | #define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x9 |
| 3143 | #define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x400 |
| 3144 | #define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0xa |
| 3145 | #define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x800 |
| 3146 | #define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0xb |
| 3147 | #define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x1000 |
| 3148 | #define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0xc |
| 3149 | #define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK 0x2000 |
| 3150 | #define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT 0xd |
| 3151 | #define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK 0x4000 |
| 3152 | #define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT 0xe |
| 3153 | #define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK 0x8000 |
| 3154 | #define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT 0xf |
| 3155 | #define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK 0x10000 |
| 3156 | #define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 |
| 3157 | #define PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN_MASK 0x40000 |
| 3158 | #define PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN__SHIFT 0x12 |
| 3159 | #define PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN_MASK 0x80000 |
| 3160 | #define PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN__SHIFT 0x13 |
| 3161 | #define PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN_MASK 0x100000 |
| 3162 | #define PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN__SHIFT 0x14 |
| 3163 | #define PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP_MASK 0xe00000 |
| 3164 | #define PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP__SHIFT 0x15 |
| 3165 | #define PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000 |
| 3166 | #define PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b |
| 3167 | #define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2 |
| 3168 | #define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 |
| 3169 | #define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x4 |
| 3170 | #define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2 |
| 3171 | #define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x8 |
| 3172 | #define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x3 |
| 3173 | #define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x10 |
| 3174 | #define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x4 |
| 3175 | #define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x20 |
| 3176 | #define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x5 |
| 3177 | #define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x40 |
| 3178 | #define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x6 |
| 3179 | #define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x80 |
| 3180 | #define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x7 |
| 3181 | #define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x100 |
| 3182 | #define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x8 |
| 3183 | #define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x200 |
| 3184 | #define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x9 |
| 3185 | #define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x400 |
| 3186 | #define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0xa |
| 3187 | #define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x800 |
| 3188 | #define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0xb |
| 3189 | #define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x1000 |
| 3190 | #define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0xc |
| 3191 | #define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK 0x2000 |
| 3192 | #define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT 0xd |
| 3193 | #define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK 0x4000 |
| 3194 | #define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT 0xe |
| 3195 | #define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK 0x8000 |
| 3196 | #define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT 0xf |
| 3197 | #define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK 0x10000 |
| 3198 | #define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 |
| 3199 | #define PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN_MASK 0x40000 |
| 3200 | #define PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN__SHIFT 0x12 |
| 3201 | #define PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN_MASK 0x80000 |
| 3202 | #define PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN__SHIFT 0x13 |
| 3203 | #define PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN_MASK 0x100000 |
| 3204 | #define PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN__SHIFT 0x14 |
| 3205 | #define PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP_MASK 0xe00000 |
| 3206 | #define PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP__SHIFT 0x15 |
| 3207 | #define PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000 |
| 3208 | #define PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b |
| 3209 | #define PCIE_STRAP_F3__RESERVED_MASK 0xffffffff |
| 3210 | #define PCIE_STRAP_F3__RESERVED__SHIFT 0x0 |
| 3211 | #define PCIE_STRAP_F4__RESERVED_MASK 0xffffffff |
| 3212 | #define PCIE_STRAP_F4__RESERVED__SHIFT 0x0 |
| 3213 | #define PCIE_STRAP_F5__RESERVED_MASK 0xffffffff |
| 3214 | #define PCIE_STRAP_F5__RESERVED__SHIFT 0x0 |
| 3215 | #define PCIE_STRAP_F6__RESERVED_MASK 0xffffffff |
| 3216 | #define PCIE_STRAP_F6__RESERVED__SHIFT 0x0 |
| 3217 | #define PCIE_STRAP_MSIX__STRAP_F0_MSIX_EN_MASK 0x1 |
| 3218 | #define PCIE_STRAP_MSIX__STRAP_F0_MSIX_EN__SHIFT 0x0 |
| 3219 | #define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_BIR_MASK 0xe |
| 3220 | #define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_BIR__SHIFT 0x1 |
| 3221 | #define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_OFFSET_MASK 0xfffff000 |
| 3222 | #define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_OFFSET__SHIFT 0xc |
| 3223 | #define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10 |
| 3224 | #define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4 |
| 3225 | #define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x1f00 |
| 3226 | #define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x8 |
| 3227 | #define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2000 |
| 3228 | #define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0xd |
| 3229 | #define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x4000 |
| 3230 | #define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0xe |
| 3231 | #define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x8000 |
| 3232 | #define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0xf |
| 3233 | #define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000 |
| 3234 | #define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 |
| 3235 | #define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000 |
| 3236 | #define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19 |
| 3237 | #define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000 |
| 3238 | #define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a |
| 3239 | #define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000 |
| 3240 | #define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c |
| 3241 | #define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000 |
| 3242 | #define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d |
| 3243 | #define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000 |
| 3244 | #define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e |
| 3245 | #define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000 |
| 3246 | #define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f |
| 3247 | #define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2 |
| 3248 | #define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1 |
| 3249 | #define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4 |
| 3250 | #define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 |
| 3251 | #define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8 |
| 3252 | #define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3 |
| 3253 | #define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10 |
| 3254 | #define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 |
| 3255 | #define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1 |
| 3256 | #define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0 |
| 3257 | #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000 |
| 3258 | #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c |
| 3259 | #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000 |
| 3260 | #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d |
| 3261 | #define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f |
| 3262 | #define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0 |
| 3263 | #define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80 |
| 3264 | #define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7 |
| 3265 | #define PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff |
| 3266 | #define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 |
| 3267 | #define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000 |
| 3268 | #define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10 |
| 3269 | #define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000 |
| 3270 | #define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18 |
| 3271 | #define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff |
| 3272 | #define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0 |
| 3273 | #define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000 |
| 3274 | #define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10 |
| 3275 | #define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff |
| 3276 | #define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0 |
| 3277 | #define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff |
| 3278 | #define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0 |
| 3279 | #define PCIE_PRBS_MISC__PRBS_EN_MASK 0x1 |
| 3280 | #define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0 |
| 3281 | #define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe |
| 3282 | #define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1 |
| 3283 | #define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10 |
| 3284 | #define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4 |
| 3285 | #define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20 |
| 3286 | #define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5 |
| 3287 | #define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0 |
| 3288 | #define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6 |
| 3289 | #define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00 |
| 3290 | #define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8 |
| 3291 | #define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000 |
| 3292 | #define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe |
| 3293 | #define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000 |
| 3294 | #define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10 |
| 3295 | #define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff |
| 3296 | #define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0 |
| 3297 | #define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff |
| 3298 | #define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0 |
| 3299 | #define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff |
| 3300 | #define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0 |
| 3301 | #define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff |
| 3302 | #define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0 |
| 3303 | #define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff |
| 3304 | #define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0 |
| 3305 | #define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff |
| 3306 | #define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0 |
| 3307 | #define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff |
| 3308 | #define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0 |
| 3309 | #define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff |
| 3310 | #define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0 |
| 3311 | #define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff |
| 3312 | #define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0 |
| 3313 | #define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff |
| 3314 | #define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0 |
| 3315 | #define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff |
| 3316 | #define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0 |
| 3317 | #define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff |
| 3318 | #define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0 |
| 3319 | #define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff |
| 3320 | #define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0 |
| 3321 | #define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff |
| 3322 | #define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0 |
| 3323 | #define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff |
| 3324 | #define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0 |
| 3325 | #define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff |
| 3326 | #define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0 |
| 3327 | #define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff |
| 3328 | #define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0 |
| 3329 | #define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff |
| 3330 | #define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0 |
| 3331 | #define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff |
| 3332 | #define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0 |
| 3333 | #define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300 |
| 3334 | #define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
| 3335 | #define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000 |
| 3336 | #define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
| 3337 | #define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000 |
| 3338 | #define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
| 3339 | #define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000 |
| 3340 | #define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
| 3341 | #define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff |
| 3342 | #define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
| 3343 | #define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x1f |
| 3344 | #define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 |
| 3345 | #define PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x100 |
| 3346 | #define PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 |
| 3347 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 3348 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 3349 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 3350 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 3351 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 3352 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 3353 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 3354 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 3355 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 3356 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 3357 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 3358 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 3359 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 3360 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 3361 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff |
| 3362 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
| 3363 | #define SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1 |
| 3364 | #define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0 |
| 3365 | #define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2 |
| 3366 | #define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1 |
| 3367 | #define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000 |
| 3368 | #define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10 |
| 3369 | #define SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000 |
| 3370 | #define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11 |
| 3371 | #define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1 |
| 3372 | #define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0 |
| 3373 | #define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2 |
| 3374 | #define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1 |
| 3375 | #define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c |
| 3376 | #define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2 |
| 3377 | #define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100 |
| 3378 | #define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8 |
| 3379 | #define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200 |
| 3380 | #define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9 |
| 3381 | #define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400 |
| 3382 | #define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa |
| 3383 | #define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000 |
| 3384 | #define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc |
| 3385 | #define SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000 |
| 3386 | #define SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd |
| 3387 | #define SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000 |
| 3388 | #define SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe |
| 3389 | #define SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000 |
| 3390 | #define SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10 |
| 3391 | #define SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000 |
| 3392 | #define SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11 |
| 3393 | #define SWRST_GENERAL_CONTROL__EP_COMPLT_CHK_EN_MASK 0x10000000 |
| 3394 | #define SWRST_GENERAL_CONTROL__EP_COMPLT_CHK_EN__SHIFT 0x1c |
| 3395 | #define SWRST_GENERAL_CONTROL__EP_COMPLT_WAIT_TMR_MASK 0x60000000 |
| 3396 | #define SWRST_GENERAL_CONTROL__EP_COMPLT_WAIT_TMR__SHIFT 0x1d |
| 3397 | #define SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000 |
| 3398 | #define SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf |
| 3399 | #define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000 |
| 3400 | #define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10 |
| 3401 | #define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000 |
| 3402 | #define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11 |
| 3403 | #define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000 |
| 3404 | #define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12 |
| 3405 | #define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000 |
| 3406 | #define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13 |
| 3407 | #define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000 |
| 3408 | #define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14 |
| 3409 | #define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000 |
| 3410 | #define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15 |
| 3411 | #define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000 |
| 3412 | #define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16 |
| 3413 | #define SWRST_COMMAND_1__SWITCHCLK_MASK 0x1 |
| 3414 | #define SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0 |
| 3415 | #define SWRST_COMMAND_1__RESETPCFG_MASK 0x2 |
| 3416 | #define SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1 |
| 3417 | #define SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4 |
| 3418 | #define SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2 |
| 3419 | #define SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8 |
| 3420 | #define SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3 |
| 3421 | #define SWRST_COMMAND_1__RESETSRBM0_MASK 0x10 |
| 3422 | #define SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4 |
| 3423 | #define SWRST_COMMAND_1__RESETSRBM1_MASK 0x20 |
| 3424 | #define SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5 |
| 3425 | #define SWRST_COMMAND_1__RESETLC_MASK 0x40 |
| 3426 | #define SWRST_COMMAND_1__RESETLC__SHIFT 0x6 |
| 3427 | #define SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100 |
| 3428 | #define SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8 |
| 3429 | #define SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200 |
| 3430 | #define SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9 |
| 3431 | #define SWRST_COMMAND_1__RESETMNTR_MASK 0x2000 |
| 3432 | #define SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd |
| 3433 | #define SWRST_COMMAND_1__RESETHLTR_MASK 0x4000 |
| 3434 | #define SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe |
| 3435 | #define SWRST_COMMAND_1__RESETCPM_MASK 0x8000 |
| 3436 | #define SWRST_COMMAND_1__RESETCPM__SHIFT 0xf |
| 3437 | #define SWRST_COMMAND_1__RESETPIF0_MASK 0x10000 |
| 3438 | #define SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10 |
| 3439 | #define SWRST_COMMAND_1__RESETPIF1_MASK 0x20000 |
| 3440 | #define SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11 |
| 3441 | #define SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000 |
| 3442 | #define SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14 |
| 3443 | #define SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000 |
| 3444 | #define SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15 |
| 3445 | #define SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000 |
| 3446 | #define SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18 |
| 3447 | #define SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000 |
| 3448 | #define SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19 |
| 3449 | #define SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000 |
| 3450 | #define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c |
| 3451 | #define SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000 |
| 3452 | #define SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d |
| 3453 | #define SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000 |
| 3454 | #define SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf |
| 3455 | #define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000 |
| 3456 | #define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10 |
| 3457 | #define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000 |
| 3458 | #define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11 |
| 3459 | #define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000 |
| 3460 | #define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12 |
| 3461 | #define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000 |
| 3462 | #define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13 |
| 3463 | #define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000 |
| 3464 | #define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14 |
| 3465 | #define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000 |
| 3466 | #define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15 |
| 3467 | #define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000 |
| 3468 | #define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16 |
| 3469 | #define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1 |
| 3470 | #define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0 |
| 3471 | #define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2 |
| 3472 | #define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1 |
| 3473 | #define SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4 |
| 3474 | #define SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2 |
| 3475 | #define SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8 |
| 3476 | #define SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3 |
| 3477 | #define SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10 |
| 3478 | #define SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4 |
| 3479 | #define SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20 |
| 3480 | #define SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5 |
| 3481 | #define SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40 |
| 3482 | #define SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6 |
| 3483 | #define SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100 |
| 3484 | #define SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8 |
| 3485 | #define SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200 |
| 3486 | #define SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9 |
| 3487 | #define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000 |
| 3488 | #define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd |
| 3489 | #define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000 |
| 3490 | #define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe |
| 3491 | #define SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000 |
| 3492 | #define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf |
| 3493 | #define SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000 |
| 3494 | #define SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10 |
| 3495 | #define SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000 |
| 3496 | #define SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11 |
| 3497 | #define SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000 |
| 3498 | #define SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14 |
| 3499 | #define SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000 |
| 3500 | #define SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15 |
| 3501 | #define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000 |
| 3502 | #define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18 |
| 3503 | #define SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000 |
| 3504 | #define SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19 |
| 3505 | #define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000 |
| 3506 | #define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c |
| 3507 | #define SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000 |
| 3508 | #define SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d |
| 3509 | #define SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000 |
| 3510 | #define SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf |
| 3511 | #define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000 |
| 3512 | #define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10 |
| 3513 | #define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000 |
| 3514 | #define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11 |
| 3515 | #define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000 |
| 3516 | #define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12 |
| 3517 | #define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000 |
| 3518 | #define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13 |
| 3519 | #define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000 |
| 3520 | #define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14 |
| 3521 | #define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000 |
| 3522 | #define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15 |
| 3523 | #define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000 |
| 3524 | #define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16 |
| 3525 | #define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1 |
| 3526 | #define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0 |
| 3527 | #define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2 |
| 3528 | #define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1 |
| 3529 | #define SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4 |
| 3530 | #define SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2 |
| 3531 | #define SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8 |
| 3532 | #define SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3 |
| 3533 | #define SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10 |
| 3534 | #define SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4 |
| 3535 | #define SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20 |
| 3536 | #define SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5 |
| 3537 | #define SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40 |
| 3538 | #define SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6 |
| 3539 | #define SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100 |
| 3540 | #define SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8 |
| 3541 | #define SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200 |
| 3542 | #define SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9 |
| 3543 | #define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000 |
| 3544 | #define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd |
| 3545 | #define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000 |
| 3546 | #define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe |
| 3547 | #define SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000 |
| 3548 | #define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf |
| 3549 | #define SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000 |
| 3550 | #define SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10 |
| 3551 | #define SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000 |
| 3552 | #define SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11 |
| 3553 | #define SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000 |
| 3554 | #define SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14 |
| 3555 | #define SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000 |
| 3556 | #define SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15 |
| 3557 | #define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000 |
| 3558 | #define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18 |
| 3559 | #define SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000 |
| 3560 | #define SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19 |
| 3561 | #define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000 |
| 3562 | #define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c |
| 3563 | #define SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000 |
| 3564 | #define SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d |
| 3565 | #define SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000 |
| 3566 | #define SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe |
| 3567 | #define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000 |
| 3568 | #define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10 |
| 3569 | #define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000 |
| 3570 | #define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11 |
| 3571 | #define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000 |
| 3572 | #define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12 |
| 3573 | #define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000 |
| 3574 | #define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13 |
| 3575 | #define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000 |
| 3576 | #define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14 |
| 3577 | #define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000 |
| 3578 | #define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15 |
| 3579 | #define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000 |
| 3580 | #define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16 |
| 3581 | #define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1 |
| 3582 | #define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0 |
| 3583 | #define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2 |
| 3584 | #define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1 |
| 3585 | #define SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4 |
| 3586 | #define SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2 |
| 3587 | #define SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8 |
| 3588 | #define SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3 |
| 3589 | #define SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10 |
| 3590 | #define SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4 |
| 3591 | #define SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20 |
| 3592 | #define SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5 |
| 3593 | #define SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40 |
| 3594 | #define SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6 |
| 3595 | #define SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100 |
| 3596 | #define SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8 |
| 3597 | #define SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200 |
| 3598 | #define SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9 |
| 3599 | #define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000 |
| 3600 | #define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd |
| 3601 | #define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000 |
| 3602 | #define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe |
| 3603 | #define SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000 |
| 3604 | #define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf |
| 3605 | #define SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000 |
| 3606 | #define SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10 |
| 3607 | #define SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000 |
| 3608 | #define SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11 |
| 3609 | #define SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000 |
| 3610 | #define SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14 |
| 3611 | #define SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000 |
| 3612 | #define SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15 |
| 3613 | #define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000 |
| 3614 | #define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18 |
| 3615 | #define SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000 |
| 3616 | #define SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19 |
| 3617 | #define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000 |
| 3618 | #define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c |
| 3619 | #define SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000 |
| 3620 | #define SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d |
| 3621 | #define SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1 |
| 3622 | #define SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0 |
| 3623 | #define SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100 |
| 3624 | #define SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8 |
| 3625 | #define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK 0x1 |
| 3626 | #define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT 0x0 |
| 3627 | #define SWRST_EP_COMMAND_0__EP_SOFT_RESET_MASK 0x2 |
| 3628 | #define SWRST_EP_COMMAND_0__EP_SOFT_RESET__SHIFT 0x1 |
| 3629 | #define SWRST_EP_COMMAND_0__EP_DRV_RESET_MASK 0x4 |
| 3630 | #define SWRST_EP_COMMAND_0__EP_DRV_RESET__SHIFT 0x2 |
| 3631 | #define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK 0x100 |
| 3632 | #define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT 0x8 |
| 3633 | #define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK 0x200 |
| 3634 | #define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT 0x9 |
| 3635 | #define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK 0x400 |
| 3636 | #define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT 0xa |
| 3637 | #define SWRST_EP_COMMAND_0__EP_FLR0_RESET_MASK 0x10000 |
| 3638 | #define SWRST_EP_COMMAND_0__EP_FLR0_RESET__SHIFT 0x10 |
| 3639 | #define SWRST_EP_COMMAND_0__EP_FLR1_RESET_MASK 0x20000 |
| 3640 | #define SWRST_EP_COMMAND_0__EP_FLR1_RESET__SHIFT 0x11 |
| 3641 | #define SWRST_EP_COMMAND_0__EP_FLR2_RESET_MASK 0x40000 |
| 3642 | #define SWRST_EP_COMMAND_0__EP_FLR2_RESET__SHIFT 0x12 |
| 3643 | #define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK 0x1 |
| 3644 | #define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT 0x0 |
| 3645 | #define SWRST_EP_CONTROL_0__EP_SOFT_RESET_EN_MASK 0x2 |
| 3646 | #define SWRST_EP_CONTROL_0__EP_SOFT_RESET_EN__SHIFT 0x1 |
| 3647 | #define SWRST_EP_CONTROL_0__EP_DRV_RESET_EN_MASK 0x4 |
| 3648 | #define SWRST_EP_CONTROL_0__EP_DRV_RESET_EN__SHIFT 0x2 |
| 3649 | #define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK 0x100 |
| 3650 | #define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT 0x8 |
| 3651 | #define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK 0x200 |
| 3652 | #define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT 0x9 |
| 3653 | #define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK 0x400 |
| 3654 | #define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT 0xa |
| 3655 | #define SWRST_EP_CONTROL_0__EP_FLR0_RESET_EN_MASK 0x10000 |
| 3656 | #define SWRST_EP_CONTROL_0__EP_FLR0_RESET_EN__SHIFT 0x10 |
| 3657 | #define SWRST_EP_CONTROL_0__EP_FLR1_RESET_EN_MASK 0x20000 |
| 3658 | #define SWRST_EP_CONTROL_0__EP_FLR1_RESET_EN__SHIFT 0x11 |
| 3659 | #define SWRST_EP_CONTROL_0__EP_FLR2_RESET_EN_MASK 0x40000 |
| 3660 | #define SWRST_EP_CONTROL_0__EP_FLR2_RESET_EN__SHIFT 0x12 |
| 3661 | #define SWRST_EP_CONTROL_0__EP_CFG_WR_RESET_EN_MASK 0x80000 |
| 3662 | #define SWRST_EP_CONTROL_0__EP_CFG_WR_RESET_EN__SHIFT 0x13 |
| 3663 | #define SWRST_EP_CONTROL_0__EP_FLR_DISABLE_CFG_RST_MASK 0xf00000 |
| 3664 | #define SWRST_EP_CONTROL_0__EP_FLR_DISABLE_CFG_RST__SHIFT 0x14 |
| 3665 | #define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1 |
| 3666 | #define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0 |
| 3667 | #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2 |
| 3668 | #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1 |
| 3669 | #define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4 |
| 3670 | #define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2 |
| 3671 | #define CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8 |
| 3672 | #define CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3 |
| 3673 | #define CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10 |
| 3674 | #define CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4 |
| 3675 | #define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20 |
| 3676 | #define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5 |
| 3677 | #define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40 |
| 3678 | #define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6 |
| 3679 | #define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80 |
| 3680 | #define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7 |
| 3681 | #define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100 |
| 3682 | #define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8 |
| 3683 | #define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200 |
| 3684 | #define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9 |
| 3685 | #define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400 |
| 3686 | #define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa |
| 3687 | #define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800 |
| 3688 | #define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb |
| 3689 | #define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000 |
| 3690 | #define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc |
| 3691 | #define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000 |
| 3692 | #define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd |
| 3693 | #define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000 |
| 3694 | #define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe |
| 3695 | #define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000 |
| 3696 | #define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf |
| 3697 | #define CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000 |
| 3698 | #define CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10 |
| 3699 | #define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000 |
| 3700 | #define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11 |
| 3701 | #define CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000 |
| 3702 | #define CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14 |
| 3703 | #define CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000 |
| 3704 | #define CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15 |
| 3705 | #define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000 |
| 3706 | #define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16 |
| 3707 | #define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000 |
| 3708 | #define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17 |
| 3709 | #define CPM_CONTROL__SPARE_REGS_MASK 0xff000000 |
| 3710 | #define CPM_CONTROL__SPARE_REGS__SHIFT 0x18 |
| 3711 | #define GSKT_CONTROL__GSKT_TxFifoBypass_MASK 0x1 |
| 3712 | #define GSKT_CONTROL__GSKT_TxFifoBypass__SHIFT 0x0 |
| 3713 | #define GSKT_CONTROL__GSKT_TxFifoDelay_MASK 0x2 |
| 3714 | #define GSKT_CONTROL__GSKT_TxFifoDelay__SHIFT 0x1 |
| 3715 | #define GSKT_CONTROL__GSKT_TxFifoDelay2_MASK 0x4 |
| 3716 | #define GSKT_CONTROL__GSKT_TxFifoDelay2__SHIFT 0x2 |
| 3717 | #define GSKT_CONTROL__GSKT_SpareRegs_MASK 0xf8 |
| 3718 | #define GSKT_CONTROL__GSKT_SpareRegs__SHIFT 0x3 |
| 3719 | #define LM_CONTROL__LoopbackSelect_MASK 0x1e |
| 3720 | #define LM_CONTROL__LoopbackSelect__SHIFT 0x1 |
| 3721 | #define LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20 |
| 3722 | #define LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5 |
| 3723 | #define LM_CONTROL__LoopbackHalfRate_MASK 0xc0 |
| 3724 | #define LM_CONTROL__LoopbackHalfRate__SHIFT 0x6 |
| 3725 | #define LM_CONTROL__LoopbackFifoPtr_MASK 0x700 |
| 3726 | #define LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8 |
| 3727 | #define LM_PCIETXMUX0__TXLANE0_MASK 0xff |
| 3728 | #define LM_PCIETXMUX0__TXLANE0__SHIFT 0x0 |
| 3729 | #define LM_PCIETXMUX0__TXLANE1_MASK 0xff00 |
| 3730 | #define LM_PCIETXMUX0__TXLANE1__SHIFT 0x8 |
| 3731 | #define LM_PCIETXMUX0__TXLANE2_MASK 0xff0000 |
| 3732 | #define LM_PCIETXMUX0__TXLANE2__SHIFT 0x10 |
| 3733 | #define LM_PCIETXMUX0__TXLANE3_MASK 0xff000000 |
| 3734 | #define LM_PCIETXMUX0__TXLANE3__SHIFT 0x18 |
| 3735 | #define LM_PCIETXMUX1__TXLANE4_MASK 0xff |
| 3736 | #define LM_PCIETXMUX1__TXLANE4__SHIFT 0x0 |
| 3737 | #define LM_PCIETXMUX1__TXLANE5_MASK 0xff00 |
| 3738 | #define LM_PCIETXMUX1__TXLANE5__SHIFT 0x8 |
| 3739 | #define LM_PCIETXMUX1__TXLANE6_MASK 0xff0000 |
| 3740 | #define LM_PCIETXMUX1__TXLANE6__SHIFT 0x10 |
| 3741 | #define LM_PCIETXMUX1__TXLANE7_MASK 0xff000000 |
| 3742 | #define LM_PCIETXMUX1__TXLANE7__SHIFT 0x18 |
| 3743 | #define LM_PCIETXMUX2__TXLANE8_MASK 0xff |
| 3744 | #define LM_PCIETXMUX2__TXLANE8__SHIFT 0x0 |
| 3745 | #define LM_PCIETXMUX2__TXLANE9_MASK 0xff00 |
| 3746 | #define LM_PCIETXMUX2__TXLANE9__SHIFT 0x8 |
| 3747 | #define LM_PCIETXMUX2__TXLANE10_MASK 0xff0000 |
| 3748 | #define LM_PCIETXMUX2__TXLANE10__SHIFT 0x10 |
| 3749 | #define LM_PCIETXMUX2__TXLANE11_MASK 0xff000000 |
| 3750 | #define LM_PCIETXMUX2__TXLANE11__SHIFT 0x18 |
| 3751 | #define LM_PCIETXMUX3__TXLANE12_MASK 0xff |
| 3752 | #define LM_PCIETXMUX3__TXLANE12__SHIFT 0x0 |
| 3753 | #define LM_PCIETXMUX3__TXLANE13_MASK 0xff00 |
| 3754 | #define LM_PCIETXMUX3__TXLANE13__SHIFT 0x8 |
| 3755 | #define LM_PCIETXMUX3__TXLANE14_MASK 0xff0000 |
| 3756 | #define LM_PCIETXMUX3__TXLANE14__SHIFT 0x10 |
| 3757 | #define LM_PCIETXMUX3__TXLANE15_MASK 0xff000000 |
| 3758 | #define LM_PCIETXMUX3__TXLANE15__SHIFT 0x18 |
| 3759 | #define LM_PCIERXMUX0__RXLANE0_MASK 0xff |
| 3760 | #define LM_PCIERXMUX0__RXLANE0__SHIFT 0x0 |
| 3761 | #define LM_PCIERXMUX0__RXLANE1_MASK 0xff00 |
| 3762 | #define LM_PCIERXMUX0__RXLANE1__SHIFT 0x8 |
| 3763 | #define LM_PCIERXMUX0__RXLANE2_MASK 0xff0000 |
| 3764 | #define LM_PCIERXMUX0__RXLANE2__SHIFT 0x10 |
| 3765 | #define LM_PCIERXMUX0__RXLANE3_MASK 0xff000000 |
| 3766 | #define LM_PCIERXMUX0__RXLANE3__SHIFT 0x18 |
| 3767 | #define LM_PCIERXMUX1__RXLANE4_MASK 0xff |
| 3768 | #define LM_PCIERXMUX1__RXLANE4__SHIFT 0x0 |
| 3769 | #define LM_PCIERXMUX1__RXLANE5_MASK 0xff00 |
| 3770 | #define LM_PCIERXMUX1__RXLANE5__SHIFT 0x8 |
| 3771 | #define LM_PCIERXMUX1__RXLANE6_MASK 0xff0000 |
| 3772 | #define LM_PCIERXMUX1__RXLANE6__SHIFT 0x10 |
| 3773 | #define LM_PCIERXMUX1__RXLANE7_MASK 0xff000000 |
| 3774 | #define LM_PCIERXMUX1__RXLANE7__SHIFT 0x18 |
| 3775 | #define LM_PCIERXMUX2__RXLANE8_MASK 0xff |
| 3776 | #define LM_PCIERXMUX2__RXLANE8__SHIFT 0x0 |
| 3777 | #define LM_PCIERXMUX2__RXLANE9_MASK 0xff00 |
| 3778 | #define LM_PCIERXMUX2__RXLANE9__SHIFT 0x8 |
| 3779 | #define LM_PCIERXMUX2__RXLANE10_MASK 0xff0000 |
| 3780 | #define LM_PCIERXMUX2__RXLANE10__SHIFT 0x10 |
| 3781 | #define LM_PCIERXMUX2__RXLANE11_MASK 0xff000000 |
| 3782 | #define LM_PCIERXMUX2__RXLANE11__SHIFT 0x18 |
| 3783 | #define LM_PCIERXMUX3__RXLANE12_MASK 0xff |
| 3784 | #define LM_PCIERXMUX3__RXLANE12__SHIFT 0x0 |
| 3785 | #define LM_PCIERXMUX3__RXLANE13_MASK 0xff00 |
| 3786 | #define LM_PCIERXMUX3__RXLANE13__SHIFT 0x8 |
| 3787 | #define LM_PCIERXMUX3__RXLANE14_MASK 0xff0000 |
| 3788 | #define LM_PCIERXMUX3__RXLANE14__SHIFT 0x10 |
| 3789 | #define LM_PCIERXMUX3__RXLANE15_MASK 0xff000000 |
| 3790 | #define LM_PCIERXMUX3__RXLANE15__SHIFT 0x18 |
| 3791 | #define LM_LANEENABLE__LANE_enable_MASK 0xffff |
| 3792 | #define LM_LANEENABLE__LANE_enable__SHIFT 0x0 |
| 3793 | #define LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff |
| 3794 | #define LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0 |
| 3795 | #define LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000 |
| 3796 | #define LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c |
| 3797 | #define LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000 |
| 3798 | #define LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d |
| 3799 | #define LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000 |
| 3800 | #define LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e |
| 3801 | #define LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000 |
| 3802 | #define LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f |
| 3803 | #define LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7 |
| 3804 | #define LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0 |
| 3805 | #define LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38 |
| 3806 | #define LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3 |
| 3807 | #define LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0 |
| 3808 | #define LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6 |
| 3809 | #define LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700 |
| 3810 | #define LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8 |
| 3811 | #define LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800 |
| 3812 | #define LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb |
| 3813 | #define LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000 |
| 3814 | #define LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe |
| 3815 | #define LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000 |
| 3816 | #define LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10 |
| 3817 | #define LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000 |
| 3818 | #define LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13 |
| 3819 | #define LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000 |
| 3820 | #define LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16 |
| 3821 | #define LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000 |
| 3822 | #define LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18 |
| 3823 | #define LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000 |
| 3824 | #define LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b |
| 3825 | #define LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000 |
| 3826 | #define LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e |
| 3827 | #define LM_POWERCONTROL1__LMTxEn0_MASK 0x1 |
| 3828 | #define LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0 |
| 3829 | #define LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2 |
| 3830 | #define LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1 |
| 3831 | #define LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c |
| 3832 | #define LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2 |
| 3833 | #define LM_POWERCONTROL1__LMSkipBit0_MASK 0x20 |
| 3834 | #define LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5 |
| 3835 | #define LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40 |
| 3836 | #define LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6 |
| 3837 | #define LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80 |
| 3838 | #define LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7 |
| 3839 | #define LM_POWERCONTROL1__LMDeemph0_MASK 0x100 |
| 3840 | #define LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8 |
| 3841 | #define LM_POWERCONTROL1__LMTxEn1_MASK 0x200 |
| 3842 | #define LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9 |
| 3843 | #define LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400 |
| 3844 | #define LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa |
| 3845 | #define LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800 |
| 3846 | #define LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb |
| 3847 | #define LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000 |
| 3848 | #define LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe |
| 3849 | #define LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000 |
| 3850 | #define LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf |
| 3851 | #define LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000 |
| 3852 | #define LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10 |
| 3853 | #define LM_POWERCONTROL1__LMDeemph1_MASK 0x20000 |
| 3854 | #define LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11 |
| 3855 | #define LM_POWERCONTROL1__LMTxEn2_MASK 0x40000 |
| 3856 | #define LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12 |
| 3857 | #define LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000 |
| 3858 | #define LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13 |
| 3859 | #define LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000 |
| 3860 | #define LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14 |
| 3861 | #define LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000 |
| 3862 | #define LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17 |
| 3863 | #define LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000 |
| 3864 | #define LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18 |
| 3865 | #define LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000 |
| 3866 | #define LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19 |
| 3867 | #define LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000 |
| 3868 | #define LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a |
| 3869 | #define LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000 |
| 3870 | #define LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b |
| 3871 | #define LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000 |
| 3872 | #define LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d |
| 3873 | #define LM_POWERCONTROL2__LMTxEn3_MASK 0x1 |
| 3874 | #define LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0 |
| 3875 | #define LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2 |
| 3876 | #define LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1 |
| 3877 | #define LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c |
| 3878 | #define LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2 |
| 3879 | #define LM_POWERCONTROL2__LMSkipBit3_MASK 0x20 |
| 3880 | #define LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5 |
| 3881 | #define LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40 |
| 3882 | #define LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6 |
| 3883 | #define LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80 |
| 3884 | #define LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7 |
| 3885 | #define LM_POWERCONTROL2__LMDeemph3_MASK 0x100 |
| 3886 | #define LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8 |
| 3887 | #define LM_POWERCONTROL2__TxCoeffID2_MASK 0x600 |
| 3888 | #define LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9 |
| 3889 | #define LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800 |
| 3890 | #define LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb |
| 3891 | #define LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000 |
| 3892 | #define LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd |
| 3893 | #define LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000 |
| 3894 | #define LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13 |
| 3895 | #define LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000 |
| 3896 | #define LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19 |
| 3897 | #define LM_POWERCONTROL3__TxCoeff3_MASK 0x3f |
| 3898 | #define LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0 |
| 3899 | #define LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0 |
| 3900 | #define LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6 |
| 3901 | #define LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000 |
| 3902 | #define LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc |
| 3903 | #define LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000 |
| 3904 | #define LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12 |
| 3905 | #define LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000 |
| 3906 | #define LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18 |
| 3907 | #define LM_POWERCONTROL4__LinkNum0_MASK 0x7 |
| 3908 | #define LM_POWERCONTROL4__LinkNum0__SHIFT 0x0 |
| 3909 | #define LM_POWERCONTROL4__LinkNum1_MASK 0x38 |
| 3910 | #define LM_POWERCONTROL4__LinkNum1__SHIFT 0x3 |
| 3911 | #define LM_POWERCONTROL4__LinkNum2_MASK 0x1c0 |
| 3912 | #define LM_POWERCONTROL4__LinkNum2__SHIFT 0x6 |
| 3913 | #define LM_POWERCONTROL4__LinkNum3_MASK 0xe00 |
| 3914 | #define LM_POWERCONTROL4__LinkNum3__SHIFT 0x9 |
| 3915 | #define LM_POWERCONTROL4__LaneNum0_MASK 0xf000 |
| 3916 | #define LM_POWERCONTROL4__LaneNum0__SHIFT 0xc |
| 3917 | #define LM_POWERCONTROL4__LaneNum1_MASK 0xf0000 |
| 3918 | #define LM_POWERCONTROL4__LaneNum1__SHIFT 0x10 |
| 3919 | #define LM_POWERCONTROL4__LaneNum2_MASK 0xf00000 |
| 3920 | #define LM_POWERCONTROL4__LaneNum2__SHIFT 0x14 |
| 3921 | #define LM_POWERCONTROL4__LaneNum3_MASK 0xf000000 |
| 3922 | #define LM_POWERCONTROL4__LaneNum3__SHIFT 0x18 |
| 3923 | #define LM_POWERCONTROL4__SpcMode0_MASK 0x10000000 |
| 3924 | #define LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c |
| 3925 | #define LM_POWERCONTROL4__SpcMode1_MASK 0x20000000 |
| 3926 | #define LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d |
| 3927 | #define LM_POWERCONTROL4__SpcMode2_MASK 0x40000000 |
| 3928 | #define LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e |
| 3929 | #define LM_POWERCONTROL4__SpcMode3_MASK 0x80000000 |
| 3930 | #define LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f |
| 3931 | #define PB0_GLB_CTRL_REG0__BACKUP_MASK 0xffff |
| 3932 | #define PB0_GLB_CTRL_REG0__BACKUP__SHIFT 0x0 |
| 3933 | #define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000 |
| 3934 | #define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10 |
| 3935 | #define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000 |
| 3936 | #define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14 |
| 3937 | #define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000 |
| 3938 | #define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17 |
| 3939 | #define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000 |
| 3940 | #define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18 |
| 3941 | #define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000 |
| 3942 | #define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19 |
| 3943 | #define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000 |
| 3944 | #define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a |
| 3945 | #define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000 |
| 3946 | #define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e |
| 3947 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1 |
| 3948 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0 |
| 3949 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e |
| 3950 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1 |
| 3951 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80 |
| 3952 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7 |
| 3953 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00 |
| 3954 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8 |
| 3955 | #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000 |
| 3956 | #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe |
| 3957 | #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000 |
| 3958 | #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf |
| 3959 | #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000 |
| 3960 | #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16 |
| 3961 | #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000 |
| 3962 | #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17 |
| 3963 | #define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000 |
| 3964 | #define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e |
| 3965 | #define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000 |
| 3966 | #define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f |
| 3967 | #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1 |
| 3968 | #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0 |
| 3969 | #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe |
| 3970 | #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1 |
| 3971 | #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100 |
| 3972 | #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8 |
| 3973 | #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00 |
| 3974 | #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9 |
| 3975 | #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000 |
| 3976 | #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10 |
| 3977 | #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000 |
| 3978 | #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11 |
| 3979 | #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000 |
| 3980 | #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18 |
| 3981 | #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000 |
| 3982 | #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19 |
| 3983 | #define PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f |
| 3984 | #define PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0 |
| 3985 | #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60 |
| 3986 | #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5 |
| 3987 | #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180 |
| 3988 | #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7 |
| 3989 | #define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600 |
| 3990 | #define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9 |
| 3991 | #define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800 |
| 3992 | #define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb |
| 3993 | #define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000 |
| 3994 | #define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc |
| 3995 | #define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000 |
| 3996 | #define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe |
| 3997 | #define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000 |
| 3998 | #define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12 |
| 3999 | #define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000 |
| 4000 | #define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15 |
| 4001 | #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000 |
| 4002 | #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16 |
| 4003 | #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000 |
| 4004 | #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17 |
| 4005 | #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000 |
| 4006 | #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b |
| 4007 | #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000 |
| 4008 | #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c |
| 4009 | #define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000 |
| 4010 | #define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f |
| 4011 | #define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff |
| 4012 | #define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0 |
| 4013 | #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000 |
| 4014 | #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10 |
| 4015 | #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000 |
| 4016 | #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12 |
| 4017 | #define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000 |
| 4018 | #define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16 |
| 4019 | #define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000 |
| 4020 | #define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a |
| 4021 | #define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000 |
| 4022 | #define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b |
| 4023 | #define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000 |
| 4024 | #define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c |
| 4025 | #define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff |
| 4026 | #define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0 |
| 4027 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3_MASK 0x1 |
| 4028 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3__SHIFT 0x0 |
| 4029 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK 0x2 |
| 4030 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7__SHIFT 0x1 |
| 4031 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11_MASK 0x4 |
| 4032 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT 0x2 |
| 4033 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15_MASK 0x8 |
| 4034 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15__SHIFT 0x3 |
| 4035 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT_MASK 0x10 |
| 4036 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT__SHIFT 0x4 |
| 4037 | #define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00 |
| 4038 | #define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8 |
| 4039 | #define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000 |
| 4040 | #define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc |
| 4041 | #define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000 |
| 4042 | #define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10 |
| 4043 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000 |
| 4044 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14 |
| 4045 | #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3_MASK 0x1 |
| 4046 | #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3__SHIFT 0x0 |
| 4047 | #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK 0x2 |
| 4048 | #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3__SHIFT 0x1 |
| 4049 | #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3_MASK 0x4 |
| 4050 | #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT 0x2 |
| 4051 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000 |
| 4052 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc |
| 4053 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000 |
| 4054 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd |
| 4055 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000 |
| 4056 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe |
| 4057 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000 |
| 4058 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf |
| 4059 | #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0_MASK 0x30000 |
| 4060 | #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0__SHIFT 0x10 |
| 4061 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000 |
| 4062 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12 |
| 4063 | #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1_MASK 0x300000 |
| 4064 | #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1__SHIFT 0x14 |
| 4065 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000 |
| 4066 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16 |
| 4067 | #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2_MASK 0x3000000 |
| 4068 | #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2__SHIFT 0x18 |
| 4069 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000 |
| 4070 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a |
| 4071 | #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3_MASK 0x30000000 |
| 4072 | #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3__SHIFT 0x1c |
| 4073 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000 |
| 4074 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e |
| 4075 | #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7_MASK 0x1 |
| 4076 | #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7__SHIFT 0x0 |
| 4077 | #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK 0x2 |
| 4078 | #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7__SHIFT 0x1 |
| 4079 | #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7_MASK 0x4 |
| 4080 | #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT 0x2 |
| 4081 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000 |
| 4082 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc |
| 4083 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000 |
| 4084 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd |
| 4085 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000 |
| 4086 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe |
| 4087 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000 |
| 4088 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf |
| 4089 | #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4_MASK 0x30000 |
| 4090 | #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4__SHIFT 0x10 |
| 4091 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000 |
| 4092 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12 |
| 4093 | #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5_MASK 0x300000 |
| 4094 | #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5__SHIFT 0x14 |
| 4095 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000 |
| 4096 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16 |
| 4097 | #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6_MASK 0x3000000 |
| 4098 | #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6__SHIFT 0x18 |
| 4099 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000 |
| 4100 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a |
| 4101 | #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7_MASK 0x30000000 |
| 4102 | #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7__SHIFT 0x1c |
| 4103 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000 |
| 4104 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e |
| 4105 | #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11_MASK 0x1 |
| 4106 | #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11__SHIFT 0x0 |
| 4107 | #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK 0x2 |
| 4108 | #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11__SHIFT 0x1 |
| 4109 | #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11_MASK 0x4 |
| 4110 | #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT 0x2 |
| 4111 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000 |
| 4112 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc |
| 4113 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000 |
| 4114 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd |
| 4115 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000 |
| 4116 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe |
| 4117 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000 |
| 4118 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf |
| 4119 | #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8_MASK 0x30000 |
| 4120 | #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8__SHIFT 0x10 |
| 4121 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000 |
| 4122 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12 |
| 4123 | #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9_MASK 0x300000 |
| 4124 | #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9__SHIFT 0x14 |
| 4125 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000 |
| 4126 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16 |
| 4127 | #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10_MASK 0x3000000 |
| 4128 | #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10__SHIFT 0x18 |
| 4129 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000 |
| 4130 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a |
| 4131 | #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11_MASK 0x30000000 |
| 4132 | #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11__SHIFT 0x1c |
| 4133 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000 |
| 4134 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e |
| 4135 | #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15_MASK 0x1 |
| 4136 | #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15__SHIFT 0x0 |
| 4137 | #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK 0x2 |
| 4138 | #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15__SHIFT 0x1 |
| 4139 | #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15_MASK 0x4 |
| 4140 | #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT 0x2 |
| 4141 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000 |
| 4142 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc |
| 4143 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000 |
| 4144 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd |
| 4145 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000 |
| 4146 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe |
| 4147 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000 |
| 4148 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf |
| 4149 | #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12_MASK 0x30000 |
| 4150 | #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12__SHIFT 0x10 |
| 4151 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000 |
| 4152 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12 |
| 4153 | #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13_MASK 0x300000 |
| 4154 | #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13__SHIFT 0x14 |
| 4155 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000 |
| 4156 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16 |
| 4157 | #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14_MASK 0x3000000 |
| 4158 | #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14__SHIFT 0x18 |
| 4159 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000 |
| 4160 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a |
| 4161 | #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15_MASK 0x30000000 |
| 4162 | #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15__SHIFT 0x1c |
| 4163 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000 |
| 4164 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e |
| 4165 | #define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff |
| 4166 | #define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0 |
| 4167 | #define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000 |
| 4168 | #define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10 |
| 4169 | #define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1 |
| 4170 | #define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0 |
| 4171 | #define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2 |
| 4172 | #define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1 |
| 4173 | #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4 |
| 4174 | #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2 |
| 4175 | #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8 |
| 4176 | #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3 |
| 4177 | #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000 |
| 4178 | #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf |
| 4179 | #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000 |
| 4180 | #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10 |
| 4181 | #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1 |
| 4182 | #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0 |
| 4183 | #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2 |
| 4184 | #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1 |
| 4185 | #define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN_MASK 0x4 |
| 4186 | #define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT 0x2 |
| 4187 | #define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL_MASK 0x8 |
| 4188 | #define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL__SHIFT 0x3 |
| 4189 | #define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN_MASK 0x10 |
| 4190 | #define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN__SHIFT 0x4 |
| 4191 | #define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL_MASK 0x20 |
| 4192 | #define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL__SHIFT 0x5 |
| 4193 | #define PB0_HW_DEBUG__HW_00_DEBUG_MASK 0x1 |
| 4194 | #define PB0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 |
| 4195 | #define PB0_HW_DEBUG__HW_01_DEBUG_MASK 0x2 |
| 4196 | #define PB0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 |
| 4197 | #define PB0_HW_DEBUG__HW_02_DEBUG_MASK 0x4 |
| 4198 | #define PB0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 |
| 4199 | #define PB0_HW_DEBUG__HW_03_DEBUG_MASK 0x8 |
| 4200 | #define PB0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 |
| 4201 | #define PB0_HW_DEBUG__HW_04_DEBUG_MASK 0x10 |
| 4202 | #define PB0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 |
| 4203 | #define PB0_HW_DEBUG__HW_05_DEBUG_MASK 0x20 |
| 4204 | #define PB0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 |
| 4205 | #define PB0_HW_DEBUG__HW_06_DEBUG_MASK 0x40 |
| 4206 | #define PB0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 |
| 4207 | #define PB0_HW_DEBUG__HW_07_DEBUG_MASK 0x80 |
| 4208 | #define PB0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 |
| 4209 | #define PB0_HW_DEBUG__HW_08_DEBUG_MASK 0x100 |
| 4210 | #define PB0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 |
| 4211 | #define PB0_HW_DEBUG__HW_09_DEBUG_MASK 0x200 |
| 4212 | #define PB0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 |
| 4213 | #define PB0_HW_DEBUG__HW_10_DEBUG_MASK 0x400 |
| 4214 | #define PB0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa |
| 4215 | #define PB0_HW_DEBUG__HW_11_DEBUG_MASK 0x800 |
| 4216 | #define PB0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb |
| 4217 | #define PB0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 |
| 4218 | #define PB0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc |
| 4219 | #define PB0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 |
| 4220 | #define PB0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd |
| 4221 | #define PB0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 |
| 4222 | #define PB0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe |
| 4223 | #define PB0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 |
| 4224 | #define PB0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf |
| 4225 | #define PB0_HW_DEBUG__HW_16_DEBUG_MASK 0x10000 |
| 4226 | #define PB0_HW_DEBUG__HW_16_DEBUG__SHIFT 0x10 |
| 4227 | #define PB0_HW_DEBUG__HW_17_DEBUG_MASK 0x20000 |
| 4228 | #define PB0_HW_DEBUG__HW_17_DEBUG__SHIFT 0x11 |
| 4229 | #define PB0_HW_DEBUG__HW_18_DEBUG_MASK 0x40000 |
| 4230 | #define PB0_HW_DEBUG__HW_18_DEBUG__SHIFT 0x12 |
| 4231 | #define PB0_HW_DEBUG__HW_19_DEBUG_MASK 0x80000 |
| 4232 | #define PB0_HW_DEBUG__HW_19_DEBUG__SHIFT 0x13 |
| 4233 | #define PB0_HW_DEBUG__HW_20_DEBUG_MASK 0x100000 |
| 4234 | #define PB0_HW_DEBUG__HW_20_DEBUG__SHIFT 0x14 |
| 4235 | #define PB0_HW_DEBUG__HW_21_DEBUG_MASK 0x200000 |
| 4236 | #define PB0_HW_DEBUG__HW_21_DEBUG__SHIFT 0x15 |
| 4237 | #define PB0_HW_DEBUG__HW_22_DEBUG_MASK 0x400000 |
| 4238 | #define PB0_HW_DEBUG__HW_22_DEBUG__SHIFT 0x16 |
| 4239 | #define PB0_HW_DEBUG__HW_23_DEBUG_MASK 0x800000 |
| 4240 | #define PB0_HW_DEBUG__HW_23_DEBUG__SHIFT 0x17 |
| 4241 | #define PB0_HW_DEBUG__HW_24_DEBUG_MASK 0x1000000 |
| 4242 | #define PB0_HW_DEBUG__HW_24_DEBUG__SHIFT 0x18 |
| 4243 | #define PB0_HW_DEBUG__HW_25_DEBUG_MASK 0x2000000 |
| 4244 | #define PB0_HW_DEBUG__HW_25_DEBUG__SHIFT 0x19 |
| 4245 | #define PB0_HW_DEBUG__HW_26_DEBUG_MASK 0x4000000 |
| 4246 | #define PB0_HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a |
| 4247 | #define PB0_HW_DEBUG__HW_27_DEBUG_MASK 0x8000000 |
| 4248 | #define PB0_HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b |
| 4249 | #define PB0_HW_DEBUG__HW_28_DEBUG_MASK 0x10000000 |
| 4250 | #define PB0_HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c |
| 4251 | #define PB0_HW_DEBUG__HW_29_DEBUG_MASK 0x20000000 |
| 4252 | #define PB0_HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d |
| 4253 | #define PB0_HW_DEBUG__HW_30_DEBUG_MASK 0x40000000 |
| 4254 | #define PB0_HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e |
| 4255 | #define PB0_HW_DEBUG__HW_31_DEBUG_MASK 0x80000000 |
| 4256 | #define PB0_HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f |
| 4257 | #define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2 |
| 4258 | #define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1 |
| 4259 | #define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4 |
| 4260 | #define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2 |
| 4261 | #define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8 |
| 4262 | #define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3 |
| 4263 | #define PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON_MASK 0x10 |
| 4264 | #define PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON__SHIFT 0x4 |
| 4265 | #define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60 |
| 4266 | #define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5 |
| 4267 | #define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80 |
| 4268 | #define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7 |
| 4269 | #define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000 |
| 4270 | #define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc |
| 4271 | #define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000 |
| 4272 | #define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd |
| 4273 | #define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000 |
| 4274 | #define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe |
| 4275 | #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000 |
| 4276 | #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf |
| 4277 | #define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000 |
| 4278 | #define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10 |
| 4279 | #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000 |
| 4280 | #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14 |
| 4281 | #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000 |
| 4282 | #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15 |
| 4283 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e |
| 4284 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1 |
| 4285 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0 |
| 4286 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5 |
| 4287 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00 |
| 4288 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9 |
| 4289 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000 |
| 4290 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe |
| 4291 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000 |
| 4292 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13 |
| 4293 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000 |
| 4294 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17 |
| 4295 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000 |
| 4296 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b |
| 4297 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000 |
| 4298 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c |
| 4299 | #define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000 |
| 4300 | #define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d |
| 4301 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000 |
| 4302 | #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e |
| 4303 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e |
| 4304 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1 |
| 4305 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20 |
| 4306 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5 |
| 4307 | #define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40 |
| 4308 | #define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6 |
| 4309 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80 |
| 4310 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7 |
| 4311 | #define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300 |
| 4312 | #define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8 |
| 4313 | #define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00 |
| 4314 | #define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa |
| 4315 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000 |
| 4316 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc |
| 4317 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000 |
| 4318 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10 |
| 4319 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000 |
| 4320 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14 |
| 4321 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000 |
| 4322 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18 |
| 4323 | #define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000 |
| 4324 | #define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c |
| 4325 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000 |
| 4326 | #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f |
| 4327 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2 |
| 4328 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1 |
| 4329 | #define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c |
| 4330 | #define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2 |
| 4331 | #define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60 |
| 4332 | #define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5 |
| 4333 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80 |
| 4334 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7 |
| 4335 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700 |
| 4336 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8 |
| 4337 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800 |
| 4338 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb |
| 4339 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000 |
| 4340 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf |
| 4341 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000 |
| 4342 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19 |
| 4343 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000 |
| 4344 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d |
| 4345 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000 |
| 4346 | #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f |
| 4347 | #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe |
| 4348 | #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1 |
| 4349 | #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0 |
| 4350 | #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4 |
| 4351 | #define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000 |
| 4352 | #define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd |
| 4353 | #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000 |
| 4354 | #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf |
| 4355 | #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000 |
| 4356 | #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10 |
| 4357 | #define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000 |
| 4358 | #define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18 |
| 4359 | #define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2 |
| 4360 | #define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1 |
| 4361 | #define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4 |
| 4362 | #define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2 |
| 4363 | #define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE_MASK 0x6 |
| 4364 | #define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE__SHIFT 0x1 |
| 4365 | #define PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE_MASK 0x18 |
| 4366 | #define PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE__SHIFT 0x3 |
| 4367 | #define PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER_MASK 0x60 |
| 4368 | #define PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER__SHIFT 0x5 |
| 4369 | #define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY_MASK 0x80 |
| 4370 | #define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY__SHIFT 0x7 |
| 4371 | #define PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE_MASK 0x300 |
| 4372 | #define PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE__SHIFT 0x8 |
| 4373 | #define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG_MASK 0x400 |
| 4374 | #define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG__SHIFT 0xa |
| 4375 | #define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT_MASK 0x1800 |
| 4376 | #define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT__SHIFT 0xb |
| 4377 | #define PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME_MASK 0x1c |
| 4378 | #define PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT 0x2 |
| 4379 | #define PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME_MASK 0x60 |
| 4380 | #define PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME__SHIFT 0x5 |
| 4381 | #define PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME_MASK 0x180 |
| 4382 | #define PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME__SHIFT 0x7 |
| 4383 | #define PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME_MASK 0x600 |
| 4384 | #define PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME__SHIFT 0x9 |
| 4385 | #define PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME_MASK 0x1800 |
| 4386 | #define PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME__SHIFT 0xb |
| 4387 | #define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0_MASK 0x10000000 |
| 4388 | #define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0__SHIFT 0x1c |
| 4389 | #define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1_MASK 0x20000000 |
| 4390 | #define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1__SHIFT 0x1d |
| 4391 | #define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR_MASK 0xc0000000 |
| 4392 | #define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR__SHIFT 0x1e |
| 4393 | #define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f |
| 4394 | #define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0 |
| 4395 | #define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80 |
| 4396 | #define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7 |
| 4397 | #define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00 |
| 4398 | #define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8 |
| 4399 | #define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000 |
| 4400 | #define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14 |
| 4401 | #define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000 |
| 4402 | #define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15 |
| 4403 | #define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000 |
| 4404 | #define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16 |
| 4405 | #define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000 |
| 4406 | #define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17 |
| 4407 | #define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000 |
| 4408 | #define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18 |
| 4409 | #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff |
| 4410 | #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0 |
| 4411 | #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100 |
| 4412 | #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8 |
| 4413 | #define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000 |
| 4414 | #define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10 |
| 4415 | #define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000 |
| 4416 | #define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11 |
| 4417 | #define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000 |
| 4418 | #define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14 |
| 4419 | #define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff |
| 4420 | #define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0 |
| 4421 | #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1 |
| 4422 | #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0 |
| 4423 | #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e |
| 4424 | #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1 |
| 4425 | #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff |
| 4426 | #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0 |
| 4427 | #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00 |
| 4428 | #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8 |
| 4429 | #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000 |
| 4430 | #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10 |
| 4431 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1 |
| 4432 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0 |
| 4433 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2 |
| 4434 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1 |
| 4435 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4 |
| 4436 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2 |
| 4437 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8 |
| 4438 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3 |
| 4439 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10 |
| 4440 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4 |
| 4441 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20 |
| 4442 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5 |
| 4443 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40 |
| 4444 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6 |
| 4445 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80 |
| 4446 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7 |
| 4447 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100 |
| 4448 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8 |
| 4449 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200 |
| 4450 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9 |
| 4451 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400 |
| 4452 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa |
| 4453 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800 |
| 4454 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb |
| 4455 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000 |
| 4456 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc |
| 4457 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000 |
| 4458 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd |
| 4459 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000 |
| 4460 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe |
| 4461 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN_MASK 0x8000 |
| 4462 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN__SHIFT 0xf |
| 4463 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN_MASK 0x10000 |
| 4464 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x10 |
| 4465 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN_MASK 0x20000 |
| 4466 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN__SHIFT 0x11 |
| 4467 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN_MASK 0x40000 |
| 4468 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x12 |
| 4469 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3 |
| 4470 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0 |
| 4471 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4 |
| 4472 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2 |
| 4473 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8 |
| 4474 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3 |
| 4475 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0 |
| 4476 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4 |
| 4477 | #define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800 |
| 4478 | #define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb |
| 4479 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff |
| 4480 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 |
| 4481 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100 |
| 4482 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8 |
| 4483 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00 |
| 4484 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9 |
| 4485 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000 |
| 4486 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc |
| 4487 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000 |
| 4488 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd |
| 4489 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000 |
| 4490 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe |
| 4491 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000 |
| 4492 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf |
| 4493 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000 |
| 4494 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c |
| 4495 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000 |
| 4496 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e |
| 4497 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000 |
| 4498 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f |
| 4499 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f |
| 4500 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0 |
| 4501 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20 |
| 4502 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5 |
| 4503 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0 |
| 4504 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6 |
| 4505 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100 |
| 4506 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8 |
| 4507 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200 |
| 4508 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9 |
| 4509 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400 |
| 4510 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa |
| 4511 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800 |
| 4512 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb |
| 4513 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000 |
| 4514 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc |
| 4515 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000 |
| 4516 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd |
| 4517 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000 |
| 4518 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe |
| 4519 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000 |
| 4520 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13 |
| 4521 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000 |
| 4522 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16 |
| 4523 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 4524 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 4525 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 |
| 4526 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 |
| 4527 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70 |
| 4528 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4 |
| 4529 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ_MASK 0x300 |
| 4530 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ__SHIFT 0x8 |
| 4531 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 4532 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 4533 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 |
| 4534 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 |
| 4535 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70 |
| 4536 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4 |
| 4537 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ_MASK 0x300 |
| 4538 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ__SHIFT 0x8 |
| 4539 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 4540 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 4541 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 |
| 4542 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 |
| 4543 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70 |
| 4544 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4 |
| 4545 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ_MASK 0x300 |
| 4546 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ__SHIFT 0x8 |
| 4547 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 4548 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 4549 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 |
| 4550 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 |
| 4551 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70 |
| 4552 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4 |
| 4553 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ_MASK 0x300 |
| 4554 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ__SHIFT 0x8 |
| 4555 | #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3 |
| 4556 | #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0 |
| 4557 | #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4 |
| 4558 | #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2 |
| 4559 | #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8 |
| 4560 | #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3 |
| 4561 | #define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10 |
| 4562 | #define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4 |
| 4563 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7 |
| 4564 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 |
| 4565 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8 |
| 4566 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3 |
| 4567 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70 |
| 4568 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4 |
| 4569 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80 |
| 4570 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7 |
| 4571 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100 |
| 4572 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8 |
| 4573 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200 |
| 4574 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9 |
| 4575 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00 |
| 4576 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa |
| 4577 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000 |
| 4578 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12 |
| 4579 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000 |
| 4580 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13 |
| 4581 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000 |
| 4582 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c |
| 4583 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000 |
| 4584 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d |
| 4585 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000 |
| 4586 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f |
| 4587 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7 |
| 4588 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0 |
| 4589 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8 |
| 4590 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3 |
| 4591 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10 |
| 4592 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4 |
| 4593 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20 |
| 4594 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5 |
| 4595 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40 |
| 4596 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6 |
| 4597 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80 |
| 4598 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7 |
| 4599 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100 |
| 4600 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8 |
| 4601 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200 |
| 4602 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9 |
| 4603 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000 |
| 4604 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe |
| 4605 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000 |
| 4606 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12 |
| 4607 | #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 4608 | #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 4609 | #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70 |
| 4610 | #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4 |
| 4611 | #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 4612 | #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 4613 | #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70 |
| 4614 | #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4 |
| 4615 | #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 4616 | #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 4617 | #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70 |
| 4618 | #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4 |
| 4619 | #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 4620 | #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 4621 | #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70 |
| 4622 | #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4 |
| 4623 | #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff |
| 4624 | #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0 |
| 4625 | #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00 |
| 4626 | #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa |
| 4627 | #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000 |
| 4628 | #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14 |
| 4629 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf |
| 4630 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0 |
| 4631 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0 |
| 4632 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4 |
| 4633 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00 |
| 4634 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8 |
| 4635 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000 |
| 4636 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc |
| 4637 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000 |
| 4638 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10 |
| 4639 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000 |
| 4640 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14 |
| 4641 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000 |
| 4642 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18 |
| 4643 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000 |
| 4644 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19 |
| 4645 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000 |
| 4646 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a |
| 4647 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000 |
| 4648 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b |
| 4649 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000 |
| 4650 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c |
| 4651 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000 |
| 4652 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d |
| 4653 | #define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000 |
| 4654 | #define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e |
| 4655 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000 |
| 4656 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc |
| 4657 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000 |
| 4658 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10 |
| 4659 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000 |
| 4660 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14 |
| 4661 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000 |
| 4662 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18 |
| 4663 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000 |
| 4664 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a |
| 4665 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000 |
| 4666 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c |
| 4667 | #define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000 |
| 4668 | #define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e |
| 4669 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1 |
| 4670 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0 |
| 4671 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2 |
| 4672 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1 |
| 4673 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4 |
| 4674 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2 |
| 4675 | #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1_MASK 0x18 |
| 4676 | #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1__SHIFT 0x3 |
| 4677 | #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2_MASK 0x60 |
| 4678 | #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2__SHIFT 0x5 |
| 4679 | #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3_MASK 0x180 |
| 4680 | #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3__SHIFT 0x7 |
| 4681 | #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE_MASK 0xe00 |
| 4682 | #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE__SHIFT 0x9 |
| 4683 | #define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1_MASK 0x3000 |
| 4684 | #define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1__SHIFT 0xc |
| 4685 | #define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2_MASK 0xc000 |
| 4686 | #define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2__SHIFT 0xe |
| 4687 | #define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3_MASK 0x30000 |
| 4688 | #define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3__SHIFT 0x10 |
| 4689 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000 |
| 4690 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14 |
| 4691 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000 |
| 4692 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18 |
| 4693 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000 |
| 4694 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c |
| 4695 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7 |
| 4696 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0 |
| 4697 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38 |
| 4698 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3 |
| 4699 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0 |
| 4700 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6 |
| 4701 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00 |
| 4702 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9 |
| 4703 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000 |
| 4704 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc |
| 4705 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000 |
| 4706 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf |
| 4707 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000 |
| 4708 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14 |
| 4709 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000 |
| 4710 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18 |
| 4711 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000 |
| 4712 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c |
| 4713 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f |
| 4714 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0 |
| 4715 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0 |
| 4716 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5 |
| 4717 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00 |
| 4718 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa |
| 4719 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000 |
| 4720 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf |
| 4721 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000 |
| 4722 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10 |
| 4723 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000 |
| 4724 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11 |
| 4725 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000 |
| 4726 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12 |
| 4727 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000 |
| 4728 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13 |
| 4729 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000 |
| 4730 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14 |
| 4731 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000 |
| 4732 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b |
| 4733 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000 |
| 4734 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c |
| 4735 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000 |
| 4736 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d |
| 4737 | #define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000 |
| 4738 | #define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f |
| 4739 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf |
| 4740 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0 |
| 4741 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0 |
| 4742 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4 |
| 4743 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00 |
| 4744 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8 |
| 4745 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000 |
| 4746 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc |
| 4747 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000 |
| 4748 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10 |
| 4749 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000 |
| 4750 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14 |
| 4751 | #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000 |
| 4752 | #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18 |
| 4753 | #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000 |
| 4754 | #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a |
| 4755 | #define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000 |
| 4756 | #define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b |
| 4757 | #define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000 |
| 4758 | #define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c |
| 4759 | #define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF_MASK 0x20000000 |
| 4760 | #define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF__SHIFT 0x1d |
| 4761 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf |
| 4762 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0 |
| 4763 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0 |
| 4764 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4 |
| 4765 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00 |
| 4766 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8 |
| 4767 | #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000 |
| 4768 | #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc |
| 4769 | #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000 |
| 4770 | #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd |
| 4771 | #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK_MASK 0x4000 |
| 4772 | #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK__SHIFT 0xe |
| 4773 | #define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3_MASK 0x10000 |
| 4774 | #define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3__SHIFT 0x10 |
| 4775 | #define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2_MASK 0x20000 |
| 4776 | #define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2__SHIFT 0x11 |
| 4777 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000 |
| 4778 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12 |
| 4779 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000 |
| 4780 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15 |
| 4781 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000 |
| 4782 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18 |
| 4783 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000 |
| 4784 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b |
| 4785 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000 |
| 4786 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c |
| 4787 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000 |
| 4788 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d |
| 4789 | #define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3 |
| 4790 | #define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0 |
| 4791 | #define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc |
| 4792 | #define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2 |
| 4793 | #define PB0_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN_MASK 0x10 |
| 4794 | #define PB0_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN__SHIFT 0x4 |
| 4795 | #define PB0_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY_MASK 0x20 |
| 4796 | #define PB0_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY__SHIFT 0x5 |
| 4797 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3_MASK 0x1 |
| 4798 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3__SHIFT 0x0 |
| 4799 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK 0x2 |
| 4800 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7__SHIFT 0x1 |
| 4801 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11_MASK 0x4 |
| 4802 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT 0x2 |
| 4803 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15_MASK 0x8 |
| 4804 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15__SHIFT 0x3 |
| 4805 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3_MASK 0x10 |
| 4806 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3__SHIFT 0x4 |
| 4807 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7_MASK 0x20 |
| 4808 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7__SHIFT 0x5 |
| 4809 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11_MASK 0x40 |
| 4810 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11__SHIFT 0x6 |
| 4811 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15_MASK 0x80 |
| 4812 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15__SHIFT 0x7 |
| 4813 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3_MASK 0x100 |
| 4814 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3__SHIFT 0x8 |
| 4815 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7_MASK 0x200 |
| 4816 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7__SHIFT 0x9 |
| 4817 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11_MASK 0x400 |
| 4818 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11__SHIFT 0xa |
| 4819 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15_MASK 0x800 |
| 4820 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15__SHIFT 0xb |
| 4821 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3_MASK 0x1000 |
| 4822 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3__SHIFT 0xc |
| 4823 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7_MASK 0x2000 |
| 4824 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7__SHIFT 0xd |
| 4825 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11_MASK 0x4000 |
| 4826 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11__SHIFT 0xe |
| 4827 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15_MASK 0x8000 |
| 4828 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15__SHIFT 0xf |
| 4829 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3_MASK 0x10000 |
| 4830 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3__SHIFT 0x10 |
| 4831 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7_MASK 0x20000 |
| 4832 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7__SHIFT 0x11 |
| 4833 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11_MASK 0x40000 |
| 4834 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11__SHIFT 0x12 |
| 4835 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15_MASK 0x80000 |
| 4836 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15__SHIFT 0x13 |
| 4837 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3_MASK 0x100000 |
| 4838 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3__SHIFT 0x14 |
| 4839 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7_MASK 0x200000 |
| 4840 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7__SHIFT 0x15 |
| 4841 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11_MASK 0x400000 |
| 4842 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11__SHIFT 0x16 |
| 4843 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15_MASK 0x800000 |
| 4844 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15__SHIFT 0x17 |
| 4845 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1 |
| 4846 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0 |
| 4847 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2 |
| 4848 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1 |
| 4849 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4 |
| 4850 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2 |
| 4851 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8 |
| 4852 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3 |
| 4853 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0 |
| 4854 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6 |
| 4855 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100 |
| 4856 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8 |
| 4857 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200 |
| 4858 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9 |
| 4859 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400 |
| 4860 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa |
| 4861 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800 |
| 4862 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb |
| 4863 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000 |
| 4864 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc |
| 4865 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000 |
| 4866 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd |
| 4867 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000 |
| 4868 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe |
| 4869 | #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000 |
| 4870 | #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf |
| 4871 | #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000 |
| 4872 | #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10 |
| 4873 | #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000 |
| 4874 | #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11 |
| 4875 | #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000 |
| 4876 | #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12 |
| 4877 | #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000 |
| 4878 | #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13 |
| 4879 | #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000 |
| 4880 | #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14 |
| 4881 | #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000 |
| 4882 | #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15 |
| 4883 | #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000 |
| 4884 | #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16 |
| 4885 | #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000 |
| 4886 | #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c |
| 4887 | #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000 |
| 4888 | #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d |
| 4889 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000 |
| 4890 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e |
| 4891 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000 |
| 4892 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f |
| 4893 | #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1 |
| 4894 | #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0 |
| 4895 | #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2 |
| 4896 | #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1 |
| 4897 | #define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff |
| 4898 | #define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0 |
| 4899 | #define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00 |
| 4900 | #define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa |
| 4901 | #define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000 |
| 4902 | #define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc |
| 4903 | #define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000 |
| 4904 | #define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd |
| 4905 | #define PB0_RX_LANE0_CTRL_REG0__RX_TERM_EN_0_MASK 0x4000 |
| 4906 | #define PB0_RX_LANE0_CTRL_REG0__RX_TERM_EN_0__SHIFT 0xe |
| 4907 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7 |
| 4908 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0 |
| 4909 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8 |
| 4910 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3 |
| 4911 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0_MASK 0x40 |
| 4912 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0__SHIFT 0x6 |
| 4913 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80 |
| 4914 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7 |
| 4915 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100 |
| 4916 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8 |
| 4917 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200 |
| 4918 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9 |
| 4919 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0_MASK 0x3fc00 |
| 4920 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0__SHIFT 0xa |
| 4921 | #define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff |
| 4922 | #define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0 |
| 4923 | #define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00 |
| 4924 | #define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa |
| 4925 | #define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000 |
| 4926 | #define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc |
| 4927 | #define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000 |
| 4928 | #define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd |
| 4929 | #define PB0_RX_LANE1_CTRL_REG0__RX_TERM_EN_1_MASK 0x4000 |
| 4930 | #define PB0_RX_LANE1_CTRL_REG0__RX_TERM_EN_1__SHIFT 0xe |
| 4931 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7 |
| 4932 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0 |
| 4933 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8 |
| 4934 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3 |
| 4935 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1_MASK 0x40 |
| 4936 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1__SHIFT 0x6 |
| 4937 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80 |
| 4938 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7 |
| 4939 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100 |
| 4940 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8 |
| 4941 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200 |
| 4942 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9 |
| 4943 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1_MASK 0x3fc00 |
| 4944 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1__SHIFT 0xa |
| 4945 | #define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff |
| 4946 | #define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0 |
| 4947 | #define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00 |
| 4948 | #define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa |
| 4949 | #define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000 |
| 4950 | #define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc |
| 4951 | #define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000 |
| 4952 | #define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd |
| 4953 | #define PB0_RX_LANE2_CTRL_REG0__RX_TERM_EN_2_MASK 0x4000 |
| 4954 | #define PB0_RX_LANE2_CTRL_REG0__RX_TERM_EN_2__SHIFT 0xe |
| 4955 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7 |
| 4956 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0 |
| 4957 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8 |
| 4958 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3 |
| 4959 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2_MASK 0x40 |
| 4960 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2__SHIFT 0x6 |
| 4961 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80 |
| 4962 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7 |
| 4963 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100 |
| 4964 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8 |
| 4965 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200 |
| 4966 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9 |
| 4967 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2_MASK 0x3fc00 |
| 4968 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2__SHIFT 0xa |
| 4969 | #define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff |
| 4970 | #define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0 |
| 4971 | #define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00 |
| 4972 | #define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa |
| 4973 | #define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000 |
| 4974 | #define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc |
| 4975 | #define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000 |
| 4976 | #define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd |
| 4977 | #define PB0_RX_LANE3_CTRL_REG0__RX_TERM_EN_3_MASK 0x4000 |
| 4978 | #define PB0_RX_LANE3_CTRL_REG0__RX_TERM_EN_3__SHIFT 0xe |
| 4979 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7 |
| 4980 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0 |
| 4981 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8 |
| 4982 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3 |
| 4983 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3_MASK 0x40 |
| 4984 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3__SHIFT 0x6 |
| 4985 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80 |
| 4986 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7 |
| 4987 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100 |
| 4988 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8 |
| 4989 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200 |
| 4990 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9 |
| 4991 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3_MASK 0x3fc00 |
| 4992 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3__SHIFT 0xa |
| 4993 | #define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff |
| 4994 | #define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0 |
| 4995 | #define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00 |
| 4996 | #define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa |
| 4997 | #define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000 |
| 4998 | #define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc |
| 4999 | #define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000 |
| 5000 | #define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd |
| 5001 | #define PB0_RX_LANE4_CTRL_REG0__RX_TERM_EN_4_MASK 0x4000 |
| 5002 | #define PB0_RX_LANE4_CTRL_REG0__RX_TERM_EN_4__SHIFT 0xe |
| 5003 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7 |
| 5004 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0 |
| 5005 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8 |
| 5006 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3 |
| 5007 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4_MASK 0x40 |
| 5008 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4__SHIFT 0x6 |
| 5009 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80 |
| 5010 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7 |
| 5011 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100 |
| 5012 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8 |
| 5013 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200 |
| 5014 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9 |
| 5015 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4_MASK 0x3fc00 |
| 5016 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4__SHIFT 0xa |
| 5017 | #define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff |
| 5018 | #define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0 |
| 5019 | #define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00 |
| 5020 | #define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa |
| 5021 | #define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000 |
| 5022 | #define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc |
| 5023 | #define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000 |
| 5024 | #define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd |
| 5025 | #define PB0_RX_LANE5_CTRL_REG0__RX_TERM_EN_5_MASK 0x4000 |
| 5026 | #define PB0_RX_LANE5_CTRL_REG0__RX_TERM_EN_5__SHIFT 0xe |
| 5027 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7 |
| 5028 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0 |
| 5029 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8 |
| 5030 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3 |
| 5031 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5_MASK 0x40 |
| 5032 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5__SHIFT 0x6 |
| 5033 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80 |
| 5034 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7 |
| 5035 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100 |
| 5036 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8 |
| 5037 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200 |
| 5038 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9 |
| 5039 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5_MASK 0x3fc00 |
| 5040 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5__SHIFT 0xa |
| 5041 | #define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff |
| 5042 | #define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0 |
| 5043 | #define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00 |
| 5044 | #define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa |
| 5045 | #define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000 |
| 5046 | #define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc |
| 5047 | #define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000 |
| 5048 | #define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd |
| 5049 | #define PB0_RX_LANE6_CTRL_REG0__RX_TERM_EN_6_MASK 0x4000 |
| 5050 | #define PB0_RX_LANE6_CTRL_REG0__RX_TERM_EN_6__SHIFT 0xe |
| 5051 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7 |
| 5052 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0 |
| 5053 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8 |
| 5054 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3 |
| 5055 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6_MASK 0x40 |
| 5056 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6__SHIFT 0x6 |
| 5057 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80 |
| 5058 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7 |
| 5059 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100 |
| 5060 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8 |
| 5061 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200 |
| 5062 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9 |
| 5063 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6_MASK 0x3fc00 |
| 5064 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6__SHIFT 0xa |
| 5065 | #define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff |
| 5066 | #define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0 |
| 5067 | #define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00 |
| 5068 | #define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa |
| 5069 | #define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000 |
| 5070 | #define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc |
| 5071 | #define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000 |
| 5072 | #define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd |
| 5073 | #define PB0_RX_LANE7_CTRL_REG0__RX_TERM_EN_7_MASK 0x4000 |
| 5074 | #define PB0_RX_LANE7_CTRL_REG0__RX_TERM_EN_7__SHIFT 0xe |
| 5075 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7 |
| 5076 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0 |
| 5077 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8 |
| 5078 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3 |
| 5079 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7_MASK 0x40 |
| 5080 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7__SHIFT 0x6 |
| 5081 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80 |
| 5082 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7 |
| 5083 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100 |
| 5084 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8 |
| 5085 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200 |
| 5086 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9 |
| 5087 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7_MASK 0x3fc00 |
| 5088 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7__SHIFT 0xa |
| 5089 | #define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff |
| 5090 | #define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0 |
| 5091 | #define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00 |
| 5092 | #define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa |
| 5093 | #define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000 |
| 5094 | #define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc |
| 5095 | #define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000 |
| 5096 | #define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd |
| 5097 | #define PB0_RX_LANE8_CTRL_REG0__RX_TERM_EN_8_MASK 0x4000 |
| 5098 | #define PB0_RX_LANE8_CTRL_REG0__RX_TERM_EN_8__SHIFT 0xe |
| 5099 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7 |
| 5100 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0 |
| 5101 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8 |
| 5102 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3 |
| 5103 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8_MASK 0x40 |
| 5104 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8__SHIFT 0x6 |
| 5105 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80 |
| 5106 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7 |
| 5107 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100 |
| 5108 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8 |
| 5109 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200 |
| 5110 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9 |
| 5111 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8_MASK 0x3fc00 |
| 5112 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8__SHIFT 0xa |
| 5113 | #define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff |
| 5114 | #define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0 |
| 5115 | #define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00 |
| 5116 | #define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa |
| 5117 | #define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000 |
| 5118 | #define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc |
| 5119 | #define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000 |
| 5120 | #define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd |
| 5121 | #define PB0_RX_LANE9_CTRL_REG0__RX_TERM_EN_9_MASK 0x4000 |
| 5122 | #define PB0_RX_LANE9_CTRL_REG0__RX_TERM_EN_9__SHIFT 0xe |
| 5123 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7 |
| 5124 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0 |
| 5125 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8 |
| 5126 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3 |
| 5127 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9_MASK 0x40 |
| 5128 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9__SHIFT 0x6 |
| 5129 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80 |
| 5130 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7 |
| 5131 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100 |
| 5132 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8 |
| 5133 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200 |
| 5134 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9 |
| 5135 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9_MASK 0x3fc00 |
| 5136 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9__SHIFT 0xa |
| 5137 | #define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff |
| 5138 | #define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0 |
| 5139 | #define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00 |
| 5140 | #define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa |
| 5141 | #define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000 |
| 5142 | #define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc |
| 5143 | #define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000 |
| 5144 | #define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd |
| 5145 | #define PB0_RX_LANE10_CTRL_REG0__RX_TERM_EN_10_MASK 0x4000 |
| 5146 | #define PB0_RX_LANE10_CTRL_REG0__RX_TERM_EN_10__SHIFT 0xe |
| 5147 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7 |
| 5148 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0 |
| 5149 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8 |
| 5150 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3 |
| 5151 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10_MASK 0x40 |
| 5152 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10__SHIFT 0x6 |
| 5153 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80 |
| 5154 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7 |
| 5155 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100 |
| 5156 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8 |
| 5157 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200 |
| 5158 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9 |
| 5159 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10_MASK 0x3fc00 |
| 5160 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10__SHIFT 0xa |
| 5161 | #define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff |
| 5162 | #define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0 |
| 5163 | #define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00 |
| 5164 | #define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa |
| 5165 | #define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000 |
| 5166 | #define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc |
| 5167 | #define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000 |
| 5168 | #define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd |
| 5169 | #define PB0_RX_LANE11_CTRL_REG0__RX_TERM_EN_11_MASK 0x4000 |
| 5170 | #define PB0_RX_LANE11_CTRL_REG0__RX_TERM_EN_11__SHIFT 0xe |
| 5171 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7 |
| 5172 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0 |
| 5173 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8 |
| 5174 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3 |
| 5175 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11_MASK 0x40 |
| 5176 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11__SHIFT 0x6 |
| 5177 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80 |
| 5178 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7 |
| 5179 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100 |
| 5180 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8 |
| 5181 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200 |
| 5182 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9 |
| 5183 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11_MASK 0x3fc00 |
| 5184 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11__SHIFT 0xa |
| 5185 | #define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff |
| 5186 | #define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0 |
| 5187 | #define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00 |
| 5188 | #define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa |
| 5189 | #define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000 |
| 5190 | #define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc |
| 5191 | #define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000 |
| 5192 | #define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd |
| 5193 | #define PB0_RX_LANE12_CTRL_REG0__RX_TERM_EN_12_MASK 0x4000 |
| 5194 | #define PB0_RX_LANE12_CTRL_REG0__RX_TERM_EN_12__SHIFT 0xe |
| 5195 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7 |
| 5196 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0 |
| 5197 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8 |
| 5198 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3 |
| 5199 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12_MASK 0x40 |
| 5200 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12__SHIFT 0x6 |
| 5201 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80 |
| 5202 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7 |
| 5203 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100 |
| 5204 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8 |
| 5205 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200 |
| 5206 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9 |
| 5207 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12_MASK 0x3fc00 |
| 5208 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12__SHIFT 0xa |
| 5209 | #define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff |
| 5210 | #define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0 |
| 5211 | #define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00 |
| 5212 | #define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa |
| 5213 | #define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000 |
| 5214 | #define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc |
| 5215 | #define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000 |
| 5216 | #define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd |
| 5217 | #define PB0_RX_LANE13_CTRL_REG0__RX_TERM_EN_13_MASK 0x4000 |
| 5218 | #define PB0_RX_LANE13_CTRL_REG0__RX_TERM_EN_13__SHIFT 0xe |
| 5219 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7 |
| 5220 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0 |
| 5221 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8 |
| 5222 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3 |
| 5223 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13_MASK 0x40 |
| 5224 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13__SHIFT 0x6 |
| 5225 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80 |
| 5226 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7 |
| 5227 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100 |
| 5228 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8 |
| 5229 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200 |
| 5230 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9 |
| 5231 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13_MASK 0x3fc00 |
| 5232 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13__SHIFT 0xa |
| 5233 | #define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff |
| 5234 | #define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0 |
| 5235 | #define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00 |
| 5236 | #define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa |
| 5237 | #define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000 |
| 5238 | #define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc |
| 5239 | #define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000 |
| 5240 | #define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd |
| 5241 | #define PB0_RX_LANE14_CTRL_REG0__RX_TERM_EN_14_MASK 0x4000 |
| 5242 | #define PB0_RX_LANE14_CTRL_REG0__RX_TERM_EN_14__SHIFT 0xe |
| 5243 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7 |
| 5244 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0 |
| 5245 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8 |
| 5246 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3 |
| 5247 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14_MASK 0x40 |
| 5248 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14__SHIFT 0x6 |
| 5249 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80 |
| 5250 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7 |
| 5251 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100 |
| 5252 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8 |
| 5253 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200 |
| 5254 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9 |
| 5255 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14_MASK 0x3fc00 |
| 5256 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14__SHIFT 0xa |
| 5257 | #define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff |
| 5258 | #define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0 |
| 5259 | #define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00 |
| 5260 | #define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa |
| 5261 | #define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000 |
| 5262 | #define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc |
| 5263 | #define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000 |
| 5264 | #define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd |
| 5265 | #define PB0_RX_LANE15_CTRL_REG0__RX_TERM_EN_15_MASK 0x4000 |
| 5266 | #define PB0_RX_LANE15_CTRL_REG0__RX_TERM_EN_15__SHIFT 0xe |
| 5267 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7 |
| 5268 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0 |
| 5269 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8 |
| 5270 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3 |
| 5271 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15_MASK 0x40 |
| 5272 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15__SHIFT 0x6 |
| 5273 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80 |
| 5274 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7 |
| 5275 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100 |
| 5276 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8 |
| 5277 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200 |
| 5278 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9 |
| 5279 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15_MASK 0x3fc00 |
| 5280 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15__SHIFT 0xa |
| 5281 | #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7 |
| 5282 | #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0 |
| 5283 | #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38 |
| 5284 | #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3 |
| 5285 | #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700 |
| 5286 | #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8 |
| 5287 | #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800 |
| 5288 | #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb |
| 5289 | #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000 |
| 5290 | #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe |
| 5291 | #define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000 |
| 5292 | #define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11 |
| 5293 | #define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000 |
| 5294 | #define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13 |
| 5295 | #define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000 |
| 5296 | #define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14 |
| 5297 | #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000 |
| 5298 | #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15 |
| 5299 | #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000 |
| 5300 | #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16 |
| 5301 | #define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000 |
| 5302 | #define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17 |
| 5303 | #define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4_MASK 0x1000000 |
| 5304 | #define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4__SHIFT 0x18 |
| 5305 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1 |
| 5306 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0 |
| 5307 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2 |
| 5308 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1 |
| 5309 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4 |
| 5310 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2 |
| 5311 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8 |
| 5312 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3 |
| 5313 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10 |
| 5314 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4 |
| 5315 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20 |
| 5316 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5 |
| 5317 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40 |
| 5318 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6 |
| 5319 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80 |
| 5320 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7 |
| 5321 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100 |
| 5322 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8 |
| 5323 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200 |
| 5324 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9 |
| 5325 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400 |
| 5326 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa |
| 5327 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800 |
| 5328 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb |
| 5329 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000 |
| 5330 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc |
| 5331 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000 |
| 5332 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd |
| 5333 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000 |
| 5334 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe |
| 5335 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000 |
| 5336 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf |
| 5337 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000 |
| 5338 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10 |
| 5339 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000 |
| 5340 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11 |
| 5341 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000 |
| 5342 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12 |
| 5343 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000 |
| 5344 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13 |
| 5345 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000 |
| 5346 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14 |
| 5347 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000 |
| 5348 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15 |
| 5349 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000 |
| 5350 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16 |
| 5351 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000 |
| 5352 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17 |
| 5353 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000 |
| 5354 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18 |
| 5355 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000 |
| 5356 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19 |
| 5357 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000 |
| 5358 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a |
| 5359 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000 |
| 5360 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b |
| 5361 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000 |
| 5362 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c |
| 5363 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000 |
| 5364 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d |
| 5365 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000 |
| 5366 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e |
| 5367 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3_MASK 0x1 |
| 5368 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3__SHIFT 0x0 |
| 5369 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK 0x2 |
| 5370 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7__SHIFT 0x1 |
| 5371 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11_MASK 0x4 |
| 5372 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT 0x2 |
| 5373 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15_MASK 0x8 |
| 5374 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15__SHIFT 0x3 |
| 5375 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3_MASK 0x100 |
| 5376 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3__SHIFT 0x8 |
| 5377 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7_MASK 0x200 |
| 5378 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7__SHIFT 0x9 |
| 5379 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11_MASK 0x400 |
| 5380 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11__SHIFT 0xa |
| 5381 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15_MASK 0x800 |
| 5382 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15__SHIFT 0xb |
| 5383 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3_MASK 0x1000 |
| 5384 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3__SHIFT 0xc |
| 5385 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7_MASK 0x2000 |
| 5386 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7__SHIFT 0xd |
| 5387 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11_MASK 0x4000 |
| 5388 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11__SHIFT 0xe |
| 5389 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15_MASK 0x8000 |
| 5390 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15__SHIFT 0xf |
| 5391 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1 |
| 5392 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0 |
| 5393 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2 |
| 5394 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1 |
| 5395 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4 |
| 5396 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2 |
| 5397 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8 |
| 5398 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3 |
| 5399 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10 |
| 5400 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4 |
| 5401 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20 |
| 5402 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5 |
| 5403 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40 |
| 5404 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6 |
| 5405 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80 |
| 5406 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7 |
| 5407 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100 |
| 5408 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8 |
| 5409 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200 |
| 5410 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9 |
| 5411 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400 |
| 5412 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa |
| 5413 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800 |
| 5414 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb |
| 5415 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000 |
| 5416 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc |
| 5417 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000 |
| 5418 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd |
| 5419 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000 |
| 5420 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe |
| 5421 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000 |
| 5422 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf |
| 5423 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000 |
| 5424 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10 |
| 5425 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000 |
| 5426 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11 |
| 5427 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000 |
| 5428 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12 |
| 5429 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000 |
| 5430 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13 |
| 5431 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000 |
| 5432 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14 |
| 5433 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000 |
| 5434 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15 |
| 5435 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000 |
| 5436 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16 |
| 5437 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000 |
| 5438 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17 |
| 5439 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000 |
| 5440 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18 |
| 5441 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000 |
| 5442 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19 |
| 5443 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000 |
| 5444 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a |
| 5445 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000 |
| 5446 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b |
| 5447 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000 |
| 5448 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c |
| 5449 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000 |
| 5450 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d |
| 5451 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000 |
| 5452 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e |
| 5453 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000 |
| 5454 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f |
| 5455 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1 |
| 5456 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0 |
| 5457 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2 |
| 5458 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1 |
| 5459 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4 |
| 5460 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2 |
| 5461 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8 |
| 5462 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3 |
| 5463 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10 |
| 5464 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4 |
| 5465 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20 |
| 5466 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5 |
| 5467 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40 |
| 5468 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6 |
| 5469 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80 |
| 5470 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7 |
| 5471 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100 |
| 5472 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8 |
| 5473 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200 |
| 5474 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9 |
| 5475 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400 |
| 5476 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa |
| 5477 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800 |
| 5478 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb |
| 5479 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000 |
| 5480 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc |
| 5481 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000 |
| 5482 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd |
| 5483 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000 |
| 5484 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe |
| 5485 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000 |
| 5486 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf |
| 5487 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000 |
| 5488 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10 |
| 5489 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000 |
| 5490 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11 |
| 5491 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000 |
| 5492 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12 |
| 5493 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000 |
| 5494 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13 |
| 5495 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000 |
| 5496 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14 |
| 5497 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000 |
| 5498 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15 |
| 5499 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000 |
| 5500 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16 |
| 5501 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000 |
| 5502 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17 |
| 5503 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000 |
| 5504 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18 |
| 5505 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000 |
| 5506 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19 |
| 5507 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000 |
| 5508 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a |
| 5509 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000 |
| 5510 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b |
| 5511 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000 |
| 5512 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c |
| 5513 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000 |
| 5514 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d |
| 5515 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000 |
| 5516 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e |
| 5517 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000 |
| 5518 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f |
| 5519 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1 |
| 5520 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0 |
| 5521 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2 |
| 5522 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1 |
| 5523 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4 |
| 5524 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2 |
| 5525 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8 |
| 5526 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3 |
| 5527 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10 |
| 5528 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4 |
| 5529 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20 |
| 5530 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5 |
| 5531 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40 |
| 5532 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6 |
| 5533 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80 |
| 5534 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7 |
| 5535 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100 |
| 5536 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8 |
| 5537 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200 |
| 5538 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9 |
| 5539 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400 |
| 5540 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa |
| 5541 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800 |
| 5542 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb |
| 5543 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000 |
| 5544 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc |
| 5545 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000 |
| 5546 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd |
| 5547 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000 |
| 5548 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe |
| 5549 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000 |
| 5550 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf |
| 5551 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000 |
| 5552 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10 |
| 5553 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000 |
| 5554 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11 |
| 5555 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000 |
| 5556 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12 |
| 5557 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000 |
| 5558 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13 |
| 5559 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000 |
| 5560 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14 |
| 5561 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000 |
| 5562 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15 |
| 5563 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000 |
| 5564 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16 |
| 5565 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000 |
| 5566 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17 |
| 5567 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000 |
| 5568 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18 |
| 5569 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000 |
| 5570 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19 |
| 5571 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000 |
| 5572 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a |
| 5573 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000 |
| 5574 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b |
| 5575 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000 |
| 5576 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c |
| 5577 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000 |
| 5578 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d |
| 5579 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000 |
| 5580 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e |
| 5581 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000 |
| 5582 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f |
| 5583 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1 |
| 5584 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0 |
| 5585 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2 |
| 5586 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1 |
| 5587 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4 |
| 5588 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2 |
| 5589 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8 |
| 5590 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3 |
| 5591 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10 |
| 5592 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4 |
| 5593 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20 |
| 5594 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5 |
| 5595 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40 |
| 5596 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6 |
| 5597 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80 |
| 5598 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7 |
| 5599 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100 |
| 5600 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8 |
| 5601 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200 |
| 5602 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9 |
| 5603 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400 |
| 5604 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa |
| 5605 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800 |
| 5606 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb |
| 5607 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000 |
| 5608 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc |
| 5609 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000 |
| 5610 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd |
| 5611 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7 |
| 5612 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0 |
| 5613 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8 |
| 5614 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3 |
| 5615 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0 |
| 5616 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4 |
| 5617 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100 |
| 5618 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8 |
| 5619 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00 |
| 5620 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9 |
| 5621 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000 |
| 5622 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd |
| 5623 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000 |
| 5624 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe |
| 5625 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000 |
| 5626 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13 |
| 5627 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000 |
| 5628 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14 |
| 5629 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000 |
| 5630 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19 |
| 5631 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000 |
| 5632 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a |
| 5633 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000 |
| 5634 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e |
| 5635 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf |
| 5636 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0 |
| 5637 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10 |
| 5638 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4 |
| 5639 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20 |
| 5640 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5 |
| 5641 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40 |
| 5642 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6 |
| 5643 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80 |
| 5644 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7 |
| 5645 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100 |
| 5646 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8 |
| 5647 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200 |
| 5648 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9 |
| 5649 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400 |
| 5650 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa |
| 5651 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800 |
| 5652 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb |
| 5653 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000 |
| 5654 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc |
| 5655 | #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000 |
| 5656 | #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd |
| 5657 | #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000 |
| 5658 | #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe |
| 5659 | #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000 |
| 5660 | #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf |
| 5661 | #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000 |
| 5662 | #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19 |
| 5663 | #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000 |
| 5664 | #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a |
| 5665 | #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000 |
| 5666 | #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b |
| 5667 | #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000 |
| 5668 | #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c |
| 5669 | #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000 |
| 5670 | #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d |
| 5671 | #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000 |
| 5672 | #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e |
| 5673 | #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000 |
| 5674 | #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f |
| 5675 | #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1 |
| 5676 | #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0 |
| 5677 | #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2 |
| 5678 | #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1 |
| 5679 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4 |
| 5680 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2 |
| 5681 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8 |
| 5682 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3 |
| 5683 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10 |
| 5684 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4 |
| 5685 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20 |
| 5686 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5 |
| 5687 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40 |
| 5688 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6 |
| 5689 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80 |
| 5690 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7 |
| 5691 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100 |
| 5692 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8 |
| 5693 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200 |
| 5694 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9 |
| 5695 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400 |
| 5696 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa |
| 5697 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800 |
| 5698 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb |
| 5699 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000 |
| 5700 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc |
| 5701 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000 |
| 5702 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10 |
| 5703 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000 |
| 5704 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14 |
| 5705 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000 |
| 5706 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19 |
| 5707 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf |
| 5708 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0 |
| 5709 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0 |
| 5710 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4 |
| 5711 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100 |
| 5712 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8 |
| 5713 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200 |
| 5714 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9 |
| 5715 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00 |
| 5716 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa |
| 5717 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000 |
| 5718 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe |
| 5719 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000 |
| 5720 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12 |
| 5721 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000 |
| 5722 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17 |
| 5723 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000 |
| 5724 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c |
| 5725 | #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf |
| 5726 | #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0 |
| 5727 | #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10 |
| 5728 | #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4 |
| 5729 | #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20 |
| 5730 | #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5 |
| 5731 | #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1 |
| 5732 | #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0 |
| 5733 | #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2 |
| 5734 | #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1 |
| 5735 | #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4 |
| 5736 | #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2 |
| 5737 | #define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8 |
| 5738 | #define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3 |
| 5739 | #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1 |
| 5740 | #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0 |
| 5741 | #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2 |
| 5742 | #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1 |
| 5743 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4 |
| 5744 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2 |
| 5745 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8 |
| 5746 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3 |
| 5747 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10 |
| 5748 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4 |
| 5749 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20 |
| 5750 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5 |
| 5751 | #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40 |
| 5752 | #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6 |
| 5753 | #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80 |
| 5754 | #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7 |
| 5755 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7 |
| 5756 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0 |
| 5757 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70 |
| 5758 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4 |
| 5759 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80 |
| 5760 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7 |
| 5761 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300 |
| 5762 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8 |
| 5763 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00 |
| 5764 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa |
| 5765 | #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1 |
| 5766 | #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0 |
| 5767 | #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2 |
| 5768 | #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1 |
| 5769 | #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4 |
| 5770 | #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2 |
| 5771 | #define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8 |
| 5772 | #define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3 |
| 5773 | #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1 |
| 5774 | #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0 |
| 5775 | #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2 |
| 5776 | #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1 |
| 5777 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4 |
| 5778 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2 |
| 5779 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8 |
| 5780 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3 |
| 5781 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10 |
| 5782 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4 |
| 5783 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20 |
| 5784 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5 |
| 5785 | #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40 |
| 5786 | #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6 |
| 5787 | #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80 |
| 5788 | #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7 |
| 5789 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7 |
| 5790 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0 |
| 5791 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70 |
| 5792 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4 |
| 5793 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80 |
| 5794 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7 |
| 5795 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300 |
| 5796 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8 |
| 5797 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00 |
| 5798 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa |
| 5799 | #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1 |
| 5800 | #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0 |
| 5801 | #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2 |
| 5802 | #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1 |
| 5803 | #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4 |
| 5804 | #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2 |
| 5805 | #define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8 |
| 5806 | #define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3 |
| 5807 | #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1 |
| 5808 | #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0 |
| 5809 | #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2 |
| 5810 | #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1 |
| 5811 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4 |
| 5812 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2 |
| 5813 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8 |
| 5814 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3 |
| 5815 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10 |
| 5816 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4 |
| 5817 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20 |
| 5818 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5 |
| 5819 | #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40 |
| 5820 | #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6 |
| 5821 | #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80 |
| 5822 | #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7 |
| 5823 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7 |
| 5824 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0 |
| 5825 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70 |
| 5826 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4 |
| 5827 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80 |
| 5828 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7 |
| 5829 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300 |
| 5830 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8 |
| 5831 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00 |
| 5832 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa |
| 5833 | #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1 |
| 5834 | #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0 |
| 5835 | #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2 |
| 5836 | #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1 |
| 5837 | #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4 |
| 5838 | #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2 |
| 5839 | #define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8 |
| 5840 | #define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3 |
| 5841 | #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1 |
| 5842 | #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0 |
| 5843 | #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2 |
| 5844 | #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1 |
| 5845 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4 |
| 5846 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2 |
| 5847 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8 |
| 5848 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3 |
| 5849 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10 |
| 5850 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4 |
| 5851 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20 |
| 5852 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5 |
| 5853 | #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40 |
| 5854 | #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6 |
| 5855 | #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80 |
| 5856 | #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7 |
| 5857 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7 |
| 5858 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0 |
| 5859 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70 |
| 5860 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4 |
| 5861 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80 |
| 5862 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7 |
| 5863 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300 |
| 5864 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8 |
| 5865 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00 |
| 5866 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa |
| 5867 | #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1 |
| 5868 | #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0 |
| 5869 | #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2 |
| 5870 | #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1 |
| 5871 | #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4 |
| 5872 | #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2 |
| 5873 | #define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8 |
| 5874 | #define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3 |
| 5875 | #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1 |
| 5876 | #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0 |
| 5877 | #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2 |
| 5878 | #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1 |
| 5879 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4 |
| 5880 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2 |
| 5881 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8 |
| 5882 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3 |
| 5883 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10 |
| 5884 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4 |
| 5885 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20 |
| 5886 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5 |
| 5887 | #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40 |
| 5888 | #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6 |
| 5889 | #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80 |
| 5890 | #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7 |
| 5891 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7 |
| 5892 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0 |
| 5893 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70 |
| 5894 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4 |
| 5895 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80 |
| 5896 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7 |
| 5897 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300 |
| 5898 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8 |
| 5899 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00 |
| 5900 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa |
| 5901 | #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1 |
| 5902 | #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0 |
| 5903 | #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2 |
| 5904 | #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1 |
| 5905 | #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4 |
| 5906 | #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2 |
| 5907 | #define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8 |
| 5908 | #define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3 |
| 5909 | #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1 |
| 5910 | #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0 |
| 5911 | #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2 |
| 5912 | #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1 |
| 5913 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4 |
| 5914 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2 |
| 5915 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8 |
| 5916 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3 |
| 5917 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10 |
| 5918 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4 |
| 5919 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20 |
| 5920 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5 |
| 5921 | #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40 |
| 5922 | #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6 |
| 5923 | #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80 |
| 5924 | #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7 |
| 5925 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7 |
| 5926 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0 |
| 5927 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70 |
| 5928 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4 |
| 5929 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80 |
| 5930 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7 |
| 5931 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300 |
| 5932 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8 |
| 5933 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00 |
| 5934 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa |
| 5935 | #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1 |
| 5936 | #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0 |
| 5937 | #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2 |
| 5938 | #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1 |
| 5939 | #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4 |
| 5940 | #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2 |
| 5941 | #define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8 |
| 5942 | #define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3 |
| 5943 | #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1 |
| 5944 | #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0 |
| 5945 | #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2 |
| 5946 | #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1 |
| 5947 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4 |
| 5948 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2 |
| 5949 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8 |
| 5950 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3 |
| 5951 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10 |
| 5952 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4 |
| 5953 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20 |
| 5954 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5 |
| 5955 | #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40 |
| 5956 | #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6 |
| 5957 | #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80 |
| 5958 | #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7 |
| 5959 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7 |
| 5960 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0 |
| 5961 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70 |
| 5962 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4 |
| 5963 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80 |
| 5964 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7 |
| 5965 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300 |
| 5966 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8 |
| 5967 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00 |
| 5968 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa |
| 5969 | #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1 |
| 5970 | #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0 |
| 5971 | #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2 |
| 5972 | #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1 |
| 5973 | #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4 |
| 5974 | #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2 |
| 5975 | #define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8 |
| 5976 | #define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3 |
| 5977 | #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1 |
| 5978 | #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0 |
| 5979 | #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2 |
| 5980 | #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1 |
| 5981 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4 |
| 5982 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2 |
| 5983 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8 |
| 5984 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3 |
| 5985 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10 |
| 5986 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4 |
| 5987 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20 |
| 5988 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5 |
| 5989 | #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40 |
| 5990 | #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6 |
| 5991 | #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80 |
| 5992 | #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7 |
| 5993 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7 |
| 5994 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0 |
| 5995 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70 |
| 5996 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4 |
| 5997 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80 |
| 5998 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7 |
| 5999 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300 |
| 6000 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8 |
| 6001 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00 |
| 6002 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa |
| 6003 | #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1 |
| 6004 | #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0 |
| 6005 | #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2 |
| 6006 | #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1 |
| 6007 | #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4 |
| 6008 | #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2 |
| 6009 | #define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8 |
| 6010 | #define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3 |
| 6011 | #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1 |
| 6012 | #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0 |
| 6013 | #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2 |
| 6014 | #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1 |
| 6015 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4 |
| 6016 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2 |
| 6017 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8 |
| 6018 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3 |
| 6019 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10 |
| 6020 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4 |
| 6021 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20 |
| 6022 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5 |
| 6023 | #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40 |
| 6024 | #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6 |
| 6025 | #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80 |
| 6026 | #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7 |
| 6027 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7 |
| 6028 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0 |
| 6029 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70 |
| 6030 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4 |
| 6031 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80 |
| 6032 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7 |
| 6033 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300 |
| 6034 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8 |
| 6035 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00 |
| 6036 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa |
| 6037 | #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1 |
| 6038 | #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0 |
| 6039 | #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2 |
| 6040 | #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1 |
| 6041 | #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4 |
| 6042 | #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2 |
| 6043 | #define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8 |
| 6044 | #define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3 |
| 6045 | #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1 |
| 6046 | #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0 |
| 6047 | #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2 |
| 6048 | #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1 |
| 6049 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4 |
| 6050 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2 |
| 6051 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8 |
| 6052 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3 |
| 6053 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10 |
| 6054 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4 |
| 6055 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20 |
| 6056 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5 |
| 6057 | #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40 |
| 6058 | #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6 |
| 6059 | #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80 |
| 6060 | #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7 |
| 6061 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7 |
| 6062 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0 |
| 6063 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70 |
| 6064 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4 |
| 6065 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80 |
| 6066 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7 |
| 6067 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300 |
| 6068 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8 |
| 6069 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00 |
| 6070 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa |
| 6071 | #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1 |
| 6072 | #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0 |
| 6073 | #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2 |
| 6074 | #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1 |
| 6075 | #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4 |
| 6076 | #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2 |
| 6077 | #define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8 |
| 6078 | #define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3 |
| 6079 | #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1 |
| 6080 | #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0 |
| 6081 | #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2 |
| 6082 | #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1 |
| 6083 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4 |
| 6084 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2 |
| 6085 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8 |
| 6086 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3 |
| 6087 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10 |
| 6088 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4 |
| 6089 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20 |
| 6090 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5 |
| 6091 | #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40 |
| 6092 | #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6 |
| 6093 | #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80 |
| 6094 | #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7 |
| 6095 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7 |
| 6096 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0 |
| 6097 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70 |
| 6098 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4 |
| 6099 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80 |
| 6100 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7 |
| 6101 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300 |
| 6102 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8 |
| 6103 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00 |
| 6104 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa |
| 6105 | #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1 |
| 6106 | #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0 |
| 6107 | #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2 |
| 6108 | #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1 |
| 6109 | #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4 |
| 6110 | #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2 |
| 6111 | #define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8 |
| 6112 | #define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3 |
| 6113 | #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1 |
| 6114 | #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0 |
| 6115 | #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2 |
| 6116 | #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1 |
| 6117 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4 |
| 6118 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2 |
| 6119 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8 |
| 6120 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3 |
| 6121 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10 |
| 6122 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4 |
| 6123 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20 |
| 6124 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5 |
| 6125 | #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40 |
| 6126 | #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6 |
| 6127 | #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80 |
| 6128 | #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7 |
| 6129 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7 |
| 6130 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0 |
| 6131 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70 |
| 6132 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4 |
| 6133 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80 |
| 6134 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7 |
| 6135 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300 |
| 6136 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8 |
| 6137 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00 |
| 6138 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa |
| 6139 | #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1 |
| 6140 | #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0 |
| 6141 | #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2 |
| 6142 | #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1 |
| 6143 | #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4 |
| 6144 | #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2 |
| 6145 | #define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8 |
| 6146 | #define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3 |
| 6147 | #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1 |
| 6148 | #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0 |
| 6149 | #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2 |
| 6150 | #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1 |
| 6151 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4 |
| 6152 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2 |
| 6153 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8 |
| 6154 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3 |
| 6155 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10 |
| 6156 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4 |
| 6157 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20 |
| 6158 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5 |
| 6159 | #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40 |
| 6160 | #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6 |
| 6161 | #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80 |
| 6162 | #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7 |
| 6163 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7 |
| 6164 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0 |
| 6165 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70 |
| 6166 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4 |
| 6167 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80 |
| 6168 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7 |
| 6169 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300 |
| 6170 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8 |
| 6171 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00 |
| 6172 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa |
| 6173 | #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1 |
| 6174 | #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0 |
| 6175 | #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2 |
| 6176 | #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1 |
| 6177 | #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4 |
| 6178 | #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2 |
| 6179 | #define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8 |
| 6180 | #define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3 |
| 6181 | #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1 |
| 6182 | #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0 |
| 6183 | #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2 |
| 6184 | #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1 |
| 6185 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4 |
| 6186 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2 |
| 6187 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8 |
| 6188 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3 |
| 6189 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10 |
| 6190 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4 |
| 6191 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20 |
| 6192 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5 |
| 6193 | #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40 |
| 6194 | #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6 |
| 6195 | #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80 |
| 6196 | #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7 |
| 6197 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7 |
| 6198 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0 |
| 6199 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70 |
| 6200 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4 |
| 6201 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80 |
| 6202 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7 |
| 6203 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300 |
| 6204 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8 |
| 6205 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00 |
| 6206 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa |
| 6207 | #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1 |
| 6208 | #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0 |
| 6209 | #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2 |
| 6210 | #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1 |
| 6211 | #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4 |
| 6212 | #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2 |
| 6213 | #define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8 |
| 6214 | #define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3 |
| 6215 | #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1 |
| 6216 | #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0 |
| 6217 | #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2 |
| 6218 | #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1 |
| 6219 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4 |
| 6220 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2 |
| 6221 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8 |
| 6222 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3 |
| 6223 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10 |
| 6224 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4 |
| 6225 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20 |
| 6226 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5 |
| 6227 | #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40 |
| 6228 | #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6 |
| 6229 | #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80 |
| 6230 | #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7 |
| 6231 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7 |
| 6232 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0 |
| 6233 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70 |
| 6234 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4 |
| 6235 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80 |
| 6236 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7 |
| 6237 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300 |
| 6238 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8 |
| 6239 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00 |
| 6240 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa |
| 6241 | #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1 |
| 6242 | #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0 |
| 6243 | #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2 |
| 6244 | #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1 |
| 6245 | #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4 |
| 6246 | #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2 |
| 6247 | #define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8 |
| 6248 | #define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3 |
| 6249 | #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1 |
| 6250 | #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0 |
| 6251 | #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2 |
| 6252 | #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1 |
| 6253 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4 |
| 6254 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2 |
| 6255 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8 |
| 6256 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3 |
| 6257 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10 |
| 6258 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4 |
| 6259 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20 |
| 6260 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5 |
| 6261 | #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40 |
| 6262 | #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6 |
| 6263 | #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80 |
| 6264 | #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7 |
| 6265 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7 |
| 6266 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0 |
| 6267 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70 |
| 6268 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4 |
| 6269 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80 |
| 6270 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7 |
| 6271 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300 |
| 6272 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8 |
| 6273 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00 |
| 6274 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa |
| 6275 | #define PB1_GLB_CTRL_REG0__BACKUP_MASK 0xffff |
| 6276 | #define PB1_GLB_CTRL_REG0__BACKUP__SHIFT 0x0 |
| 6277 | #define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000 |
| 6278 | #define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10 |
| 6279 | #define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000 |
| 6280 | #define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14 |
| 6281 | #define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000 |
| 6282 | #define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17 |
| 6283 | #define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000 |
| 6284 | #define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18 |
| 6285 | #define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000 |
| 6286 | #define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19 |
| 6287 | #define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000 |
| 6288 | #define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a |
| 6289 | #define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000 |
| 6290 | #define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e |
| 6291 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1 |
| 6292 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0 |
| 6293 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e |
| 6294 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1 |
| 6295 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80 |
| 6296 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7 |
| 6297 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00 |
| 6298 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8 |
| 6299 | #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000 |
| 6300 | #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe |
| 6301 | #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000 |
| 6302 | #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf |
| 6303 | #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000 |
| 6304 | #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16 |
| 6305 | #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000 |
| 6306 | #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17 |
| 6307 | #define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000 |
| 6308 | #define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e |
| 6309 | #define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000 |
| 6310 | #define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f |
| 6311 | #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1 |
| 6312 | #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0 |
| 6313 | #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe |
| 6314 | #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1 |
| 6315 | #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100 |
| 6316 | #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8 |
| 6317 | #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00 |
| 6318 | #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9 |
| 6319 | #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000 |
| 6320 | #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10 |
| 6321 | #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000 |
| 6322 | #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11 |
| 6323 | #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000 |
| 6324 | #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18 |
| 6325 | #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000 |
| 6326 | #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19 |
| 6327 | #define PB1_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f |
| 6328 | #define PB1_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0 |
| 6329 | #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60 |
| 6330 | #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5 |
| 6331 | #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180 |
| 6332 | #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7 |
| 6333 | #define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600 |
| 6334 | #define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9 |
| 6335 | #define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800 |
| 6336 | #define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb |
| 6337 | #define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000 |
| 6338 | #define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc |
| 6339 | #define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000 |
| 6340 | #define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe |
| 6341 | #define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000 |
| 6342 | #define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12 |
| 6343 | #define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000 |
| 6344 | #define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15 |
| 6345 | #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000 |
| 6346 | #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16 |
| 6347 | #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000 |
| 6348 | #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17 |
| 6349 | #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000 |
| 6350 | #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b |
| 6351 | #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000 |
| 6352 | #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c |
| 6353 | #define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000 |
| 6354 | #define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f |
| 6355 | #define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff |
| 6356 | #define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0 |
| 6357 | #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000 |
| 6358 | #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10 |
| 6359 | #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000 |
| 6360 | #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12 |
| 6361 | #define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000 |
| 6362 | #define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16 |
| 6363 | #define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000 |
| 6364 | #define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a |
| 6365 | #define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000 |
| 6366 | #define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b |
| 6367 | #define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000 |
| 6368 | #define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c |
| 6369 | #define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff |
| 6370 | #define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0 |
| 6371 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3_MASK 0x1 |
| 6372 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3__SHIFT 0x0 |
| 6373 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK 0x2 |
| 6374 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7__SHIFT 0x1 |
| 6375 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11_MASK 0x4 |
| 6376 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT 0x2 |
| 6377 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15_MASK 0x8 |
| 6378 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15__SHIFT 0x3 |
| 6379 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT_MASK 0x10 |
| 6380 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT__SHIFT 0x4 |
| 6381 | #define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00 |
| 6382 | #define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8 |
| 6383 | #define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000 |
| 6384 | #define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc |
| 6385 | #define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000 |
| 6386 | #define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10 |
| 6387 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000 |
| 6388 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14 |
| 6389 | #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3_MASK 0x1 |
| 6390 | #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3__SHIFT 0x0 |
| 6391 | #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK 0x2 |
| 6392 | #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3__SHIFT 0x1 |
| 6393 | #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3_MASK 0x4 |
| 6394 | #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT 0x2 |
| 6395 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000 |
| 6396 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc |
| 6397 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000 |
| 6398 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd |
| 6399 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000 |
| 6400 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe |
| 6401 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000 |
| 6402 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf |
| 6403 | #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0_MASK 0x30000 |
| 6404 | #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0__SHIFT 0x10 |
| 6405 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000 |
| 6406 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12 |
| 6407 | #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1_MASK 0x300000 |
| 6408 | #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1__SHIFT 0x14 |
| 6409 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000 |
| 6410 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16 |
| 6411 | #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2_MASK 0x3000000 |
| 6412 | #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2__SHIFT 0x18 |
| 6413 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000 |
| 6414 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a |
| 6415 | #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3_MASK 0x30000000 |
| 6416 | #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3__SHIFT 0x1c |
| 6417 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000 |
| 6418 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e |
| 6419 | #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7_MASK 0x1 |
| 6420 | #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7__SHIFT 0x0 |
| 6421 | #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK 0x2 |
| 6422 | #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7__SHIFT 0x1 |
| 6423 | #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7_MASK 0x4 |
| 6424 | #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT 0x2 |
| 6425 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000 |
| 6426 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc |
| 6427 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000 |
| 6428 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd |
| 6429 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000 |
| 6430 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe |
| 6431 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000 |
| 6432 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf |
| 6433 | #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4_MASK 0x30000 |
| 6434 | #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4__SHIFT 0x10 |
| 6435 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000 |
| 6436 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12 |
| 6437 | #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5_MASK 0x300000 |
| 6438 | #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5__SHIFT 0x14 |
| 6439 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000 |
| 6440 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16 |
| 6441 | #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6_MASK 0x3000000 |
| 6442 | #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6__SHIFT 0x18 |
| 6443 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000 |
| 6444 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a |
| 6445 | #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7_MASK 0x30000000 |
| 6446 | #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7__SHIFT 0x1c |
| 6447 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000 |
| 6448 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e |
| 6449 | #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11_MASK 0x1 |
| 6450 | #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11__SHIFT 0x0 |
| 6451 | #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK 0x2 |
| 6452 | #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11__SHIFT 0x1 |
| 6453 | #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11_MASK 0x4 |
| 6454 | #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT 0x2 |
| 6455 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000 |
| 6456 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc |
| 6457 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000 |
| 6458 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd |
| 6459 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000 |
| 6460 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe |
| 6461 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000 |
| 6462 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf |
| 6463 | #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8_MASK 0x30000 |
| 6464 | #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8__SHIFT 0x10 |
| 6465 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000 |
| 6466 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12 |
| 6467 | #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9_MASK 0x300000 |
| 6468 | #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9__SHIFT 0x14 |
| 6469 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000 |
| 6470 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16 |
| 6471 | #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10_MASK 0x3000000 |
| 6472 | #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10__SHIFT 0x18 |
| 6473 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000 |
| 6474 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a |
| 6475 | #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11_MASK 0x30000000 |
| 6476 | #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11__SHIFT 0x1c |
| 6477 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000 |
| 6478 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e |
| 6479 | #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15_MASK 0x1 |
| 6480 | #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15__SHIFT 0x0 |
| 6481 | #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK 0x2 |
| 6482 | #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15__SHIFT 0x1 |
| 6483 | #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15_MASK 0x4 |
| 6484 | #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT 0x2 |
| 6485 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000 |
| 6486 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc |
| 6487 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000 |
| 6488 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd |
| 6489 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000 |
| 6490 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe |
| 6491 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000 |
| 6492 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf |
| 6493 | #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12_MASK 0x30000 |
| 6494 | #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12__SHIFT 0x10 |
| 6495 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000 |
| 6496 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12 |
| 6497 | #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13_MASK 0x300000 |
| 6498 | #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13__SHIFT 0x14 |
| 6499 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000 |
| 6500 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16 |
| 6501 | #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14_MASK 0x3000000 |
| 6502 | #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14__SHIFT 0x18 |
| 6503 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000 |
| 6504 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a |
| 6505 | #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15_MASK 0x30000000 |
| 6506 | #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15__SHIFT 0x1c |
| 6507 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000 |
| 6508 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e |
| 6509 | #define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff |
| 6510 | #define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0 |
| 6511 | #define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000 |
| 6512 | #define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10 |
| 6513 | #define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1 |
| 6514 | #define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0 |
| 6515 | #define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2 |
| 6516 | #define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1 |
| 6517 | #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4 |
| 6518 | #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2 |
| 6519 | #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8 |
| 6520 | #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3 |
| 6521 | #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000 |
| 6522 | #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf |
| 6523 | #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000 |
| 6524 | #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10 |
| 6525 | #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1 |
| 6526 | #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0 |
| 6527 | #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2 |
| 6528 | #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1 |
| 6529 | #define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN_MASK 0x4 |
| 6530 | #define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT 0x2 |
| 6531 | #define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL_MASK 0x8 |
| 6532 | #define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL__SHIFT 0x3 |
| 6533 | #define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN_MASK 0x10 |
| 6534 | #define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN__SHIFT 0x4 |
| 6535 | #define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL_MASK 0x20 |
| 6536 | #define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL__SHIFT 0x5 |
| 6537 | #define PB1_HW_DEBUG__HW_00_DEBUG_MASK 0x1 |
| 6538 | #define PB1_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 |
| 6539 | #define PB1_HW_DEBUG__HW_01_DEBUG_MASK 0x2 |
| 6540 | #define PB1_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 |
| 6541 | #define PB1_HW_DEBUG__HW_02_DEBUG_MASK 0x4 |
| 6542 | #define PB1_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 |
| 6543 | #define PB1_HW_DEBUG__HW_03_DEBUG_MASK 0x8 |
| 6544 | #define PB1_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 |
| 6545 | #define PB1_HW_DEBUG__HW_04_DEBUG_MASK 0x10 |
| 6546 | #define PB1_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 |
| 6547 | #define PB1_HW_DEBUG__HW_05_DEBUG_MASK 0x20 |
| 6548 | #define PB1_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 |
| 6549 | #define PB1_HW_DEBUG__HW_06_DEBUG_MASK 0x40 |
| 6550 | #define PB1_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 |
| 6551 | #define PB1_HW_DEBUG__HW_07_DEBUG_MASK 0x80 |
| 6552 | #define PB1_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 |
| 6553 | #define PB1_HW_DEBUG__HW_08_DEBUG_MASK 0x100 |
| 6554 | #define PB1_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 |
| 6555 | #define PB1_HW_DEBUG__HW_09_DEBUG_MASK 0x200 |
| 6556 | #define PB1_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 |
| 6557 | #define PB1_HW_DEBUG__HW_10_DEBUG_MASK 0x400 |
| 6558 | #define PB1_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa |
| 6559 | #define PB1_HW_DEBUG__HW_11_DEBUG_MASK 0x800 |
| 6560 | #define PB1_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb |
| 6561 | #define PB1_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 |
| 6562 | #define PB1_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc |
| 6563 | #define PB1_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 |
| 6564 | #define PB1_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd |
| 6565 | #define PB1_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 |
| 6566 | #define PB1_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe |
| 6567 | #define PB1_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 |
| 6568 | #define PB1_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf |
| 6569 | #define PB1_HW_DEBUG__HW_16_DEBUG_MASK 0x10000 |
| 6570 | #define PB1_HW_DEBUG__HW_16_DEBUG__SHIFT 0x10 |
| 6571 | #define PB1_HW_DEBUG__HW_17_DEBUG_MASK 0x20000 |
| 6572 | #define PB1_HW_DEBUG__HW_17_DEBUG__SHIFT 0x11 |
| 6573 | #define PB1_HW_DEBUG__HW_18_DEBUG_MASK 0x40000 |
| 6574 | #define PB1_HW_DEBUG__HW_18_DEBUG__SHIFT 0x12 |
| 6575 | #define PB1_HW_DEBUG__HW_19_DEBUG_MASK 0x80000 |
| 6576 | #define PB1_HW_DEBUG__HW_19_DEBUG__SHIFT 0x13 |
| 6577 | #define PB1_HW_DEBUG__HW_20_DEBUG_MASK 0x100000 |
| 6578 | #define PB1_HW_DEBUG__HW_20_DEBUG__SHIFT 0x14 |
| 6579 | #define PB1_HW_DEBUG__HW_21_DEBUG_MASK 0x200000 |
| 6580 | #define PB1_HW_DEBUG__HW_21_DEBUG__SHIFT 0x15 |
| 6581 | #define PB1_HW_DEBUG__HW_22_DEBUG_MASK 0x400000 |
| 6582 | #define PB1_HW_DEBUG__HW_22_DEBUG__SHIFT 0x16 |
| 6583 | #define PB1_HW_DEBUG__HW_23_DEBUG_MASK 0x800000 |
| 6584 | #define PB1_HW_DEBUG__HW_23_DEBUG__SHIFT 0x17 |
| 6585 | #define PB1_HW_DEBUG__HW_24_DEBUG_MASK 0x1000000 |
| 6586 | #define PB1_HW_DEBUG__HW_24_DEBUG__SHIFT 0x18 |
| 6587 | #define PB1_HW_DEBUG__HW_25_DEBUG_MASK 0x2000000 |
| 6588 | #define PB1_HW_DEBUG__HW_25_DEBUG__SHIFT 0x19 |
| 6589 | #define PB1_HW_DEBUG__HW_26_DEBUG_MASK 0x4000000 |
| 6590 | #define PB1_HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a |
| 6591 | #define PB1_HW_DEBUG__HW_27_DEBUG_MASK 0x8000000 |
| 6592 | #define PB1_HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b |
| 6593 | #define PB1_HW_DEBUG__HW_28_DEBUG_MASK 0x10000000 |
| 6594 | #define PB1_HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c |
| 6595 | #define PB1_HW_DEBUG__HW_29_DEBUG_MASK 0x20000000 |
| 6596 | #define PB1_HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d |
| 6597 | #define PB1_HW_DEBUG__HW_30_DEBUG_MASK 0x40000000 |
| 6598 | #define PB1_HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e |
| 6599 | #define PB1_HW_DEBUG__HW_31_DEBUG_MASK 0x80000000 |
| 6600 | #define PB1_HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f |
| 6601 | #define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2 |
| 6602 | #define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1 |
| 6603 | #define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4 |
| 6604 | #define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2 |
| 6605 | #define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8 |
| 6606 | #define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3 |
| 6607 | #define PB1_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON_MASK 0x10 |
| 6608 | #define PB1_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON__SHIFT 0x4 |
| 6609 | #define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60 |
| 6610 | #define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5 |
| 6611 | #define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80 |
| 6612 | #define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7 |
| 6613 | #define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000 |
| 6614 | #define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc |
| 6615 | #define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000 |
| 6616 | #define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd |
| 6617 | #define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000 |
| 6618 | #define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe |
| 6619 | #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000 |
| 6620 | #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf |
| 6621 | #define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000 |
| 6622 | #define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10 |
| 6623 | #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000 |
| 6624 | #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14 |
| 6625 | #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000 |
| 6626 | #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15 |
| 6627 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e |
| 6628 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1 |
| 6629 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0 |
| 6630 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5 |
| 6631 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00 |
| 6632 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9 |
| 6633 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000 |
| 6634 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe |
| 6635 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000 |
| 6636 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13 |
| 6637 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000 |
| 6638 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17 |
| 6639 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000 |
| 6640 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b |
| 6641 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000 |
| 6642 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c |
| 6643 | #define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000 |
| 6644 | #define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d |
| 6645 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000 |
| 6646 | #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e |
| 6647 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e |
| 6648 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1 |
| 6649 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20 |
| 6650 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5 |
| 6651 | #define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40 |
| 6652 | #define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6 |
| 6653 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80 |
| 6654 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7 |
| 6655 | #define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300 |
| 6656 | #define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8 |
| 6657 | #define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00 |
| 6658 | #define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa |
| 6659 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000 |
| 6660 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc |
| 6661 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000 |
| 6662 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10 |
| 6663 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000 |
| 6664 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14 |
| 6665 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000 |
| 6666 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18 |
| 6667 | #define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000 |
| 6668 | #define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c |
| 6669 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000 |
| 6670 | #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f |
| 6671 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2 |
| 6672 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1 |
| 6673 | #define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c |
| 6674 | #define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2 |
| 6675 | #define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60 |
| 6676 | #define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5 |
| 6677 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80 |
| 6678 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7 |
| 6679 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700 |
| 6680 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8 |
| 6681 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800 |
| 6682 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb |
| 6683 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000 |
| 6684 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf |
| 6685 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000 |
| 6686 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19 |
| 6687 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000 |
| 6688 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d |
| 6689 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000 |
| 6690 | #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f |
| 6691 | #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe |
| 6692 | #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1 |
| 6693 | #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0 |
| 6694 | #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4 |
| 6695 | #define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000 |
| 6696 | #define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd |
| 6697 | #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000 |
| 6698 | #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf |
| 6699 | #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000 |
| 6700 | #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10 |
| 6701 | #define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000 |
| 6702 | #define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18 |
| 6703 | #define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2 |
| 6704 | #define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1 |
| 6705 | #define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4 |
| 6706 | #define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2 |
| 6707 | #define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE_MASK 0x6 |
| 6708 | #define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE__SHIFT 0x1 |
| 6709 | #define PB1_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE_MASK 0x18 |
| 6710 | #define PB1_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE__SHIFT 0x3 |
| 6711 | #define PB1_STRAP_GLB_REG1__STRAP_RX_EI_FILTER_MASK 0x60 |
| 6712 | #define PB1_STRAP_GLB_REG1__STRAP_RX_EI_FILTER__SHIFT 0x5 |
| 6713 | #define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY_MASK 0x80 |
| 6714 | #define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY__SHIFT 0x7 |
| 6715 | #define PB1_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE_MASK 0x300 |
| 6716 | #define PB1_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE__SHIFT 0x8 |
| 6717 | #define PB1_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG_MASK 0x400 |
| 6718 | #define PB1_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG__SHIFT 0xa |
| 6719 | #define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT_MASK 0x1800 |
| 6720 | #define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT__SHIFT 0xb |
| 6721 | #define PB1_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME_MASK 0x1c |
| 6722 | #define PB1_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT 0x2 |
| 6723 | #define PB1_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME_MASK 0x60 |
| 6724 | #define PB1_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME__SHIFT 0x5 |
| 6725 | #define PB1_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME_MASK 0x180 |
| 6726 | #define PB1_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME__SHIFT 0x7 |
| 6727 | #define PB1_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME_MASK 0x600 |
| 6728 | #define PB1_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME__SHIFT 0x9 |
| 6729 | #define PB1_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME_MASK 0x1800 |
| 6730 | #define PB1_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME__SHIFT 0xb |
| 6731 | #define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS0_MASK 0x10000000 |
| 6732 | #define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS0__SHIFT 0x1c |
| 6733 | #define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS1_MASK 0x20000000 |
| 6734 | #define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS1__SHIFT 0x1d |
| 6735 | #define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR_MASK 0xc0000000 |
| 6736 | #define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR__SHIFT 0x1e |
| 6737 | #define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f |
| 6738 | #define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0 |
| 6739 | #define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80 |
| 6740 | #define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7 |
| 6741 | #define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00 |
| 6742 | #define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8 |
| 6743 | #define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000 |
| 6744 | #define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14 |
| 6745 | #define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000 |
| 6746 | #define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15 |
| 6747 | #define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000 |
| 6748 | #define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16 |
| 6749 | #define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000 |
| 6750 | #define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17 |
| 6751 | #define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000 |
| 6752 | #define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18 |
| 6753 | #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff |
| 6754 | #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0 |
| 6755 | #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100 |
| 6756 | #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8 |
| 6757 | #define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000 |
| 6758 | #define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10 |
| 6759 | #define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000 |
| 6760 | #define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11 |
| 6761 | #define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000 |
| 6762 | #define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14 |
| 6763 | #define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff |
| 6764 | #define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0 |
| 6765 | #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1 |
| 6766 | #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0 |
| 6767 | #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e |
| 6768 | #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1 |
| 6769 | #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff |
| 6770 | #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0 |
| 6771 | #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00 |
| 6772 | #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8 |
| 6773 | #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000 |
| 6774 | #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10 |
| 6775 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1 |
| 6776 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0 |
| 6777 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2 |
| 6778 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1 |
| 6779 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4 |
| 6780 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2 |
| 6781 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8 |
| 6782 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3 |
| 6783 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10 |
| 6784 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4 |
| 6785 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20 |
| 6786 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5 |
| 6787 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40 |
| 6788 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6 |
| 6789 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80 |
| 6790 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7 |
| 6791 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100 |
| 6792 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8 |
| 6793 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200 |
| 6794 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9 |
| 6795 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400 |
| 6796 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa |
| 6797 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800 |
| 6798 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb |
| 6799 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000 |
| 6800 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc |
| 6801 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000 |
| 6802 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd |
| 6803 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000 |
| 6804 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe |
| 6805 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN_MASK 0x8000 |
| 6806 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN__SHIFT 0xf |
| 6807 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN_MASK 0x10000 |
| 6808 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x10 |
| 6809 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN_MASK 0x20000 |
| 6810 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN__SHIFT 0x11 |
| 6811 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN_MASK 0x40000 |
| 6812 | #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x12 |
| 6813 | #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3 |
| 6814 | #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0 |
| 6815 | #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4 |
| 6816 | #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2 |
| 6817 | #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8 |
| 6818 | #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3 |
| 6819 | #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0 |
| 6820 | #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4 |
| 6821 | #define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800 |
| 6822 | #define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb |
| 6823 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff |
| 6824 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 |
| 6825 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100 |
| 6826 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8 |
| 6827 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00 |
| 6828 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9 |
| 6829 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000 |
| 6830 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc |
| 6831 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000 |
| 6832 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd |
| 6833 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000 |
| 6834 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe |
| 6835 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000 |
| 6836 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf |
| 6837 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000 |
| 6838 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c |
| 6839 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000 |
| 6840 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e |
| 6841 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000 |
| 6842 | #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f |
| 6843 | #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f |
| 6844 | #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0 |
| 6845 | #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20 |
| 6846 | #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5 |
| 6847 | #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0 |
| 6848 | #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6 |
| 6849 | #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100 |
| 6850 | #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8 |
| 6851 | #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200 |
| 6852 | #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9 |
| 6853 | #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400 |
| 6854 | #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa |
| 6855 | #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800 |
| 6856 | #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb |
| 6857 | #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000 |
| 6858 | #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc |
| 6859 | #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000 |
| 6860 | #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd |
| 6861 | #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000 |
| 6862 | #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe |
| 6863 | #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000 |
| 6864 | #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13 |
| 6865 | #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000 |
| 6866 | #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16 |
| 6867 | #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 6868 | #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 6869 | #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 |
| 6870 | #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 |
| 6871 | #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70 |
| 6872 | #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4 |
| 6873 | #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ_MASK 0x300 |
| 6874 | #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ__SHIFT 0x8 |
| 6875 | #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 6876 | #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 6877 | #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 |
| 6878 | #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 |
| 6879 | #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70 |
| 6880 | #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4 |
| 6881 | #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ_MASK 0x300 |
| 6882 | #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ__SHIFT 0x8 |
| 6883 | #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 6884 | #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 6885 | #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 |
| 6886 | #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 |
| 6887 | #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70 |
| 6888 | #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4 |
| 6889 | #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ_MASK 0x300 |
| 6890 | #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ__SHIFT 0x8 |
| 6891 | #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 6892 | #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 6893 | #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 |
| 6894 | #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 |
| 6895 | #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70 |
| 6896 | #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4 |
| 6897 | #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ_MASK 0x300 |
| 6898 | #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ__SHIFT 0x8 |
| 6899 | #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3 |
| 6900 | #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0 |
| 6901 | #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4 |
| 6902 | #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2 |
| 6903 | #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8 |
| 6904 | #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3 |
| 6905 | #define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10 |
| 6906 | #define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4 |
| 6907 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7 |
| 6908 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 |
| 6909 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8 |
| 6910 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3 |
| 6911 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70 |
| 6912 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4 |
| 6913 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80 |
| 6914 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7 |
| 6915 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100 |
| 6916 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8 |
| 6917 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200 |
| 6918 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9 |
| 6919 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00 |
| 6920 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa |
| 6921 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000 |
| 6922 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12 |
| 6923 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000 |
| 6924 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13 |
| 6925 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000 |
| 6926 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c |
| 6927 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000 |
| 6928 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d |
| 6929 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000 |
| 6930 | #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f |
| 6931 | #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7 |
| 6932 | #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0 |
| 6933 | #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8 |
| 6934 | #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3 |
| 6935 | #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10 |
| 6936 | #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4 |
| 6937 | #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20 |
| 6938 | #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5 |
| 6939 | #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40 |
| 6940 | #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6 |
| 6941 | #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80 |
| 6942 | #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7 |
| 6943 | #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100 |
| 6944 | #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8 |
| 6945 | #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200 |
| 6946 | #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9 |
| 6947 | #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000 |
| 6948 | #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe |
| 6949 | #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000 |
| 6950 | #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12 |
| 6951 | #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 6952 | #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 6953 | #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70 |
| 6954 | #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4 |
| 6955 | #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 6956 | #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 6957 | #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70 |
| 6958 | #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4 |
| 6959 | #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 6960 | #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 6961 | #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70 |
| 6962 | #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4 |
| 6963 | #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 |
| 6964 | #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 |
| 6965 | #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70 |
| 6966 | #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4 |
| 6967 | #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff |
| 6968 | #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0 |
| 6969 | #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00 |
| 6970 | #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa |
| 6971 | #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000 |
| 6972 | #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14 |
| 6973 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf |
| 6974 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0 |
| 6975 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0 |
| 6976 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4 |
| 6977 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00 |
| 6978 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8 |
| 6979 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000 |
| 6980 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc |
| 6981 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000 |
| 6982 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10 |
| 6983 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000 |
| 6984 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14 |
| 6985 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000 |
| 6986 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18 |
| 6987 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000 |
| 6988 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19 |
| 6989 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000 |
| 6990 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a |
| 6991 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000 |
| 6992 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b |
| 6993 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000 |
| 6994 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c |
| 6995 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000 |
| 6996 | #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d |
| 6997 | #define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000 |
| 6998 | #define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e |
| 6999 | #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000 |
| 7000 | #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc |
| 7001 | #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000 |
| 7002 | #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10 |
| 7003 | #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000 |
| 7004 | #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14 |
| 7005 | #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000 |
| 7006 | #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18 |
| 7007 | #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000 |
| 7008 | #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a |
| 7009 | #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000 |
| 7010 | #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c |
| 7011 | #define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000 |
| 7012 | #define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e |
| 7013 | #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1 |
| 7014 | #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0 |
| 7015 | #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2 |
| 7016 | #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1 |
| 7017 | #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4 |
| 7018 | #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2 |
| 7019 | #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1_MASK 0x18 |
| 7020 | #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1__SHIFT 0x3 |
| 7021 | #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2_MASK 0x60 |
| 7022 | #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2__SHIFT 0x5 |
| 7023 | #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3_MASK 0x180 |
| 7024 | #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3__SHIFT 0x7 |
| 7025 | #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE_MASK 0xe00 |
| 7026 | #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE__SHIFT 0x9 |
| 7027 | #define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1_MASK 0x3000 |
| 7028 | #define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1__SHIFT 0xc |
| 7029 | #define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2_MASK 0xc000 |
| 7030 | #define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2__SHIFT 0xe |
| 7031 | #define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3_MASK 0x30000 |
| 7032 | #define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3__SHIFT 0x10 |
| 7033 | #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000 |
| 7034 | #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14 |
| 7035 | #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000 |
| 7036 | #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18 |
| 7037 | #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000 |
| 7038 | #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c |
| 7039 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7 |
| 7040 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0 |
| 7041 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38 |
| 7042 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3 |
| 7043 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0 |
| 7044 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6 |
| 7045 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00 |
| 7046 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9 |
| 7047 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000 |
| 7048 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc |
| 7049 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000 |
| 7050 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf |
| 7051 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000 |
| 7052 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14 |
| 7053 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000 |
| 7054 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18 |
| 7055 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000 |
| 7056 | #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c |
| 7057 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f |
| 7058 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0 |
| 7059 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0 |
| 7060 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5 |
| 7061 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00 |
| 7062 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa |
| 7063 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000 |
| 7064 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf |
| 7065 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000 |
| 7066 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10 |
| 7067 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000 |
| 7068 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11 |
| 7069 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000 |
| 7070 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12 |
| 7071 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000 |
| 7072 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13 |
| 7073 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000 |
| 7074 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14 |
| 7075 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000 |
| 7076 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b |
| 7077 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000 |
| 7078 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c |
| 7079 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000 |
| 7080 | #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d |
| 7081 | #define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000 |
| 7082 | #define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f |
| 7083 | #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf |
| 7084 | #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0 |
| 7085 | #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0 |
| 7086 | #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4 |
| 7087 | #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00 |
| 7088 | #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8 |
| 7089 | #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000 |
| 7090 | #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc |
| 7091 | #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000 |
| 7092 | #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10 |
| 7093 | #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000 |
| 7094 | #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14 |
| 7095 | #define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000 |
| 7096 | #define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18 |
| 7097 | #define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000 |
| 7098 | #define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a |
| 7099 | #define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000 |
| 7100 | #define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b |
| 7101 | #define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000 |
| 7102 | #define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c |
| 7103 | #define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF_MASK 0x20000000 |
| 7104 | #define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF__SHIFT 0x1d |
| 7105 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf |
| 7106 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0 |
| 7107 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0 |
| 7108 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4 |
| 7109 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00 |
| 7110 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8 |
| 7111 | #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000 |
| 7112 | #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc |
| 7113 | #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000 |
| 7114 | #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd |
| 7115 | #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK_MASK 0x4000 |
| 7116 | #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK__SHIFT 0xe |
| 7117 | #define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3_MASK 0x10000 |
| 7118 | #define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3__SHIFT 0x10 |
| 7119 | #define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2_MASK 0x20000 |
| 7120 | #define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2__SHIFT 0x11 |
| 7121 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000 |
| 7122 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12 |
| 7123 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000 |
| 7124 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15 |
| 7125 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000 |
| 7126 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18 |
| 7127 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000 |
| 7128 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b |
| 7129 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000 |
| 7130 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c |
| 7131 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000 |
| 7132 | #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d |
| 7133 | #define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3 |
| 7134 | #define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0 |
| 7135 | #define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc |
| 7136 | #define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2 |
| 7137 | #define PB1_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN_MASK 0x10 |
| 7138 | #define PB1_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN__SHIFT 0x4 |
| 7139 | #define PB1_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY_MASK 0x20 |
| 7140 | #define PB1_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY__SHIFT 0x5 |
| 7141 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3_MASK 0x1 |
| 7142 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3__SHIFT 0x0 |
| 7143 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK 0x2 |
| 7144 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7__SHIFT 0x1 |
| 7145 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11_MASK 0x4 |
| 7146 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT 0x2 |
| 7147 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15_MASK 0x8 |
| 7148 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15__SHIFT 0x3 |
| 7149 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3_MASK 0x10 |
| 7150 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3__SHIFT 0x4 |
| 7151 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7_MASK 0x20 |
| 7152 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7__SHIFT 0x5 |
| 7153 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11_MASK 0x40 |
| 7154 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11__SHIFT 0x6 |
| 7155 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15_MASK 0x80 |
| 7156 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15__SHIFT 0x7 |
| 7157 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3_MASK 0x100 |
| 7158 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3__SHIFT 0x8 |
| 7159 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7_MASK 0x200 |
| 7160 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7__SHIFT 0x9 |
| 7161 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11_MASK 0x400 |
| 7162 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11__SHIFT 0xa |
| 7163 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15_MASK 0x800 |
| 7164 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15__SHIFT 0xb |
| 7165 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3_MASK 0x1000 |
| 7166 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3__SHIFT 0xc |
| 7167 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7_MASK 0x2000 |
| 7168 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7__SHIFT 0xd |
| 7169 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11_MASK 0x4000 |
| 7170 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11__SHIFT 0xe |
| 7171 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15_MASK 0x8000 |
| 7172 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15__SHIFT 0xf |
| 7173 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3_MASK 0x10000 |
| 7174 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3__SHIFT 0x10 |
| 7175 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7_MASK 0x20000 |
| 7176 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7__SHIFT 0x11 |
| 7177 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11_MASK 0x40000 |
| 7178 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11__SHIFT 0x12 |
| 7179 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15_MASK 0x80000 |
| 7180 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15__SHIFT 0x13 |
| 7181 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3_MASK 0x100000 |
| 7182 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3__SHIFT 0x14 |
| 7183 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7_MASK 0x200000 |
| 7184 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7__SHIFT 0x15 |
| 7185 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11_MASK 0x400000 |
| 7186 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11__SHIFT 0x16 |
| 7187 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15_MASK 0x800000 |
| 7188 | #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15__SHIFT 0x17 |
| 7189 | #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1 |
| 7190 | #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0 |
| 7191 | #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2 |
| 7192 | #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1 |
| 7193 | #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4 |
| 7194 | #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2 |
| 7195 | #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8 |
| 7196 | #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3 |
| 7197 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0 |
| 7198 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6 |
| 7199 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100 |
| 7200 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8 |
| 7201 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200 |
| 7202 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9 |
| 7203 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400 |
| 7204 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa |
| 7205 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800 |
| 7206 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb |
| 7207 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000 |
| 7208 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc |
| 7209 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000 |
| 7210 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd |
| 7211 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000 |
| 7212 | #define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe |
| 7213 | #define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000 |
| 7214 | #define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf |
| 7215 | #define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000 |
| 7216 | #define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10 |
| 7217 | #define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000 |
| 7218 | #define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11 |
| 7219 | #define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000 |
| 7220 | #define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12 |
| 7221 | #define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000 |
| 7222 | #define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13 |
| 7223 | #define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000 |
| 7224 | #define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14 |
| 7225 | #define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000 |
| 7226 | #define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15 |
| 7227 | #define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000 |
| 7228 | #define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16 |
| 7229 | #define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000 |
| 7230 | #define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c |
| 7231 | #define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000 |
| 7232 | #define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d |
| 7233 | #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000 |
| 7234 | #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e |
| 7235 | #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000 |
| 7236 | #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f |
| 7237 | #define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1 |
| 7238 | #define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0 |
| 7239 | #define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2 |
| 7240 | #define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1 |
| 7241 | #define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff |
| 7242 | #define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0 |
| 7243 | #define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00 |
| 7244 | #define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa |
| 7245 | #define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000 |
| 7246 | #define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc |
| 7247 | #define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000 |
| 7248 | #define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd |
| 7249 | #define PB1_RX_LANE0_CTRL_REG0__RX_TERM_EN_0_MASK 0x4000 |
| 7250 | #define PB1_RX_LANE0_CTRL_REG0__RX_TERM_EN_0__SHIFT 0xe |
| 7251 | #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7 |
| 7252 | #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0 |
| 7253 | #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8 |
| 7254 | #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3 |
| 7255 | #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0_MASK 0x40 |
| 7256 | #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0__SHIFT 0x6 |
| 7257 | #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80 |
| 7258 | #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7 |
| 7259 | #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100 |
| 7260 | #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8 |
| 7261 | #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200 |
| 7262 | #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9 |
| 7263 | #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0_MASK 0x3fc00 |
| 7264 | #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0__SHIFT 0xa |
| 7265 | #define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff |
| 7266 | #define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0 |
| 7267 | #define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00 |
| 7268 | #define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa |
| 7269 | #define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000 |
| 7270 | #define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc |
| 7271 | #define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000 |
| 7272 | #define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd |
| 7273 | #define PB1_RX_LANE1_CTRL_REG0__RX_TERM_EN_1_MASK 0x4000 |
| 7274 | #define PB1_RX_LANE1_CTRL_REG0__RX_TERM_EN_1__SHIFT 0xe |
| 7275 | #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7 |
| 7276 | #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0 |
| 7277 | #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8 |
| 7278 | #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3 |
| 7279 | #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1_MASK 0x40 |
| 7280 | #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1__SHIFT 0x6 |
| 7281 | #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80 |
| 7282 | #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7 |
| 7283 | #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100 |
| 7284 | #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8 |
| 7285 | #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200 |
| 7286 | #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9 |
| 7287 | #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1_MASK 0x3fc00 |
| 7288 | #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1__SHIFT 0xa |
| 7289 | #define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff |
| 7290 | #define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0 |
| 7291 | #define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00 |
| 7292 | #define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa |
| 7293 | #define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000 |
| 7294 | #define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc |
| 7295 | #define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000 |
| 7296 | #define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd |
| 7297 | #define PB1_RX_LANE2_CTRL_REG0__RX_TERM_EN_2_MASK 0x4000 |
| 7298 | #define PB1_RX_LANE2_CTRL_REG0__RX_TERM_EN_2__SHIFT 0xe |
| 7299 | #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7 |
| 7300 | #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0 |
| 7301 | #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8 |
| 7302 | #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3 |
| 7303 | #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2_MASK 0x40 |
| 7304 | #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2__SHIFT 0x6 |
| 7305 | #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80 |
| 7306 | #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7 |
| 7307 | #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100 |
| 7308 | #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8 |
| 7309 | #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200 |
| 7310 | #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9 |
| 7311 | #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2_MASK 0x3fc00 |
| 7312 | #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2__SHIFT 0xa |
| 7313 | #define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff |
| 7314 | #define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0 |
| 7315 | #define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00 |
| 7316 | #define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa |
| 7317 | #define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000 |
| 7318 | #define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc |
| 7319 | #define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000 |
| 7320 | #define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd |
| 7321 | #define PB1_RX_LANE3_CTRL_REG0__RX_TERM_EN_3_MASK 0x4000 |
| 7322 | #define PB1_RX_LANE3_CTRL_REG0__RX_TERM_EN_3__SHIFT 0xe |
| 7323 | #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7 |
| 7324 | #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0 |
| 7325 | #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8 |
| 7326 | #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3 |
| 7327 | #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3_MASK 0x40 |
| 7328 | #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3__SHIFT 0x6 |
| 7329 | #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80 |
| 7330 | #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7 |
| 7331 | #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100 |
| 7332 | #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8 |
| 7333 | #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200 |
| 7334 | #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9 |
| 7335 | #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3_MASK 0x3fc00 |
| 7336 | #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3__SHIFT 0xa |
| 7337 | #define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff |
| 7338 | #define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0 |
| 7339 | #define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00 |
| 7340 | #define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa |
| 7341 | #define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000 |
| 7342 | #define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc |
| 7343 | #define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000 |
| 7344 | #define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd |
| 7345 | #define PB1_RX_LANE4_CTRL_REG0__RX_TERM_EN_4_MASK 0x4000 |
| 7346 | #define PB1_RX_LANE4_CTRL_REG0__RX_TERM_EN_4__SHIFT 0xe |
| 7347 | #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7 |
| 7348 | #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0 |
| 7349 | #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8 |
| 7350 | #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3 |
| 7351 | #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4_MASK 0x40 |
| 7352 | #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4__SHIFT 0x6 |
| 7353 | #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80 |
| 7354 | #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7 |
| 7355 | #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100 |
| 7356 | #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8 |
| 7357 | #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200 |
| 7358 | #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9 |
| 7359 | #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4_MASK 0x3fc00 |
| 7360 | #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4__SHIFT 0xa |
| 7361 | #define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff |
| 7362 | #define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0 |
| 7363 | #define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00 |
| 7364 | #define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa |
| 7365 | #define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000 |
| 7366 | #define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc |
| 7367 | #define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000 |
| 7368 | #define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd |
| 7369 | #define PB1_RX_LANE5_CTRL_REG0__RX_TERM_EN_5_MASK 0x4000 |
| 7370 | #define PB1_RX_LANE5_CTRL_REG0__RX_TERM_EN_5__SHIFT 0xe |
| 7371 | #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7 |
| 7372 | #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0 |
| 7373 | #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8 |
| 7374 | #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3 |
| 7375 | #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5_MASK 0x40 |
| 7376 | #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5__SHIFT 0x6 |
| 7377 | #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80 |
| 7378 | #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7 |
| 7379 | #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100 |
| 7380 | #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8 |
| 7381 | #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200 |
| 7382 | #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9 |
| 7383 | #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5_MASK 0x3fc00 |
| 7384 | #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5__SHIFT 0xa |
| 7385 | #define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff |
| 7386 | #define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0 |
| 7387 | #define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00 |
| 7388 | #define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa |
| 7389 | #define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000 |
| 7390 | #define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc |
| 7391 | #define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000 |
| 7392 | #define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd |
| 7393 | #define PB1_RX_LANE6_CTRL_REG0__RX_TERM_EN_6_MASK 0x4000 |
| 7394 | #define PB1_RX_LANE6_CTRL_REG0__RX_TERM_EN_6__SHIFT 0xe |
| 7395 | #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7 |
| 7396 | #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0 |
| 7397 | #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8 |
| 7398 | #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3 |
| 7399 | #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6_MASK 0x40 |
| 7400 | #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6__SHIFT 0x6 |
| 7401 | #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80 |
| 7402 | #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7 |
| 7403 | #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100 |
| 7404 | #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8 |
| 7405 | #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200 |
| 7406 | #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9 |
| 7407 | #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6_MASK 0x3fc00 |
| 7408 | #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6__SHIFT 0xa |
| 7409 | #define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff |
| 7410 | #define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0 |
| 7411 | #define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00 |
| 7412 | #define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa |
| 7413 | #define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000 |
| 7414 | #define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc |
| 7415 | #define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000 |
| 7416 | #define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd |
| 7417 | #define PB1_RX_LANE7_CTRL_REG0__RX_TERM_EN_7_MASK 0x4000 |
| 7418 | #define PB1_RX_LANE7_CTRL_REG0__RX_TERM_EN_7__SHIFT 0xe |
| 7419 | #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7 |
| 7420 | #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0 |
| 7421 | #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8 |
| 7422 | #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3 |
| 7423 | #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7_MASK 0x40 |
| 7424 | #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7__SHIFT 0x6 |
| 7425 | #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80 |
| 7426 | #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7 |
| 7427 | #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100 |
| 7428 | #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8 |
| 7429 | #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200 |
| 7430 | #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9 |
| 7431 | #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7_MASK 0x3fc00 |
| 7432 | #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7__SHIFT 0xa |
| 7433 | #define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff |
| 7434 | #define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0 |
| 7435 | #define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00 |
| 7436 | #define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa |
| 7437 | #define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000 |
| 7438 | #define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc |
| 7439 | #define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000 |
| 7440 | #define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd |
| 7441 | #define PB1_RX_LANE8_CTRL_REG0__RX_TERM_EN_8_MASK 0x4000 |
| 7442 | #define PB1_RX_LANE8_CTRL_REG0__RX_TERM_EN_8__SHIFT 0xe |
| 7443 | #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7 |
| 7444 | #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0 |
| 7445 | #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8 |
| 7446 | #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3 |
| 7447 | #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8_MASK 0x40 |
| 7448 | #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8__SHIFT 0x6 |
| 7449 | #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80 |
| 7450 | #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7 |
| 7451 | #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100 |
| 7452 | #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8 |
| 7453 | #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200 |
| 7454 | #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9 |
| 7455 | #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8_MASK 0x3fc00 |
| 7456 | #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8__SHIFT 0xa |
| 7457 | #define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff |
| 7458 | #define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0 |
| 7459 | #define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00 |
| 7460 | #define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa |
| 7461 | #define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000 |
| 7462 | #define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc |
| 7463 | #define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000 |
| 7464 | #define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd |
| 7465 | #define PB1_RX_LANE9_CTRL_REG0__RX_TERM_EN_9_MASK 0x4000 |
| 7466 | #define PB1_RX_LANE9_CTRL_REG0__RX_TERM_EN_9__SHIFT 0xe |
| 7467 | #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7 |
| 7468 | #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0 |
| 7469 | #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8 |
| 7470 | #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3 |
| 7471 | #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9_MASK 0x40 |
| 7472 | #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9__SHIFT 0x6 |
| 7473 | #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80 |
| 7474 | #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7 |
| 7475 | #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100 |
| 7476 | #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8 |
| 7477 | #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200 |
| 7478 | #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9 |
| 7479 | #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9_MASK 0x3fc00 |
| 7480 | #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9__SHIFT 0xa |
| 7481 | #define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff |
| 7482 | #define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0 |
| 7483 | #define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00 |
| 7484 | #define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa |
| 7485 | #define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000 |
| 7486 | #define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc |
| 7487 | #define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000 |
| 7488 | #define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd |
| 7489 | #define PB1_RX_LANE10_CTRL_REG0__RX_TERM_EN_10_MASK 0x4000 |
| 7490 | #define PB1_RX_LANE10_CTRL_REG0__RX_TERM_EN_10__SHIFT 0xe |
| 7491 | #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7 |
| 7492 | #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0 |
| 7493 | #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8 |
| 7494 | #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3 |
| 7495 | #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10_MASK 0x40 |
| 7496 | #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10__SHIFT 0x6 |
| 7497 | #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80 |
| 7498 | #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7 |
| 7499 | #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100 |
| 7500 | #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8 |
| 7501 | #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200 |
| 7502 | #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9 |
| 7503 | #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10_MASK 0x3fc00 |
| 7504 | #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10__SHIFT 0xa |
| 7505 | #define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff |
| 7506 | #define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0 |
| 7507 | #define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00 |
| 7508 | #define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa |
| 7509 | #define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000 |
| 7510 | #define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc |
| 7511 | #define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000 |
| 7512 | #define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd |
| 7513 | #define PB1_RX_LANE11_CTRL_REG0__RX_TERM_EN_11_MASK 0x4000 |
| 7514 | #define PB1_RX_LANE11_CTRL_REG0__RX_TERM_EN_11__SHIFT 0xe |
| 7515 | #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7 |
| 7516 | #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0 |
| 7517 | #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8 |
| 7518 | #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3 |
| 7519 | #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11_MASK 0x40 |
| 7520 | #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11__SHIFT 0x6 |
| 7521 | #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80 |
| 7522 | #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7 |
| 7523 | #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100 |
| 7524 | #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8 |
| 7525 | #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200 |
| 7526 | #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9 |
| 7527 | #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11_MASK 0x3fc00 |
| 7528 | #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11__SHIFT 0xa |
| 7529 | #define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff |
| 7530 | #define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0 |
| 7531 | #define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00 |
| 7532 | #define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa |
| 7533 | #define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000 |
| 7534 | #define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc |
| 7535 | #define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000 |
| 7536 | #define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd |
| 7537 | #define PB1_RX_LANE12_CTRL_REG0__RX_TERM_EN_12_MASK 0x4000 |
| 7538 | #define PB1_RX_LANE12_CTRL_REG0__RX_TERM_EN_12__SHIFT 0xe |
| 7539 | #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7 |
| 7540 | #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0 |
| 7541 | #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8 |
| 7542 | #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3 |
| 7543 | #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12_MASK 0x40 |
| 7544 | #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12__SHIFT 0x6 |
| 7545 | #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80 |
| 7546 | #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7 |
| 7547 | #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100 |
| 7548 | #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8 |
| 7549 | #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200 |
| 7550 | #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9 |
| 7551 | #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12_MASK 0x3fc00 |
| 7552 | #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12__SHIFT 0xa |
| 7553 | #define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff |
| 7554 | #define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0 |
| 7555 | #define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00 |
| 7556 | #define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa |
| 7557 | #define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000 |
| 7558 | #define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc |
| 7559 | #define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000 |
| 7560 | #define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd |
| 7561 | #define PB1_RX_LANE13_CTRL_REG0__RX_TERM_EN_13_MASK 0x4000 |
| 7562 | #define PB1_RX_LANE13_CTRL_REG0__RX_TERM_EN_13__SHIFT 0xe |
| 7563 | #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7 |
| 7564 | #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0 |
| 7565 | #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8 |
| 7566 | #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3 |
| 7567 | #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13_MASK 0x40 |
| 7568 | #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13__SHIFT 0x6 |
| 7569 | #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80 |
| 7570 | #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7 |
| 7571 | #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100 |
| 7572 | #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8 |
| 7573 | #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200 |
| 7574 | #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9 |
| 7575 | #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13_MASK 0x3fc00 |
| 7576 | #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13__SHIFT 0xa |
| 7577 | #define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff |
| 7578 | #define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0 |
| 7579 | #define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00 |
| 7580 | #define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa |
| 7581 | #define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000 |
| 7582 | #define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc |
| 7583 | #define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000 |
| 7584 | #define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd |
| 7585 | #define PB1_RX_LANE14_CTRL_REG0__RX_TERM_EN_14_MASK 0x4000 |
| 7586 | #define PB1_RX_LANE14_CTRL_REG0__RX_TERM_EN_14__SHIFT 0xe |
| 7587 | #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7 |
| 7588 | #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0 |
| 7589 | #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8 |
| 7590 | #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3 |
| 7591 | #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14_MASK 0x40 |
| 7592 | #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14__SHIFT 0x6 |
| 7593 | #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80 |
| 7594 | #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7 |
| 7595 | #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100 |
| 7596 | #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8 |
| 7597 | #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200 |
| 7598 | #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9 |
| 7599 | #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14_MASK 0x3fc00 |
| 7600 | #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14__SHIFT 0xa |
| 7601 | #define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff |
| 7602 | #define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0 |
| 7603 | #define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00 |
| 7604 | #define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa |
| 7605 | #define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000 |
| 7606 | #define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc |
| 7607 | #define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000 |
| 7608 | #define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd |
| 7609 | #define PB1_RX_LANE15_CTRL_REG0__RX_TERM_EN_15_MASK 0x4000 |
| 7610 | #define PB1_RX_LANE15_CTRL_REG0__RX_TERM_EN_15__SHIFT 0xe |
| 7611 | #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7 |
| 7612 | #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0 |
| 7613 | #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8 |
| 7614 | #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3 |
| 7615 | #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15_MASK 0x40 |
| 7616 | #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15__SHIFT 0x6 |
| 7617 | #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80 |
| 7618 | #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7 |
| 7619 | #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100 |
| 7620 | #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8 |
| 7621 | #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200 |
| 7622 | #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9 |
| 7623 | #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15_MASK 0x3fc00 |
| 7624 | #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15__SHIFT 0xa |
| 7625 | #define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7 |
| 7626 | #define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0 |
| 7627 | #define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38 |
| 7628 | #define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3 |
| 7629 | #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700 |
| 7630 | #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8 |
| 7631 | #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800 |
| 7632 | #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb |
| 7633 | #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000 |
| 7634 | #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe |
| 7635 | #define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000 |
| 7636 | #define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11 |
| 7637 | #define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000 |
| 7638 | #define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13 |
| 7639 | #define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000 |
| 7640 | #define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14 |
| 7641 | #define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000 |
| 7642 | #define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15 |
| 7643 | #define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000 |
| 7644 | #define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16 |
| 7645 | #define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000 |
| 7646 | #define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17 |
| 7647 | #define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4_MASK 0x1000000 |
| 7648 | #define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4__SHIFT 0x18 |
| 7649 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1 |
| 7650 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0 |
| 7651 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2 |
| 7652 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1 |
| 7653 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4 |
| 7654 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2 |
| 7655 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8 |
| 7656 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3 |
| 7657 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10 |
| 7658 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4 |
| 7659 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20 |
| 7660 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5 |
| 7661 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40 |
| 7662 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6 |
| 7663 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80 |
| 7664 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7 |
| 7665 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100 |
| 7666 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8 |
| 7667 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200 |
| 7668 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9 |
| 7669 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400 |
| 7670 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa |
| 7671 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800 |
| 7672 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb |
| 7673 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000 |
| 7674 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc |
| 7675 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000 |
| 7676 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd |
| 7677 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000 |
| 7678 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe |
| 7679 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000 |
| 7680 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf |
| 7681 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000 |
| 7682 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10 |
| 7683 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000 |
| 7684 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11 |
| 7685 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000 |
| 7686 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12 |
| 7687 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000 |
| 7688 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13 |
| 7689 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000 |
| 7690 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14 |
| 7691 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000 |
| 7692 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15 |
| 7693 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000 |
| 7694 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16 |
| 7695 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000 |
| 7696 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17 |
| 7697 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000 |
| 7698 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18 |
| 7699 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000 |
| 7700 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19 |
| 7701 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000 |
| 7702 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a |
| 7703 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000 |
| 7704 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b |
| 7705 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000 |
| 7706 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c |
| 7707 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000 |
| 7708 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d |
| 7709 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000 |
| 7710 | #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e |
| 7711 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3_MASK 0x1 |
| 7712 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3__SHIFT 0x0 |
| 7713 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK 0x2 |
| 7714 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7__SHIFT 0x1 |
| 7715 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11_MASK 0x4 |
| 7716 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT 0x2 |
| 7717 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15_MASK 0x8 |
| 7718 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15__SHIFT 0x3 |
| 7719 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3_MASK 0x100 |
| 7720 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3__SHIFT 0x8 |
| 7721 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7_MASK 0x200 |
| 7722 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7__SHIFT 0x9 |
| 7723 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11_MASK 0x400 |
| 7724 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11__SHIFT 0xa |
| 7725 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15_MASK 0x800 |
| 7726 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15__SHIFT 0xb |
| 7727 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3_MASK 0x1000 |
| 7728 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3__SHIFT 0xc |
| 7729 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7_MASK 0x2000 |
| 7730 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7__SHIFT 0xd |
| 7731 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11_MASK 0x4000 |
| 7732 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11__SHIFT 0xe |
| 7733 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15_MASK 0x8000 |
| 7734 | #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15__SHIFT 0xf |
| 7735 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1 |
| 7736 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0 |
| 7737 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2 |
| 7738 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1 |
| 7739 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4 |
| 7740 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2 |
| 7741 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8 |
| 7742 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3 |
| 7743 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10 |
| 7744 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4 |
| 7745 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20 |
| 7746 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5 |
| 7747 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40 |
| 7748 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6 |
| 7749 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80 |
| 7750 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7 |
| 7751 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100 |
| 7752 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8 |
| 7753 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200 |
| 7754 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9 |
| 7755 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400 |
| 7756 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa |
| 7757 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800 |
| 7758 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb |
| 7759 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000 |
| 7760 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc |
| 7761 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000 |
| 7762 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd |
| 7763 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000 |
| 7764 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe |
| 7765 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000 |
| 7766 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf |
| 7767 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000 |
| 7768 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10 |
| 7769 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000 |
| 7770 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11 |
| 7771 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000 |
| 7772 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12 |
| 7773 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000 |
| 7774 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13 |
| 7775 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000 |
| 7776 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14 |
| 7777 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000 |
| 7778 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15 |
| 7779 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000 |
| 7780 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16 |
| 7781 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000 |
| 7782 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17 |
| 7783 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000 |
| 7784 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18 |
| 7785 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000 |
| 7786 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19 |
| 7787 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000 |
| 7788 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a |
| 7789 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000 |
| 7790 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b |
| 7791 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000 |
| 7792 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c |
| 7793 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000 |
| 7794 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d |
| 7795 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000 |
| 7796 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e |
| 7797 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000 |
| 7798 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f |
| 7799 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1 |
| 7800 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0 |
| 7801 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2 |
| 7802 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1 |
| 7803 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4 |
| 7804 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2 |
| 7805 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8 |
| 7806 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3 |
| 7807 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10 |
| 7808 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4 |
| 7809 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20 |
| 7810 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5 |
| 7811 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40 |
| 7812 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6 |
| 7813 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80 |
| 7814 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7 |
| 7815 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100 |
| 7816 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8 |
| 7817 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200 |
| 7818 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9 |
| 7819 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400 |
| 7820 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa |
| 7821 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800 |
| 7822 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb |
| 7823 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000 |
| 7824 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc |
| 7825 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000 |
| 7826 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd |
| 7827 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000 |
| 7828 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe |
| 7829 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000 |
| 7830 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf |
| 7831 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000 |
| 7832 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10 |
| 7833 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000 |
| 7834 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11 |
| 7835 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000 |
| 7836 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12 |
| 7837 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000 |
| 7838 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13 |
| 7839 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000 |
| 7840 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14 |
| 7841 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000 |
| 7842 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15 |
| 7843 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000 |
| 7844 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16 |
| 7845 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000 |
| 7846 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17 |
| 7847 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000 |
| 7848 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18 |
| 7849 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000 |
| 7850 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19 |
| 7851 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000 |
| 7852 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a |
| 7853 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000 |
| 7854 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b |
| 7855 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000 |
| 7856 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c |
| 7857 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000 |
| 7858 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d |
| 7859 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000 |
| 7860 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e |
| 7861 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000 |
| 7862 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f |
| 7863 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1 |
| 7864 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0 |
| 7865 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2 |
| 7866 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1 |
| 7867 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4 |
| 7868 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2 |
| 7869 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8 |
| 7870 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3 |
| 7871 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10 |
| 7872 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4 |
| 7873 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20 |
| 7874 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5 |
| 7875 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40 |
| 7876 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6 |
| 7877 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80 |
| 7878 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7 |
| 7879 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100 |
| 7880 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8 |
| 7881 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200 |
| 7882 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9 |
| 7883 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400 |
| 7884 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa |
| 7885 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800 |
| 7886 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb |
| 7887 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000 |
| 7888 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc |
| 7889 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000 |
| 7890 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd |
| 7891 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000 |
| 7892 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe |
| 7893 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000 |
| 7894 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf |
| 7895 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000 |
| 7896 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10 |
| 7897 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000 |
| 7898 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11 |
| 7899 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000 |
| 7900 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12 |
| 7901 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000 |
| 7902 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13 |
| 7903 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000 |
| 7904 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14 |
| 7905 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000 |
| 7906 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15 |
| 7907 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000 |
| 7908 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16 |
| 7909 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000 |
| 7910 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17 |
| 7911 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000 |
| 7912 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18 |
| 7913 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000 |
| 7914 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19 |
| 7915 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000 |
| 7916 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a |
| 7917 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000 |
| 7918 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b |
| 7919 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000 |
| 7920 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c |
| 7921 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000 |
| 7922 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d |
| 7923 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000 |
| 7924 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e |
| 7925 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000 |
| 7926 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f |
| 7927 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1 |
| 7928 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0 |
| 7929 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2 |
| 7930 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1 |
| 7931 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4 |
| 7932 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2 |
| 7933 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8 |
| 7934 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3 |
| 7935 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10 |
| 7936 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4 |
| 7937 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20 |
| 7938 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5 |
| 7939 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40 |
| 7940 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6 |
| 7941 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80 |
| 7942 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7 |
| 7943 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100 |
| 7944 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8 |
| 7945 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200 |
| 7946 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9 |
| 7947 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400 |
| 7948 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa |
| 7949 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800 |
| 7950 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb |
| 7951 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000 |
| 7952 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc |
| 7953 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000 |
| 7954 | #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd |
| 7955 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7 |
| 7956 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0 |
| 7957 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8 |
| 7958 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3 |
| 7959 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0 |
| 7960 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4 |
| 7961 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100 |
| 7962 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8 |
| 7963 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00 |
| 7964 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9 |
| 7965 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000 |
| 7966 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd |
| 7967 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000 |
| 7968 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe |
| 7969 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000 |
| 7970 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13 |
| 7971 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000 |
| 7972 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14 |
| 7973 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000 |
| 7974 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19 |
| 7975 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000 |
| 7976 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a |
| 7977 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000 |
| 7978 | #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e |
| 7979 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf |
| 7980 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0 |
| 7981 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10 |
| 7982 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4 |
| 7983 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20 |
| 7984 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5 |
| 7985 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40 |
| 7986 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6 |
| 7987 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80 |
| 7988 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7 |
| 7989 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100 |
| 7990 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8 |
| 7991 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200 |
| 7992 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9 |
| 7993 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400 |
| 7994 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa |
| 7995 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800 |
| 7996 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb |
| 7997 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000 |
| 7998 | #define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc |
| 7999 | #define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000 |
| 8000 | #define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd |
| 8001 | #define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000 |
| 8002 | #define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe |
| 8003 | #define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000 |
| 8004 | #define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf |
| 8005 | #define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000 |
| 8006 | #define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19 |
| 8007 | #define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000 |
| 8008 | #define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a |
| 8009 | #define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000 |
| 8010 | #define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b |
| 8011 | #define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000 |
| 8012 | #define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c |
| 8013 | #define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000 |
| 8014 | #define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d |
| 8015 | #define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000 |
| 8016 | #define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e |
| 8017 | #define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000 |
| 8018 | #define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f |
| 8019 | #define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1 |
| 8020 | #define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0 |
| 8021 | #define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2 |
| 8022 | #define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1 |
| 8023 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4 |
| 8024 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2 |
| 8025 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8 |
| 8026 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3 |
| 8027 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10 |
| 8028 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4 |
| 8029 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20 |
| 8030 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5 |
| 8031 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40 |
| 8032 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6 |
| 8033 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80 |
| 8034 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7 |
| 8035 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100 |
| 8036 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8 |
| 8037 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200 |
| 8038 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9 |
| 8039 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400 |
| 8040 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa |
| 8041 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800 |
| 8042 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb |
| 8043 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000 |
| 8044 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc |
| 8045 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000 |
| 8046 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10 |
| 8047 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000 |
| 8048 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14 |
| 8049 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000 |
| 8050 | #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19 |
| 8051 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf |
| 8052 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0 |
| 8053 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0 |
| 8054 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4 |
| 8055 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100 |
| 8056 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8 |
| 8057 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200 |
| 8058 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9 |
| 8059 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00 |
| 8060 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa |
| 8061 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000 |
| 8062 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe |
| 8063 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000 |
| 8064 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12 |
| 8065 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000 |
| 8066 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17 |
| 8067 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000 |
| 8068 | #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c |
| 8069 | #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf |
| 8070 | #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0 |
| 8071 | #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10 |
| 8072 | #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4 |
| 8073 | #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20 |
| 8074 | #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5 |
| 8075 | #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1 |
| 8076 | #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0 |
| 8077 | #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2 |
| 8078 | #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1 |
| 8079 | #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4 |
| 8080 | #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2 |
| 8081 | #define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8 |
| 8082 | #define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3 |
| 8083 | #define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1 |
| 8084 | #define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0 |
| 8085 | #define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2 |
| 8086 | #define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1 |
| 8087 | #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4 |
| 8088 | #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2 |
| 8089 | #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8 |
| 8090 | #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3 |
| 8091 | #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10 |
| 8092 | #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4 |
| 8093 | #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20 |
| 8094 | #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5 |
| 8095 | #define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40 |
| 8096 | #define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6 |
| 8097 | #define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80 |
| 8098 | #define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7 |
| 8099 | #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7 |
| 8100 | #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0 |
| 8101 | #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70 |
| 8102 | #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4 |
| 8103 | #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80 |
| 8104 | #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7 |
| 8105 | #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300 |
| 8106 | #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8 |
| 8107 | #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00 |
| 8108 | #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa |
| 8109 | #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1 |
| 8110 | #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0 |
| 8111 | #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2 |
| 8112 | #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1 |
| 8113 | #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4 |
| 8114 | #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2 |
| 8115 | #define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8 |
| 8116 | #define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3 |
| 8117 | #define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1 |
| 8118 | #define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0 |
| 8119 | #define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2 |
| 8120 | #define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1 |
| 8121 | #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4 |
| 8122 | #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2 |
| 8123 | #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8 |
| 8124 | #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3 |
| 8125 | #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10 |
| 8126 | #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4 |
| 8127 | #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20 |
| 8128 | #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5 |
| 8129 | #define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40 |
| 8130 | #define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6 |
| 8131 | #define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80 |
| 8132 | #define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7 |
| 8133 | #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7 |
| 8134 | #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0 |
| 8135 | #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70 |
| 8136 | #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4 |
| 8137 | #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80 |
| 8138 | #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7 |
| 8139 | #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300 |
| 8140 | #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8 |
| 8141 | #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00 |
| 8142 | #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa |
| 8143 | #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1 |
| 8144 | #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0 |
| 8145 | #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2 |
| 8146 | #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1 |
| 8147 | #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4 |
| 8148 | #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2 |
| 8149 | #define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8 |
| 8150 | #define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3 |
| 8151 | #define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1 |
| 8152 | #define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0 |
| 8153 | #define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2 |
| 8154 | #define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1 |
| 8155 | #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4 |
| 8156 | #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2 |
| 8157 | #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8 |
| 8158 | #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3 |
| 8159 | #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10 |
| 8160 | #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4 |
| 8161 | #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20 |
| 8162 | #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5 |
| 8163 | #define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40 |
| 8164 | #define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6 |
| 8165 | #define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80 |
| 8166 | #define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7 |
| 8167 | #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7 |
| 8168 | #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0 |
| 8169 | #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70 |
| 8170 | #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4 |
| 8171 | #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80 |
| 8172 | #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7 |
| 8173 | #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300 |
| 8174 | #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8 |
| 8175 | #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00 |
| 8176 | #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa |
| 8177 | #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1 |
| 8178 | #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0 |
| 8179 | #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2 |
| 8180 | #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1 |
| 8181 | #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4 |
| 8182 | #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2 |
| 8183 | #define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8 |
| 8184 | #define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3 |
| 8185 | #define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1 |
| 8186 | #define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0 |
| 8187 | #define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2 |
| 8188 | #define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1 |
| 8189 | #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4 |
| 8190 | #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2 |
| 8191 | #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8 |
| 8192 | #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3 |
| 8193 | #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10 |
| 8194 | #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4 |
| 8195 | #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20 |
| 8196 | #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5 |
| 8197 | #define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40 |
| 8198 | #define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6 |
| 8199 | #define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80 |
| 8200 | #define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7 |
| 8201 | #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7 |
| 8202 | #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0 |
| 8203 | #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70 |
| 8204 | #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4 |
| 8205 | #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80 |
| 8206 | #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7 |
| 8207 | #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300 |
| 8208 | #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8 |
| 8209 | #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00 |
| 8210 | #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa |
| 8211 | #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1 |
| 8212 | #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0 |
| 8213 | #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2 |
| 8214 | #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1 |
| 8215 | #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4 |
| 8216 | #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2 |
| 8217 | #define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8 |
| 8218 | #define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3 |
| 8219 | #define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1 |
| 8220 | #define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0 |
| 8221 | #define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2 |
| 8222 | #define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1 |
| 8223 | #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4 |
| 8224 | #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2 |
| 8225 | #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8 |
| 8226 | #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3 |
| 8227 | #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10 |
| 8228 | #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4 |
| 8229 | #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20 |
| 8230 | #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5 |
| 8231 | #define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40 |
| 8232 | #define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6 |
| 8233 | #define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80 |
| 8234 | #define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7 |
| 8235 | #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7 |
| 8236 | #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0 |
| 8237 | #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70 |
| 8238 | #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4 |
| 8239 | #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80 |
| 8240 | #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7 |
| 8241 | #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300 |
| 8242 | #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8 |
| 8243 | #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00 |
| 8244 | #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa |
| 8245 | #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1 |
| 8246 | #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0 |
| 8247 | #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2 |
| 8248 | #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1 |
| 8249 | #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4 |
| 8250 | #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2 |
| 8251 | #define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8 |
| 8252 | #define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3 |
| 8253 | #define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1 |
| 8254 | #define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0 |
| 8255 | #define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2 |
| 8256 | #define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1 |
| 8257 | #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4 |
| 8258 | #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2 |
| 8259 | #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8 |
| 8260 | #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3 |
| 8261 | #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10 |
| 8262 | #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4 |
| 8263 | #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20 |
| 8264 | #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5 |
| 8265 | #define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40 |
| 8266 | #define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6 |
| 8267 | #define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80 |
| 8268 | #define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7 |
| 8269 | #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7 |
| 8270 | #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0 |
| 8271 | #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70 |
| 8272 | #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4 |
| 8273 | #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80 |
| 8274 | #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7 |
| 8275 | #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300 |
| 8276 | #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8 |
| 8277 | #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00 |
| 8278 | #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa |
| 8279 | #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1 |
| 8280 | #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0 |
| 8281 | #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2 |
| 8282 | #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1 |
| 8283 | #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4 |
| 8284 | #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2 |
| 8285 | #define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8 |
| 8286 | #define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3 |
| 8287 | #define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1 |
| 8288 | #define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0 |
| 8289 | #define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2 |
| 8290 | #define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1 |
| 8291 | #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4 |
| 8292 | #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2 |
| 8293 | #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8 |
| 8294 | #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3 |
| 8295 | #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10 |
| 8296 | #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4 |
| 8297 | #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20 |
| 8298 | #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5 |
| 8299 | #define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40 |
| 8300 | #define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6 |
| 8301 | #define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80 |
| 8302 | #define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7 |
| 8303 | #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7 |
| 8304 | #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0 |
| 8305 | #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70 |
| 8306 | #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4 |
| 8307 | #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80 |
| 8308 | #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7 |
| 8309 | #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300 |
| 8310 | #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8 |
| 8311 | #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00 |
| 8312 | #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa |
| 8313 | #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1 |
| 8314 | #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0 |
| 8315 | #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2 |
| 8316 | #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1 |
| 8317 | #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4 |
| 8318 | #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2 |
| 8319 | #define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8 |
| 8320 | #define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3 |
| 8321 | #define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1 |
| 8322 | #define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0 |
| 8323 | #define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2 |
| 8324 | #define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1 |
| 8325 | #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4 |
| 8326 | #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2 |
| 8327 | #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8 |
| 8328 | #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3 |
| 8329 | #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10 |
| 8330 | #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4 |
| 8331 | #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20 |
| 8332 | #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5 |
| 8333 | #define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40 |
| 8334 | #define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6 |
| 8335 | #define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80 |
| 8336 | #define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7 |
| 8337 | #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7 |
| 8338 | #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0 |
| 8339 | #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70 |
| 8340 | #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4 |
| 8341 | #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80 |
| 8342 | #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7 |
| 8343 | #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300 |
| 8344 | #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8 |
| 8345 | #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00 |
| 8346 | #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa |
| 8347 | #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1 |
| 8348 | #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0 |
| 8349 | #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2 |
| 8350 | #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1 |
| 8351 | #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4 |
| 8352 | #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2 |
| 8353 | #define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8 |
| 8354 | #define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3 |
| 8355 | #define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1 |
| 8356 | #define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0 |
| 8357 | #define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2 |
| 8358 | #define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1 |
| 8359 | #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4 |
| 8360 | #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2 |
| 8361 | #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8 |
| 8362 | #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3 |
| 8363 | #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10 |
| 8364 | #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4 |
| 8365 | #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20 |
| 8366 | #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5 |
| 8367 | #define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40 |
| 8368 | #define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6 |
| 8369 | #define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80 |
| 8370 | #define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7 |
| 8371 | #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7 |
| 8372 | #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0 |
| 8373 | #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70 |
| 8374 | #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4 |
| 8375 | #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80 |
| 8376 | #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7 |
| 8377 | #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300 |
| 8378 | #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8 |
| 8379 | #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00 |
| 8380 | #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa |
| 8381 | #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1 |
| 8382 | #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0 |
| 8383 | #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2 |
| 8384 | #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1 |
| 8385 | #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4 |
| 8386 | #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2 |
| 8387 | #define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8 |
| 8388 | #define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3 |
| 8389 | #define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1 |
| 8390 | #define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0 |
| 8391 | #define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2 |
| 8392 | #define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1 |
| 8393 | #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4 |
| 8394 | #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2 |
| 8395 | #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8 |
| 8396 | #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3 |
| 8397 | #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10 |
| 8398 | #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4 |
| 8399 | #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20 |
| 8400 | #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5 |
| 8401 | #define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40 |
| 8402 | #define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6 |
| 8403 | #define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80 |
| 8404 | #define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7 |
| 8405 | #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7 |
| 8406 | #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0 |
| 8407 | #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70 |
| 8408 | #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4 |
| 8409 | #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80 |
| 8410 | #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7 |
| 8411 | #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300 |
| 8412 | #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8 |
| 8413 | #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00 |
| 8414 | #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa |
| 8415 | #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1 |
| 8416 | #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0 |
| 8417 | #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2 |
| 8418 | #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1 |
| 8419 | #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4 |
| 8420 | #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2 |
| 8421 | #define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8 |
| 8422 | #define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3 |
| 8423 | #define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1 |
| 8424 | #define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0 |
| 8425 | #define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2 |
| 8426 | #define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1 |
| 8427 | #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4 |
| 8428 | #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2 |
| 8429 | #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8 |
| 8430 | #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3 |
| 8431 | #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10 |
| 8432 | #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4 |
| 8433 | #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20 |
| 8434 | #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5 |
| 8435 | #define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40 |
| 8436 | #define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6 |
| 8437 | #define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80 |
| 8438 | #define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7 |
| 8439 | #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7 |
| 8440 | #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0 |
| 8441 | #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70 |
| 8442 | #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4 |
| 8443 | #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80 |
| 8444 | #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7 |
| 8445 | #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300 |
| 8446 | #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8 |
| 8447 | #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00 |
| 8448 | #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa |
| 8449 | #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1 |
| 8450 | #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0 |
| 8451 | #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2 |
| 8452 | #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1 |
| 8453 | #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4 |
| 8454 | #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2 |
| 8455 | #define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8 |
| 8456 | #define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3 |
| 8457 | #define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1 |
| 8458 | #define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0 |
| 8459 | #define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2 |
| 8460 | #define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1 |
| 8461 | #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4 |
| 8462 | #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2 |
| 8463 | #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8 |
| 8464 | #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3 |
| 8465 | #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10 |
| 8466 | #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4 |
| 8467 | #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20 |
| 8468 | #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5 |
| 8469 | #define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40 |
| 8470 | #define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6 |
| 8471 | #define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80 |
| 8472 | #define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7 |
| 8473 | #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7 |
| 8474 | #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0 |
| 8475 | #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70 |
| 8476 | #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4 |
| 8477 | #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80 |
| 8478 | #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7 |
| 8479 | #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300 |
| 8480 | #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8 |
| 8481 | #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00 |
| 8482 | #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa |
| 8483 | #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1 |
| 8484 | #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0 |
| 8485 | #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2 |
| 8486 | #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1 |
| 8487 | #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4 |
| 8488 | #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2 |
| 8489 | #define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8 |
| 8490 | #define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3 |
| 8491 | #define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1 |
| 8492 | #define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0 |
| 8493 | #define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2 |
| 8494 | #define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1 |
| 8495 | #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4 |
| 8496 | #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2 |
| 8497 | #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8 |
| 8498 | #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3 |
| 8499 | #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10 |
| 8500 | #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4 |
| 8501 | #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20 |
| 8502 | #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5 |
| 8503 | #define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40 |
| 8504 | #define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6 |
| 8505 | #define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80 |
| 8506 | #define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7 |
| 8507 | #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7 |
| 8508 | #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0 |
| 8509 | #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70 |
| 8510 | #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4 |
| 8511 | #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80 |
| 8512 | #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7 |
| 8513 | #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300 |
| 8514 | #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8 |
| 8515 | #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00 |
| 8516 | #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa |
| 8517 | #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1 |
| 8518 | #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0 |
| 8519 | #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2 |
| 8520 | #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1 |
| 8521 | #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4 |
| 8522 | #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2 |
| 8523 | #define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8 |
| 8524 | #define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3 |
| 8525 | #define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1 |
| 8526 | #define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0 |
| 8527 | #define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2 |
| 8528 | #define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1 |
| 8529 | #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4 |
| 8530 | #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2 |
| 8531 | #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8 |
| 8532 | #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3 |
| 8533 | #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10 |
| 8534 | #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4 |
| 8535 | #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20 |
| 8536 | #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5 |
| 8537 | #define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40 |
| 8538 | #define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6 |
| 8539 | #define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80 |
| 8540 | #define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7 |
| 8541 | #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7 |
| 8542 | #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0 |
| 8543 | #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70 |
| 8544 | #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4 |
| 8545 | #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80 |
| 8546 | #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7 |
| 8547 | #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300 |
| 8548 | #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8 |
| 8549 | #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00 |
| 8550 | #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa |
| 8551 | #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1 |
| 8552 | #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0 |
| 8553 | #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2 |
| 8554 | #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1 |
| 8555 | #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4 |
| 8556 | #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2 |
| 8557 | #define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8 |
| 8558 | #define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3 |
| 8559 | #define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1 |
| 8560 | #define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0 |
| 8561 | #define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2 |
| 8562 | #define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1 |
| 8563 | #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4 |
| 8564 | #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2 |
| 8565 | #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8 |
| 8566 | #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3 |
| 8567 | #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10 |
| 8568 | #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4 |
| 8569 | #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20 |
| 8570 | #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5 |
| 8571 | #define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40 |
| 8572 | #define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6 |
| 8573 | #define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80 |
| 8574 | #define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7 |
| 8575 | #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7 |
| 8576 | #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0 |
| 8577 | #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70 |
| 8578 | #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4 |
| 8579 | #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80 |
| 8580 | #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7 |
| 8581 | #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300 |
| 8582 | #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8 |
| 8583 | #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00 |
| 8584 | #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa |
| 8585 | #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1 |
| 8586 | #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0 |
| 8587 | #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2 |
| 8588 | #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1 |
| 8589 | #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4 |
| 8590 | #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2 |
| 8591 | #define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8 |
| 8592 | #define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3 |
| 8593 | #define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1 |
| 8594 | #define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0 |
| 8595 | #define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2 |
| 8596 | #define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1 |
| 8597 | #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4 |
| 8598 | #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2 |
| 8599 | #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8 |
| 8600 | #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3 |
| 8601 | #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10 |
| 8602 | #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4 |
| 8603 | #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20 |
| 8604 | #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5 |
| 8605 | #define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40 |
| 8606 | #define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6 |
| 8607 | #define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80 |
| 8608 | #define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7 |
| 8609 | #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7 |
| 8610 | #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0 |
| 8611 | #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70 |
| 8612 | #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4 |
| 8613 | #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80 |
| 8614 | #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7 |
| 8615 | #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300 |
| 8616 | #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8 |
| 8617 | #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00 |
| 8618 | #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa |
| 8619 | #define PB0_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff |
| 8620 | #define PB0_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0 |
| 8621 | #define PB0_PIF_HW_DEBUG__HW_00_DEBUG_MASK 0x1 |
| 8622 | #define PB0_PIF_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 |
| 8623 | #define PB0_PIF_HW_DEBUG__HW_01_DEBUG_MASK 0x2 |
| 8624 | #define PB0_PIF_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 |
| 8625 | #define PB0_PIF_HW_DEBUG__HW_02_DEBUG_MASK 0x4 |
| 8626 | #define PB0_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 |
| 8627 | #define PB0_PIF_HW_DEBUG__HW_03_DEBUG_MASK 0x8 |
| 8628 | #define PB0_PIF_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 |
| 8629 | #define PB0_PIF_HW_DEBUG__HW_04_DEBUG_MASK 0x10 |
| 8630 | #define PB0_PIF_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 |
| 8631 | #define PB0_PIF_HW_DEBUG__HW_05_DEBUG_MASK 0x20 |
| 8632 | #define PB0_PIF_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 |
| 8633 | #define PB0_PIF_HW_DEBUG__HW_06_DEBUG_MASK 0x40 |
| 8634 | #define PB0_PIF_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 |
| 8635 | #define PB0_PIF_HW_DEBUG__HW_07_DEBUG_MASK 0x80 |
| 8636 | #define PB0_PIF_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 |
| 8637 | #define PB0_PIF_HW_DEBUG__HW_08_DEBUG_MASK 0x100 |
| 8638 | #define PB0_PIF_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 |
| 8639 | #define PB0_PIF_HW_DEBUG__HW_09_DEBUG_MASK 0x200 |
| 8640 | #define PB0_PIF_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 |
| 8641 | #define PB0_PIF_HW_DEBUG__HW_10_DEBUG_MASK 0x400 |
| 8642 | #define PB0_PIF_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa |
| 8643 | #define PB0_PIF_HW_DEBUG__HW_11_DEBUG_MASK 0x800 |
| 8644 | #define PB0_PIF_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb |
| 8645 | #define PB0_PIF_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 |
| 8646 | #define PB0_PIF_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc |
| 8647 | #define PB0_PIF_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 |
| 8648 | #define PB0_PIF_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd |
| 8649 | #define PB0_PIF_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 |
| 8650 | #define PB0_PIF_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe |
| 8651 | #define PB0_PIF_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 |
| 8652 | #define PB0_PIF_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf |
| 8653 | #define PB0_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2 |
| 8654 | #define PB0_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1 |
| 8655 | #define PB0_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4 |
| 8656 | #define PB0_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2 |
| 8657 | #define PB0_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8 |
| 8658 | #define PB0_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3 |
| 8659 | #define PB0_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10 |
| 8660 | #define PB0_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4 |
| 8661 | #define PB0_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20 |
| 8662 | #define PB0_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5 |
| 8663 | #define PB0_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0 |
| 8664 | #define PB0_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6 |
| 8665 | #define PB0_PIF_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300 |
| 8666 | #define PB0_PIF_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8 |
| 8667 | #define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400 |
| 8668 | #define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa |
| 8669 | #define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800 |
| 8670 | #define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb |
| 8671 | #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000 |
| 8672 | #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc |
| 8673 | #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000 |
| 8674 | #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd |
| 8675 | #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000 |
| 8676 | #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe |
| 8677 | #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000 |
| 8678 | #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf |
| 8679 | #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000 |
| 8680 | #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10 |
| 8681 | #define PB0_PIF_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1 |
| 8682 | #define PB0_PIF_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0 |
| 8683 | #define PB0_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2 |
| 8684 | #define PB0_PIF_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1 |
| 8685 | #define PB0_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4 |
| 8686 | #define PB0_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2 |
| 8687 | #define PB0_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8 |
| 8688 | #define PB0_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3 |
| 8689 | #define PB0_PIF_CTRL__PHY_RST_PWROK_VDD_MASK 0x10 |
| 8690 | #define PB0_PIF_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4 |
| 8691 | #define PB0_PIF_CTRL__PIF_PLL_STATUS_MASK 0xc0 |
| 8692 | #define PB0_PIF_CTRL__PIF_PLL_STATUS__SHIFT 0x6 |
| 8693 | #define PB0_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100 |
| 8694 | #define PB0_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8 |
| 8695 | #define PB0_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200 |
| 8696 | #define PB0_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9 |
| 8697 | #define PB0_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400 |
| 8698 | #define PB0_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa |
| 8699 | #define PB0_PIF_CTRL__PIF_PG_EXIT_MODE_MASK 0x800 |
| 8700 | #define PB0_PIF_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb |
| 8701 | #define PB0_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000 |
| 8702 | #define PB0_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc |
| 8703 | #define PB0_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000 |
| 8704 | #define PB0_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd |
| 8705 | #define PB0_PIF_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000 |
| 8706 | #define PB0_PIF_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe |
| 8707 | #define PB0_PIF_TX_CTRL__TXPWR_IN_S2_MASK 0x7 |
| 8708 | #define PB0_PIF_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0 |
| 8709 | #define PB0_PIF_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38 |
| 8710 | #define PB0_PIF_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3 |
| 8711 | #define PB0_PIF_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0 |
| 8712 | #define PB0_PIF_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6 |
| 8713 | #define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00 |
| 8714 | #define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9 |
| 8715 | #define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000 |
| 8716 | #define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc |
| 8717 | #define PB0_PIF_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000 |
| 8718 | #define PB0_PIF_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf |
| 8719 | #define PB0_PIF_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000 |
| 8720 | #define PB0_PIF_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12 |
| 8721 | #define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000 |
| 8722 | #define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15 |
| 8723 | #define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000 |
| 8724 | #define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16 |
| 8725 | #define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000 |
| 8726 | #define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17 |
| 8727 | #define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000 |
| 8728 | #define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18 |
| 8729 | #define PB0_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7 |
| 8730 | #define PB0_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0 |
| 8731 | #define PB0_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38 |
| 8732 | #define PB0_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3 |
| 8733 | #define PB0_PIF_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0 |
| 8734 | #define PB0_PIF_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6 |
| 8735 | #define PB0_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200 |
| 8736 | #define PB0_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 |
| 8737 | #define PB0_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 |
| 8738 | #define PB0_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa |
| 8739 | #define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000 |
| 8740 | #define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10 |
| 8741 | #define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000 |
| 8742 | #define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11 |
| 8743 | #define PB0_PIF_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000 |
| 8744 | #define PB0_PIF_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15 |
| 8745 | #define PB0_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000 |
| 8746 | #define PB0_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16 |
| 8747 | #define PB0_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000 |
| 8748 | #define PB0_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19 |
| 8749 | #define PB0_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000 |
| 8750 | #define PB0_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a |
| 8751 | #define PB0_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000 |
| 8752 | #define PB0_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d |
| 8753 | #define PB0_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000 |
| 8754 | #define PB0_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e |
| 8755 | #define PB0_PIF_RX_CTRL__RXPWR_IN_S2_MASK 0x7 |
| 8756 | #define PB0_PIF_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0 |
| 8757 | #define PB0_PIF_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38 |
| 8758 | #define PB0_PIF_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3 |
| 8759 | #define PB0_PIF_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0 |
| 8760 | #define PB0_PIF_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6 |
| 8761 | #define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00 |
| 8762 | #define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9 |
| 8763 | #define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000 |
| 8764 | #define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc |
| 8765 | #define PB0_PIF_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000 |
| 8766 | #define PB0_PIF_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf |
| 8767 | #define PB0_PIF_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000 |
| 8768 | #define PB0_PIF_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12 |
| 8769 | #define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000 |
| 8770 | #define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15 |
| 8771 | #define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000 |
| 8772 | #define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16 |
| 8773 | #define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000 |
| 8774 | #define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17 |
| 8775 | #define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000 |
| 8776 | #define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18 |
| 8777 | #define PB0_PIF_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000 |
| 8778 | #define PB0_PIF_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19 |
| 8779 | #define PB0_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000 |
| 8780 | #define PB0_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a |
| 8781 | #define PB0_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7 |
| 8782 | #define PB0_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0 |
| 8783 | #define PB0_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38 |
| 8784 | #define PB0_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3 |
| 8785 | #define PB0_PIF_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0 |
| 8786 | #define PB0_PIF_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6 |
| 8787 | #define PB0_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200 |
| 8788 | #define PB0_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 |
| 8789 | #define PB0_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 |
| 8790 | #define PB0_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa |
| 8791 | #define PB0_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000 |
| 8792 | #define PB0_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10 |
| 8793 | #define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000 |
| 8794 | #define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11 |
| 8795 | #define PB0_PIF_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000 |
| 8796 | #define PB0_PIF_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13 |
| 8797 | #define PB0_PIF_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000 |
| 8798 | #define PB0_PIF_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15 |
| 8799 | #define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000 |
| 8800 | #define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18 |
| 8801 | #define PB0_PIF_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000 |
| 8802 | #define PB0_PIF_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19 |
| 8803 | #define PB0_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000 |
| 8804 | #define PB0_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b |
| 8805 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1 |
| 8806 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0 |
| 8807 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2 |
| 8808 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1 |
| 8809 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4 |
| 8810 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2 |
| 8811 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8 |
| 8812 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3 |
| 8813 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10 |
| 8814 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4 |
| 8815 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20 |
| 8816 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5 |
| 8817 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40 |
| 8818 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6 |
| 8819 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80 |
| 8820 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7 |
| 8821 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000 |
| 8822 | #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10 |
| 8823 | #define PB0_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1 |
| 8824 | #define PB0_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0 |
| 8825 | #define PB0_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2 |
| 8826 | #define PB0_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1 |
| 8827 | #define PB0_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4 |
| 8828 | #define PB0_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2 |
| 8829 | #define PB0_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8 |
| 8830 | #define PB0_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3 |
| 8831 | #define PB0_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10 |
| 8832 | #define PB0_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4 |
| 8833 | #define PB0_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20 |
| 8834 | #define PB0_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5 |
| 8835 | #define PB0_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40 |
| 8836 | #define PB0_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6 |
| 8837 | #define PB0_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80 |
| 8838 | #define PB0_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7 |
| 8839 | #define PB0_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100 |
| 8840 | #define PB0_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8 |
| 8841 | #define PB0_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200 |
| 8842 | #define PB0_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9 |
| 8843 | #define PB0_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400 |
| 8844 | #define PB0_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa |
| 8845 | #define PB0_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800 |
| 8846 | #define PB0_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb |
| 8847 | #define PB0_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000 |
| 8848 | #define PB0_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10 |
| 8849 | #define PB0_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000 |
| 8850 | #define PB0_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11 |
| 8851 | #define PB0_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000 |
| 8852 | #define PB0_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14 |
| 8853 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1 |
| 8854 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0 |
| 8855 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2 |
| 8856 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1 |
| 8857 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4 |
| 8858 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2 |
| 8859 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8 |
| 8860 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3 |
| 8861 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10 |
| 8862 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4 |
| 8863 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20 |
| 8864 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5 |
| 8865 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40 |
| 8866 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6 |
| 8867 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80 |
| 8868 | #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7 |
| 8869 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100 |
| 8870 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8 |
| 8871 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200 |
| 8872 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9 |
| 8873 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400 |
| 8874 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa |
| 8875 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800 |
| 8876 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb |
| 8877 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000 |
| 8878 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc |
| 8879 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000 |
| 8880 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd |
| 8881 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000 |
| 8882 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe |
| 8883 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000 |
| 8884 | #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf |
| 8885 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000 |
| 8886 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10 |
| 8887 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000 |
| 8888 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11 |
| 8889 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000 |
| 8890 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12 |
| 8891 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000 |
| 8892 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13 |
| 8893 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000 |
| 8894 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14 |
| 8895 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000 |
| 8896 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15 |
| 8897 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000 |
| 8898 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16 |
| 8899 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000 |
| 8900 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17 |
| 8901 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000 |
| 8902 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18 |
| 8903 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000 |
| 8904 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19 |
| 8905 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000 |
| 8906 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a |
| 8907 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000 |
| 8908 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b |
| 8909 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000 |
| 8910 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c |
| 8911 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000 |
| 8912 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d |
| 8913 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000 |
| 8914 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e |
| 8915 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000 |
| 8916 | #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f |
| 8917 | #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3 |
| 8918 | #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0 |
| 8919 | #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc |
| 8920 | #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2 |
| 8921 | #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10 |
| 8922 | #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4 |
| 8923 | #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60 |
| 8924 | #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5 |
| 8925 | #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80 |
| 8926 | #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7 |
| 8927 | #define PB0_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100 |
| 8928 | #define PB0_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8 |
| 8929 | #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200 |
| 8930 | #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9 |
| 8931 | #define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1 |
| 8932 | #define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0 |
| 8933 | #define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2 |
| 8934 | #define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1 |
| 8935 | #define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4 |
| 8936 | #define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2 |
| 8937 | #define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38 |
| 8938 | #define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3 |
| 8939 | #define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40 |
| 8940 | #define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6 |
| 8941 | #define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180 |
| 8942 | #define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7 |
| 8943 | #define PB0_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200 |
| 8944 | #define PB0_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9 |
| 8945 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000 |
| 8946 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10 |
| 8947 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000 |
| 8948 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11 |
| 8949 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000 |
| 8950 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12 |
| 8951 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000 |
| 8952 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13 |
| 8953 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000 |
| 8954 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14 |
| 8955 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000 |
| 8956 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15 |
| 8957 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000 |
| 8958 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16 |
| 8959 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000 |
| 8960 | #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17 |
| 8961 | #define PB0_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1 |
| 8962 | #define PB0_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0 |
| 8963 | #define PB0_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2 |
| 8964 | #define PB0_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1 |
| 8965 | #define PB0_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4 |
| 8966 | #define PB0_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2 |
| 8967 | #define PB0_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8 |
| 8968 | #define PB0_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3 |
| 8969 | #define PB0_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10 |
| 8970 | #define PB0_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4 |
| 8971 | #define PB0_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20 |
| 8972 | #define PB0_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5 |
| 8973 | #define PB0_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40 |
| 8974 | #define PB0_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6 |
| 8975 | #define PB0_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80 |
| 8976 | #define PB0_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7 |
| 8977 | #define PB0_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100 |
| 8978 | #define PB0_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8 |
| 8979 | #define PB0_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200 |
| 8980 | #define PB0_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9 |
| 8981 | #define PB0_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400 |
| 8982 | #define PB0_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa |
| 8983 | #define PB0_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800 |
| 8984 | #define PB0_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb |
| 8985 | #define PB0_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000 |
| 8986 | #define PB0_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc |
| 8987 | #define PB0_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000 |
| 8988 | #define PB0_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd |
| 8989 | #define PB0_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000 |
| 8990 | #define PB0_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe |
| 8991 | #define PB0_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000 |
| 8992 | #define PB0_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf |
| 8993 | #define PB0_PIF_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000 |
| 8994 | #define PB0_PIF_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10 |
| 8995 | #define PB0_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000 |
| 8996 | #define PB0_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11 |
| 8997 | #define PB0_PIF_LANE0_OVRD2__GANGMODE_0_MASK 0x7 |
| 8998 | #define PB0_PIF_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0 |
| 8999 | #define PB0_PIF_LANE0_OVRD2__FREQDIV_0_MASK 0x18 |
| 9000 | #define PB0_PIF_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3 |
| 9001 | #define PB0_PIF_LANE0_OVRD2__LINKSPEED_0_MASK 0x60 |
| 9002 | #define PB0_PIF_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5 |
| 9003 | #define PB0_PIF_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80 |
| 9004 | #define PB0_PIF_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7 |
| 9005 | #define PB0_PIF_LANE0_OVRD2__TXPWR_0_MASK 0x700 |
| 9006 | #define PB0_PIF_LANE0_OVRD2__TXPWR_0__SHIFT 0x8 |
| 9007 | #define PB0_PIF_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800 |
| 9008 | #define PB0_PIF_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb |
| 9009 | #define PB0_PIF_LANE0_OVRD2__RXPWR_0_MASK 0xe000 |
| 9010 | #define PB0_PIF_LANE0_OVRD2__RXPWR_0__SHIFT 0xd |
| 9011 | #define PB0_PIF_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000 |
| 9012 | #define PB0_PIF_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10 |
| 9013 | #define PB0_PIF_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000 |
| 9014 | #define PB0_PIF_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12 |
| 9015 | #define PB0_PIF_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000 |
| 9016 | #define PB0_PIF_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13 |
| 9017 | #define PB0_PIF_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000 |
| 9018 | #define PB0_PIF_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14 |
| 9019 | #define PB0_PIF_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000 |
| 9020 | #define PB0_PIF_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15 |
| 9021 | #define PB0_PIF_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000 |
| 9022 | #define PB0_PIF_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16 |
| 9023 | #define PB0_PIF_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000 |
| 9024 | #define PB0_PIF_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17 |
| 9025 | #define PB0_PIF_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000 |
| 9026 | #define PB0_PIF_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18 |
| 9027 | #define PB0_PIF_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000 |
| 9028 | #define PB0_PIF_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a |
| 9029 | #define PB0_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1 |
| 9030 | #define PB0_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0 |
| 9031 | #define PB0_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2 |
| 9032 | #define PB0_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1 |
| 9033 | #define PB0_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4 |
| 9034 | #define PB0_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2 |
| 9035 | #define PB0_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8 |
| 9036 | #define PB0_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3 |
| 9037 | #define PB0_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10 |
| 9038 | #define PB0_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4 |
| 9039 | #define PB0_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20 |
| 9040 | #define PB0_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5 |
| 9041 | #define PB0_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40 |
| 9042 | #define PB0_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6 |
| 9043 | #define PB0_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80 |
| 9044 | #define PB0_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7 |
| 9045 | #define PB0_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100 |
| 9046 | #define PB0_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8 |
| 9047 | #define PB0_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200 |
| 9048 | #define PB0_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9 |
| 9049 | #define PB0_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400 |
| 9050 | #define PB0_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa |
| 9051 | #define PB0_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800 |
| 9052 | #define PB0_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb |
| 9053 | #define PB0_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000 |
| 9054 | #define PB0_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc |
| 9055 | #define PB0_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000 |
| 9056 | #define PB0_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd |
| 9057 | #define PB0_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000 |
| 9058 | #define PB0_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe |
| 9059 | #define PB0_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000 |
| 9060 | #define PB0_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf |
| 9061 | #define PB0_PIF_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000 |
| 9062 | #define PB0_PIF_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10 |
| 9063 | #define PB0_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000 |
| 9064 | #define PB0_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11 |
| 9065 | #define PB0_PIF_LANE1_OVRD2__GANGMODE_1_MASK 0x7 |
| 9066 | #define PB0_PIF_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0 |
| 9067 | #define PB0_PIF_LANE1_OVRD2__FREQDIV_1_MASK 0x18 |
| 9068 | #define PB0_PIF_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3 |
| 9069 | #define PB0_PIF_LANE1_OVRD2__LINKSPEED_1_MASK 0x60 |
| 9070 | #define PB0_PIF_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5 |
| 9071 | #define PB0_PIF_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80 |
| 9072 | #define PB0_PIF_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7 |
| 9073 | #define PB0_PIF_LANE1_OVRD2__TXPWR_1_MASK 0x700 |
| 9074 | #define PB0_PIF_LANE1_OVRD2__TXPWR_1__SHIFT 0x8 |
| 9075 | #define PB0_PIF_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800 |
| 9076 | #define PB0_PIF_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb |
| 9077 | #define PB0_PIF_LANE1_OVRD2__RXPWR_1_MASK 0xe000 |
| 9078 | #define PB0_PIF_LANE1_OVRD2__RXPWR_1__SHIFT 0xd |
| 9079 | #define PB0_PIF_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000 |
| 9080 | #define PB0_PIF_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10 |
| 9081 | #define PB0_PIF_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000 |
| 9082 | #define PB0_PIF_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12 |
| 9083 | #define PB0_PIF_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000 |
| 9084 | #define PB0_PIF_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13 |
| 9085 | #define PB0_PIF_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000 |
| 9086 | #define PB0_PIF_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14 |
| 9087 | #define PB0_PIF_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000 |
| 9088 | #define PB0_PIF_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15 |
| 9089 | #define PB0_PIF_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000 |
| 9090 | #define PB0_PIF_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16 |
| 9091 | #define PB0_PIF_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000 |
| 9092 | #define PB0_PIF_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17 |
| 9093 | #define PB0_PIF_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000 |
| 9094 | #define PB0_PIF_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18 |
| 9095 | #define PB0_PIF_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000 |
| 9096 | #define PB0_PIF_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a |
| 9097 | #define PB0_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1 |
| 9098 | #define PB0_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0 |
| 9099 | #define PB0_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2 |
| 9100 | #define PB0_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1 |
| 9101 | #define PB0_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4 |
| 9102 | #define PB0_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2 |
| 9103 | #define PB0_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8 |
| 9104 | #define PB0_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3 |
| 9105 | #define PB0_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10 |
| 9106 | #define PB0_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4 |
| 9107 | #define PB0_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20 |
| 9108 | #define PB0_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5 |
| 9109 | #define PB0_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40 |
| 9110 | #define PB0_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6 |
| 9111 | #define PB0_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80 |
| 9112 | #define PB0_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7 |
| 9113 | #define PB0_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100 |
| 9114 | #define PB0_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8 |
| 9115 | #define PB0_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200 |
| 9116 | #define PB0_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9 |
| 9117 | #define PB0_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400 |
| 9118 | #define PB0_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa |
| 9119 | #define PB0_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800 |
| 9120 | #define PB0_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb |
| 9121 | #define PB0_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000 |
| 9122 | #define PB0_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc |
| 9123 | #define PB0_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000 |
| 9124 | #define PB0_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd |
| 9125 | #define PB0_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000 |
| 9126 | #define PB0_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe |
| 9127 | #define PB0_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000 |
| 9128 | #define PB0_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf |
| 9129 | #define PB0_PIF_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000 |
| 9130 | #define PB0_PIF_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10 |
| 9131 | #define PB0_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000 |
| 9132 | #define PB0_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11 |
| 9133 | #define PB0_PIF_LANE2_OVRD2__GANGMODE_2_MASK 0x7 |
| 9134 | #define PB0_PIF_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0 |
| 9135 | #define PB0_PIF_LANE2_OVRD2__FREQDIV_2_MASK 0x18 |
| 9136 | #define PB0_PIF_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3 |
| 9137 | #define PB0_PIF_LANE2_OVRD2__LINKSPEED_2_MASK 0x60 |
| 9138 | #define PB0_PIF_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5 |
| 9139 | #define PB0_PIF_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80 |
| 9140 | #define PB0_PIF_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7 |
| 9141 | #define PB0_PIF_LANE2_OVRD2__TXPWR_2_MASK 0x700 |
| 9142 | #define PB0_PIF_LANE2_OVRD2__TXPWR_2__SHIFT 0x8 |
| 9143 | #define PB0_PIF_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800 |
| 9144 | #define PB0_PIF_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb |
| 9145 | #define PB0_PIF_LANE2_OVRD2__RXPWR_2_MASK 0xe000 |
| 9146 | #define PB0_PIF_LANE2_OVRD2__RXPWR_2__SHIFT 0xd |
| 9147 | #define PB0_PIF_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000 |
| 9148 | #define PB0_PIF_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10 |
| 9149 | #define PB0_PIF_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000 |
| 9150 | #define PB0_PIF_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12 |
| 9151 | #define PB0_PIF_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000 |
| 9152 | #define PB0_PIF_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13 |
| 9153 | #define PB0_PIF_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000 |
| 9154 | #define PB0_PIF_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14 |
| 9155 | #define PB0_PIF_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000 |
| 9156 | #define PB0_PIF_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15 |
| 9157 | #define PB0_PIF_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000 |
| 9158 | #define PB0_PIF_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16 |
| 9159 | #define PB0_PIF_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000 |
| 9160 | #define PB0_PIF_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17 |
| 9161 | #define PB0_PIF_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000 |
| 9162 | #define PB0_PIF_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18 |
| 9163 | #define PB0_PIF_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000 |
| 9164 | #define PB0_PIF_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a |
| 9165 | #define PB0_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1 |
| 9166 | #define PB0_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0 |
| 9167 | #define PB0_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2 |
| 9168 | #define PB0_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1 |
| 9169 | #define PB0_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4 |
| 9170 | #define PB0_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2 |
| 9171 | #define PB0_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8 |
| 9172 | #define PB0_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3 |
| 9173 | #define PB0_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10 |
| 9174 | #define PB0_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4 |
| 9175 | #define PB0_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20 |
| 9176 | #define PB0_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5 |
| 9177 | #define PB0_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40 |
| 9178 | #define PB0_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6 |
| 9179 | #define PB0_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80 |
| 9180 | #define PB0_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7 |
| 9181 | #define PB0_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100 |
| 9182 | #define PB0_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8 |
| 9183 | #define PB0_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200 |
| 9184 | #define PB0_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9 |
| 9185 | #define PB0_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400 |
| 9186 | #define PB0_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa |
| 9187 | #define PB0_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800 |
| 9188 | #define PB0_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb |
| 9189 | #define PB0_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000 |
| 9190 | #define PB0_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc |
| 9191 | #define PB0_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000 |
| 9192 | #define PB0_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd |
| 9193 | #define PB0_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000 |
| 9194 | #define PB0_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe |
| 9195 | #define PB0_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000 |
| 9196 | #define PB0_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf |
| 9197 | #define PB0_PIF_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000 |
| 9198 | #define PB0_PIF_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10 |
| 9199 | #define PB0_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000 |
| 9200 | #define PB0_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11 |
| 9201 | #define PB0_PIF_LANE3_OVRD2__GANGMODE_3_MASK 0x7 |
| 9202 | #define PB0_PIF_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0 |
| 9203 | #define PB0_PIF_LANE3_OVRD2__FREQDIV_3_MASK 0x18 |
| 9204 | #define PB0_PIF_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3 |
| 9205 | #define PB0_PIF_LANE3_OVRD2__LINKSPEED_3_MASK 0x60 |
| 9206 | #define PB0_PIF_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5 |
| 9207 | #define PB0_PIF_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80 |
| 9208 | #define PB0_PIF_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7 |
| 9209 | #define PB0_PIF_LANE3_OVRD2__TXPWR_3_MASK 0x700 |
| 9210 | #define PB0_PIF_LANE3_OVRD2__TXPWR_3__SHIFT 0x8 |
| 9211 | #define PB0_PIF_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800 |
| 9212 | #define PB0_PIF_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb |
| 9213 | #define PB0_PIF_LANE3_OVRD2__RXPWR_3_MASK 0xe000 |
| 9214 | #define PB0_PIF_LANE3_OVRD2__RXPWR_3__SHIFT 0xd |
| 9215 | #define PB0_PIF_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000 |
| 9216 | #define PB0_PIF_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10 |
| 9217 | #define PB0_PIF_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000 |
| 9218 | #define PB0_PIF_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12 |
| 9219 | #define PB0_PIF_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000 |
| 9220 | #define PB0_PIF_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13 |
| 9221 | #define PB0_PIF_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000 |
| 9222 | #define PB0_PIF_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14 |
| 9223 | #define PB0_PIF_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000 |
| 9224 | #define PB0_PIF_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15 |
| 9225 | #define PB0_PIF_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000 |
| 9226 | #define PB0_PIF_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16 |
| 9227 | #define PB0_PIF_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000 |
| 9228 | #define PB0_PIF_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17 |
| 9229 | #define PB0_PIF_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000 |
| 9230 | #define PB0_PIF_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18 |
| 9231 | #define PB0_PIF_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000 |
| 9232 | #define PB0_PIF_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a |
| 9233 | #define PB0_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1 |
| 9234 | #define PB0_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0 |
| 9235 | #define PB0_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2 |
| 9236 | #define PB0_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1 |
| 9237 | #define PB0_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4 |
| 9238 | #define PB0_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2 |
| 9239 | #define PB0_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8 |
| 9240 | #define PB0_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3 |
| 9241 | #define PB0_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10 |
| 9242 | #define PB0_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4 |
| 9243 | #define PB0_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20 |
| 9244 | #define PB0_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5 |
| 9245 | #define PB0_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40 |
| 9246 | #define PB0_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6 |
| 9247 | #define PB0_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80 |
| 9248 | #define PB0_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7 |
| 9249 | #define PB0_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100 |
| 9250 | #define PB0_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8 |
| 9251 | #define PB0_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200 |
| 9252 | #define PB0_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9 |
| 9253 | #define PB0_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400 |
| 9254 | #define PB0_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa |
| 9255 | #define PB0_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800 |
| 9256 | #define PB0_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb |
| 9257 | #define PB0_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000 |
| 9258 | #define PB0_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc |
| 9259 | #define PB0_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000 |
| 9260 | #define PB0_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd |
| 9261 | #define PB0_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000 |
| 9262 | #define PB0_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe |
| 9263 | #define PB0_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000 |
| 9264 | #define PB0_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf |
| 9265 | #define PB0_PIF_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000 |
| 9266 | #define PB0_PIF_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10 |
| 9267 | #define PB0_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000 |
| 9268 | #define PB0_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11 |
| 9269 | #define PB0_PIF_LANE4_OVRD2__GANGMODE_4_MASK 0x7 |
| 9270 | #define PB0_PIF_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0 |
| 9271 | #define PB0_PIF_LANE4_OVRD2__FREQDIV_4_MASK 0x18 |
| 9272 | #define PB0_PIF_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3 |
| 9273 | #define PB0_PIF_LANE4_OVRD2__LINKSPEED_4_MASK 0x60 |
| 9274 | #define PB0_PIF_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5 |
| 9275 | #define PB0_PIF_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80 |
| 9276 | #define PB0_PIF_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7 |
| 9277 | #define PB0_PIF_LANE4_OVRD2__TXPWR_4_MASK 0x700 |
| 9278 | #define PB0_PIF_LANE4_OVRD2__TXPWR_4__SHIFT 0x8 |
| 9279 | #define PB0_PIF_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800 |
| 9280 | #define PB0_PIF_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb |
| 9281 | #define PB0_PIF_LANE4_OVRD2__RXPWR_4_MASK 0xe000 |
| 9282 | #define PB0_PIF_LANE4_OVRD2__RXPWR_4__SHIFT 0xd |
| 9283 | #define PB0_PIF_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000 |
| 9284 | #define PB0_PIF_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10 |
| 9285 | #define PB0_PIF_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000 |
| 9286 | #define PB0_PIF_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12 |
| 9287 | #define PB0_PIF_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000 |
| 9288 | #define PB0_PIF_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13 |
| 9289 | #define PB0_PIF_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000 |
| 9290 | #define PB0_PIF_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14 |
| 9291 | #define PB0_PIF_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000 |
| 9292 | #define PB0_PIF_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15 |
| 9293 | #define PB0_PIF_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000 |
| 9294 | #define PB0_PIF_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16 |
| 9295 | #define PB0_PIF_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000 |
| 9296 | #define PB0_PIF_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17 |
| 9297 | #define PB0_PIF_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000 |
| 9298 | #define PB0_PIF_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18 |
| 9299 | #define PB0_PIF_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000 |
| 9300 | #define PB0_PIF_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a |
| 9301 | #define PB0_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1 |
| 9302 | #define PB0_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0 |
| 9303 | #define PB0_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2 |
| 9304 | #define PB0_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1 |
| 9305 | #define PB0_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4 |
| 9306 | #define PB0_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2 |
| 9307 | #define PB0_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8 |
| 9308 | #define PB0_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3 |
| 9309 | #define PB0_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10 |
| 9310 | #define PB0_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4 |
| 9311 | #define PB0_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20 |
| 9312 | #define PB0_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5 |
| 9313 | #define PB0_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40 |
| 9314 | #define PB0_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6 |
| 9315 | #define PB0_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80 |
| 9316 | #define PB0_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7 |
| 9317 | #define PB0_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100 |
| 9318 | #define PB0_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8 |
| 9319 | #define PB0_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200 |
| 9320 | #define PB0_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9 |
| 9321 | #define PB0_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400 |
| 9322 | #define PB0_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa |
| 9323 | #define PB0_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800 |
| 9324 | #define PB0_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb |
| 9325 | #define PB0_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000 |
| 9326 | #define PB0_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc |
| 9327 | #define PB0_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000 |
| 9328 | #define PB0_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd |
| 9329 | #define PB0_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000 |
| 9330 | #define PB0_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe |
| 9331 | #define PB0_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000 |
| 9332 | #define PB0_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf |
| 9333 | #define PB0_PIF_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000 |
| 9334 | #define PB0_PIF_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10 |
| 9335 | #define PB0_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000 |
| 9336 | #define PB0_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11 |
| 9337 | #define PB0_PIF_LANE5_OVRD2__GANGMODE_5_MASK 0x7 |
| 9338 | #define PB0_PIF_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0 |
| 9339 | #define PB0_PIF_LANE5_OVRD2__FREQDIV_5_MASK 0x18 |
| 9340 | #define PB0_PIF_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3 |
| 9341 | #define PB0_PIF_LANE5_OVRD2__LINKSPEED_5_MASK 0x60 |
| 9342 | #define PB0_PIF_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5 |
| 9343 | #define PB0_PIF_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80 |
| 9344 | #define PB0_PIF_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7 |
| 9345 | #define PB0_PIF_LANE5_OVRD2__TXPWR_5_MASK 0x700 |
| 9346 | #define PB0_PIF_LANE5_OVRD2__TXPWR_5__SHIFT 0x8 |
| 9347 | #define PB0_PIF_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800 |
| 9348 | #define PB0_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb |
| 9349 | #define PB0_PIF_LANE5_OVRD2__RXPWR_5_MASK 0xe000 |
| 9350 | #define PB0_PIF_LANE5_OVRD2__RXPWR_5__SHIFT 0xd |
| 9351 | #define PB0_PIF_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000 |
| 9352 | #define PB0_PIF_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10 |
| 9353 | #define PB0_PIF_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000 |
| 9354 | #define PB0_PIF_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12 |
| 9355 | #define PB0_PIF_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000 |
| 9356 | #define PB0_PIF_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13 |
| 9357 | #define PB0_PIF_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000 |
| 9358 | #define PB0_PIF_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14 |
| 9359 | #define PB0_PIF_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000 |
| 9360 | #define PB0_PIF_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15 |
| 9361 | #define PB0_PIF_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000 |
| 9362 | #define PB0_PIF_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16 |
| 9363 | #define PB0_PIF_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000 |
| 9364 | #define PB0_PIF_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17 |
| 9365 | #define PB0_PIF_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000 |
| 9366 | #define PB0_PIF_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18 |
| 9367 | #define PB0_PIF_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000 |
| 9368 | #define PB0_PIF_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a |
| 9369 | #define PB0_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1 |
| 9370 | #define PB0_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0 |
| 9371 | #define PB0_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2 |
| 9372 | #define PB0_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1 |
| 9373 | #define PB0_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4 |
| 9374 | #define PB0_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2 |
| 9375 | #define PB0_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8 |
| 9376 | #define PB0_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3 |
| 9377 | #define PB0_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10 |
| 9378 | #define PB0_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4 |
| 9379 | #define PB0_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20 |
| 9380 | #define PB0_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5 |
| 9381 | #define PB0_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40 |
| 9382 | #define PB0_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6 |
| 9383 | #define PB0_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80 |
| 9384 | #define PB0_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7 |
| 9385 | #define PB0_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100 |
| 9386 | #define PB0_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8 |
| 9387 | #define PB0_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200 |
| 9388 | #define PB0_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9 |
| 9389 | #define PB0_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400 |
| 9390 | #define PB0_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa |
| 9391 | #define PB0_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800 |
| 9392 | #define PB0_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb |
| 9393 | #define PB0_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000 |
| 9394 | #define PB0_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc |
| 9395 | #define PB0_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000 |
| 9396 | #define PB0_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd |
| 9397 | #define PB0_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000 |
| 9398 | #define PB0_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe |
| 9399 | #define PB0_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000 |
| 9400 | #define PB0_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf |
| 9401 | #define PB0_PIF_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000 |
| 9402 | #define PB0_PIF_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10 |
| 9403 | #define PB0_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000 |
| 9404 | #define PB0_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11 |
| 9405 | #define PB0_PIF_LANE6_OVRD2__GANGMODE_6_MASK 0x7 |
| 9406 | #define PB0_PIF_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0 |
| 9407 | #define PB0_PIF_LANE6_OVRD2__FREQDIV_6_MASK 0x18 |
| 9408 | #define PB0_PIF_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3 |
| 9409 | #define PB0_PIF_LANE6_OVRD2__LINKSPEED_6_MASK 0x60 |
| 9410 | #define PB0_PIF_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5 |
| 9411 | #define PB0_PIF_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80 |
| 9412 | #define PB0_PIF_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7 |
| 9413 | #define PB0_PIF_LANE6_OVRD2__TXPWR_6_MASK 0x700 |
| 9414 | #define PB0_PIF_LANE6_OVRD2__TXPWR_6__SHIFT 0x8 |
| 9415 | #define PB0_PIF_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800 |
| 9416 | #define PB0_PIF_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb |
| 9417 | #define PB0_PIF_LANE6_OVRD2__RXPWR_6_MASK 0xe000 |
| 9418 | #define PB0_PIF_LANE6_OVRD2__RXPWR_6__SHIFT 0xd |
| 9419 | #define PB0_PIF_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000 |
| 9420 | #define PB0_PIF_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10 |
| 9421 | #define PB0_PIF_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000 |
| 9422 | #define PB0_PIF_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12 |
| 9423 | #define PB0_PIF_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000 |
| 9424 | #define PB0_PIF_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13 |
| 9425 | #define PB0_PIF_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000 |
| 9426 | #define PB0_PIF_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14 |
| 9427 | #define PB0_PIF_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000 |
| 9428 | #define PB0_PIF_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15 |
| 9429 | #define PB0_PIF_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000 |
| 9430 | #define PB0_PIF_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16 |
| 9431 | #define PB0_PIF_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000 |
| 9432 | #define PB0_PIF_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17 |
| 9433 | #define PB0_PIF_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000 |
| 9434 | #define PB0_PIF_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18 |
| 9435 | #define PB0_PIF_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000 |
| 9436 | #define PB0_PIF_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a |
| 9437 | #define PB0_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1 |
| 9438 | #define PB0_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0 |
| 9439 | #define PB0_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2 |
| 9440 | #define PB0_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1 |
| 9441 | #define PB0_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4 |
| 9442 | #define PB0_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2 |
| 9443 | #define PB0_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8 |
| 9444 | #define PB0_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3 |
| 9445 | #define PB0_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10 |
| 9446 | #define PB0_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4 |
| 9447 | #define PB0_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20 |
| 9448 | #define PB0_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5 |
| 9449 | #define PB0_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40 |
| 9450 | #define PB0_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6 |
| 9451 | #define PB0_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80 |
| 9452 | #define PB0_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7 |
| 9453 | #define PB0_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100 |
| 9454 | #define PB0_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8 |
| 9455 | #define PB0_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200 |
| 9456 | #define PB0_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9 |
| 9457 | #define PB0_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400 |
| 9458 | #define PB0_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa |
| 9459 | #define PB0_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800 |
| 9460 | #define PB0_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb |
| 9461 | #define PB0_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000 |
| 9462 | #define PB0_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc |
| 9463 | #define PB0_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000 |
| 9464 | #define PB0_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd |
| 9465 | #define PB0_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000 |
| 9466 | #define PB0_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe |
| 9467 | #define PB0_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000 |
| 9468 | #define PB0_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf |
| 9469 | #define PB0_PIF_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000 |
| 9470 | #define PB0_PIF_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10 |
| 9471 | #define PB0_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000 |
| 9472 | #define PB0_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11 |
| 9473 | #define PB0_PIF_LANE7_OVRD2__GANGMODE_7_MASK 0x7 |
| 9474 | #define PB0_PIF_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0 |
| 9475 | #define PB0_PIF_LANE7_OVRD2__FREQDIV_7_MASK 0x18 |
| 9476 | #define PB0_PIF_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3 |
| 9477 | #define PB0_PIF_LANE7_OVRD2__LINKSPEED_7_MASK 0x60 |
| 9478 | #define PB0_PIF_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5 |
| 9479 | #define PB0_PIF_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80 |
| 9480 | #define PB0_PIF_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7 |
| 9481 | #define PB0_PIF_LANE7_OVRD2__TXPWR_7_MASK 0x700 |
| 9482 | #define PB0_PIF_LANE7_OVRD2__TXPWR_7__SHIFT 0x8 |
| 9483 | #define PB0_PIF_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800 |
| 9484 | #define PB0_PIF_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb |
| 9485 | #define PB0_PIF_LANE7_OVRD2__RXPWR_7_MASK 0xe000 |
| 9486 | #define PB0_PIF_LANE7_OVRD2__RXPWR_7__SHIFT 0xd |
| 9487 | #define PB0_PIF_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000 |
| 9488 | #define PB0_PIF_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10 |
| 9489 | #define PB0_PIF_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000 |
| 9490 | #define PB0_PIF_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12 |
| 9491 | #define PB0_PIF_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000 |
| 9492 | #define PB0_PIF_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13 |
| 9493 | #define PB0_PIF_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000 |
| 9494 | #define PB0_PIF_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14 |
| 9495 | #define PB0_PIF_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000 |
| 9496 | #define PB0_PIF_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15 |
| 9497 | #define PB0_PIF_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000 |
| 9498 | #define PB0_PIF_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16 |
| 9499 | #define PB0_PIF_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000 |
| 9500 | #define PB0_PIF_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17 |
| 9501 | #define PB0_PIF_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000 |
| 9502 | #define PB0_PIF_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18 |
| 9503 | #define PB0_PIF_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000 |
| 9504 | #define PB0_PIF_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a |
| 9505 | #define PB1_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff |
| 9506 | #define PB1_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0 |
| 9507 | #define PB1_PIF_HW_DEBUG__HW_00_DEBUG_MASK 0x1 |
| 9508 | #define PB1_PIF_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 |
| 9509 | #define PB1_PIF_HW_DEBUG__HW_01_DEBUG_MASK 0x2 |
| 9510 | #define PB1_PIF_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 |
| 9511 | #define PB1_PIF_HW_DEBUG__HW_02_DEBUG_MASK 0x4 |
| 9512 | #define PB1_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 |
| 9513 | #define PB1_PIF_HW_DEBUG__HW_03_DEBUG_MASK 0x8 |
| 9514 | #define PB1_PIF_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 |
| 9515 | #define PB1_PIF_HW_DEBUG__HW_04_DEBUG_MASK 0x10 |
| 9516 | #define PB1_PIF_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 |
| 9517 | #define PB1_PIF_HW_DEBUG__HW_05_DEBUG_MASK 0x20 |
| 9518 | #define PB1_PIF_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 |
| 9519 | #define PB1_PIF_HW_DEBUG__HW_06_DEBUG_MASK 0x40 |
| 9520 | #define PB1_PIF_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 |
| 9521 | #define PB1_PIF_HW_DEBUG__HW_07_DEBUG_MASK 0x80 |
| 9522 | #define PB1_PIF_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 |
| 9523 | #define PB1_PIF_HW_DEBUG__HW_08_DEBUG_MASK 0x100 |
| 9524 | #define PB1_PIF_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 |
| 9525 | #define PB1_PIF_HW_DEBUG__HW_09_DEBUG_MASK 0x200 |
| 9526 | #define PB1_PIF_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 |
| 9527 | #define PB1_PIF_HW_DEBUG__HW_10_DEBUG_MASK 0x400 |
| 9528 | #define PB1_PIF_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa |
| 9529 | #define PB1_PIF_HW_DEBUG__HW_11_DEBUG_MASK 0x800 |
| 9530 | #define PB1_PIF_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb |
| 9531 | #define PB1_PIF_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 |
| 9532 | #define PB1_PIF_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc |
| 9533 | #define PB1_PIF_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 |
| 9534 | #define PB1_PIF_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd |
| 9535 | #define PB1_PIF_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 |
| 9536 | #define PB1_PIF_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe |
| 9537 | #define PB1_PIF_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 |
| 9538 | #define PB1_PIF_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf |
| 9539 | #define PB1_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2 |
| 9540 | #define PB1_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1 |
| 9541 | #define PB1_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4 |
| 9542 | #define PB1_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2 |
| 9543 | #define PB1_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8 |
| 9544 | #define PB1_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3 |
| 9545 | #define PB1_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10 |
| 9546 | #define PB1_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4 |
| 9547 | #define PB1_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20 |
| 9548 | #define PB1_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5 |
| 9549 | #define PB1_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0 |
| 9550 | #define PB1_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6 |
| 9551 | #define PB1_PIF_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300 |
| 9552 | #define PB1_PIF_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8 |
| 9553 | #define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400 |
| 9554 | #define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa |
| 9555 | #define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800 |
| 9556 | #define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb |
| 9557 | #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000 |
| 9558 | #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc |
| 9559 | #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000 |
| 9560 | #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd |
| 9561 | #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000 |
| 9562 | #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe |
| 9563 | #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000 |
| 9564 | #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf |
| 9565 | #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000 |
| 9566 | #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10 |
| 9567 | #define PB1_PIF_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1 |
| 9568 | #define PB1_PIF_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0 |
| 9569 | #define PB1_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2 |
| 9570 | #define PB1_PIF_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1 |
| 9571 | #define PB1_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4 |
| 9572 | #define PB1_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2 |
| 9573 | #define PB1_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8 |
| 9574 | #define PB1_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3 |
| 9575 | #define PB1_PIF_CTRL__PHY_RST_PWROK_VDD_MASK 0x10 |
| 9576 | #define PB1_PIF_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4 |
| 9577 | #define PB1_PIF_CTRL__PIF_PLL_STATUS_MASK 0xc0 |
| 9578 | #define PB1_PIF_CTRL__PIF_PLL_STATUS__SHIFT 0x6 |
| 9579 | #define PB1_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100 |
| 9580 | #define PB1_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8 |
| 9581 | #define PB1_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200 |
| 9582 | #define PB1_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9 |
| 9583 | #define PB1_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400 |
| 9584 | #define PB1_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa |
| 9585 | #define PB1_PIF_CTRL__PIF_PG_EXIT_MODE_MASK 0x800 |
| 9586 | #define PB1_PIF_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb |
| 9587 | #define PB1_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000 |
| 9588 | #define PB1_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc |
| 9589 | #define PB1_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000 |
| 9590 | #define PB1_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd |
| 9591 | #define PB1_PIF_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000 |
| 9592 | #define PB1_PIF_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe |
| 9593 | #define PB1_PIF_TX_CTRL__TXPWR_IN_S2_MASK 0x7 |
| 9594 | #define PB1_PIF_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0 |
| 9595 | #define PB1_PIF_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38 |
| 9596 | #define PB1_PIF_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3 |
| 9597 | #define PB1_PIF_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0 |
| 9598 | #define PB1_PIF_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6 |
| 9599 | #define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00 |
| 9600 | #define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9 |
| 9601 | #define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000 |
| 9602 | #define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc |
| 9603 | #define PB1_PIF_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000 |
| 9604 | #define PB1_PIF_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf |
| 9605 | #define PB1_PIF_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000 |
| 9606 | #define PB1_PIF_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12 |
| 9607 | #define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000 |
| 9608 | #define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15 |
| 9609 | #define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000 |
| 9610 | #define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16 |
| 9611 | #define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000 |
| 9612 | #define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17 |
| 9613 | #define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000 |
| 9614 | #define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18 |
| 9615 | #define PB1_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7 |
| 9616 | #define PB1_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0 |
| 9617 | #define PB1_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38 |
| 9618 | #define PB1_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3 |
| 9619 | #define PB1_PIF_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0 |
| 9620 | #define PB1_PIF_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6 |
| 9621 | #define PB1_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200 |
| 9622 | #define PB1_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 |
| 9623 | #define PB1_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 |
| 9624 | #define PB1_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa |
| 9625 | #define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000 |
| 9626 | #define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10 |
| 9627 | #define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000 |
| 9628 | #define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11 |
| 9629 | #define PB1_PIF_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000 |
| 9630 | #define PB1_PIF_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15 |
| 9631 | #define PB1_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000 |
| 9632 | #define PB1_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16 |
| 9633 | #define PB1_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000 |
| 9634 | #define PB1_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19 |
| 9635 | #define PB1_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000 |
| 9636 | #define PB1_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a |
| 9637 | #define PB1_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000 |
| 9638 | #define PB1_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d |
| 9639 | #define PB1_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000 |
| 9640 | #define PB1_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e |
| 9641 | #define PB1_PIF_RX_CTRL__RXPWR_IN_S2_MASK 0x7 |
| 9642 | #define PB1_PIF_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0 |
| 9643 | #define PB1_PIF_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38 |
| 9644 | #define PB1_PIF_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3 |
| 9645 | #define PB1_PIF_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0 |
| 9646 | #define PB1_PIF_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6 |
| 9647 | #define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00 |
| 9648 | #define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9 |
| 9649 | #define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000 |
| 9650 | #define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc |
| 9651 | #define PB1_PIF_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000 |
| 9652 | #define PB1_PIF_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf |
| 9653 | #define PB1_PIF_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000 |
| 9654 | #define PB1_PIF_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12 |
| 9655 | #define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000 |
| 9656 | #define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15 |
| 9657 | #define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000 |
| 9658 | #define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16 |
| 9659 | #define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000 |
| 9660 | #define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17 |
| 9661 | #define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000 |
| 9662 | #define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18 |
| 9663 | #define PB1_PIF_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000 |
| 9664 | #define PB1_PIF_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19 |
| 9665 | #define PB1_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000 |
| 9666 | #define PB1_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a |
| 9667 | #define PB1_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7 |
| 9668 | #define PB1_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0 |
| 9669 | #define PB1_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38 |
| 9670 | #define PB1_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3 |
| 9671 | #define PB1_PIF_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0 |
| 9672 | #define PB1_PIF_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6 |
| 9673 | #define PB1_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200 |
| 9674 | #define PB1_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 |
| 9675 | #define PB1_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 |
| 9676 | #define PB1_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa |
| 9677 | #define PB1_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000 |
| 9678 | #define PB1_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10 |
| 9679 | #define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000 |
| 9680 | #define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11 |
| 9681 | #define PB1_PIF_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000 |
| 9682 | #define PB1_PIF_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13 |
| 9683 | #define PB1_PIF_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000 |
| 9684 | #define PB1_PIF_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15 |
| 9685 | #define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000 |
| 9686 | #define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18 |
| 9687 | #define PB1_PIF_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000 |
| 9688 | #define PB1_PIF_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19 |
| 9689 | #define PB1_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000 |
| 9690 | #define PB1_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b |
| 9691 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1 |
| 9692 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0 |
| 9693 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2 |
| 9694 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1 |
| 9695 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4 |
| 9696 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2 |
| 9697 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8 |
| 9698 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3 |
| 9699 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10 |
| 9700 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4 |
| 9701 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20 |
| 9702 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5 |
| 9703 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40 |
| 9704 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6 |
| 9705 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80 |
| 9706 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7 |
| 9707 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000 |
| 9708 | #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10 |
| 9709 | #define PB1_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1 |
| 9710 | #define PB1_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0 |
| 9711 | #define PB1_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2 |
| 9712 | #define PB1_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1 |
| 9713 | #define PB1_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4 |
| 9714 | #define PB1_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2 |
| 9715 | #define PB1_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8 |
| 9716 | #define PB1_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3 |
| 9717 | #define PB1_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10 |
| 9718 | #define PB1_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4 |
| 9719 | #define PB1_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20 |
| 9720 | #define PB1_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5 |
| 9721 | #define PB1_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40 |
| 9722 | #define PB1_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6 |
| 9723 | #define PB1_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80 |
| 9724 | #define PB1_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7 |
| 9725 | #define PB1_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100 |
| 9726 | #define PB1_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8 |
| 9727 | #define PB1_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200 |
| 9728 | #define PB1_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9 |
| 9729 | #define PB1_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400 |
| 9730 | #define PB1_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa |
| 9731 | #define PB1_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800 |
| 9732 | #define PB1_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb |
| 9733 | #define PB1_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000 |
| 9734 | #define PB1_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10 |
| 9735 | #define PB1_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000 |
| 9736 | #define PB1_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11 |
| 9737 | #define PB1_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000 |
| 9738 | #define PB1_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14 |
| 9739 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1 |
| 9740 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0 |
| 9741 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2 |
| 9742 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1 |
| 9743 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4 |
| 9744 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2 |
| 9745 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8 |
| 9746 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3 |
| 9747 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10 |
| 9748 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4 |
| 9749 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20 |
| 9750 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5 |
| 9751 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40 |
| 9752 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6 |
| 9753 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80 |
| 9754 | #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7 |
| 9755 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100 |
| 9756 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8 |
| 9757 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200 |
| 9758 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9 |
| 9759 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400 |
| 9760 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa |
| 9761 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800 |
| 9762 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb |
| 9763 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000 |
| 9764 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc |
| 9765 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000 |
| 9766 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd |
| 9767 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000 |
| 9768 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe |
| 9769 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000 |
| 9770 | #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf |
| 9771 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000 |
| 9772 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10 |
| 9773 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000 |
| 9774 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11 |
| 9775 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000 |
| 9776 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12 |
| 9777 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000 |
| 9778 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13 |
| 9779 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000 |
| 9780 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14 |
| 9781 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000 |
| 9782 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15 |
| 9783 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000 |
| 9784 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16 |
| 9785 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000 |
| 9786 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17 |
| 9787 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000 |
| 9788 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18 |
| 9789 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000 |
| 9790 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19 |
| 9791 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000 |
| 9792 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a |
| 9793 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000 |
| 9794 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b |
| 9795 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000 |
| 9796 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c |
| 9797 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000 |
| 9798 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d |
| 9799 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000 |
| 9800 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e |
| 9801 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000 |
| 9802 | #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f |
| 9803 | #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3 |
| 9804 | #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0 |
| 9805 | #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc |
| 9806 | #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2 |
| 9807 | #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10 |
| 9808 | #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4 |
| 9809 | #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60 |
| 9810 | #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5 |
| 9811 | #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80 |
| 9812 | #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7 |
| 9813 | #define PB1_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100 |
| 9814 | #define PB1_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8 |
| 9815 | #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200 |
| 9816 | #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9 |
| 9817 | #define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1 |
| 9818 | #define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0 |
| 9819 | #define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2 |
| 9820 | #define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1 |
| 9821 | #define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4 |
| 9822 | #define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2 |
| 9823 | #define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38 |
| 9824 | #define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3 |
| 9825 | #define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40 |
| 9826 | #define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6 |
| 9827 | #define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180 |
| 9828 | #define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7 |
| 9829 | #define PB1_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200 |
| 9830 | #define PB1_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9 |
| 9831 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000 |
| 9832 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10 |
| 9833 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000 |
| 9834 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11 |
| 9835 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000 |
| 9836 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12 |
| 9837 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000 |
| 9838 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13 |
| 9839 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000 |
| 9840 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14 |
| 9841 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000 |
| 9842 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15 |
| 9843 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000 |
| 9844 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16 |
| 9845 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000 |
| 9846 | #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17 |
| 9847 | #define PB1_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1 |
| 9848 | #define PB1_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0 |
| 9849 | #define PB1_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2 |
| 9850 | #define PB1_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1 |
| 9851 | #define PB1_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4 |
| 9852 | #define PB1_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2 |
| 9853 | #define PB1_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8 |
| 9854 | #define PB1_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3 |
| 9855 | #define PB1_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10 |
| 9856 | #define PB1_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4 |
| 9857 | #define PB1_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20 |
| 9858 | #define PB1_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5 |
| 9859 | #define PB1_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40 |
| 9860 | #define PB1_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6 |
| 9861 | #define PB1_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80 |
| 9862 | #define PB1_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7 |
| 9863 | #define PB1_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100 |
| 9864 | #define PB1_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8 |
| 9865 | #define PB1_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200 |
| 9866 | #define PB1_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9 |
| 9867 | #define PB1_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400 |
| 9868 | #define PB1_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa |
| 9869 | #define PB1_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800 |
| 9870 | #define PB1_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb |
| 9871 | #define PB1_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000 |
| 9872 | #define PB1_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc |
| 9873 | #define PB1_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000 |
| 9874 | #define PB1_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd |
| 9875 | #define PB1_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000 |
| 9876 | #define PB1_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe |
| 9877 | #define PB1_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000 |
| 9878 | #define PB1_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf |
| 9879 | #define PB1_PIF_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000 |
| 9880 | #define PB1_PIF_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10 |
| 9881 | #define PB1_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000 |
| 9882 | #define PB1_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11 |
| 9883 | #define PB1_PIF_LANE0_OVRD2__GANGMODE_0_MASK 0x7 |
| 9884 | #define PB1_PIF_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0 |
| 9885 | #define PB1_PIF_LANE0_OVRD2__FREQDIV_0_MASK 0x18 |
| 9886 | #define PB1_PIF_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3 |
| 9887 | #define PB1_PIF_LANE0_OVRD2__LINKSPEED_0_MASK 0x60 |
| 9888 | #define PB1_PIF_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5 |
| 9889 | #define PB1_PIF_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80 |
| 9890 | #define PB1_PIF_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7 |
| 9891 | #define PB1_PIF_LANE0_OVRD2__TXPWR_0_MASK 0x700 |
| 9892 | #define PB1_PIF_LANE0_OVRD2__TXPWR_0__SHIFT 0x8 |
| 9893 | #define PB1_PIF_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800 |
| 9894 | #define PB1_PIF_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb |
| 9895 | #define PB1_PIF_LANE0_OVRD2__RXPWR_0_MASK 0xe000 |
| 9896 | #define PB1_PIF_LANE0_OVRD2__RXPWR_0__SHIFT 0xd |
| 9897 | #define PB1_PIF_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000 |
| 9898 | #define PB1_PIF_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10 |
| 9899 | #define PB1_PIF_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000 |
| 9900 | #define PB1_PIF_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12 |
| 9901 | #define PB1_PIF_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000 |
| 9902 | #define PB1_PIF_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13 |
| 9903 | #define PB1_PIF_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000 |
| 9904 | #define PB1_PIF_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14 |
| 9905 | #define PB1_PIF_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000 |
| 9906 | #define PB1_PIF_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15 |
| 9907 | #define PB1_PIF_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000 |
| 9908 | #define PB1_PIF_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16 |
| 9909 | #define PB1_PIF_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000 |
| 9910 | #define PB1_PIF_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17 |
| 9911 | #define PB1_PIF_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000 |
| 9912 | #define PB1_PIF_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18 |
| 9913 | #define PB1_PIF_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000 |
| 9914 | #define PB1_PIF_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a |
| 9915 | #define PB1_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1 |
| 9916 | #define PB1_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0 |
| 9917 | #define PB1_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2 |
| 9918 | #define PB1_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1 |
| 9919 | #define PB1_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4 |
| 9920 | #define PB1_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2 |
| 9921 | #define PB1_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8 |
| 9922 | #define PB1_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3 |
| 9923 | #define PB1_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10 |
| 9924 | #define PB1_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4 |
| 9925 | #define PB1_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20 |
| 9926 | #define PB1_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5 |
| 9927 | #define PB1_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40 |
| 9928 | #define PB1_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6 |
| 9929 | #define PB1_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80 |
| 9930 | #define PB1_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7 |
| 9931 | #define PB1_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100 |
| 9932 | #define PB1_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8 |
| 9933 | #define PB1_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200 |
| 9934 | #define PB1_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9 |
| 9935 | #define PB1_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400 |
| 9936 | #define PB1_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa |
| 9937 | #define PB1_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800 |
| 9938 | #define PB1_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb |
| 9939 | #define PB1_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000 |
| 9940 | #define PB1_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc |
| 9941 | #define PB1_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000 |
| 9942 | #define PB1_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd |
| 9943 | #define PB1_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000 |
| 9944 | #define PB1_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe |
| 9945 | #define PB1_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000 |
| 9946 | #define PB1_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf |
| 9947 | #define PB1_PIF_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000 |
| 9948 | #define PB1_PIF_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10 |
| 9949 | #define PB1_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000 |
| 9950 | #define PB1_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11 |
| 9951 | #define PB1_PIF_LANE1_OVRD2__GANGMODE_1_MASK 0x7 |
| 9952 | #define PB1_PIF_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0 |
| 9953 | #define PB1_PIF_LANE1_OVRD2__FREQDIV_1_MASK 0x18 |
| 9954 | #define PB1_PIF_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3 |
| 9955 | #define PB1_PIF_LANE1_OVRD2__LINKSPEED_1_MASK 0x60 |
| 9956 | #define PB1_PIF_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5 |
| 9957 | #define PB1_PIF_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80 |
| 9958 | #define PB1_PIF_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7 |
| 9959 | #define PB1_PIF_LANE1_OVRD2__TXPWR_1_MASK 0x700 |
| 9960 | #define PB1_PIF_LANE1_OVRD2__TXPWR_1__SHIFT 0x8 |
| 9961 | #define PB1_PIF_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800 |
| 9962 | #define PB1_PIF_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb |
| 9963 | #define PB1_PIF_LANE1_OVRD2__RXPWR_1_MASK 0xe000 |
| 9964 | #define PB1_PIF_LANE1_OVRD2__RXPWR_1__SHIFT 0xd |
| 9965 | #define PB1_PIF_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000 |
| 9966 | #define PB1_PIF_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10 |
| 9967 | #define PB1_PIF_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000 |
| 9968 | #define PB1_PIF_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12 |
| 9969 | #define PB1_PIF_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000 |
| 9970 | #define PB1_PIF_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13 |
| 9971 | #define PB1_PIF_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000 |
| 9972 | #define PB1_PIF_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14 |
| 9973 | #define PB1_PIF_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000 |
| 9974 | #define PB1_PIF_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15 |
| 9975 | #define PB1_PIF_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000 |
| 9976 | #define PB1_PIF_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16 |
| 9977 | #define PB1_PIF_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000 |
| 9978 | #define PB1_PIF_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17 |
| 9979 | #define PB1_PIF_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000 |
| 9980 | #define PB1_PIF_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18 |
| 9981 | #define PB1_PIF_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000 |
| 9982 | #define PB1_PIF_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a |
| 9983 | #define PB1_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1 |
| 9984 | #define PB1_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0 |
| 9985 | #define PB1_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2 |
| 9986 | #define PB1_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1 |
| 9987 | #define PB1_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4 |
| 9988 | #define PB1_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2 |
| 9989 | #define PB1_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8 |
| 9990 | #define PB1_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3 |
| 9991 | #define PB1_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10 |
| 9992 | #define PB1_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4 |
| 9993 | #define PB1_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20 |
| 9994 | #define PB1_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5 |
| 9995 | #define PB1_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40 |
| 9996 | #define PB1_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6 |
| 9997 | #define PB1_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80 |
| 9998 | #define PB1_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7 |
| 9999 | #define PB1_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100 |
| 10000 | #define PB1_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8 |
| 10001 | #define PB1_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200 |
| 10002 | #define PB1_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9 |
| 10003 | #define PB1_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400 |
| 10004 | #define PB1_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa |
| 10005 | #define PB1_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800 |
| 10006 | #define PB1_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb |
| 10007 | #define PB1_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000 |
| 10008 | #define PB1_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc |
| 10009 | #define PB1_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000 |
| 10010 | #define PB1_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd |
| 10011 | #define PB1_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000 |
| 10012 | #define PB1_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe |
| 10013 | #define PB1_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000 |
| 10014 | #define PB1_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf |
| 10015 | #define PB1_PIF_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000 |
| 10016 | #define PB1_PIF_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10 |
| 10017 | #define PB1_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000 |
| 10018 | #define PB1_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11 |
| 10019 | #define PB1_PIF_LANE2_OVRD2__GANGMODE_2_MASK 0x7 |
| 10020 | #define PB1_PIF_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0 |
| 10021 | #define PB1_PIF_LANE2_OVRD2__FREQDIV_2_MASK 0x18 |
| 10022 | #define PB1_PIF_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3 |
| 10023 | #define PB1_PIF_LANE2_OVRD2__LINKSPEED_2_MASK 0x60 |
| 10024 | #define PB1_PIF_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5 |
| 10025 | #define PB1_PIF_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80 |
| 10026 | #define PB1_PIF_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7 |
| 10027 | #define PB1_PIF_LANE2_OVRD2__TXPWR_2_MASK 0x700 |
| 10028 | #define PB1_PIF_LANE2_OVRD2__TXPWR_2__SHIFT 0x8 |
| 10029 | #define PB1_PIF_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800 |
| 10030 | #define PB1_PIF_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb |
| 10031 | #define PB1_PIF_LANE2_OVRD2__RXPWR_2_MASK 0xe000 |
| 10032 | #define PB1_PIF_LANE2_OVRD2__RXPWR_2__SHIFT 0xd |
| 10033 | #define PB1_PIF_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000 |
| 10034 | #define PB1_PIF_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10 |
| 10035 | #define PB1_PIF_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000 |
| 10036 | #define PB1_PIF_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12 |
| 10037 | #define PB1_PIF_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000 |
| 10038 | #define PB1_PIF_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13 |
| 10039 | #define PB1_PIF_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000 |
| 10040 | #define PB1_PIF_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14 |
| 10041 | #define PB1_PIF_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000 |
| 10042 | #define PB1_PIF_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15 |
| 10043 | #define PB1_PIF_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000 |
| 10044 | #define PB1_PIF_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16 |
| 10045 | #define PB1_PIF_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000 |
| 10046 | #define PB1_PIF_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17 |
| 10047 | #define PB1_PIF_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000 |
| 10048 | #define PB1_PIF_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18 |
| 10049 | #define PB1_PIF_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000 |
| 10050 | #define PB1_PIF_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a |
| 10051 | #define PB1_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1 |
| 10052 | #define PB1_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0 |
| 10053 | #define PB1_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2 |
| 10054 | #define PB1_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1 |
| 10055 | #define PB1_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4 |
| 10056 | #define PB1_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2 |
| 10057 | #define PB1_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8 |
| 10058 | #define PB1_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3 |
| 10059 | #define PB1_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10 |
| 10060 | #define PB1_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4 |
| 10061 | #define PB1_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20 |
| 10062 | #define PB1_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5 |
| 10063 | #define PB1_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40 |
| 10064 | #define PB1_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6 |
| 10065 | #define PB1_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80 |
| 10066 | #define PB1_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7 |
| 10067 | #define PB1_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100 |
| 10068 | #define PB1_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8 |
| 10069 | #define PB1_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200 |
| 10070 | #define PB1_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9 |
| 10071 | #define PB1_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400 |
| 10072 | #define PB1_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa |
| 10073 | #define PB1_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800 |
| 10074 | #define PB1_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb |
| 10075 | #define PB1_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000 |
| 10076 | #define PB1_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc |
| 10077 | #define PB1_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000 |
| 10078 | #define PB1_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd |
| 10079 | #define PB1_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000 |
| 10080 | #define PB1_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe |
| 10081 | #define PB1_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000 |
| 10082 | #define PB1_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf |
| 10083 | #define PB1_PIF_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000 |
| 10084 | #define PB1_PIF_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10 |
| 10085 | #define PB1_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000 |
| 10086 | #define PB1_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11 |
| 10087 | #define PB1_PIF_LANE3_OVRD2__GANGMODE_3_MASK 0x7 |
| 10088 | #define PB1_PIF_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0 |
| 10089 | #define PB1_PIF_LANE3_OVRD2__FREQDIV_3_MASK 0x18 |
| 10090 | #define PB1_PIF_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3 |
| 10091 | #define PB1_PIF_LANE3_OVRD2__LINKSPEED_3_MASK 0x60 |
| 10092 | #define PB1_PIF_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5 |
| 10093 | #define PB1_PIF_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80 |
| 10094 | #define PB1_PIF_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7 |
| 10095 | #define PB1_PIF_LANE3_OVRD2__TXPWR_3_MASK 0x700 |
| 10096 | #define PB1_PIF_LANE3_OVRD2__TXPWR_3__SHIFT 0x8 |
| 10097 | #define PB1_PIF_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800 |
| 10098 | #define PB1_PIF_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb |
| 10099 | #define PB1_PIF_LANE3_OVRD2__RXPWR_3_MASK 0xe000 |
| 10100 | #define PB1_PIF_LANE3_OVRD2__RXPWR_3__SHIFT 0xd |
| 10101 | #define PB1_PIF_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000 |
| 10102 | #define PB1_PIF_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10 |
| 10103 | #define PB1_PIF_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000 |
| 10104 | #define PB1_PIF_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12 |
| 10105 | #define PB1_PIF_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000 |
| 10106 | #define PB1_PIF_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13 |
| 10107 | #define PB1_PIF_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000 |
| 10108 | #define PB1_PIF_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14 |
| 10109 | #define PB1_PIF_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000 |
| 10110 | #define PB1_PIF_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15 |
| 10111 | #define PB1_PIF_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000 |
| 10112 | #define PB1_PIF_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16 |
| 10113 | #define PB1_PIF_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000 |
| 10114 | #define PB1_PIF_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17 |
| 10115 | #define PB1_PIF_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000 |
| 10116 | #define PB1_PIF_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18 |
| 10117 | #define PB1_PIF_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000 |
| 10118 | #define PB1_PIF_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a |
| 10119 | #define PB1_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1 |
| 10120 | #define PB1_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0 |
| 10121 | #define PB1_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2 |
| 10122 | #define PB1_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1 |
| 10123 | #define PB1_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4 |
| 10124 | #define PB1_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2 |
| 10125 | #define PB1_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8 |
| 10126 | #define PB1_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3 |
| 10127 | #define PB1_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10 |
| 10128 | #define PB1_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4 |
| 10129 | #define PB1_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20 |
| 10130 | #define PB1_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5 |
| 10131 | #define PB1_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40 |
| 10132 | #define PB1_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6 |
| 10133 | #define PB1_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80 |
| 10134 | #define PB1_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7 |
| 10135 | #define PB1_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100 |
| 10136 | #define PB1_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8 |
| 10137 | #define PB1_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200 |
| 10138 | #define PB1_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9 |
| 10139 | #define PB1_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400 |
| 10140 | #define PB1_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa |
| 10141 | #define PB1_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800 |
| 10142 | #define PB1_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb |
| 10143 | #define PB1_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000 |
| 10144 | #define PB1_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc |
| 10145 | #define PB1_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000 |
| 10146 | #define PB1_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd |
| 10147 | #define PB1_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000 |
| 10148 | #define PB1_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe |
| 10149 | #define PB1_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000 |
| 10150 | #define PB1_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf |
| 10151 | #define PB1_PIF_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000 |
| 10152 | #define PB1_PIF_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10 |
| 10153 | #define PB1_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000 |
| 10154 | #define PB1_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11 |
| 10155 | #define PB1_PIF_LANE4_OVRD2__GANGMODE_4_MASK 0x7 |
| 10156 | #define PB1_PIF_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0 |
| 10157 | #define PB1_PIF_LANE4_OVRD2__FREQDIV_4_MASK 0x18 |
| 10158 | #define PB1_PIF_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3 |
| 10159 | #define PB1_PIF_LANE4_OVRD2__LINKSPEED_4_MASK 0x60 |
| 10160 | #define PB1_PIF_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5 |
| 10161 | #define PB1_PIF_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80 |
| 10162 | #define PB1_PIF_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7 |
| 10163 | #define PB1_PIF_LANE4_OVRD2__TXPWR_4_MASK 0x700 |
| 10164 | #define PB1_PIF_LANE4_OVRD2__TXPWR_4__SHIFT 0x8 |
| 10165 | #define PB1_PIF_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800 |
| 10166 | #define PB1_PIF_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb |
| 10167 | #define PB1_PIF_LANE4_OVRD2__RXPWR_4_MASK 0xe000 |
| 10168 | #define PB1_PIF_LANE4_OVRD2__RXPWR_4__SHIFT 0xd |
| 10169 | #define PB1_PIF_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000 |
| 10170 | #define PB1_PIF_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10 |
| 10171 | #define PB1_PIF_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000 |
| 10172 | #define PB1_PIF_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12 |
| 10173 | #define PB1_PIF_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000 |
| 10174 | #define PB1_PIF_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13 |
| 10175 | #define PB1_PIF_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000 |
| 10176 | #define PB1_PIF_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14 |
| 10177 | #define PB1_PIF_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000 |
| 10178 | #define PB1_PIF_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15 |
| 10179 | #define PB1_PIF_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000 |
| 10180 | #define PB1_PIF_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16 |
| 10181 | #define PB1_PIF_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000 |
| 10182 | #define PB1_PIF_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17 |
| 10183 | #define PB1_PIF_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000 |
| 10184 | #define PB1_PIF_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18 |
| 10185 | #define PB1_PIF_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000 |
| 10186 | #define PB1_PIF_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a |
| 10187 | #define PB1_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1 |
| 10188 | #define PB1_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0 |
| 10189 | #define PB1_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2 |
| 10190 | #define PB1_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1 |
| 10191 | #define PB1_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4 |
| 10192 | #define PB1_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2 |
| 10193 | #define PB1_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8 |
| 10194 | #define PB1_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3 |
| 10195 | #define PB1_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10 |
| 10196 | #define PB1_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4 |
| 10197 | #define PB1_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20 |
| 10198 | #define PB1_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5 |
| 10199 | #define PB1_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40 |
| 10200 | #define PB1_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6 |
| 10201 | #define PB1_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80 |
| 10202 | #define PB1_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7 |
| 10203 | #define PB1_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100 |
| 10204 | #define PB1_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8 |
| 10205 | #define PB1_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200 |
| 10206 | #define PB1_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9 |
| 10207 | #define PB1_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400 |
| 10208 | #define PB1_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa |
| 10209 | #define PB1_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800 |
| 10210 | #define PB1_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb |
| 10211 | #define PB1_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000 |
| 10212 | #define PB1_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc |
| 10213 | #define PB1_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000 |
| 10214 | #define PB1_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd |
| 10215 | #define PB1_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000 |
| 10216 | #define PB1_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe |
| 10217 | #define PB1_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000 |
| 10218 | #define PB1_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf |
| 10219 | #define PB1_PIF_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000 |
| 10220 | #define PB1_PIF_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10 |
| 10221 | #define PB1_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000 |
| 10222 | #define PB1_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11 |
| 10223 | #define PB1_PIF_LANE5_OVRD2__GANGMODE_5_MASK 0x7 |
| 10224 | #define PB1_PIF_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0 |
| 10225 | #define PB1_PIF_LANE5_OVRD2__FREQDIV_5_MASK 0x18 |
| 10226 | #define PB1_PIF_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3 |
| 10227 | #define PB1_PIF_LANE5_OVRD2__LINKSPEED_5_MASK 0x60 |
| 10228 | #define PB1_PIF_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5 |
| 10229 | #define PB1_PIF_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80 |
| 10230 | #define PB1_PIF_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7 |
| 10231 | #define PB1_PIF_LANE5_OVRD2__TXPWR_5_MASK 0x700 |
| 10232 | #define PB1_PIF_LANE5_OVRD2__TXPWR_5__SHIFT 0x8 |
| 10233 | #define PB1_PIF_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800 |
| 10234 | #define PB1_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb |
| 10235 | #define PB1_PIF_LANE5_OVRD2__RXPWR_5_MASK 0xe000 |
| 10236 | #define PB1_PIF_LANE5_OVRD2__RXPWR_5__SHIFT 0xd |
| 10237 | #define PB1_PIF_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000 |
| 10238 | #define PB1_PIF_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10 |
| 10239 | #define PB1_PIF_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000 |
| 10240 | #define PB1_PIF_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12 |
| 10241 | #define PB1_PIF_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000 |
| 10242 | #define PB1_PIF_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13 |
| 10243 | #define PB1_PIF_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000 |
| 10244 | #define PB1_PIF_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14 |
| 10245 | #define PB1_PIF_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000 |
| 10246 | #define PB1_PIF_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15 |
| 10247 | #define PB1_PIF_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000 |
| 10248 | #define PB1_PIF_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16 |
| 10249 | #define PB1_PIF_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000 |
| 10250 | #define PB1_PIF_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17 |
| 10251 | #define PB1_PIF_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000 |
| 10252 | #define PB1_PIF_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18 |
| 10253 | #define PB1_PIF_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000 |
| 10254 | #define PB1_PIF_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a |
| 10255 | #define PB1_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1 |
| 10256 | #define PB1_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0 |
| 10257 | #define PB1_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2 |
| 10258 | #define PB1_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1 |
| 10259 | #define PB1_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4 |
| 10260 | #define PB1_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2 |
| 10261 | #define PB1_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8 |
| 10262 | #define PB1_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3 |
| 10263 | #define PB1_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10 |
| 10264 | #define PB1_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4 |
| 10265 | #define PB1_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20 |
| 10266 | #define PB1_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5 |
| 10267 | #define PB1_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40 |
| 10268 | #define PB1_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6 |
| 10269 | #define PB1_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80 |
| 10270 | #define PB1_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7 |
| 10271 | #define PB1_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100 |
| 10272 | #define PB1_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8 |
| 10273 | #define PB1_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200 |
| 10274 | #define PB1_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9 |
| 10275 | #define PB1_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400 |
| 10276 | #define PB1_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa |
| 10277 | #define PB1_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800 |
| 10278 | #define PB1_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb |
| 10279 | #define PB1_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000 |
| 10280 | #define PB1_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc |
| 10281 | #define PB1_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000 |
| 10282 | #define PB1_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd |
| 10283 | #define PB1_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000 |
| 10284 | #define PB1_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe |
| 10285 | #define PB1_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000 |
| 10286 | #define PB1_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf |
| 10287 | #define PB1_PIF_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000 |
| 10288 | #define PB1_PIF_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10 |
| 10289 | #define PB1_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000 |
| 10290 | #define PB1_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11 |
| 10291 | #define PB1_PIF_LANE6_OVRD2__GANGMODE_6_MASK 0x7 |
| 10292 | #define PB1_PIF_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0 |
| 10293 | #define PB1_PIF_LANE6_OVRD2__FREQDIV_6_MASK 0x18 |
| 10294 | #define PB1_PIF_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3 |
| 10295 | #define PB1_PIF_LANE6_OVRD2__LINKSPEED_6_MASK 0x60 |
| 10296 | #define PB1_PIF_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5 |
| 10297 | #define PB1_PIF_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80 |
| 10298 | #define PB1_PIF_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7 |
| 10299 | #define PB1_PIF_LANE6_OVRD2__TXPWR_6_MASK 0x700 |
| 10300 | #define PB1_PIF_LANE6_OVRD2__TXPWR_6__SHIFT 0x8 |
| 10301 | #define PB1_PIF_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800 |
| 10302 | #define PB1_PIF_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb |
| 10303 | #define PB1_PIF_LANE6_OVRD2__RXPWR_6_MASK 0xe000 |
| 10304 | #define PB1_PIF_LANE6_OVRD2__RXPWR_6__SHIFT 0xd |
| 10305 | #define PB1_PIF_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000 |
| 10306 | #define PB1_PIF_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10 |
| 10307 | #define PB1_PIF_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000 |
| 10308 | #define PB1_PIF_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12 |
| 10309 | #define PB1_PIF_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000 |
| 10310 | #define PB1_PIF_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13 |
| 10311 | #define PB1_PIF_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000 |
| 10312 | #define PB1_PIF_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14 |
| 10313 | #define PB1_PIF_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000 |
| 10314 | #define PB1_PIF_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15 |
| 10315 | #define PB1_PIF_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000 |
| 10316 | #define PB1_PIF_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16 |
| 10317 | #define PB1_PIF_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000 |
| 10318 | #define PB1_PIF_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17 |
| 10319 | #define PB1_PIF_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x300 |