1 | /* |
2 | * Copyright 2023 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #ifndef _nbio_7_11_0_SH_MASK_HEADER |
24 | #define |
25 | |
26 | |
27 | // addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec |
28 | //NB_VENDOR_ID |
29 | #define NB_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
30 | #define NB_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
31 | //NB_DEVICE_ID |
32 | #define NB_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
33 | #define NB_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
34 | //NB_COMMAND |
35 | #define NB_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
36 | #define NB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
37 | #define NB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
38 | #define NB_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
39 | #define NB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
40 | #define NB_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
41 | //NB_STATUS |
42 | #define NB_STATUS__CAP_LIST__SHIFT 0x4 |
43 | #define NB_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
44 | #define NB_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
45 | #define NB_STATUS__CAP_LIST_MASK 0x0010L |
46 | #define NB_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
47 | #define NB_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
48 | //NB_SUB_CLASS |
49 | #define NB_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0 |
50 | #define NB_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL |
51 | //NB_BASE_CODE |
52 | #define NB_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0 |
53 | #define NB_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL |
54 | //NB_CACHE_LINE |
55 | #define NB_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
56 | #define NB_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
57 | //NB_LATENCY |
58 | #define NB_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
59 | #define NB_LATENCY__LATENCY_TIMER_MASK 0xFFL |
60 | //NB_HEADER |
61 | #define 0x0 |
62 | #define 0x7 |
63 | #define 0x7FL |
64 | #define 0x80L |
65 | //NB_ADAPTER_ID |
66 | #define NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
67 | #define NB_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
68 | #define NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
69 | #define NB_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
70 | //NB_CAPABILITIES_PTR |
71 | #define NB_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0 |
72 | #define NB_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL |
73 | //NB_HEADER_W |
74 | #define 0x7 |
75 | #define 0x00000080L |
76 | //NB_PCI_CTRL |
77 | #define NB_PCI_CTRL__PMEDis__SHIFT 0x4 |
78 | #define NB_PCI_CTRL__SErrDis__SHIFT 0x5 |
79 | #define NB_PCI_CTRL__MMIOEnable__SHIFT 0x17 |
80 | #define NB_PCI_CTRL__HPDis__SHIFT 0x1a |
81 | #define NB_PCI_CTRL__PMEDis_MASK 0x00000010L |
82 | #define NB_PCI_CTRL__SErrDis_MASK 0x00000020L |
83 | #define NB_PCI_CTRL__MMIOEnable_MASK 0x00800000L |
84 | #define NB_PCI_CTRL__HPDis_MASK 0x04000000L |
85 | //NB_ADAPTER_ID_W |
86 | #define NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
87 | #define NB_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
88 | #define NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
89 | #define NB_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
90 | //NBCFG_SCRATCH_0 |
91 | #define NBCFG_SCRATCH_0__NBCFG_SCRATCH_0__SHIFT 0x0 |
92 | #define NBCFG_SCRATCH_0__NBCFG_SCRATCH_0_MASK 0xFFFFFFFFL |
93 | //NBCFG_SCRATCH_1 |
94 | #define NBCFG_SCRATCH_1__NBCFG_SCRATCH_1__SHIFT 0x0 |
95 | #define NBCFG_SCRATCH_1__NBCFG_SCRATCH_1_MASK 0xFFFFFFFFL |
96 | //NBCFG_SCRATCH_2 |
97 | #define NBCFG_SCRATCH_2__NBCFG_SCRATCH_2__SHIFT 0x0 |
98 | #define NBCFG_SCRATCH_2__NBCFG_SCRATCH_2_MASK 0xFFFFFFFFL |
99 | //NBCFG_SCRATCH_3 |
100 | #define NBCFG_SCRATCH_3__NBCFG_SCRATCH_3__SHIFT 0x0 |
101 | #define NBCFG_SCRATCH_3__NBCFG_SCRATCH_3_MASK 0xFFFFFFFFL |
102 | //NBCFG_SCRATCH_4 |
103 | #define NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT 0x0 |
104 | #define NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK 0xFFFFFFFFL |
105 | //NB_PCI_ARB |
106 | #define NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 |
107 | #define NB_PCI_ARB__PMEMode__SHIFT 0x8 |
108 | #define NB_PCI_ARB__PMETurnOff__SHIFT 0x9 |
109 | #define NB_PCI_ARB__PMETOAckStatus__SHIFT 0xa |
110 | #define NB_PCI_ARB__PMETarget__SHIFT 0x10 |
111 | #define NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L |
112 | #define NB_PCI_ARB__PMEMode_MASK 0x00000100L |
113 | #define NB_PCI_ARB__PMETurnOff_MASK 0x00000200L |
114 | #define NB_PCI_ARB__PMETOAckStatus_MASK 0x00000400L |
115 | #define NB_PCI_ARB__PMETarget_MASK 0x00FF0000L |
116 | //NB_DRAM_SLOT1_BASE |
117 | #define NB_DRAM_SLOT1_BASE__DRAM_BASE__SHIFT 0x17 |
118 | #define NB_DRAM_SLOT1_BASE__DRAM_BASE_MASK 0xFF800000L |
119 | //NB_INDEX_DATA_MUTEX0 |
120 | #define NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0__SHIFT 0x0 |
121 | #define NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK__SHIFT 0x1f |
122 | #define NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_MASK 0x7FFFFFFFL |
123 | #define NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK_MASK 0x80000000L |
124 | //NB_INDEX_DATA_MUTEX1 |
125 | #define NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1__SHIFT 0x0 |
126 | #define NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK__SHIFT 0x1f |
127 | #define NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_MASK 0x7FFFFFFFL |
128 | #define NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK_MASK 0x80000000L |
129 | //NB_VENDOR_ID_W |
130 | #define NB_VENDOR_ID_W__VENDOR_ID__SHIFT 0x0 |
131 | #define NB_VENDOR_ID_W__VENDOR_ID_MASK 0xFFFFL |
132 | //NB_DEVICE_ID_W |
133 | #define NB_DEVICE_ID_W__DEVICE_ID__SHIFT 0x0 |
134 | #define NB_DEVICE_ID_W__DEVICE_ID_MASK 0xFFFFL |
135 | |
136 | |
137 | // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp |
138 | //BIF_CFG_DEV0_RC_VENDOR_ID |
139 | #define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
140 | #define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
141 | //BIF_CFG_DEV0_RC_DEVICE_ID |
142 | #define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
143 | #define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
144 | //BIF_CFG_DEV0_RC_COMMAND |
145 | #define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN__SHIFT 0x0 |
146 | #define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN__SHIFT 0x1 |
147 | #define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
148 | #define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
149 | #define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
150 | #define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
151 | #define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING__SHIFT 0x7 |
152 | #define BIF_CFG_DEV0_RC_COMMAND__SERR_EN__SHIFT 0x8 |
153 | #define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
154 | #define BIF_CFG_DEV0_RC_COMMAND__INT_DIS__SHIFT 0xa |
155 | #define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN_MASK 0x0001L |
156 | #define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN_MASK 0x0002L |
157 | #define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
158 | #define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
159 | #define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
160 | #define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
161 | #define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING_MASK 0x0080L |
162 | #define BIF_CFG_DEV0_RC_COMMAND__SERR_EN_MASK 0x0100L |
163 | #define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN_MASK 0x0200L |
164 | #define BIF_CFG_DEV0_RC_COMMAND__INT_DIS_MASK 0x0400L |
165 | //BIF_CFG_DEV0_RC_STATUS |
166 | #define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
167 | #define BIF_CFG_DEV0_RC_STATUS__INT_STATUS__SHIFT 0x3 |
168 | #define BIF_CFG_DEV0_RC_STATUS__CAP_LIST__SHIFT 0x4 |
169 | #define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP__SHIFT 0x5 |
170 | #define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
171 | #define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
172 | #define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
173 | #define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
174 | #define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
175 | #define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
176 | #define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
177 | #define BIF_CFG_DEV0_RC_STATUS__INT_STATUS_MASK 0x0008L |
178 | #define BIF_CFG_DEV0_RC_STATUS__CAP_LIST_MASK 0x0010L |
179 | #define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP_MASK 0x0020L |
180 | #define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
181 | #define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING_MASK 0x0600L |
182 | #define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
183 | #define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
184 | #define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
185 | #define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
186 | //BIF_CFG_DEV0_RC_REVISION_ID |
187 | #define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
188 | #define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
189 | #define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
190 | #define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
191 | //BIF_CFG_DEV0_RC_PROG_INTERFACE |
192 | #define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
193 | #define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
194 | //BIF_CFG_DEV0_RC_SUB_CLASS |
195 | #define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
196 | #define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
197 | //BIF_CFG_DEV0_RC_BASE_CLASS |
198 | #define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
199 | #define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
200 | //BIF_CFG_DEV0_RC_CACHE_LINE |
201 | #define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
202 | #define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
203 | //BIF_CFG_DEV0_RC_LATENCY |
204 | #define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
205 | #define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER_MASK 0xFFL |
206 | //BIF_CFG_DEV0_RC_HEADER |
207 | #define 0x0 |
208 | #define 0x7 |
209 | #define 0x7FL |
210 | #define 0x80L |
211 | //BIF_CFG_DEV0_RC_BIST |
212 | #define BIF_CFG_DEV0_RC_BIST__BIST_COMP__SHIFT 0x0 |
213 | #define BIF_CFG_DEV0_RC_BIST__BIST_STRT__SHIFT 0x6 |
214 | #define BIF_CFG_DEV0_RC_BIST__BIST_CAP__SHIFT 0x7 |
215 | #define BIF_CFG_DEV0_RC_BIST__BIST_COMP_MASK 0x0FL |
216 | #define BIF_CFG_DEV0_RC_BIST__BIST_STRT_MASK 0x40L |
217 | #define BIF_CFG_DEV0_RC_BIST__BIST_CAP_MASK 0x80L |
218 | //BIF_CFG_DEV0_RC_BASE_ADDR_1 |
219 | #define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
220 | #define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
221 | //BIF_CFG_DEV0_RC_BASE_ADDR_2 |
222 | #define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
223 | #define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
224 | //BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY |
225 | #define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
226 | #define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
227 | #define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
228 | #define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
229 | #define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
230 | #define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
231 | #define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
232 | #define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
233 | //BIF_CFG_DEV0_RC_IO_BASE_LIMIT |
234 | #define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
235 | #define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
236 | #define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
237 | #define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
238 | #define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
239 | #define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
240 | #define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
241 | #define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
242 | //BIF_CFG_DEV0_RC_SECONDARY_STATUS |
243 | #define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 |
244 | #define BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
245 | #define BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
246 | #define BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
247 | #define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
248 | #define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
249 | #define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
250 | #define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L |
251 | #define BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
252 | #define BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
253 | #define BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
254 | #define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
255 | #define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
256 | #define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
257 | //BIF_CFG_DEV0_RC_MEM_BASE_LIMIT |
258 | #define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
259 | #define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
260 | #define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
261 | #define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
262 | #define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
263 | #define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
264 | #define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
265 | #define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
266 | //BIF_CFG_DEV0_RC_PREF_BASE_LIMIT |
267 | #define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
268 | #define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
269 | #define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
270 | #define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
271 | #define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
272 | #define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
273 | #define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
274 | #define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
275 | //BIF_CFG_DEV0_RC_PREF_BASE_UPPER |
276 | #define BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
277 | #define BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
278 | //BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER |
279 | #define BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
280 | #define BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
281 | //BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI |
282 | #define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
283 | #define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
284 | #define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
285 | #define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
286 | //BIF_CFG_DEV0_RC_CAP_PTR |
287 | #define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR__SHIFT 0x0 |
288 | #define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR_MASK 0xFFL |
289 | //BIF_CFG_DEV0_RC_ROM_BASE_ADDR |
290 | #define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
291 | #define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
292 | //BIF_CFG_DEV0_RC_INTERRUPT_LINE |
293 | #define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
294 | #define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
295 | //BIF_CFG_DEV0_RC_INTERRUPT_PIN |
296 | #define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
297 | #define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
298 | //BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL |
299 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
300 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
301 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
302 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
303 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
304 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
305 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
306 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
307 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 |
308 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 |
309 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa |
310 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb |
311 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
312 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
313 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
314 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
315 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
316 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
317 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
318 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
319 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L |
320 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L |
321 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L |
322 | #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L |
323 | //BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL |
324 | #define BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
325 | #define BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
326 | //BIF_CFG_DEV0_RC_PMI_CAP_LIST |
327 | #define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
328 | #define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
329 | #define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
330 | #define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
331 | //BIF_CFG_DEV0_RC_PMI_CAP |
332 | #define BIF_CFG_DEV0_RC_PMI_CAP__VERSION__SHIFT 0x0 |
333 | #define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
334 | #define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
335 | #define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
336 | #define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
337 | #define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
338 | #define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
339 | #define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
340 | #define BIF_CFG_DEV0_RC_PMI_CAP__VERSION_MASK 0x0007L |
341 | #define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK_MASK 0x0008L |
342 | #define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
343 | #define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
344 | #define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
345 | #define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
346 | #define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
347 | #define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
348 | //BIF_CFG_DEV0_RC_PMI_STATUS_CNTL |
349 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
350 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
351 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
352 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
353 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
354 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
355 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
356 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
357 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
358 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
359 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
360 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
361 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
362 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
363 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
364 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
365 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
366 | #define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
367 | //BIF_CFG_DEV0_RC_PCIE_CAP_LIST |
368 | #define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
369 | #define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
370 | #define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
371 | #define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
372 | //BIF_CFG_DEV0_RC_PCIE_CAP |
373 | #define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION__SHIFT 0x0 |
374 | #define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
375 | #define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
376 | #define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
377 | #define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION_MASK 0x000FL |
378 | #define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
379 | #define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
380 | #define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
381 | //BIF_CFG_DEV0_RC_DEVICE_CAP |
382 | #define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
383 | #define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
384 | #define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
385 | #define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
386 | #define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
387 | #define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
388 | #define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
389 | #define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
390 | #define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
391 | #define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
392 | #define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
393 | #define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
394 | #define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
395 | #define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
396 | //BIF_CFG_DEV0_RC_DEVICE_CNTL |
397 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
398 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
399 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
400 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
401 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
402 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
403 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
404 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
405 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
406 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
407 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
408 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
409 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
410 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
411 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
412 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
413 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
414 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
415 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
416 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
417 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
418 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
419 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
420 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
421 | //BIF_CFG_DEV0_RC_DEVICE_STATUS |
422 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
423 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
424 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
425 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
426 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
427 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
428 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
429 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
430 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
431 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
432 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
433 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
434 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
435 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
436 | //BIF_CFG_DEV0_RC_LINK_CAP |
437 | #define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
438 | #define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
439 | #define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
440 | #define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
441 | #define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
442 | #define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
443 | #define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
444 | #define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
445 | #define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
446 | #define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
447 | #define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
448 | #define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
449 | #define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
450 | #define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
451 | #define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
452 | #define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
453 | #define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
454 | #define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
455 | #define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
456 | #define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
457 | #define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
458 | #define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
459 | //BIF_CFG_DEV0_RC_LINK_CNTL |
460 | #define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
461 | #define BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
462 | #define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
463 | #define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
464 | #define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
465 | #define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
466 | #define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
467 | #define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
468 | #define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
469 | #define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
470 | #define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
471 | #define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
472 | #define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
473 | #define BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
474 | #define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
475 | #define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS_MASK 0x0010L |
476 | #define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
477 | #define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
478 | #define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
479 | #define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
480 | #define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
481 | #define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
482 | #define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
483 | #define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
484 | //BIF_CFG_DEV0_RC_LINK_STATUS |
485 | #define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
486 | #define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
487 | #define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
488 | #define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
489 | #define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
490 | #define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
491 | #define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
492 | #define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
493 | #define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
494 | #define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
495 | #define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
496 | #define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
497 | #define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
498 | #define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
499 | //BIF_CFG_DEV0_RC_SLOT_CAP |
500 | #define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
501 | #define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
502 | #define BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
503 | #define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
504 | #define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
505 | #define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
506 | #define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
507 | #define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
508 | #define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
509 | #define BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
510 | #define BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
511 | #define BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
512 | #define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
513 | #define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
514 | #define BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
515 | #define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
516 | #define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
517 | #define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
518 | #define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
519 | #define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
520 | #define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
521 | #define BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
522 | #define BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
523 | #define BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
524 | //BIF_CFG_DEV0_RC_SLOT_CNTL |
525 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
526 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
527 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
528 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
529 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
530 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
531 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
532 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
533 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
534 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
535 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
536 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
537 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
538 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
539 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
540 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
541 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
542 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
543 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
544 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
545 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
546 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
547 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
548 | #define BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
549 | //BIF_CFG_DEV0_RC_SLOT_STATUS |
550 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
551 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
552 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
553 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
554 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
555 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
556 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
557 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
558 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
559 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
560 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
561 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
562 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
563 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
564 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
565 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
566 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
567 | #define BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
568 | //BIF_CFG_DEV0_RC_ROOT_CNTL |
569 | #define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
570 | #define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
571 | #define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
572 | #define BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
573 | #define BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
574 | #define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
575 | #define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
576 | #define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
577 | #define BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
578 | #define BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
579 | //BIF_CFG_DEV0_RC_ROOT_CAP |
580 | #define BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
581 | #define BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
582 | //BIF_CFG_DEV0_RC_ROOT_STATUS |
583 | #define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
584 | #define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
585 | #define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
586 | #define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
587 | #define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
588 | #define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
589 | //BIF_CFG_DEV0_RC_DEVICE_CAP2 |
590 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
591 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
592 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
593 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
594 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
595 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
596 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
597 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
598 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
599 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
600 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
601 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
602 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
603 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
604 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
605 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
606 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
607 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
608 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
609 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
610 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
611 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
612 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
613 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
614 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
615 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
616 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
617 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
618 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
619 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
620 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
621 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
622 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
623 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
624 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
625 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
626 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
627 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
628 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
629 | #define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
630 | //BIF_CFG_DEV0_RC_DEVICE_CNTL2 |
631 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
632 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
633 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
634 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
635 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
636 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
637 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
638 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
639 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
640 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
641 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
642 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
643 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
644 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
645 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
646 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
647 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
648 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
649 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
650 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
651 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
652 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
653 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
654 | #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
655 | //BIF_CFG_DEV0_RC_DEVICE_STATUS2 |
656 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
657 | #define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
658 | //BIF_CFG_DEV0_RC_LINK_CAP2 |
659 | #define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
660 | #define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
661 | #define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
662 | #define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
663 | #define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
664 | #define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
665 | #define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
666 | #define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
667 | #define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
668 | #define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
669 | #define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
670 | #define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
671 | #define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
672 | #define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
673 | //BIF_CFG_DEV0_RC_LINK_CNTL2 |
674 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
675 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
676 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
677 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
678 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
679 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
680 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
681 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
682 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
683 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
684 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
685 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
686 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
687 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
688 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
689 | #define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
690 | //BIF_CFG_DEV0_RC_LINK_STATUS2 |
691 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
692 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
693 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
694 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
695 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
696 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
697 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
698 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
699 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
700 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
701 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
702 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
703 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
704 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
705 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
706 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
707 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
708 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
709 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
710 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
711 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
712 | #define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
713 | //BIF_CFG_DEV0_RC_SLOT_CAP2 |
714 | #define BIF_CFG_DEV0_RC_SLOT_CAP2__RESERVED__SHIFT 0x0 |
715 | #define BIF_CFG_DEV0_RC_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
716 | //BIF_CFG_DEV0_RC_SLOT_CNTL2 |
717 | #define BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
718 | #define BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
719 | //BIF_CFG_DEV0_RC_SLOT_STATUS2 |
720 | #define BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
721 | #define BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
722 | //BIF_CFG_DEV0_RC_MSI_CAP_LIST |
723 | #define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
724 | #define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
725 | #define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
726 | #define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
727 | //BIF_CFG_DEV0_RC_MSI_MSG_CNTL |
728 | #define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
729 | #define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
730 | #define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
731 | #define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
732 | #define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
733 | #define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
734 | #define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
735 | #define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
736 | #define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
737 | #define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
738 | #define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
739 | #define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
740 | #define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
741 | #define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
742 | //BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO |
743 | #define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
744 | #define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
745 | //BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI |
746 | #define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
747 | #define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
748 | //BIF_CFG_DEV0_RC_MSI_MSG_DATA |
749 | #define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
750 | #define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
751 | //BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA |
752 | #define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
753 | #define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
754 | //BIF_CFG_DEV0_RC_MSI_MSG_DATA_64 |
755 | #define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
756 | #define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
757 | //BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64 |
758 | #define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
759 | #define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
760 | //BIF_CFG_DEV0_RC_SSID_CAP_LIST |
761 | #define BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
762 | #define BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
763 | #define BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
764 | #define BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
765 | //BIF_CFG_DEV0_RC_SSID_CAP |
766 | #define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
767 | #define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
768 | #define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
769 | #define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
770 | //BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST |
771 | #define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
772 | #define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
773 | #define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
774 | #define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
775 | //BIF_CFG_DEV0_RC_MSI_MAP_CAP |
776 | #define BIF_CFG_DEV0_RC_MSI_MAP_CAP__EN__SHIFT 0x0 |
777 | #define BIF_CFG_DEV0_RC_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
778 | #define BIF_CFG_DEV0_RC_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
779 | #define BIF_CFG_DEV0_RC_MSI_MAP_CAP__EN_MASK 0x0001L |
780 | #define BIF_CFG_DEV0_RC_MSI_MAP_CAP__FIXD_MASK 0x0002L |
781 | #define BIF_CFG_DEV0_RC_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
782 | //BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
783 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
784 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
785 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
786 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
787 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
788 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
789 | //BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR |
790 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
791 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
792 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
793 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
794 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
795 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
796 | //BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1 |
797 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
798 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
799 | //BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2 |
800 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
801 | #define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
802 | //BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST |
803 | #define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
804 | #define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
805 | #define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
806 | #define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
807 | #define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
808 | #define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
809 | //BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1 |
810 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
811 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
812 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
813 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
814 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
815 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
816 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
817 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
818 | //BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2 |
819 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
820 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
821 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
822 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
823 | //BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL |
824 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
825 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
826 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
827 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
828 | //BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS |
829 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
830 | #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
831 | //BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP |
832 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
833 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
834 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
835 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
836 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
837 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
838 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
839 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
840 | //BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL |
841 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
842 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
843 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
844 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
845 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
846 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
847 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
848 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
849 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
850 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
851 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
852 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
853 | //BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS |
854 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
855 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
856 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
857 | #define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
858 | //BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP |
859 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
860 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
861 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
862 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
863 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
864 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
865 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
866 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
867 | //BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL |
868 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
869 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
870 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
871 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
872 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
873 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
874 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
875 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
876 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
877 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
878 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
879 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
880 | //BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS |
881 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
882 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
883 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
884 | #define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
885 | //BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
886 | #define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
887 | #define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
888 | #define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
889 | #define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
890 | #define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
891 | #define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
892 | //BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1 |
893 | #define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
894 | #define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
895 | //BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2 |
896 | #define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
897 | #define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
898 | //BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
899 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
900 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
901 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
902 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
903 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
904 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
905 | //BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS |
906 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
907 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
908 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
909 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
910 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
911 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
912 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
913 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
914 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
915 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
916 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
917 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
918 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
919 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
920 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
921 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
922 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
923 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
924 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
925 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
926 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
927 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
928 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
929 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
930 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
931 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
932 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
933 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
934 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
935 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
936 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
937 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
938 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
939 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
940 | //BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK |
941 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
942 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
943 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
944 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
945 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
946 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
947 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
948 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
949 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
950 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
951 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
952 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
953 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
954 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
955 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
956 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
957 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
958 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
959 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
960 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
961 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
962 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
963 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
964 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
965 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
966 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
967 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
968 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
969 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
970 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
971 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
972 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
973 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
974 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
975 | //BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY |
976 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
977 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
978 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
979 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
980 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
981 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
982 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
983 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
984 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
985 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
986 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
987 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
988 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
989 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
990 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
991 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
992 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
993 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
994 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
995 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
996 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
997 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
998 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
999 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
1000 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
1001 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
1002 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
1003 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
1004 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
1005 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
1006 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
1007 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
1008 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
1009 | #define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
1010 | //BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS |
1011 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
1012 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
1013 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
1014 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
1015 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
1016 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
1017 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
1018 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
1019 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
1020 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
1021 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
1022 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
1023 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
1024 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
1025 | //BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK |
1026 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
1027 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
1028 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
1029 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
1030 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
1031 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
1032 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
1033 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
1034 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
1035 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
1036 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
1037 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
1038 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
1039 | #define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
1040 | //BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL |
1041 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
1042 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
1043 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
1044 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
1045 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
1046 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
1047 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
1048 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
1049 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
1050 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
1051 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
1052 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
1053 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
1054 | #define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
1055 | //BIF_CFG_DEV0_RC_PCIE_HDR_LOG0 |
1056 | #define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
1057 | #define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
1058 | //BIF_CFG_DEV0_RC_PCIE_HDR_LOG1 |
1059 | #define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
1060 | #define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
1061 | //BIF_CFG_DEV0_RC_PCIE_HDR_LOG2 |
1062 | #define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
1063 | #define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
1064 | //BIF_CFG_DEV0_RC_PCIE_HDR_LOG3 |
1065 | #define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
1066 | #define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
1067 | //BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD |
1068 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
1069 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
1070 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
1071 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
1072 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
1073 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
1074 | //BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS |
1075 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
1076 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
1077 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
1078 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
1079 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
1080 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
1081 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
1082 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
1083 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
1084 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
1085 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
1086 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
1087 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
1088 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
1089 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
1090 | #define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
1091 | //BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID |
1092 | #define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
1093 | #define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
1094 | #define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
1095 | #define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
1096 | //BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0 |
1097 | #define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
1098 | #define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
1099 | //BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1 |
1100 | #define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
1101 | #define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
1102 | //BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2 |
1103 | #define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
1104 | #define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
1105 | //BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3 |
1106 | #define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
1107 | #define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
1108 | //BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST |
1109 | #define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
1110 | #define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
1111 | #define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
1112 | #define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
1113 | #define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
1114 | #define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
1115 | //BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3 |
1116 | #define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
1117 | #define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
1118 | #define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
1119 | #define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
1120 | #define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
1121 | #define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
1122 | //BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS |
1123 | #define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
1124 | #define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
1125 | //BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL |
1126 | #define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1127 | #define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1128 | #define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1129 | #define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1130 | #define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1131 | #define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1132 | #define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1133 | #define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1134 | //BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL |
1135 | #define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1136 | #define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1137 | #define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1138 | #define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1139 | #define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1140 | #define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1141 | #define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1142 | #define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1143 | //BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL |
1144 | #define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1145 | #define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1146 | #define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1147 | #define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1148 | #define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1149 | #define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1150 | #define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1151 | #define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1152 | //BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL |
1153 | #define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1154 | #define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1155 | #define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1156 | #define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1157 | #define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1158 | #define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1159 | #define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1160 | #define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1161 | //BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL |
1162 | #define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1163 | #define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1164 | #define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1165 | #define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1166 | #define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1167 | #define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1168 | #define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1169 | #define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1170 | //BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL |
1171 | #define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1172 | #define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1173 | #define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1174 | #define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1175 | #define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1176 | #define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1177 | #define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1178 | #define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1179 | //BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL |
1180 | #define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1181 | #define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1182 | #define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1183 | #define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1184 | #define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1185 | #define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1186 | #define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1187 | #define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1188 | //BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL |
1189 | #define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1190 | #define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1191 | #define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1192 | #define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1193 | #define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1194 | #define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1195 | #define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1196 | #define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1197 | //BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL |
1198 | #define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1199 | #define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1200 | #define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1201 | #define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1202 | #define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1203 | #define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1204 | #define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1205 | #define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1206 | //BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL |
1207 | #define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1208 | #define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1209 | #define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1210 | #define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1211 | #define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1212 | #define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1213 | #define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1214 | #define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1215 | //BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL |
1216 | #define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1217 | #define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1218 | #define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1219 | #define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1220 | #define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1221 | #define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1222 | #define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1223 | #define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1224 | //BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL |
1225 | #define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1226 | #define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1227 | #define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1228 | #define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1229 | #define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1230 | #define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1231 | #define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1232 | #define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1233 | //BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL |
1234 | #define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1235 | #define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1236 | #define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1237 | #define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1238 | #define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1239 | #define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1240 | #define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1241 | #define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1242 | //BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL |
1243 | #define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1244 | #define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1245 | #define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1246 | #define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1247 | #define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1248 | #define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1249 | #define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1250 | #define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1251 | //BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL |
1252 | #define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1253 | #define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1254 | #define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1255 | #define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1256 | #define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1257 | #define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1258 | #define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1259 | #define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1260 | //BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL |
1261 | #define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
1262 | #define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
1263 | #define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
1264 | #define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
1265 | #define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
1266 | #define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
1267 | #define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
1268 | #define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
1269 | //BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST |
1270 | #define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
1271 | #define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
1272 | #define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
1273 | #define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
1274 | #define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
1275 | #define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
1276 | //BIF_CFG_DEV0_RC_PCIE_ACS_CAP |
1277 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
1278 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
1279 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
1280 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
1281 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
1282 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
1283 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
1284 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
1285 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
1286 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
1287 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
1288 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
1289 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
1290 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
1291 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
1292 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
1293 | //BIF_CFG_DEV0_RC_PCIE_ACS_CNTL |
1294 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
1295 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
1296 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
1297 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
1298 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
1299 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
1300 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
1301 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
1302 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
1303 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
1304 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
1305 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
1306 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
1307 | #define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
1308 | //BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST |
1309 | #define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
1310 | #define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
1311 | #define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
1312 | #define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
1313 | #define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
1314 | #define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
1315 | //BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP |
1316 | #define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
1317 | #define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
1318 | #define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
1319 | #define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
1320 | //BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS |
1321 | #define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
1322 | #define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
1323 | #define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
1324 | #define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
1325 | //BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST |
1326 | #define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
1327 | #define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
1328 | #define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
1329 | #define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
1330 | #define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
1331 | #define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
1332 | //BIF_CFG_DEV0_RC_LINK_CAP_16GT |
1333 | #define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
1334 | #define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
1335 | //BIF_CFG_DEV0_RC_LINK_CNTL_16GT |
1336 | #define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
1337 | #define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
1338 | //BIF_CFG_DEV0_RC_LINK_STATUS_16GT |
1339 | #define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
1340 | #define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
1341 | #define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
1342 | #define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
1343 | #define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
1344 | #define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
1345 | #define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
1346 | #define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
1347 | #define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
1348 | #define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
1349 | //BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT |
1350 | #define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
1351 | #define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
1352 | //BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT |
1353 | #define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
1354 | #define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
1355 | //BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT |
1356 | #define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
1357 | #define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
1358 | //BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT |
1359 | #define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1360 | #define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
1361 | #define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
1362 | #define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
1363 | //BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT |
1364 | #define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1365 | #define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
1366 | #define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
1367 | #define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
1368 | //BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT |
1369 | #define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1370 | #define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
1371 | #define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
1372 | #define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
1373 | //BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT |
1374 | #define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1375 | #define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
1376 | #define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
1377 | #define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
1378 | //BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT |
1379 | #define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1380 | #define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
1381 | #define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
1382 | #define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
1383 | //BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT |
1384 | #define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1385 | #define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
1386 | #define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
1387 | #define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
1388 | //BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT |
1389 | #define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1390 | #define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
1391 | #define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
1392 | #define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
1393 | //BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT |
1394 | #define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1395 | #define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
1396 | #define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
1397 | #define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
1398 | //BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT |
1399 | #define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1400 | #define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
1401 | #define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
1402 | #define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
1403 | //BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT |
1404 | #define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1405 | #define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
1406 | #define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
1407 | #define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
1408 | //BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT |
1409 | #define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1410 | #define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
1411 | #define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
1412 | #define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
1413 | //BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT |
1414 | #define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1415 | #define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
1416 | #define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
1417 | #define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
1418 | //BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT |
1419 | #define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1420 | #define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
1421 | #define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
1422 | #define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
1423 | //BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT |
1424 | #define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1425 | #define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
1426 | #define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
1427 | #define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
1428 | //BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT |
1429 | #define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1430 | #define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
1431 | #define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
1432 | #define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
1433 | //BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT |
1434 | #define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
1435 | #define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
1436 | #define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
1437 | #define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
1438 | //BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST |
1439 | #define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
1440 | #define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
1441 | #define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
1442 | #define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
1443 | #define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
1444 | #define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
1445 | //BIF_CFG_DEV0_RC_MARGINING_PORT_CAP |
1446 | #define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
1447 | #define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
1448 | //BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS |
1449 | #define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
1450 | #define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
1451 | #define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
1452 | #define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
1453 | //BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL |
1454 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
1455 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
1456 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
1457 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
1458 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
1459 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
1460 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
1461 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
1462 | //BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS |
1463 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1464 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1465 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
1466 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1467 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1468 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
1469 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
1470 | #define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1471 | //BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL |
1472 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
1473 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
1474 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
1475 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
1476 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
1477 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
1478 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
1479 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
1480 | //BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS |
1481 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1482 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1483 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
1484 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1485 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1486 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
1487 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
1488 | #define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1489 | //BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL |
1490 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
1491 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
1492 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
1493 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
1494 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
1495 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
1496 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
1497 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
1498 | //BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS |
1499 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1500 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1501 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
1502 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1503 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1504 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
1505 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
1506 | #define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1507 | //BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL |
1508 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
1509 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
1510 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
1511 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
1512 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
1513 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
1514 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
1515 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
1516 | //BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS |
1517 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1518 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1519 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
1520 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1521 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1522 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
1523 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
1524 | #define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1525 | //BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL |
1526 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
1527 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
1528 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
1529 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
1530 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
1531 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
1532 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
1533 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
1534 | //BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS |
1535 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1536 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1537 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
1538 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1539 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1540 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
1541 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
1542 | #define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1543 | //BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL |
1544 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
1545 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
1546 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
1547 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
1548 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
1549 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
1550 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
1551 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
1552 | //BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS |
1553 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1554 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1555 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
1556 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1557 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1558 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
1559 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
1560 | #define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1561 | //BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL |
1562 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
1563 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
1564 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
1565 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
1566 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
1567 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
1568 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
1569 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
1570 | //BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS |
1571 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1572 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1573 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
1574 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1575 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1576 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
1577 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
1578 | #define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1579 | //BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL |
1580 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
1581 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
1582 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
1583 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
1584 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
1585 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
1586 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
1587 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
1588 | //BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS |
1589 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1590 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1591 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
1592 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1593 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1594 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
1595 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
1596 | #define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1597 | //BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL |
1598 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
1599 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
1600 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
1601 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
1602 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
1603 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
1604 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
1605 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
1606 | //BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS |
1607 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1608 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1609 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
1610 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1611 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1612 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
1613 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
1614 | #define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1615 | //BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL |
1616 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
1617 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
1618 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
1619 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
1620 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
1621 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
1622 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
1623 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
1624 | //BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS |
1625 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1626 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1627 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
1628 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1629 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1630 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
1631 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
1632 | #define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1633 | //BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL |
1634 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
1635 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
1636 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
1637 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
1638 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
1639 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
1640 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
1641 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
1642 | //BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS |
1643 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1644 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1645 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
1646 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1647 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1648 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
1649 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
1650 | #define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1651 | //BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL |
1652 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
1653 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
1654 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
1655 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
1656 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
1657 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
1658 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
1659 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
1660 | //BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS |
1661 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1662 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1663 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
1664 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1665 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1666 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
1667 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
1668 | #define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1669 | //BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL |
1670 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
1671 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
1672 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
1673 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
1674 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
1675 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
1676 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
1677 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
1678 | //BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS |
1679 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1680 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1681 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
1682 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1683 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1684 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
1685 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
1686 | #define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1687 | //BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL |
1688 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
1689 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
1690 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
1691 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
1692 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
1693 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
1694 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
1695 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
1696 | //BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS |
1697 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1698 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1699 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
1700 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1701 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1702 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
1703 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
1704 | #define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1705 | //BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL |
1706 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
1707 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
1708 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
1709 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
1710 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
1711 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
1712 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
1713 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
1714 | //BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS |
1715 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1716 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1717 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
1718 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1719 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1720 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
1721 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
1722 | #define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1723 | //BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL |
1724 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
1725 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
1726 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
1727 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
1728 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
1729 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
1730 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
1731 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
1732 | //BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS |
1733 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
1734 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
1735 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
1736 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
1737 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
1738 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
1739 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
1740 | #define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
1741 | //BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST |
1742 | #define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
1743 | #define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
1744 | #define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
1745 | #define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
1746 | #define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
1747 | #define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
1748 | //BIF_CFG_DEV0_RC_RTR_DATA1 |
1749 | #define BIF_CFG_DEV0_RC_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
1750 | #define BIF_CFG_DEV0_RC_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
1751 | #define BIF_CFG_DEV0_RC_RTR_DATA1__VALID__SHIFT 0x1f |
1752 | #define BIF_CFG_DEV0_RC_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
1753 | #define BIF_CFG_DEV0_RC_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
1754 | #define BIF_CFG_DEV0_RC_RTR_DATA1__VALID_MASK 0x80000000L |
1755 | //BIF_CFG_DEV0_RC_RTR_DATA2 |
1756 | #define BIF_CFG_DEV0_RC_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
1757 | #define BIF_CFG_DEV0_RC_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
1758 | #define BIF_CFG_DEV0_RC_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
1759 | #define BIF_CFG_DEV0_RC_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
1760 | |
1761 | |
1762 | // addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp |
1763 | //BIF_CFG_DEV1_RC_VENDOR_ID |
1764 | #define BIF_CFG_DEV1_RC_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
1765 | #define BIF_CFG_DEV1_RC_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
1766 | //BIF_CFG_DEV1_RC_DEVICE_ID |
1767 | #define BIF_CFG_DEV1_RC_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
1768 | #define BIF_CFG_DEV1_RC_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
1769 | //BIF_CFG_DEV1_RC_COMMAND |
1770 | #define BIF_CFG_DEV1_RC_COMMAND__IOEN_DN__SHIFT 0x0 |
1771 | #define BIF_CFG_DEV1_RC_COMMAND__MEMEN_DN__SHIFT 0x1 |
1772 | #define BIF_CFG_DEV1_RC_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
1773 | #define BIF_CFG_DEV1_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
1774 | #define BIF_CFG_DEV1_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
1775 | #define BIF_CFG_DEV1_RC_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
1776 | #define BIF_CFG_DEV1_RC_COMMAND__AD_STEPPING__SHIFT 0x7 |
1777 | #define BIF_CFG_DEV1_RC_COMMAND__SERR_EN__SHIFT 0x8 |
1778 | #define BIF_CFG_DEV1_RC_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
1779 | #define BIF_CFG_DEV1_RC_COMMAND__INT_DIS__SHIFT 0xa |
1780 | #define BIF_CFG_DEV1_RC_COMMAND__IOEN_DN_MASK 0x0001L |
1781 | #define BIF_CFG_DEV1_RC_COMMAND__MEMEN_DN_MASK 0x0002L |
1782 | #define BIF_CFG_DEV1_RC_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
1783 | #define BIF_CFG_DEV1_RC_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
1784 | #define BIF_CFG_DEV1_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
1785 | #define BIF_CFG_DEV1_RC_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
1786 | #define BIF_CFG_DEV1_RC_COMMAND__AD_STEPPING_MASK 0x0080L |
1787 | #define BIF_CFG_DEV1_RC_COMMAND__SERR_EN_MASK 0x0100L |
1788 | #define BIF_CFG_DEV1_RC_COMMAND__FAST_B2B_EN_MASK 0x0200L |
1789 | #define BIF_CFG_DEV1_RC_COMMAND__INT_DIS_MASK 0x0400L |
1790 | //BIF_CFG_DEV1_RC_STATUS |
1791 | #define BIF_CFG_DEV1_RC_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
1792 | #define BIF_CFG_DEV1_RC_STATUS__INT_STATUS__SHIFT 0x3 |
1793 | #define BIF_CFG_DEV1_RC_STATUS__CAP_LIST__SHIFT 0x4 |
1794 | #define BIF_CFG_DEV1_RC_STATUS__PCI_66_CAP__SHIFT 0x5 |
1795 | #define BIF_CFG_DEV1_RC_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
1796 | #define BIF_CFG_DEV1_RC_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
1797 | #define BIF_CFG_DEV1_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
1798 | #define BIF_CFG_DEV1_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
1799 | #define BIF_CFG_DEV1_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
1800 | #define BIF_CFG_DEV1_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
1801 | #define BIF_CFG_DEV1_RC_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
1802 | #define BIF_CFG_DEV1_RC_STATUS__INT_STATUS_MASK 0x0008L |
1803 | #define BIF_CFG_DEV1_RC_STATUS__CAP_LIST_MASK 0x0010L |
1804 | #define BIF_CFG_DEV1_RC_STATUS__PCI_66_CAP_MASK 0x0020L |
1805 | #define BIF_CFG_DEV1_RC_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
1806 | #define BIF_CFG_DEV1_RC_STATUS__DEVSEL_TIMING_MASK 0x0600L |
1807 | #define BIF_CFG_DEV1_RC_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
1808 | #define BIF_CFG_DEV1_RC_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
1809 | #define BIF_CFG_DEV1_RC_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
1810 | #define BIF_CFG_DEV1_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
1811 | //BIF_CFG_DEV1_RC_REVISION_ID |
1812 | #define BIF_CFG_DEV1_RC_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
1813 | #define BIF_CFG_DEV1_RC_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
1814 | #define BIF_CFG_DEV1_RC_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
1815 | #define BIF_CFG_DEV1_RC_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
1816 | //BIF_CFG_DEV1_RC_PROG_INTERFACE |
1817 | #define BIF_CFG_DEV1_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
1818 | #define BIF_CFG_DEV1_RC_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
1819 | //BIF_CFG_DEV1_RC_SUB_CLASS |
1820 | #define BIF_CFG_DEV1_RC_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
1821 | #define BIF_CFG_DEV1_RC_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
1822 | //BIF_CFG_DEV1_RC_BASE_CLASS |
1823 | #define BIF_CFG_DEV1_RC_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
1824 | #define BIF_CFG_DEV1_RC_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
1825 | //BIF_CFG_DEV1_RC_CACHE_LINE |
1826 | #define BIF_CFG_DEV1_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
1827 | #define BIF_CFG_DEV1_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
1828 | //BIF_CFG_DEV1_RC_LATENCY |
1829 | #define BIF_CFG_DEV1_RC_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
1830 | #define BIF_CFG_DEV1_RC_LATENCY__LATENCY_TIMER_MASK 0xFFL |
1831 | //BIF_CFG_DEV1_RC_HEADER |
1832 | #define 0x0 |
1833 | #define 0x7 |
1834 | #define 0x7FL |
1835 | #define 0x80L |
1836 | //BIF_CFG_DEV1_RC_BIST |
1837 | #define BIF_CFG_DEV1_RC_BIST__BIST_COMP__SHIFT 0x0 |
1838 | #define BIF_CFG_DEV1_RC_BIST__BIST_STRT__SHIFT 0x6 |
1839 | #define BIF_CFG_DEV1_RC_BIST__BIST_CAP__SHIFT 0x7 |
1840 | #define BIF_CFG_DEV1_RC_BIST__BIST_COMP_MASK 0x0FL |
1841 | #define BIF_CFG_DEV1_RC_BIST__BIST_STRT_MASK 0x40L |
1842 | #define BIF_CFG_DEV1_RC_BIST__BIST_CAP_MASK 0x80L |
1843 | //BIF_CFG_DEV1_RC_BASE_ADDR_1 |
1844 | #define BIF_CFG_DEV1_RC_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
1845 | #define BIF_CFG_DEV1_RC_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
1846 | //BIF_CFG_DEV1_RC_BASE_ADDR_2 |
1847 | #define BIF_CFG_DEV1_RC_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
1848 | #define BIF_CFG_DEV1_RC_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
1849 | //BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY |
1850 | #define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
1851 | #define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
1852 | #define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
1853 | #define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
1854 | #define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
1855 | #define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
1856 | #define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
1857 | #define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
1858 | //BIF_CFG_DEV1_RC_IO_BASE_LIMIT |
1859 | #define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
1860 | #define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
1861 | #define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
1862 | #define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
1863 | #define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
1864 | #define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
1865 | #define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
1866 | #define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
1867 | //BIF_CFG_DEV1_RC_SECONDARY_STATUS |
1868 | #define BIF_CFG_DEV1_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 |
1869 | #define BIF_CFG_DEV1_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
1870 | #define BIF_CFG_DEV1_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
1871 | #define BIF_CFG_DEV1_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
1872 | #define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
1873 | #define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
1874 | #define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
1875 | #define BIF_CFG_DEV1_RC_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L |
1876 | #define BIF_CFG_DEV1_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
1877 | #define BIF_CFG_DEV1_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
1878 | #define BIF_CFG_DEV1_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
1879 | #define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
1880 | #define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
1881 | #define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
1882 | //BIF_CFG_DEV1_RC_MEM_BASE_LIMIT |
1883 | #define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
1884 | #define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
1885 | #define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
1886 | #define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
1887 | #define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
1888 | #define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
1889 | #define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
1890 | #define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
1891 | //BIF_CFG_DEV1_RC_PREF_BASE_LIMIT |
1892 | #define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
1893 | #define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
1894 | #define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
1895 | #define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
1896 | #define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
1897 | #define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
1898 | #define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
1899 | #define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
1900 | //BIF_CFG_DEV1_RC_PREF_BASE_UPPER |
1901 | #define BIF_CFG_DEV1_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
1902 | #define BIF_CFG_DEV1_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
1903 | //BIF_CFG_DEV1_RC_PREF_LIMIT_UPPER |
1904 | #define BIF_CFG_DEV1_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
1905 | #define BIF_CFG_DEV1_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
1906 | //BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI |
1907 | #define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
1908 | #define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
1909 | #define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
1910 | #define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
1911 | //BIF_CFG_DEV1_RC_CAP_PTR |
1912 | #define BIF_CFG_DEV1_RC_CAP_PTR__CAP_PTR__SHIFT 0x0 |
1913 | #define BIF_CFG_DEV1_RC_CAP_PTR__CAP_PTR_MASK 0xFFL |
1914 | //BIF_CFG_DEV1_RC_ROM_BASE_ADDR |
1915 | #define BIF_CFG_DEV1_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
1916 | #define BIF_CFG_DEV1_RC_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
1917 | //BIF_CFG_DEV1_RC_INTERRUPT_LINE |
1918 | #define BIF_CFG_DEV1_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
1919 | #define BIF_CFG_DEV1_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
1920 | //BIF_CFG_DEV1_RC_INTERRUPT_PIN |
1921 | #define BIF_CFG_DEV1_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
1922 | #define BIF_CFG_DEV1_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
1923 | //BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL |
1924 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
1925 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
1926 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
1927 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
1928 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
1929 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
1930 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
1931 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
1932 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 |
1933 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 |
1934 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa |
1935 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb |
1936 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
1937 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
1938 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
1939 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
1940 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
1941 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
1942 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
1943 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
1944 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L |
1945 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L |
1946 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L |
1947 | #define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L |
1948 | //BIF_CFG_DEV1_RC_EXT_BRIDGE_CNTL |
1949 | #define BIF_CFG_DEV1_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
1950 | #define BIF_CFG_DEV1_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
1951 | //BIF_CFG_DEV1_RC_PMI_CAP_LIST |
1952 | #define BIF_CFG_DEV1_RC_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
1953 | #define BIF_CFG_DEV1_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
1954 | #define BIF_CFG_DEV1_RC_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
1955 | #define BIF_CFG_DEV1_RC_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
1956 | //BIF_CFG_DEV1_RC_PMI_CAP |
1957 | #define BIF_CFG_DEV1_RC_PMI_CAP__VERSION__SHIFT 0x0 |
1958 | #define BIF_CFG_DEV1_RC_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
1959 | #define BIF_CFG_DEV1_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
1960 | #define BIF_CFG_DEV1_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
1961 | #define BIF_CFG_DEV1_RC_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
1962 | #define BIF_CFG_DEV1_RC_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
1963 | #define BIF_CFG_DEV1_RC_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
1964 | #define BIF_CFG_DEV1_RC_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
1965 | #define BIF_CFG_DEV1_RC_PMI_CAP__VERSION_MASK 0x0007L |
1966 | #define BIF_CFG_DEV1_RC_PMI_CAP__PME_CLOCK_MASK 0x0008L |
1967 | #define BIF_CFG_DEV1_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
1968 | #define BIF_CFG_DEV1_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
1969 | #define BIF_CFG_DEV1_RC_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
1970 | #define BIF_CFG_DEV1_RC_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
1971 | #define BIF_CFG_DEV1_RC_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
1972 | #define BIF_CFG_DEV1_RC_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
1973 | //BIF_CFG_DEV1_RC_PMI_STATUS_CNTL |
1974 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
1975 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
1976 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
1977 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
1978 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
1979 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
1980 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
1981 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
1982 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
1983 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
1984 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
1985 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
1986 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
1987 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
1988 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
1989 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
1990 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
1991 | #define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
1992 | //BIF_CFG_DEV1_RC_PCIE_CAP_LIST |
1993 | #define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
1994 | #define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
1995 | #define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
1996 | #define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
1997 | //BIF_CFG_DEV1_RC_PCIE_CAP |
1998 | #define BIF_CFG_DEV1_RC_PCIE_CAP__VERSION__SHIFT 0x0 |
1999 | #define BIF_CFG_DEV1_RC_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
2000 | #define BIF_CFG_DEV1_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
2001 | #define BIF_CFG_DEV1_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
2002 | #define BIF_CFG_DEV1_RC_PCIE_CAP__VERSION_MASK 0x000FL |
2003 | #define BIF_CFG_DEV1_RC_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
2004 | #define BIF_CFG_DEV1_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
2005 | #define BIF_CFG_DEV1_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
2006 | //BIF_CFG_DEV1_RC_DEVICE_CAP |
2007 | #define BIF_CFG_DEV1_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
2008 | #define BIF_CFG_DEV1_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
2009 | #define BIF_CFG_DEV1_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
2010 | #define BIF_CFG_DEV1_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
2011 | #define BIF_CFG_DEV1_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
2012 | #define BIF_CFG_DEV1_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
2013 | #define BIF_CFG_DEV1_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
2014 | #define BIF_CFG_DEV1_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
2015 | #define BIF_CFG_DEV1_RC_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
2016 | #define BIF_CFG_DEV1_RC_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
2017 | #define BIF_CFG_DEV1_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
2018 | #define BIF_CFG_DEV1_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
2019 | #define BIF_CFG_DEV1_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
2020 | #define BIF_CFG_DEV1_RC_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
2021 | //BIF_CFG_DEV1_RC_DEVICE_CNTL |
2022 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
2023 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
2024 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
2025 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
2026 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
2027 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
2028 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
2029 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
2030 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
2031 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
2032 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
2033 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
2034 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
2035 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
2036 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
2037 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
2038 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
2039 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
2040 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
2041 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
2042 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
2043 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
2044 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
2045 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
2046 | //BIF_CFG_DEV1_RC_DEVICE_STATUS |
2047 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
2048 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
2049 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
2050 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
2051 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
2052 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
2053 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
2054 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
2055 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
2056 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
2057 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
2058 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
2059 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
2060 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
2061 | //BIF_CFG_DEV1_RC_LINK_CAP |
2062 | #define BIF_CFG_DEV1_RC_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
2063 | #define BIF_CFG_DEV1_RC_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
2064 | #define BIF_CFG_DEV1_RC_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
2065 | #define BIF_CFG_DEV1_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
2066 | #define BIF_CFG_DEV1_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
2067 | #define BIF_CFG_DEV1_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
2068 | #define BIF_CFG_DEV1_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
2069 | #define BIF_CFG_DEV1_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
2070 | #define BIF_CFG_DEV1_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
2071 | #define BIF_CFG_DEV1_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
2072 | #define BIF_CFG_DEV1_RC_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
2073 | #define BIF_CFG_DEV1_RC_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
2074 | #define BIF_CFG_DEV1_RC_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
2075 | #define BIF_CFG_DEV1_RC_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
2076 | #define BIF_CFG_DEV1_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
2077 | #define BIF_CFG_DEV1_RC_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
2078 | #define BIF_CFG_DEV1_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
2079 | #define BIF_CFG_DEV1_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
2080 | #define BIF_CFG_DEV1_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
2081 | #define BIF_CFG_DEV1_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
2082 | #define BIF_CFG_DEV1_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
2083 | #define BIF_CFG_DEV1_RC_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
2084 | //BIF_CFG_DEV1_RC_LINK_CNTL |
2085 | #define BIF_CFG_DEV1_RC_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
2086 | #define BIF_CFG_DEV1_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
2087 | #define BIF_CFG_DEV1_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
2088 | #define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
2089 | #define BIF_CFG_DEV1_RC_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
2090 | #define BIF_CFG_DEV1_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
2091 | #define BIF_CFG_DEV1_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
2092 | #define BIF_CFG_DEV1_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
2093 | #define BIF_CFG_DEV1_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
2094 | #define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
2095 | #define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
2096 | #define BIF_CFG_DEV1_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
2097 | #define BIF_CFG_DEV1_RC_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
2098 | #define BIF_CFG_DEV1_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
2099 | #define BIF_CFG_DEV1_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
2100 | #define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_DIS_MASK 0x0010L |
2101 | #define BIF_CFG_DEV1_RC_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
2102 | #define BIF_CFG_DEV1_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
2103 | #define BIF_CFG_DEV1_RC_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
2104 | #define BIF_CFG_DEV1_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
2105 | #define BIF_CFG_DEV1_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
2106 | #define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
2107 | #define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
2108 | #define BIF_CFG_DEV1_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
2109 | //BIF_CFG_DEV1_RC_LINK_STATUS |
2110 | #define BIF_CFG_DEV1_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
2111 | #define BIF_CFG_DEV1_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
2112 | #define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
2113 | #define BIF_CFG_DEV1_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
2114 | #define BIF_CFG_DEV1_RC_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
2115 | #define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
2116 | #define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
2117 | #define BIF_CFG_DEV1_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
2118 | #define BIF_CFG_DEV1_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
2119 | #define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
2120 | #define BIF_CFG_DEV1_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
2121 | #define BIF_CFG_DEV1_RC_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
2122 | #define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
2123 | #define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
2124 | //BIF_CFG_DEV1_RC_SLOT_CAP |
2125 | #define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
2126 | #define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
2127 | #define BIF_CFG_DEV1_RC_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
2128 | #define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
2129 | #define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
2130 | #define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
2131 | #define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
2132 | #define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
2133 | #define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
2134 | #define BIF_CFG_DEV1_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
2135 | #define BIF_CFG_DEV1_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
2136 | #define BIF_CFG_DEV1_RC_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
2137 | #define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
2138 | #define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
2139 | #define BIF_CFG_DEV1_RC_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
2140 | #define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
2141 | #define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
2142 | #define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
2143 | #define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
2144 | #define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
2145 | #define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
2146 | #define BIF_CFG_DEV1_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
2147 | #define BIF_CFG_DEV1_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
2148 | #define BIF_CFG_DEV1_RC_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
2149 | //BIF_CFG_DEV1_RC_SLOT_CNTL |
2150 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
2151 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
2152 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
2153 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
2154 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
2155 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
2156 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
2157 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
2158 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
2159 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
2160 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
2161 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
2162 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
2163 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
2164 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
2165 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
2166 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
2167 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
2168 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
2169 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
2170 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
2171 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
2172 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
2173 | #define BIF_CFG_DEV1_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
2174 | //BIF_CFG_DEV1_RC_SLOT_STATUS |
2175 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
2176 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
2177 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
2178 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
2179 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
2180 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
2181 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
2182 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
2183 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
2184 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
2185 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
2186 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
2187 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
2188 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
2189 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
2190 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
2191 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
2192 | #define BIF_CFG_DEV1_RC_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
2193 | //BIF_CFG_DEV1_RC_ROOT_CNTL |
2194 | #define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
2195 | #define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
2196 | #define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
2197 | #define BIF_CFG_DEV1_RC_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
2198 | #define BIF_CFG_DEV1_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
2199 | #define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
2200 | #define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
2201 | #define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
2202 | #define BIF_CFG_DEV1_RC_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
2203 | #define BIF_CFG_DEV1_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
2204 | //BIF_CFG_DEV1_RC_ROOT_CAP |
2205 | #define BIF_CFG_DEV1_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
2206 | #define BIF_CFG_DEV1_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
2207 | //BIF_CFG_DEV1_RC_ROOT_STATUS |
2208 | #define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
2209 | #define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
2210 | #define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
2211 | #define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
2212 | #define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
2213 | #define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
2214 | //BIF_CFG_DEV1_RC_DEVICE_CAP2 |
2215 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
2216 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
2217 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
2218 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
2219 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
2220 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
2221 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
2222 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
2223 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
2224 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
2225 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
2226 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
2227 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
2228 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
2229 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
2230 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
2231 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
2232 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
2233 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
2234 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
2235 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
2236 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
2237 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
2238 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
2239 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
2240 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
2241 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
2242 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
2243 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
2244 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
2245 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
2246 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
2247 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
2248 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
2249 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
2250 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
2251 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
2252 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
2253 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
2254 | #define BIF_CFG_DEV1_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
2255 | //BIF_CFG_DEV1_RC_DEVICE_CNTL2 |
2256 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
2257 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
2258 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
2259 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
2260 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
2261 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
2262 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
2263 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
2264 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
2265 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
2266 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
2267 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
2268 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
2269 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
2270 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
2271 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
2272 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
2273 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
2274 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
2275 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
2276 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
2277 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
2278 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
2279 | #define BIF_CFG_DEV1_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
2280 | //BIF_CFG_DEV1_RC_DEVICE_STATUS2 |
2281 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
2282 | #define BIF_CFG_DEV1_RC_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
2283 | //BIF_CFG_DEV1_RC_LINK_CAP2 |
2284 | #define BIF_CFG_DEV1_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
2285 | #define BIF_CFG_DEV1_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
2286 | #define BIF_CFG_DEV1_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
2287 | #define BIF_CFG_DEV1_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
2288 | #define BIF_CFG_DEV1_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
2289 | #define BIF_CFG_DEV1_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
2290 | #define BIF_CFG_DEV1_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
2291 | #define BIF_CFG_DEV1_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
2292 | #define BIF_CFG_DEV1_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
2293 | #define BIF_CFG_DEV1_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
2294 | #define BIF_CFG_DEV1_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
2295 | #define BIF_CFG_DEV1_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
2296 | #define BIF_CFG_DEV1_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
2297 | #define BIF_CFG_DEV1_RC_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
2298 | //BIF_CFG_DEV1_RC_LINK_CNTL2 |
2299 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
2300 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
2301 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
2302 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
2303 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
2304 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
2305 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
2306 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
2307 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
2308 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
2309 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
2310 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
2311 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
2312 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
2313 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
2314 | #define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
2315 | //BIF_CFG_DEV1_RC_LINK_STATUS2 |
2316 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
2317 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
2318 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
2319 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
2320 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
2321 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
2322 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
2323 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
2324 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
2325 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
2326 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
2327 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
2328 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
2329 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
2330 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
2331 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
2332 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
2333 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
2334 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
2335 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
2336 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
2337 | #define BIF_CFG_DEV1_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
2338 | //BIF_CFG_DEV1_RC_SLOT_CAP2 |
2339 | #define BIF_CFG_DEV1_RC_SLOT_CAP2__RESERVED__SHIFT 0x0 |
2340 | #define BIF_CFG_DEV1_RC_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
2341 | //BIF_CFG_DEV1_RC_SLOT_CNTL2 |
2342 | #define BIF_CFG_DEV1_RC_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
2343 | #define BIF_CFG_DEV1_RC_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
2344 | //BIF_CFG_DEV1_RC_SLOT_STATUS2 |
2345 | #define BIF_CFG_DEV1_RC_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
2346 | #define BIF_CFG_DEV1_RC_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
2347 | //BIF_CFG_DEV1_RC_MSI_CAP_LIST |
2348 | #define BIF_CFG_DEV1_RC_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
2349 | #define BIF_CFG_DEV1_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
2350 | #define BIF_CFG_DEV1_RC_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
2351 | #define BIF_CFG_DEV1_RC_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
2352 | //BIF_CFG_DEV1_RC_MSI_MSG_CNTL |
2353 | #define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
2354 | #define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
2355 | #define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
2356 | #define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
2357 | #define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
2358 | #define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
2359 | #define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
2360 | #define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
2361 | #define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
2362 | #define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
2363 | #define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
2364 | #define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
2365 | #define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
2366 | #define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
2367 | //BIF_CFG_DEV1_RC_MSI_MSG_ADDR_LO |
2368 | #define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
2369 | #define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
2370 | //BIF_CFG_DEV1_RC_MSI_MSG_ADDR_HI |
2371 | #define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
2372 | #define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
2373 | //BIF_CFG_DEV1_RC_MSI_MSG_DATA |
2374 | #define BIF_CFG_DEV1_RC_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
2375 | #define BIF_CFG_DEV1_RC_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
2376 | //BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA |
2377 | #define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
2378 | #define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
2379 | //BIF_CFG_DEV1_RC_MSI_MSG_DATA_64 |
2380 | #define BIF_CFG_DEV1_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
2381 | #define BIF_CFG_DEV1_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
2382 | //BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA_64 |
2383 | #define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
2384 | #define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
2385 | //BIF_CFG_DEV1_RC_SSID_CAP_LIST |
2386 | #define BIF_CFG_DEV1_RC_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
2387 | #define BIF_CFG_DEV1_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
2388 | #define BIF_CFG_DEV1_RC_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
2389 | #define BIF_CFG_DEV1_RC_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
2390 | //BIF_CFG_DEV1_RC_SSID_CAP |
2391 | #define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
2392 | #define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
2393 | #define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
2394 | #define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
2395 | //BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST |
2396 | #define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
2397 | #define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
2398 | #define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
2399 | #define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
2400 | //BIF_CFG_DEV1_RC_MSI_MAP_CAP |
2401 | #define BIF_CFG_DEV1_RC_MSI_MAP_CAP__EN__SHIFT 0x0 |
2402 | #define BIF_CFG_DEV1_RC_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
2403 | #define BIF_CFG_DEV1_RC_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
2404 | #define BIF_CFG_DEV1_RC_MSI_MAP_CAP__EN_MASK 0x0001L |
2405 | #define BIF_CFG_DEV1_RC_MSI_MAP_CAP__FIXD_MASK 0x0002L |
2406 | #define BIF_CFG_DEV1_RC_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
2407 | //BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
2408 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
2409 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
2410 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
2411 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
2412 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
2413 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
2414 | //BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR |
2415 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
2416 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
2417 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
2418 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
2419 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
2420 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
2421 | //BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC1 |
2422 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
2423 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
2424 | //BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC2 |
2425 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
2426 | #define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
2427 | //BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST |
2428 | #define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
2429 | #define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
2430 | #define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
2431 | #define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
2432 | #define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
2433 | #define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
2434 | //BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1 |
2435 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
2436 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
2437 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
2438 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
2439 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
2440 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
2441 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
2442 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
2443 | //BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2 |
2444 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
2445 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
2446 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
2447 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
2448 | //BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL |
2449 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
2450 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
2451 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
2452 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
2453 | //BIF_CFG_DEV1_RC_PCIE_PORT_VC_STATUS |
2454 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
2455 | #define BIF_CFG_DEV1_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
2456 | //BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP |
2457 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
2458 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
2459 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
2460 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
2461 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
2462 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
2463 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
2464 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
2465 | //BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL |
2466 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
2467 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
2468 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
2469 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
2470 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
2471 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
2472 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
2473 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
2474 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
2475 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
2476 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
2477 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
2478 | //BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS |
2479 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
2480 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
2481 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
2482 | #define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
2483 | //BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP |
2484 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
2485 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
2486 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
2487 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
2488 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
2489 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
2490 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
2491 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
2492 | //BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL |
2493 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
2494 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
2495 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
2496 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
2497 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
2498 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
2499 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
2500 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
2501 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
2502 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
2503 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
2504 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
2505 | //BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS |
2506 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
2507 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
2508 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
2509 | #define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
2510 | //BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
2511 | #define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
2512 | #define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
2513 | #define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
2514 | #define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
2515 | #define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
2516 | #define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
2517 | //BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW1 |
2518 | #define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
2519 | #define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
2520 | //BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW2 |
2521 | #define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
2522 | #define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
2523 | //BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
2524 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
2525 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
2526 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
2527 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
2528 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
2529 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
2530 | //BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS |
2531 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
2532 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
2533 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
2534 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
2535 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
2536 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
2537 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
2538 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
2539 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
2540 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
2541 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
2542 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
2543 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
2544 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
2545 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
2546 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
2547 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
2548 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
2549 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
2550 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
2551 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
2552 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
2553 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
2554 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
2555 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
2556 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
2557 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
2558 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
2559 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
2560 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
2561 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
2562 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
2563 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
2564 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
2565 | //BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK |
2566 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
2567 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
2568 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
2569 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
2570 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
2571 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
2572 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
2573 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
2574 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
2575 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
2576 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
2577 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
2578 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
2579 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
2580 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
2581 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
2582 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
2583 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
2584 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
2585 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
2586 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
2587 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
2588 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
2589 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
2590 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
2591 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
2592 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
2593 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
2594 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
2595 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
2596 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
2597 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
2598 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
2599 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
2600 | //BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY |
2601 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
2602 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
2603 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
2604 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
2605 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
2606 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
2607 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
2608 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
2609 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
2610 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
2611 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
2612 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
2613 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
2614 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
2615 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
2616 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
2617 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
2618 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
2619 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
2620 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
2621 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
2622 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
2623 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
2624 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
2625 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
2626 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
2627 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
2628 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
2629 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
2630 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
2631 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
2632 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
2633 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
2634 | #define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
2635 | //BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS |
2636 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
2637 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
2638 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
2639 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
2640 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
2641 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
2642 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
2643 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
2644 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
2645 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
2646 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
2647 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
2648 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
2649 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
2650 | //BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK |
2651 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
2652 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
2653 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
2654 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
2655 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
2656 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
2657 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
2658 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
2659 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
2660 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
2661 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
2662 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
2663 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
2664 | #define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
2665 | //BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL |
2666 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
2667 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
2668 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
2669 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
2670 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
2671 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
2672 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
2673 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
2674 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
2675 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
2676 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
2677 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
2678 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
2679 | #define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
2680 | //BIF_CFG_DEV1_RC_PCIE_HDR_LOG0 |
2681 | #define BIF_CFG_DEV1_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
2682 | #define BIF_CFG_DEV1_RC_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
2683 | //BIF_CFG_DEV1_RC_PCIE_HDR_LOG1 |
2684 | #define BIF_CFG_DEV1_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
2685 | #define BIF_CFG_DEV1_RC_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
2686 | //BIF_CFG_DEV1_RC_PCIE_HDR_LOG2 |
2687 | #define BIF_CFG_DEV1_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
2688 | #define BIF_CFG_DEV1_RC_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
2689 | //BIF_CFG_DEV1_RC_PCIE_HDR_LOG3 |
2690 | #define BIF_CFG_DEV1_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
2691 | #define BIF_CFG_DEV1_RC_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
2692 | //BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD |
2693 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
2694 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
2695 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
2696 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
2697 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
2698 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
2699 | //BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS |
2700 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
2701 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
2702 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
2703 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
2704 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
2705 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
2706 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
2707 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
2708 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
2709 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
2710 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
2711 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
2712 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
2713 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
2714 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
2715 | #define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
2716 | //BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID |
2717 | #define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
2718 | #define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
2719 | #define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
2720 | #define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
2721 | //BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG0 |
2722 | #define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
2723 | #define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
2724 | //BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG1 |
2725 | #define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
2726 | #define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
2727 | //BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG2 |
2728 | #define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
2729 | #define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
2730 | //BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG3 |
2731 | #define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
2732 | #define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
2733 | //BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST |
2734 | #define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
2735 | #define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
2736 | #define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
2737 | #define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
2738 | #define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
2739 | #define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
2740 | //BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3 |
2741 | #define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
2742 | #define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
2743 | #define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
2744 | #define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
2745 | #define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
2746 | #define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
2747 | //BIF_CFG_DEV1_RC_PCIE_LANE_ERROR_STATUS |
2748 | #define BIF_CFG_DEV1_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
2749 | #define BIF_CFG_DEV1_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
2750 | //BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL |
2751 | #define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2752 | #define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2753 | #define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2754 | #define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2755 | #define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2756 | #define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2757 | #define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2758 | #define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2759 | //BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL |
2760 | #define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2761 | #define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2762 | #define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2763 | #define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2764 | #define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2765 | #define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2766 | #define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2767 | #define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2768 | //BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL |
2769 | #define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2770 | #define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2771 | #define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2772 | #define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2773 | #define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2774 | #define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2775 | #define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2776 | #define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2777 | //BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL |
2778 | #define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2779 | #define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2780 | #define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2781 | #define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2782 | #define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2783 | #define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2784 | #define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2785 | #define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2786 | //BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL |
2787 | #define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2788 | #define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2789 | #define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2790 | #define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2791 | #define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2792 | #define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2793 | #define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2794 | #define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2795 | //BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL |
2796 | #define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2797 | #define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2798 | #define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2799 | #define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2800 | #define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2801 | #define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2802 | #define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2803 | #define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2804 | //BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL |
2805 | #define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2806 | #define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2807 | #define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2808 | #define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2809 | #define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2810 | #define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2811 | #define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2812 | #define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2813 | //BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL |
2814 | #define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2815 | #define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2816 | #define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2817 | #define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2818 | #define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2819 | #define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2820 | #define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2821 | #define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2822 | //BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL |
2823 | #define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2824 | #define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2825 | #define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2826 | #define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2827 | #define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2828 | #define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2829 | #define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2830 | #define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2831 | //BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL |
2832 | #define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2833 | #define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2834 | #define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2835 | #define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2836 | #define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2837 | #define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2838 | #define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2839 | #define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2840 | //BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL |
2841 | #define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2842 | #define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2843 | #define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2844 | #define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2845 | #define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2846 | #define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2847 | #define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2848 | #define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2849 | //BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL |
2850 | #define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2851 | #define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2852 | #define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2853 | #define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2854 | #define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2855 | #define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2856 | #define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2857 | #define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2858 | //BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL |
2859 | #define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2860 | #define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2861 | #define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2862 | #define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2863 | #define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2864 | #define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2865 | #define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2866 | #define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2867 | //BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL |
2868 | #define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2869 | #define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2870 | #define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2871 | #define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2872 | #define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2873 | #define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2874 | #define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2875 | #define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2876 | //BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL |
2877 | #define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2878 | #define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2879 | #define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2880 | #define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2881 | #define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2882 | #define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2883 | #define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2884 | #define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2885 | //BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL |
2886 | #define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
2887 | #define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
2888 | #define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
2889 | #define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
2890 | #define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
2891 | #define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
2892 | #define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
2893 | #define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
2894 | //BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST |
2895 | #define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
2896 | #define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
2897 | #define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
2898 | #define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
2899 | #define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
2900 | #define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
2901 | //BIF_CFG_DEV1_RC_PCIE_ACS_CAP |
2902 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
2903 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
2904 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
2905 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
2906 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
2907 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
2908 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
2909 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
2910 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
2911 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
2912 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
2913 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
2914 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
2915 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
2916 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
2917 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
2918 | //BIF_CFG_DEV1_RC_PCIE_ACS_CNTL |
2919 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
2920 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
2921 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
2922 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
2923 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
2924 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
2925 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
2926 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
2927 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
2928 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
2929 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
2930 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
2931 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
2932 | #define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
2933 | //BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST |
2934 | #define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
2935 | #define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
2936 | #define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
2937 | #define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
2938 | #define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
2939 | #define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
2940 | //BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP |
2941 | #define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
2942 | #define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
2943 | #define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
2944 | #define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
2945 | //BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS |
2946 | #define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
2947 | #define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
2948 | #define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
2949 | #define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
2950 | //BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST |
2951 | #define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
2952 | #define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
2953 | #define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
2954 | #define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
2955 | #define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
2956 | #define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
2957 | //BIF_CFG_DEV1_RC_LINK_CAP_16GT |
2958 | #define BIF_CFG_DEV1_RC_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
2959 | #define BIF_CFG_DEV1_RC_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
2960 | //BIF_CFG_DEV1_RC_LINK_CNTL_16GT |
2961 | #define BIF_CFG_DEV1_RC_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
2962 | #define BIF_CFG_DEV1_RC_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
2963 | //BIF_CFG_DEV1_RC_LINK_STATUS_16GT |
2964 | #define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
2965 | #define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
2966 | #define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
2967 | #define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
2968 | #define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
2969 | #define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
2970 | #define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
2971 | #define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
2972 | #define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
2973 | #define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
2974 | //BIF_CFG_DEV1_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT |
2975 | #define BIF_CFG_DEV1_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
2976 | #define BIF_CFG_DEV1_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
2977 | //BIF_CFG_DEV1_RC_RTM1_PARITY_MISMATCH_STATUS_16GT |
2978 | #define BIF_CFG_DEV1_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
2979 | #define BIF_CFG_DEV1_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
2980 | //BIF_CFG_DEV1_RC_RTM2_PARITY_MISMATCH_STATUS_16GT |
2981 | #define BIF_CFG_DEV1_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
2982 | #define BIF_CFG_DEV1_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
2983 | //BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT |
2984 | #define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
2985 | #define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
2986 | #define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
2987 | #define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
2988 | //BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT |
2989 | #define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
2990 | #define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
2991 | #define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
2992 | #define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
2993 | //BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT |
2994 | #define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
2995 | #define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
2996 | #define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
2997 | #define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
2998 | //BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT |
2999 | #define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
3000 | #define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
3001 | #define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
3002 | #define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
3003 | //BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT |
3004 | #define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
3005 | #define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
3006 | #define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
3007 | #define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
3008 | //BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT |
3009 | #define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
3010 | #define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
3011 | #define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
3012 | #define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
3013 | //BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT |
3014 | #define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
3015 | #define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
3016 | #define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
3017 | #define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
3018 | //BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT |
3019 | #define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
3020 | #define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
3021 | #define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
3022 | #define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
3023 | //BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT |
3024 | #define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
3025 | #define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
3026 | #define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
3027 | #define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
3028 | //BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT |
3029 | #define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
3030 | #define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
3031 | #define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
3032 | #define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
3033 | //BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT |
3034 | #define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
3035 | #define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
3036 | #define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
3037 | #define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
3038 | //BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT |
3039 | #define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
3040 | #define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
3041 | #define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
3042 | #define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
3043 | //BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT |
3044 | #define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
3045 | #define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
3046 | #define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
3047 | #define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
3048 | //BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT |
3049 | #define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
3050 | #define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
3051 | #define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
3052 | #define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
3053 | //BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT |
3054 | #define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
3055 | #define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
3056 | #define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
3057 | #define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
3058 | //BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT |
3059 | #define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
3060 | #define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
3061 | #define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
3062 | #define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
3063 | //BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST |
3064 | #define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
3065 | #define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
3066 | #define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
3067 | #define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
3068 | #define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
3069 | #define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
3070 | //BIF_CFG_DEV1_RC_MARGINING_PORT_CAP |
3071 | #define BIF_CFG_DEV1_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
3072 | #define BIF_CFG_DEV1_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
3073 | //BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS |
3074 | #define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
3075 | #define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
3076 | #define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
3077 | #define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
3078 | //BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL |
3079 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
3080 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
3081 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
3082 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
3083 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
3084 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
3085 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
3086 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
3087 | //BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS |
3088 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3089 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3090 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
3091 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3092 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3093 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
3094 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
3095 | #define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3096 | //BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL |
3097 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
3098 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
3099 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
3100 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
3101 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
3102 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
3103 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
3104 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
3105 | //BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS |
3106 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3107 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3108 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
3109 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3110 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3111 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
3112 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
3113 | #define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3114 | //BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL |
3115 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
3116 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
3117 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
3118 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
3119 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
3120 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
3121 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
3122 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
3123 | //BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS |
3124 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3125 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3126 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
3127 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3128 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3129 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
3130 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
3131 | #define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3132 | //BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL |
3133 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
3134 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
3135 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
3136 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
3137 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
3138 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
3139 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
3140 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
3141 | //BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS |
3142 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3143 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3144 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
3145 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3146 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3147 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
3148 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
3149 | #define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3150 | //BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL |
3151 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
3152 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
3153 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
3154 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
3155 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
3156 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
3157 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
3158 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
3159 | //BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS |
3160 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3161 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3162 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
3163 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3164 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3165 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
3166 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
3167 | #define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3168 | //BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL |
3169 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
3170 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
3171 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
3172 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
3173 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
3174 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
3175 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
3176 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
3177 | //BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS |
3178 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3179 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3180 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
3181 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3182 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3183 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
3184 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
3185 | #define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3186 | //BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL |
3187 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
3188 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
3189 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
3190 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
3191 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
3192 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
3193 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
3194 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
3195 | //BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS |
3196 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3197 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3198 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
3199 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3200 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3201 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
3202 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
3203 | #define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3204 | //BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL |
3205 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
3206 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
3207 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
3208 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
3209 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
3210 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
3211 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
3212 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
3213 | //BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS |
3214 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3215 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3216 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
3217 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3218 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3219 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
3220 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
3221 | #define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3222 | //BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL |
3223 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
3224 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
3225 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
3226 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
3227 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
3228 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
3229 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
3230 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
3231 | //BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS |
3232 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3233 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3234 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
3235 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3236 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3237 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
3238 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
3239 | #define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3240 | //BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL |
3241 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
3242 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
3243 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
3244 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
3245 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
3246 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
3247 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
3248 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
3249 | //BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS |
3250 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3251 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3252 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
3253 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3254 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3255 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
3256 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
3257 | #define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3258 | //BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL |
3259 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
3260 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
3261 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
3262 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
3263 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
3264 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
3265 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
3266 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
3267 | //BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS |
3268 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3269 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3270 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
3271 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3272 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3273 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
3274 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
3275 | #define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3276 | //BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL |
3277 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
3278 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
3279 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
3280 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
3281 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
3282 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
3283 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
3284 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
3285 | //BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS |
3286 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3287 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3288 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
3289 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3290 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3291 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
3292 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
3293 | #define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3294 | //BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL |
3295 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
3296 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
3297 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
3298 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
3299 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
3300 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
3301 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
3302 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
3303 | //BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS |
3304 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3305 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3306 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
3307 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3308 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3309 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
3310 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
3311 | #define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3312 | //BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL |
3313 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
3314 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
3315 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
3316 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
3317 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
3318 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
3319 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
3320 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
3321 | //BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS |
3322 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3323 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3324 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
3325 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3326 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3327 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
3328 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
3329 | #define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3330 | //BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL |
3331 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
3332 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
3333 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
3334 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
3335 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
3336 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
3337 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
3338 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
3339 | //BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS |
3340 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3341 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3342 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
3343 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3344 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3345 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
3346 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
3347 | #define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3348 | //BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL |
3349 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
3350 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
3351 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
3352 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
3353 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
3354 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
3355 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
3356 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
3357 | //BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS |
3358 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
3359 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
3360 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
3361 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
3362 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
3363 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
3364 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
3365 | #define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
3366 | //BIF_CFG_DEV1_RC_PCIE_RTR_ENH_CAP_LIST |
3367 | #define BIF_CFG_DEV1_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
3368 | #define BIF_CFG_DEV1_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
3369 | #define BIF_CFG_DEV1_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
3370 | #define BIF_CFG_DEV1_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
3371 | #define BIF_CFG_DEV1_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
3372 | #define BIF_CFG_DEV1_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
3373 | //BIF_CFG_DEV1_RC_RTR_DATA1 |
3374 | #define BIF_CFG_DEV1_RC_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
3375 | #define BIF_CFG_DEV1_RC_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
3376 | #define BIF_CFG_DEV1_RC_RTR_DATA1__VALID__SHIFT 0x1f |
3377 | #define BIF_CFG_DEV1_RC_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
3378 | #define BIF_CFG_DEV1_RC_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
3379 | #define BIF_CFG_DEV1_RC_RTR_DATA1__VALID_MASK 0x80000000L |
3380 | //BIF_CFG_DEV1_RC_RTR_DATA2 |
3381 | #define BIF_CFG_DEV1_RC_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
3382 | #define BIF_CFG_DEV1_RC_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
3383 | #define BIF_CFG_DEV1_RC_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
3384 | #define BIF_CFG_DEV1_RC_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
3385 | |
3386 | |
3387 | // addressBlock: nbio_nbif0_bif_cfg_dev2_rc_bifcfgdecp |
3388 | //BIF_CFG_DEV2_RC_VENDOR_ID |
3389 | #define BIF_CFG_DEV2_RC_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
3390 | #define BIF_CFG_DEV2_RC_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
3391 | //BIF_CFG_DEV2_RC_DEVICE_ID |
3392 | #define BIF_CFG_DEV2_RC_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
3393 | #define BIF_CFG_DEV2_RC_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
3394 | //BIF_CFG_DEV2_RC_COMMAND |
3395 | #define BIF_CFG_DEV2_RC_COMMAND__IOEN_DN__SHIFT 0x0 |
3396 | #define BIF_CFG_DEV2_RC_COMMAND__MEMEN_DN__SHIFT 0x1 |
3397 | #define BIF_CFG_DEV2_RC_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
3398 | #define BIF_CFG_DEV2_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
3399 | #define BIF_CFG_DEV2_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
3400 | #define BIF_CFG_DEV2_RC_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
3401 | #define BIF_CFG_DEV2_RC_COMMAND__AD_STEPPING__SHIFT 0x7 |
3402 | #define BIF_CFG_DEV2_RC_COMMAND__SERR_EN__SHIFT 0x8 |
3403 | #define BIF_CFG_DEV2_RC_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
3404 | #define BIF_CFG_DEV2_RC_COMMAND__INT_DIS__SHIFT 0xa |
3405 | #define BIF_CFG_DEV2_RC_COMMAND__IOEN_DN_MASK 0x0001L |
3406 | #define BIF_CFG_DEV2_RC_COMMAND__MEMEN_DN_MASK 0x0002L |
3407 | #define BIF_CFG_DEV2_RC_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
3408 | #define BIF_CFG_DEV2_RC_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
3409 | #define BIF_CFG_DEV2_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
3410 | #define BIF_CFG_DEV2_RC_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
3411 | #define BIF_CFG_DEV2_RC_COMMAND__AD_STEPPING_MASK 0x0080L |
3412 | #define BIF_CFG_DEV2_RC_COMMAND__SERR_EN_MASK 0x0100L |
3413 | #define BIF_CFG_DEV2_RC_COMMAND__FAST_B2B_EN_MASK 0x0200L |
3414 | #define BIF_CFG_DEV2_RC_COMMAND__INT_DIS_MASK 0x0400L |
3415 | //BIF_CFG_DEV2_RC_STATUS |
3416 | #define BIF_CFG_DEV2_RC_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
3417 | #define BIF_CFG_DEV2_RC_STATUS__INT_STATUS__SHIFT 0x3 |
3418 | #define BIF_CFG_DEV2_RC_STATUS__CAP_LIST__SHIFT 0x4 |
3419 | #define BIF_CFG_DEV2_RC_STATUS__PCI_66_CAP__SHIFT 0x5 |
3420 | #define BIF_CFG_DEV2_RC_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
3421 | #define BIF_CFG_DEV2_RC_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
3422 | #define BIF_CFG_DEV2_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
3423 | #define BIF_CFG_DEV2_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
3424 | #define BIF_CFG_DEV2_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
3425 | #define BIF_CFG_DEV2_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
3426 | #define BIF_CFG_DEV2_RC_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
3427 | #define BIF_CFG_DEV2_RC_STATUS__INT_STATUS_MASK 0x0008L |
3428 | #define BIF_CFG_DEV2_RC_STATUS__CAP_LIST_MASK 0x0010L |
3429 | #define BIF_CFG_DEV2_RC_STATUS__PCI_66_CAP_MASK 0x0020L |
3430 | #define BIF_CFG_DEV2_RC_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
3431 | #define BIF_CFG_DEV2_RC_STATUS__DEVSEL_TIMING_MASK 0x0600L |
3432 | #define BIF_CFG_DEV2_RC_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
3433 | #define BIF_CFG_DEV2_RC_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
3434 | #define BIF_CFG_DEV2_RC_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
3435 | #define BIF_CFG_DEV2_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
3436 | //BIF_CFG_DEV2_RC_REVISION_ID |
3437 | #define BIF_CFG_DEV2_RC_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
3438 | #define BIF_CFG_DEV2_RC_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
3439 | #define BIF_CFG_DEV2_RC_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
3440 | #define BIF_CFG_DEV2_RC_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
3441 | //BIF_CFG_DEV2_RC_PROG_INTERFACE |
3442 | #define BIF_CFG_DEV2_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
3443 | #define BIF_CFG_DEV2_RC_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
3444 | //BIF_CFG_DEV2_RC_SUB_CLASS |
3445 | #define BIF_CFG_DEV2_RC_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
3446 | #define BIF_CFG_DEV2_RC_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
3447 | //BIF_CFG_DEV2_RC_BASE_CLASS |
3448 | #define BIF_CFG_DEV2_RC_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
3449 | #define BIF_CFG_DEV2_RC_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
3450 | //BIF_CFG_DEV2_RC_CACHE_LINE |
3451 | #define BIF_CFG_DEV2_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
3452 | #define BIF_CFG_DEV2_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
3453 | //BIF_CFG_DEV2_RC_LATENCY |
3454 | #define BIF_CFG_DEV2_RC_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
3455 | #define BIF_CFG_DEV2_RC_LATENCY__LATENCY_TIMER_MASK 0xFFL |
3456 | //BIF_CFG_DEV2_RC_HEADER |
3457 | #define 0x0 |
3458 | #define 0x7 |
3459 | #define 0x7FL |
3460 | #define 0x80L |
3461 | //BIF_CFG_DEV2_RC_BIST |
3462 | #define BIF_CFG_DEV2_RC_BIST__BIST_COMP__SHIFT 0x0 |
3463 | #define BIF_CFG_DEV2_RC_BIST__BIST_STRT__SHIFT 0x6 |
3464 | #define BIF_CFG_DEV2_RC_BIST__BIST_CAP__SHIFT 0x7 |
3465 | #define BIF_CFG_DEV2_RC_BIST__BIST_COMP_MASK 0x0FL |
3466 | #define BIF_CFG_DEV2_RC_BIST__BIST_STRT_MASK 0x40L |
3467 | #define BIF_CFG_DEV2_RC_BIST__BIST_CAP_MASK 0x80L |
3468 | //BIF_CFG_DEV2_RC_BASE_ADDR_1 |
3469 | #define BIF_CFG_DEV2_RC_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
3470 | #define BIF_CFG_DEV2_RC_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
3471 | //BIF_CFG_DEV2_RC_BASE_ADDR_2 |
3472 | #define BIF_CFG_DEV2_RC_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
3473 | #define BIF_CFG_DEV2_RC_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
3474 | //BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY |
3475 | #define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
3476 | #define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
3477 | #define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
3478 | #define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
3479 | #define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
3480 | #define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
3481 | #define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
3482 | #define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
3483 | //BIF_CFG_DEV2_RC_IO_BASE_LIMIT |
3484 | #define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
3485 | #define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
3486 | #define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
3487 | #define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
3488 | #define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
3489 | #define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
3490 | #define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
3491 | #define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
3492 | //BIF_CFG_DEV2_RC_SECONDARY_STATUS |
3493 | #define BIF_CFG_DEV2_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 |
3494 | #define BIF_CFG_DEV2_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
3495 | #define BIF_CFG_DEV2_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
3496 | #define BIF_CFG_DEV2_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
3497 | #define BIF_CFG_DEV2_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
3498 | #define BIF_CFG_DEV2_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
3499 | #define BIF_CFG_DEV2_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
3500 | #define BIF_CFG_DEV2_RC_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L |
3501 | #define BIF_CFG_DEV2_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
3502 | #define BIF_CFG_DEV2_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
3503 | #define BIF_CFG_DEV2_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
3504 | #define BIF_CFG_DEV2_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
3505 | #define BIF_CFG_DEV2_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
3506 | #define BIF_CFG_DEV2_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
3507 | //BIF_CFG_DEV2_RC_MEM_BASE_LIMIT |
3508 | #define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
3509 | #define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
3510 | #define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
3511 | #define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
3512 | #define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
3513 | #define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
3514 | #define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
3515 | #define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
3516 | //BIF_CFG_DEV2_RC_PREF_BASE_LIMIT |
3517 | #define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
3518 | #define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
3519 | #define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
3520 | #define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
3521 | #define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
3522 | #define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
3523 | #define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
3524 | #define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
3525 | //BIF_CFG_DEV2_RC_PREF_BASE_UPPER |
3526 | #define BIF_CFG_DEV2_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
3527 | #define BIF_CFG_DEV2_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
3528 | //BIF_CFG_DEV2_RC_PREF_LIMIT_UPPER |
3529 | #define BIF_CFG_DEV2_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
3530 | #define BIF_CFG_DEV2_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
3531 | //BIF_CFG_DEV2_RC_IO_BASE_LIMIT_HI |
3532 | #define BIF_CFG_DEV2_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
3533 | #define BIF_CFG_DEV2_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
3534 | #define BIF_CFG_DEV2_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
3535 | #define BIF_CFG_DEV2_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
3536 | //BIF_CFG_DEV2_RC_CAP_PTR |
3537 | #define BIF_CFG_DEV2_RC_CAP_PTR__CAP_PTR__SHIFT 0x0 |
3538 | #define BIF_CFG_DEV2_RC_CAP_PTR__CAP_PTR_MASK 0xFFL |
3539 | //BIF_CFG_DEV2_RC_ROM_BASE_ADDR |
3540 | #define BIF_CFG_DEV2_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
3541 | #define BIF_CFG_DEV2_RC_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
3542 | //BIF_CFG_DEV2_RC_INTERRUPT_LINE |
3543 | #define BIF_CFG_DEV2_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
3544 | #define BIF_CFG_DEV2_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
3545 | //BIF_CFG_DEV2_RC_INTERRUPT_PIN |
3546 | #define BIF_CFG_DEV2_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
3547 | #define BIF_CFG_DEV2_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
3548 | //BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL |
3549 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
3550 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
3551 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
3552 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
3553 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
3554 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
3555 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
3556 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
3557 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 |
3558 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 |
3559 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa |
3560 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb |
3561 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
3562 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
3563 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
3564 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
3565 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
3566 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
3567 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
3568 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
3569 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L |
3570 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L |
3571 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L |
3572 | #define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L |
3573 | //BIF_CFG_DEV2_RC_EXT_BRIDGE_CNTL |
3574 | #define BIF_CFG_DEV2_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
3575 | #define BIF_CFG_DEV2_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
3576 | //BIF_CFG_DEV2_RC_PMI_CAP_LIST |
3577 | #define BIF_CFG_DEV2_RC_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
3578 | #define BIF_CFG_DEV2_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
3579 | #define BIF_CFG_DEV2_RC_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
3580 | #define BIF_CFG_DEV2_RC_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
3581 | //BIF_CFG_DEV2_RC_PMI_CAP |
3582 | #define BIF_CFG_DEV2_RC_PMI_CAP__VERSION__SHIFT 0x0 |
3583 | #define BIF_CFG_DEV2_RC_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
3584 | #define BIF_CFG_DEV2_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
3585 | #define BIF_CFG_DEV2_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
3586 | #define BIF_CFG_DEV2_RC_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
3587 | #define BIF_CFG_DEV2_RC_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
3588 | #define BIF_CFG_DEV2_RC_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
3589 | #define BIF_CFG_DEV2_RC_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
3590 | #define BIF_CFG_DEV2_RC_PMI_CAP__VERSION_MASK 0x0007L |
3591 | #define BIF_CFG_DEV2_RC_PMI_CAP__PME_CLOCK_MASK 0x0008L |
3592 | #define BIF_CFG_DEV2_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
3593 | #define BIF_CFG_DEV2_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
3594 | #define BIF_CFG_DEV2_RC_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
3595 | #define BIF_CFG_DEV2_RC_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
3596 | #define BIF_CFG_DEV2_RC_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
3597 | #define BIF_CFG_DEV2_RC_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
3598 | //BIF_CFG_DEV2_RC_PMI_STATUS_CNTL |
3599 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
3600 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
3601 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
3602 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
3603 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
3604 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
3605 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
3606 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
3607 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
3608 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
3609 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
3610 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
3611 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
3612 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
3613 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
3614 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
3615 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
3616 | #define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
3617 | //BIF_CFG_DEV2_RC_PCIE_CAP_LIST |
3618 | #define BIF_CFG_DEV2_RC_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
3619 | #define BIF_CFG_DEV2_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
3620 | #define BIF_CFG_DEV2_RC_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
3621 | #define BIF_CFG_DEV2_RC_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
3622 | //BIF_CFG_DEV2_RC_PCIE_CAP |
3623 | #define BIF_CFG_DEV2_RC_PCIE_CAP__VERSION__SHIFT 0x0 |
3624 | #define BIF_CFG_DEV2_RC_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
3625 | #define BIF_CFG_DEV2_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
3626 | #define BIF_CFG_DEV2_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
3627 | #define BIF_CFG_DEV2_RC_PCIE_CAP__VERSION_MASK 0x000FL |
3628 | #define BIF_CFG_DEV2_RC_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
3629 | #define BIF_CFG_DEV2_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
3630 | #define BIF_CFG_DEV2_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
3631 | //BIF_CFG_DEV2_RC_DEVICE_CAP |
3632 | #define BIF_CFG_DEV2_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
3633 | #define BIF_CFG_DEV2_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
3634 | #define BIF_CFG_DEV2_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
3635 | #define BIF_CFG_DEV2_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
3636 | #define BIF_CFG_DEV2_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
3637 | #define BIF_CFG_DEV2_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
3638 | #define BIF_CFG_DEV2_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
3639 | #define BIF_CFG_DEV2_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
3640 | #define BIF_CFG_DEV2_RC_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
3641 | #define BIF_CFG_DEV2_RC_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
3642 | #define BIF_CFG_DEV2_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
3643 | #define BIF_CFG_DEV2_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
3644 | #define BIF_CFG_DEV2_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
3645 | #define BIF_CFG_DEV2_RC_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
3646 | //BIF_CFG_DEV2_RC_DEVICE_CNTL |
3647 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
3648 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
3649 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
3650 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
3651 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
3652 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
3653 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
3654 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
3655 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
3656 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
3657 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
3658 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
3659 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
3660 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
3661 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
3662 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
3663 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
3664 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
3665 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
3666 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
3667 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
3668 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
3669 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
3670 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
3671 | //BIF_CFG_DEV2_RC_DEVICE_STATUS |
3672 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
3673 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
3674 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
3675 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
3676 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
3677 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
3678 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
3679 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
3680 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
3681 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
3682 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
3683 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
3684 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
3685 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
3686 | //BIF_CFG_DEV2_RC_LINK_CAP |
3687 | #define BIF_CFG_DEV2_RC_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
3688 | #define BIF_CFG_DEV2_RC_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
3689 | #define BIF_CFG_DEV2_RC_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
3690 | #define BIF_CFG_DEV2_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
3691 | #define BIF_CFG_DEV2_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
3692 | #define BIF_CFG_DEV2_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
3693 | #define BIF_CFG_DEV2_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
3694 | #define BIF_CFG_DEV2_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
3695 | #define BIF_CFG_DEV2_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
3696 | #define BIF_CFG_DEV2_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
3697 | #define BIF_CFG_DEV2_RC_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
3698 | #define BIF_CFG_DEV2_RC_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
3699 | #define BIF_CFG_DEV2_RC_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
3700 | #define BIF_CFG_DEV2_RC_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
3701 | #define BIF_CFG_DEV2_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
3702 | #define BIF_CFG_DEV2_RC_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
3703 | #define BIF_CFG_DEV2_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
3704 | #define BIF_CFG_DEV2_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
3705 | #define BIF_CFG_DEV2_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
3706 | #define BIF_CFG_DEV2_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
3707 | #define BIF_CFG_DEV2_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
3708 | #define BIF_CFG_DEV2_RC_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
3709 | //BIF_CFG_DEV2_RC_LINK_CNTL |
3710 | #define BIF_CFG_DEV2_RC_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
3711 | #define BIF_CFG_DEV2_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
3712 | #define BIF_CFG_DEV2_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
3713 | #define BIF_CFG_DEV2_RC_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
3714 | #define BIF_CFG_DEV2_RC_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
3715 | #define BIF_CFG_DEV2_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
3716 | #define BIF_CFG_DEV2_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
3717 | #define BIF_CFG_DEV2_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
3718 | #define BIF_CFG_DEV2_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
3719 | #define BIF_CFG_DEV2_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
3720 | #define BIF_CFG_DEV2_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
3721 | #define BIF_CFG_DEV2_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
3722 | #define BIF_CFG_DEV2_RC_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
3723 | #define BIF_CFG_DEV2_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
3724 | #define BIF_CFG_DEV2_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
3725 | #define BIF_CFG_DEV2_RC_LINK_CNTL__LINK_DIS_MASK 0x0010L |
3726 | #define BIF_CFG_DEV2_RC_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
3727 | #define BIF_CFG_DEV2_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
3728 | #define BIF_CFG_DEV2_RC_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
3729 | #define BIF_CFG_DEV2_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
3730 | #define BIF_CFG_DEV2_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
3731 | #define BIF_CFG_DEV2_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
3732 | #define BIF_CFG_DEV2_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
3733 | #define BIF_CFG_DEV2_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
3734 | //BIF_CFG_DEV2_RC_LINK_STATUS |
3735 | #define BIF_CFG_DEV2_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
3736 | #define BIF_CFG_DEV2_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
3737 | #define BIF_CFG_DEV2_RC_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
3738 | #define BIF_CFG_DEV2_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
3739 | #define BIF_CFG_DEV2_RC_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
3740 | #define BIF_CFG_DEV2_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
3741 | #define BIF_CFG_DEV2_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
3742 | #define BIF_CFG_DEV2_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
3743 | #define BIF_CFG_DEV2_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
3744 | #define BIF_CFG_DEV2_RC_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
3745 | #define BIF_CFG_DEV2_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
3746 | #define BIF_CFG_DEV2_RC_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
3747 | #define BIF_CFG_DEV2_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
3748 | #define BIF_CFG_DEV2_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
3749 | //BIF_CFG_DEV2_RC_SLOT_CAP |
3750 | #define BIF_CFG_DEV2_RC_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
3751 | #define BIF_CFG_DEV2_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
3752 | #define BIF_CFG_DEV2_RC_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
3753 | #define BIF_CFG_DEV2_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
3754 | #define BIF_CFG_DEV2_RC_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
3755 | #define BIF_CFG_DEV2_RC_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
3756 | #define BIF_CFG_DEV2_RC_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
3757 | #define BIF_CFG_DEV2_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
3758 | #define BIF_CFG_DEV2_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
3759 | #define BIF_CFG_DEV2_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
3760 | #define BIF_CFG_DEV2_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
3761 | #define BIF_CFG_DEV2_RC_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
3762 | #define BIF_CFG_DEV2_RC_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
3763 | #define BIF_CFG_DEV2_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
3764 | #define BIF_CFG_DEV2_RC_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
3765 | #define BIF_CFG_DEV2_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
3766 | #define BIF_CFG_DEV2_RC_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
3767 | #define BIF_CFG_DEV2_RC_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
3768 | #define BIF_CFG_DEV2_RC_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
3769 | #define BIF_CFG_DEV2_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
3770 | #define BIF_CFG_DEV2_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
3771 | #define BIF_CFG_DEV2_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
3772 | #define BIF_CFG_DEV2_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
3773 | #define BIF_CFG_DEV2_RC_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
3774 | //BIF_CFG_DEV2_RC_SLOT_CNTL |
3775 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
3776 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
3777 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
3778 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
3779 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
3780 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
3781 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
3782 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
3783 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
3784 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
3785 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
3786 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
3787 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
3788 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
3789 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
3790 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
3791 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
3792 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
3793 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
3794 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
3795 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
3796 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
3797 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
3798 | #define BIF_CFG_DEV2_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
3799 | //BIF_CFG_DEV2_RC_SLOT_STATUS |
3800 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
3801 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
3802 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
3803 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
3804 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
3805 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
3806 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
3807 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
3808 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
3809 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
3810 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
3811 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
3812 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
3813 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
3814 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
3815 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
3816 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
3817 | #define BIF_CFG_DEV2_RC_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
3818 | //BIF_CFG_DEV2_RC_ROOT_CNTL |
3819 | #define BIF_CFG_DEV2_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
3820 | #define BIF_CFG_DEV2_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
3821 | #define BIF_CFG_DEV2_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
3822 | #define BIF_CFG_DEV2_RC_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
3823 | #define BIF_CFG_DEV2_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
3824 | #define BIF_CFG_DEV2_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
3825 | #define BIF_CFG_DEV2_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
3826 | #define BIF_CFG_DEV2_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
3827 | #define BIF_CFG_DEV2_RC_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
3828 | #define BIF_CFG_DEV2_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
3829 | //BIF_CFG_DEV2_RC_ROOT_CAP |
3830 | #define BIF_CFG_DEV2_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
3831 | #define BIF_CFG_DEV2_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
3832 | //BIF_CFG_DEV2_RC_ROOT_STATUS |
3833 | #define BIF_CFG_DEV2_RC_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
3834 | #define BIF_CFG_DEV2_RC_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
3835 | #define BIF_CFG_DEV2_RC_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
3836 | #define BIF_CFG_DEV2_RC_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
3837 | #define BIF_CFG_DEV2_RC_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
3838 | #define BIF_CFG_DEV2_RC_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
3839 | //BIF_CFG_DEV2_RC_DEVICE_CAP2 |
3840 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
3841 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
3842 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
3843 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
3844 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
3845 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
3846 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
3847 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
3848 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
3849 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
3850 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
3851 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
3852 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
3853 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
3854 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
3855 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
3856 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
3857 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
3858 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
3859 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
3860 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
3861 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
3862 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
3863 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
3864 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
3865 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
3866 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
3867 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
3868 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
3869 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
3870 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
3871 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
3872 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
3873 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
3874 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
3875 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
3876 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
3877 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
3878 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
3879 | #define BIF_CFG_DEV2_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
3880 | //BIF_CFG_DEV2_RC_DEVICE_CNTL2 |
3881 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
3882 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
3883 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
3884 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
3885 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
3886 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
3887 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
3888 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
3889 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
3890 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
3891 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
3892 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
3893 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
3894 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
3895 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
3896 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
3897 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
3898 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
3899 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
3900 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
3901 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
3902 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
3903 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
3904 | #define BIF_CFG_DEV2_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
3905 | //BIF_CFG_DEV2_RC_DEVICE_STATUS2 |
3906 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
3907 | #define BIF_CFG_DEV2_RC_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
3908 | //BIF_CFG_DEV2_RC_LINK_CAP2 |
3909 | #define BIF_CFG_DEV2_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
3910 | #define BIF_CFG_DEV2_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
3911 | #define BIF_CFG_DEV2_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
3912 | #define BIF_CFG_DEV2_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
3913 | #define BIF_CFG_DEV2_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
3914 | #define BIF_CFG_DEV2_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
3915 | #define BIF_CFG_DEV2_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
3916 | #define BIF_CFG_DEV2_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
3917 | #define BIF_CFG_DEV2_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
3918 | #define BIF_CFG_DEV2_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
3919 | #define BIF_CFG_DEV2_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
3920 | #define BIF_CFG_DEV2_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
3921 | #define BIF_CFG_DEV2_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
3922 | #define BIF_CFG_DEV2_RC_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
3923 | //BIF_CFG_DEV2_RC_LINK_CNTL2 |
3924 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
3925 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
3926 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
3927 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
3928 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
3929 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
3930 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
3931 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
3932 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
3933 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
3934 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
3935 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
3936 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
3937 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
3938 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
3939 | #define BIF_CFG_DEV2_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
3940 | //BIF_CFG_DEV2_RC_LINK_STATUS2 |
3941 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
3942 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
3943 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
3944 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
3945 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
3946 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
3947 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
3948 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
3949 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
3950 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
3951 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
3952 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
3953 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
3954 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
3955 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
3956 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
3957 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
3958 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
3959 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
3960 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
3961 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
3962 | #define BIF_CFG_DEV2_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
3963 | //BIF_CFG_DEV2_RC_SLOT_CAP2 |
3964 | #define BIF_CFG_DEV2_RC_SLOT_CAP2__RESERVED__SHIFT 0x0 |
3965 | #define BIF_CFG_DEV2_RC_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
3966 | //BIF_CFG_DEV2_RC_SLOT_CNTL2 |
3967 | #define BIF_CFG_DEV2_RC_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
3968 | #define BIF_CFG_DEV2_RC_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
3969 | //BIF_CFG_DEV2_RC_SLOT_STATUS2 |
3970 | #define BIF_CFG_DEV2_RC_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
3971 | #define BIF_CFG_DEV2_RC_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
3972 | //BIF_CFG_DEV2_RC_MSI_CAP_LIST |
3973 | #define BIF_CFG_DEV2_RC_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
3974 | #define BIF_CFG_DEV2_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
3975 | #define BIF_CFG_DEV2_RC_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
3976 | #define BIF_CFG_DEV2_RC_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
3977 | //BIF_CFG_DEV2_RC_MSI_MSG_CNTL |
3978 | #define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
3979 | #define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
3980 | #define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
3981 | #define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
3982 | #define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
3983 | #define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
3984 | #define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
3985 | #define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
3986 | #define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
3987 | #define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
3988 | #define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
3989 | #define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
3990 | #define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
3991 | #define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
3992 | //BIF_CFG_DEV2_RC_MSI_MSG_ADDR_LO |
3993 | #define BIF_CFG_DEV2_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
3994 | #define BIF_CFG_DEV2_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
3995 | //BIF_CFG_DEV2_RC_MSI_MSG_ADDR_HI |
3996 | #define BIF_CFG_DEV2_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
3997 | #define BIF_CFG_DEV2_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
3998 | //BIF_CFG_DEV2_RC_MSI_MSG_DATA |
3999 | #define BIF_CFG_DEV2_RC_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
4000 | #define BIF_CFG_DEV2_RC_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
4001 | //BIF_CFG_DEV2_RC_MSI_EXT_MSG_DATA |
4002 | #define BIF_CFG_DEV2_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
4003 | #define BIF_CFG_DEV2_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
4004 | //BIF_CFG_DEV2_RC_MSI_MSG_DATA_64 |
4005 | #define BIF_CFG_DEV2_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
4006 | #define BIF_CFG_DEV2_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
4007 | //BIF_CFG_DEV2_RC_MSI_EXT_MSG_DATA_64 |
4008 | #define BIF_CFG_DEV2_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
4009 | #define BIF_CFG_DEV2_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
4010 | //BIF_CFG_DEV2_RC_SSID_CAP_LIST |
4011 | #define BIF_CFG_DEV2_RC_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
4012 | #define BIF_CFG_DEV2_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
4013 | #define BIF_CFG_DEV2_RC_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
4014 | #define BIF_CFG_DEV2_RC_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
4015 | //BIF_CFG_DEV2_RC_SSID_CAP |
4016 | #define BIF_CFG_DEV2_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
4017 | #define BIF_CFG_DEV2_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
4018 | #define BIF_CFG_DEV2_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
4019 | #define BIF_CFG_DEV2_RC_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
4020 | //BIF_CFG_DEV2_RC_MSI_MAP_CAP_LIST |
4021 | #define BIF_CFG_DEV2_RC_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
4022 | #define BIF_CFG_DEV2_RC_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
4023 | #define BIF_CFG_DEV2_RC_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
4024 | #define BIF_CFG_DEV2_RC_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
4025 | //BIF_CFG_DEV2_RC_MSI_MAP_CAP |
4026 | #define BIF_CFG_DEV2_RC_MSI_MAP_CAP__EN__SHIFT 0x0 |
4027 | #define BIF_CFG_DEV2_RC_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
4028 | #define BIF_CFG_DEV2_RC_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
4029 | #define BIF_CFG_DEV2_RC_MSI_MAP_CAP__EN_MASK 0x0001L |
4030 | #define BIF_CFG_DEV2_RC_MSI_MAP_CAP__FIXD_MASK 0x0002L |
4031 | #define BIF_CFG_DEV2_RC_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
4032 | //BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
4033 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4034 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4035 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4036 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4037 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4038 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4039 | //BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_HDR |
4040 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
4041 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
4042 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
4043 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
4044 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
4045 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
4046 | //BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC1 |
4047 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
4048 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
4049 | //BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC2 |
4050 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
4051 | #define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
4052 | //BIF_CFG_DEV2_RC_PCIE_VC_ENH_CAP_LIST |
4053 | #define BIF_CFG_DEV2_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4054 | #define BIF_CFG_DEV2_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4055 | #define BIF_CFG_DEV2_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4056 | #define BIF_CFG_DEV2_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4057 | #define BIF_CFG_DEV2_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4058 | #define BIF_CFG_DEV2_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4059 | //BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1 |
4060 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
4061 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
4062 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
4063 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
4064 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
4065 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
4066 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
4067 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
4068 | //BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG2 |
4069 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
4070 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
4071 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
4072 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
4073 | //BIF_CFG_DEV2_RC_PCIE_PORT_VC_CNTL |
4074 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
4075 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
4076 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
4077 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
4078 | //BIF_CFG_DEV2_RC_PCIE_PORT_VC_STATUS |
4079 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
4080 | #define BIF_CFG_DEV2_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
4081 | //BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP |
4082 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
4083 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
4084 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
4085 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
4086 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
4087 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
4088 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
4089 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
4090 | //BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL |
4091 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
4092 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
4093 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
4094 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
4095 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
4096 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
4097 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
4098 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
4099 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
4100 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
4101 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
4102 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
4103 | //BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_STATUS |
4104 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
4105 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
4106 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
4107 | #define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
4108 | //BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP |
4109 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
4110 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
4111 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
4112 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
4113 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
4114 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
4115 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
4116 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
4117 | //BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL |
4118 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
4119 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
4120 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
4121 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
4122 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
4123 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
4124 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
4125 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
4126 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
4127 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
4128 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
4129 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
4130 | //BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_STATUS |
4131 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
4132 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
4133 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
4134 | #define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
4135 | //BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
4136 | #define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4137 | #define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4138 | #define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4139 | #define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4140 | #define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4141 | #define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4142 | //BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_DW1 |
4143 | #define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
4144 | #define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
4145 | //BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_DW2 |
4146 | #define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
4147 | #define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
4148 | //BIF_CFG_DEV2_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
4149 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4150 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4151 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4152 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4153 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4154 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4155 | //BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS |
4156 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
4157 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
4158 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
4159 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
4160 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
4161 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
4162 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
4163 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
4164 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
4165 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
4166 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
4167 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
4168 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
4169 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
4170 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
4171 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
4172 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
4173 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
4174 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
4175 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
4176 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
4177 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
4178 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
4179 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
4180 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
4181 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
4182 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
4183 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
4184 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
4185 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
4186 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
4187 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
4188 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
4189 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
4190 | //BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK |
4191 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
4192 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
4193 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
4194 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
4195 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
4196 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
4197 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
4198 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
4199 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
4200 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
4201 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
4202 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
4203 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
4204 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
4205 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
4206 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
4207 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
4208 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
4209 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
4210 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
4211 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
4212 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
4213 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
4214 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
4215 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
4216 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
4217 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
4218 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
4219 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
4220 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
4221 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
4222 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
4223 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
4224 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
4225 | //BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY |
4226 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
4227 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
4228 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
4229 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
4230 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
4231 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
4232 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
4233 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
4234 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
4235 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
4236 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
4237 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
4238 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
4239 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
4240 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
4241 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
4242 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
4243 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
4244 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
4245 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
4246 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
4247 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
4248 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
4249 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
4250 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
4251 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
4252 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
4253 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
4254 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
4255 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
4256 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
4257 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
4258 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
4259 | #define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
4260 | //BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS |
4261 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
4262 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
4263 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
4264 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
4265 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
4266 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
4267 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
4268 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
4269 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
4270 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
4271 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
4272 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
4273 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
4274 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
4275 | //BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK |
4276 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
4277 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
4278 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
4279 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
4280 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
4281 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
4282 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
4283 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
4284 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
4285 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
4286 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
4287 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
4288 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
4289 | #define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
4290 | //BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL |
4291 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
4292 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
4293 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
4294 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
4295 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
4296 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
4297 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
4298 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
4299 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
4300 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
4301 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
4302 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
4303 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
4304 | #define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
4305 | //BIF_CFG_DEV2_RC_PCIE_HDR_LOG0 |
4306 | #define BIF_CFG_DEV2_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
4307 | #define BIF_CFG_DEV2_RC_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
4308 | //BIF_CFG_DEV2_RC_PCIE_HDR_LOG1 |
4309 | #define BIF_CFG_DEV2_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
4310 | #define BIF_CFG_DEV2_RC_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
4311 | //BIF_CFG_DEV2_RC_PCIE_HDR_LOG2 |
4312 | #define BIF_CFG_DEV2_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
4313 | #define BIF_CFG_DEV2_RC_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
4314 | //BIF_CFG_DEV2_RC_PCIE_HDR_LOG3 |
4315 | #define BIF_CFG_DEV2_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
4316 | #define BIF_CFG_DEV2_RC_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
4317 | //BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_CMD |
4318 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
4319 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
4320 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
4321 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
4322 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
4323 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
4324 | //BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS |
4325 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
4326 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
4327 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
4328 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
4329 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
4330 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
4331 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
4332 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
4333 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
4334 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
4335 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
4336 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
4337 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
4338 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
4339 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
4340 | #define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
4341 | //BIF_CFG_DEV2_RC_PCIE_ERR_SRC_ID |
4342 | #define BIF_CFG_DEV2_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
4343 | #define BIF_CFG_DEV2_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
4344 | #define BIF_CFG_DEV2_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
4345 | #define BIF_CFG_DEV2_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
4346 | //BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG0 |
4347 | #define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
4348 | #define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
4349 | //BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG1 |
4350 | #define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
4351 | #define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
4352 | //BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG2 |
4353 | #define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
4354 | #define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
4355 | //BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG3 |
4356 | #define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
4357 | #define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
4358 | //BIF_CFG_DEV2_RC_PCIE_SECONDARY_ENH_CAP_LIST |
4359 | #define BIF_CFG_DEV2_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4360 | #define BIF_CFG_DEV2_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4361 | #define BIF_CFG_DEV2_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4362 | #define BIF_CFG_DEV2_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4363 | #define BIF_CFG_DEV2_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4364 | #define BIF_CFG_DEV2_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4365 | //BIF_CFG_DEV2_RC_PCIE_LINK_CNTL3 |
4366 | #define BIF_CFG_DEV2_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
4367 | #define BIF_CFG_DEV2_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
4368 | #define BIF_CFG_DEV2_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
4369 | #define BIF_CFG_DEV2_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
4370 | #define BIF_CFG_DEV2_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
4371 | #define BIF_CFG_DEV2_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
4372 | //BIF_CFG_DEV2_RC_PCIE_LANE_ERROR_STATUS |
4373 | #define BIF_CFG_DEV2_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
4374 | #define BIF_CFG_DEV2_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
4375 | //BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL |
4376 | #define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4377 | #define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4378 | #define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4379 | #define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4380 | #define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4381 | #define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4382 | #define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4383 | #define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4384 | //BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL |
4385 | #define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4386 | #define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4387 | #define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4388 | #define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4389 | #define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4390 | #define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4391 | #define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4392 | #define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4393 | //BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL |
4394 | #define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4395 | #define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4396 | #define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4397 | #define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4398 | #define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4399 | #define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4400 | #define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4401 | #define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4402 | //BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL |
4403 | #define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4404 | #define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4405 | #define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4406 | #define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4407 | #define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4408 | #define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4409 | #define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4410 | #define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4411 | //BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL |
4412 | #define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4413 | #define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4414 | #define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4415 | #define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4416 | #define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4417 | #define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4418 | #define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4419 | #define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4420 | //BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL |
4421 | #define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4422 | #define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4423 | #define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4424 | #define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4425 | #define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4426 | #define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4427 | #define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4428 | #define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4429 | //BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL |
4430 | #define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4431 | #define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4432 | #define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4433 | #define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4434 | #define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4435 | #define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4436 | #define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4437 | #define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4438 | //BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL |
4439 | #define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4440 | #define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4441 | #define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4442 | #define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4443 | #define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4444 | #define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4445 | #define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4446 | #define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4447 | //BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL |
4448 | #define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4449 | #define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4450 | #define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4451 | #define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4452 | #define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4453 | #define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4454 | #define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4455 | #define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4456 | //BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL |
4457 | #define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4458 | #define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4459 | #define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4460 | #define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4461 | #define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4462 | #define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4463 | #define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4464 | #define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4465 | //BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL |
4466 | #define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4467 | #define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4468 | #define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4469 | #define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4470 | #define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4471 | #define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4472 | #define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4473 | #define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4474 | //BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL |
4475 | #define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4476 | #define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4477 | #define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4478 | #define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4479 | #define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4480 | #define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4481 | #define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4482 | #define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4483 | //BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL |
4484 | #define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4485 | #define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4486 | #define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4487 | #define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4488 | #define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4489 | #define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4490 | #define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4491 | #define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4492 | //BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL |
4493 | #define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4494 | #define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4495 | #define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4496 | #define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4497 | #define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4498 | #define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4499 | #define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4500 | #define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4501 | //BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL |
4502 | #define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4503 | #define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4504 | #define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4505 | #define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4506 | #define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4507 | #define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4508 | #define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4509 | #define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4510 | //BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL |
4511 | #define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
4512 | #define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
4513 | #define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
4514 | #define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
4515 | #define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
4516 | #define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
4517 | #define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
4518 | #define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
4519 | //BIF_CFG_DEV2_RC_PCIE_ACS_ENH_CAP_LIST |
4520 | #define BIF_CFG_DEV2_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4521 | #define BIF_CFG_DEV2_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4522 | #define BIF_CFG_DEV2_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4523 | #define BIF_CFG_DEV2_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4524 | #define BIF_CFG_DEV2_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4525 | #define BIF_CFG_DEV2_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4526 | //BIF_CFG_DEV2_RC_PCIE_ACS_CAP |
4527 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
4528 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
4529 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
4530 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
4531 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
4532 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
4533 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
4534 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
4535 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
4536 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
4537 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
4538 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
4539 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
4540 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
4541 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
4542 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
4543 | //BIF_CFG_DEV2_RC_PCIE_ACS_CNTL |
4544 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
4545 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
4546 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
4547 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
4548 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
4549 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
4550 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
4551 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
4552 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
4553 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
4554 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
4555 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
4556 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
4557 | #define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
4558 | //BIF_CFG_DEV2_RC_PCIE_DLF_ENH_CAP_LIST |
4559 | #define BIF_CFG_DEV2_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4560 | #define BIF_CFG_DEV2_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4561 | #define BIF_CFG_DEV2_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4562 | #define BIF_CFG_DEV2_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4563 | #define BIF_CFG_DEV2_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4564 | #define BIF_CFG_DEV2_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4565 | //BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_CAP |
4566 | #define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
4567 | #define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
4568 | #define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
4569 | #define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
4570 | //BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_STATUS |
4571 | #define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
4572 | #define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
4573 | #define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
4574 | #define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
4575 | //BIF_CFG_DEV2_RC_PCIE_PHY_16GT_ENH_CAP_LIST |
4576 | #define BIF_CFG_DEV2_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4577 | #define BIF_CFG_DEV2_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4578 | #define BIF_CFG_DEV2_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4579 | #define BIF_CFG_DEV2_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4580 | #define BIF_CFG_DEV2_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4581 | #define BIF_CFG_DEV2_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4582 | //BIF_CFG_DEV2_RC_LINK_CAP_16GT |
4583 | #define BIF_CFG_DEV2_RC_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
4584 | #define BIF_CFG_DEV2_RC_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
4585 | //BIF_CFG_DEV2_RC_LINK_CNTL_16GT |
4586 | #define BIF_CFG_DEV2_RC_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
4587 | #define BIF_CFG_DEV2_RC_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
4588 | //BIF_CFG_DEV2_RC_LINK_STATUS_16GT |
4589 | #define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
4590 | #define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
4591 | #define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
4592 | #define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
4593 | #define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
4594 | #define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
4595 | #define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
4596 | #define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
4597 | #define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
4598 | #define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
4599 | //BIF_CFG_DEV2_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT |
4600 | #define BIF_CFG_DEV2_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
4601 | #define BIF_CFG_DEV2_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
4602 | //BIF_CFG_DEV2_RC_RTM1_PARITY_MISMATCH_STATUS_16GT |
4603 | #define BIF_CFG_DEV2_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
4604 | #define BIF_CFG_DEV2_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
4605 | //BIF_CFG_DEV2_RC_RTM2_PARITY_MISMATCH_STATUS_16GT |
4606 | #define BIF_CFG_DEV2_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
4607 | #define BIF_CFG_DEV2_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
4608 | //BIF_CFG_DEV2_RC_LANE_0_EQUALIZATION_CNTL_16GT |
4609 | #define BIF_CFG_DEV2_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4610 | #define BIF_CFG_DEV2_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
4611 | #define BIF_CFG_DEV2_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
4612 | #define BIF_CFG_DEV2_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
4613 | //BIF_CFG_DEV2_RC_LANE_1_EQUALIZATION_CNTL_16GT |
4614 | #define BIF_CFG_DEV2_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4615 | #define BIF_CFG_DEV2_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
4616 | #define BIF_CFG_DEV2_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
4617 | #define BIF_CFG_DEV2_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
4618 | //BIF_CFG_DEV2_RC_LANE_2_EQUALIZATION_CNTL_16GT |
4619 | #define BIF_CFG_DEV2_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4620 | #define BIF_CFG_DEV2_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
4621 | #define BIF_CFG_DEV2_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
4622 | #define BIF_CFG_DEV2_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
4623 | //BIF_CFG_DEV2_RC_LANE_3_EQUALIZATION_CNTL_16GT |
4624 | #define BIF_CFG_DEV2_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4625 | #define BIF_CFG_DEV2_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
4626 | #define BIF_CFG_DEV2_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
4627 | #define BIF_CFG_DEV2_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
4628 | //BIF_CFG_DEV2_RC_LANE_4_EQUALIZATION_CNTL_16GT |
4629 | #define BIF_CFG_DEV2_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4630 | #define BIF_CFG_DEV2_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
4631 | #define BIF_CFG_DEV2_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
4632 | #define BIF_CFG_DEV2_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
4633 | //BIF_CFG_DEV2_RC_LANE_5_EQUALIZATION_CNTL_16GT |
4634 | #define BIF_CFG_DEV2_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4635 | #define BIF_CFG_DEV2_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
4636 | #define BIF_CFG_DEV2_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
4637 | #define BIF_CFG_DEV2_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
4638 | //BIF_CFG_DEV2_RC_LANE_6_EQUALIZATION_CNTL_16GT |
4639 | #define BIF_CFG_DEV2_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4640 | #define BIF_CFG_DEV2_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
4641 | #define BIF_CFG_DEV2_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
4642 | #define BIF_CFG_DEV2_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
4643 | //BIF_CFG_DEV2_RC_LANE_7_EQUALIZATION_CNTL_16GT |
4644 | #define BIF_CFG_DEV2_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4645 | #define BIF_CFG_DEV2_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
4646 | #define BIF_CFG_DEV2_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
4647 | #define BIF_CFG_DEV2_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
4648 | //BIF_CFG_DEV2_RC_LANE_8_EQUALIZATION_CNTL_16GT |
4649 | #define BIF_CFG_DEV2_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4650 | #define BIF_CFG_DEV2_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
4651 | #define BIF_CFG_DEV2_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
4652 | #define BIF_CFG_DEV2_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
4653 | //BIF_CFG_DEV2_RC_LANE_9_EQUALIZATION_CNTL_16GT |
4654 | #define BIF_CFG_DEV2_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4655 | #define BIF_CFG_DEV2_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
4656 | #define BIF_CFG_DEV2_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
4657 | #define BIF_CFG_DEV2_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
4658 | //BIF_CFG_DEV2_RC_LANE_10_EQUALIZATION_CNTL_16GT |
4659 | #define BIF_CFG_DEV2_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4660 | #define BIF_CFG_DEV2_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
4661 | #define BIF_CFG_DEV2_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
4662 | #define BIF_CFG_DEV2_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
4663 | //BIF_CFG_DEV2_RC_LANE_11_EQUALIZATION_CNTL_16GT |
4664 | #define BIF_CFG_DEV2_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4665 | #define BIF_CFG_DEV2_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
4666 | #define BIF_CFG_DEV2_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
4667 | #define BIF_CFG_DEV2_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
4668 | //BIF_CFG_DEV2_RC_LANE_12_EQUALIZATION_CNTL_16GT |
4669 | #define BIF_CFG_DEV2_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4670 | #define BIF_CFG_DEV2_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
4671 | #define BIF_CFG_DEV2_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
4672 | #define BIF_CFG_DEV2_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
4673 | //BIF_CFG_DEV2_RC_LANE_13_EQUALIZATION_CNTL_16GT |
4674 | #define BIF_CFG_DEV2_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4675 | #define BIF_CFG_DEV2_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
4676 | #define BIF_CFG_DEV2_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
4677 | #define BIF_CFG_DEV2_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
4678 | //BIF_CFG_DEV2_RC_LANE_14_EQUALIZATION_CNTL_16GT |
4679 | #define BIF_CFG_DEV2_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4680 | #define BIF_CFG_DEV2_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
4681 | #define BIF_CFG_DEV2_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
4682 | #define BIF_CFG_DEV2_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
4683 | //BIF_CFG_DEV2_RC_LANE_15_EQUALIZATION_CNTL_16GT |
4684 | #define BIF_CFG_DEV2_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
4685 | #define BIF_CFG_DEV2_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
4686 | #define BIF_CFG_DEV2_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
4687 | #define BIF_CFG_DEV2_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
4688 | //BIF_CFG_DEV2_RC_PCIE_MARGINING_ENH_CAP_LIST |
4689 | #define BIF_CFG_DEV2_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4690 | #define BIF_CFG_DEV2_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4691 | #define BIF_CFG_DEV2_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4692 | #define BIF_CFG_DEV2_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4693 | #define BIF_CFG_DEV2_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4694 | #define BIF_CFG_DEV2_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4695 | //BIF_CFG_DEV2_RC_MARGINING_PORT_CAP |
4696 | #define BIF_CFG_DEV2_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
4697 | #define BIF_CFG_DEV2_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
4698 | //BIF_CFG_DEV2_RC_MARGINING_PORT_STATUS |
4699 | #define BIF_CFG_DEV2_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
4700 | #define BIF_CFG_DEV2_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
4701 | #define BIF_CFG_DEV2_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
4702 | #define BIF_CFG_DEV2_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
4703 | //BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL |
4704 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
4705 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
4706 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
4707 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
4708 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
4709 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
4710 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
4711 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
4712 | //BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS |
4713 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4714 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4715 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
4716 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4717 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4718 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
4719 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
4720 | #define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4721 | //BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL |
4722 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
4723 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
4724 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
4725 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
4726 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
4727 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
4728 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
4729 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
4730 | //BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS |
4731 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4732 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4733 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
4734 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4735 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4736 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
4737 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
4738 | #define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4739 | //BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL |
4740 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
4741 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
4742 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
4743 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
4744 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
4745 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
4746 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
4747 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
4748 | //BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS |
4749 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4750 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4751 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
4752 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4753 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4754 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
4755 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
4756 | #define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4757 | //BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL |
4758 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
4759 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
4760 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
4761 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
4762 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
4763 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
4764 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
4765 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
4766 | //BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS |
4767 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4768 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4769 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
4770 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4771 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4772 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
4773 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
4774 | #define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4775 | //BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL |
4776 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
4777 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
4778 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
4779 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
4780 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
4781 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
4782 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
4783 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
4784 | //BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS |
4785 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4786 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4787 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
4788 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4789 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4790 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
4791 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
4792 | #define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4793 | //BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL |
4794 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
4795 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
4796 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
4797 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
4798 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
4799 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
4800 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
4801 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
4802 | //BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS |
4803 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4804 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4805 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
4806 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4807 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4808 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
4809 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
4810 | #define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4811 | //BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL |
4812 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
4813 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
4814 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
4815 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
4816 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
4817 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
4818 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
4819 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
4820 | //BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS |
4821 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4822 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4823 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
4824 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4825 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4826 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
4827 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
4828 | #define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4829 | //BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL |
4830 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
4831 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
4832 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
4833 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
4834 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
4835 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
4836 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
4837 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
4838 | //BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS |
4839 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4840 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4841 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
4842 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4843 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4844 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
4845 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
4846 | #define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4847 | //BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL |
4848 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
4849 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
4850 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
4851 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
4852 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
4853 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
4854 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
4855 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
4856 | //BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS |
4857 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4858 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4859 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
4860 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4861 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4862 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
4863 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
4864 | #define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4865 | //BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL |
4866 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
4867 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
4868 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
4869 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
4870 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
4871 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
4872 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
4873 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
4874 | //BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS |
4875 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4876 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4877 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
4878 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4879 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4880 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
4881 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
4882 | #define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4883 | //BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL |
4884 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
4885 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
4886 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
4887 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
4888 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
4889 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
4890 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
4891 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
4892 | //BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS |
4893 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4894 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4895 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
4896 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4897 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4898 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
4899 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
4900 | #define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4901 | //BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL |
4902 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
4903 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
4904 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
4905 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
4906 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
4907 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
4908 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
4909 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
4910 | //BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS |
4911 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4912 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4913 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
4914 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4915 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4916 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
4917 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
4918 | #define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4919 | //BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL |
4920 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
4921 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
4922 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
4923 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
4924 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
4925 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
4926 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
4927 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
4928 | //BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS |
4929 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4930 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4931 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
4932 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4933 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4934 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
4935 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
4936 | #define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4937 | //BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL |
4938 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
4939 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
4940 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
4941 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
4942 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
4943 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
4944 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
4945 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
4946 | //BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS |
4947 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4948 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4949 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
4950 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4951 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4952 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
4953 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
4954 | #define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4955 | //BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL |
4956 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
4957 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
4958 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
4959 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
4960 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
4961 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
4962 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
4963 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
4964 | //BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS |
4965 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4966 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4967 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
4968 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4969 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4970 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
4971 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
4972 | #define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4973 | //BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL |
4974 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
4975 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
4976 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
4977 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
4978 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
4979 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
4980 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
4981 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
4982 | //BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS |
4983 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
4984 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
4985 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
4986 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
4987 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
4988 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
4989 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
4990 | #define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
4991 | //BIF_CFG_DEV2_RC_PCIE_RTR_ENH_CAP_LIST |
4992 | #define BIF_CFG_DEV2_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
4993 | #define BIF_CFG_DEV2_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
4994 | #define BIF_CFG_DEV2_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
4995 | #define BIF_CFG_DEV2_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
4996 | #define BIF_CFG_DEV2_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
4997 | #define BIF_CFG_DEV2_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
4998 | //BIF_CFG_DEV2_RC_RTR_DATA1 |
4999 | #define BIF_CFG_DEV2_RC_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
5000 | #define BIF_CFG_DEV2_RC_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
5001 | #define BIF_CFG_DEV2_RC_RTR_DATA1__VALID__SHIFT 0x1f |
5002 | #define BIF_CFG_DEV2_RC_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
5003 | #define BIF_CFG_DEV2_RC_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
5004 | #define BIF_CFG_DEV2_RC_RTR_DATA1__VALID_MASK 0x80000000L |
5005 | //BIF_CFG_DEV2_RC_RTR_DATA2 |
5006 | #define BIF_CFG_DEV2_RC_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
5007 | #define BIF_CFG_DEV2_RC_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
5008 | #define BIF_CFG_DEV2_RC_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
5009 | #define BIF_CFG_DEV2_RC_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
5010 | |
5011 | |
5012 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp |
5013 | //BIF_CFG_DEV0_EPF0_VENDOR_ID |
5014 | #define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
5015 | #define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
5016 | //BIF_CFG_DEV0_EPF0_DEVICE_ID |
5017 | #define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
5018 | #define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
5019 | //BIF_CFG_DEV0_EPF0_COMMAND |
5020 | #define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
5021 | #define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
5022 | #define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
5023 | #define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
5024 | #define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
5025 | #define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
5026 | #define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT 0x7 |
5027 | #define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT 0x8 |
5028 | #define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
5029 | #define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT 0xa |
5030 | #define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
5031 | #define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
5032 | #define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
5033 | #define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
5034 | #define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
5035 | #define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
5036 | #define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK 0x0080L |
5037 | #define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK 0x0100L |
5038 | #define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
5039 | #define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK 0x0400L |
5040 | //BIF_CFG_DEV0_EPF0_STATUS |
5041 | #define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
5042 | #define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT 0x3 |
5043 | #define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT 0x4 |
5044 | #define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT 0x5 |
5045 | #define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
5046 | #define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
5047 | #define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
5048 | #define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
5049 | #define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
5050 | #define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
5051 | #define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
5052 | #define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK 0x0008L |
5053 | #define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK 0x0010L |
5054 | #define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK 0x0020L |
5055 | #define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
5056 | #define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
5057 | #define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
5058 | #define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
5059 | #define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
5060 | #define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
5061 | //BIF_CFG_DEV0_EPF0_REVISION_ID |
5062 | #define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
5063 | #define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
5064 | #define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
5065 | #define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
5066 | //BIF_CFG_DEV0_EPF0_PROG_INTERFACE |
5067 | #define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
5068 | #define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
5069 | //BIF_CFG_DEV0_EPF0_SUB_CLASS |
5070 | #define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
5071 | #define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
5072 | //BIF_CFG_DEV0_EPF0_BASE_CLASS |
5073 | #define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
5074 | #define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
5075 | //BIF_CFG_DEV0_EPF0_CACHE_LINE |
5076 | #define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
5077 | #define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
5078 | //BIF_CFG_DEV0_EPF0_LATENCY |
5079 | #define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
5080 | #define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
5081 | //BIF_CFG_DEV0_EPF0_HEADER |
5082 | #define 0x0 |
5083 | #define 0x7 |
5084 | #define 0x7FL |
5085 | #define 0x80L |
5086 | //BIF_CFG_DEV0_EPF0_BIST |
5087 | #define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT 0x0 |
5088 | #define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT 0x6 |
5089 | #define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT 0x7 |
5090 | #define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK 0x0FL |
5091 | #define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK 0x40L |
5092 | #define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK 0x80L |
5093 | //BIF_CFG_DEV0_EPF0_BASE_ADDR_1 |
5094 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
5095 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
5096 | //BIF_CFG_DEV0_EPF0_BASE_ADDR_2 |
5097 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
5098 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
5099 | //BIF_CFG_DEV0_EPF0_BASE_ADDR_3 |
5100 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
5101 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
5102 | //BIF_CFG_DEV0_EPF0_BASE_ADDR_4 |
5103 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
5104 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
5105 | //BIF_CFG_DEV0_EPF0_BASE_ADDR_5 |
5106 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
5107 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
5108 | //BIF_CFG_DEV0_EPF0_BASE_ADDR_6 |
5109 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
5110 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
5111 | //BIF_CFG_DEV0_EPF0_ADAPTER_ID |
5112 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
5113 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
5114 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
5115 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
5116 | //BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR |
5117 | #define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
5118 | #define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
5119 | //BIF_CFG_DEV0_EPF0_CAP_PTR |
5120 | #define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
5121 | #define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK 0xFFL |
5122 | //BIF_CFG_DEV0_EPF0_INTERRUPT_LINE |
5123 | #define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
5124 | #define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
5125 | //BIF_CFG_DEV0_EPF0_INTERRUPT_PIN |
5126 | #define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
5127 | #define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
5128 | //BIF_CFG_DEV0_EPF0_MIN_GRANT |
5129 | #define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
5130 | #define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
5131 | //BIF_CFG_DEV0_EPF0_MAX_LATENCY |
5132 | #define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
5133 | #define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
5134 | //BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST |
5135 | #define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
5136 | #define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
5137 | #define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
5138 | #define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
5139 | #define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
5140 | #define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
5141 | //BIF_CFG_DEV0_EPF0_ADAPTER_ID_W |
5142 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
5143 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
5144 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
5145 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
5146 | //BIF_CFG_DEV0_EPF0_PMI_CAP_LIST |
5147 | #define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
5148 | #define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
5149 | #define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
5150 | #define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
5151 | //BIF_CFG_DEV0_EPF0_PMI_CAP |
5152 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT 0x0 |
5153 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
5154 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
5155 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
5156 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
5157 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
5158 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
5159 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
5160 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK 0x0007L |
5161 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
5162 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
5163 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
5164 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
5165 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
5166 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
5167 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
5168 | //BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL |
5169 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
5170 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
5171 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
5172 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
5173 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
5174 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
5175 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
5176 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
5177 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
5178 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
5179 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
5180 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
5181 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
5182 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
5183 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
5184 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
5185 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
5186 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
5187 | //BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST |
5188 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
5189 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
5190 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
5191 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
5192 | //BIF_CFG_DEV0_EPF0_PCIE_CAP |
5193 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT 0x0 |
5194 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
5195 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
5196 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
5197 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK 0x000FL |
5198 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
5199 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
5200 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
5201 | //BIF_CFG_DEV0_EPF0_DEVICE_CAP |
5202 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
5203 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
5204 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
5205 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
5206 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
5207 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
5208 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
5209 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
5210 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
5211 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
5212 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
5213 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
5214 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
5215 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
5216 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
5217 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
5218 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
5219 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
5220 | //BIF_CFG_DEV0_EPF0_DEVICE_CNTL |
5221 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
5222 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
5223 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
5224 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
5225 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
5226 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
5227 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
5228 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
5229 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
5230 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
5231 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
5232 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
5233 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
5234 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
5235 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
5236 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
5237 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
5238 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
5239 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
5240 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
5241 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
5242 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
5243 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
5244 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
5245 | //BIF_CFG_DEV0_EPF0_DEVICE_STATUS |
5246 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
5247 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
5248 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
5249 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
5250 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
5251 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
5252 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
5253 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
5254 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
5255 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
5256 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
5257 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
5258 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
5259 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
5260 | //BIF_CFG_DEV0_EPF0_LINK_CAP |
5261 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
5262 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
5263 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
5264 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
5265 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
5266 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
5267 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
5268 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
5269 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
5270 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
5271 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
5272 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
5273 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
5274 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
5275 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
5276 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
5277 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
5278 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
5279 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
5280 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
5281 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
5282 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
5283 | //BIF_CFG_DEV0_EPF0_LINK_CNTL |
5284 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
5285 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
5286 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
5287 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
5288 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
5289 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
5290 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
5291 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
5292 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
5293 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
5294 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
5295 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
5296 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
5297 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
5298 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
5299 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
5300 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
5301 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
5302 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
5303 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
5304 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
5305 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
5306 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
5307 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
5308 | //BIF_CFG_DEV0_EPF0_LINK_STATUS |
5309 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
5310 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
5311 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
5312 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
5313 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
5314 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
5315 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
5316 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
5317 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
5318 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
5319 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
5320 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
5321 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
5322 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
5323 | //BIF_CFG_DEV0_EPF0_DEVICE_CAP2 |
5324 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
5325 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
5326 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
5327 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
5328 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
5329 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
5330 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
5331 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
5332 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
5333 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
5334 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
5335 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
5336 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
5337 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
5338 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
5339 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
5340 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
5341 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
5342 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
5343 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
5344 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
5345 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
5346 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
5347 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
5348 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
5349 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
5350 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
5351 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
5352 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
5353 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
5354 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
5355 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
5356 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
5357 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
5358 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
5359 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
5360 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
5361 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
5362 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
5363 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
5364 | //BIF_CFG_DEV0_EPF0_DEVICE_CNTL2 |
5365 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
5366 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
5367 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
5368 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
5369 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
5370 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
5371 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
5372 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
5373 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
5374 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
5375 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
5376 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
5377 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
5378 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
5379 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
5380 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
5381 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
5382 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
5383 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
5384 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
5385 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
5386 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
5387 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
5388 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
5389 | //BIF_CFG_DEV0_EPF0_DEVICE_STATUS2 |
5390 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
5391 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
5392 | //BIF_CFG_DEV0_EPF0_LINK_CAP2 |
5393 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
5394 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
5395 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
5396 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
5397 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
5398 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
5399 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
5400 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
5401 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
5402 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
5403 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
5404 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
5405 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
5406 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
5407 | //BIF_CFG_DEV0_EPF0_LINK_CNTL2 |
5408 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
5409 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
5410 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
5411 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
5412 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
5413 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
5414 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
5415 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
5416 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
5417 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
5418 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
5419 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
5420 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
5421 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
5422 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
5423 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
5424 | //BIF_CFG_DEV0_EPF0_LINK_STATUS2 |
5425 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
5426 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
5427 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
5428 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
5429 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
5430 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
5431 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
5432 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
5433 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
5434 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
5435 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
5436 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
5437 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
5438 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
5439 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
5440 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
5441 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
5442 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
5443 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
5444 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
5445 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
5446 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
5447 | //BIF_CFG_DEV0_EPF0_MSI_CAP_LIST |
5448 | #define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
5449 | #define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
5450 | #define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
5451 | #define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
5452 | //BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL |
5453 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
5454 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
5455 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
5456 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
5457 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
5458 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
5459 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
5460 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
5461 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
5462 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
5463 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
5464 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
5465 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
5466 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
5467 | //BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO |
5468 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
5469 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
5470 | //BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI |
5471 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
5472 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
5473 | //BIF_CFG_DEV0_EPF0_MSI_MSG_DATA |
5474 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
5475 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
5476 | //BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA |
5477 | #define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
5478 | #define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
5479 | //BIF_CFG_DEV0_EPF0_MSI_MASK |
5480 | #define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
5481 | #define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
5482 | //BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 |
5483 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
5484 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
5485 | //BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 |
5486 | #define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
5487 | #define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
5488 | //BIF_CFG_DEV0_EPF0_MSI_MASK_64 |
5489 | #define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
5490 | #define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
5491 | //BIF_CFG_DEV0_EPF0_MSI_PENDING |
5492 | #define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
5493 | #define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
5494 | //BIF_CFG_DEV0_EPF0_MSI_PENDING_64 |
5495 | #define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
5496 | #define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
5497 | //BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST |
5498 | #define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
5499 | #define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
5500 | #define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
5501 | #define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
5502 | //BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL |
5503 | #define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
5504 | #define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
5505 | #define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
5506 | #define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
5507 | #define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
5508 | #define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
5509 | //BIF_CFG_DEV0_EPF0_MSIX_TABLE |
5510 | #define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
5511 | #define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
5512 | #define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
5513 | #define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
5514 | //BIF_CFG_DEV0_EPF0_MSIX_PBA |
5515 | #define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
5516 | #define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
5517 | #define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
5518 | #define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
5519 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
5520 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5521 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5522 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5523 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5524 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5525 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5526 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR |
5527 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
5528 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
5529 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
5530 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
5531 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
5532 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
5533 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 |
5534 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
5535 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
5536 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 |
5537 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
5538 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
5539 | //BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST |
5540 | #define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5541 | #define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5542 | #define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5543 | #define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5544 | #define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5545 | #define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5546 | //BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 |
5547 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
5548 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
5549 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
5550 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
5551 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
5552 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
5553 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
5554 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
5555 | //BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 |
5556 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
5557 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
5558 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
5559 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
5560 | //BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL |
5561 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
5562 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
5563 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
5564 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
5565 | //BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS |
5566 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
5567 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
5568 | //BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP |
5569 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
5570 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
5571 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
5572 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
5573 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
5574 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
5575 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
5576 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
5577 | //BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL |
5578 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
5579 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
5580 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
5581 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
5582 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
5583 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
5584 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
5585 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
5586 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
5587 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
5588 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
5589 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
5590 | //BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS |
5591 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
5592 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
5593 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
5594 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
5595 | //BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP |
5596 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
5597 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
5598 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
5599 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
5600 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
5601 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
5602 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
5603 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
5604 | //BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL |
5605 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
5606 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
5607 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
5608 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
5609 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
5610 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
5611 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
5612 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
5613 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
5614 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
5615 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
5616 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
5617 | //BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS |
5618 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
5619 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
5620 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
5621 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
5622 | //BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
5623 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5624 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5625 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5626 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5627 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5628 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5629 | //BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 |
5630 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
5631 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
5632 | //BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 |
5633 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
5634 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
5635 | //BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
5636 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5637 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5638 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5639 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5640 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5641 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5642 | //BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS |
5643 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
5644 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
5645 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
5646 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
5647 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
5648 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
5649 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
5650 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
5651 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
5652 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
5653 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
5654 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
5655 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
5656 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
5657 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
5658 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
5659 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
5660 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
5661 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
5662 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
5663 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
5664 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
5665 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
5666 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
5667 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
5668 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
5669 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
5670 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
5671 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
5672 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
5673 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
5674 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
5675 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
5676 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
5677 | //BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK |
5678 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
5679 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
5680 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
5681 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
5682 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
5683 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
5684 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
5685 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
5686 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
5687 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
5688 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
5689 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
5690 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
5691 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
5692 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
5693 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
5694 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
5695 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
5696 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
5697 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
5698 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
5699 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
5700 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
5701 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
5702 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
5703 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
5704 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
5705 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
5706 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
5707 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
5708 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
5709 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
5710 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
5711 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
5712 | //BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY |
5713 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
5714 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
5715 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
5716 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
5717 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
5718 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
5719 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
5720 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
5721 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
5722 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
5723 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
5724 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
5725 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
5726 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
5727 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
5728 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
5729 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
5730 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
5731 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
5732 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
5733 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
5734 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
5735 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
5736 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
5737 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
5738 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
5739 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
5740 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
5741 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
5742 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
5743 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
5744 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
5745 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
5746 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
5747 | //BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS |
5748 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
5749 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
5750 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
5751 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
5752 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
5753 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
5754 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
5755 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
5756 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
5757 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
5758 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
5759 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
5760 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
5761 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
5762 | //BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK |
5763 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
5764 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
5765 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
5766 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
5767 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
5768 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
5769 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
5770 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
5771 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
5772 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
5773 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
5774 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
5775 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
5776 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
5777 | //BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL |
5778 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
5779 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
5780 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
5781 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
5782 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
5783 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
5784 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
5785 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
5786 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
5787 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
5788 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
5789 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
5790 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
5791 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
5792 | //BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 |
5793 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
5794 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
5795 | //BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 |
5796 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
5797 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
5798 | //BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 |
5799 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
5800 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
5801 | //BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 |
5802 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
5803 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
5804 | //BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 |
5805 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
5806 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
5807 | //BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 |
5808 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
5809 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
5810 | //BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 |
5811 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
5812 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
5813 | //BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 |
5814 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
5815 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
5816 | //BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST |
5817 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5818 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5819 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5820 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5821 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5822 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5823 | //BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP |
5824 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
5825 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
5826 | //BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL |
5827 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
5828 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
5829 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
5830 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
5831 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
5832 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
5833 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
5834 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
5835 | //BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP |
5836 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
5837 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
5838 | //BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL |
5839 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
5840 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
5841 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
5842 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
5843 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
5844 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
5845 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
5846 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
5847 | //BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP |
5848 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
5849 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
5850 | //BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL |
5851 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
5852 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
5853 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
5854 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
5855 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
5856 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
5857 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
5858 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
5859 | //BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP |
5860 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
5861 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
5862 | //BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL |
5863 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
5864 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
5865 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
5866 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
5867 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
5868 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
5869 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
5870 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
5871 | //BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP |
5872 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
5873 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
5874 | //BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL |
5875 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
5876 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
5877 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
5878 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
5879 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
5880 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
5881 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
5882 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
5883 | //BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP |
5884 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
5885 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
5886 | //BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL |
5887 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
5888 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
5889 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
5890 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
5891 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
5892 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
5893 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
5894 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
5895 | //BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
5896 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5897 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5898 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5899 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5900 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5901 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5902 | //BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT |
5903 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
5904 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
5905 | //BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA |
5906 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
5907 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
5908 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
5909 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
5910 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
5911 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
5912 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
5913 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
5914 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
5915 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
5916 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
5917 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
5918 | //BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP |
5919 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
5920 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
5921 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST |
5922 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5923 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5924 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5925 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5926 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5927 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5928 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP |
5929 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
5930 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
5931 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
5932 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
5933 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
5934 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
5935 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
5936 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
5937 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
5938 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
5939 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR |
5940 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
5941 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
5942 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS |
5943 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
5944 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
5945 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
5946 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
5947 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL |
5948 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
5949 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
5950 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
5951 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5952 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5953 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
5954 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5955 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5956 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
5957 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5958 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5959 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
5960 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5961 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5962 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
5963 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5964 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5965 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
5966 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5967 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5968 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
5969 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5970 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5971 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
5972 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
5973 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
5974 | //BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST |
5975 | #define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
5976 | #define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
5977 | #define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
5978 | #define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
5979 | #define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
5980 | #define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
5981 | //BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 |
5982 | #define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
5983 | #define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
5984 | #define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
5985 | #define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
5986 | #define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
5987 | #define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
5988 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS |
5989 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
5990 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
5991 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL |
5992 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
5993 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
5994 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
5995 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
5996 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
5997 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
5998 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
5999 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6000 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL |
6001 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
6002 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
6003 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
6004 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
6005 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
6006 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
6007 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
6008 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6009 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL |
6010 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
6011 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
6012 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
6013 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
6014 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
6015 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
6016 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
6017 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6018 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL |
6019 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
6020 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
6021 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
6022 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
6023 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
6024 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
6025 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
6026 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6027 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL |
6028 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
6029 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
6030 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
6031 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
6032 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
6033 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
6034 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
6035 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6036 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL |
6037 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
6038 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
6039 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
6040 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
6041 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
6042 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
6043 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
6044 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6045 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL |
6046 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
6047 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
6048 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
6049 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
6050 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
6051 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
6052 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
6053 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6054 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL |
6055 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
6056 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
6057 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
6058 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
6059 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
6060 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
6061 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
6062 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6063 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL |
6064 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
6065 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
6066 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
6067 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
6068 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
6069 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
6070 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
6071 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6072 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL |
6073 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
6074 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
6075 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
6076 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
6077 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
6078 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
6079 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
6080 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6081 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL |
6082 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
6083 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
6084 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
6085 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
6086 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
6087 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
6088 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
6089 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6090 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL |
6091 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
6092 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
6093 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
6094 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
6095 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
6096 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
6097 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
6098 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6099 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL |
6100 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
6101 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
6102 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
6103 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
6104 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
6105 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
6106 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
6107 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6108 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL |
6109 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
6110 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
6111 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
6112 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
6113 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
6114 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
6115 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
6116 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6117 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL |
6118 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
6119 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
6120 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
6121 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
6122 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
6123 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
6124 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
6125 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6126 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL |
6127 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
6128 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
6129 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
6130 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
6131 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
6132 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
6133 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
6134 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
6135 | //BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST |
6136 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6137 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6138 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6139 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6140 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6141 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6142 | //BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP |
6143 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
6144 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
6145 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
6146 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
6147 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
6148 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
6149 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
6150 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
6151 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
6152 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
6153 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
6154 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
6155 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
6156 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
6157 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
6158 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
6159 | //BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL |
6160 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
6161 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
6162 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
6163 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
6164 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
6165 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
6166 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
6167 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
6168 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
6169 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
6170 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
6171 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
6172 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
6173 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
6174 | //BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST |
6175 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6176 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6177 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6178 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6179 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6180 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6181 | //BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP |
6182 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
6183 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
6184 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
6185 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 |
6186 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
6187 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
6188 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
6189 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L |
6190 | //BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL |
6191 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
6192 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
6193 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
6194 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
6195 | //BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST |
6196 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6197 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6198 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6199 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6200 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6201 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6202 | //BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL |
6203 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
6204 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
6205 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
6206 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
6207 | //BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS |
6208 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
6209 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
6210 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
6211 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
6212 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
6213 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
6214 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
6215 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
6216 | //BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
6217 | #define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
6218 | #define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
6219 | //BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
6220 | #define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
6221 | #define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
6222 | //BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST |
6223 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6224 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6225 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6226 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6227 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6228 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6229 | //BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP |
6230 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
6231 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
6232 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
6233 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
6234 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
6235 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
6236 | //BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL |
6237 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
6238 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
6239 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
6240 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
6241 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
6242 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
6243 | //BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST |
6244 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6245 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6246 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6247 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6248 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6249 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6250 | //BIF_CFG_DEV0_EPF0_PCIE_MC_CAP |
6251 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
6252 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
6253 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
6254 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
6255 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
6256 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
6257 | //BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL |
6258 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
6259 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
6260 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
6261 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
6262 | //BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 |
6263 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
6264 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
6265 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
6266 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
6267 | //BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 |
6268 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
6269 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
6270 | //BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 |
6271 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
6272 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
6273 | //BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 |
6274 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
6275 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
6276 | //BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 |
6277 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
6278 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
6279 | //BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 |
6280 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
6281 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
6282 | //BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
6283 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
6284 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
6285 | //BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
6286 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
6287 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
6288 | //BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST |
6289 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6290 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6291 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6292 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6293 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6294 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6295 | //BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP |
6296 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
6297 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
6298 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
6299 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
6300 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
6301 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
6302 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
6303 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
6304 | //BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST |
6305 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6306 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6307 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6308 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6309 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6310 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6311 | //BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP |
6312 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
6313 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
6314 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
6315 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
6316 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
6317 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
6318 | //BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL |
6319 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
6320 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
6321 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
6322 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
6323 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
6324 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
6325 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST |
6326 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6327 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6328 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6329 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6330 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6331 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6332 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP |
6333 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
6334 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 |
6335 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
6336 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L |
6337 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL |
6338 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
6339 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
6340 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
6341 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 |
6342 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
6343 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
6344 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
6345 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L |
6346 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS |
6347 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS |
6348 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
6349 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
6350 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS |
6351 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
6352 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
6353 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS |
6354 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
6355 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
6356 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK |
6357 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
6358 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL |
6359 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET |
6360 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
6361 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
6362 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE |
6363 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
6364 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
6365 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID |
6366 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
6367 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
6368 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
6369 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
6370 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
6371 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
6372 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
6373 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
6374 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 |
6375 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
6376 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
6377 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 |
6378 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
6379 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
6380 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 |
6381 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
6382 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
6383 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 |
6384 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
6385 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
6386 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 |
6387 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
6388 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
6389 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 |
6390 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
6391 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
6392 | //BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST |
6393 | #define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6394 | #define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6395 | #define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6396 | #define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6397 | #define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6398 | #define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6399 | //BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP |
6400 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
6401 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
6402 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
6403 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
6404 | //BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS |
6405 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
6406 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
6407 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
6408 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
6409 | //BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST |
6410 | #define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6411 | #define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6412 | #define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6413 | #define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6414 | #define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6415 | #define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6416 | //BIF_CFG_DEV0_EPF0_LINK_CAP_16GT |
6417 | #define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
6418 | #define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
6419 | //BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT |
6420 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
6421 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
6422 | //BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT |
6423 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
6424 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
6425 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
6426 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
6427 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
6428 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
6429 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
6430 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
6431 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
6432 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
6433 | //BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT |
6434 | #define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
6435 | #define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
6436 | //BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT |
6437 | #define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
6438 | #define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
6439 | //BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT |
6440 | #define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
6441 | #define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
6442 | //BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT |
6443 | #define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6444 | #define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
6445 | #define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
6446 | #define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
6447 | //BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT |
6448 | #define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6449 | #define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
6450 | #define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
6451 | #define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
6452 | //BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT |
6453 | #define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6454 | #define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
6455 | #define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
6456 | #define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
6457 | //BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT |
6458 | #define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6459 | #define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
6460 | #define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
6461 | #define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
6462 | //BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT |
6463 | #define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6464 | #define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
6465 | #define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
6466 | #define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
6467 | //BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT |
6468 | #define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6469 | #define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
6470 | #define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
6471 | #define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
6472 | //BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT |
6473 | #define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6474 | #define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
6475 | #define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
6476 | #define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
6477 | //BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT |
6478 | #define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6479 | #define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
6480 | #define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
6481 | #define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
6482 | //BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT |
6483 | #define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6484 | #define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
6485 | #define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
6486 | #define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
6487 | //BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT |
6488 | #define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6489 | #define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
6490 | #define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
6491 | #define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
6492 | //BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT |
6493 | #define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6494 | #define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
6495 | #define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
6496 | #define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
6497 | //BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT |
6498 | #define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6499 | #define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
6500 | #define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
6501 | #define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
6502 | //BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT |
6503 | #define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6504 | #define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
6505 | #define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
6506 | #define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
6507 | //BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT |
6508 | #define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6509 | #define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
6510 | #define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
6511 | #define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
6512 | //BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT |
6513 | #define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6514 | #define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
6515 | #define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
6516 | #define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
6517 | //BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT |
6518 | #define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
6519 | #define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
6520 | #define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
6521 | #define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
6522 | //BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST |
6523 | #define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6524 | #define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6525 | #define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6526 | #define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6527 | #define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6528 | #define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6529 | //BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP |
6530 | #define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
6531 | #define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
6532 | //BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS |
6533 | #define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
6534 | #define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
6535 | #define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
6536 | #define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
6537 | //BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL |
6538 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
6539 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
6540 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
6541 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
6542 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
6543 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
6544 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
6545 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
6546 | //BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS |
6547 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6548 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6549 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
6550 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6551 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6552 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
6553 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
6554 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6555 | //BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL |
6556 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
6557 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
6558 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
6559 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
6560 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
6561 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
6562 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
6563 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
6564 | //BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS |
6565 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6566 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6567 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
6568 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6569 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6570 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
6571 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
6572 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6573 | //BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL |
6574 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
6575 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
6576 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
6577 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
6578 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
6579 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
6580 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
6581 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
6582 | //BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS |
6583 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6584 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6585 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
6586 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6587 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6588 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
6589 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
6590 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6591 | //BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL |
6592 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
6593 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
6594 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
6595 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
6596 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
6597 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
6598 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
6599 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
6600 | //BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS |
6601 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6602 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6603 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
6604 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6605 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6606 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
6607 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
6608 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6609 | //BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL |
6610 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
6611 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
6612 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
6613 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
6614 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
6615 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
6616 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
6617 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
6618 | //BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS |
6619 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6620 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6621 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
6622 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6623 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6624 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
6625 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
6626 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6627 | //BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL |
6628 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
6629 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
6630 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
6631 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
6632 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
6633 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
6634 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
6635 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
6636 | //BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS |
6637 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6638 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6639 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
6640 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6641 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6642 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
6643 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
6644 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6645 | //BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL |
6646 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
6647 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
6648 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
6649 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
6650 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
6651 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
6652 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
6653 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
6654 | //BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS |
6655 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6656 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6657 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
6658 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6659 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6660 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
6661 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
6662 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6663 | //BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL |
6664 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
6665 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
6666 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
6667 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
6668 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
6669 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
6670 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
6671 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
6672 | //BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS |
6673 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6674 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6675 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
6676 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6677 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6678 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
6679 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
6680 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6681 | //BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL |
6682 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
6683 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
6684 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
6685 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
6686 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
6687 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
6688 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
6689 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
6690 | //BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS |
6691 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6692 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6693 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
6694 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6695 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6696 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
6697 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
6698 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6699 | //BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL |
6700 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
6701 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
6702 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
6703 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
6704 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
6705 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
6706 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
6707 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
6708 | //BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS |
6709 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6710 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6711 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
6712 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6713 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6714 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
6715 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
6716 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6717 | //BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL |
6718 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
6719 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
6720 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
6721 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
6722 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
6723 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
6724 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
6725 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
6726 | //BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS |
6727 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6728 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6729 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
6730 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6731 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6732 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
6733 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
6734 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6735 | //BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL |
6736 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
6737 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
6738 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
6739 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
6740 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
6741 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
6742 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
6743 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
6744 | //BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS |
6745 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6746 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6747 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
6748 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6749 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6750 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
6751 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
6752 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6753 | //BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL |
6754 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
6755 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
6756 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
6757 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
6758 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
6759 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
6760 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
6761 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
6762 | //BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS |
6763 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6764 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6765 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
6766 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6767 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6768 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
6769 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
6770 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6771 | //BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL |
6772 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
6773 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
6774 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
6775 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
6776 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
6777 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
6778 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
6779 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
6780 | //BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS |
6781 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6782 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6783 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
6784 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6785 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6786 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
6787 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
6788 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6789 | //BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL |
6790 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
6791 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
6792 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
6793 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
6794 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
6795 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
6796 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
6797 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
6798 | //BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS |
6799 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6800 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6801 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
6802 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6803 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6804 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
6805 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
6806 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6807 | //BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL |
6808 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
6809 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
6810 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
6811 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
6812 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
6813 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
6814 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
6815 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
6816 | //BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS |
6817 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
6818 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
6819 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
6820 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
6821 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
6822 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
6823 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
6824 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
6825 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST |
6826 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6827 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6828 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6829 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6830 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6831 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6832 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP |
6833 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
6834 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
6835 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL |
6836 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
6837 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
6838 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
6839 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
6840 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
6841 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
6842 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
6843 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
6844 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP |
6845 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
6846 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
6847 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL |
6848 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
6849 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
6850 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
6851 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
6852 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
6853 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
6854 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
6855 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
6856 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP |
6857 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
6858 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
6859 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL |
6860 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
6861 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
6862 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
6863 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
6864 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
6865 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
6866 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
6867 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
6868 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP |
6869 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
6870 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
6871 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL |
6872 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
6873 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
6874 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
6875 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
6876 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
6877 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
6878 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
6879 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
6880 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP |
6881 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
6882 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
6883 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL |
6884 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
6885 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
6886 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
6887 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
6888 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
6889 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
6890 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
6891 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
6892 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP |
6893 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
6894 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
6895 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL |
6896 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
6897 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
6898 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
6899 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
6900 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
6901 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
6902 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
6903 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
6904 | //BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST |
6905 | #define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
6906 | #define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
6907 | #define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
6908 | #define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
6909 | #define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
6910 | #define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
6911 | //BIF_CFG_DEV0_EPF0_RTR_DATA1 |
6912 | #define BIF_CFG_DEV0_EPF0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
6913 | #define BIF_CFG_DEV0_EPF0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
6914 | #define BIF_CFG_DEV0_EPF0_RTR_DATA1__VALID__SHIFT 0x1f |
6915 | #define BIF_CFG_DEV0_EPF0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
6916 | #define BIF_CFG_DEV0_EPF0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
6917 | #define BIF_CFG_DEV0_EPF0_RTR_DATA1__VALID_MASK 0x80000000L |
6918 | //BIF_CFG_DEV0_EPF0_RTR_DATA2 |
6919 | #define BIF_CFG_DEV0_EPF0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
6920 | #define BIF_CFG_DEV0_EPF0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
6921 | #define BIF_CFG_DEV0_EPF0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
6922 | #define BIF_CFG_DEV0_EPF0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
6923 | //PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV |
6924 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
6925 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
6926 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
6927 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL |
6928 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L |
6929 | #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L |
6930 | |
6931 | |
6932 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp |
6933 | //BIF_CFG_DEV0_EPF1_VENDOR_ID |
6934 | #define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
6935 | #define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
6936 | //BIF_CFG_DEV0_EPF1_DEVICE_ID |
6937 | #define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
6938 | #define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
6939 | //BIF_CFG_DEV0_EPF1_COMMAND |
6940 | #define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
6941 | #define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
6942 | #define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
6943 | #define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
6944 | #define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
6945 | #define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
6946 | #define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT 0x7 |
6947 | #define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT 0x8 |
6948 | #define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
6949 | #define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT 0xa |
6950 | #define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
6951 | #define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
6952 | #define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
6953 | #define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
6954 | #define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
6955 | #define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
6956 | #define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK 0x0080L |
6957 | #define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK 0x0100L |
6958 | #define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
6959 | #define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK 0x0400L |
6960 | //BIF_CFG_DEV0_EPF1_STATUS |
6961 | #define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
6962 | #define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT 0x3 |
6963 | #define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT 0x4 |
6964 | #define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT 0x5 |
6965 | #define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
6966 | #define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
6967 | #define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
6968 | #define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
6969 | #define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
6970 | #define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
6971 | #define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
6972 | #define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK 0x0008L |
6973 | #define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK 0x0010L |
6974 | #define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK 0x0020L |
6975 | #define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
6976 | #define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
6977 | #define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
6978 | #define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
6979 | #define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
6980 | #define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
6981 | //BIF_CFG_DEV0_EPF1_REVISION_ID |
6982 | #define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
6983 | #define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
6984 | #define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
6985 | #define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
6986 | //BIF_CFG_DEV0_EPF1_PROG_INTERFACE |
6987 | #define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
6988 | #define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
6989 | //BIF_CFG_DEV0_EPF1_SUB_CLASS |
6990 | #define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
6991 | #define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
6992 | //BIF_CFG_DEV0_EPF1_BASE_CLASS |
6993 | #define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
6994 | #define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
6995 | //BIF_CFG_DEV0_EPF1_CACHE_LINE |
6996 | #define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
6997 | #define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
6998 | //BIF_CFG_DEV0_EPF1_LATENCY |
6999 | #define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
7000 | #define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
7001 | //BIF_CFG_DEV0_EPF1_HEADER |
7002 | #define 0x0 |
7003 | #define 0x7 |
7004 | #define 0x7FL |
7005 | #define 0x80L |
7006 | //BIF_CFG_DEV0_EPF1_BIST |
7007 | #define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT 0x0 |
7008 | #define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT 0x6 |
7009 | #define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT 0x7 |
7010 | #define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK 0x0FL |
7011 | #define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK 0x40L |
7012 | #define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK 0x80L |
7013 | //BIF_CFG_DEV0_EPF1_BASE_ADDR_1 |
7014 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
7015 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
7016 | //BIF_CFG_DEV0_EPF1_BASE_ADDR_2 |
7017 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
7018 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
7019 | //BIF_CFG_DEV0_EPF1_BASE_ADDR_3 |
7020 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
7021 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
7022 | //BIF_CFG_DEV0_EPF1_BASE_ADDR_4 |
7023 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
7024 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
7025 | //BIF_CFG_DEV0_EPF1_BASE_ADDR_5 |
7026 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
7027 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
7028 | //BIF_CFG_DEV0_EPF1_BASE_ADDR_6 |
7029 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
7030 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
7031 | //BIF_CFG_DEV0_EPF1_ADAPTER_ID |
7032 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
7033 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
7034 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
7035 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
7036 | //BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR |
7037 | #define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
7038 | #define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
7039 | //BIF_CFG_DEV0_EPF1_CAP_PTR |
7040 | #define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
7041 | #define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK 0xFFL |
7042 | //BIF_CFG_DEV0_EPF1_INTERRUPT_LINE |
7043 | #define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
7044 | #define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
7045 | //BIF_CFG_DEV0_EPF1_INTERRUPT_PIN |
7046 | #define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
7047 | #define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
7048 | //BIF_CFG_DEV0_EPF1_MIN_GRANT |
7049 | #define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
7050 | #define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
7051 | //BIF_CFG_DEV0_EPF1_MAX_LATENCY |
7052 | #define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
7053 | #define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
7054 | //BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST |
7055 | #define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
7056 | #define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
7057 | #define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
7058 | #define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
7059 | #define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
7060 | #define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
7061 | //BIF_CFG_DEV0_EPF1_ADAPTER_ID_W |
7062 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
7063 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
7064 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
7065 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
7066 | //BIF_CFG_DEV0_EPF1_PMI_CAP_LIST |
7067 | #define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
7068 | #define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
7069 | #define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
7070 | #define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
7071 | //BIF_CFG_DEV0_EPF1_PMI_CAP |
7072 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT 0x0 |
7073 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
7074 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
7075 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
7076 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
7077 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
7078 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
7079 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
7080 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK 0x0007L |
7081 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
7082 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
7083 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
7084 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
7085 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
7086 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
7087 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
7088 | //BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL |
7089 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
7090 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
7091 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
7092 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
7093 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
7094 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
7095 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
7096 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
7097 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
7098 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
7099 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
7100 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
7101 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
7102 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
7103 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
7104 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
7105 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
7106 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
7107 | //BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST |
7108 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
7109 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
7110 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
7111 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
7112 | //BIF_CFG_DEV0_EPF1_PCIE_CAP |
7113 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT 0x0 |
7114 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
7115 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
7116 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
7117 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK 0x000FL |
7118 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
7119 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
7120 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
7121 | //BIF_CFG_DEV0_EPF1_DEVICE_CAP |
7122 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
7123 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
7124 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
7125 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
7126 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
7127 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
7128 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
7129 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
7130 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
7131 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
7132 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
7133 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
7134 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
7135 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
7136 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
7137 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
7138 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
7139 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
7140 | //BIF_CFG_DEV0_EPF1_DEVICE_CNTL |
7141 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
7142 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
7143 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
7144 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
7145 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
7146 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
7147 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
7148 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
7149 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
7150 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
7151 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
7152 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
7153 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
7154 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
7155 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
7156 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
7157 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
7158 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
7159 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
7160 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
7161 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
7162 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
7163 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
7164 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
7165 | //BIF_CFG_DEV0_EPF1_DEVICE_STATUS |
7166 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
7167 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
7168 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
7169 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
7170 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
7171 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
7172 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
7173 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
7174 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
7175 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
7176 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
7177 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
7178 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
7179 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
7180 | //BIF_CFG_DEV0_EPF1_LINK_CAP |
7181 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
7182 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
7183 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
7184 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
7185 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
7186 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
7187 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
7188 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
7189 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
7190 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
7191 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
7192 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
7193 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
7194 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
7195 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
7196 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
7197 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
7198 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
7199 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
7200 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
7201 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
7202 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
7203 | //BIF_CFG_DEV0_EPF1_LINK_CNTL |
7204 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
7205 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
7206 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
7207 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
7208 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
7209 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
7210 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
7211 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
7212 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
7213 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
7214 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
7215 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
7216 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
7217 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
7218 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
7219 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
7220 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
7221 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
7222 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
7223 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
7224 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
7225 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
7226 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
7227 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
7228 | //BIF_CFG_DEV0_EPF1_LINK_STATUS |
7229 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
7230 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
7231 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
7232 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
7233 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
7234 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
7235 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
7236 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
7237 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
7238 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
7239 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
7240 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
7241 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
7242 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
7243 | //BIF_CFG_DEV0_EPF1_DEVICE_CAP2 |
7244 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
7245 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
7246 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
7247 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
7248 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
7249 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
7250 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
7251 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
7252 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
7253 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
7254 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
7255 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
7256 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
7257 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
7258 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
7259 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
7260 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
7261 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
7262 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
7263 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
7264 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
7265 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
7266 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
7267 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
7268 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
7269 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
7270 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
7271 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
7272 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
7273 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
7274 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
7275 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
7276 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
7277 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
7278 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
7279 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
7280 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
7281 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
7282 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
7283 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
7284 | //BIF_CFG_DEV0_EPF1_DEVICE_CNTL2 |
7285 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
7286 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
7287 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
7288 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
7289 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
7290 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
7291 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
7292 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
7293 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
7294 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
7295 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
7296 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
7297 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
7298 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
7299 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
7300 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
7301 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
7302 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
7303 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
7304 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
7305 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
7306 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
7307 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
7308 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
7309 | //BIF_CFG_DEV0_EPF1_DEVICE_STATUS2 |
7310 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
7311 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
7312 | //BIF_CFG_DEV0_EPF1_LINK_CAP2 |
7313 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
7314 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
7315 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
7316 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
7317 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
7318 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
7319 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
7320 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
7321 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
7322 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
7323 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
7324 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
7325 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
7326 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
7327 | //BIF_CFG_DEV0_EPF1_LINK_CNTL2 |
7328 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
7329 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
7330 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
7331 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
7332 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
7333 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
7334 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
7335 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
7336 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
7337 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
7338 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
7339 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
7340 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
7341 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
7342 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
7343 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
7344 | //BIF_CFG_DEV0_EPF1_LINK_STATUS2 |
7345 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
7346 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
7347 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
7348 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
7349 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
7350 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
7351 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
7352 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
7353 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
7354 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
7355 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
7356 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
7357 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
7358 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
7359 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
7360 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
7361 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
7362 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
7363 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
7364 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
7365 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
7366 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
7367 | //BIF_CFG_DEV0_EPF1_MSI_CAP_LIST |
7368 | #define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
7369 | #define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
7370 | #define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
7371 | #define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
7372 | //BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL |
7373 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
7374 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
7375 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
7376 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
7377 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
7378 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
7379 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
7380 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
7381 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
7382 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
7383 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
7384 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
7385 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
7386 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
7387 | //BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO |
7388 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
7389 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
7390 | //BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI |
7391 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
7392 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
7393 | //BIF_CFG_DEV0_EPF1_MSI_MSG_DATA |
7394 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
7395 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
7396 | //BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA |
7397 | #define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
7398 | #define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
7399 | //BIF_CFG_DEV0_EPF1_MSI_MASK |
7400 | #define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
7401 | #define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
7402 | //BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 |
7403 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
7404 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
7405 | //BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 |
7406 | #define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
7407 | #define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
7408 | //BIF_CFG_DEV0_EPF1_MSI_MASK_64 |
7409 | #define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
7410 | #define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
7411 | //BIF_CFG_DEV0_EPF1_MSI_PENDING |
7412 | #define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
7413 | #define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
7414 | //BIF_CFG_DEV0_EPF1_MSI_PENDING_64 |
7415 | #define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
7416 | #define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
7417 | //BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST |
7418 | #define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
7419 | #define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
7420 | #define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
7421 | #define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
7422 | //BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL |
7423 | #define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
7424 | #define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
7425 | #define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
7426 | #define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
7427 | #define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
7428 | #define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
7429 | //BIF_CFG_DEV0_EPF1_MSIX_TABLE |
7430 | #define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
7431 | #define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
7432 | #define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
7433 | #define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
7434 | //BIF_CFG_DEV0_EPF1_MSIX_PBA |
7435 | #define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
7436 | #define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
7437 | #define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
7438 | #define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
7439 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
7440 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7441 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7442 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7443 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7444 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7445 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7446 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR |
7447 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
7448 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
7449 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
7450 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
7451 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
7452 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
7453 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 |
7454 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
7455 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
7456 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 |
7457 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
7458 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
7459 | //BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
7460 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7461 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7462 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7463 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7464 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7465 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7466 | //BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1 |
7467 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
7468 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
7469 | //BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2 |
7470 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
7471 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
7472 | //BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
7473 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7474 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7475 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7476 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7477 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7478 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7479 | //BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS |
7480 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
7481 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
7482 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
7483 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
7484 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
7485 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
7486 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
7487 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
7488 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
7489 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
7490 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
7491 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
7492 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
7493 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
7494 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
7495 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
7496 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
7497 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
7498 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
7499 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
7500 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
7501 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
7502 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
7503 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
7504 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
7505 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
7506 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
7507 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
7508 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
7509 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
7510 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
7511 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
7512 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
7513 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
7514 | //BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK |
7515 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
7516 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
7517 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
7518 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
7519 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
7520 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
7521 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
7522 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
7523 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
7524 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
7525 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
7526 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
7527 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
7528 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
7529 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
7530 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
7531 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
7532 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
7533 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
7534 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
7535 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
7536 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
7537 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
7538 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
7539 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
7540 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
7541 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
7542 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
7543 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
7544 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
7545 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
7546 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
7547 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
7548 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
7549 | //BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY |
7550 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
7551 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
7552 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
7553 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
7554 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
7555 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
7556 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
7557 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
7558 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
7559 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
7560 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
7561 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
7562 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
7563 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
7564 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
7565 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
7566 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
7567 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
7568 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
7569 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
7570 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
7571 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
7572 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
7573 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
7574 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
7575 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
7576 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
7577 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
7578 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
7579 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
7580 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
7581 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
7582 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
7583 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
7584 | //BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS |
7585 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
7586 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
7587 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
7588 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
7589 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
7590 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
7591 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
7592 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
7593 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
7594 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
7595 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
7596 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
7597 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
7598 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
7599 | //BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK |
7600 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
7601 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
7602 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
7603 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
7604 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
7605 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
7606 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
7607 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
7608 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
7609 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
7610 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
7611 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
7612 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
7613 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
7614 | //BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL |
7615 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
7616 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
7617 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
7618 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
7619 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
7620 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
7621 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
7622 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
7623 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
7624 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
7625 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
7626 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
7627 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
7628 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
7629 | //BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 |
7630 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
7631 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
7632 | //BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 |
7633 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
7634 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
7635 | //BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 |
7636 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
7637 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
7638 | //BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 |
7639 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
7640 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
7641 | //BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 |
7642 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
7643 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
7644 | //BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 |
7645 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
7646 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
7647 | //BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 |
7648 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
7649 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
7650 | //BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 |
7651 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
7652 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
7653 | //BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST |
7654 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7655 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7656 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7657 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7658 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7659 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7660 | //BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP |
7661 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
7662 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
7663 | //BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL |
7664 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
7665 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
7666 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
7667 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
7668 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
7669 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
7670 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
7671 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
7672 | //BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP |
7673 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
7674 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
7675 | //BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL |
7676 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
7677 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
7678 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
7679 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
7680 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
7681 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
7682 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
7683 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
7684 | //BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP |
7685 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
7686 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
7687 | //BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL |
7688 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
7689 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
7690 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
7691 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
7692 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
7693 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
7694 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
7695 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
7696 | //BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP |
7697 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
7698 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
7699 | //BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL |
7700 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
7701 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
7702 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
7703 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
7704 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
7705 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
7706 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
7707 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
7708 | //BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP |
7709 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
7710 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
7711 | //BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL |
7712 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
7713 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
7714 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
7715 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
7716 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
7717 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
7718 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
7719 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
7720 | //BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP |
7721 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
7722 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
7723 | //BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL |
7724 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
7725 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
7726 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
7727 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
7728 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
7729 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
7730 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
7731 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
7732 | //BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
7733 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7734 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7735 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7736 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7737 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7738 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7739 | //BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT |
7740 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
7741 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
7742 | //BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA |
7743 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
7744 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
7745 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
7746 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
7747 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
7748 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
7749 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
7750 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
7751 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
7752 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
7753 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
7754 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
7755 | //BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP |
7756 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
7757 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
7758 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST |
7759 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7760 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7761 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7762 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7763 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7764 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7765 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP |
7766 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
7767 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
7768 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
7769 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
7770 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
7771 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
7772 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
7773 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
7774 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
7775 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
7776 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR |
7777 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
7778 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
7779 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS |
7780 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
7781 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
7782 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
7783 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
7784 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL |
7785 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
7786 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
7787 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
7788 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7789 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7790 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
7791 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7792 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7793 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
7794 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7795 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7796 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
7797 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7798 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7799 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
7800 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7801 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7802 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
7803 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7804 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7805 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
7806 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7807 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7808 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
7809 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
7810 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
7811 | //BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST |
7812 | #define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7813 | #define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7814 | #define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7815 | #define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7816 | #define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7817 | #define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7818 | //BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3 |
7819 | #define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
7820 | #define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
7821 | #define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
7822 | #define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
7823 | #define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
7824 | #define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
7825 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS |
7826 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
7827 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
7828 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL |
7829 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7830 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7831 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7832 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7833 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7834 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7835 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7836 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7837 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL |
7838 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7839 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7840 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7841 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7842 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7843 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7844 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7845 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7846 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL |
7847 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7848 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7849 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7850 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7851 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7852 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7853 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7854 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7855 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL |
7856 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7857 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7858 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7859 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7860 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7861 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7862 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7863 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7864 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL |
7865 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7866 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7867 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7868 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7869 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7870 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7871 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7872 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7873 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL |
7874 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7875 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7876 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7877 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7878 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7879 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7880 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7881 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7882 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL |
7883 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7884 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7885 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7886 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7887 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7888 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7889 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7890 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7891 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL |
7892 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7893 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7894 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7895 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7896 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7897 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7898 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7899 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7900 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL |
7901 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7902 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7903 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7904 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7905 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7906 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7907 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7908 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7909 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL |
7910 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7911 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7912 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7913 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7914 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7915 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7916 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7917 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7918 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL |
7919 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7920 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7921 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7922 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7923 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7924 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7925 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7926 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7927 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL |
7928 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7929 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7930 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7931 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7932 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7933 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7934 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7935 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7936 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL |
7937 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7938 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7939 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7940 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7941 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7942 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7943 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7944 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7945 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL |
7946 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7947 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7948 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7949 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7950 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7951 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7952 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7953 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7954 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL |
7955 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7956 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7957 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7958 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7959 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7960 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7961 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7962 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7963 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL |
7964 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
7965 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
7966 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
7967 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
7968 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
7969 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
7970 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
7971 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
7972 | //BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST |
7973 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
7974 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
7975 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
7976 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
7977 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
7978 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
7979 | //BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP |
7980 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
7981 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
7982 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
7983 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
7984 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
7985 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
7986 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
7987 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
7988 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
7989 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
7990 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
7991 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
7992 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
7993 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
7994 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
7995 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
7996 | //BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL |
7997 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
7998 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
7999 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
8000 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
8001 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
8002 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
8003 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
8004 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
8005 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
8006 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
8007 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
8008 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
8009 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
8010 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
8011 | //BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST |
8012 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8013 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8014 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8015 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8016 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8017 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8018 | //BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP |
8019 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
8020 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
8021 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
8022 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 |
8023 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
8024 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
8025 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
8026 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L |
8027 | //BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL |
8028 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
8029 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
8030 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
8031 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
8032 | //BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST |
8033 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8034 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8035 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8036 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8037 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8038 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8039 | //BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL |
8040 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
8041 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
8042 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
8043 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
8044 | //BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS |
8045 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
8046 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
8047 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
8048 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
8049 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
8050 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
8051 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
8052 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
8053 | //BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
8054 | #define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
8055 | #define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
8056 | //BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
8057 | #define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
8058 | #define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
8059 | //BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST |
8060 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8061 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8062 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8063 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8064 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8065 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8066 | //BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP |
8067 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
8068 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
8069 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
8070 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
8071 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
8072 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
8073 | //BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL |
8074 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
8075 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
8076 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
8077 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
8078 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
8079 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
8080 | //BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST |
8081 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8082 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8083 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8084 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8085 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8086 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8087 | //BIF_CFG_DEV0_EPF1_PCIE_MC_CAP |
8088 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
8089 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
8090 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
8091 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
8092 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
8093 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
8094 | //BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL |
8095 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
8096 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
8097 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
8098 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
8099 | //BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0 |
8100 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
8101 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
8102 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
8103 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
8104 | //BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1 |
8105 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
8106 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
8107 | //BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0 |
8108 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
8109 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
8110 | //BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1 |
8111 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
8112 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
8113 | //BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0 |
8114 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
8115 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
8116 | //BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1 |
8117 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
8118 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
8119 | //BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0 |
8120 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
8121 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
8122 | //BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1 |
8123 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
8124 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
8125 | //BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST |
8126 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8127 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8128 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8129 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8130 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8131 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8132 | //BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP |
8133 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
8134 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
8135 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
8136 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
8137 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
8138 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
8139 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
8140 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
8141 | //BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST |
8142 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8143 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8144 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8145 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8146 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8147 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8148 | //BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP |
8149 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
8150 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
8151 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
8152 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
8153 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
8154 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
8155 | //BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL |
8156 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
8157 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
8158 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
8159 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
8160 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
8161 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
8162 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST |
8163 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8164 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8165 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8166 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8167 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8168 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8169 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP |
8170 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
8171 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 |
8172 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
8173 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L |
8174 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL |
8175 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
8176 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
8177 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
8178 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 |
8179 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
8180 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
8181 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
8182 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L |
8183 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS |
8184 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS |
8185 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
8186 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
8187 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS |
8188 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
8189 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
8190 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS |
8191 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
8192 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
8193 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK |
8194 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
8195 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL |
8196 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET |
8197 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
8198 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
8199 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE |
8200 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
8201 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
8202 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID |
8203 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
8204 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
8205 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
8206 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
8207 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
8208 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
8209 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
8210 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
8211 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 |
8212 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
8213 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
8214 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 |
8215 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
8216 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
8217 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 |
8218 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
8219 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
8220 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 |
8221 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
8222 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
8223 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 |
8224 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
8225 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
8226 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 |
8227 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
8228 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
8229 | //BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST |
8230 | #define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8231 | #define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8232 | #define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8233 | #define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8234 | #define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8235 | #define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8236 | //BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP |
8237 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
8238 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
8239 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
8240 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
8241 | //BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS |
8242 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
8243 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
8244 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
8245 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
8246 | //BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST |
8247 | #define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8248 | #define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8249 | #define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8250 | #define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8251 | #define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8252 | #define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8253 | //BIF_CFG_DEV0_EPF1_LINK_CAP_16GT |
8254 | #define BIF_CFG_DEV0_EPF1_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
8255 | #define BIF_CFG_DEV0_EPF1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
8256 | //BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT |
8257 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
8258 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
8259 | //BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT |
8260 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
8261 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
8262 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
8263 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
8264 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
8265 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
8266 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
8267 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
8268 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
8269 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
8270 | //BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT |
8271 | #define BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
8272 | #define BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
8273 | //BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT |
8274 | #define BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
8275 | #define BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
8276 | //BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT |
8277 | #define BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
8278 | #define BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
8279 | //BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT |
8280 | #define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8281 | #define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
8282 | #define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
8283 | #define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
8284 | //BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT |
8285 | #define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8286 | #define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
8287 | #define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
8288 | #define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
8289 | //BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT |
8290 | #define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8291 | #define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
8292 | #define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
8293 | #define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
8294 | //BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT |
8295 | #define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8296 | #define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
8297 | #define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
8298 | #define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
8299 | //BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT |
8300 | #define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8301 | #define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
8302 | #define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
8303 | #define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
8304 | //BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT |
8305 | #define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8306 | #define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
8307 | #define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
8308 | #define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
8309 | //BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT |
8310 | #define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8311 | #define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
8312 | #define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
8313 | #define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
8314 | //BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT |
8315 | #define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8316 | #define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
8317 | #define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
8318 | #define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
8319 | //BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT |
8320 | #define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8321 | #define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
8322 | #define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
8323 | #define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
8324 | //BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT |
8325 | #define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8326 | #define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
8327 | #define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
8328 | #define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
8329 | //BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT |
8330 | #define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8331 | #define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
8332 | #define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
8333 | #define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
8334 | //BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT |
8335 | #define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8336 | #define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
8337 | #define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
8338 | #define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
8339 | //BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT |
8340 | #define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8341 | #define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
8342 | #define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
8343 | #define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
8344 | //BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT |
8345 | #define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8346 | #define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
8347 | #define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
8348 | #define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
8349 | //BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT |
8350 | #define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8351 | #define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
8352 | #define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
8353 | #define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
8354 | //BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT |
8355 | #define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
8356 | #define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
8357 | #define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
8358 | #define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
8359 | //BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST |
8360 | #define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8361 | #define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8362 | #define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8363 | #define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8364 | #define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8365 | #define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8366 | //BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP |
8367 | #define BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
8368 | #define BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
8369 | //BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS |
8370 | #define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
8371 | #define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
8372 | #define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
8373 | #define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
8374 | //BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL |
8375 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
8376 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
8377 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
8378 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
8379 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
8380 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
8381 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
8382 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
8383 | //BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS |
8384 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8385 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8386 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
8387 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8388 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8389 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
8390 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
8391 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8392 | //BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL |
8393 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
8394 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
8395 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
8396 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
8397 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
8398 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
8399 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
8400 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
8401 | //BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS |
8402 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8403 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8404 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
8405 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8406 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8407 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
8408 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
8409 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8410 | //BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL |
8411 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
8412 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
8413 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
8414 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
8415 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
8416 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
8417 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
8418 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
8419 | //BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS |
8420 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8421 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8422 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
8423 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8424 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8425 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
8426 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
8427 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8428 | //BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL |
8429 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
8430 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
8431 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
8432 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
8433 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
8434 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
8435 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
8436 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
8437 | //BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS |
8438 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8439 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8440 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
8441 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8442 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8443 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
8444 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
8445 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8446 | //BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL |
8447 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
8448 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
8449 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
8450 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
8451 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
8452 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
8453 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
8454 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
8455 | //BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS |
8456 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8457 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8458 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
8459 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8460 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8461 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
8462 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
8463 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8464 | //BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL |
8465 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
8466 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
8467 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
8468 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
8469 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
8470 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
8471 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
8472 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
8473 | //BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS |
8474 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8475 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8476 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
8477 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8478 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8479 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
8480 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
8481 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8482 | //BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL |
8483 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
8484 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
8485 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
8486 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
8487 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
8488 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
8489 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
8490 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
8491 | //BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS |
8492 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8493 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8494 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
8495 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8496 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8497 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
8498 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
8499 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8500 | //BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL |
8501 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
8502 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
8503 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
8504 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
8505 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
8506 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
8507 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
8508 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
8509 | //BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS |
8510 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8511 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8512 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
8513 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8514 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8515 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
8516 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
8517 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8518 | //BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL |
8519 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
8520 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
8521 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
8522 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
8523 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
8524 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
8525 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
8526 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
8527 | //BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS |
8528 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8529 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8530 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
8531 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8532 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8533 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
8534 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
8535 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8536 | //BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL |
8537 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
8538 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
8539 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
8540 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
8541 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
8542 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
8543 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
8544 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
8545 | //BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS |
8546 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8547 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8548 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
8549 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8550 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8551 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
8552 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
8553 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8554 | //BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL |
8555 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
8556 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
8557 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
8558 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
8559 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
8560 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
8561 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
8562 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
8563 | //BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS |
8564 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8565 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8566 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
8567 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8568 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8569 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
8570 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
8571 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8572 | //BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL |
8573 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
8574 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
8575 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
8576 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
8577 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
8578 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
8579 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
8580 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
8581 | //BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS |
8582 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8583 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8584 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
8585 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8586 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8587 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
8588 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
8589 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8590 | //BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL |
8591 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
8592 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
8593 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
8594 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
8595 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
8596 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
8597 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
8598 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
8599 | //BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS |
8600 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8601 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8602 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
8603 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8604 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8605 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
8606 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
8607 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8608 | //BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL |
8609 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
8610 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
8611 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
8612 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
8613 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
8614 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
8615 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
8616 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
8617 | //BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS |
8618 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8619 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8620 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
8621 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8622 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8623 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
8624 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
8625 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8626 | //BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL |
8627 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
8628 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
8629 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
8630 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
8631 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
8632 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
8633 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
8634 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
8635 | //BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS |
8636 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8637 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8638 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
8639 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8640 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8641 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
8642 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
8643 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8644 | //BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL |
8645 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
8646 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
8647 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
8648 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
8649 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
8650 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
8651 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
8652 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
8653 | //BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS |
8654 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
8655 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
8656 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
8657 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
8658 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
8659 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
8660 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
8661 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
8662 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST |
8663 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8664 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8665 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8666 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8667 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8668 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8669 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP |
8670 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
8671 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
8672 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL |
8673 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
8674 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
8675 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
8676 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
8677 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
8678 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
8679 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
8680 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
8681 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP |
8682 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
8683 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
8684 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL |
8685 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
8686 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
8687 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
8688 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
8689 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
8690 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
8691 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
8692 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
8693 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP |
8694 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
8695 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
8696 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL |
8697 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
8698 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
8699 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
8700 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
8701 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
8702 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
8703 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
8704 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
8705 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP |
8706 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
8707 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
8708 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL |
8709 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
8710 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
8711 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
8712 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
8713 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
8714 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
8715 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
8716 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
8717 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP |
8718 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
8719 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
8720 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL |
8721 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
8722 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
8723 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
8724 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
8725 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
8726 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
8727 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
8728 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
8729 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP |
8730 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
8731 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
8732 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL |
8733 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
8734 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
8735 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
8736 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
8737 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
8738 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
8739 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
8740 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
8741 | //BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST |
8742 | #define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
8743 | #define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
8744 | #define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
8745 | #define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
8746 | #define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
8747 | #define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
8748 | //BIF_CFG_DEV0_EPF1_RTR_DATA1 |
8749 | #define BIF_CFG_DEV0_EPF1_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
8750 | #define BIF_CFG_DEV0_EPF1_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
8751 | #define BIF_CFG_DEV0_EPF1_RTR_DATA1__VALID__SHIFT 0x1f |
8752 | #define BIF_CFG_DEV0_EPF1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
8753 | #define BIF_CFG_DEV0_EPF1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
8754 | #define BIF_CFG_DEV0_EPF1_RTR_DATA1__VALID_MASK 0x80000000L |
8755 | //BIF_CFG_DEV0_EPF1_RTR_DATA2 |
8756 | #define BIF_CFG_DEV0_EPF1_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
8757 | #define BIF_CFG_DEV0_EPF1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
8758 | #define BIF_CFG_DEV0_EPF1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
8759 | #define BIF_CFG_DEV0_EPF1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
8760 | |
8761 | |
8762 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp |
8763 | //BIF_CFG_DEV0_EPF2_VENDOR_ID |
8764 | #define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
8765 | #define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
8766 | //BIF_CFG_DEV0_EPF2_DEVICE_ID |
8767 | #define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
8768 | #define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
8769 | //BIF_CFG_DEV0_EPF2_COMMAND |
8770 | #define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
8771 | #define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
8772 | #define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
8773 | #define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
8774 | #define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
8775 | #define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
8776 | #define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING__SHIFT 0x7 |
8777 | #define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN__SHIFT 0x8 |
8778 | #define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
8779 | #define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS__SHIFT 0xa |
8780 | #define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
8781 | #define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
8782 | #define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
8783 | #define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
8784 | #define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
8785 | #define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
8786 | #define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING_MASK 0x0080L |
8787 | #define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN_MASK 0x0100L |
8788 | #define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
8789 | #define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS_MASK 0x0400L |
8790 | //BIF_CFG_DEV0_EPF2_STATUS |
8791 | #define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
8792 | #define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS__SHIFT 0x3 |
8793 | #define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST__SHIFT 0x4 |
8794 | #define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP__SHIFT 0x5 |
8795 | #define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
8796 | #define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
8797 | #define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
8798 | #define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
8799 | #define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
8800 | #define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
8801 | #define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
8802 | #define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS_MASK 0x0008L |
8803 | #define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST_MASK 0x0010L |
8804 | #define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP_MASK 0x0020L |
8805 | #define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
8806 | #define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
8807 | #define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
8808 | #define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
8809 | #define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
8810 | #define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
8811 | //BIF_CFG_DEV0_EPF2_REVISION_ID |
8812 | #define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
8813 | #define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
8814 | #define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
8815 | #define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
8816 | //BIF_CFG_DEV0_EPF2_PROG_INTERFACE |
8817 | #define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
8818 | #define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
8819 | //BIF_CFG_DEV0_EPF2_SUB_CLASS |
8820 | #define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
8821 | #define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
8822 | //BIF_CFG_DEV0_EPF2_BASE_CLASS |
8823 | #define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
8824 | #define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
8825 | //BIF_CFG_DEV0_EPF2_CACHE_LINE |
8826 | #define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
8827 | #define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
8828 | //BIF_CFG_DEV0_EPF2_LATENCY |
8829 | #define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
8830 | #define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
8831 | //BIF_CFG_DEV0_EPF2_HEADER |
8832 | #define 0x0 |
8833 | #define 0x7 |
8834 | #define 0x7FL |
8835 | #define 0x80L |
8836 | //BIF_CFG_DEV0_EPF2_BIST |
8837 | #define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP__SHIFT 0x0 |
8838 | #define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT__SHIFT 0x6 |
8839 | #define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP__SHIFT 0x7 |
8840 | #define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP_MASK 0x0FL |
8841 | #define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT_MASK 0x40L |
8842 | #define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP_MASK 0x80L |
8843 | //BIF_CFG_DEV0_EPF2_BASE_ADDR_1 |
8844 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
8845 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
8846 | //BIF_CFG_DEV0_EPF2_BASE_ADDR_2 |
8847 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
8848 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
8849 | //BIF_CFG_DEV0_EPF2_BASE_ADDR_3 |
8850 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
8851 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
8852 | //BIF_CFG_DEV0_EPF2_BASE_ADDR_4 |
8853 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
8854 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
8855 | //BIF_CFG_DEV0_EPF2_BASE_ADDR_5 |
8856 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
8857 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
8858 | //BIF_CFG_DEV0_EPF2_BASE_ADDR_6 |
8859 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
8860 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
8861 | //BIF_CFG_DEV0_EPF2_ADAPTER_ID |
8862 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
8863 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
8864 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
8865 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
8866 | //BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR |
8867 | #define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
8868 | #define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
8869 | //BIF_CFG_DEV0_EPF2_CAP_PTR |
8870 | #define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
8871 | #define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR_MASK 0xFFL |
8872 | //BIF_CFG_DEV0_EPF2_INTERRUPT_LINE |
8873 | #define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
8874 | #define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
8875 | //BIF_CFG_DEV0_EPF2_INTERRUPT_PIN |
8876 | #define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
8877 | #define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
8878 | //BIF_CFG_DEV0_EPF2_MIN_GRANT |
8879 | #define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
8880 | #define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT_MASK 0xFFL |
8881 | //BIF_CFG_DEV0_EPF2_MAX_LATENCY |
8882 | #define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
8883 | #define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
8884 | //BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST |
8885 | #define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
8886 | #define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
8887 | #define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
8888 | #define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
8889 | #define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
8890 | #define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
8891 | //BIF_CFG_DEV0_EPF2_ADAPTER_ID_W |
8892 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
8893 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
8894 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
8895 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
8896 | //BIF_CFG_DEV0_EPF2_PMI_CAP_LIST |
8897 | #define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
8898 | #define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
8899 | #define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
8900 | #define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
8901 | //BIF_CFG_DEV0_EPF2_PMI_CAP |
8902 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION__SHIFT 0x0 |
8903 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
8904 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
8905 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
8906 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
8907 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
8908 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
8909 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
8910 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION_MASK 0x0007L |
8911 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
8912 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
8913 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
8914 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
8915 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
8916 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
8917 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
8918 | //BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL |
8919 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
8920 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
8921 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
8922 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
8923 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
8924 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
8925 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
8926 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
8927 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
8928 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
8929 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
8930 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
8931 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
8932 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
8933 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
8934 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
8935 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
8936 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
8937 | //BIF_CFG_DEV0_EPF2_SBRN |
8938 | #define BIF_CFG_DEV0_EPF2_SBRN__SBRN__SHIFT 0x0 |
8939 | #define BIF_CFG_DEV0_EPF2_SBRN__SBRN_MASK 0xFFL |
8940 | //BIF_CFG_DEV0_EPF2_FLADJ |
8941 | #define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ__SHIFT 0x0 |
8942 | #define BIF_CFG_DEV0_EPF2_FLADJ__NFC__SHIFT 0x6 |
8943 | #define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ_MASK 0x3FL |
8944 | #define BIF_CFG_DEV0_EPF2_FLADJ__NFC_MASK 0x40L |
8945 | //BIF_CFG_DEV0_EPF2_DBESL_DBESLD |
8946 | #define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL__SHIFT 0x0 |
8947 | #define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
8948 | #define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL_MASK 0x0FL |
8949 | #define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD_MASK 0xF0L |
8950 | //BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST |
8951 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
8952 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
8953 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
8954 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
8955 | //BIF_CFG_DEV0_EPF2_PCIE_CAP |
8956 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION__SHIFT 0x0 |
8957 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
8958 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
8959 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
8960 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION_MASK 0x000FL |
8961 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
8962 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
8963 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
8964 | //BIF_CFG_DEV0_EPF2_DEVICE_CAP |
8965 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
8966 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
8967 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
8968 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
8969 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
8970 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
8971 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
8972 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
8973 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
8974 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
8975 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
8976 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
8977 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
8978 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
8979 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
8980 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
8981 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
8982 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
8983 | //BIF_CFG_DEV0_EPF2_DEVICE_CNTL |
8984 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
8985 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
8986 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
8987 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
8988 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
8989 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
8990 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
8991 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
8992 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
8993 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
8994 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
8995 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
8996 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
8997 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
8998 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
8999 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
9000 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
9001 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
9002 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
9003 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
9004 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
9005 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
9006 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
9007 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
9008 | //BIF_CFG_DEV0_EPF2_DEVICE_STATUS |
9009 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
9010 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
9011 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
9012 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
9013 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
9014 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
9015 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
9016 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
9017 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
9018 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
9019 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
9020 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
9021 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
9022 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
9023 | //BIF_CFG_DEV0_EPF2_LINK_CAP |
9024 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
9025 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
9026 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
9027 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
9028 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
9029 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
9030 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
9031 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
9032 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
9033 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
9034 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
9035 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
9036 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
9037 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
9038 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
9039 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
9040 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
9041 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
9042 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
9043 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
9044 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
9045 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
9046 | //BIF_CFG_DEV0_EPF2_LINK_CNTL |
9047 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
9048 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
9049 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
9050 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
9051 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
9052 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
9053 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
9054 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
9055 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
9056 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
9057 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
9058 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
9059 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
9060 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
9061 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
9062 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
9063 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
9064 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
9065 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
9066 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
9067 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
9068 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
9069 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
9070 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
9071 | //BIF_CFG_DEV0_EPF2_LINK_STATUS |
9072 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
9073 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
9074 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
9075 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
9076 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
9077 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
9078 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
9079 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
9080 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
9081 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
9082 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
9083 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
9084 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
9085 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
9086 | //BIF_CFG_DEV0_EPF2_DEVICE_CAP2 |
9087 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
9088 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
9089 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
9090 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
9091 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
9092 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
9093 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
9094 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
9095 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
9096 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
9097 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
9098 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
9099 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
9100 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
9101 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
9102 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
9103 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
9104 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
9105 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
9106 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
9107 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
9108 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
9109 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
9110 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
9111 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
9112 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
9113 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
9114 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
9115 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
9116 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
9117 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
9118 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
9119 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
9120 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
9121 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
9122 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
9123 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
9124 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
9125 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
9126 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
9127 | //BIF_CFG_DEV0_EPF2_DEVICE_CNTL2 |
9128 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
9129 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
9130 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
9131 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
9132 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
9133 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
9134 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
9135 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
9136 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
9137 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
9138 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
9139 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
9140 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
9141 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
9142 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
9143 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
9144 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
9145 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
9146 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
9147 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
9148 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
9149 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
9150 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
9151 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
9152 | //BIF_CFG_DEV0_EPF2_DEVICE_STATUS2 |
9153 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
9154 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
9155 | //BIF_CFG_DEV0_EPF2_LINK_CAP2 |
9156 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
9157 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
9158 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
9159 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
9160 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
9161 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
9162 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
9163 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
9164 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
9165 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
9166 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
9167 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
9168 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
9169 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
9170 | //BIF_CFG_DEV0_EPF2_LINK_CNTL2 |
9171 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
9172 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
9173 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
9174 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
9175 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
9176 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
9177 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
9178 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
9179 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
9180 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
9181 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
9182 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
9183 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
9184 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
9185 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
9186 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
9187 | //BIF_CFG_DEV0_EPF2_LINK_STATUS2 |
9188 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
9189 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
9190 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
9191 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
9192 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
9193 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
9194 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
9195 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
9196 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
9197 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
9198 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
9199 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
9200 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
9201 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
9202 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
9203 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
9204 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
9205 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
9206 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
9207 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
9208 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
9209 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
9210 | //BIF_CFG_DEV0_EPF2_MSI_CAP_LIST |
9211 | #define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
9212 | #define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
9213 | #define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
9214 | #define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
9215 | //BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL |
9216 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
9217 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
9218 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
9219 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
9220 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
9221 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
9222 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
9223 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
9224 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
9225 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
9226 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
9227 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
9228 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
9229 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
9230 | //BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO |
9231 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
9232 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
9233 | //BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI |
9234 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
9235 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
9236 | //BIF_CFG_DEV0_EPF2_MSI_MSG_DATA |
9237 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
9238 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
9239 | //BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA |
9240 | #define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
9241 | #define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
9242 | //BIF_CFG_DEV0_EPF2_MSI_MASK |
9243 | #define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK__SHIFT 0x0 |
9244 | #define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
9245 | //BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64 |
9246 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
9247 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
9248 | //BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64 |
9249 | #define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
9250 | #define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
9251 | //BIF_CFG_DEV0_EPF2_MSI_MASK_64 |
9252 | #define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
9253 | #define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
9254 | //BIF_CFG_DEV0_EPF2_MSI_PENDING |
9255 | #define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
9256 | #define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
9257 | //BIF_CFG_DEV0_EPF2_MSI_PENDING_64 |
9258 | #define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
9259 | #define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
9260 | //BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST |
9261 | #define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
9262 | #define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
9263 | #define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
9264 | #define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
9265 | //BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL |
9266 | #define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
9267 | #define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
9268 | #define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
9269 | #define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
9270 | #define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
9271 | #define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
9272 | //BIF_CFG_DEV0_EPF2_MSIX_TABLE |
9273 | #define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
9274 | #define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
9275 | #define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
9276 | #define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
9277 | //BIF_CFG_DEV0_EPF2_MSIX_PBA |
9278 | #define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
9279 | #define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
9280 | #define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
9281 | #define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
9282 | //BIF_CFG_DEV0_EPF2_SATA_CAP_0 |
9283 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
9284 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
9285 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
9286 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
9287 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
9288 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
9289 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
9290 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
9291 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
9292 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
9293 | //BIF_CFG_DEV0_EPF2_SATA_CAP_1 |
9294 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
9295 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
9296 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
9297 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
9298 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
9299 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
9300 | //BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX |
9301 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
9302 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
9303 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
9304 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
9305 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
9306 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
9307 | //BIF_CFG_DEV0_EPF2_SATA_IDP_DATA |
9308 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
9309 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
9310 | //BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
9311 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9312 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9313 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9314 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9315 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9316 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9317 | //BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR |
9318 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
9319 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
9320 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
9321 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
9322 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
9323 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
9324 | //BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1 |
9325 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
9326 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
9327 | //BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2 |
9328 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
9329 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
9330 | //BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
9331 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9332 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9333 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9334 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9335 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9336 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9337 | //BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS |
9338 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
9339 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
9340 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
9341 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
9342 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
9343 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
9344 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
9345 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
9346 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
9347 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
9348 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
9349 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
9350 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
9351 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
9352 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
9353 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
9354 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
9355 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
9356 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
9357 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
9358 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
9359 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
9360 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
9361 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
9362 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
9363 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
9364 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
9365 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
9366 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
9367 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
9368 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
9369 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
9370 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
9371 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
9372 | //BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK |
9373 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
9374 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
9375 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
9376 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
9377 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
9378 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
9379 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
9380 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
9381 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
9382 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
9383 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
9384 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
9385 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
9386 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
9387 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
9388 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
9389 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
9390 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
9391 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
9392 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
9393 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
9394 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
9395 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
9396 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
9397 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
9398 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
9399 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
9400 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
9401 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
9402 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
9403 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
9404 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
9405 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
9406 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
9407 | //BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY |
9408 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
9409 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
9410 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
9411 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
9412 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
9413 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
9414 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
9415 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
9416 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
9417 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
9418 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
9419 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
9420 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
9421 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
9422 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
9423 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
9424 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
9425 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
9426 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
9427 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
9428 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
9429 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
9430 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
9431 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
9432 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
9433 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
9434 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
9435 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
9436 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
9437 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
9438 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
9439 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
9440 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
9441 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
9442 | //BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS |
9443 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
9444 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
9445 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
9446 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
9447 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
9448 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
9449 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
9450 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
9451 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
9452 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
9453 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
9454 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
9455 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
9456 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
9457 | //BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK |
9458 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
9459 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
9460 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
9461 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
9462 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
9463 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
9464 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
9465 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
9466 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
9467 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
9468 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
9469 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
9470 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
9471 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
9472 | //BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL |
9473 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
9474 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
9475 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
9476 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
9477 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
9478 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
9479 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
9480 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
9481 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
9482 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
9483 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
9484 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
9485 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
9486 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
9487 | //BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0 |
9488 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
9489 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
9490 | //BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1 |
9491 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
9492 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
9493 | //BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2 |
9494 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
9495 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
9496 | //BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3 |
9497 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
9498 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
9499 | //BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0 |
9500 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
9501 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
9502 | //BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1 |
9503 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
9504 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
9505 | //BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2 |
9506 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
9507 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
9508 | //BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3 |
9509 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
9510 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
9511 | //BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST |
9512 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9513 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9514 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9515 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9516 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9517 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9518 | //BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP |
9519 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
9520 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
9521 | //BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL |
9522 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
9523 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
9524 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
9525 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
9526 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
9527 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
9528 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
9529 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
9530 | //BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP |
9531 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
9532 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
9533 | //BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL |
9534 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
9535 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
9536 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
9537 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
9538 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
9539 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
9540 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
9541 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
9542 | //BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP |
9543 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
9544 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
9545 | //BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL |
9546 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
9547 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
9548 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
9549 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
9550 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
9551 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
9552 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
9553 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
9554 | //BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP |
9555 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
9556 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
9557 | //BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL |
9558 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
9559 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
9560 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
9561 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
9562 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
9563 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
9564 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
9565 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
9566 | //BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP |
9567 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
9568 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
9569 | //BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL |
9570 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
9571 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
9572 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
9573 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
9574 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
9575 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
9576 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
9577 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
9578 | //BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP |
9579 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
9580 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
9581 | //BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL |
9582 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
9583 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
9584 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
9585 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
9586 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
9587 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
9588 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
9589 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
9590 | //BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST |
9591 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9592 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9593 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9594 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9595 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9596 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9597 | //BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT |
9598 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
9599 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
9600 | //BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA |
9601 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
9602 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
9603 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
9604 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
9605 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
9606 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
9607 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
9608 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
9609 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
9610 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
9611 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
9612 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
9613 | //BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP |
9614 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
9615 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
9616 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST |
9617 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9618 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9619 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9620 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9621 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9622 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9623 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP |
9624 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
9625 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
9626 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
9627 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
9628 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
9629 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
9630 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
9631 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
9632 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
9633 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
9634 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR |
9635 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
9636 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
9637 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS |
9638 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
9639 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
9640 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
9641 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
9642 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL |
9643 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
9644 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
9645 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
9646 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9647 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9648 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
9649 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9650 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9651 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
9652 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9653 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9654 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
9655 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9656 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9657 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
9658 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9659 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9660 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
9661 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9662 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9663 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
9664 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9665 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9666 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
9667 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
9668 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
9669 | //BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST |
9670 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9671 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9672 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9673 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9674 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9675 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9676 | //BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP |
9677 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
9678 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
9679 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
9680 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
9681 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
9682 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
9683 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
9684 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
9685 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
9686 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
9687 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
9688 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
9689 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
9690 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
9691 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
9692 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
9693 | //BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL |
9694 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
9695 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
9696 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
9697 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
9698 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
9699 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
9700 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
9701 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
9702 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
9703 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
9704 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
9705 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
9706 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
9707 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
9708 | //BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST |
9709 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9710 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9711 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9712 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9713 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9714 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9715 | //BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP |
9716 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
9717 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
9718 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
9719 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
9720 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
9721 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
9722 | //BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL |
9723 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
9724 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
9725 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
9726 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
9727 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
9728 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
9729 | //BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST |
9730 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9731 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9732 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9733 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9734 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9735 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9736 | //BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP |
9737 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
9738 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
9739 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
9740 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
9741 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
9742 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
9743 | //BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL |
9744 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
9745 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
9746 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
9747 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
9748 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
9749 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
9750 | //BIF_CFG_DEV0_EPF2_PCIE_RTR_ENH_CAP_LIST |
9751 | #define BIF_CFG_DEV0_EPF2_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
9752 | #define BIF_CFG_DEV0_EPF2_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
9753 | #define BIF_CFG_DEV0_EPF2_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
9754 | #define BIF_CFG_DEV0_EPF2_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
9755 | #define BIF_CFG_DEV0_EPF2_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
9756 | #define BIF_CFG_DEV0_EPF2_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
9757 | //BIF_CFG_DEV0_EPF2_RTR_DATA1 |
9758 | #define BIF_CFG_DEV0_EPF2_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
9759 | #define BIF_CFG_DEV0_EPF2_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
9760 | #define BIF_CFG_DEV0_EPF2_RTR_DATA1__VALID__SHIFT 0x1f |
9761 | #define BIF_CFG_DEV0_EPF2_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
9762 | #define BIF_CFG_DEV0_EPF2_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
9763 | #define BIF_CFG_DEV0_EPF2_RTR_DATA1__VALID_MASK 0x80000000L |
9764 | //BIF_CFG_DEV0_EPF2_RTR_DATA2 |
9765 | #define BIF_CFG_DEV0_EPF2_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
9766 | #define BIF_CFG_DEV0_EPF2_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
9767 | #define BIF_CFG_DEV0_EPF2_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
9768 | #define BIF_CFG_DEV0_EPF2_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
9769 | |
9770 | |
9771 | // addressBlock: nbio_nbif0_bif_cfg_dev2_epf0_bifcfgdecp |
9772 | //BIF_CFG_DEV2_EPF0_VENDOR_ID |
9773 | #define BIF_CFG_DEV2_EPF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
9774 | #define BIF_CFG_DEV2_EPF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
9775 | //BIF_CFG_DEV2_EPF0_DEVICE_ID |
9776 | #define BIF_CFG_DEV2_EPF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
9777 | #define BIF_CFG_DEV2_EPF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
9778 | //BIF_CFG_DEV2_EPF0_COMMAND |
9779 | #define BIF_CFG_DEV2_EPF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
9780 | #define BIF_CFG_DEV2_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
9781 | #define BIF_CFG_DEV2_EPF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
9782 | #define BIF_CFG_DEV2_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
9783 | #define BIF_CFG_DEV2_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
9784 | #define BIF_CFG_DEV2_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
9785 | #define BIF_CFG_DEV2_EPF0_COMMAND__AD_STEPPING__SHIFT 0x7 |
9786 | #define BIF_CFG_DEV2_EPF0_COMMAND__SERR_EN__SHIFT 0x8 |
9787 | #define BIF_CFG_DEV2_EPF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
9788 | #define BIF_CFG_DEV2_EPF0_COMMAND__INT_DIS__SHIFT 0xa |
9789 | #define BIF_CFG_DEV2_EPF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
9790 | #define BIF_CFG_DEV2_EPF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
9791 | #define BIF_CFG_DEV2_EPF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
9792 | #define BIF_CFG_DEV2_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
9793 | #define BIF_CFG_DEV2_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
9794 | #define BIF_CFG_DEV2_EPF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
9795 | #define BIF_CFG_DEV2_EPF0_COMMAND__AD_STEPPING_MASK 0x0080L |
9796 | #define BIF_CFG_DEV2_EPF0_COMMAND__SERR_EN_MASK 0x0100L |
9797 | #define BIF_CFG_DEV2_EPF0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
9798 | #define BIF_CFG_DEV2_EPF0_COMMAND__INT_DIS_MASK 0x0400L |
9799 | //BIF_CFG_DEV2_EPF0_STATUS |
9800 | #define BIF_CFG_DEV2_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
9801 | #define BIF_CFG_DEV2_EPF0_STATUS__INT_STATUS__SHIFT 0x3 |
9802 | #define BIF_CFG_DEV2_EPF0_STATUS__CAP_LIST__SHIFT 0x4 |
9803 | #define BIF_CFG_DEV2_EPF0_STATUS__PCI_66_CAP__SHIFT 0x5 |
9804 | #define BIF_CFG_DEV2_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
9805 | #define BIF_CFG_DEV2_EPF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
9806 | #define BIF_CFG_DEV2_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
9807 | #define BIF_CFG_DEV2_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
9808 | #define BIF_CFG_DEV2_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
9809 | #define BIF_CFG_DEV2_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
9810 | #define BIF_CFG_DEV2_EPF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
9811 | #define BIF_CFG_DEV2_EPF0_STATUS__INT_STATUS_MASK 0x0008L |
9812 | #define BIF_CFG_DEV2_EPF0_STATUS__CAP_LIST_MASK 0x0010L |
9813 | #define BIF_CFG_DEV2_EPF0_STATUS__PCI_66_CAP_MASK 0x0020L |
9814 | #define BIF_CFG_DEV2_EPF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
9815 | #define BIF_CFG_DEV2_EPF0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
9816 | #define BIF_CFG_DEV2_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
9817 | #define BIF_CFG_DEV2_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
9818 | #define BIF_CFG_DEV2_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
9819 | #define BIF_CFG_DEV2_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
9820 | //BIF_CFG_DEV2_EPF0_REVISION_ID |
9821 | #define BIF_CFG_DEV2_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
9822 | #define BIF_CFG_DEV2_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
9823 | #define BIF_CFG_DEV2_EPF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
9824 | #define BIF_CFG_DEV2_EPF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
9825 | //BIF_CFG_DEV2_EPF0_PROG_INTERFACE |
9826 | #define BIF_CFG_DEV2_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
9827 | #define BIF_CFG_DEV2_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
9828 | //BIF_CFG_DEV2_EPF0_SUB_CLASS |
9829 | #define BIF_CFG_DEV2_EPF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
9830 | #define BIF_CFG_DEV2_EPF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
9831 | //BIF_CFG_DEV2_EPF0_BASE_CLASS |
9832 | #define BIF_CFG_DEV2_EPF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
9833 | #define BIF_CFG_DEV2_EPF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
9834 | //BIF_CFG_DEV2_EPF0_CACHE_LINE |
9835 | #define BIF_CFG_DEV2_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
9836 | #define BIF_CFG_DEV2_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
9837 | //BIF_CFG_DEV2_EPF0_LATENCY |
9838 | #define BIF_CFG_DEV2_EPF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
9839 | #define BIF_CFG_DEV2_EPF0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
9840 | //BIF_CFG_DEV2_EPF0_HEADER |
9841 | #define 0x0 |
9842 | #define 0x7 |
9843 | #define 0x7FL |
9844 | #define 0x80L |
9845 | //BIF_CFG_DEV2_EPF0_BIST |
9846 | #define BIF_CFG_DEV2_EPF0_BIST__BIST_COMP__SHIFT 0x0 |
9847 | #define BIF_CFG_DEV2_EPF0_BIST__BIST_STRT__SHIFT 0x6 |
9848 | #define BIF_CFG_DEV2_EPF0_BIST__BIST_CAP__SHIFT 0x7 |
9849 | #define BIF_CFG_DEV2_EPF0_BIST__BIST_COMP_MASK 0x0FL |
9850 | #define BIF_CFG_DEV2_EPF0_BIST__BIST_STRT_MASK 0x40L |
9851 | #define BIF_CFG_DEV2_EPF0_BIST__BIST_CAP_MASK 0x80L |
9852 | //BIF_CFG_DEV2_EPF0_BASE_ADDR_1 |
9853 | #define BIF_CFG_DEV2_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
9854 | #define BIF_CFG_DEV2_EPF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
9855 | //BIF_CFG_DEV2_EPF0_BASE_ADDR_2 |
9856 | #define BIF_CFG_DEV2_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
9857 | #define BIF_CFG_DEV2_EPF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
9858 | //BIF_CFG_DEV2_EPF0_BASE_ADDR_3 |
9859 | #define BIF_CFG_DEV2_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
9860 | #define BIF_CFG_DEV2_EPF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
9861 | //BIF_CFG_DEV2_EPF0_BASE_ADDR_4 |
9862 | #define BIF_CFG_DEV2_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
9863 | #define BIF_CFG_DEV2_EPF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
9864 | //BIF_CFG_DEV2_EPF0_BASE_ADDR_5 |
9865 | #define BIF_CFG_DEV2_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
9866 | #define BIF_CFG_DEV2_EPF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
9867 | //BIF_CFG_DEV2_EPF0_BASE_ADDR_6 |
9868 | #define BIF_CFG_DEV2_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
9869 | #define BIF_CFG_DEV2_EPF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
9870 | //BIF_CFG_DEV2_EPF0_ADAPTER_ID |
9871 | #define BIF_CFG_DEV2_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
9872 | #define BIF_CFG_DEV2_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
9873 | #define BIF_CFG_DEV2_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
9874 | #define BIF_CFG_DEV2_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
9875 | //BIF_CFG_DEV2_EPF0_ROM_BASE_ADDR |
9876 | #define BIF_CFG_DEV2_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
9877 | #define BIF_CFG_DEV2_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
9878 | //BIF_CFG_DEV2_EPF0_CAP_PTR |
9879 | #define BIF_CFG_DEV2_EPF0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
9880 | #define BIF_CFG_DEV2_EPF0_CAP_PTR__CAP_PTR_MASK 0xFFL |
9881 | //BIF_CFG_DEV2_EPF0_INTERRUPT_LINE |
9882 | #define BIF_CFG_DEV2_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
9883 | #define BIF_CFG_DEV2_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
9884 | //BIF_CFG_DEV2_EPF0_INTERRUPT_PIN |
9885 | #define BIF_CFG_DEV2_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
9886 | #define BIF_CFG_DEV2_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
9887 | //BIF_CFG_DEV2_EPF0_MIN_GRANT |
9888 | #define BIF_CFG_DEV2_EPF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
9889 | #define BIF_CFG_DEV2_EPF0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
9890 | //BIF_CFG_DEV2_EPF0_MAX_LATENCY |
9891 | #define BIF_CFG_DEV2_EPF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
9892 | #define BIF_CFG_DEV2_EPF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
9893 | //BIF_CFG_DEV2_EPF0_VENDOR_CAP_LIST |
9894 | #define BIF_CFG_DEV2_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
9895 | #define BIF_CFG_DEV2_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
9896 | #define BIF_CFG_DEV2_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
9897 | #define BIF_CFG_DEV2_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
9898 | #define BIF_CFG_DEV2_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
9899 | #define BIF_CFG_DEV2_EPF0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
9900 | //BIF_CFG_DEV2_EPF0_ADAPTER_ID_W |
9901 | #define BIF_CFG_DEV2_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
9902 | #define BIF_CFG_DEV2_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
9903 | #define BIF_CFG_DEV2_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
9904 | #define BIF_CFG_DEV2_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
9905 | //BIF_CFG_DEV2_EPF0_PMI_CAP_LIST |
9906 | #define BIF_CFG_DEV2_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
9907 | #define BIF_CFG_DEV2_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
9908 | #define BIF_CFG_DEV2_EPF0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
9909 | #define BIF_CFG_DEV2_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
9910 | //BIF_CFG_DEV2_EPF0_PMI_CAP |
9911 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__VERSION__SHIFT 0x0 |
9912 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
9913 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
9914 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
9915 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
9916 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
9917 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
9918 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
9919 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__VERSION_MASK 0x0007L |
9920 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
9921 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
9922 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
9923 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
9924 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
9925 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
9926 | #define BIF_CFG_DEV2_EPF0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
9927 | //BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL |
9928 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
9929 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
9930 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
9931 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
9932 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
9933 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
9934 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
9935 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
9936 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
9937 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
9938 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
9939 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
9940 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
9941 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
9942 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
9943 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
9944 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
9945 | #define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
9946 | //BIF_CFG_DEV2_EPF0_SBRN |
9947 | #define BIF_CFG_DEV2_EPF0_SBRN__SBRN__SHIFT 0x0 |
9948 | #define BIF_CFG_DEV2_EPF0_SBRN__SBRN_MASK 0xFFL |
9949 | //BIF_CFG_DEV2_EPF0_FLADJ |
9950 | #define BIF_CFG_DEV2_EPF0_FLADJ__FLADJ__SHIFT 0x0 |
9951 | #define BIF_CFG_DEV2_EPF0_FLADJ__NFC__SHIFT 0x6 |
9952 | #define BIF_CFG_DEV2_EPF0_FLADJ__FLADJ_MASK 0x3FL |
9953 | #define BIF_CFG_DEV2_EPF0_FLADJ__NFC_MASK 0x40L |
9954 | //BIF_CFG_DEV2_EPF0_DBESL_DBESLD |
9955 | #define BIF_CFG_DEV2_EPF0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
9956 | #define BIF_CFG_DEV2_EPF0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
9957 | #define BIF_CFG_DEV2_EPF0_DBESL_DBESLD__DBESL_MASK 0x0FL |
9958 | #define BIF_CFG_DEV2_EPF0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
9959 | //BIF_CFG_DEV2_EPF0_PCIE_CAP_LIST |
9960 | #define BIF_CFG_DEV2_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
9961 | #define BIF_CFG_DEV2_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
9962 | #define BIF_CFG_DEV2_EPF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
9963 | #define BIF_CFG_DEV2_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
9964 | //BIF_CFG_DEV2_EPF0_PCIE_CAP |
9965 | #define BIF_CFG_DEV2_EPF0_PCIE_CAP__VERSION__SHIFT 0x0 |
9966 | #define BIF_CFG_DEV2_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
9967 | #define BIF_CFG_DEV2_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
9968 | #define BIF_CFG_DEV2_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
9969 | #define BIF_CFG_DEV2_EPF0_PCIE_CAP__VERSION_MASK 0x000FL |
9970 | #define BIF_CFG_DEV2_EPF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
9971 | #define BIF_CFG_DEV2_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
9972 | #define BIF_CFG_DEV2_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
9973 | //BIF_CFG_DEV2_EPF0_DEVICE_CAP |
9974 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
9975 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
9976 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
9977 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
9978 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
9979 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
9980 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
9981 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
9982 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
9983 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
9984 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
9985 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
9986 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
9987 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
9988 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
9989 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
9990 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
9991 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
9992 | //BIF_CFG_DEV2_EPF0_DEVICE_CNTL |
9993 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
9994 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
9995 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
9996 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
9997 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
9998 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
9999 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
10000 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
10001 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
10002 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
10003 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
10004 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
10005 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
10006 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
10007 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
10008 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
10009 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
10010 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
10011 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
10012 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
10013 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
10014 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
10015 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
10016 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
10017 | //BIF_CFG_DEV2_EPF0_DEVICE_STATUS |
10018 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
10019 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
10020 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
10021 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
10022 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
10023 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
10024 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
10025 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
10026 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
10027 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
10028 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
10029 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
10030 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
10031 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
10032 | //BIF_CFG_DEV2_EPF0_LINK_CAP |
10033 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
10034 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
10035 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
10036 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
10037 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
10038 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
10039 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
10040 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
10041 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
10042 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
10043 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
10044 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
10045 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
10046 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
10047 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
10048 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
10049 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
10050 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
10051 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
10052 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
10053 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
10054 | #define BIF_CFG_DEV2_EPF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
10055 | //BIF_CFG_DEV2_EPF0_LINK_CNTL |
10056 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
10057 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
10058 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
10059 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
10060 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
10061 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
10062 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
10063 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
10064 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
10065 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
10066 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
10067 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
10068 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
10069 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
10070 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
10071 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
10072 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
10073 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
10074 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
10075 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
10076 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
10077 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
10078 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
10079 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
10080 | //BIF_CFG_DEV2_EPF0_LINK_STATUS |
10081 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
10082 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
10083 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
10084 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
10085 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
10086 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
10087 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
10088 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
10089 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
10090 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
10091 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
10092 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
10093 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
10094 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
10095 | //BIF_CFG_DEV2_EPF0_DEVICE_CAP2 |
10096 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
10097 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
10098 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
10099 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
10100 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
10101 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
10102 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
10103 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
10104 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
10105 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
10106 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
10107 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
10108 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
10109 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
10110 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
10111 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
10112 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
10113 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
10114 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
10115 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
10116 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
10117 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
10118 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
10119 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
10120 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
10121 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
10122 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
10123 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
10124 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
10125 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
10126 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
10127 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
10128 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
10129 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
10130 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
10131 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
10132 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
10133 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
10134 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
10135 | #define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
10136 | //BIF_CFG_DEV2_EPF0_DEVICE_CNTL2 |
10137 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
10138 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
10139 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
10140 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
10141 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
10142 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
10143 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
10144 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
10145 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
10146 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
10147 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
10148 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
10149 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
10150 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
10151 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
10152 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
10153 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
10154 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
10155 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
10156 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
10157 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
10158 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
10159 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
10160 | #define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
10161 | //BIF_CFG_DEV2_EPF0_DEVICE_STATUS2 |
10162 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
10163 | #define BIF_CFG_DEV2_EPF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
10164 | //BIF_CFG_DEV2_EPF0_LINK_CAP2 |
10165 | #define BIF_CFG_DEV2_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
10166 | #define BIF_CFG_DEV2_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
10167 | #define BIF_CFG_DEV2_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
10168 | #define BIF_CFG_DEV2_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
10169 | #define BIF_CFG_DEV2_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
10170 | #define BIF_CFG_DEV2_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
10171 | #define BIF_CFG_DEV2_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
10172 | #define BIF_CFG_DEV2_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
10173 | #define BIF_CFG_DEV2_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
10174 | #define BIF_CFG_DEV2_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
10175 | #define BIF_CFG_DEV2_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
10176 | #define BIF_CFG_DEV2_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
10177 | #define BIF_CFG_DEV2_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
10178 | #define BIF_CFG_DEV2_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
10179 | //BIF_CFG_DEV2_EPF0_LINK_CNTL2 |
10180 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
10181 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
10182 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
10183 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
10184 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
10185 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
10186 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
10187 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
10188 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
10189 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
10190 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
10191 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
10192 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
10193 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
10194 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
10195 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
10196 | //BIF_CFG_DEV2_EPF0_LINK_STATUS2 |
10197 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
10198 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
10199 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
10200 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
10201 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
10202 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
10203 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
10204 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
10205 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
10206 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
10207 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
10208 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
10209 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
10210 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
10211 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
10212 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
10213 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
10214 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
10215 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
10216 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
10217 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
10218 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
10219 | //BIF_CFG_DEV2_EPF0_MSI_CAP_LIST |
10220 | #define BIF_CFG_DEV2_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
10221 | #define BIF_CFG_DEV2_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
10222 | #define BIF_CFG_DEV2_EPF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
10223 | #define BIF_CFG_DEV2_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
10224 | //BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL |
10225 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
10226 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
10227 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
10228 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
10229 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
10230 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
10231 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
10232 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
10233 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
10234 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
10235 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
10236 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
10237 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
10238 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
10239 | //BIF_CFG_DEV2_EPF0_MSI_MSG_ADDR_LO |
10240 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
10241 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
10242 | //BIF_CFG_DEV2_EPF0_MSI_MSG_ADDR_HI |
10243 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
10244 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
10245 | //BIF_CFG_DEV2_EPF0_MSI_MSG_DATA |
10246 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
10247 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
10248 | //BIF_CFG_DEV2_EPF0_MSI_EXT_MSG_DATA |
10249 | #define BIF_CFG_DEV2_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
10250 | #define BIF_CFG_DEV2_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
10251 | //BIF_CFG_DEV2_EPF0_MSI_MASK |
10252 | #define BIF_CFG_DEV2_EPF0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
10253 | #define BIF_CFG_DEV2_EPF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
10254 | //BIF_CFG_DEV2_EPF0_MSI_MSG_DATA_64 |
10255 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
10256 | #define BIF_CFG_DEV2_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
10257 | //BIF_CFG_DEV2_EPF0_MSI_EXT_MSG_DATA_64 |
10258 | #define BIF_CFG_DEV2_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
10259 | #define BIF_CFG_DEV2_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
10260 | //BIF_CFG_DEV2_EPF0_MSI_MASK_64 |
10261 | #define BIF_CFG_DEV2_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
10262 | #define BIF_CFG_DEV2_EPF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
10263 | //BIF_CFG_DEV2_EPF0_MSI_PENDING |
10264 | #define BIF_CFG_DEV2_EPF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
10265 | #define BIF_CFG_DEV2_EPF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
10266 | //BIF_CFG_DEV2_EPF0_MSI_PENDING_64 |
10267 | #define BIF_CFG_DEV2_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
10268 | #define BIF_CFG_DEV2_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
10269 | //BIF_CFG_DEV2_EPF0_MSIX_CAP_LIST |
10270 | #define BIF_CFG_DEV2_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
10271 | #define BIF_CFG_DEV2_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
10272 | #define BIF_CFG_DEV2_EPF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
10273 | #define BIF_CFG_DEV2_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
10274 | //BIF_CFG_DEV2_EPF0_MSIX_MSG_CNTL |
10275 | #define BIF_CFG_DEV2_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
10276 | #define BIF_CFG_DEV2_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
10277 | #define BIF_CFG_DEV2_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
10278 | #define BIF_CFG_DEV2_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
10279 | #define BIF_CFG_DEV2_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
10280 | #define BIF_CFG_DEV2_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
10281 | //BIF_CFG_DEV2_EPF0_MSIX_TABLE |
10282 | #define BIF_CFG_DEV2_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
10283 | #define BIF_CFG_DEV2_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
10284 | #define BIF_CFG_DEV2_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
10285 | #define BIF_CFG_DEV2_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
10286 | //BIF_CFG_DEV2_EPF0_MSIX_PBA |
10287 | #define BIF_CFG_DEV2_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
10288 | #define BIF_CFG_DEV2_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
10289 | #define BIF_CFG_DEV2_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
10290 | #define BIF_CFG_DEV2_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
10291 | //BIF_CFG_DEV2_EPF0_SATA_CAP_0 |
10292 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
10293 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
10294 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
10295 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
10296 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
10297 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
10298 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
10299 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
10300 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
10301 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
10302 | //BIF_CFG_DEV2_EPF0_SATA_CAP_1 |
10303 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
10304 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
10305 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
10306 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
10307 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
10308 | #define BIF_CFG_DEV2_EPF0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
10309 | //BIF_CFG_DEV2_EPF0_SATA_IDP_INDEX |
10310 | #define BIF_CFG_DEV2_EPF0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
10311 | #define BIF_CFG_DEV2_EPF0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
10312 | #define BIF_CFG_DEV2_EPF0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
10313 | #define BIF_CFG_DEV2_EPF0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
10314 | #define BIF_CFG_DEV2_EPF0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
10315 | #define BIF_CFG_DEV2_EPF0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
10316 | //BIF_CFG_DEV2_EPF0_SATA_IDP_DATA |
10317 | #define BIF_CFG_DEV2_EPF0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
10318 | #define BIF_CFG_DEV2_EPF0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
10319 | //BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
10320 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10321 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10322 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10323 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10324 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10325 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10326 | //BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_HDR |
10327 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
10328 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
10329 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
10330 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
10331 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
10332 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
10333 | //BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC1 |
10334 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
10335 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
10336 | //BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC2 |
10337 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
10338 | #define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
10339 | //BIF_CFG_DEV2_EPF0_PCIE_VC_ENH_CAP_LIST |
10340 | #define BIF_CFG_DEV2_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10341 | #define BIF_CFG_DEV2_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10342 | #define BIF_CFG_DEV2_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10343 | #define BIF_CFG_DEV2_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10344 | #define BIF_CFG_DEV2_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10345 | #define BIF_CFG_DEV2_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10346 | //BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1 |
10347 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
10348 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
10349 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
10350 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
10351 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
10352 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
10353 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
10354 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
10355 | //BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG2 |
10356 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
10357 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
10358 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
10359 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
10360 | //BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CNTL |
10361 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
10362 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
10363 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
10364 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
10365 | //BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_STATUS |
10366 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
10367 | #define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
10368 | //BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP |
10369 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
10370 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
10371 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
10372 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
10373 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
10374 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
10375 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
10376 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
10377 | //BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL |
10378 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
10379 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
10380 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
10381 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
10382 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
10383 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
10384 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
10385 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
10386 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
10387 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
10388 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
10389 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
10390 | //BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_STATUS |
10391 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
10392 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
10393 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
10394 | #define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
10395 | //BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP |
10396 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
10397 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
10398 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
10399 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
10400 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
10401 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
10402 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
10403 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
10404 | //BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL |
10405 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
10406 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
10407 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
10408 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
10409 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
10410 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
10411 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
10412 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
10413 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
10414 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
10415 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
10416 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
10417 | //BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_STATUS |
10418 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
10419 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
10420 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
10421 | #define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
10422 | //BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
10423 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10424 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10425 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10426 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10427 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10428 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10429 | //BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS |
10430 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
10431 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
10432 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
10433 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
10434 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
10435 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
10436 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
10437 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
10438 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
10439 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
10440 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
10441 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
10442 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
10443 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
10444 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
10445 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
10446 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
10447 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
10448 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
10449 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
10450 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
10451 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
10452 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
10453 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
10454 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
10455 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
10456 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
10457 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
10458 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
10459 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
10460 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
10461 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
10462 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
10463 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
10464 | //BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK |
10465 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
10466 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
10467 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
10468 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
10469 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
10470 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
10471 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
10472 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
10473 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
10474 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
10475 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
10476 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
10477 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
10478 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
10479 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
10480 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
10481 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
10482 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
10483 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
10484 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
10485 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
10486 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
10487 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
10488 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
10489 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
10490 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
10491 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
10492 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
10493 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
10494 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
10495 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
10496 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
10497 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
10498 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
10499 | //BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY |
10500 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
10501 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
10502 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
10503 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
10504 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
10505 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
10506 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
10507 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
10508 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
10509 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
10510 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
10511 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
10512 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
10513 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
10514 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
10515 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
10516 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
10517 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
10518 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
10519 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
10520 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
10521 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
10522 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
10523 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
10524 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
10525 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
10526 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
10527 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
10528 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
10529 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
10530 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
10531 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
10532 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
10533 | #define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
10534 | //BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS |
10535 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
10536 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
10537 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
10538 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
10539 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
10540 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
10541 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
10542 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
10543 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
10544 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
10545 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
10546 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
10547 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
10548 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
10549 | //BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK |
10550 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
10551 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
10552 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
10553 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
10554 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
10555 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
10556 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
10557 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
10558 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
10559 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
10560 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
10561 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
10562 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
10563 | #define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
10564 | //BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL |
10565 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
10566 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
10567 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
10568 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
10569 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
10570 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
10571 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
10572 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
10573 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
10574 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
10575 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
10576 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
10577 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
10578 | #define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
10579 | //BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG0 |
10580 | #define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
10581 | #define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
10582 | //BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG1 |
10583 | #define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
10584 | #define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
10585 | //BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG2 |
10586 | #define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
10587 | #define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
10588 | //BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG3 |
10589 | #define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
10590 | #define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
10591 | //BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG0 |
10592 | #define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
10593 | #define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
10594 | //BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG1 |
10595 | #define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
10596 | #define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
10597 | //BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG2 |
10598 | #define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
10599 | #define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
10600 | //BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG3 |
10601 | #define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
10602 | #define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
10603 | //BIF_CFG_DEV2_EPF0_PCIE_BAR_ENH_CAP_LIST |
10604 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10605 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10606 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10607 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10608 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10609 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10610 | //BIF_CFG_DEV2_EPF0_PCIE_BAR1_CAP |
10611 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
10612 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
10613 | //BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL |
10614 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
10615 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
10616 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
10617 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
10618 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
10619 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
10620 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
10621 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
10622 | //BIF_CFG_DEV2_EPF0_PCIE_BAR2_CAP |
10623 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
10624 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
10625 | //BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL |
10626 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
10627 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
10628 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
10629 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
10630 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
10631 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
10632 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
10633 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
10634 | //BIF_CFG_DEV2_EPF0_PCIE_BAR3_CAP |
10635 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
10636 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
10637 | //BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL |
10638 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
10639 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
10640 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
10641 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
10642 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
10643 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
10644 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
10645 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
10646 | //BIF_CFG_DEV2_EPF0_PCIE_BAR4_CAP |
10647 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
10648 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
10649 | //BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL |
10650 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
10651 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
10652 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
10653 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
10654 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
10655 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
10656 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
10657 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
10658 | //BIF_CFG_DEV2_EPF0_PCIE_BAR5_CAP |
10659 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
10660 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
10661 | //BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL |
10662 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
10663 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
10664 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
10665 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
10666 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
10667 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
10668 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
10669 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
10670 | //BIF_CFG_DEV2_EPF0_PCIE_BAR6_CAP |
10671 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
10672 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
10673 | //BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL |
10674 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
10675 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
10676 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
10677 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
10678 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
10679 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
10680 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
10681 | #define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
10682 | //BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
10683 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10684 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10685 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10686 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10687 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10688 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10689 | //BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA_SELECT |
10690 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
10691 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
10692 | //BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA |
10693 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
10694 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
10695 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
10696 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
10697 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
10698 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
10699 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
10700 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
10701 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
10702 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
10703 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
10704 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
10705 | //BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_CAP |
10706 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
10707 | #define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
10708 | //BIF_CFG_DEV2_EPF0_PCIE_DPA_ENH_CAP_LIST |
10709 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10710 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10711 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10712 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10713 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10714 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10715 | //BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP |
10716 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
10717 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
10718 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
10719 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
10720 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
10721 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
10722 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
10723 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
10724 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
10725 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
10726 | //BIF_CFG_DEV2_EPF0_PCIE_DPA_LATENCY_INDICATOR |
10727 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
10728 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
10729 | //BIF_CFG_DEV2_EPF0_PCIE_DPA_STATUS |
10730 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
10731 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
10732 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
10733 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
10734 | //BIF_CFG_DEV2_EPF0_PCIE_DPA_CNTL |
10735 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
10736 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
10737 | //BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
10738 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10739 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10740 | //BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
10741 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10742 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10743 | //BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
10744 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10745 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10746 | //BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
10747 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10748 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10749 | //BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
10750 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10751 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10752 | //BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
10753 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10754 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10755 | //BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
10756 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10757 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10758 | //BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
10759 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
10760 | #define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
10761 | //BIF_CFG_DEV2_EPF0_PCIE_SECONDARY_ENH_CAP_LIST |
10762 | #define BIF_CFG_DEV2_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10763 | #define BIF_CFG_DEV2_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10764 | #define BIF_CFG_DEV2_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10765 | #define BIF_CFG_DEV2_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10766 | #define BIF_CFG_DEV2_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10767 | #define BIF_CFG_DEV2_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10768 | //BIF_CFG_DEV2_EPF0_PCIE_LINK_CNTL3 |
10769 | #define BIF_CFG_DEV2_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
10770 | #define BIF_CFG_DEV2_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
10771 | #define BIF_CFG_DEV2_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
10772 | #define BIF_CFG_DEV2_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
10773 | #define BIF_CFG_DEV2_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
10774 | #define BIF_CFG_DEV2_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
10775 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_ERROR_STATUS |
10776 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
10777 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
10778 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL |
10779 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10780 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10781 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10782 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10783 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10784 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10785 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10786 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10787 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL |
10788 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10789 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10790 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10791 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10792 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10793 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10794 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10795 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10796 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL |
10797 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10798 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10799 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10800 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10801 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10802 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10803 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10804 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10805 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL |
10806 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10807 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10808 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10809 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10810 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10811 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10812 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10813 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10814 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL |
10815 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10816 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10817 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10818 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10819 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10820 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10821 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10822 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10823 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL |
10824 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10825 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10826 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10827 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10828 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10829 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10830 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10831 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10832 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL |
10833 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10834 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10835 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10836 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10837 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10838 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10839 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10840 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10841 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL |
10842 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10843 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10844 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10845 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10846 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10847 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10848 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10849 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10850 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL |
10851 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10852 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10853 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10854 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10855 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10856 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10857 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10858 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10859 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL |
10860 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10861 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10862 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10863 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10864 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10865 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10866 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10867 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10868 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL |
10869 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10870 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10871 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10872 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10873 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10874 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10875 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10876 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10877 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL |
10878 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10879 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10880 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10881 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10882 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10883 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10884 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10885 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10886 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL |
10887 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10888 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10889 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10890 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10891 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10892 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10893 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10894 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10895 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL |
10896 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10897 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10898 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10899 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10900 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10901 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10902 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10903 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10904 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL |
10905 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10906 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10907 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10908 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10909 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10910 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10911 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10912 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10913 | //BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL |
10914 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
10915 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
10916 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
10917 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
10918 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
10919 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
10920 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
10921 | #define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
10922 | //BIF_CFG_DEV2_EPF0_PCIE_ACS_ENH_CAP_LIST |
10923 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10924 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10925 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10926 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10927 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10928 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10929 | //BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP |
10930 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
10931 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
10932 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
10933 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
10934 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
10935 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
10936 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
10937 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
10938 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
10939 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
10940 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
10941 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
10942 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
10943 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
10944 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
10945 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
10946 | //BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL |
10947 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
10948 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
10949 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
10950 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
10951 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
10952 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
10953 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
10954 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
10955 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
10956 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
10957 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
10958 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
10959 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
10960 | #define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
10961 | //BIF_CFG_DEV2_EPF0_PCIE_PASID_ENH_CAP_LIST |
10962 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10963 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10964 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10965 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10966 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10967 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10968 | //BIF_CFG_DEV2_EPF0_PCIE_PASID_CAP |
10969 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
10970 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
10971 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
10972 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
10973 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
10974 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
10975 | //BIF_CFG_DEV2_EPF0_PCIE_PASID_CNTL |
10976 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
10977 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
10978 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
10979 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
10980 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
10981 | #define BIF_CFG_DEV2_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
10982 | //BIF_CFG_DEV2_EPF0_PCIE_LTR_ENH_CAP_LIST |
10983 | #define BIF_CFG_DEV2_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
10984 | #define BIF_CFG_DEV2_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
10985 | #define BIF_CFG_DEV2_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
10986 | #define BIF_CFG_DEV2_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
10987 | #define BIF_CFG_DEV2_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
10988 | #define BIF_CFG_DEV2_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
10989 | //BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP |
10990 | #define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
10991 | #define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
10992 | #define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
10993 | #define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
10994 | #define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
10995 | #define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
10996 | #define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
10997 | #define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
10998 | //BIF_CFG_DEV2_EPF0_PCIE_ARI_ENH_CAP_LIST |
10999 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
11000 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
11001 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
11002 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
11003 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
11004 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
11005 | //BIF_CFG_DEV2_EPF0_PCIE_ARI_CAP |
11006 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
11007 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
11008 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
11009 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
11010 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
11011 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
11012 | //BIF_CFG_DEV2_EPF0_PCIE_ARI_CNTL |
11013 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
11014 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
11015 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
11016 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
11017 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
11018 | #define BIF_CFG_DEV2_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
11019 | //BIF_CFG_DEV2_EPF0_PCIE_DLF_ENH_CAP_LIST |
11020 | #define BIF_CFG_DEV2_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
11021 | #define BIF_CFG_DEV2_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
11022 | #define BIF_CFG_DEV2_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
11023 | #define BIF_CFG_DEV2_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
11024 | #define BIF_CFG_DEV2_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
11025 | #define BIF_CFG_DEV2_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
11026 | //BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_CAP |
11027 | #define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
11028 | #define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
11029 | #define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
11030 | #define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
11031 | //BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_STATUS |
11032 | #define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
11033 | #define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
11034 | #define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
11035 | #define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
11036 | //BIF_CFG_DEV2_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST |
11037 | #define BIF_CFG_DEV2_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
11038 | #define BIF_CFG_DEV2_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
11039 | #define BIF_CFG_DEV2_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
11040 | #define BIF_CFG_DEV2_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
11041 | #define BIF_CFG_DEV2_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
11042 | #define BIF_CFG_DEV2_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
11043 | //BIF_CFG_DEV2_EPF0_LINK_CAP_16GT |
11044 | #define BIF_CFG_DEV2_EPF0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
11045 | #define BIF_CFG_DEV2_EPF0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
11046 | //BIF_CFG_DEV2_EPF0_LINK_CNTL_16GT |
11047 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
11048 | #define BIF_CFG_DEV2_EPF0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
11049 | //BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT |
11050 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
11051 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
11052 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
11053 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
11054 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
11055 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
11056 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
11057 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
11058 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
11059 | #define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
11060 | //BIF_CFG_DEV2_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT |
11061 | #define BIF_CFG_DEV2_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
11062 | #define BIF_CFG_DEV2_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
11063 | //BIF_CFG_DEV2_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT |
11064 | #define BIF_CFG_DEV2_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
11065 | #define BIF_CFG_DEV2_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
11066 | //BIF_CFG_DEV2_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT |
11067 | #define BIF_CFG_DEV2_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
11068 | #define BIF_CFG_DEV2_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
11069 | //BIF_CFG_DEV2_EPF0_LANE_0_EQUALIZATION_CNTL_16GT |
11070 | #define BIF_CFG_DEV2_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11071 | #define BIF_CFG_DEV2_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
11072 | #define BIF_CFG_DEV2_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
11073 | #define BIF_CFG_DEV2_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
11074 | //BIF_CFG_DEV2_EPF0_LANE_1_EQUALIZATION_CNTL_16GT |
11075 | #define BIF_CFG_DEV2_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11076 | #define BIF_CFG_DEV2_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
11077 | #define BIF_CFG_DEV2_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
11078 | #define BIF_CFG_DEV2_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
11079 | //BIF_CFG_DEV2_EPF0_LANE_2_EQUALIZATION_CNTL_16GT |
11080 | #define BIF_CFG_DEV2_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11081 | #define BIF_CFG_DEV2_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
11082 | #define BIF_CFG_DEV2_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
11083 | #define BIF_CFG_DEV2_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
11084 | //BIF_CFG_DEV2_EPF0_LANE_3_EQUALIZATION_CNTL_16GT |
11085 | #define BIF_CFG_DEV2_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11086 | #define BIF_CFG_DEV2_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
11087 | #define BIF_CFG_DEV2_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
11088 | #define BIF_CFG_DEV2_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
11089 | //BIF_CFG_DEV2_EPF0_LANE_4_EQUALIZATION_CNTL_16GT |
11090 | #define BIF_CFG_DEV2_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11091 | #define BIF_CFG_DEV2_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
11092 | #define BIF_CFG_DEV2_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
11093 | #define BIF_CFG_DEV2_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
11094 | //BIF_CFG_DEV2_EPF0_LANE_5_EQUALIZATION_CNTL_16GT |
11095 | #define BIF_CFG_DEV2_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11096 | #define BIF_CFG_DEV2_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
11097 | #define BIF_CFG_DEV2_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
11098 | #define BIF_CFG_DEV2_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
11099 | //BIF_CFG_DEV2_EPF0_LANE_6_EQUALIZATION_CNTL_16GT |
11100 | #define BIF_CFG_DEV2_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11101 | #define BIF_CFG_DEV2_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
11102 | #define BIF_CFG_DEV2_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
11103 | #define BIF_CFG_DEV2_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
11104 | //BIF_CFG_DEV2_EPF0_LANE_7_EQUALIZATION_CNTL_16GT |
11105 | #define BIF_CFG_DEV2_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11106 | #define BIF_CFG_DEV2_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
11107 | #define BIF_CFG_DEV2_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
11108 | #define BIF_CFG_DEV2_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
11109 | //BIF_CFG_DEV2_EPF0_LANE_8_EQUALIZATION_CNTL_16GT |
11110 | #define BIF_CFG_DEV2_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11111 | #define BIF_CFG_DEV2_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
11112 | #define BIF_CFG_DEV2_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
11113 | #define BIF_CFG_DEV2_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
11114 | //BIF_CFG_DEV2_EPF0_LANE_9_EQUALIZATION_CNTL_16GT |
11115 | #define BIF_CFG_DEV2_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11116 | #define BIF_CFG_DEV2_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
11117 | #define BIF_CFG_DEV2_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
11118 | #define BIF_CFG_DEV2_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
11119 | //BIF_CFG_DEV2_EPF0_LANE_10_EQUALIZATION_CNTL_16GT |
11120 | #define BIF_CFG_DEV2_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11121 | #define BIF_CFG_DEV2_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
11122 | #define BIF_CFG_DEV2_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
11123 | #define BIF_CFG_DEV2_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
11124 | //BIF_CFG_DEV2_EPF0_LANE_11_EQUALIZATION_CNTL_16GT |
11125 | #define BIF_CFG_DEV2_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11126 | #define BIF_CFG_DEV2_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
11127 | #define BIF_CFG_DEV2_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
11128 | #define BIF_CFG_DEV2_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
11129 | //BIF_CFG_DEV2_EPF0_LANE_12_EQUALIZATION_CNTL_16GT |
11130 | #define BIF_CFG_DEV2_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11131 | #define BIF_CFG_DEV2_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
11132 | #define BIF_CFG_DEV2_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
11133 | #define BIF_CFG_DEV2_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
11134 | //BIF_CFG_DEV2_EPF0_LANE_13_EQUALIZATION_CNTL_16GT |
11135 | #define BIF_CFG_DEV2_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11136 | #define BIF_CFG_DEV2_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
11137 | #define BIF_CFG_DEV2_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
11138 | #define BIF_CFG_DEV2_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
11139 | //BIF_CFG_DEV2_EPF0_LANE_14_EQUALIZATION_CNTL_16GT |
11140 | #define BIF_CFG_DEV2_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11141 | #define BIF_CFG_DEV2_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
11142 | #define BIF_CFG_DEV2_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
11143 | #define BIF_CFG_DEV2_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
11144 | //BIF_CFG_DEV2_EPF0_LANE_15_EQUALIZATION_CNTL_16GT |
11145 | #define BIF_CFG_DEV2_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
11146 | #define BIF_CFG_DEV2_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
11147 | #define BIF_CFG_DEV2_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
11148 | #define BIF_CFG_DEV2_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
11149 | //BIF_CFG_DEV2_EPF0_PCIE_MARGINING_ENH_CAP_LIST |
11150 | #define BIF_CFG_DEV2_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
11151 | #define BIF_CFG_DEV2_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
11152 | #define BIF_CFG_DEV2_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
11153 | #define BIF_CFG_DEV2_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
11154 | #define BIF_CFG_DEV2_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
11155 | #define BIF_CFG_DEV2_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
11156 | //BIF_CFG_DEV2_EPF0_MARGINING_PORT_CAP |
11157 | #define BIF_CFG_DEV2_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
11158 | #define BIF_CFG_DEV2_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
11159 | //BIF_CFG_DEV2_EPF0_MARGINING_PORT_STATUS |
11160 | #define BIF_CFG_DEV2_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
11161 | #define BIF_CFG_DEV2_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
11162 | #define BIF_CFG_DEV2_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
11163 | #define BIF_CFG_DEV2_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
11164 | //BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL |
11165 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
11166 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
11167 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
11168 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
11169 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
11170 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
11171 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
11172 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
11173 | //BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS |
11174 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11175 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11176 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
11177 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11178 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11179 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
11180 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
11181 | #define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11182 | //BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL |
11183 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
11184 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
11185 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
11186 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
11187 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
11188 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
11189 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
11190 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
11191 | //BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS |
11192 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11193 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11194 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
11195 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11196 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11197 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
11198 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
11199 | #define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11200 | //BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL |
11201 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
11202 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
11203 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
11204 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
11205 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
11206 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
11207 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
11208 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
11209 | //BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS |
11210 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11211 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11212 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
11213 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11214 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11215 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
11216 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
11217 | #define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11218 | //BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL |
11219 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
11220 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
11221 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
11222 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
11223 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
11224 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
11225 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
11226 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
11227 | //BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS |
11228 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11229 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11230 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
11231 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11232 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11233 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
11234 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
11235 | #define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11236 | //BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL |
11237 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
11238 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
11239 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
11240 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
11241 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
11242 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
11243 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
11244 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
11245 | //BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS |
11246 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11247 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11248 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
11249 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11250 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11251 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
11252 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
11253 | #define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11254 | //BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL |
11255 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
11256 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
11257 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
11258 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
11259 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
11260 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
11261 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
11262 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
11263 | //BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS |
11264 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11265 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11266 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
11267 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11268 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11269 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
11270 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
11271 | #define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11272 | //BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL |
11273 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
11274 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
11275 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
11276 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
11277 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
11278 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
11279 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
11280 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
11281 | //BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS |
11282 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11283 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11284 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
11285 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11286 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11287 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
11288 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
11289 | #define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11290 | //BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL |
11291 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
11292 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
11293 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
11294 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
11295 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
11296 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
11297 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
11298 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
11299 | //BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS |
11300 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11301 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11302 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
11303 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11304 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11305 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
11306 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
11307 | #define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11308 | //BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL |
11309 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
11310 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
11311 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
11312 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
11313 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
11314 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
11315 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
11316 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
11317 | //BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS |
11318 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11319 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11320 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
11321 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11322 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11323 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
11324 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
11325 | #define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11326 | //BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL |
11327 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
11328 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
11329 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
11330 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
11331 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
11332 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
11333 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
11334 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
11335 | //BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS |
11336 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11337 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11338 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
11339 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11340 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11341 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
11342 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
11343 | #define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11344 | //BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL |
11345 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
11346 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
11347 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
11348 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
11349 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
11350 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
11351 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
11352 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
11353 | //BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS |
11354 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11355 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11356 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
11357 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11358 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11359 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
11360 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
11361 | #define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11362 | //BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL |
11363 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
11364 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
11365 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
11366 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
11367 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
11368 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
11369 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
11370 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
11371 | //BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS |
11372 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11373 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11374 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
11375 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11376 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11377 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
11378 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
11379 | #define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11380 | //BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL |
11381 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
11382 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
11383 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
11384 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
11385 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
11386 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
11387 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
11388 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
11389 | //BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS |
11390 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11391 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11392 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
11393 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11394 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11395 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
11396 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
11397 | #define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11398 | //BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL |
11399 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
11400 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
11401 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
11402 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
11403 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
11404 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
11405 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
11406 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
11407 | //BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS |
11408 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11409 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11410 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
11411 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11412 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11413 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
11414 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
11415 | #define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11416 | //BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL |
11417 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
11418 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
11419 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
11420 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
11421 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
11422 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
11423 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
11424 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
11425 | //BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS |
11426 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11427 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11428 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
11429 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11430 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11431 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
11432 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
11433 | #define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11434 | //BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL |
11435 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
11436 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
11437 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
11438 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
11439 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
11440 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
11441 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
11442 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
11443 | //BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS |
11444 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
11445 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
11446 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
11447 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
11448 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
11449 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
11450 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
11451 | #define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
11452 | //BIF_CFG_DEV2_EPF0_PCIE_RTR_ENH_CAP_LIST |
11453 | #define BIF_CFG_DEV2_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
11454 | #define BIF_CFG_DEV2_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
11455 | #define BIF_CFG_DEV2_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
11456 | #define BIF_CFG_DEV2_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
11457 | #define BIF_CFG_DEV2_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
11458 | #define BIF_CFG_DEV2_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
11459 | //BIF_CFG_DEV2_EPF0_RTR_DATA1 |
11460 | #define BIF_CFG_DEV2_EPF0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
11461 | #define BIF_CFG_DEV2_EPF0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
11462 | #define BIF_CFG_DEV2_EPF0_RTR_DATA1__VALID__SHIFT 0x1f |
11463 | #define BIF_CFG_DEV2_EPF0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
11464 | #define BIF_CFG_DEV2_EPF0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
11465 | #define BIF_CFG_DEV2_EPF0_RTR_DATA1__VALID_MASK 0x80000000L |
11466 | //BIF_CFG_DEV2_EPF0_RTR_DATA2 |
11467 | #define BIF_CFG_DEV2_EPF0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
11468 | #define BIF_CFG_DEV2_EPF0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
11469 | #define BIF_CFG_DEV2_EPF0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
11470 | #define BIF_CFG_DEV2_EPF0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
11471 | |
11472 | |
11473 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp |
11474 | //BIF_CFG_DEV0_EPF4_VENDOR_ID |
11475 | #define BIF_CFG_DEV0_EPF4_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
11476 | #define BIF_CFG_DEV0_EPF4_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
11477 | //BIF_CFG_DEV0_EPF4_DEVICE_ID |
11478 | #define BIF_CFG_DEV0_EPF4_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
11479 | #define BIF_CFG_DEV0_EPF4_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
11480 | //BIF_CFG_DEV0_EPF4_COMMAND |
11481 | #define BIF_CFG_DEV0_EPF4_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
11482 | #define BIF_CFG_DEV0_EPF4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
11483 | #define BIF_CFG_DEV0_EPF4_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
11484 | #define BIF_CFG_DEV0_EPF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
11485 | #define BIF_CFG_DEV0_EPF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
11486 | #define BIF_CFG_DEV0_EPF4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
11487 | #define BIF_CFG_DEV0_EPF4_COMMAND__AD_STEPPING__SHIFT 0x7 |
11488 | #define BIF_CFG_DEV0_EPF4_COMMAND__SERR_EN__SHIFT 0x8 |
11489 | #define BIF_CFG_DEV0_EPF4_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
11490 | #define BIF_CFG_DEV0_EPF4_COMMAND__INT_DIS__SHIFT 0xa |
11491 | #define BIF_CFG_DEV0_EPF4_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
11492 | #define BIF_CFG_DEV0_EPF4_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
11493 | #define BIF_CFG_DEV0_EPF4_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
11494 | #define BIF_CFG_DEV0_EPF4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
11495 | #define BIF_CFG_DEV0_EPF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
11496 | #define BIF_CFG_DEV0_EPF4_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
11497 | #define BIF_CFG_DEV0_EPF4_COMMAND__AD_STEPPING_MASK 0x0080L |
11498 | #define BIF_CFG_DEV0_EPF4_COMMAND__SERR_EN_MASK 0x0100L |
11499 | #define BIF_CFG_DEV0_EPF4_COMMAND__FAST_B2B_EN_MASK 0x0200L |
11500 | #define BIF_CFG_DEV0_EPF4_COMMAND__INT_DIS_MASK 0x0400L |
11501 | //BIF_CFG_DEV0_EPF4_STATUS |
11502 | #define BIF_CFG_DEV0_EPF4_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
11503 | #define BIF_CFG_DEV0_EPF4_STATUS__INT_STATUS__SHIFT 0x3 |
11504 | #define BIF_CFG_DEV0_EPF4_STATUS__CAP_LIST__SHIFT 0x4 |
11505 | #define BIF_CFG_DEV0_EPF4_STATUS__PCI_66_CAP__SHIFT 0x5 |
11506 | #define BIF_CFG_DEV0_EPF4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
11507 | #define BIF_CFG_DEV0_EPF4_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
11508 | #define BIF_CFG_DEV0_EPF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
11509 | #define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
11510 | #define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
11511 | #define BIF_CFG_DEV0_EPF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
11512 | #define BIF_CFG_DEV0_EPF4_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
11513 | #define BIF_CFG_DEV0_EPF4_STATUS__INT_STATUS_MASK 0x0008L |
11514 | #define BIF_CFG_DEV0_EPF4_STATUS__CAP_LIST_MASK 0x0010L |
11515 | #define BIF_CFG_DEV0_EPF4_STATUS__PCI_66_CAP_MASK 0x0020L |
11516 | #define BIF_CFG_DEV0_EPF4_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
11517 | #define BIF_CFG_DEV0_EPF4_STATUS__DEVSEL_TIMING_MASK 0x0600L |
11518 | #define BIF_CFG_DEV0_EPF4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
11519 | #define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
11520 | #define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
11521 | #define BIF_CFG_DEV0_EPF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
11522 | //BIF_CFG_DEV0_EPF4_REVISION_ID |
11523 | #define BIF_CFG_DEV0_EPF4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
11524 | #define BIF_CFG_DEV0_EPF4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
11525 | #define BIF_CFG_DEV0_EPF4_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
11526 | #define BIF_CFG_DEV0_EPF4_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
11527 | //BIF_CFG_DEV0_EPF4_PROG_INTERFACE |
11528 | #define BIF_CFG_DEV0_EPF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
11529 | #define BIF_CFG_DEV0_EPF4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
11530 | //BIF_CFG_DEV0_EPF4_SUB_CLASS |
11531 | #define BIF_CFG_DEV0_EPF4_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
11532 | #define BIF_CFG_DEV0_EPF4_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
11533 | //BIF_CFG_DEV0_EPF4_BASE_CLASS |
11534 | #define BIF_CFG_DEV0_EPF4_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
11535 | #define BIF_CFG_DEV0_EPF4_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
11536 | //BIF_CFG_DEV0_EPF4_CACHE_LINE |
11537 | #define BIF_CFG_DEV0_EPF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
11538 | #define BIF_CFG_DEV0_EPF4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
11539 | //BIF_CFG_DEV0_EPF4_LATENCY |
11540 | #define BIF_CFG_DEV0_EPF4_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
11541 | #define BIF_CFG_DEV0_EPF4_LATENCY__LATENCY_TIMER_MASK 0xFFL |
11542 | //BIF_CFG_DEV0_EPF4_HEADER |
11543 | #define 0x0 |
11544 | #define 0x7 |
11545 | #define 0x7FL |
11546 | #define 0x80L |
11547 | //BIF_CFG_DEV0_EPF4_BIST |
11548 | #define BIF_CFG_DEV0_EPF4_BIST__BIST_COMP__SHIFT 0x0 |
11549 | #define BIF_CFG_DEV0_EPF4_BIST__BIST_STRT__SHIFT 0x6 |
11550 | #define BIF_CFG_DEV0_EPF4_BIST__BIST_CAP__SHIFT 0x7 |
11551 | #define BIF_CFG_DEV0_EPF4_BIST__BIST_COMP_MASK 0x0FL |
11552 | #define BIF_CFG_DEV0_EPF4_BIST__BIST_STRT_MASK 0x40L |
11553 | #define BIF_CFG_DEV0_EPF4_BIST__BIST_CAP_MASK 0x80L |
11554 | //BIF_CFG_DEV0_EPF4_BASE_ADDR_1 |
11555 | #define BIF_CFG_DEV0_EPF4_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
11556 | #define BIF_CFG_DEV0_EPF4_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
11557 | //BIF_CFG_DEV0_EPF4_BASE_ADDR_2 |
11558 | #define BIF_CFG_DEV0_EPF4_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
11559 | #define BIF_CFG_DEV0_EPF4_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
11560 | //BIF_CFG_DEV0_EPF4_BASE_ADDR_3 |
11561 | #define BIF_CFG_DEV0_EPF4_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
11562 | #define BIF_CFG_DEV0_EPF4_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
11563 | //BIF_CFG_DEV0_EPF4_BASE_ADDR_4 |
11564 | #define BIF_CFG_DEV0_EPF4_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
11565 | #define BIF_CFG_DEV0_EPF4_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
11566 | //BIF_CFG_DEV0_EPF4_BASE_ADDR_5 |
11567 | #define BIF_CFG_DEV0_EPF4_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
11568 | #define BIF_CFG_DEV0_EPF4_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
11569 | //BIF_CFG_DEV0_EPF4_BASE_ADDR_6 |
11570 | #define BIF_CFG_DEV0_EPF4_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
11571 | #define BIF_CFG_DEV0_EPF4_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
11572 | //BIF_CFG_DEV0_EPF4_ADAPTER_ID |
11573 | #define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
11574 | #define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
11575 | #define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
11576 | #define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
11577 | //BIF_CFG_DEV0_EPF4_ROM_BASE_ADDR |
11578 | #define BIF_CFG_DEV0_EPF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
11579 | #define BIF_CFG_DEV0_EPF4_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
11580 | //BIF_CFG_DEV0_EPF4_CAP_PTR |
11581 | #define BIF_CFG_DEV0_EPF4_CAP_PTR__CAP_PTR__SHIFT 0x0 |
11582 | #define BIF_CFG_DEV0_EPF4_CAP_PTR__CAP_PTR_MASK 0xFFL |
11583 | //BIF_CFG_DEV0_EPF4_INTERRUPT_LINE |
11584 | #define BIF_CFG_DEV0_EPF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
11585 | #define BIF_CFG_DEV0_EPF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
11586 | //BIF_CFG_DEV0_EPF4_INTERRUPT_PIN |
11587 | #define BIF_CFG_DEV0_EPF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
11588 | #define BIF_CFG_DEV0_EPF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
11589 | //BIF_CFG_DEV0_EPF4_MIN_GRANT |
11590 | #define BIF_CFG_DEV0_EPF4_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
11591 | #define BIF_CFG_DEV0_EPF4_MIN_GRANT__MIN_GNT_MASK 0xFFL |
11592 | //BIF_CFG_DEV0_EPF4_MAX_LATENCY |
11593 | #define BIF_CFG_DEV0_EPF4_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
11594 | #define BIF_CFG_DEV0_EPF4_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
11595 | //BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST |
11596 | #define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
11597 | #define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
11598 | #define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
11599 | #define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
11600 | #define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
11601 | #define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
11602 | //BIF_CFG_DEV0_EPF4_ADAPTER_ID_W |
11603 | #define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
11604 | #define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
11605 | #define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
11606 | #define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
11607 | //BIF_CFG_DEV0_EPF4_PMI_CAP_LIST |
11608 | #define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
11609 | #define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
11610 | #define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
11611 | #define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
11612 | //BIF_CFG_DEV0_EPF4_PMI_CAP |
11613 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__VERSION__SHIFT 0x0 |
11614 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
11615 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
11616 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
11617 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
11618 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
11619 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
11620 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
11621 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__VERSION_MASK 0x0007L |
11622 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_CLOCK_MASK 0x0008L |
11623 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
11624 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
11625 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
11626 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
11627 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
11628 | #define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
11629 | //BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL |
11630 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
11631 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
11632 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
11633 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
11634 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
11635 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
11636 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
11637 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
11638 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
11639 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
11640 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
11641 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
11642 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
11643 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
11644 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
11645 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
11646 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
11647 | #define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
11648 | //BIF_CFG_DEV0_EPF4_SBRN |
11649 | #define BIF_CFG_DEV0_EPF4_SBRN__SBRN__SHIFT 0x0 |
11650 | #define BIF_CFG_DEV0_EPF4_SBRN__SBRN_MASK 0xFFL |
11651 | //BIF_CFG_DEV0_EPF4_FLADJ |
11652 | #define BIF_CFG_DEV0_EPF4_FLADJ__FLADJ__SHIFT 0x0 |
11653 | #define BIF_CFG_DEV0_EPF4_FLADJ__NFC__SHIFT 0x6 |
11654 | #define BIF_CFG_DEV0_EPF4_FLADJ__FLADJ_MASK 0x3FL |
11655 | #define BIF_CFG_DEV0_EPF4_FLADJ__NFC_MASK 0x40L |
11656 | //BIF_CFG_DEV0_EPF4_DBESL_DBESLD |
11657 | #define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESL__SHIFT 0x0 |
11658 | #define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
11659 | #define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESL_MASK 0x0FL |
11660 | #define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESLD_MASK 0xF0L |
11661 | //BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST |
11662 | #define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
11663 | #define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
11664 | #define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
11665 | #define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
11666 | //BIF_CFG_DEV0_EPF4_PCIE_CAP |
11667 | #define BIF_CFG_DEV0_EPF4_PCIE_CAP__VERSION__SHIFT 0x0 |
11668 | #define BIF_CFG_DEV0_EPF4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
11669 | #define BIF_CFG_DEV0_EPF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
11670 | #define BIF_CFG_DEV0_EPF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
11671 | #define BIF_CFG_DEV0_EPF4_PCIE_CAP__VERSION_MASK 0x000FL |
11672 | #define BIF_CFG_DEV0_EPF4_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
11673 | #define BIF_CFG_DEV0_EPF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
11674 | #define BIF_CFG_DEV0_EPF4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
11675 | //BIF_CFG_DEV0_EPF4_DEVICE_CAP |
11676 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
11677 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
11678 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
11679 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
11680 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
11681 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
11682 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
11683 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
11684 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
11685 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
11686 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
11687 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
11688 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
11689 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
11690 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
11691 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
11692 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
11693 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
11694 | //BIF_CFG_DEV0_EPF4_DEVICE_CNTL |
11695 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
11696 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
11697 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
11698 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
11699 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
11700 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
11701 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
11702 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
11703 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
11704 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
11705 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
11706 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
11707 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
11708 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
11709 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
11710 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
11711 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
11712 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
11713 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
11714 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
11715 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
11716 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
11717 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
11718 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
11719 | //BIF_CFG_DEV0_EPF4_DEVICE_STATUS |
11720 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
11721 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
11722 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
11723 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
11724 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
11725 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
11726 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
11727 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
11728 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
11729 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
11730 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
11731 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
11732 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
11733 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
11734 | //BIF_CFG_DEV0_EPF4_LINK_CAP |
11735 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
11736 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
11737 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
11738 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
11739 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
11740 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
11741 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
11742 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
11743 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
11744 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
11745 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
11746 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
11747 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
11748 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
11749 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
11750 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
11751 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
11752 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
11753 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
11754 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
11755 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
11756 | #define BIF_CFG_DEV0_EPF4_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
11757 | //BIF_CFG_DEV0_EPF4_LINK_CNTL |
11758 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
11759 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
11760 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
11761 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
11762 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
11763 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
11764 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
11765 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
11766 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
11767 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
11768 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
11769 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
11770 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
11771 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
11772 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
11773 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_DIS_MASK 0x0010L |
11774 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
11775 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
11776 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
11777 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
11778 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
11779 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
11780 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
11781 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
11782 | //BIF_CFG_DEV0_EPF4_LINK_STATUS |
11783 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
11784 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
11785 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
11786 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
11787 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
11788 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
11789 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
11790 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
11791 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
11792 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
11793 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
11794 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
11795 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
11796 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
11797 | //BIF_CFG_DEV0_EPF4_DEVICE_CAP2 |
11798 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
11799 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
11800 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
11801 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
11802 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
11803 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
11804 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
11805 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
11806 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
11807 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
11808 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
11809 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
11810 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
11811 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
11812 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
11813 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
11814 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
11815 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
11816 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
11817 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
11818 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
11819 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
11820 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
11821 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
11822 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
11823 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
11824 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
11825 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
11826 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
11827 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
11828 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
11829 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
11830 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
11831 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
11832 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
11833 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
11834 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
11835 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
11836 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
11837 | #define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
11838 | //BIF_CFG_DEV0_EPF4_DEVICE_CNTL2 |
11839 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
11840 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
11841 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
11842 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
11843 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
11844 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
11845 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
11846 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
11847 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
11848 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
11849 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
11850 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
11851 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
11852 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
11853 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
11854 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
11855 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
11856 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
11857 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
11858 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
11859 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
11860 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
11861 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
11862 | #define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
11863 | //BIF_CFG_DEV0_EPF4_DEVICE_STATUS2 |
11864 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
11865 | #define BIF_CFG_DEV0_EPF4_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
11866 | //BIF_CFG_DEV0_EPF4_LINK_CAP2 |
11867 | #define BIF_CFG_DEV0_EPF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
11868 | #define BIF_CFG_DEV0_EPF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
11869 | #define BIF_CFG_DEV0_EPF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
11870 | #define BIF_CFG_DEV0_EPF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
11871 | #define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
11872 | #define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
11873 | #define BIF_CFG_DEV0_EPF4_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
11874 | #define BIF_CFG_DEV0_EPF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
11875 | #define BIF_CFG_DEV0_EPF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
11876 | #define BIF_CFG_DEV0_EPF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
11877 | #define BIF_CFG_DEV0_EPF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
11878 | #define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
11879 | #define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
11880 | #define BIF_CFG_DEV0_EPF4_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
11881 | //BIF_CFG_DEV0_EPF4_LINK_CNTL2 |
11882 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
11883 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
11884 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
11885 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
11886 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
11887 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
11888 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
11889 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
11890 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
11891 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
11892 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
11893 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
11894 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
11895 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
11896 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
11897 | #define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
11898 | //BIF_CFG_DEV0_EPF4_LINK_STATUS2 |
11899 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
11900 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
11901 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
11902 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
11903 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
11904 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
11905 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
11906 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
11907 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
11908 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
11909 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
11910 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
11911 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
11912 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
11913 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
11914 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
11915 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
11916 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
11917 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
11918 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
11919 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
11920 | #define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
11921 | //BIF_CFG_DEV0_EPF4_MSI_CAP_LIST |
11922 | #define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
11923 | #define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
11924 | #define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
11925 | #define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
11926 | //BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL |
11927 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
11928 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
11929 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
11930 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
11931 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
11932 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
11933 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
11934 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
11935 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
11936 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
11937 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
11938 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
11939 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
11940 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
11941 | //BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_LO |
11942 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
11943 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
11944 | //BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_HI |
11945 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
11946 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
11947 | //BIF_CFG_DEV0_EPF4_MSI_MSG_DATA |
11948 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
11949 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
11950 | //BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA |
11951 | #define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
11952 | #define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
11953 | //BIF_CFG_DEV0_EPF4_MSI_MASK |
11954 | #define BIF_CFG_DEV0_EPF4_MSI_MASK__MSI_MASK__SHIFT 0x0 |
11955 | #define BIF_CFG_DEV0_EPF4_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
11956 | //BIF_CFG_DEV0_EPF4_MSI_MSG_DATA_64 |
11957 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
11958 | #define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
11959 | //BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA_64 |
11960 | #define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
11961 | #define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
11962 | //BIF_CFG_DEV0_EPF4_MSI_MASK_64 |
11963 | #define BIF_CFG_DEV0_EPF4_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
11964 | #define BIF_CFG_DEV0_EPF4_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
11965 | //BIF_CFG_DEV0_EPF4_MSI_PENDING |
11966 | #define BIF_CFG_DEV0_EPF4_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
11967 | #define BIF_CFG_DEV0_EPF4_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
11968 | //BIF_CFG_DEV0_EPF4_MSI_PENDING_64 |
11969 | #define BIF_CFG_DEV0_EPF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
11970 | #define BIF_CFG_DEV0_EPF4_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
11971 | //BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST |
11972 | #define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
11973 | #define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
11974 | #define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
11975 | #define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
11976 | //BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL |
11977 | #define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
11978 | #define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
11979 | #define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
11980 | #define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
11981 | #define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
11982 | #define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
11983 | //BIF_CFG_DEV0_EPF4_MSIX_TABLE |
11984 | #define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
11985 | #define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
11986 | #define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
11987 | #define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
11988 | //BIF_CFG_DEV0_EPF4_MSIX_PBA |
11989 | #define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
11990 | #define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
11991 | #define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
11992 | #define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
11993 | //BIF_CFG_DEV0_EPF4_SATA_CAP_0 |
11994 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
11995 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
11996 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
11997 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
11998 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
11999 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
12000 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
12001 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
12002 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
12003 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
12004 | //BIF_CFG_DEV0_EPF4_SATA_CAP_1 |
12005 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
12006 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
12007 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
12008 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
12009 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
12010 | #define BIF_CFG_DEV0_EPF4_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
12011 | //BIF_CFG_DEV0_EPF4_SATA_IDP_INDEX |
12012 | #define BIF_CFG_DEV0_EPF4_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
12013 | #define BIF_CFG_DEV0_EPF4_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
12014 | #define BIF_CFG_DEV0_EPF4_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
12015 | #define BIF_CFG_DEV0_EPF4_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
12016 | #define BIF_CFG_DEV0_EPF4_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
12017 | #define BIF_CFG_DEV0_EPF4_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
12018 | //BIF_CFG_DEV0_EPF4_SATA_IDP_DATA |
12019 | #define BIF_CFG_DEV0_EPF4_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
12020 | #define BIF_CFG_DEV0_EPF4_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
12021 | //BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
12022 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12023 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12024 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12025 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12026 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12027 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12028 | //BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR |
12029 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
12030 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
12031 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
12032 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
12033 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
12034 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
12035 | //BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC1 |
12036 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
12037 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
12038 | //BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC2 |
12039 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
12040 | #define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
12041 | //BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
12042 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12043 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12044 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12045 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12046 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12047 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12048 | //BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS |
12049 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
12050 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
12051 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
12052 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
12053 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
12054 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
12055 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
12056 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
12057 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
12058 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
12059 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
12060 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
12061 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
12062 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
12063 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
12064 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
12065 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
12066 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
12067 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
12068 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
12069 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
12070 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
12071 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
12072 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
12073 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
12074 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
12075 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
12076 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
12077 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
12078 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
12079 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
12080 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
12081 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
12082 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
12083 | //BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK |
12084 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
12085 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
12086 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
12087 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
12088 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
12089 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
12090 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
12091 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
12092 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
12093 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
12094 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
12095 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
12096 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
12097 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
12098 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
12099 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
12100 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
12101 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
12102 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
12103 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
12104 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
12105 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
12106 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
12107 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
12108 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
12109 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
12110 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
12111 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
12112 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
12113 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
12114 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
12115 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
12116 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
12117 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
12118 | //BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY |
12119 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
12120 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
12121 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
12122 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
12123 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
12124 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
12125 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
12126 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
12127 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
12128 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
12129 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
12130 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
12131 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
12132 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
12133 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
12134 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
12135 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
12136 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
12137 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
12138 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
12139 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
12140 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
12141 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
12142 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
12143 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
12144 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
12145 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
12146 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
12147 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
12148 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
12149 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
12150 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
12151 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
12152 | #define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
12153 | //BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS |
12154 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
12155 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
12156 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
12157 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
12158 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
12159 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
12160 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
12161 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
12162 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
12163 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
12164 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
12165 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
12166 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
12167 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
12168 | //BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK |
12169 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
12170 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
12171 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
12172 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
12173 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
12174 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
12175 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
12176 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
12177 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
12178 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
12179 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
12180 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
12181 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
12182 | #define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
12183 | //BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL |
12184 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
12185 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
12186 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
12187 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
12188 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
12189 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
12190 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
12191 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
12192 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
12193 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
12194 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
12195 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
12196 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
12197 | #define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
12198 | //BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG0 |
12199 | #define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
12200 | #define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
12201 | //BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG1 |
12202 | #define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
12203 | #define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
12204 | //BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG2 |
12205 | #define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
12206 | #define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
12207 | //BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG3 |
12208 | #define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
12209 | #define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
12210 | //BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG0 |
12211 | #define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
12212 | #define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
12213 | //BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG1 |
12214 | #define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
12215 | #define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
12216 | //BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG2 |
12217 | #define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
12218 | #define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
12219 | //BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG3 |
12220 | #define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
12221 | #define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
12222 | //BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST |
12223 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12224 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12225 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12226 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12227 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12228 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12229 | //BIF_CFG_DEV0_EPF4_PCIE_BAR1_CAP |
12230 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
12231 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
12232 | //BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL |
12233 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
12234 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
12235 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
12236 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
12237 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
12238 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
12239 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
12240 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
12241 | //BIF_CFG_DEV0_EPF4_PCIE_BAR2_CAP |
12242 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
12243 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
12244 | //BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL |
12245 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
12246 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
12247 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
12248 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
12249 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
12250 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
12251 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
12252 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
12253 | //BIF_CFG_DEV0_EPF4_PCIE_BAR3_CAP |
12254 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
12255 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
12256 | //BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL |
12257 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
12258 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
12259 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
12260 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
12261 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
12262 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
12263 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
12264 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
12265 | //BIF_CFG_DEV0_EPF4_PCIE_BAR4_CAP |
12266 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
12267 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
12268 | //BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL |
12269 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
12270 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
12271 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
12272 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
12273 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
12274 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
12275 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
12276 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
12277 | //BIF_CFG_DEV0_EPF4_PCIE_BAR5_CAP |
12278 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
12279 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
12280 | //BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL |
12281 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
12282 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
12283 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
12284 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
12285 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
12286 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
12287 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
12288 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
12289 | //BIF_CFG_DEV0_EPF4_PCIE_BAR6_CAP |
12290 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
12291 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
12292 | //BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL |
12293 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
12294 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
12295 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
12296 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
12297 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
12298 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
12299 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
12300 | #define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
12301 | //BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST |
12302 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12303 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12304 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12305 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12306 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12307 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12308 | //BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA_SELECT |
12309 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
12310 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
12311 | //BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA |
12312 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
12313 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
12314 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
12315 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
12316 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
12317 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
12318 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
12319 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
12320 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
12321 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
12322 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
12323 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
12324 | //BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_CAP |
12325 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
12326 | #define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
12327 | //BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST |
12328 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12329 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12330 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12331 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12332 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12333 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12334 | //BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP |
12335 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
12336 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
12337 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
12338 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
12339 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
12340 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
12341 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
12342 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
12343 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
12344 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
12345 | //BIF_CFG_DEV0_EPF4_PCIE_DPA_LATENCY_INDICATOR |
12346 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
12347 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
12348 | //BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS |
12349 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
12350 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
12351 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
12352 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
12353 | //BIF_CFG_DEV0_EPF4_PCIE_DPA_CNTL |
12354 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
12355 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
12356 | //BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
12357 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12358 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12359 | //BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
12360 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12361 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12362 | //BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
12363 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12364 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12365 | //BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
12366 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12367 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12368 | //BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
12369 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12370 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12371 | //BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
12372 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12373 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12374 | //BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
12375 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12376 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12377 | //BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
12378 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
12379 | #define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
12380 | //BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST |
12381 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12382 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12383 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12384 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12385 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12386 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12387 | //BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP |
12388 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
12389 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
12390 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
12391 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
12392 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
12393 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
12394 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
12395 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
12396 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
12397 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
12398 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
12399 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
12400 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
12401 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
12402 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
12403 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
12404 | //BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL |
12405 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
12406 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
12407 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
12408 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
12409 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
12410 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
12411 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
12412 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
12413 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
12414 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
12415 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
12416 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
12417 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
12418 | #define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
12419 | //BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST |
12420 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12421 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12422 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12423 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12424 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12425 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12426 | //BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP |
12427 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
12428 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
12429 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
12430 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
12431 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
12432 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
12433 | //BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL |
12434 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
12435 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
12436 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
12437 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
12438 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
12439 | #define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
12440 | //BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST |
12441 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12442 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12443 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12444 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12445 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12446 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12447 | //BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP |
12448 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
12449 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
12450 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
12451 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
12452 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
12453 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
12454 | //BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL |
12455 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
12456 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
12457 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
12458 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
12459 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
12460 | #define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
12461 | //BIF_CFG_DEV0_EPF4_PCIE_RTR_ENH_CAP_LIST |
12462 | #define BIF_CFG_DEV0_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
12463 | #define BIF_CFG_DEV0_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
12464 | #define BIF_CFG_DEV0_EPF4_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
12465 | #define BIF_CFG_DEV0_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
12466 | #define BIF_CFG_DEV0_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
12467 | #define BIF_CFG_DEV0_EPF4_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
12468 | //BIF_CFG_DEV0_EPF4_RTR_DATA1 |
12469 | #define BIF_CFG_DEV0_EPF4_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
12470 | #define BIF_CFG_DEV0_EPF4_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
12471 | #define BIF_CFG_DEV0_EPF4_RTR_DATA1__VALID__SHIFT 0x1f |
12472 | #define BIF_CFG_DEV0_EPF4_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
12473 | #define BIF_CFG_DEV0_EPF4_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
12474 | #define BIF_CFG_DEV0_EPF4_RTR_DATA1__VALID_MASK 0x80000000L |
12475 | //BIF_CFG_DEV0_EPF4_RTR_DATA2 |
12476 | #define BIF_CFG_DEV0_EPF4_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
12477 | #define BIF_CFG_DEV0_EPF4_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
12478 | #define BIF_CFG_DEV0_EPF4_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
12479 | #define BIF_CFG_DEV0_EPF4_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
12480 | |
12481 | |
12482 | // addressBlock: nbio_nbif0_bif_cfg_dev2_epf3_bifcfgdecp |
12483 | //BIF_CFG_DEV2_EPF3_VENDOR_ID |
12484 | #define BIF_CFG_DEV2_EPF3_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
12485 | #define BIF_CFG_DEV2_EPF3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
12486 | //BIF_CFG_DEV2_EPF3_DEVICE_ID |
12487 | #define BIF_CFG_DEV2_EPF3_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
12488 | #define BIF_CFG_DEV2_EPF3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
12489 | //BIF_CFG_DEV2_EPF3_COMMAND |
12490 | #define BIF_CFG_DEV2_EPF3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
12491 | #define BIF_CFG_DEV2_EPF3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
12492 | #define BIF_CFG_DEV2_EPF3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
12493 | #define BIF_CFG_DEV2_EPF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
12494 | #define BIF_CFG_DEV2_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
12495 | #define BIF_CFG_DEV2_EPF3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
12496 | #define BIF_CFG_DEV2_EPF3_COMMAND__AD_STEPPING__SHIFT 0x7 |
12497 | #define BIF_CFG_DEV2_EPF3_COMMAND__SERR_EN__SHIFT 0x8 |
12498 | #define BIF_CFG_DEV2_EPF3_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
12499 | #define BIF_CFG_DEV2_EPF3_COMMAND__INT_DIS__SHIFT 0xa |
12500 | #define BIF_CFG_DEV2_EPF3_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
12501 | #define BIF_CFG_DEV2_EPF3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
12502 | #define BIF_CFG_DEV2_EPF3_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
12503 | #define BIF_CFG_DEV2_EPF3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
12504 | #define BIF_CFG_DEV2_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
12505 | #define BIF_CFG_DEV2_EPF3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
12506 | #define BIF_CFG_DEV2_EPF3_COMMAND__AD_STEPPING_MASK 0x0080L |
12507 | #define BIF_CFG_DEV2_EPF3_COMMAND__SERR_EN_MASK 0x0100L |
12508 | #define BIF_CFG_DEV2_EPF3_COMMAND__FAST_B2B_EN_MASK 0x0200L |
12509 | #define BIF_CFG_DEV2_EPF3_COMMAND__INT_DIS_MASK 0x0400L |
12510 | //BIF_CFG_DEV2_EPF3_STATUS |
12511 | #define BIF_CFG_DEV2_EPF3_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
12512 | #define BIF_CFG_DEV2_EPF3_STATUS__INT_STATUS__SHIFT 0x3 |
12513 | #define BIF_CFG_DEV2_EPF3_STATUS__CAP_LIST__SHIFT 0x4 |
12514 | #define BIF_CFG_DEV2_EPF3_STATUS__PCI_66_CAP__SHIFT 0x5 |
12515 | #define BIF_CFG_DEV2_EPF3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
12516 | #define BIF_CFG_DEV2_EPF3_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
12517 | #define BIF_CFG_DEV2_EPF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
12518 | #define BIF_CFG_DEV2_EPF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
12519 | #define BIF_CFG_DEV2_EPF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
12520 | #define BIF_CFG_DEV2_EPF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
12521 | #define BIF_CFG_DEV2_EPF3_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
12522 | #define BIF_CFG_DEV2_EPF3_STATUS__INT_STATUS_MASK 0x0008L |
12523 | #define BIF_CFG_DEV2_EPF3_STATUS__CAP_LIST_MASK 0x0010L |
12524 | #define BIF_CFG_DEV2_EPF3_STATUS__PCI_66_CAP_MASK 0x0020L |
12525 | #define BIF_CFG_DEV2_EPF3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
12526 | #define BIF_CFG_DEV2_EPF3_STATUS__DEVSEL_TIMING_MASK 0x0600L |
12527 | #define BIF_CFG_DEV2_EPF3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
12528 | #define BIF_CFG_DEV2_EPF3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
12529 | #define BIF_CFG_DEV2_EPF3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
12530 | #define BIF_CFG_DEV2_EPF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
12531 | //BIF_CFG_DEV2_EPF3_REVISION_ID |
12532 | #define BIF_CFG_DEV2_EPF3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
12533 | #define BIF_CFG_DEV2_EPF3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
12534 | #define BIF_CFG_DEV2_EPF3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
12535 | #define BIF_CFG_DEV2_EPF3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
12536 | //BIF_CFG_DEV2_EPF3_PROG_INTERFACE |
12537 | #define BIF_CFG_DEV2_EPF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
12538 | #define BIF_CFG_DEV2_EPF3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
12539 | //BIF_CFG_DEV2_EPF3_SUB_CLASS |
12540 | #define BIF_CFG_DEV2_EPF3_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
12541 | #define BIF_CFG_DEV2_EPF3_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
12542 | //BIF_CFG_DEV2_EPF3_BASE_CLASS |
12543 | #define BIF_CFG_DEV2_EPF3_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
12544 | #define BIF_CFG_DEV2_EPF3_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
12545 | //BIF_CFG_DEV2_EPF3_CACHE_LINE |
12546 | #define BIF_CFG_DEV2_EPF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
12547 | #define BIF_CFG_DEV2_EPF3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
12548 | //BIF_CFG_DEV2_EPF3_LATENCY |
12549 | #define BIF_CFG_DEV2_EPF3_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
12550 | #define BIF_CFG_DEV2_EPF3_LATENCY__LATENCY_TIMER_MASK 0xFFL |
12551 | //BIF_CFG_DEV2_EPF3_HEADER |
12552 | #define 0x0 |
12553 | #define 0x7 |
12554 | #define 0x7FL |
12555 | #define 0x80L |
12556 | //BIF_CFG_DEV2_EPF3_BIST |
12557 | #define BIF_CFG_DEV2_EPF3_BIST__BIST_COMP__SHIFT 0x0 |
12558 | #define BIF_CFG_DEV2_EPF3_BIST__BIST_STRT__SHIFT 0x6 |
12559 | #define BIF_CFG_DEV2_EPF3_BIST__BIST_CAP__SHIFT 0x7 |
12560 | #define BIF_CFG_DEV2_EPF3_BIST__BIST_COMP_MASK 0x0FL |
12561 | #define BIF_CFG_DEV2_EPF3_BIST__BIST_STRT_MASK 0x40L |
12562 | #define BIF_CFG_DEV2_EPF3_BIST__BIST_CAP_MASK 0x80L |
12563 | //BIF_CFG_DEV2_EPF3_BASE_ADDR_1 |
12564 | #define BIF_CFG_DEV2_EPF3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
12565 | #define BIF_CFG_DEV2_EPF3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
12566 | //BIF_CFG_DEV2_EPF3_BASE_ADDR_2 |
12567 | #define BIF_CFG_DEV2_EPF3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
12568 | #define BIF_CFG_DEV2_EPF3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
12569 | //BIF_CFG_DEV2_EPF3_BASE_ADDR_3 |
12570 | #define BIF_CFG_DEV2_EPF3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
12571 | #define BIF_CFG_DEV2_EPF3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
12572 | //BIF_CFG_DEV2_EPF3_BASE_ADDR_4 |
12573 | #define BIF_CFG_DEV2_EPF3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
12574 | #define BIF_CFG_DEV2_EPF3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
12575 | //BIF_CFG_DEV2_EPF3_BASE_ADDR_5 |
12576 | #define BIF_CFG_DEV2_EPF3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
12577 | #define BIF_CFG_DEV2_EPF3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
12578 | //BIF_CFG_DEV2_EPF3_BASE_ADDR_6 |
12579 | #define BIF_CFG_DEV2_EPF3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
12580 | #define BIF_CFG_DEV2_EPF3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
12581 | //BIF_CFG_DEV2_EPF3_ADAPTER_ID |
12582 | #define BIF_CFG_DEV2_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
12583 | #define BIF_CFG_DEV2_EPF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
12584 | #define BIF_CFG_DEV2_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
12585 | #define BIF_CFG_DEV2_EPF3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
12586 | //BIF_CFG_DEV2_EPF3_ROM_BASE_ADDR |
12587 | #define BIF_CFG_DEV2_EPF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
12588 | #define BIF_CFG_DEV2_EPF3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
12589 | //BIF_CFG_DEV2_EPF3_CAP_PTR |
12590 | #define BIF_CFG_DEV2_EPF3_CAP_PTR__CAP_PTR__SHIFT 0x0 |
12591 | #define BIF_CFG_DEV2_EPF3_CAP_PTR__CAP_PTR_MASK 0xFFL |
12592 | //BIF_CFG_DEV2_EPF3_INTERRUPT_LINE |
12593 | #define BIF_CFG_DEV2_EPF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
12594 | #define BIF_CFG_DEV2_EPF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
12595 | //BIF_CFG_DEV2_EPF3_INTERRUPT_PIN |
12596 | #define BIF_CFG_DEV2_EPF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
12597 | #define BIF_CFG_DEV2_EPF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
12598 | //BIF_CFG_DEV2_EPF3_MIN_GRANT |
12599 | #define BIF_CFG_DEV2_EPF3_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
12600 | #define BIF_CFG_DEV2_EPF3_MIN_GRANT__MIN_GNT_MASK 0xFFL |
12601 | //BIF_CFG_DEV2_EPF3_MAX_LATENCY |
12602 | #define BIF_CFG_DEV2_EPF3_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
12603 | #define BIF_CFG_DEV2_EPF3_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
12604 | //BIF_CFG_DEV2_EPF3_VENDOR_CAP_LIST |
12605 | #define BIF_CFG_DEV2_EPF3_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
12606 | #define BIF_CFG_DEV2_EPF3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
12607 | #define BIF_CFG_DEV2_EPF3_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
12608 | #define BIF_CFG_DEV2_EPF3_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
12609 | #define BIF_CFG_DEV2_EPF3_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
12610 | #define BIF_CFG_DEV2_EPF3_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
12611 | //BIF_CFG_DEV2_EPF3_ADAPTER_ID_W |
12612 | #define BIF_CFG_DEV2_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
12613 | #define BIF_CFG_DEV2_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
12614 | #define BIF_CFG_DEV2_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
12615 | #define BIF_CFG_DEV2_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
12616 | //BIF_CFG_DEV2_EPF3_PMI_CAP_LIST |
12617 | #define BIF_CFG_DEV2_EPF3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
12618 | #define BIF_CFG_DEV2_EPF3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
12619 | #define BIF_CFG_DEV2_EPF3_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
12620 | #define BIF_CFG_DEV2_EPF3_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
12621 | //BIF_CFG_DEV2_EPF3_PMI_CAP |
12622 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__VERSION__SHIFT 0x0 |
12623 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
12624 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
12625 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
12626 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
12627 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
12628 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
12629 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
12630 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__VERSION_MASK 0x0007L |
12631 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__PME_CLOCK_MASK 0x0008L |
12632 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
12633 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
12634 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
12635 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
12636 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
12637 | #define BIF_CFG_DEV2_EPF3_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
12638 | //BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL |
12639 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
12640 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
12641 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
12642 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
12643 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
12644 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
12645 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
12646 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
12647 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
12648 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
12649 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
12650 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
12651 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
12652 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
12653 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
12654 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
12655 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
12656 | #define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
12657 | //BIF_CFG_DEV2_EPF3_SBRN |
12658 | #define BIF_CFG_DEV2_EPF3_SBRN__SBRN__SHIFT 0x0 |
12659 | #define BIF_CFG_DEV2_EPF3_SBRN__SBRN_MASK 0xFFL |
12660 | //BIF_CFG_DEV2_EPF3_FLADJ |
12661 | #define BIF_CFG_DEV2_EPF3_FLADJ__FLADJ__SHIFT 0x0 |
12662 | #define BIF_CFG_DEV2_EPF3_FLADJ__NFC__SHIFT 0x6 |
12663 | #define BIF_CFG_DEV2_EPF3_FLADJ__FLADJ_MASK 0x3FL |
12664 | #define BIF_CFG_DEV2_EPF3_FLADJ__NFC_MASK 0x40L |
12665 | //BIF_CFG_DEV2_EPF3_DBESL_DBESLD |
12666 | #define BIF_CFG_DEV2_EPF3_DBESL_DBESLD__DBESL__SHIFT 0x0 |
12667 | #define BIF_CFG_DEV2_EPF3_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
12668 | #define BIF_CFG_DEV2_EPF3_DBESL_DBESLD__DBESL_MASK 0x0FL |
12669 | #define BIF_CFG_DEV2_EPF3_DBESL_DBESLD__DBESLD_MASK 0xF0L |
12670 | //BIF_CFG_DEV2_EPF3_PCIE_CAP_LIST |
12671 | #define BIF_CFG_DEV2_EPF3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
12672 | #define BIF_CFG_DEV2_EPF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
12673 | #define BIF_CFG_DEV2_EPF3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
12674 | #define BIF_CFG_DEV2_EPF3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
12675 | //BIF_CFG_DEV2_EPF3_PCIE_CAP |
12676 | #define BIF_CFG_DEV2_EPF3_PCIE_CAP__VERSION__SHIFT 0x0 |
12677 | #define BIF_CFG_DEV2_EPF3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
12678 | #define BIF_CFG_DEV2_EPF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
12679 | #define BIF_CFG_DEV2_EPF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
12680 | #define BIF_CFG_DEV2_EPF3_PCIE_CAP__VERSION_MASK 0x000FL |
12681 | #define BIF_CFG_DEV2_EPF3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
12682 | #define BIF_CFG_DEV2_EPF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
12683 | #define BIF_CFG_DEV2_EPF3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
12684 | //BIF_CFG_DEV2_EPF3_DEVICE_CAP |
12685 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
12686 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
12687 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
12688 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
12689 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
12690 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
12691 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
12692 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
12693 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
12694 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
12695 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
12696 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
12697 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
12698 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
12699 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
12700 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
12701 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
12702 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
12703 | //BIF_CFG_DEV2_EPF3_DEVICE_CNTL |
12704 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
12705 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
12706 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
12707 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
12708 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
12709 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
12710 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
12711 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
12712 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
12713 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
12714 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
12715 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
12716 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
12717 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
12718 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
12719 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
12720 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
12721 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
12722 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
12723 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
12724 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
12725 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
12726 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
12727 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
12728 | //BIF_CFG_DEV2_EPF3_DEVICE_STATUS |
12729 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
12730 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
12731 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
12732 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
12733 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
12734 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
12735 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
12736 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
12737 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
12738 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
12739 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
12740 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
12741 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
12742 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
12743 | //BIF_CFG_DEV2_EPF3_LINK_CAP |
12744 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
12745 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
12746 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
12747 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
12748 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
12749 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
12750 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
12751 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
12752 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
12753 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
12754 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
12755 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
12756 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
12757 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
12758 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
12759 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
12760 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
12761 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
12762 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
12763 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
12764 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
12765 | #define BIF_CFG_DEV2_EPF3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
12766 | //BIF_CFG_DEV2_EPF3_LINK_CNTL |
12767 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
12768 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
12769 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
12770 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
12771 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
12772 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
12773 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
12774 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
12775 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
12776 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
12777 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
12778 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
12779 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
12780 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
12781 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
12782 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__LINK_DIS_MASK 0x0010L |
12783 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
12784 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
12785 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
12786 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
12787 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
12788 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
12789 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
12790 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
12791 | //BIF_CFG_DEV2_EPF3_LINK_STATUS |
12792 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
12793 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
12794 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
12795 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
12796 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
12797 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
12798 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
12799 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
12800 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
12801 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
12802 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
12803 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
12804 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
12805 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
12806 | //BIF_CFG_DEV2_EPF3_DEVICE_CAP2 |
12807 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
12808 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
12809 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
12810 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
12811 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
12812 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
12813 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
12814 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
12815 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
12816 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
12817 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
12818 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
12819 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
12820 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
12821 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
12822 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
12823 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
12824 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
12825 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
12826 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
12827 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
12828 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
12829 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
12830 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
12831 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
12832 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
12833 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
12834 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
12835 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
12836 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
12837 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
12838 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
12839 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
12840 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
12841 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
12842 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
12843 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
12844 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
12845 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
12846 | #define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
12847 | //BIF_CFG_DEV2_EPF3_DEVICE_CNTL2 |
12848 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
12849 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
12850 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
12851 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
12852 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
12853 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
12854 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
12855 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
12856 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
12857 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
12858 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
12859 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
12860 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
12861 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
12862 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
12863 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
12864 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
12865 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
12866 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
12867 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
12868 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
12869 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
12870 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
12871 | #define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
12872 | //BIF_CFG_DEV2_EPF3_DEVICE_STATUS2 |
12873 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
12874 | #define BIF_CFG_DEV2_EPF3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
12875 | //BIF_CFG_DEV2_EPF3_LINK_CAP2 |
12876 | #define BIF_CFG_DEV2_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
12877 | #define BIF_CFG_DEV2_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
12878 | #define BIF_CFG_DEV2_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
12879 | #define BIF_CFG_DEV2_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
12880 | #define BIF_CFG_DEV2_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
12881 | #define BIF_CFG_DEV2_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
12882 | #define BIF_CFG_DEV2_EPF3_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
12883 | #define BIF_CFG_DEV2_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
12884 | #define BIF_CFG_DEV2_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
12885 | #define BIF_CFG_DEV2_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
12886 | #define BIF_CFG_DEV2_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
12887 | #define BIF_CFG_DEV2_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
12888 | #define BIF_CFG_DEV2_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
12889 | #define BIF_CFG_DEV2_EPF3_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
12890 | //BIF_CFG_DEV2_EPF3_LINK_CNTL2 |
12891 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
12892 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
12893 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
12894 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
12895 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
12896 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
12897 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
12898 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
12899 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
12900 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
12901 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
12902 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
12903 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
12904 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
12905 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
12906 | #define BIF_CFG_DEV2_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
12907 | //BIF_CFG_DEV2_EPF3_LINK_STATUS2 |
12908 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
12909 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
12910 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
12911 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
12912 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
12913 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
12914 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
12915 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
12916 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
12917 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
12918 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
12919 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
12920 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
12921 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
12922 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
12923 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
12924 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
12925 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
12926 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
12927 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
12928 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
12929 | #define BIF_CFG_DEV2_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
12930 | //BIF_CFG_DEV2_EPF3_MSI_CAP_LIST |
12931 | #define BIF_CFG_DEV2_EPF3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
12932 | #define BIF_CFG_DEV2_EPF3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
12933 | #define BIF_CFG_DEV2_EPF3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
12934 | #define BIF_CFG_DEV2_EPF3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
12935 | //BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL |
12936 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
12937 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
12938 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
12939 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
12940 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
12941 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
12942 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
12943 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
12944 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
12945 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
12946 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
12947 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
12948 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
12949 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
12950 | //BIF_CFG_DEV2_EPF3_MSI_MSG_ADDR_LO |
12951 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
12952 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
12953 | //BIF_CFG_DEV2_EPF3_MSI_MSG_ADDR_HI |
12954 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
12955 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
12956 | //BIF_CFG_DEV2_EPF3_MSI_MSG_DATA |
12957 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
12958 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
12959 | //BIF_CFG_DEV2_EPF3_MSI_EXT_MSG_DATA |
12960 | #define BIF_CFG_DEV2_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
12961 | #define BIF_CFG_DEV2_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
12962 | //BIF_CFG_DEV2_EPF3_MSI_MASK |
12963 | #define BIF_CFG_DEV2_EPF3_MSI_MASK__MSI_MASK__SHIFT 0x0 |
12964 | #define BIF_CFG_DEV2_EPF3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
12965 | //BIF_CFG_DEV2_EPF3_MSI_MSG_DATA_64 |
12966 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
12967 | #define BIF_CFG_DEV2_EPF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
12968 | //BIF_CFG_DEV2_EPF3_MSI_EXT_MSG_DATA_64 |
12969 | #define BIF_CFG_DEV2_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
12970 | #define BIF_CFG_DEV2_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
12971 | //BIF_CFG_DEV2_EPF3_MSI_MASK_64 |
12972 | #define BIF_CFG_DEV2_EPF3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
12973 | #define BIF_CFG_DEV2_EPF3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
12974 | //BIF_CFG_DEV2_EPF3_MSI_PENDING |
12975 | #define BIF_CFG_DEV2_EPF3_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
12976 | #define BIF_CFG_DEV2_EPF3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
12977 | //BIF_CFG_DEV2_EPF3_MSI_PENDING_64 |
12978 | #define BIF_CFG_DEV2_EPF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
12979 | #define BIF_CFG_DEV2_EPF3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
12980 | //BIF_CFG_DEV2_EPF3_MSIX_CAP_LIST |
12981 | #define BIF_CFG_DEV2_EPF3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
12982 | #define BIF_CFG_DEV2_EPF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
12983 | #define BIF_CFG_DEV2_EPF3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
12984 | #define BIF_CFG_DEV2_EPF3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
12985 | //BIF_CFG_DEV2_EPF3_MSIX_MSG_CNTL |
12986 | #define BIF_CFG_DEV2_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
12987 | #define BIF_CFG_DEV2_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
12988 | #define BIF_CFG_DEV2_EPF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
12989 | #define BIF_CFG_DEV2_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
12990 | #define BIF_CFG_DEV2_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
12991 | #define BIF_CFG_DEV2_EPF3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
12992 | //BIF_CFG_DEV2_EPF3_MSIX_TABLE |
12993 | #define BIF_CFG_DEV2_EPF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
12994 | #define BIF_CFG_DEV2_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
12995 | #define BIF_CFG_DEV2_EPF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
12996 | #define BIF_CFG_DEV2_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
12997 | //BIF_CFG_DEV2_EPF3_MSIX_PBA |
12998 | #define BIF_CFG_DEV2_EPF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
12999 | #define BIF_CFG_DEV2_EPF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
13000 | #define BIF_CFG_DEV2_EPF3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
13001 | #define BIF_CFG_DEV2_EPF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
13002 | //BIF_CFG_DEV2_EPF3_SATA_CAP_0 |
13003 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
13004 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
13005 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
13006 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
13007 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
13008 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
13009 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
13010 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
13011 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
13012 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
13013 | //BIF_CFG_DEV2_EPF3_SATA_CAP_1 |
13014 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
13015 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
13016 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
13017 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
13018 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
13019 | #define BIF_CFG_DEV2_EPF3_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
13020 | //BIF_CFG_DEV2_EPF3_SATA_IDP_INDEX |
13021 | #define BIF_CFG_DEV2_EPF3_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
13022 | #define BIF_CFG_DEV2_EPF3_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
13023 | #define BIF_CFG_DEV2_EPF3_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
13024 | #define BIF_CFG_DEV2_EPF3_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
13025 | #define BIF_CFG_DEV2_EPF3_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
13026 | #define BIF_CFG_DEV2_EPF3_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
13027 | //BIF_CFG_DEV2_EPF3_SATA_IDP_DATA |
13028 | #define BIF_CFG_DEV2_EPF3_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
13029 | #define BIF_CFG_DEV2_EPF3_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
13030 | //BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
13031 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13032 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13033 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13034 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13035 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13036 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13037 | //BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_HDR |
13038 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
13039 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
13040 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
13041 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
13042 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
13043 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
13044 | //BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC1 |
13045 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
13046 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
13047 | //BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC2 |
13048 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
13049 | #define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
13050 | //BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
13051 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13052 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13053 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13054 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13055 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13056 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13057 | //BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS |
13058 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
13059 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
13060 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
13061 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
13062 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
13063 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
13064 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
13065 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
13066 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
13067 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
13068 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
13069 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
13070 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
13071 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
13072 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
13073 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
13074 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
13075 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
13076 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
13077 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
13078 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
13079 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
13080 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
13081 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
13082 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
13083 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
13084 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
13085 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
13086 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
13087 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
13088 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
13089 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
13090 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
13091 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
13092 | //BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK |
13093 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
13094 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
13095 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
13096 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
13097 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
13098 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
13099 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
13100 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
13101 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
13102 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
13103 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
13104 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
13105 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
13106 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
13107 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
13108 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
13109 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
13110 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
13111 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
13112 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
13113 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
13114 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
13115 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
13116 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
13117 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
13118 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
13119 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
13120 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
13121 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
13122 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
13123 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
13124 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
13125 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
13126 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
13127 | //BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY |
13128 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
13129 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
13130 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
13131 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
13132 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
13133 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
13134 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
13135 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
13136 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
13137 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
13138 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
13139 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
13140 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
13141 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
13142 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
13143 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
13144 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
13145 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
13146 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
13147 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
13148 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
13149 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
13150 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
13151 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
13152 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
13153 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
13154 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
13155 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
13156 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
13157 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
13158 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
13159 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
13160 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
13161 | #define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
13162 | //BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS |
13163 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
13164 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
13165 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
13166 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
13167 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
13168 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
13169 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
13170 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
13171 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
13172 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
13173 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
13174 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
13175 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
13176 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
13177 | //BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK |
13178 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
13179 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
13180 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
13181 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
13182 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
13183 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
13184 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
13185 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
13186 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
13187 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
13188 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
13189 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
13190 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
13191 | #define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
13192 | //BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL |
13193 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
13194 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
13195 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
13196 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
13197 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
13198 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
13199 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
13200 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
13201 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
13202 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
13203 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
13204 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
13205 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
13206 | #define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
13207 | //BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG0 |
13208 | #define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
13209 | #define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
13210 | //BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG1 |
13211 | #define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
13212 | #define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
13213 | //BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG2 |
13214 | #define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
13215 | #define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
13216 | //BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG3 |
13217 | #define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
13218 | #define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
13219 | //BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG0 |
13220 | #define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
13221 | #define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
13222 | //BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG1 |
13223 | #define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
13224 | #define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
13225 | //BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG2 |
13226 | #define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
13227 | #define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
13228 | //BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG3 |
13229 | #define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
13230 | #define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
13231 | //BIF_CFG_DEV2_EPF3_PCIE_BAR_ENH_CAP_LIST |
13232 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13233 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13234 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13235 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13236 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13237 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13238 | //BIF_CFG_DEV2_EPF3_PCIE_BAR1_CAP |
13239 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
13240 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
13241 | //BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL |
13242 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
13243 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
13244 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
13245 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
13246 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
13247 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
13248 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
13249 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
13250 | //BIF_CFG_DEV2_EPF3_PCIE_BAR2_CAP |
13251 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
13252 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
13253 | //BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL |
13254 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
13255 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
13256 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
13257 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
13258 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
13259 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
13260 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
13261 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
13262 | //BIF_CFG_DEV2_EPF3_PCIE_BAR3_CAP |
13263 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
13264 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
13265 | //BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL |
13266 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
13267 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
13268 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
13269 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
13270 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
13271 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
13272 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
13273 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
13274 | //BIF_CFG_DEV2_EPF3_PCIE_BAR4_CAP |
13275 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
13276 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
13277 | //BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL |
13278 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
13279 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
13280 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
13281 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
13282 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
13283 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
13284 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
13285 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
13286 | //BIF_CFG_DEV2_EPF3_PCIE_BAR5_CAP |
13287 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
13288 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
13289 | //BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL |
13290 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
13291 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
13292 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
13293 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
13294 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
13295 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
13296 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
13297 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
13298 | //BIF_CFG_DEV2_EPF3_PCIE_BAR6_CAP |
13299 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
13300 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
13301 | //BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL |
13302 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
13303 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
13304 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
13305 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
13306 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
13307 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
13308 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
13309 | #define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
13310 | //BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST |
13311 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13312 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13313 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13314 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13315 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13316 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13317 | //BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA_SELECT |
13318 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
13319 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
13320 | //BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA |
13321 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
13322 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
13323 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
13324 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
13325 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
13326 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
13327 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
13328 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
13329 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
13330 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
13331 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
13332 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
13333 | //BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_CAP |
13334 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
13335 | #define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
13336 | //BIF_CFG_DEV2_EPF3_PCIE_DPA_ENH_CAP_LIST |
13337 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13338 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13339 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13340 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13341 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13342 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13343 | //BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP |
13344 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
13345 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
13346 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
13347 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
13348 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
13349 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
13350 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
13351 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
13352 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
13353 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
13354 | //BIF_CFG_DEV2_EPF3_PCIE_DPA_LATENCY_INDICATOR |
13355 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
13356 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
13357 | //BIF_CFG_DEV2_EPF3_PCIE_DPA_STATUS |
13358 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
13359 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
13360 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
13361 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
13362 | //BIF_CFG_DEV2_EPF3_PCIE_DPA_CNTL |
13363 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
13364 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
13365 | //BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
13366 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
13367 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
13368 | //BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
13369 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
13370 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
13371 | //BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
13372 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
13373 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
13374 | //BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
13375 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
13376 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
13377 | //BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
13378 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
13379 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
13380 | //BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
13381 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
13382 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
13383 | //BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
13384 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
13385 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
13386 | //BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
13387 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
13388 | #define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
13389 | //BIF_CFG_DEV2_EPF3_PCIE_ACS_ENH_CAP_LIST |
13390 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13391 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13392 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13393 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13394 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13395 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13396 | //BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP |
13397 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
13398 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
13399 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
13400 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
13401 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
13402 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
13403 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
13404 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
13405 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
13406 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
13407 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
13408 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
13409 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
13410 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
13411 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
13412 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
13413 | //BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL |
13414 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
13415 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
13416 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
13417 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
13418 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
13419 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
13420 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
13421 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
13422 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
13423 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
13424 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
13425 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
13426 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
13427 | #define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
13428 | //BIF_CFG_DEV2_EPF3_PCIE_PASID_ENH_CAP_LIST |
13429 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13430 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13431 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13432 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13433 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13434 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13435 | //BIF_CFG_DEV2_EPF3_PCIE_PASID_CAP |
13436 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
13437 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
13438 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
13439 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
13440 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
13441 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
13442 | //BIF_CFG_DEV2_EPF3_PCIE_PASID_CNTL |
13443 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
13444 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
13445 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
13446 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
13447 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
13448 | #define BIF_CFG_DEV2_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
13449 | //BIF_CFG_DEV2_EPF3_PCIE_ARI_ENH_CAP_LIST |
13450 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13451 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13452 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13453 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13454 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13455 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13456 | //BIF_CFG_DEV2_EPF3_PCIE_ARI_CAP |
13457 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
13458 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
13459 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
13460 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
13461 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
13462 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
13463 | //BIF_CFG_DEV2_EPF3_PCIE_ARI_CNTL |
13464 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
13465 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
13466 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
13467 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
13468 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
13469 | #define BIF_CFG_DEV2_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
13470 | //BIF_CFG_DEV2_EPF3_PCIE_RTR_ENH_CAP_LIST |
13471 | #define BIF_CFG_DEV2_EPF3_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
13472 | #define BIF_CFG_DEV2_EPF3_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
13473 | #define BIF_CFG_DEV2_EPF3_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
13474 | #define BIF_CFG_DEV2_EPF3_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
13475 | #define BIF_CFG_DEV2_EPF3_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
13476 | #define BIF_CFG_DEV2_EPF3_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
13477 | //BIF_CFG_DEV2_EPF3_RTR_DATA1 |
13478 | #define BIF_CFG_DEV2_EPF3_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
13479 | #define BIF_CFG_DEV2_EPF3_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
13480 | #define BIF_CFG_DEV2_EPF3_RTR_DATA1__VALID__SHIFT 0x1f |
13481 | #define BIF_CFG_DEV2_EPF3_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
13482 | #define BIF_CFG_DEV2_EPF3_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
13483 | #define BIF_CFG_DEV2_EPF3_RTR_DATA1__VALID_MASK 0x80000000L |
13484 | //BIF_CFG_DEV2_EPF3_RTR_DATA2 |
13485 | #define BIF_CFG_DEV2_EPF3_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
13486 | #define BIF_CFG_DEV2_EPF3_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
13487 | #define BIF_CFG_DEV2_EPF3_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
13488 | #define BIF_CFG_DEV2_EPF3_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
13489 | |
13490 | |
13491 | // addressBlock: nbio_nbif0_bif_cfg_dev2_epf4_bifcfgdecp |
13492 | //BIF_CFG_DEV2_EPF4_VENDOR_ID |
13493 | #define BIF_CFG_DEV2_EPF4_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
13494 | #define BIF_CFG_DEV2_EPF4_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
13495 | //BIF_CFG_DEV2_EPF4_DEVICE_ID |
13496 | #define BIF_CFG_DEV2_EPF4_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
13497 | #define BIF_CFG_DEV2_EPF4_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
13498 | //BIF_CFG_DEV2_EPF4_COMMAND |
13499 | #define BIF_CFG_DEV2_EPF4_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
13500 | #define BIF_CFG_DEV2_EPF4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
13501 | #define BIF_CFG_DEV2_EPF4_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
13502 | #define BIF_CFG_DEV2_EPF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
13503 | #define BIF_CFG_DEV2_EPF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
13504 | #define BIF_CFG_DEV2_EPF4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
13505 | #define BIF_CFG_DEV2_EPF4_COMMAND__AD_STEPPING__SHIFT 0x7 |
13506 | #define BIF_CFG_DEV2_EPF4_COMMAND__SERR_EN__SHIFT 0x8 |
13507 | #define BIF_CFG_DEV2_EPF4_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
13508 | #define BIF_CFG_DEV2_EPF4_COMMAND__INT_DIS__SHIFT 0xa |
13509 | #define BIF_CFG_DEV2_EPF4_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
13510 | #define BIF_CFG_DEV2_EPF4_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
13511 | #define BIF_CFG_DEV2_EPF4_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
13512 | #define BIF_CFG_DEV2_EPF4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
13513 | #define BIF_CFG_DEV2_EPF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
13514 | #define BIF_CFG_DEV2_EPF4_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
13515 | #define BIF_CFG_DEV2_EPF4_COMMAND__AD_STEPPING_MASK 0x0080L |
13516 | #define BIF_CFG_DEV2_EPF4_COMMAND__SERR_EN_MASK 0x0100L |
13517 | #define BIF_CFG_DEV2_EPF4_COMMAND__FAST_B2B_EN_MASK 0x0200L |
13518 | #define BIF_CFG_DEV2_EPF4_COMMAND__INT_DIS_MASK 0x0400L |
13519 | //BIF_CFG_DEV2_EPF4_STATUS |
13520 | #define BIF_CFG_DEV2_EPF4_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
13521 | #define BIF_CFG_DEV2_EPF4_STATUS__INT_STATUS__SHIFT 0x3 |
13522 | #define BIF_CFG_DEV2_EPF4_STATUS__CAP_LIST__SHIFT 0x4 |
13523 | #define BIF_CFG_DEV2_EPF4_STATUS__PCI_66_CAP__SHIFT 0x5 |
13524 | #define BIF_CFG_DEV2_EPF4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
13525 | #define BIF_CFG_DEV2_EPF4_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
13526 | #define BIF_CFG_DEV2_EPF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
13527 | #define BIF_CFG_DEV2_EPF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
13528 | #define BIF_CFG_DEV2_EPF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
13529 | #define BIF_CFG_DEV2_EPF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
13530 | #define BIF_CFG_DEV2_EPF4_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
13531 | #define BIF_CFG_DEV2_EPF4_STATUS__INT_STATUS_MASK 0x0008L |
13532 | #define BIF_CFG_DEV2_EPF4_STATUS__CAP_LIST_MASK 0x0010L |
13533 | #define BIF_CFG_DEV2_EPF4_STATUS__PCI_66_CAP_MASK 0x0020L |
13534 | #define BIF_CFG_DEV2_EPF4_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
13535 | #define BIF_CFG_DEV2_EPF4_STATUS__DEVSEL_TIMING_MASK 0x0600L |
13536 | #define BIF_CFG_DEV2_EPF4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
13537 | #define BIF_CFG_DEV2_EPF4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
13538 | #define BIF_CFG_DEV2_EPF4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
13539 | #define BIF_CFG_DEV2_EPF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
13540 | //BIF_CFG_DEV2_EPF4_REVISION_ID |
13541 | #define BIF_CFG_DEV2_EPF4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
13542 | #define BIF_CFG_DEV2_EPF4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
13543 | #define BIF_CFG_DEV2_EPF4_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
13544 | #define BIF_CFG_DEV2_EPF4_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
13545 | //BIF_CFG_DEV2_EPF4_PROG_INTERFACE |
13546 | #define BIF_CFG_DEV2_EPF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
13547 | #define BIF_CFG_DEV2_EPF4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
13548 | //BIF_CFG_DEV2_EPF4_SUB_CLASS |
13549 | #define BIF_CFG_DEV2_EPF4_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
13550 | #define BIF_CFG_DEV2_EPF4_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
13551 | //BIF_CFG_DEV2_EPF4_BASE_CLASS |
13552 | #define BIF_CFG_DEV2_EPF4_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
13553 | #define BIF_CFG_DEV2_EPF4_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
13554 | //BIF_CFG_DEV2_EPF4_CACHE_LINE |
13555 | #define BIF_CFG_DEV2_EPF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
13556 | #define BIF_CFG_DEV2_EPF4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
13557 | //BIF_CFG_DEV2_EPF4_LATENCY |
13558 | #define BIF_CFG_DEV2_EPF4_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
13559 | #define BIF_CFG_DEV2_EPF4_LATENCY__LATENCY_TIMER_MASK 0xFFL |
13560 | //BIF_CFG_DEV2_EPF4_HEADER |
13561 | #define 0x0 |
13562 | #define 0x7 |
13563 | #define 0x7FL |
13564 | #define 0x80L |
13565 | //BIF_CFG_DEV2_EPF4_BIST |
13566 | #define BIF_CFG_DEV2_EPF4_BIST__BIST_COMP__SHIFT 0x0 |
13567 | #define BIF_CFG_DEV2_EPF4_BIST__BIST_STRT__SHIFT 0x6 |
13568 | #define BIF_CFG_DEV2_EPF4_BIST__BIST_CAP__SHIFT 0x7 |
13569 | #define BIF_CFG_DEV2_EPF4_BIST__BIST_COMP_MASK 0x0FL |
13570 | #define BIF_CFG_DEV2_EPF4_BIST__BIST_STRT_MASK 0x40L |
13571 | #define BIF_CFG_DEV2_EPF4_BIST__BIST_CAP_MASK 0x80L |
13572 | //BIF_CFG_DEV2_EPF4_BASE_ADDR_1 |
13573 | #define BIF_CFG_DEV2_EPF4_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
13574 | #define BIF_CFG_DEV2_EPF4_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
13575 | //BIF_CFG_DEV2_EPF4_BASE_ADDR_2 |
13576 | #define BIF_CFG_DEV2_EPF4_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
13577 | #define BIF_CFG_DEV2_EPF4_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
13578 | //BIF_CFG_DEV2_EPF4_BASE_ADDR_3 |
13579 | #define BIF_CFG_DEV2_EPF4_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
13580 | #define BIF_CFG_DEV2_EPF4_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
13581 | //BIF_CFG_DEV2_EPF4_BASE_ADDR_4 |
13582 | #define BIF_CFG_DEV2_EPF4_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
13583 | #define BIF_CFG_DEV2_EPF4_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
13584 | //BIF_CFG_DEV2_EPF4_BASE_ADDR_5 |
13585 | #define BIF_CFG_DEV2_EPF4_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
13586 | #define BIF_CFG_DEV2_EPF4_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
13587 | //BIF_CFG_DEV2_EPF4_BASE_ADDR_6 |
13588 | #define BIF_CFG_DEV2_EPF4_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
13589 | #define BIF_CFG_DEV2_EPF4_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
13590 | //BIF_CFG_DEV2_EPF4_ADAPTER_ID |
13591 | #define BIF_CFG_DEV2_EPF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
13592 | #define BIF_CFG_DEV2_EPF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
13593 | #define BIF_CFG_DEV2_EPF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
13594 | #define BIF_CFG_DEV2_EPF4_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
13595 | //BIF_CFG_DEV2_EPF4_ROM_BASE_ADDR |
13596 | #define BIF_CFG_DEV2_EPF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
13597 | #define BIF_CFG_DEV2_EPF4_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
13598 | //BIF_CFG_DEV2_EPF4_CAP_PTR |
13599 | #define BIF_CFG_DEV2_EPF4_CAP_PTR__CAP_PTR__SHIFT 0x0 |
13600 | #define BIF_CFG_DEV2_EPF4_CAP_PTR__CAP_PTR_MASK 0xFFL |
13601 | //BIF_CFG_DEV2_EPF4_INTERRUPT_LINE |
13602 | #define BIF_CFG_DEV2_EPF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
13603 | #define BIF_CFG_DEV2_EPF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
13604 | //BIF_CFG_DEV2_EPF4_INTERRUPT_PIN |
13605 | #define BIF_CFG_DEV2_EPF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
13606 | #define BIF_CFG_DEV2_EPF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
13607 | //BIF_CFG_DEV2_EPF4_MIN_GRANT |
13608 | #define BIF_CFG_DEV2_EPF4_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
13609 | #define BIF_CFG_DEV2_EPF4_MIN_GRANT__MIN_GNT_MASK 0xFFL |
13610 | //BIF_CFG_DEV2_EPF4_MAX_LATENCY |
13611 | #define BIF_CFG_DEV2_EPF4_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
13612 | #define BIF_CFG_DEV2_EPF4_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
13613 | //BIF_CFG_DEV2_EPF4_VENDOR_CAP_LIST |
13614 | #define BIF_CFG_DEV2_EPF4_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
13615 | #define BIF_CFG_DEV2_EPF4_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
13616 | #define BIF_CFG_DEV2_EPF4_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
13617 | #define BIF_CFG_DEV2_EPF4_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
13618 | #define BIF_CFG_DEV2_EPF4_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
13619 | #define BIF_CFG_DEV2_EPF4_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
13620 | //BIF_CFG_DEV2_EPF4_ADAPTER_ID_W |
13621 | #define BIF_CFG_DEV2_EPF4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
13622 | #define BIF_CFG_DEV2_EPF4_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
13623 | #define BIF_CFG_DEV2_EPF4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
13624 | #define BIF_CFG_DEV2_EPF4_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
13625 | //BIF_CFG_DEV2_EPF4_PMI_CAP_LIST |
13626 | #define BIF_CFG_DEV2_EPF4_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
13627 | #define BIF_CFG_DEV2_EPF4_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
13628 | #define BIF_CFG_DEV2_EPF4_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
13629 | #define BIF_CFG_DEV2_EPF4_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
13630 | //BIF_CFG_DEV2_EPF4_PMI_CAP |
13631 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__VERSION__SHIFT 0x0 |
13632 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
13633 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
13634 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
13635 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
13636 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
13637 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
13638 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
13639 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__VERSION_MASK 0x0007L |
13640 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__PME_CLOCK_MASK 0x0008L |
13641 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
13642 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
13643 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
13644 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
13645 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
13646 | #define BIF_CFG_DEV2_EPF4_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
13647 | //BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL |
13648 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
13649 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
13650 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
13651 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
13652 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
13653 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
13654 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
13655 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
13656 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
13657 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
13658 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
13659 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
13660 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
13661 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
13662 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
13663 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
13664 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
13665 | #define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
13666 | //BIF_CFG_DEV2_EPF4_SBRN |
13667 | #define BIF_CFG_DEV2_EPF4_SBRN__SBRN__SHIFT 0x0 |
13668 | #define BIF_CFG_DEV2_EPF4_SBRN__SBRN_MASK 0xFFL |
13669 | //BIF_CFG_DEV2_EPF4_FLADJ |
13670 | #define BIF_CFG_DEV2_EPF4_FLADJ__FLADJ__SHIFT 0x0 |
13671 | #define BIF_CFG_DEV2_EPF4_FLADJ__NFC__SHIFT 0x6 |
13672 | #define BIF_CFG_DEV2_EPF4_FLADJ__FLADJ_MASK 0x3FL |
13673 | #define BIF_CFG_DEV2_EPF4_FLADJ__NFC_MASK 0x40L |
13674 | //BIF_CFG_DEV2_EPF4_DBESL_DBESLD |
13675 | #define BIF_CFG_DEV2_EPF4_DBESL_DBESLD__DBESL__SHIFT 0x0 |
13676 | #define BIF_CFG_DEV2_EPF4_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
13677 | #define BIF_CFG_DEV2_EPF4_DBESL_DBESLD__DBESL_MASK 0x0FL |
13678 | #define BIF_CFG_DEV2_EPF4_DBESL_DBESLD__DBESLD_MASK 0xF0L |
13679 | //BIF_CFG_DEV2_EPF4_PCIE_CAP_LIST |
13680 | #define BIF_CFG_DEV2_EPF4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
13681 | #define BIF_CFG_DEV2_EPF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
13682 | #define BIF_CFG_DEV2_EPF4_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
13683 | #define BIF_CFG_DEV2_EPF4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
13684 | //BIF_CFG_DEV2_EPF4_PCIE_CAP |
13685 | #define BIF_CFG_DEV2_EPF4_PCIE_CAP__VERSION__SHIFT 0x0 |
13686 | #define BIF_CFG_DEV2_EPF4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
13687 | #define BIF_CFG_DEV2_EPF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
13688 | #define BIF_CFG_DEV2_EPF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
13689 | #define BIF_CFG_DEV2_EPF4_PCIE_CAP__VERSION_MASK 0x000FL |
13690 | #define BIF_CFG_DEV2_EPF4_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
13691 | #define BIF_CFG_DEV2_EPF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
13692 | #define BIF_CFG_DEV2_EPF4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
13693 | //BIF_CFG_DEV2_EPF4_DEVICE_CAP |
13694 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
13695 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
13696 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
13697 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
13698 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
13699 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
13700 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
13701 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
13702 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
13703 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
13704 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
13705 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
13706 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
13707 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
13708 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
13709 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
13710 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
13711 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
13712 | //BIF_CFG_DEV2_EPF4_DEVICE_CNTL |
13713 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
13714 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
13715 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
13716 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
13717 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
13718 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
13719 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
13720 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
13721 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
13722 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
13723 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
13724 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
13725 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
13726 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
13727 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
13728 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
13729 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
13730 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
13731 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
13732 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
13733 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
13734 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
13735 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
13736 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
13737 | //BIF_CFG_DEV2_EPF4_DEVICE_STATUS |
13738 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
13739 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
13740 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
13741 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
13742 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
13743 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
13744 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
13745 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
13746 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
13747 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
13748 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
13749 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
13750 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
13751 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
13752 | //BIF_CFG_DEV2_EPF4_LINK_CAP |
13753 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
13754 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
13755 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
13756 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
13757 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
13758 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
13759 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
13760 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
13761 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
13762 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
13763 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
13764 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
13765 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
13766 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
13767 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
13768 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
13769 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
13770 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
13771 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
13772 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
13773 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
13774 | #define BIF_CFG_DEV2_EPF4_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
13775 | //BIF_CFG_DEV2_EPF4_LINK_CNTL |
13776 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
13777 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
13778 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
13779 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
13780 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
13781 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
13782 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
13783 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
13784 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
13785 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
13786 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
13787 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
13788 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
13789 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
13790 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
13791 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__LINK_DIS_MASK 0x0010L |
13792 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
13793 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
13794 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
13795 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
13796 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
13797 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
13798 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
13799 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
13800 | //BIF_CFG_DEV2_EPF4_LINK_STATUS |
13801 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
13802 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
13803 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
13804 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
13805 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
13806 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
13807 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
13808 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
13809 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
13810 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
13811 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
13812 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
13813 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
13814 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
13815 | //BIF_CFG_DEV2_EPF4_DEVICE_CAP2 |
13816 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
13817 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
13818 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
13819 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
13820 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
13821 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
13822 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
13823 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
13824 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
13825 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
13826 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
13827 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
13828 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
13829 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
13830 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
13831 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
13832 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
13833 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
13834 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
13835 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
13836 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
13837 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
13838 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
13839 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
13840 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
13841 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
13842 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
13843 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
13844 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
13845 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
13846 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
13847 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
13848 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
13849 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
13850 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
13851 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
13852 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
13853 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
13854 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
13855 | #define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
13856 | //BIF_CFG_DEV2_EPF4_DEVICE_CNTL2 |
13857 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
13858 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
13859 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
13860 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
13861 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
13862 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
13863 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
13864 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
13865 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
13866 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
13867 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
13868 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
13869 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
13870 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
13871 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
13872 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
13873 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
13874 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
13875 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
13876 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
13877 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
13878 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
13879 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
13880 | #define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
13881 | //BIF_CFG_DEV2_EPF4_DEVICE_STATUS2 |
13882 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
13883 | #define BIF_CFG_DEV2_EPF4_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
13884 | //BIF_CFG_DEV2_EPF4_LINK_CAP2 |
13885 | #define BIF_CFG_DEV2_EPF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
13886 | #define BIF_CFG_DEV2_EPF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
13887 | #define BIF_CFG_DEV2_EPF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
13888 | #define BIF_CFG_DEV2_EPF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
13889 | #define BIF_CFG_DEV2_EPF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
13890 | #define BIF_CFG_DEV2_EPF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
13891 | #define BIF_CFG_DEV2_EPF4_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
13892 | #define BIF_CFG_DEV2_EPF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
13893 | #define BIF_CFG_DEV2_EPF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
13894 | #define BIF_CFG_DEV2_EPF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
13895 | #define BIF_CFG_DEV2_EPF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
13896 | #define BIF_CFG_DEV2_EPF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
13897 | #define BIF_CFG_DEV2_EPF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
13898 | #define BIF_CFG_DEV2_EPF4_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
13899 | //BIF_CFG_DEV2_EPF4_LINK_CNTL2 |
13900 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
13901 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
13902 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
13903 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
13904 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
13905 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
13906 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
13907 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
13908 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
13909 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
13910 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
13911 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
13912 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
13913 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
13914 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
13915 | #define BIF_CFG_DEV2_EPF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
13916 | //BIF_CFG_DEV2_EPF4_LINK_STATUS2 |
13917 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
13918 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
13919 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
13920 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
13921 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
13922 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
13923 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
13924 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
13925 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
13926 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
13927 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
13928 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
13929 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
13930 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
13931 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
13932 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
13933 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
13934 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
13935 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
13936 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
13937 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
13938 | #define BIF_CFG_DEV2_EPF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
13939 | //BIF_CFG_DEV2_EPF4_MSI_CAP_LIST |
13940 | #define BIF_CFG_DEV2_EPF4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
13941 | #define BIF_CFG_DEV2_EPF4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
13942 | #define BIF_CFG_DEV2_EPF4_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
13943 | #define BIF_CFG_DEV2_EPF4_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
13944 | //BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL |
13945 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
13946 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
13947 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
13948 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
13949 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
13950 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
13951 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
13952 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
13953 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
13954 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
13955 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
13956 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
13957 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
13958 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
13959 | //BIF_CFG_DEV2_EPF4_MSI_MSG_ADDR_LO |
13960 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
13961 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
13962 | //BIF_CFG_DEV2_EPF4_MSI_MSG_ADDR_HI |
13963 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
13964 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
13965 | //BIF_CFG_DEV2_EPF4_MSI_MSG_DATA |
13966 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
13967 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
13968 | //BIF_CFG_DEV2_EPF4_MSI_EXT_MSG_DATA |
13969 | #define BIF_CFG_DEV2_EPF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
13970 | #define BIF_CFG_DEV2_EPF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
13971 | //BIF_CFG_DEV2_EPF4_MSI_MASK |
13972 | #define BIF_CFG_DEV2_EPF4_MSI_MASK__MSI_MASK__SHIFT 0x0 |
13973 | #define BIF_CFG_DEV2_EPF4_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
13974 | //BIF_CFG_DEV2_EPF4_MSI_MSG_DATA_64 |
13975 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
13976 | #define BIF_CFG_DEV2_EPF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
13977 | //BIF_CFG_DEV2_EPF4_MSI_EXT_MSG_DATA_64 |
13978 | #define BIF_CFG_DEV2_EPF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
13979 | #define BIF_CFG_DEV2_EPF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
13980 | //BIF_CFG_DEV2_EPF4_MSI_MASK_64 |
13981 | #define BIF_CFG_DEV2_EPF4_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
13982 | #define BIF_CFG_DEV2_EPF4_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
13983 | //BIF_CFG_DEV2_EPF4_MSI_PENDING |
13984 | #define BIF_CFG_DEV2_EPF4_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
13985 | #define BIF_CFG_DEV2_EPF4_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
13986 | //BIF_CFG_DEV2_EPF4_MSI_PENDING_64 |
13987 | #define BIF_CFG_DEV2_EPF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
13988 | #define BIF_CFG_DEV2_EPF4_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
13989 | //BIF_CFG_DEV2_EPF4_MSIX_CAP_LIST |
13990 | #define BIF_CFG_DEV2_EPF4_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
13991 | #define BIF_CFG_DEV2_EPF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
13992 | #define BIF_CFG_DEV2_EPF4_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
13993 | #define BIF_CFG_DEV2_EPF4_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
13994 | //BIF_CFG_DEV2_EPF4_MSIX_MSG_CNTL |
13995 | #define BIF_CFG_DEV2_EPF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
13996 | #define BIF_CFG_DEV2_EPF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
13997 | #define BIF_CFG_DEV2_EPF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
13998 | #define BIF_CFG_DEV2_EPF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
13999 | #define BIF_CFG_DEV2_EPF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
14000 | #define BIF_CFG_DEV2_EPF4_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
14001 | //BIF_CFG_DEV2_EPF4_MSIX_TABLE |
14002 | #define BIF_CFG_DEV2_EPF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
14003 | #define BIF_CFG_DEV2_EPF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
14004 | #define BIF_CFG_DEV2_EPF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
14005 | #define BIF_CFG_DEV2_EPF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
14006 | //BIF_CFG_DEV2_EPF4_MSIX_PBA |
14007 | #define BIF_CFG_DEV2_EPF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
14008 | #define BIF_CFG_DEV2_EPF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
14009 | #define BIF_CFG_DEV2_EPF4_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
14010 | #define BIF_CFG_DEV2_EPF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
14011 | //BIF_CFG_DEV2_EPF4_SATA_CAP_0 |
14012 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
14013 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
14014 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
14015 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
14016 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
14017 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
14018 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
14019 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
14020 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
14021 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
14022 | //BIF_CFG_DEV2_EPF4_SATA_CAP_1 |
14023 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
14024 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
14025 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
14026 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
14027 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
14028 | #define BIF_CFG_DEV2_EPF4_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
14029 | //BIF_CFG_DEV2_EPF4_SATA_IDP_INDEX |
14030 | #define BIF_CFG_DEV2_EPF4_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
14031 | #define BIF_CFG_DEV2_EPF4_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
14032 | #define BIF_CFG_DEV2_EPF4_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
14033 | #define BIF_CFG_DEV2_EPF4_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
14034 | #define BIF_CFG_DEV2_EPF4_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
14035 | #define BIF_CFG_DEV2_EPF4_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
14036 | //BIF_CFG_DEV2_EPF4_SATA_IDP_DATA |
14037 | #define BIF_CFG_DEV2_EPF4_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
14038 | #define BIF_CFG_DEV2_EPF4_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
14039 | //BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
14040 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14041 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14042 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14043 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14044 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14045 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14046 | //BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_HDR |
14047 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
14048 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
14049 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
14050 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
14051 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
14052 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
14053 | //BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC1 |
14054 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
14055 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
14056 | //BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC2 |
14057 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
14058 | #define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
14059 | //BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
14060 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14061 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14062 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14063 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14064 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14065 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14066 | //BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS |
14067 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
14068 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
14069 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
14070 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
14071 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
14072 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
14073 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
14074 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
14075 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
14076 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
14077 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
14078 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
14079 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
14080 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
14081 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
14082 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
14083 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
14084 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
14085 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
14086 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
14087 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
14088 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
14089 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
14090 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
14091 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
14092 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
14093 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
14094 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
14095 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
14096 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
14097 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
14098 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
14099 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
14100 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
14101 | //BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK |
14102 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
14103 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
14104 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
14105 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
14106 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
14107 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
14108 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
14109 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
14110 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
14111 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
14112 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
14113 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
14114 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
14115 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
14116 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
14117 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
14118 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
14119 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
14120 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
14121 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
14122 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
14123 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
14124 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
14125 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
14126 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
14127 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
14128 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
14129 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
14130 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
14131 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
14132 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
14133 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
14134 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
14135 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
14136 | //BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY |
14137 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
14138 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
14139 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
14140 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
14141 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
14142 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
14143 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
14144 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
14145 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
14146 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
14147 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
14148 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
14149 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
14150 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
14151 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
14152 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
14153 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
14154 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
14155 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
14156 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
14157 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
14158 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
14159 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
14160 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
14161 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
14162 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
14163 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
14164 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
14165 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
14166 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
14167 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
14168 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
14169 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
14170 | #define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
14171 | //BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS |
14172 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
14173 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
14174 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
14175 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
14176 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
14177 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
14178 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
14179 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
14180 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
14181 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
14182 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
14183 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
14184 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
14185 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
14186 | //BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK |
14187 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
14188 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
14189 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
14190 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
14191 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
14192 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
14193 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
14194 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
14195 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
14196 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
14197 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
14198 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
14199 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
14200 | #define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
14201 | //BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL |
14202 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
14203 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
14204 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
14205 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
14206 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
14207 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
14208 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
14209 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
14210 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
14211 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
14212 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
14213 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
14214 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
14215 | #define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
14216 | //BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG0 |
14217 | #define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
14218 | #define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
14219 | //BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG1 |
14220 | #define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
14221 | #define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
14222 | //BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG2 |
14223 | #define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
14224 | #define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
14225 | //BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG3 |
14226 | #define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
14227 | #define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
14228 | //BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG0 |
14229 | #define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
14230 | #define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
14231 | //BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG1 |
14232 | #define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
14233 | #define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
14234 | //BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG2 |
14235 | #define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
14236 | #define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
14237 | //BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG3 |
14238 | #define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
14239 | #define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
14240 | //BIF_CFG_DEV2_EPF4_PCIE_BAR_ENH_CAP_LIST |
14241 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14242 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14243 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14244 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14245 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14246 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14247 | //BIF_CFG_DEV2_EPF4_PCIE_BAR1_CAP |
14248 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
14249 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
14250 | //BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL |
14251 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
14252 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
14253 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
14254 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
14255 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
14256 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
14257 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
14258 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
14259 | //BIF_CFG_DEV2_EPF4_PCIE_BAR2_CAP |
14260 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
14261 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
14262 | //BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL |
14263 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
14264 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
14265 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
14266 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
14267 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
14268 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
14269 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
14270 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
14271 | //BIF_CFG_DEV2_EPF4_PCIE_BAR3_CAP |
14272 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
14273 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
14274 | //BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL |
14275 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
14276 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
14277 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
14278 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
14279 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
14280 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
14281 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
14282 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
14283 | //BIF_CFG_DEV2_EPF4_PCIE_BAR4_CAP |
14284 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
14285 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
14286 | //BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL |
14287 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
14288 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
14289 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
14290 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
14291 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
14292 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
14293 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
14294 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
14295 | //BIF_CFG_DEV2_EPF4_PCIE_BAR5_CAP |
14296 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
14297 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
14298 | //BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL |
14299 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
14300 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
14301 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
14302 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
14303 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
14304 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
14305 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
14306 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
14307 | //BIF_CFG_DEV2_EPF4_PCIE_BAR6_CAP |
14308 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
14309 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
14310 | //BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL |
14311 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
14312 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
14313 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
14314 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
14315 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
14316 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
14317 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
14318 | #define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
14319 | //BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST |
14320 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14321 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14322 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14323 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14324 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14325 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14326 | //BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA_SELECT |
14327 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
14328 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
14329 | //BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA |
14330 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
14331 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
14332 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
14333 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
14334 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
14335 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
14336 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
14337 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
14338 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
14339 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
14340 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
14341 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
14342 | //BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_CAP |
14343 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
14344 | #define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
14345 | //BIF_CFG_DEV2_EPF4_PCIE_DPA_ENH_CAP_LIST |
14346 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14347 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14348 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14349 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14350 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14351 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14352 | //BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP |
14353 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
14354 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
14355 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
14356 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
14357 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
14358 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
14359 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
14360 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
14361 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
14362 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
14363 | //BIF_CFG_DEV2_EPF4_PCIE_DPA_LATENCY_INDICATOR |
14364 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
14365 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
14366 | //BIF_CFG_DEV2_EPF4_PCIE_DPA_STATUS |
14367 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
14368 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
14369 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
14370 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
14371 | //BIF_CFG_DEV2_EPF4_PCIE_DPA_CNTL |
14372 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
14373 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
14374 | //BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
14375 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14376 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14377 | //BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
14378 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14379 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14380 | //BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
14381 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14382 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14383 | //BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
14384 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14385 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14386 | //BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
14387 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14388 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14389 | //BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
14390 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14391 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14392 | //BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
14393 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14394 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14395 | //BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
14396 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
14397 | #define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
14398 | //BIF_CFG_DEV2_EPF4_PCIE_ACS_ENH_CAP_LIST |
14399 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14400 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14401 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14402 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14403 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14404 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14405 | //BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP |
14406 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
14407 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
14408 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
14409 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
14410 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
14411 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
14412 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
14413 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
14414 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
14415 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
14416 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
14417 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
14418 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
14419 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
14420 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
14421 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
14422 | //BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL |
14423 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
14424 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
14425 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
14426 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
14427 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
14428 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
14429 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
14430 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
14431 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
14432 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
14433 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
14434 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
14435 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
14436 | #define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
14437 | //BIF_CFG_DEV2_EPF4_PCIE_PASID_ENH_CAP_LIST |
14438 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14439 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14440 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14441 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14442 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14443 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14444 | //BIF_CFG_DEV2_EPF4_PCIE_PASID_CAP |
14445 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
14446 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
14447 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
14448 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
14449 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
14450 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
14451 | //BIF_CFG_DEV2_EPF4_PCIE_PASID_CNTL |
14452 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
14453 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
14454 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
14455 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
14456 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
14457 | #define BIF_CFG_DEV2_EPF4_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
14458 | //BIF_CFG_DEV2_EPF4_PCIE_ARI_ENH_CAP_LIST |
14459 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14460 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14461 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14462 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14463 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14464 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14465 | //BIF_CFG_DEV2_EPF4_PCIE_ARI_CAP |
14466 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
14467 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
14468 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
14469 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
14470 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
14471 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
14472 | //BIF_CFG_DEV2_EPF4_PCIE_ARI_CNTL |
14473 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
14474 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
14475 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
14476 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
14477 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
14478 | #define BIF_CFG_DEV2_EPF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
14479 | //BIF_CFG_DEV2_EPF4_PCIE_RTR_ENH_CAP_LIST |
14480 | #define BIF_CFG_DEV2_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
14481 | #define BIF_CFG_DEV2_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
14482 | #define BIF_CFG_DEV2_EPF4_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
14483 | #define BIF_CFG_DEV2_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
14484 | #define BIF_CFG_DEV2_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
14485 | #define BIF_CFG_DEV2_EPF4_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
14486 | //BIF_CFG_DEV2_EPF4_RTR_DATA1 |
14487 | #define BIF_CFG_DEV2_EPF4_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
14488 | #define BIF_CFG_DEV2_EPF4_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
14489 | #define BIF_CFG_DEV2_EPF4_RTR_DATA1__VALID__SHIFT 0x1f |
14490 | #define BIF_CFG_DEV2_EPF4_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
14491 | #define BIF_CFG_DEV2_EPF4_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
14492 | #define BIF_CFG_DEV2_EPF4_RTR_DATA1__VALID_MASK 0x80000000L |
14493 | //BIF_CFG_DEV2_EPF4_RTR_DATA2 |
14494 | #define BIF_CFG_DEV2_EPF4_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
14495 | #define BIF_CFG_DEV2_EPF4_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
14496 | #define BIF_CFG_DEV2_EPF4_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
14497 | #define BIF_CFG_DEV2_EPF4_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
14498 | |
14499 | |
14500 | // addressBlock: nbio_nbif0_bif_cfg_dev2_epf5_bifcfgdecp |
14501 | //BIF_CFG_DEV2_EPF5_VENDOR_ID |
14502 | #define BIF_CFG_DEV2_EPF5_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
14503 | #define BIF_CFG_DEV2_EPF5_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
14504 | //BIF_CFG_DEV2_EPF5_DEVICE_ID |
14505 | #define BIF_CFG_DEV2_EPF5_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
14506 | #define BIF_CFG_DEV2_EPF5_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
14507 | //BIF_CFG_DEV2_EPF5_COMMAND |
14508 | #define BIF_CFG_DEV2_EPF5_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
14509 | #define BIF_CFG_DEV2_EPF5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
14510 | #define BIF_CFG_DEV2_EPF5_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
14511 | #define BIF_CFG_DEV2_EPF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
14512 | #define BIF_CFG_DEV2_EPF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
14513 | #define BIF_CFG_DEV2_EPF5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
14514 | #define BIF_CFG_DEV2_EPF5_COMMAND__AD_STEPPING__SHIFT 0x7 |
14515 | #define BIF_CFG_DEV2_EPF5_COMMAND__SERR_EN__SHIFT 0x8 |
14516 | #define BIF_CFG_DEV2_EPF5_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
14517 | #define BIF_CFG_DEV2_EPF5_COMMAND__INT_DIS__SHIFT 0xa |
14518 | #define BIF_CFG_DEV2_EPF5_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
14519 | #define BIF_CFG_DEV2_EPF5_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
14520 | #define BIF_CFG_DEV2_EPF5_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
14521 | #define BIF_CFG_DEV2_EPF5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
14522 | #define BIF_CFG_DEV2_EPF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
14523 | #define BIF_CFG_DEV2_EPF5_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
14524 | #define BIF_CFG_DEV2_EPF5_COMMAND__AD_STEPPING_MASK 0x0080L |
14525 | #define BIF_CFG_DEV2_EPF5_COMMAND__SERR_EN_MASK 0x0100L |
14526 | #define BIF_CFG_DEV2_EPF5_COMMAND__FAST_B2B_EN_MASK 0x0200L |
14527 | #define BIF_CFG_DEV2_EPF5_COMMAND__INT_DIS_MASK 0x0400L |
14528 | //BIF_CFG_DEV2_EPF5_STATUS |
14529 | #define BIF_CFG_DEV2_EPF5_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
14530 | #define BIF_CFG_DEV2_EPF5_STATUS__INT_STATUS__SHIFT 0x3 |
14531 | #define BIF_CFG_DEV2_EPF5_STATUS__CAP_LIST__SHIFT 0x4 |
14532 | #define BIF_CFG_DEV2_EPF5_STATUS__PCI_66_CAP__SHIFT 0x5 |
14533 | #define BIF_CFG_DEV2_EPF5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
14534 | #define BIF_CFG_DEV2_EPF5_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
14535 | #define BIF_CFG_DEV2_EPF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
14536 | #define BIF_CFG_DEV2_EPF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
14537 | #define BIF_CFG_DEV2_EPF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
14538 | #define BIF_CFG_DEV2_EPF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
14539 | #define BIF_CFG_DEV2_EPF5_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
14540 | #define BIF_CFG_DEV2_EPF5_STATUS__INT_STATUS_MASK 0x0008L |
14541 | #define BIF_CFG_DEV2_EPF5_STATUS__CAP_LIST_MASK 0x0010L |
14542 | #define BIF_CFG_DEV2_EPF5_STATUS__PCI_66_CAP_MASK 0x0020L |
14543 | #define BIF_CFG_DEV2_EPF5_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
14544 | #define BIF_CFG_DEV2_EPF5_STATUS__DEVSEL_TIMING_MASK 0x0600L |
14545 | #define BIF_CFG_DEV2_EPF5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
14546 | #define BIF_CFG_DEV2_EPF5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
14547 | #define BIF_CFG_DEV2_EPF5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
14548 | #define BIF_CFG_DEV2_EPF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
14549 | //BIF_CFG_DEV2_EPF5_REVISION_ID |
14550 | #define BIF_CFG_DEV2_EPF5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
14551 | #define BIF_CFG_DEV2_EPF5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
14552 | #define BIF_CFG_DEV2_EPF5_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
14553 | #define BIF_CFG_DEV2_EPF5_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
14554 | //BIF_CFG_DEV2_EPF5_PROG_INTERFACE |
14555 | #define BIF_CFG_DEV2_EPF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
14556 | #define BIF_CFG_DEV2_EPF5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
14557 | //BIF_CFG_DEV2_EPF5_SUB_CLASS |
14558 | #define BIF_CFG_DEV2_EPF5_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
14559 | #define BIF_CFG_DEV2_EPF5_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
14560 | //BIF_CFG_DEV2_EPF5_BASE_CLASS |
14561 | #define BIF_CFG_DEV2_EPF5_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
14562 | #define BIF_CFG_DEV2_EPF5_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
14563 | //BIF_CFG_DEV2_EPF5_CACHE_LINE |
14564 | #define BIF_CFG_DEV2_EPF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
14565 | #define BIF_CFG_DEV2_EPF5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
14566 | //BIF_CFG_DEV2_EPF5_LATENCY |
14567 | #define BIF_CFG_DEV2_EPF5_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
14568 | #define BIF_CFG_DEV2_EPF5_LATENCY__LATENCY_TIMER_MASK 0xFFL |
14569 | //BIF_CFG_DEV2_EPF5_HEADER |
14570 | #define 0x0 |
14571 | #define 0x7 |
14572 | #define 0x7FL |
14573 | #define 0x80L |
14574 | //BIF_CFG_DEV2_EPF5_BIST |
14575 | #define BIF_CFG_DEV2_EPF5_BIST__BIST_COMP__SHIFT 0x0 |
14576 | #define BIF_CFG_DEV2_EPF5_BIST__BIST_STRT__SHIFT 0x6 |
14577 | #define BIF_CFG_DEV2_EPF5_BIST__BIST_CAP__SHIFT 0x7 |
14578 | #define BIF_CFG_DEV2_EPF5_BIST__BIST_COMP_MASK 0x0FL |
14579 | #define BIF_CFG_DEV2_EPF5_BIST__BIST_STRT_MASK 0x40L |
14580 | #define BIF_CFG_DEV2_EPF5_BIST__BIST_CAP_MASK 0x80L |
14581 | //BIF_CFG_DEV2_EPF5_BASE_ADDR_1 |
14582 | #define BIF_CFG_DEV2_EPF5_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
14583 | #define BIF_CFG_DEV2_EPF5_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
14584 | //BIF_CFG_DEV2_EPF5_BASE_ADDR_2 |
14585 | #define BIF_CFG_DEV2_EPF5_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
14586 | #define BIF_CFG_DEV2_EPF5_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
14587 | //BIF_CFG_DEV2_EPF5_BASE_ADDR_3 |
14588 | #define BIF_CFG_DEV2_EPF5_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
14589 | #define BIF_CFG_DEV2_EPF5_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
14590 | //BIF_CFG_DEV2_EPF5_BASE_ADDR_4 |
14591 | #define BIF_CFG_DEV2_EPF5_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
14592 | #define BIF_CFG_DEV2_EPF5_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
14593 | //BIF_CFG_DEV2_EPF5_BASE_ADDR_5 |
14594 | #define BIF_CFG_DEV2_EPF5_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
14595 | #define BIF_CFG_DEV2_EPF5_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
14596 | //BIF_CFG_DEV2_EPF5_BASE_ADDR_6 |
14597 | #define BIF_CFG_DEV2_EPF5_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
14598 | #define BIF_CFG_DEV2_EPF5_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
14599 | //BIF_CFG_DEV2_EPF5_ADAPTER_ID |
14600 | #define BIF_CFG_DEV2_EPF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
14601 | #define BIF_CFG_DEV2_EPF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
14602 | #define BIF_CFG_DEV2_EPF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
14603 | #define BIF_CFG_DEV2_EPF5_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
14604 | //BIF_CFG_DEV2_EPF5_ROM_BASE_ADDR |
14605 | #define BIF_CFG_DEV2_EPF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
14606 | #define BIF_CFG_DEV2_EPF5_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
14607 | //BIF_CFG_DEV2_EPF5_CAP_PTR |
14608 | #define BIF_CFG_DEV2_EPF5_CAP_PTR__CAP_PTR__SHIFT 0x0 |
14609 | #define BIF_CFG_DEV2_EPF5_CAP_PTR__CAP_PTR_MASK 0xFFL |
14610 | //BIF_CFG_DEV2_EPF5_INTERRUPT_LINE |
14611 | #define BIF_CFG_DEV2_EPF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
14612 | #define BIF_CFG_DEV2_EPF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
14613 | //BIF_CFG_DEV2_EPF5_INTERRUPT_PIN |
14614 | #define BIF_CFG_DEV2_EPF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
14615 | #define BIF_CFG_DEV2_EPF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
14616 | //BIF_CFG_DEV2_EPF5_MIN_GRANT |
14617 | #define BIF_CFG_DEV2_EPF5_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
14618 | #define BIF_CFG_DEV2_EPF5_MIN_GRANT__MIN_GNT_MASK 0xFFL |
14619 | //BIF_CFG_DEV2_EPF5_MAX_LATENCY |
14620 | #define BIF_CFG_DEV2_EPF5_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
14621 | #define BIF_CFG_DEV2_EPF5_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
14622 | //BIF_CFG_DEV2_EPF5_VENDOR_CAP_LIST |
14623 | #define BIF_CFG_DEV2_EPF5_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
14624 | #define BIF_CFG_DEV2_EPF5_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
14625 | #define BIF_CFG_DEV2_EPF5_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
14626 | #define BIF_CFG_DEV2_EPF5_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
14627 | #define BIF_CFG_DEV2_EPF5_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
14628 | #define BIF_CFG_DEV2_EPF5_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
14629 | //BIF_CFG_DEV2_EPF5_ADAPTER_ID_W |
14630 | #define BIF_CFG_DEV2_EPF5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
14631 | #define BIF_CFG_DEV2_EPF5_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
14632 | #define BIF_CFG_DEV2_EPF5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
14633 | #define BIF_CFG_DEV2_EPF5_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
14634 | //BIF_CFG_DEV2_EPF5_PMI_CAP_LIST |
14635 | #define BIF_CFG_DEV2_EPF5_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
14636 | #define BIF_CFG_DEV2_EPF5_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
14637 | #define BIF_CFG_DEV2_EPF5_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
14638 | #define BIF_CFG_DEV2_EPF5_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
14639 | //BIF_CFG_DEV2_EPF5_PMI_CAP |
14640 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__VERSION__SHIFT 0x0 |
14641 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
14642 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
14643 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
14644 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
14645 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
14646 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
14647 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
14648 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__VERSION_MASK 0x0007L |
14649 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__PME_CLOCK_MASK 0x0008L |
14650 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
14651 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
14652 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
14653 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
14654 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
14655 | #define BIF_CFG_DEV2_EPF5_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
14656 | //BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL |
14657 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
14658 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
14659 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
14660 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
14661 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
14662 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
14663 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
14664 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
14665 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
14666 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
14667 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
14668 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
14669 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
14670 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
14671 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
14672 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
14673 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
14674 | #define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
14675 | //BIF_CFG_DEV2_EPF5_PCIE_CAP_LIST |
14676 | #define BIF_CFG_DEV2_EPF5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
14677 | #define BIF_CFG_DEV2_EPF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
14678 | #define BIF_CFG_DEV2_EPF5_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
14679 | #define BIF_CFG_DEV2_EPF5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
14680 | //BIF_CFG_DEV2_EPF5_PCIE_CAP |
14681 | #define BIF_CFG_DEV2_EPF5_PCIE_CAP__VERSION__SHIFT 0x0 |
14682 | #define BIF_CFG_DEV2_EPF5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
14683 | #define BIF_CFG_DEV2_EPF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
14684 | #define BIF_CFG_DEV2_EPF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
14685 | #define BIF_CFG_DEV2_EPF5_PCIE_CAP__VERSION_MASK 0x000FL |
14686 | #define BIF_CFG_DEV2_EPF5_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
14687 | #define BIF_CFG_DEV2_EPF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
14688 | #define BIF_CFG_DEV2_EPF5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
14689 | //BIF_CFG_DEV2_EPF5_DEVICE_CAP |
14690 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
14691 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
14692 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
14693 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
14694 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
14695 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
14696 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
14697 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
14698 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
14699 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
14700 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
14701 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
14702 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
14703 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
14704 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
14705 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
14706 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
14707 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
14708 | //BIF_CFG_DEV2_EPF5_DEVICE_CNTL |
14709 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
14710 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
14711 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
14712 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
14713 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
14714 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
14715 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
14716 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
14717 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
14718 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
14719 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
14720 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
14721 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
14722 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
14723 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
14724 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
14725 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
14726 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
14727 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
14728 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
14729 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
14730 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
14731 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
14732 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
14733 | //BIF_CFG_DEV2_EPF5_DEVICE_STATUS |
14734 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
14735 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
14736 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
14737 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
14738 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
14739 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
14740 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
14741 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
14742 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
14743 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
14744 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
14745 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
14746 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
14747 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
14748 | //BIF_CFG_DEV2_EPF5_LINK_CAP |
14749 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
14750 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
14751 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
14752 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
14753 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
14754 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
14755 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
14756 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
14757 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
14758 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
14759 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
14760 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
14761 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
14762 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
14763 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
14764 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
14765 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
14766 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
14767 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
14768 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
14769 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
14770 | #define BIF_CFG_DEV2_EPF5_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
14771 | //BIF_CFG_DEV2_EPF5_LINK_CNTL |
14772 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
14773 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
14774 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
14775 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
14776 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
14777 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
14778 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
14779 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
14780 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
14781 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
14782 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
14783 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
14784 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
14785 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
14786 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
14787 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__LINK_DIS_MASK 0x0010L |
14788 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
14789 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
14790 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
14791 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
14792 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
14793 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
14794 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
14795 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
14796 | //BIF_CFG_DEV2_EPF5_LINK_STATUS |
14797 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
14798 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
14799 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
14800 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
14801 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
14802 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
14803 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
14804 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
14805 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
14806 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
14807 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
14808 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
14809 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
14810 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
14811 | //BIF_CFG_DEV2_EPF5_DEVICE_CAP2 |
14812 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
14813 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
14814 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
14815 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
14816 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
14817 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
14818 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
14819 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
14820 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
14821 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
14822 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
14823 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
14824 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
14825 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
14826 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
14827 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
14828 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
14829 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
14830 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
14831 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
14832 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
14833 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
14834 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
14835 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
14836 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
14837 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
14838 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
14839 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
14840 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
14841 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
14842 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
14843 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
14844 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
14845 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
14846 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
14847 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
14848 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
14849 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
14850 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
14851 | #define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
14852 | //BIF_CFG_DEV2_EPF5_DEVICE_CNTL2 |
14853 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
14854 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
14855 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
14856 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
14857 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
14858 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
14859 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
14860 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
14861 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
14862 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
14863 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
14864 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
14865 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
14866 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
14867 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
14868 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
14869 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
14870 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
14871 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
14872 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
14873 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
14874 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
14875 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
14876 | #define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
14877 | //BIF_CFG_DEV2_EPF5_DEVICE_STATUS2 |
14878 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
14879 | #define BIF_CFG_DEV2_EPF5_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
14880 | //BIF_CFG_DEV2_EPF5_LINK_CAP2 |
14881 | #define BIF_CFG_DEV2_EPF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
14882 | #define BIF_CFG_DEV2_EPF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
14883 | #define BIF_CFG_DEV2_EPF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
14884 | #define BIF_CFG_DEV2_EPF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
14885 | #define BIF_CFG_DEV2_EPF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
14886 | #define BIF_CFG_DEV2_EPF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
14887 | #define BIF_CFG_DEV2_EPF5_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
14888 | #define BIF_CFG_DEV2_EPF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
14889 | #define BIF_CFG_DEV2_EPF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
14890 | #define BIF_CFG_DEV2_EPF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
14891 | #define BIF_CFG_DEV2_EPF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
14892 | #define BIF_CFG_DEV2_EPF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
14893 | #define BIF_CFG_DEV2_EPF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
14894 | #define BIF_CFG_DEV2_EPF5_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
14895 | //BIF_CFG_DEV2_EPF5_LINK_CNTL2 |
14896 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
14897 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
14898 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
14899 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
14900 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
14901 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
14902 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
14903 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
14904 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
14905 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
14906 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
14907 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
14908 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
14909 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
14910 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
14911 | #define BIF_CFG_DEV2_EPF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
14912 | //BIF_CFG_DEV2_EPF5_LINK_STATUS2 |
14913 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
14914 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
14915 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
14916 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
14917 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
14918 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
14919 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
14920 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
14921 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
14922 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
14923 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
14924 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
14925 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
14926 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
14927 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
14928 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
14929 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
14930 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
14931 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
14932 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
14933 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
14934 | #define BIF_CFG_DEV2_EPF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
14935 | //BIF_CFG_DEV2_EPF5_MSI_CAP_LIST |
14936 | #define BIF_CFG_DEV2_EPF5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
14937 | #define BIF_CFG_DEV2_EPF5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
14938 | #define BIF_CFG_DEV2_EPF5_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
14939 | #define BIF_CFG_DEV2_EPF5_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
14940 | //BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL |
14941 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
14942 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
14943 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
14944 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
14945 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
14946 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
14947 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
14948 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
14949 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
14950 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
14951 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
14952 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
14953 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
14954 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
14955 | //BIF_CFG_DEV2_EPF5_MSI_MSG_ADDR_LO |
14956 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
14957 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
14958 | //BIF_CFG_DEV2_EPF5_MSI_MSG_ADDR_HI |
14959 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
14960 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
14961 | //BIF_CFG_DEV2_EPF5_MSI_MSG_DATA |
14962 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
14963 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
14964 | //BIF_CFG_DEV2_EPF5_MSI_EXT_MSG_DATA |
14965 | #define BIF_CFG_DEV2_EPF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
14966 | #define BIF_CFG_DEV2_EPF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
14967 | //BIF_CFG_DEV2_EPF5_MSI_MASK |
14968 | #define BIF_CFG_DEV2_EPF5_MSI_MASK__MSI_MASK__SHIFT 0x0 |
14969 | #define BIF_CFG_DEV2_EPF5_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
14970 | //BIF_CFG_DEV2_EPF5_MSI_MSG_DATA_64 |
14971 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
14972 | #define BIF_CFG_DEV2_EPF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
14973 | //BIF_CFG_DEV2_EPF5_MSI_EXT_MSG_DATA_64 |
14974 | #define BIF_CFG_DEV2_EPF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
14975 | #define BIF_CFG_DEV2_EPF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
14976 | //BIF_CFG_DEV2_EPF5_MSI_MASK_64 |
14977 | #define BIF_CFG_DEV2_EPF5_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
14978 | #define BIF_CFG_DEV2_EPF5_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
14979 | //BIF_CFG_DEV2_EPF5_MSI_PENDING |
14980 | #define BIF_CFG_DEV2_EPF5_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
14981 | #define BIF_CFG_DEV2_EPF5_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
14982 | //BIF_CFG_DEV2_EPF5_MSI_PENDING_64 |
14983 | #define BIF_CFG_DEV2_EPF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
14984 | #define BIF_CFG_DEV2_EPF5_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
14985 | //BIF_CFG_DEV2_EPF5_MSIX_CAP_LIST |
14986 | #define BIF_CFG_DEV2_EPF5_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
14987 | #define BIF_CFG_DEV2_EPF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
14988 | #define BIF_CFG_DEV2_EPF5_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
14989 | #define BIF_CFG_DEV2_EPF5_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
14990 | //BIF_CFG_DEV2_EPF5_MSIX_MSG_CNTL |
14991 | #define BIF_CFG_DEV2_EPF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
14992 | #define BIF_CFG_DEV2_EPF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
14993 | #define BIF_CFG_DEV2_EPF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
14994 | #define BIF_CFG_DEV2_EPF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
14995 | #define BIF_CFG_DEV2_EPF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
14996 | #define BIF_CFG_DEV2_EPF5_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
14997 | //BIF_CFG_DEV2_EPF5_MSIX_TABLE |
14998 | #define BIF_CFG_DEV2_EPF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
14999 | #define BIF_CFG_DEV2_EPF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
15000 | #define BIF_CFG_DEV2_EPF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
15001 | #define BIF_CFG_DEV2_EPF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
15002 | //BIF_CFG_DEV2_EPF5_MSIX_PBA |
15003 | #define BIF_CFG_DEV2_EPF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
15004 | #define BIF_CFG_DEV2_EPF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
15005 | #define BIF_CFG_DEV2_EPF5_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
15006 | #define BIF_CFG_DEV2_EPF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
15007 | //BIF_CFG_DEV2_EPF5_SATA_CAP_0 |
15008 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
15009 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
15010 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
15011 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
15012 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
15013 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
15014 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
15015 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
15016 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
15017 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
15018 | //BIF_CFG_DEV2_EPF5_SATA_CAP_1 |
15019 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
15020 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
15021 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
15022 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
15023 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
15024 | #define BIF_CFG_DEV2_EPF5_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
15025 | //BIF_CFG_DEV2_EPF5_SATA_IDP_INDEX |
15026 | #define BIF_CFG_DEV2_EPF5_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
15027 | #define BIF_CFG_DEV2_EPF5_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
15028 | #define BIF_CFG_DEV2_EPF5_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
15029 | #define BIF_CFG_DEV2_EPF5_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
15030 | #define BIF_CFG_DEV2_EPF5_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
15031 | #define BIF_CFG_DEV2_EPF5_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
15032 | //BIF_CFG_DEV2_EPF5_SATA_IDP_DATA |
15033 | #define BIF_CFG_DEV2_EPF5_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
15034 | #define BIF_CFG_DEV2_EPF5_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
15035 | //BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
15036 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
15037 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
15038 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
15039 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
15040 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
15041 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
15042 | //BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_HDR |
15043 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
15044 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
15045 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
15046 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
15047 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
15048 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
15049 | //BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC1 |
15050 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
15051 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
15052 | //BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC2 |
15053 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
15054 | #define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
15055 | //BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
15056 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
15057 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
15058 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
15059 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
15060 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
15061 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
15062 | //BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS |
15063 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
15064 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
15065 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
15066 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
15067 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
15068 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
15069 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
15070 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
15071 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
15072 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
15073 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
15074 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
15075 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
15076 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
15077 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
15078 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
15079 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
15080 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
15081 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
15082 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
15083 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
15084 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
15085 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
15086 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
15087 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
15088 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
15089 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
15090 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
15091 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
15092 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
15093 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
15094 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
15095 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
15096 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
15097 | //BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK |
15098 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
15099 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
15100 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
15101 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
15102 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
15103 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
15104 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
15105 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
15106 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
15107 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
15108 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
15109 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
15110 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
15111 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
15112 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
15113 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
15114 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
15115 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
15116 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
15117 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
15118 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
15119 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
15120 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
15121 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
15122 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
15123 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
15124 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
15125 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
15126 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
15127 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
15128 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
15129 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
15130 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
15131 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
15132 | //BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY |
15133 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
15134 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
15135 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
15136 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
15137 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
15138 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
15139 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
15140 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
15141 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
15142 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
15143 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
15144 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
15145 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
15146 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
15147 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
15148 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
15149 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
15150 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
15151 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
15152 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
15153 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
15154 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
15155 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
15156 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
15157 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
15158 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
15159 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
15160 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
15161 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
15162 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
15163 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
15164 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
15165 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
15166 | #define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
15167 | //BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS |
15168 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
15169 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
15170 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
15171 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
15172 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
15173 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
15174 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
15175 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
15176 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
15177 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
15178 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
15179 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
15180 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
15181 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
15182 | //BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK |
15183 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
15184 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
15185 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
15186 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
15187 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
15188 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
15189 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
15190 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
15191 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
15192 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
15193 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
15194 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
15195 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
15196 | #define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
15197 | //BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL |
15198 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
15199 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
15200 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
15201 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
15202 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
15203 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
15204 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
15205 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
15206 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
15207 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
15208 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
15209 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
15210 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
15211 | #define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
15212 | //BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG0 |
15213 | #define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
15214 | #define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
15215 | //BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG1 |
15216 | #define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
15217 | #define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
15218 | //BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG2 |
15219 | #define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
15220 | #define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
15221 | //BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG3 |
15222 | #define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
15223 | #define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
15224 | //BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG0 |
15225 | #define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
15226 | #define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
15227 | //BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG1 |
15228 | #define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
15229 | #define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
15230 | //BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG2 |
15231 | #define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
15232 | #define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
15233 | //BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG3 |
15234 | #define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
15235 | #define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
15236 | //BIF_CFG_DEV2_EPF5_PCIE_BAR_ENH_CAP_LIST |
15237 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
15238 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
15239 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
15240 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
15241 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
15242 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
15243 | //BIF_CFG_DEV2_EPF5_PCIE_BAR1_CAP |
15244 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
15245 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
15246 | //BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL |
15247 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
15248 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
15249 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
15250 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
15251 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
15252 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
15253 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
15254 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
15255 | //BIF_CFG_DEV2_EPF5_PCIE_BAR2_CAP |
15256 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
15257 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
15258 | //BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL |
15259 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
15260 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
15261 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
15262 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
15263 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
15264 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
15265 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
15266 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
15267 | //BIF_CFG_DEV2_EPF5_PCIE_BAR3_CAP |
15268 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
15269 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
15270 | //BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL |
15271 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
15272 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
15273 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
15274 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
15275 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
15276 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
15277 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
15278 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
15279 | //BIF_CFG_DEV2_EPF5_PCIE_BAR4_CAP |
15280 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
15281 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
15282 | //BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL |
15283 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
15284 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
15285 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
15286 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
15287 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
15288 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
15289 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
15290 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
15291 | //BIF_CFG_DEV2_EPF5_PCIE_BAR5_CAP |
15292 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
15293 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
15294 | //BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL |
15295 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
15296 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
15297 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
15298 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
15299 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
15300 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
15301 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
15302 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
15303 | //BIF_CFG_DEV2_EPF5_PCIE_BAR6_CAP |
15304 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
15305 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
15306 | //BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL |
15307 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
15308 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
15309 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
15310 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
15311 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
15312 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
15313 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
15314 | #define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
15315 | //BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST |
15316 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
15317 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
15318 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
15319 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
15320 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
15321 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
15322 | //BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA_SELECT |
15323 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
15324 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
15325 | //BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA |
15326 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
15327 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
15328 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
15329 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
15330 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
15331 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
15332 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
15333 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
15334 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
15335 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
15336 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
15337 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
15338 | //BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_CAP |
15339 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
15340 | #define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
15341 | //BIF_CFG_DEV2_EPF5_PCIE_DPA_ENH_CAP_LIST |
15342 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
15343 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
15344 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
15345 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
15346 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
15347 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
15348 | //BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP |
15349 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
15350 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
15351 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
15352 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
15353 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
15354 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
15355 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
15356 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
15357 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
15358 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
15359 | //BIF_CFG_DEV2_EPF5_PCIE_DPA_LATENCY_INDICATOR |
15360 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
15361 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
15362 | //BIF_CFG_DEV2_EPF5_PCIE_DPA_STATUS |
15363 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
15364 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
15365 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
15366 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
15367 | //BIF_CFG_DEV2_EPF5_PCIE_DPA_CNTL |
15368 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
15369 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
15370 | //BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
15371 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
15372 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
15373 | //BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
15374 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
15375 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
15376 | //BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
15377 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
15378 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
15379 | //BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
15380 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
15381 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
15382 | //BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
15383 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
15384 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
15385 | //BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
15386 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
15387 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
15388 | //BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
15389 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
15390 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
15391 | //BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
15392 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
15393 | #define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
15394 | //BIF_CFG_DEV2_EPF5_PCIE_ACS_ENH_CAP_LIST |
15395 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
15396 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
15397 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
15398 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
15399 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
15400 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
15401 | //BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP |
15402 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
15403 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
15404 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
15405 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
15406 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
15407 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
15408 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
15409 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
15410 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
15411 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
15412 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
15413 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
15414 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
15415 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
15416 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
15417 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
15418 | //BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL |
15419 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
15420 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
15421 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
15422 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
15423 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
15424 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
15425 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
15426 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
15427 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
15428 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
15429 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
15430 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
15431 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
15432 | #define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
15433 | //BIF_CFG_DEV2_EPF5_PCIE_PASID_ENH_CAP_LIST |
15434 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
15435 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
15436 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
15437 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
15438 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
15439 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
15440 | //BIF_CFG_DEV2_EPF5_PCIE_PASID_CAP |
15441 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
15442 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
15443 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
15444 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
15445 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
15446 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
15447 | //BIF_CFG_DEV2_EPF5_PCIE_PASID_CNTL |
15448 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
15449 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
15450 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
15451 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
15452 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
15453 | #define BIF_CFG_DEV2_EPF5_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
15454 | //BIF_CFG_DEV2_EPF5_PCIE_ARI_ENH_CAP_LIST |
15455 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
15456 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
15457 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
15458 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
15459 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
15460 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
15461 | //BIF_CFG_DEV2_EPF5_PCIE_ARI_CAP |
15462 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
15463 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
15464 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
15465 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
15466 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
15467 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
15468 | //BIF_CFG_DEV2_EPF5_PCIE_ARI_CNTL |
15469 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
15470 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
15471 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
15472 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
15473 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
15474 | #define BIF_CFG_DEV2_EPF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
15475 | //BIF_CFG_DEV2_EPF5_PCIE_RTR_ENH_CAP_LIST |
15476 | #define BIF_CFG_DEV2_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
15477 | #define BIF_CFG_DEV2_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
15478 | #define BIF_CFG_DEV2_EPF5_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
15479 | #define BIF_CFG_DEV2_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
15480 | #define BIF_CFG_DEV2_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
15481 | #define BIF_CFG_DEV2_EPF5_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
15482 | //BIF_CFG_DEV2_EPF5_RTR_DATA1 |
15483 | #define BIF_CFG_DEV2_EPF5_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
15484 | #define BIF_CFG_DEV2_EPF5_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
15485 | #define BIF_CFG_DEV2_EPF5_RTR_DATA1__VALID__SHIFT 0x1f |
15486 | #define BIF_CFG_DEV2_EPF5_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
15487 | #define BIF_CFG_DEV2_EPF5_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
15488 | #define BIF_CFG_DEV2_EPF5_RTR_DATA1__VALID_MASK 0x80000000L |
15489 | //BIF_CFG_DEV2_EPF5_RTR_DATA2 |
15490 | #define BIF_CFG_DEV2_EPF5_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
15491 | #define BIF_CFG_DEV2_EPF5_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
15492 | #define BIF_CFG_DEV2_EPF5_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
15493 | #define BIF_CFG_DEV2_EPF5_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
15494 | |
15495 | |
15496 | // addressBlock: nbio_nbif0_bif_cfg_dev2_epf6_bifcfgdecp |
15497 | //BIF_CFG_DEV2_EPF6_VENDOR_ID |
15498 | #define BIF_CFG_DEV2_EPF6_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
15499 | #define BIF_CFG_DEV2_EPF6_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
15500 | //BIF_CFG_DEV2_EPF6_DEVICE_ID |
15501 | #define BIF_CFG_DEV2_EPF6_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
15502 | #define BIF_CFG_DEV2_EPF6_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
15503 | //BIF_CFG_DEV2_EPF6_COMMAND |
15504 | #define BIF_CFG_DEV2_EPF6_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
15505 | #define BIF_CFG_DEV2_EPF6_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
15506 | #define BIF_CFG_DEV2_EPF6_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
15507 | #define BIF_CFG_DEV2_EPF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
15508 | #define BIF_CFG_DEV2_EPF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
15509 | #define BIF_CFG_DEV2_EPF6_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
15510 | #define BIF_CFG_DEV2_EPF6_COMMAND__AD_STEPPING__SHIFT 0x7 |
15511 | #define BIF_CFG_DEV2_EPF6_COMMAND__SERR_EN__SHIFT 0x8 |
15512 | #define BIF_CFG_DEV2_EPF6_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
15513 | #define BIF_CFG_DEV2_EPF6_COMMAND__INT_DIS__SHIFT 0xa |
15514 | #define BIF_CFG_DEV2_EPF6_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
15515 | #define BIF_CFG_DEV2_EPF6_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
15516 | #define BIF_CFG_DEV2_EPF6_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
15517 | #define BIF_CFG_DEV2_EPF6_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
15518 | #define BIF_CFG_DEV2_EPF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
15519 | #define BIF_CFG_DEV2_EPF6_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
15520 | #define BIF_CFG_DEV2_EPF6_COMMAND__AD_STEPPING_MASK 0x0080L |
15521 | #define BIF_CFG_DEV2_EPF6_COMMAND__SERR_EN_MASK 0x0100L |
15522 | #define BIF_CFG_DEV2_EPF6_COMMAND__FAST_B2B_EN_MASK 0x0200L |
15523 | #define BIF_CFG_DEV2_EPF6_COMMAND__INT_DIS_MASK 0x0400L |
15524 | //BIF_CFG_DEV2_EPF6_STATUS |
15525 | #define BIF_CFG_DEV2_EPF6_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
15526 | #define BIF_CFG_DEV2_EPF6_STATUS__INT_STATUS__SHIFT 0x3 |
15527 | #define BIF_CFG_DEV2_EPF6_STATUS__CAP_LIST__SHIFT 0x4 |
15528 | #define BIF_CFG_DEV2_EPF6_STATUS__PCI_66_CAP__SHIFT 0x5 |
15529 | #define BIF_CFG_DEV2_EPF6_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
15530 | #define BIF_CFG_DEV2_EPF6_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
15531 | #define BIF_CFG_DEV2_EPF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
15532 | #define BIF_CFG_DEV2_EPF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
15533 | #define BIF_CFG_DEV2_EPF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
15534 | #define BIF_CFG_DEV2_EPF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
15535 | #define BIF_CFG_DEV2_EPF6_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
15536 | #define BIF_CFG_DEV2_EPF6_STATUS__INT_STATUS_MASK 0x0008L |
15537 | #define BIF_CFG_DEV2_EPF6_STATUS__CAP_LIST_MASK 0x0010L |
15538 | #define BIF_CFG_DEV2_EPF6_STATUS__PCI_66_CAP_MASK 0x0020L |
15539 | #define BIF_CFG_DEV2_EPF6_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
15540 | #define BIF_CFG_DEV2_EPF6_STATUS__DEVSEL_TIMING_MASK 0x0600L |
15541 | #define BIF_CFG_DEV2_EPF6_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
15542 | #define BIF_CFG_DEV2_EPF6_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
15543 | #define BIF_CFG_DEV2_EPF6_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
15544 | #define BIF_CFG_DEV2_EPF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
15545 | //BIF_CFG_DEV2_EPF6_REVISION_ID |
15546 | #define BIF_CFG_DEV2_EPF6_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
15547 | #define BIF_CFG_DEV2_EPF6_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
15548 | #define BIF_CFG_DEV2_EPF6_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
15549 | #define BIF_CFG_DEV2_EPF6_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
15550 | //BIF_CFG_DEV2_EPF6_PROG_INTERFACE |
15551 | #define BIF_CFG_DEV2_EPF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
15552 | #define BIF_CFG_DEV2_EPF6_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
15553 | //BIF_CFG_DEV2_EPF6_SUB_CLASS |
15554 | #define BIF_CFG_DEV2_EPF6_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
15555 | #define BIF_CFG_DEV2_EPF6_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
15556 | //BIF_CFG_DEV2_EPF6_BASE_CLASS |
15557 | #define BIF_CFG_DEV2_EPF6_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
15558 | #define BIF_CFG_DEV2_EPF6_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
15559 | //BIF_CFG_DEV2_EPF6_CACHE_LINE |
15560 | #define BIF_CFG_DEV2_EPF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
15561 | #define BIF_CFG_DEV2_EPF6_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
15562 | //BIF_CFG_DEV2_EPF6_LATENCY |
15563 | #define BIF_CFG_DEV2_EPF6_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
15564 | #define BIF_CFG_DEV2_EPF6_LATENCY__LATENCY_TIMER_MASK 0xFFL |
15565 | //BIF_CFG_DEV2_EPF6_HEADER |
15566 | #define 0x0 |
15567 | #define 0x7 |
15568 | #define 0x7FL |
15569 | #define 0x80L |
15570 | //BIF_CFG_DEV2_EPF6_BIST |
15571 | #define BIF_CFG_DEV2_EPF6_BIST__BIST_COMP__SHIFT 0x0 |
15572 | #define BIF_CFG_DEV2_EPF6_BIST__BIST_STRT__SHIFT 0x6 |
15573 | #define BIF_CFG_DEV2_EPF6_BIST__BIST_CAP__SHIFT 0x7 |
15574 | #define BIF_CFG_DEV2_EPF6_BIST__BIST_COMP_MASK 0x0FL |
15575 | #define BIF_CFG_DEV2_EPF6_BIST__BIST_STRT_MASK 0x40L |
15576 | #define BIF_CFG_DEV2_EPF6_BIST__BIST_CAP_MASK 0x80L |
15577 | //BIF_CFG_DEV2_EPF6_BASE_ADDR_1 |
15578 | #define BIF_CFG_DEV2_EPF6_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
15579 | #define BIF_CFG_DEV2_EPF6_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
15580 | //BIF_CFG_DEV2_EPF6_BASE_ADDR_2 |
15581 | #define BIF_CFG_DEV2_EPF6_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
15582 | #define BIF_CFG_DEV2_EPF6_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
15583 | //BIF_CFG_DEV2_EPF6_BASE_ADDR_3 |
15584 | #define BIF_CFG_DEV2_EPF6_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
15585 | #define BIF_CFG_DEV2_EPF6_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
15586 | //BIF_CFG_DEV2_EPF6_BASE_ADDR_4 |
15587 | #define BIF_CFG_DEV2_EPF6_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
15588 | #define BIF_CFG_DEV2_EPF6_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
15589 | //BIF_CFG_DEV2_EPF6_BASE_ADDR_5 |
15590 | #define BIF_CFG_DEV2_EPF6_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
15591 | #define BIF_CFG_DEV2_EPF6_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
15592 | //BIF_CFG_DEV2_EPF6_BASE_ADDR_6 |
15593 | #define BIF_CFG_DEV2_EPF6_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
15594 | #define BIF_CFG_DEV2_EPF6_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
15595 | //BIF_CFG_DEV2_EPF6_ADAPTER_ID |
15596 | #define BIF_CFG_DEV2_EPF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
15597 | #define BIF_CFG_DEV2_EPF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
15598 | #define BIF_CFG_DEV2_EPF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
15599 | #define BIF_CFG_DEV2_EPF6_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
15600 | //BIF_CFG_DEV2_EPF6_ROM_BASE_ADDR |
15601 | #define BIF_CFG_DEV2_EPF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
15602 | #define BIF_CFG_DEV2_EPF6_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
15603 | //BIF_CFG_DEV2_EPF6_CAP_PTR |
15604 | #define BIF_CFG_DEV2_EPF6_CAP_PTR__CAP_PTR__SHIFT 0x0 |
15605 | #define BIF_CFG_DEV2_EPF6_CAP_PTR__CAP_PTR_MASK 0xFFL |
15606 | //BIF_CFG_DEV2_EPF6_INTERRUPT_LINE |
15607 | #define BIF_CFG_DEV2_EPF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
15608 | #define BIF_CFG_DEV2_EPF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
15609 | //BIF_CFG_DEV2_EPF6_INTERRUPT_PIN |
15610 | #define BIF_CFG_DEV2_EPF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
15611 | #define BIF_CFG_DEV2_EPF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
15612 | //BIF_CFG_DEV2_EPF6_MIN_GRANT |
15613 | #define BIF_CFG_DEV2_EPF6_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
15614 | #define BIF_CFG_DEV2_EPF6_MIN_GRANT__MIN_GNT_MASK 0xFFL |
15615 | //BIF_CFG_DEV2_EPF6_MAX_LATENCY |
15616 | #define BIF_CFG_DEV2_EPF6_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
15617 | #define BIF_CFG_DEV2_EPF6_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
15618 | //BIF_CFG_DEV2_EPF6_VENDOR_CAP_LIST |
15619 | #define BIF_CFG_DEV2_EPF6_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
15620 | #define BIF_CFG_DEV2_EPF6_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
15621 | #define BIF_CFG_DEV2_EPF6_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
15622 | #define BIF_CFG_DEV2_EPF6_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
15623 | #define BIF_CFG_DEV2_EPF6_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
15624 | #define BIF_CFG_DEV2_EPF6_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
15625 | //BIF_CFG_DEV2_EPF6_ADAPTER_ID_W |
15626 | #define BIF_CFG_DEV2_EPF6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
15627 | #define BIF_CFG_DEV2_EPF6_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
15628 | #define BIF_CFG_DEV2_EPF6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
15629 | #define BIF_CFG_DEV2_EPF6_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
15630 | //BIF_CFG_DEV2_EPF6_PMI_CAP_LIST |
15631 | #define BIF_CFG_DEV2_EPF6_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
15632 | #define BIF_CFG_DEV2_EPF6_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
15633 | #define BIF_CFG_DEV2_EPF6_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
15634 | #define BIF_CFG_DEV2_EPF6_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
15635 | //BIF_CFG_DEV2_EPF6_PMI_CAP |
15636 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__VERSION__SHIFT 0x0 |
15637 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
15638 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
15639 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
15640 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
15641 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
15642 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
15643 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
15644 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__VERSION_MASK 0x0007L |
15645 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__PME_CLOCK_MASK 0x0008L |
15646 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
15647 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
15648 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
15649 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
15650 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
15651 | #define BIF_CFG_DEV2_EPF6_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
15652 | //BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL |
15653 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
15654 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
15655 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
15656 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
15657 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
15658 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
15659 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
15660 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
15661 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
15662 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
15663 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
15664 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
15665 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
15666 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
15667 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
15668 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
15669 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
15670 | #define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
15671 | //BIF_CFG_DEV2_EPF6_PCIE_CAP_LIST |
15672 | #define BIF_CFG_DEV2_EPF6_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
15673 | #define BIF_CFG_DEV2_EPF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
15674 | #define BIF_CFG_DEV2_EPF6_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
15675 | #define BIF_CFG_DEV2_EPF6_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
15676 | //BIF_CFG_DEV2_EPF6_PCIE_CAP |
15677 | #define BIF_CFG_DEV2_EPF6_PCIE_CAP__VERSION__SHIFT 0x0 |
15678 | #define BIF_CFG_DEV2_EPF6_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
15679 | #define BIF_CFG_DEV2_EPF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
15680 | #define BIF_CFG_DEV2_EPF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
15681 | #define BIF_CFG_DEV2_EPF6_PCIE_CAP__VERSION_MASK 0x000FL |
15682 | #define BIF_CFG_DEV2_EPF6_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
15683 | #define BIF_CFG_DEV2_EPF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
15684 | #define BIF_CFG_DEV2_EPF6_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
15685 | //BIF_CFG_DEV2_EPF6_DEVICE_CAP |
15686 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
15687 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
15688 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
15689 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
15690 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
15691 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
15692 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
15693 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
15694 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
15695 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
15696 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
15697 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
15698 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
15699 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
15700 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
15701 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
15702 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
15703 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
15704 | //BIF_CFG_DEV2_EPF6_DEVICE_CNTL |
15705 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
15706 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
15707 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
15708 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
15709 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
15710 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
15711 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
15712 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
15713 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
15714 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
15715 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
15716 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
15717 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
15718 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
15719 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
15720 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
15721 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
15722 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
15723 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
15724 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
15725 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
15726 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
15727 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
15728 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
15729 | //BIF_CFG_DEV2_EPF6_DEVICE_STATUS |
15730 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
15731 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
15732 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
15733 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
15734 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
15735 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
15736 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
15737 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
15738 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
15739 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
15740 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
15741 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
15742 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
15743 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
15744 | //BIF_CFG_DEV2_EPF6_LINK_CAP |
15745 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
15746 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
15747 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
15748 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
15749 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
15750 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
15751 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
15752 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
15753 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
15754 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
15755 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
15756 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
15757 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
15758 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
15759 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
15760 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
15761 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
15762 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
15763 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
15764 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
15765 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
15766 | #define BIF_CFG_DEV2_EPF6_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
15767 | //BIF_CFG_DEV2_EPF6_LINK_CNTL |
15768 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
15769 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
15770 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
15771 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
15772 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
15773 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
15774 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
15775 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
15776 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
15777 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
15778 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
15779 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
15780 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
15781 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
15782 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
15783 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__LINK_DIS_MASK 0x0010L |
15784 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
15785 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
15786 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
15787 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
15788 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
15789 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
15790 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
15791 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
15792 | //BIF_CFG_DEV2_EPF6_LINK_STATUS |
15793 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
15794 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
15795 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
15796 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
15797 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
15798 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
15799 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
15800 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
15801 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
15802 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
15803 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
15804 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
15805 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
15806 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
15807 | //BIF_CFG_DEV2_EPF6_DEVICE_CAP2 |
15808 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
15809 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
15810 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
15811 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
15812 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
15813 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
15814 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
15815 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
15816 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
15817 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
15818 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
15819 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
15820 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
15821 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
15822 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
15823 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
15824 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
15825 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
15826 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
15827 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
15828 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
15829 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
15830 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
15831 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
15832 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
15833 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
15834 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
15835 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
15836 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
15837 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
15838 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
15839 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
15840 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
15841 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
15842 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
15843 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
15844 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
15845 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
15846 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
15847 | #define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
15848 | //BIF_CFG_DEV2_EPF6_DEVICE_CNTL2 |
15849 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
15850 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
15851 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
15852 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
15853 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
15854 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
15855 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
15856 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
15857 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
15858 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
15859 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
15860 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
15861 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
15862 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
15863 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
15864 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
15865 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
15866 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
15867 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
15868 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
15869 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
15870 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
15871 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
15872 | #define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
15873 | //BIF_CFG_DEV2_EPF6_DEVICE_STATUS2 |
15874 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
15875 | #define BIF_CFG_DEV2_EPF6_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
15876 | //BIF_CFG_DEV2_EPF6_LINK_CAP2 |
15877 | #define BIF_CFG_DEV2_EPF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
15878 | #define BIF_CFG_DEV2_EPF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
15879 | #define BIF_CFG_DEV2_EPF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
15880 | #define BIF_CFG_DEV2_EPF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
15881 | #define BIF_CFG_DEV2_EPF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
15882 | #define BIF_CFG_DEV2_EPF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
15883 | #define BIF_CFG_DEV2_EPF6_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
15884 | #define BIF_CFG_DEV2_EPF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
15885 | #define BIF_CFG_DEV2_EPF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
15886 | #define BIF_CFG_DEV2_EPF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
15887 | #define BIF_CFG_DEV2_EPF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
15888 | #define BIF_CFG_DEV2_EPF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
15889 | #define BIF_CFG_DEV2_EPF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
15890 | #define BIF_CFG_DEV2_EPF6_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
15891 | //BIF_CFG_DEV2_EPF6_LINK_CNTL2 |
15892 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
15893 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
15894 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
15895 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
15896 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
15897 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
15898 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
15899 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
15900 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
15901 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
15902 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
15903 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
15904 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
15905 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
15906 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
15907 | #define BIF_CFG_DEV2_EPF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
15908 | //BIF_CFG_DEV2_EPF6_LINK_STATUS2 |
15909 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
15910 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
15911 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
15912 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
15913 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
15914 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
15915 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
15916 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
15917 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
15918 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
15919 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
15920 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
15921 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
15922 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
15923 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
15924 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
15925 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
15926 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
15927 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
15928 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
15929 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
15930 | #define BIF_CFG_DEV2_EPF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
15931 | //BIF_CFG_DEV2_EPF6_MSI_CAP_LIST |
15932 | #define BIF_CFG_DEV2_EPF6_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
15933 | #define BIF_CFG_DEV2_EPF6_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
15934 | #define BIF_CFG_DEV2_EPF6_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
15935 | #define BIF_CFG_DEV2_EPF6_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
15936 | //BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL |
15937 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
15938 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
15939 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
15940 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
15941 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
15942 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
15943 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
15944 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
15945 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
15946 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
15947 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
15948 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
15949 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
15950 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
15951 | //BIF_CFG_DEV2_EPF6_MSI_MSG_ADDR_LO |
15952 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
15953 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
15954 | //BIF_CFG_DEV2_EPF6_MSI_MSG_ADDR_HI |
15955 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
15956 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
15957 | //BIF_CFG_DEV2_EPF6_MSI_MSG_DATA |
15958 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
15959 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
15960 | //BIF_CFG_DEV2_EPF6_MSI_EXT_MSG_DATA |
15961 | #define BIF_CFG_DEV2_EPF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
15962 | #define BIF_CFG_DEV2_EPF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
15963 | //BIF_CFG_DEV2_EPF6_MSI_MASK |
15964 | #define BIF_CFG_DEV2_EPF6_MSI_MASK__MSI_MASK__SHIFT 0x0 |
15965 | #define BIF_CFG_DEV2_EPF6_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
15966 | //BIF_CFG_DEV2_EPF6_MSI_MSG_DATA_64 |
15967 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
15968 | #define BIF_CFG_DEV2_EPF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
15969 | //BIF_CFG_DEV2_EPF6_MSI_EXT_MSG_DATA_64 |
15970 | #define BIF_CFG_DEV2_EPF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
15971 | #define BIF_CFG_DEV2_EPF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
15972 | //BIF_CFG_DEV2_EPF6_MSI_MASK_64 |
15973 | #define BIF_CFG_DEV2_EPF6_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
15974 | #define BIF_CFG_DEV2_EPF6_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
15975 | //BIF_CFG_DEV2_EPF6_MSI_PENDING |
15976 | #define BIF_CFG_DEV2_EPF6_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
15977 | #define BIF_CFG_DEV2_EPF6_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
15978 | //BIF_CFG_DEV2_EPF6_MSI_PENDING_64 |
15979 | #define BIF_CFG_DEV2_EPF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
15980 | #define BIF_CFG_DEV2_EPF6_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
15981 | //BIF_CFG_DEV2_EPF6_MSIX_CAP_LIST |
15982 | #define BIF_CFG_DEV2_EPF6_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
15983 | #define BIF_CFG_DEV2_EPF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
15984 | #define BIF_CFG_DEV2_EPF6_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
15985 | #define BIF_CFG_DEV2_EPF6_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
15986 | //BIF_CFG_DEV2_EPF6_MSIX_MSG_CNTL |
15987 | #define BIF_CFG_DEV2_EPF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
15988 | #define BIF_CFG_DEV2_EPF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
15989 | #define BIF_CFG_DEV2_EPF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
15990 | #define BIF_CFG_DEV2_EPF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
15991 | #define BIF_CFG_DEV2_EPF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
15992 | #define BIF_CFG_DEV2_EPF6_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
15993 | //BIF_CFG_DEV2_EPF6_MSIX_TABLE |
15994 | #define BIF_CFG_DEV2_EPF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
15995 | #define BIF_CFG_DEV2_EPF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
15996 | #define BIF_CFG_DEV2_EPF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
15997 | #define BIF_CFG_DEV2_EPF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
15998 | //BIF_CFG_DEV2_EPF6_MSIX_PBA |
15999 | #define BIF_CFG_DEV2_EPF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
16000 | #define BIF_CFG_DEV2_EPF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
16001 | #define BIF_CFG_DEV2_EPF6_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
16002 | #define BIF_CFG_DEV2_EPF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
16003 | //BIF_CFG_DEV2_EPF6_SATA_CAP_0 |
16004 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
16005 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
16006 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
16007 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
16008 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
16009 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
16010 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
16011 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
16012 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
16013 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
16014 | //BIF_CFG_DEV2_EPF6_SATA_CAP_1 |
16015 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
16016 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
16017 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
16018 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
16019 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
16020 | #define BIF_CFG_DEV2_EPF6_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
16021 | //BIF_CFG_DEV2_EPF6_SATA_IDP_INDEX |
16022 | #define BIF_CFG_DEV2_EPF6_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
16023 | #define BIF_CFG_DEV2_EPF6_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
16024 | #define BIF_CFG_DEV2_EPF6_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
16025 | #define BIF_CFG_DEV2_EPF6_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
16026 | #define BIF_CFG_DEV2_EPF6_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
16027 | #define BIF_CFG_DEV2_EPF6_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
16028 | //BIF_CFG_DEV2_EPF6_SATA_IDP_DATA |
16029 | #define BIF_CFG_DEV2_EPF6_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
16030 | #define BIF_CFG_DEV2_EPF6_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
16031 | //BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
16032 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
16033 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
16034 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
16035 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
16036 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
16037 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
16038 | //BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_HDR |
16039 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
16040 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
16041 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
16042 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
16043 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
16044 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
16045 | //BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC1 |
16046 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
16047 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
16048 | //BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC2 |
16049 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
16050 | #define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
16051 | //BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
16052 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
16053 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
16054 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
16055 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
16056 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
16057 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
16058 | //BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS |
16059 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
16060 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
16061 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
16062 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
16063 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
16064 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
16065 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
16066 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
16067 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
16068 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
16069 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
16070 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
16071 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
16072 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
16073 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
16074 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
16075 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
16076 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
16077 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
16078 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
16079 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
16080 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
16081 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
16082 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
16083 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
16084 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
16085 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
16086 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
16087 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
16088 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
16089 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
16090 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
16091 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
16092 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
16093 | //BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK |
16094 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
16095 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
16096 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
16097 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
16098 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
16099 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
16100 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
16101 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
16102 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
16103 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
16104 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
16105 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
16106 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
16107 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
16108 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
16109 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
16110 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
16111 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
16112 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
16113 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
16114 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
16115 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
16116 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
16117 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
16118 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
16119 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
16120 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
16121 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
16122 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
16123 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
16124 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
16125 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
16126 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
16127 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
16128 | //BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY |
16129 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
16130 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
16131 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
16132 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
16133 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
16134 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
16135 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
16136 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
16137 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
16138 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
16139 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
16140 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
16141 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
16142 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
16143 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
16144 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
16145 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
16146 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
16147 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
16148 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
16149 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
16150 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
16151 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
16152 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
16153 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
16154 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
16155 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
16156 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
16157 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
16158 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
16159 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
16160 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
16161 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
16162 | #define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
16163 | //BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS |
16164 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
16165 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
16166 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
16167 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
16168 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
16169 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
16170 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
16171 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
16172 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
16173 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
16174 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
16175 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
16176 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
16177 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
16178 | //BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK |
16179 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
16180 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
16181 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
16182 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
16183 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
16184 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
16185 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
16186 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
16187 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
16188 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
16189 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
16190 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
16191 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
16192 | #define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
16193 | //BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL |
16194 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
16195 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
16196 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
16197 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
16198 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
16199 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
16200 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
16201 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
16202 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
16203 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
16204 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
16205 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
16206 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
16207 | #define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
16208 | //BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG0 |
16209 | #define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
16210 | #define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
16211 | //BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG1 |
16212 | #define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
16213 | #define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
16214 | //BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG2 |
16215 | #define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
16216 | #define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
16217 | //BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG3 |
16218 | #define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
16219 | #define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
16220 | //BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG0 |
16221 | #define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
16222 | #define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
16223 | //BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG1 |
16224 | #define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
16225 | #define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
16226 | //BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG2 |
16227 | #define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
16228 | #define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
16229 | //BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG3 |
16230 | #define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
16231 | #define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
16232 | //BIF_CFG_DEV2_EPF6_PCIE_BAR_ENH_CAP_LIST |
16233 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
16234 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
16235 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
16236 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
16237 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
16238 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
16239 | //BIF_CFG_DEV2_EPF6_PCIE_BAR1_CAP |
16240 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
16241 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
16242 | //BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL |
16243 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
16244 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
16245 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
16246 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
16247 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
16248 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
16249 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
16250 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
16251 | //BIF_CFG_DEV2_EPF6_PCIE_BAR2_CAP |
16252 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
16253 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
16254 | //BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL |
16255 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
16256 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
16257 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
16258 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
16259 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
16260 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
16261 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
16262 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
16263 | //BIF_CFG_DEV2_EPF6_PCIE_BAR3_CAP |
16264 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
16265 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
16266 | //BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL |
16267 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
16268 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
16269 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
16270 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
16271 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
16272 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
16273 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
16274 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
16275 | //BIF_CFG_DEV2_EPF6_PCIE_BAR4_CAP |
16276 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
16277 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
16278 | //BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL |
16279 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
16280 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
16281 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
16282 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
16283 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
16284 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
16285 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
16286 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
16287 | //BIF_CFG_DEV2_EPF6_PCIE_BAR5_CAP |
16288 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
16289 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
16290 | //BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL |
16291 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
16292 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
16293 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
16294 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
16295 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
16296 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
16297 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
16298 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
16299 | //BIF_CFG_DEV2_EPF6_PCIE_BAR6_CAP |
16300 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
16301 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
16302 | //BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL |
16303 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
16304 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
16305 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
16306 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
16307 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
16308 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
16309 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
16310 | #define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
16311 | //BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST |
16312 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
16313 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
16314 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
16315 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
16316 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
16317 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
16318 | //BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA_SELECT |
16319 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
16320 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
16321 | //BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA |
16322 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
16323 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
16324 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
16325 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
16326 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
16327 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
16328 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
16329 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
16330 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
16331 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
16332 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
16333 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
16334 | //BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_CAP |
16335 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
16336 | #define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
16337 | //BIF_CFG_DEV2_EPF6_PCIE_DPA_ENH_CAP_LIST |
16338 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
16339 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
16340 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
16341 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
16342 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
16343 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
16344 | //BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP |
16345 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
16346 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
16347 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
16348 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
16349 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
16350 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
16351 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
16352 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
16353 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
16354 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
16355 | //BIF_CFG_DEV2_EPF6_PCIE_DPA_LATENCY_INDICATOR |
16356 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
16357 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
16358 | //BIF_CFG_DEV2_EPF6_PCIE_DPA_STATUS |
16359 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
16360 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
16361 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
16362 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
16363 | //BIF_CFG_DEV2_EPF6_PCIE_DPA_CNTL |
16364 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
16365 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
16366 | //BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
16367 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
16368 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
16369 | //BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
16370 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
16371 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
16372 | //BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
16373 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
16374 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
16375 | //BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
16376 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
16377 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
16378 | //BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
16379 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
16380 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
16381 | //BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
16382 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
16383 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
16384 | //BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
16385 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
16386 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
16387 | //BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
16388 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
16389 | #define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
16390 | //BIF_CFG_DEV2_EPF6_PCIE_ACS_ENH_CAP_LIST |
16391 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
16392 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
16393 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
16394 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
16395 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
16396 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
16397 | //BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP |
16398 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
16399 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
16400 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
16401 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
16402 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
16403 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
16404 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
16405 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
16406 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
16407 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
16408 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
16409 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
16410 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
16411 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
16412 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
16413 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
16414 | //BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL |
16415 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
16416 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
16417 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
16418 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
16419 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
16420 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
16421 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
16422 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
16423 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
16424 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
16425 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
16426 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
16427 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
16428 | #define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
16429 | //BIF_CFG_DEV2_EPF6_PCIE_PASID_ENH_CAP_LIST |
16430 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
16431 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
16432 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
16433 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
16434 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
16435 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
16436 | //BIF_CFG_DEV2_EPF6_PCIE_PASID_CAP |
16437 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
16438 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
16439 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
16440 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
16441 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
16442 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
16443 | //BIF_CFG_DEV2_EPF6_PCIE_PASID_CNTL |
16444 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
16445 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
16446 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
16447 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
16448 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
16449 | #define BIF_CFG_DEV2_EPF6_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
16450 | //BIF_CFG_DEV2_EPF6_PCIE_ARI_ENH_CAP_LIST |
16451 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
16452 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
16453 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
16454 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
16455 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
16456 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
16457 | //BIF_CFG_DEV2_EPF6_PCIE_ARI_CAP |
16458 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
16459 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
16460 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
16461 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
16462 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
16463 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
16464 | //BIF_CFG_DEV2_EPF6_PCIE_ARI_CNTL |
16465 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
16466 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
16467 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
16468 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
16469 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
16470 | #define BIF_CFG_DEV2_EPF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
16471 | //BIF_CFG_DEV2_EPF6_PCIE_RTR_ENH_CAP_LIST |
16472 | #define BIF_CFG_DEV2_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
16473 | #define BIF_CFG_DEV2_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
16474 | #define BIF_CFG_DEV2_EPF6_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
16475 | #define BIF_CFG_DEV2_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
16476 | #define BIF_CFG_DEV2_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
16477 | #define BIF_CFG_DEV2_EPF6_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
16478 | //BIF_CFG_DEV2_EPF6_RTR_DATA1 |
16479 | #define BIF_CFG_DEV2_EPF6_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
16480 | #define BIF_CFG_DEV2_EPF6_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
16481 | #define BIF_CFG_DEV2_EPF6_RTR_DATA1__VALID__SHIFT 0x1f |
16482 | #define BIF_CFG_DEV2_EPF6_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
16483 | #define BIF_CFG_DEV2_EPF6_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
16484 | #define BIF_CFG_DEV2_EPF6_RTR_DATA1__VALID_MASK 0x80000000L |
16485 | //BIF_CFG_DEV2_EPF6_RTR_DATA2 |
16486 | #define BIF_CFG_DEV2_EPF6_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
16487 | #define BIF_CFG_DEV2_EPF6_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
16488 | #define BIF_CFG_DEV2_EPF6_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
16489 | #define BIF_CFG_DEV2_EPF6_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
16490 | |
16491 | |
16492 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp |
16493 | //BIF_CFG_DEV0_EPF5_VENDOR_ID |
16494 | #define BIF_CFG_DEV0_EPF5_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
16495 | #define BIF_CFG_DEV0_EPF5_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
16496 | //BIF_CFG_DEV0_EPF5_DEVICE_ID |
16497 | #define BIF_CFG_DEV0_EPF5_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
16498 | #define BIF_CFG_DEV0_EPF5_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
16499 | //BIF_CFG_DEV0_EPF5_COMMAND |
16500 | #define BIF_CFG_DEV0_EPF5_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
16501 | #define BIF_CFG_DEV0_EPF5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
16502 | #define BIF_CFG_DEV0_EPF5_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
16503 | #define BIF_CFG_DEV0_EPF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
16504 | #define BIF_CFG_DEV0_EPF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
16505 | #define BIF_CFG_DEV0_EPF5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
16506 | #define BIF_CFG_DEV0_EPF5_COMMAND__AD_STEPPING__SHIFT 0x7 |
16507 | #define BIF_CFG_DEV0_EPF5_COMMAND__SERR_EN__SHIFT 0x8 |
16508 | #define BIF_CFG_DEV0_EPF5_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
16509 | #define BIF_CFG_DEV0_EPF5_COMMAND__INT_DIS__SHIFT 0xa |
16510 | #define BIF_CFG_DEV0_EPF5_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
16511 | #define BIF_CFG_DEV0_EPF5_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
16512 | #define BIF_CFG_DEV0_EPF5_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
16513 | #define BIF_CFG_DEV0_EPF5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
16514 | #define BIF_CFG_DEV0_EPF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
16515 | #define BIF_CFG_DEV0_EPF5_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
16516 | #define BIF_CFG_DEV0_EPF5_COMMAND__AD_STEPPING_MASK 0x0080L |
16517 | #define BIF_CFG_DEV0_EPF5_COMMAND__SERR_EN_MASK 0x0100L |
16518 | #define BIF_CFG_DEV0_EPF5_COMMAND__FAST_B2B_EN_MASK 0x0200L |
16519 | #define BIF_CFG_DEV0_EPF5_COMMAND__INT_DIS_MASK 0x0400L |
16520 | //BIF_CFG_DEV0_EPF5_STATUS |
16521 | #define BIF_CFG_DEV0_EPF5_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
16522 | #define BIF_CFG_DEV0_EPF5_STATUS__INT_STATUS__SHIFT 0x3 |
16523 | #define BIF_CFG_DEV0_EPF5_STATUS__CAP_LIST__SHIFT 0x4 |
16524 | #define BIF_CFG_DEV0_EPF5_STATUS__PCI_66_CAP__SHIFT 0x5 |
16525 | #define BIF_CFG_DEV0_EPF5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
16526 | #define BIF_CFG_DEV0_EPF5_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
16527 | #define BIF_CFG_DEV0_EPF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
16528 | #define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
16529 | #define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
16530 | #define BIF_CFG_DEV0_EPF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
16531 | #define BIF_CFG_DEV0_EPF5_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
16532 | #define BIF_CFG_DEV0_EPF5_STATUS__INT_STATUS_MASK 0x0008L |
16533 | #define BIF_CFG_DEV0_EPF5_STATUS__CAP_LIST_MASK 0x0010L |
16534 | #define BIF_CFG_DEV0_EPF5_STATUS__PCI_66_CAP_MASK 0x0020L |
16535 | #define BIF_CFG_DEV0_EPF5_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
16536 | #define BIF_CFG_DEV0_EPF5_STATUS__DEVSEL_TIMING_MASK 0x0600L |
16537 | #define BIF_CFG_DEV0_EPF5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
16538 | #define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
16539 | #define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
16540 | #define BIF_CFG_DEV0_EPF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
16541 | //BIF_CFG_DEV0_EPF5_REVISION_ID |
16542 | #define BIF_CFG_DEV0_EPF5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
16543 | #define BIF_CFG_DEV0_EPF5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
16544 | #define BIF_CFG_DEV0_EPF5_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
16545 | #define BIF_CFG_DEV0_EPF5_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
16546 | //BIF_CFG_DEV0_EPF5_PROG_INTERFACE |
16547 | #define BIF_CFG_DEV0_EPF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
16548 | #define BIF_CFG_DEV0_EPF5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
16549 | //BIF_CFG_DEV0_EPF5_SUB_CLASS |
16550 | #define BIF_CFG_DEV0_EPF5_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
16551 | #define BIF_CFG_DEV0_EPF5_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
16552 | //BIF_CFG_DEV0_EPF5_BASE_CLASS |
16553 | #define BIF_CFG_DEV0_EPF5_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
16554 | #define BIF_CFG_DEV0_EPF5_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
16555 | //BIF_CFG_DEV0_EPF5_CACHE_LINE |
16556 | #define BIF_CFG_DEV0_EPF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
16557 | #define BIF_CFG_DEV0_EPF5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
16558 | //BIF_CFG_DEV0_EPF5_LATENCY |
16559 | #define BIF_CFG_DEV0_EPF5_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
16560 | #define BIF_CFG_DEV0_EPF5_LATENCY__LATENCY_TIMER_MASK 0xFFL |
16561 | //BIF_CFG_DEV0_EPF5_HEADER |
16562 | #define 0x0 |
16563 | #define 0x7 |
16564 | #define 0x7FL |
16565 | #define 0x80L |
16566 | //BIF_CFG_DEV0_EPF5_BIST |
16567 | #define BIF_CFG_DEV0_EPF5_BIST__BIST_COMP__SHIFT 0x0 |
16568 | #define BIF_CFG_DEV0_EPF5_BIST__BIST_STRT__SHIFT 0x6 |
16569 | #define BIF_CFG_DEV0_EPF5_BIST__BIST_CAP__SHIFT 0x7 |
16570 | #define BIF_CFG_DEV0_EPF5_BIST__BIST_COMP_MASK 0x0FL |
16571 | #define BIF_CFG_DEV0_EPF5_BIST__BIST_STRT_MASK 0x40L |
16572 | #define BIF_CFG_DEV0_EPF5_BIST__BIST_CAP_MASK 0x80L |
16573 | //BIF_CFG_DEV0_EPF5_BASE_ADDR_1 |
16574 | #define BIF_CFG_DEV0_EPF5_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
16575 | #define BIF_CFG_DEV0_EPF5_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
16576 | //BIF_CFG_DEV0_EPF5_BASE_ADDR_2 |
16577 | #define BIF_CFG_DEV0_EPF5_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
16578 | #define BIF_CFG_DEV0_EPF5_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
16579 | //BIF_CFG_DEV0_EPF5_BASE_ADDR_3 |
16580 | #define BIF_CFG_DEV0_EPF5_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
16581 | #define BIF_CFG_DEV0_EPF5_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
16582 | //BIF_CFG_DEV0_EPF5_BASE_ADDR_4 |
16583 | #define BIF_CFG_DEV0_EPF5_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
16584 | #define BIF_CFG_DEV0_EPF5_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
16585 | //BIF_CFG_DEV0_EPF5_BASE_ADDR_5 |
16586 | #define BIF_CFG_DEV0_EPF5_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
16587 | #define BIF_CFG_DEV0_EPF5_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
16588 | //BIF_CFG_DEV0_EPF5_BASE_ADDR_6 |
16589 | #define BIF_CFG_DEV0_EPF5_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
16590 | #define BIF_CFG_DEV0_EPF5_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
16591 | //BIF_CFG_DEV0_EPF5_ADAPTER_ID |
16592 | #define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
16593 | #define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
16594 | #define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
16595 | #define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
16596 | //BIF_CFG_DEV0_EPF5_ROM_BASE_ADDR |
16597 | #define BIF_CFG_DEV0_EPF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
16598 | #define BIF_CFG_DEV0_EPF5_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
16599 | //BIF_CFG_DEV0_EPF5_CAP_PTR |
16600 | #define BIF_CFG_DEV0_EPF5_CAP_PTR__CAP_PTR__SHIFT 0x0 |
16601 | #define BIF_CFG_DEV0_EPF5_CAP_PTR__CAP_PTR_MASK 0xFFL |
16602 | //BIF_CFG_DEV0_EPF5_INTERRUPT_LINE |
16603 | #define BIF_CFG_DEV0_EPF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
16604 | #define BIF_CFG_DEV0_EPF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
16605 | //BIF_CFG_DEV0_EPF5_INTERRUPT_PIN |
16606 | #define BIF_CFG_DEV0_EPF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
16607 | #define BIF_CFG_DEV0_EPF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
16608 | //BIF_CFG_DEV0_EPF5_MIN_GRANT |
16609 | #define BIF_CFG_DEV0_EPF5_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
16610 | #define BIF_CFG_DEV0_EPF5_MIN_GRANT__MIN_GNT_MASK 0xFFL |
16611 | //BIF_CFG_DEV0_EPF5_MAX_LATENCY |
16612 | #define BIF_CFG_DEV0_EPF5_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
16613 | #define BIF_CFG_DEV0_EPF5_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
16614 | //BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST |
16615 | #define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
16616 | #define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
16617 | #define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
16618 | #define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
16619 | #define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
16620 | #define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
16621 | //BIF_CFG_DEV0_EPF5_ADAPTER_ID_W |
16622 | #define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
16623 | #define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
16624 | #define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
16625 | #define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
16626 | //BIF_CFG_DEV0_EPF5_PMI_CAP_LIST |
16627 | #define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
16628 | #define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
16629 | #define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
16630 | #define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
16631 | //BIF_CFG_DEV0_EPF5_PMI_CAP |
16632 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__VERSION__SHIFT 0x0 |
16633 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
16634 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
16635 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
16636 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
16637 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
16638 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
16639 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
16640 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__VERSION_MASK 0x0007L |
16641 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_CLOCK_MASK 0x0008L |
16642 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
16643 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
16644 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
16645 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
16646 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
16647 | #define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
16648 | //BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL |
16649 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
16650 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
16651 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
16652 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
16653 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
16654 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
16655 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
16656 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
16657 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
16658 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
16659 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
16660 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
16661 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
16662 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
16663 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
16664 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
16665 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
16666 | #define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
16667 | //BIF_CFG_DEV0_EPF5_SBRN |
16668 | #define BIF_CFG_DEV0_EPF5_SBRN__SBRN__SHIFT 0x0 |
16669 | #define BIF_CFG_DEV0_EPF5_SBRN__SBRN_MASK 0xFFL |
16670 | //BIF_CFG_DEV0_EPF5_FLADJ |
16671 | #define BIF_CFG_DEV0_EPF5_FLADJ__FLADJ__SHIFT 0x0 |
16672 | #define BIF_CFG_DEV0_EPF5_FLADJ__NFC__SHIFT 0x6 |
16673 | #define BIF_CFG_DEV0_EPF5_FLADJ__FLADJ_MASK 0x3FL |
16674 | #define BIF_CFG_DEV0_EPF5_FLADJ__NFC_MASK 0x40L |
16675 | //BIF_CFG_DEV0_EPF5_DBESL_DBESLD |
16676 | #define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESL__SHIFT 0x0 |
16677 | #define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
16678 | #define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESL_MASK 0x0FL |
16679 | #define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESLD_MASK 0xF0L |
16680 | //BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST |
16681 | #define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
16682 | #define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
16683 | #define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
16684 | #define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
16685 | //BIF_CFG_DEV0_EPF5_PCIE_CAP |
16686 | #define BIF_CFG_DEV0_EPF5_PCIE_CAP__VERSION__SHIFT 0x0 |
16687 | #define BIF_CFG_DEV0_EPF5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
16688 | #define BIF_CFG_DEV0_EPF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
16689 | #define BIF_CFG_DEV0_EPF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
16690 | #define BIF_CFG_DEV0_EPF5_PCIE_CAP__VERSION_MASK 0x000FL |
16691 | #define BIF_CFG_DEV0_EPF5_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
16692 | #define BIF_CFG_DEV0_EPF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
16693 | #define BIF_CFG_DEV0_EPF5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
16694 | //BIF_CFG_DEV0_EPF5_DEVICE_CAP |
16695 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
16696 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
16697 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
16698 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
16699 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
16700 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
16701 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
16702 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
16703 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
16704 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
16705 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
16706 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
16707 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
16708 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
16709 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
16710 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
16711 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
16712 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
16713 | //BIF_CFG_DEV0_EPF5_DEVICE_CNTL |
16714 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
16715 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
16716 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
16717 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
16718 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
16719 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
16720 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
16721 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
16722 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
16723 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
16724 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
16725 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
16726 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
16727 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
16728 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
16729 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
16730 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
16731 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
16732 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
16733 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
16734 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
16735 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
16736 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
16737 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
16738 | //BIF_CFG_DEV0_EPF5_DEVICE_STATUS |
16739 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
16740 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
16741 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
16742 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
16743 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
16744 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
16745 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
16746 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
16747 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
16748 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
16749 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
16750 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
16751 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
16752 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
16753 | //BIF_CFG_DEV0_EPF5_LINK_CAP |
16754 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
16755 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
16756 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
16757 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
16758 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
16759 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
16760 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
16761 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
16762 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
16763 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
16764 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
16765 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
16766 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
16767 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
16768 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
16769 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
16770 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
16771 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
16772 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
16773 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
16774 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
16775 | #define BIF_CFG_DEV0_EPF5_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
16776 | //BIF_CFG_DEV0_EPF5_LINK_CNTL |
16777 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
16778 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
16779 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
16780 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
16781 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
16782 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
16783 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
16784 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
16785 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
16786 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
16787 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
16788 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
16789 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
16790 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
16791 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
16792 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_DIS_MASK 0x0010L |
16793 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
16794 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
16795 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
16796 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
16797 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
16798 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
16799 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
16800 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
16801 | //BIF_CFG_DEV0_EPF5_LINK_STATUS |
16802 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
16803 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
16804 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
16805 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
16806 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
16807 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
16808 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
16809 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
16810 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
16811 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
16812 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
16813 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
16814 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
16815 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
16816 | //BIF_CFG_DEV0_EPF5_DEVICE_CAP2 |
16817 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
16818 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
16819 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
16820 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
16821 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
16822 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
16823 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
16824 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
16825 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
16826 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
16827 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
16828 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
16829 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
16830 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
16831 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
16832 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
16833 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
16834 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
16835 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
16836 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
16837 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
16838 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
16839 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
16840 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
16841 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
16842 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
16843 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
16844 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
16845 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
16846 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
16847 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
16848 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
16849 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
16850 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
16851 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
16852 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
16853 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
16854 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
16855 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
16856 | #define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
16857 | //BIF_CFG_DEV0_EPF5_DEVICE_CNTL2 |
16858 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
16859 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
16860 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
16861 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
16862 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
16863 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
16864 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
16865 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
16866 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
16867 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
16868 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
16869 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
16870 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
16871 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
16872 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
16873 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
16874 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
16875 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
16876 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
16877 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
16878 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
16879 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
16880 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
16881 | #define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
16882 | //BIF_CFG_DEV0_EPF5_DEVICE_STATUS2 |
16883 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
16884 | #define BIF_CFG_DEV0_EPF5_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
16885 | //BIF_CFG_DEV0_EPF5_LINK_CAP2 |
16886 | #define BIF_CFG_DEV0_EPF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
16887 | #define BIF_CFG_DEV0_EPF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
16888 | #define BIF_CFG_DEV0_EPF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
16889 | #define BIF_CFG_DEV0_EPF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
16890 | #define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
16891 | #define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
16892 | #define BIF_CFG_DEV0_EPF5_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
16893 | #define BIF_CFG_DEV0_EPF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
16894 | #define BIF_CFG_DEV0_EPF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
16895 | #define BIF_CFG_DEV0_EPF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
16896 | #define BIF_CFG_DEV0_EPF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
16897 | #define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
16898 | #define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
16899 | #define BIF_CFG_DEV0_EPF5_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
16900 | //BIF_CFG_DEV0_EPF5_LINK_CNTL2 |
16901 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
16902 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
16903 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
16904 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
16905 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
16906 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
16907 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
16908 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
16909 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
16910 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
16911 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
16912 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
16913 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
16914 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
16915 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
16916 | #define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
16917 | //BIF_CFG_DEV0_EPF5_LINK_STATUS2 |
16918 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
16919 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
16920 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
16921 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
16922 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
16923 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
16924 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
16925 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
16926 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
16927 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
16928 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
16929 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
16930 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
16931 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
16932 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
16933 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
16934 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
16935 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
16936 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
16937 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
16938 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
16939 | #define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
16940 | //BIF_CFG_DEV0_EPF5_MSI_CAP_LIST |
16941 | #define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
16942 | #define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
16943 | #define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
16944 | #define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
16945 | //BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL |
16946 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
16947 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
16948 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
16949 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
16950 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
16951 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
16952 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
16953 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
16954 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
16955 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
16956 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
16957 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
16958 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
16959 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
16960 | //BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_LO |
16961 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
16962 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
16963 | //BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_HI |
16964 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
16965 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
16966 | //BIF_CFG_DEV0_EPF5_MSI_MSG_DATA |
16967 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
16968 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
16969 | //BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA |
16970 | #define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
16971 | #define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
16972 | //BIF_CFG_DEV0_EPF5_MSI_MASK |
16973 | #define BIF_CFG_DEV0_EPF5_MSI_MASK__MSI_MASK__SHIFT 0x0 |
16974 | #define BIF_CFG_DEV0_EPF5_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
16975 | //BIF_CFG_DEV0_EPF5_MSI_MSG_DATA_64 |
16976 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
16977 | #define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
16978 | //BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA_64 |
16979 | #define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
16980 | #define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
16981 | //BIF_CFG_DEV0_EPF5_MSI_MASK_64 |
16982 | #define BIF_CFG_DEV0_EPF5_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
16983 | #define BIF_CFG_DEV0_EPF5_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
16984 | //BIF_CFG_DEV0_EPF5_MSI_PENDING |
16985 | #define BIF_CFG_DEV0_EPF5_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
16986 | #define BIF_CFG_DEV0_EPF5_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
16987 | //BIF_CFG_DEV0_EPF5_MSI_PENDING_64 |
16988 | #define BIF_CFG_DEV0_EPF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
16989 | #define BIF_CFG_DEV0_EPF5_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
16990 | //BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST |
16991 | #define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
16992 | #define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
16993 | #define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
16994 | #define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
16995 | //BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL |
16996 | #define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
16997 | #define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
16998 | #define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
16999 | #define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
17000 | #define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
17001 | #define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
17002 | //BIF_CFG_DEV0_EPF5_MSIX_TABLE |
17003 | #define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
17004 | #define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
17005 | #define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
17006 | #define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
17007 | //BIF_CFG_DEV0_EPF5_MSIX_PBA |
17008 | #define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
17009 | #define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
17010 | #define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
17011 | #define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
17012 | //BIF_CFG_DEV0_EPF5_SATA_CAP_0 |
17013 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
17014 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
17015 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
17016 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
17017 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
17018 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
17019 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
17020 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
17021 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
17022 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
17023 | //BIF_CFG_DEV0_EPF5_SATA_CAP_1 |
17024 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
17025 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
17026 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
17027 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
17028 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
17029 | #define BIF_CFG_DEV0_EPF5_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
17030 | //BIF_CFG_DEV0_EPF5_SATA_IDP_INDEX |
17031 | #define BIF_CFG_DEV0_EPF5_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
17032 | #define BIF_CFG_DEV0_EPF5_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
17033 | #define BIF_CFG_DEV0_EPF5_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
17034 | #define BIF_CFG_DEV0_EPF5_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
17035 | #define BIF_CFG_DEV0_EPF5_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
17036 | #define BIF_CFG_DEV0_EPF5_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
17037 | //BIF_CFG_DEV0_EPF5_SATA_IDP_DATA |
17038 | #define BIF_CFG_DEV0_EPF5_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
17039 | #define BIF_CFG_DEV0_EPF5_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
17040 | //BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
17041 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
17042 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
17043 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
17044 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
17045 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
17046 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
17047 | //BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR |
17048 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
17049 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
17050 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
17051 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
17052 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
17053 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
17054 | //BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC1 |
17055 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
17056 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
17057 | //BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC2 |
17058 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
17059 | #define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
17060 | //BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
17061 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
17062 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
17063 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
17064 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
17065 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
17066 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
17067 | //BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS |
17068 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
17069 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
17070 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
17071 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
17072 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
17073 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
17074 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
17075 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
17076 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
17077 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
17078 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
17079 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
17080 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
17081 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
17082 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
17083 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
17084 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
17085 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
17086 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
17087 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
17088 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
17089 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
17090 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
17091 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
17092 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
17093 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
17094 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
17095 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
17096 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
17097 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
17098 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
17099 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
17100 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
17101 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
17102 | //BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK |
17103 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
17104 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
17105 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
17106 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
17107 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
17108 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
17109 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
17110 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
17111 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
17112 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
17113 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
17114 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
17115 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
17116 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
17117 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
17118 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
17119 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
17120 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
17121 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
17122 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
17123 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
17124 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
17125 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
17126 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
17127 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
17128 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
17129 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
17130 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
17131 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
17132 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
17133 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
17134 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
17135 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
17136 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
17137 | //BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY |
17138 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
17139 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
17140 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
17141 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
17142 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
17143 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
17144 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
17145 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
17146 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
17147 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
17148 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
17149 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
17150 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
17151 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
17152 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
17153 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
17154 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
17155 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
17156 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
17157 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
17158 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
17159 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
17160 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
17161 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
17162 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
17163 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
17164 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
17165 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
17166 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
17167 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
17168 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
17169 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
17170 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
17171 | #define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
17172 | //BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS |
17173 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
17174 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
17175 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
17176 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
17177 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
17178 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
17179 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
17180 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
17181 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
17182 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
17183 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
17184 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
17185 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
17186 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
17187 | //BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK |
17188 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
17189 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
17190 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
17191 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
17192 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
17193 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
17194 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
17195 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
17196 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
17197 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
17198 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
17199 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
17200 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
17201 | #define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
17202 | //BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL |
17203 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
17204 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
17205 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
17206 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
17207 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
17208 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
17209 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
17210 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
17211 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
17212 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
17213 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
17214 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
17215 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
17216 | #define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
17217 | //BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG0 |
17218 | #define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
17219 | #define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
17220 | //BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG1 |
17221 | #define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
17222 | #define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
17223 | //BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG2 |
17224 | #define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
17225 | #define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
17226 | //BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG3 |
17227 | #define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
17228 | #define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
17229 | //BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG0 |
17230 | #define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
17231 | #define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
17232 | //BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG1 |
17233 | #define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
17234 | #define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
17235 | //BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG2 |
17236 | #define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
17237 | #define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
17238 | //BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG3 |
17239 | #define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
17240 | #define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
17241 | //BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST |
17242 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
17243 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
17244 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
17245 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
17246 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
17247 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
17248 | //BIF_CFG_DEV0_EPF5_PCIE_BAR1_CAP |
17249 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
17250 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
17251 | //BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL |
17252 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
17253 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
17254 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
17255 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
17256 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
17257 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
17258 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
17259 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
17260 | //BIF_CFG_DEV0_EPF5_PCIE_BAR2_CAP |
17261 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
17262 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
17263 | //BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL |
17264 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
17265 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
17266 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
17267 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
17268 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
17269 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
17270 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
17271 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
17272 | //BIF_CFG_DEV0_EPF5_PCIE_BAR3_CAP |
17273 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
17274 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
17275 | //BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL |
17276 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
17277 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
17278 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
17279 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
17280 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
17281 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
17282 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
17283 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
17284 | //BIF_CFG_DEV0_EPF5_PCIE_BAR4_CAP |
17285 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
17286 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
17287 | //BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL |
17288 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
17289 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
17290 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
17291 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
17292 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
17293 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
17294 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
17295 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
17296 | //BIF_CFG_DEV0_EPF5_PCIE_BAR5_CAP |
17297 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
17298 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
17299 | //BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL |
17300 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
17301 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
17302 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
17303 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
17304 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
17305 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
17306 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
17307 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
17308 | //BIF_CFG_DEV0_EPF5_PCIE_BAR6_CAP |
17309 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
17310 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
17311 | //BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL |
17312 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
17313 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
17314 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
17315 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
17316 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
17317 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
17318 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
17319 | #define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
17320 | //BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST |
17321 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
17322 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
17323 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
17324 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
17325 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
17326 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
17327 | //BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA_SELECT |
17328 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
17329 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
17330 | //BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA |
17331 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
17332 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
17333 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
17334 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
17335 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
17336 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
17337 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
17338 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
17339 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
17340 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
17341 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
17342 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
17343 | //BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_CAP |
17344 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
17345 | #define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
17346 | //BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST |
17347 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
17348 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
17349 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
17350 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
17351 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
17352 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
17353 | //BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP |
17354 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
17355 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
17356 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
17357 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
17358 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
17359 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
17360 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
17361 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
17362 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
17363 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
17364 | //BIF_CFG_DEV0_EPF5_PCIE_DPA_LATENCY_INDICATOR |
17365 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
17366 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
17367 | //BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS |
17368 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
17369 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
17370 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
17371 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
17372 | //BIF_CFG_DEV0_EPF5_PCIE_DPA_CNTL |
17373 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
17374 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
17375 | //BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
17376 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
17377 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
17378 | //BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
17379 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
17380 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
17381 | //BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
17382 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
17383 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
17384 | //BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
17385 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
17386 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
17387 | //BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
17388 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
17389 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
17390 | //BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
17391 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
17392 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
17393 | //BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
17394 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
17395 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
17396 | //BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
17397 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
17398 | #define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
17399 | //BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST |
17400 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
17401 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
17402 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
17403 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
17404 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
17405 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
17406 | //BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP |
17407 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
17408 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
17409 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
17410 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
17411 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
17412 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
17413 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
17414 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
17415 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
17416 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
17417 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
17418 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
17419 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
17420 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
17421 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
17422 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
17423 | //BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL |
17424 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
17425 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
17426 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
17427 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
17428 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
17429 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
17430 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
17431 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
17432 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
17433 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
17434 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
17435 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
17436 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
17437 | #define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
17438 | //BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST |
17439 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
17440 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
17441 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
17442 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
17443 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
17444 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
17445 | //BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP |
17446 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
17447 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
17448 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
17449 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
17450 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
17451 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
17452 | //BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL |
17453 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
17454 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
17455 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
17456 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
17457 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
17458 | #define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
17459 | //BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST |
17460 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
17461 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
17462 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
17463 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
17464 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
17465 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
17466 | //BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP |
17467 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
17468 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
17469 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
17470 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
17471 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
17472 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
17473 | //BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL |
17474 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
17475 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
17476 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
17477 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
17478 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
17479 | #define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
17480 | //BIF_CFG_DEV0_EPF5_PCIE_RTR_ENH_CAP_LIST |
17481 | #define BIF_CFG_DEV0_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
17482 | #define BIF_CFG_DEV0_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
17483 | #define BIF_CFG_DEV0_EPF5_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
17484 | #define BIF_CFG_DEV0_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
17485 | #define BIF_CFG_DEV0_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
17486 | #define BIF_CFG_DEV0_EPF5_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
17487 | //BIF_CFG_DEV0_EPF5_RTR_DATA1 |
17488 | #define BIF_CFG_DEV0_EPF5_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
17489 | #define BIF_CFG_DEV0_EPF5_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
17490 | #define BIF_CFG_DEV0_EPF5_RTR_DATA1__VALID__SHIFT 0x1f |
17491 | #define BIF_CFG_DEV0_EPF5_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
17492 | #define BIF_CFG_DEV0_EPF5_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
17493 | #define BIF_CFG_DEV0_EPF5_RTR_DATA1__VALID_MASK 0x80000000L |
17494 | //BIF_CFG_DEV0_EPF5_RTR_DATA2 |
17495 | #define BIF_CFG_DEV0_EPF5_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
17496 | #define BIF_CFG_DEV0_EPF5_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
17497 | #define BIF_CFG_DEV0_EPF5_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
17498 | #define BIF_CFG_DEV0_EPF5_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
17499 | |
17500 | |
17501 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp |
17502 | //BIF_CFG_DEV1_EPF1_VENDOR_ID |
17503 | #define BIF_CFG_DEV1_EPF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
17504 | #define BIF_CFG_DEV1_EPF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
17505 | //BIF_CFG_DEV1_EPF1_DEVICE_ID |
17506 | #define BIF_CFG_DEV1_EPF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
17507 | #define BIF_CFG_DEV1_EPF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
17508 | //BIF_CFG_DEV1_EPF1_COMMAND |
17509 | #define BIF_CFG_DEV1_EPF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
17510 | #define BIF_CFG_DEV1_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
17511 | #define BIF_CFG_DEV1_EPF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
17512 | #define BIF_CFG_DEV1_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
17513 | #define BIF_CFG_DEV1_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
17514 | #define BIF_CFG_DEV1_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
17515 | #define BIF_CFG_DEV1_EPF1_COMMAND__AD_STEPPING__SHIFT 0x7 |
17516 | #define BIF_CFG_DEV1_EPF1_COMMAND__SERR_EN__SHIFT 0x8 |
17517 | #define BIF_CFG_DEV1_EPF1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
17518 | #define BIF_CFG_DEV1_EPF1_COMMAND__INT_DIS__SHIFT 0xa |
17519 | #define BIF_CFG_DEV1_EPF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
17520 | #define BIF_CFG_DEV1_EPF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
17521 | #define BIF_CFG_DEV1_EPF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
17522 | #define BIF_CFG_DEV1_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
17523 | #define BIF_CFG_DEV1_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
17524 | #define BIF_CFG_DEV1_EPF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
17525 | #define BIF_CFG_DEV1_EPF1_COMMAND__AD_STEPPING_MASK 0x0080L |
17526 | #define BIF_CFG_DEV1_EPF1_COMMAND__SERR_EN_MASK 0x0100L |
17527 | #define BIF_CFG_DEV1_EPF1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
17528 | #define BIF_CFG_DEV1_EPF1_COMMAND__INT_DIS_MASK 0x0400L |
17529 | //BIF_CFG_DEV1_EPF1_STATUS |
17530 | #define BIF_CFG_DEV1_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
17531 | #define BIF_CFG_DEV1_EPF1_STATUS__INT_STATUS__SHIFT 0x3 |
17532 | #define BIF_CFG_DEV1_EPF1_STATUS__CAP_LIST__SHIFT 0x4 |
17533 | #define BIF_CFG_DEV1_EPF1_STATUS__PCI_66_CAP__SHIFT 0x5 |
17534 | #define BIF_CFG_DEV1_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
17535 | #define BIF_CFG_DEV1_EPF1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
17536 | #define BIF_CFG_DEV1_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
17537 | #define BIF_CFG_DEV1_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
17538 | #define BIF_CFG_DEV1_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
17539 | #define BIF_CFG_DEV1_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
17540 | #define BIF_CFG_DEV1_EPF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
17541 | #define BIF_CFG_DEV1_EPF1_STATUS__INT_STATUS_MASK 0x0008L |
17542 | #define BIF_CFG_DEV1_EPF1_STATUS__CAP_LIST_MASK 0x0010L |
17543 | #define BIF_CFG_DEV1_EPF1_STATUS__PCI_66_CAP_MASK 0x0020L |
17544 | #define BIF_CFG_DEV1_EPF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
17545 | #define BIF_CFG_DEV1_EPF1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
17546 | #define BIF_CFG_DEV1_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
17547 | #define BIF_CFG_DEV1_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
17548 | #define BIF_CFG_DEV1_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
17549 | #define BIF_CFG_DEV1_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
17550 | //BIF_CFG_DEV1_EPF1_REVISION_ID |
17551 | #define BIF_CFG_DEV1_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
17552 | #define BIF_CFG_DEV1_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
17553 | #define BIF_CFG_DEV1_EPF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
17554 | #define BIF_CFG_DEV1_EPF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
17555 | //BIF_CFG_DEV1_EPF1_PROG_INTERFACE |
17556 | #define BIF_CFG_DEV1_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
17557 | #define BIF_CFG_DEV1_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
17558 | //BIF_CFG_DEV1_EPF1_SUB_CLASS |
17559 | #define BIF_CFG_DEV1_EPF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
17560 | #define BIF_CFG_DEV1_EPF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
17561 | //BIF_CFG_DEV1_EPF1_BASE_CLASS |
17562 | #define BIF_CFG_DEV1_EPF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
17563 | #define BIF_CFG_DEV1_EPF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
17564 | //BIF_CFG_DEV1_EPF1_CACHE_LINE |
17565 | #define BIF_CFG_DEV1_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
17566 | #define BIF_CFG_DEV1_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
17567 | //BIF_CFG_DEV1_EPF1_LATENCY |
17568 | #define BIF_CFG_DEV1_EPF1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
17569 | #define BIF_CFG_DEV1_EPF1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
17570 | //BIF_CFG_DEV1_EPF1_HEADER |
17571 | #define 0x0 |
17572 | #define 0x7 |
17573 | #define 0x7FL |
17574 | #define 0x80L |
17575 | //BIF_CFG_DEV1_EPF1_BIST |
17576 | #define BIF_CFG_DEV1_EPF1_BIST__BIST_COMP__SHIFT 0x0 |
17577 | #define BIF_CFG_DEV1_EPF1_BIST__BIST_STRT__SHIFT 0x6 |
17578 | #define BIF_CFG_DEV1_EPF1_BIST__BIST_CAP__SHIFT 0x7 |
17579 | #define BIF_CFG_DEV1_EPF1_BIST__BIST_COMP_MASK 0x0FL |
17580 | #define BIF_CFG_DEV1_EPF1_BIST__BIST_STRT_MASK 0x40L |
17581 | #define BIF_CFG_DEV1_EPF1_BIST__BIST_CAP_MASK 0x80L |
17582 | //BIF_CFG_DEV1_EPF1_BASE_ADDR_1 |
17583 | #define BIF_CFG_DEV1_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
17584 | #define BIF_CFG_DEV1_EPF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
17585 | //BIF_CFG_DEV1_EPF1_BASE_ADDR_2 |
17586 | #define BIF_CFG_DEV1_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
17587 | #define BIF_CFG_DEV1_EPF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
17588 | //BIF_CFG_DEV1_EPF1_BASE_ADDR_3 |
17589 | #define BIF_CFG_DEV1_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
17590 | #define BIF_CFG_DEV1_EPF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
17591 | //BIF_CFG_DEV1_EPF1_BASE_ADDR_4 |
17592 | #define BIF_CFG_DEV1_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
17593 | #define BIF_CFG_DEV1_EPF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
17594 | //BIF_CFG_DEV1_EPF1_BASE_ADDR_5 |
17595 | #define BIF_CFG_DEV1_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
17596 | #define BIF_CFG_DEV1_EPF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
17597 | //BIF_CFG_DEV1_EPF1_BASE_ADDR_6 |
17598 | #define BIF_CFG_DEV1_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
17599 | #define BIF_CFG_DEV1_EPF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
17600 | //BIF_CFG_DEV1_EPF1_ADAPTER_ID |
17601 | #define BIF_CFG_DEV1_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
17602 | #define BIF_CFG_DEV1_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
17603 | #define BIF_CFG_DEV1_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
17604 | #define BIF_CFG_DEV1_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
17605 | //BIF_CFG_DEV1_EPF1_ROM_BASE_ADDR |
17606 | #define BIF_CFG_DEV1_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
17607 | #define BIF_CFG_DEV1_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
17608 | //BIF_CFG_DEV1_EPF1_CAP_PTR |
17609 | #define BIF_CFG_DEV1_EPF1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
17610 | #define BIF_CFG_DEV1_EPF1_CAP_PTR__CAP_PTR_MASK 0xFFL |
17611 | //BIF_CFG_DEV1_EPF1_INTERRUPT_LINE |
17612 | #define BIF_CFG_DEV1_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
17613 | #define BIF_CFG_DEV1_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
17614 | //BIF_CFG_DEV1_EPF1_INTERRUPT_PIN |
17615 | #define BIF_CFG_DEV1_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
17616 | #define BIF_CFG_DEV1_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
17617 | //BIF_CFG_DEV1_EPF1_MIN_GRANT |
17618 | #define BIF_CFG_DEV1_EPF1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
17619 | #define BIF_CFG_DEV1_EPF1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
17620 | //BIF_CFG_DEV1_EPF1_MAX_LATENCY |
17621 | #define BIF_CFG_DEV1_EPF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
17622 | #define BIF_CFG_DEV1_EPF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
17623 | //BIF_CFG_DEV1_EPF1_VENDOR_CAP_LIST |
17624 | #define BIF_CFG_DEV1_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
17625 | #define BIF_CFG_DEV1_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
17626 | #define BIF_CFG_DEV1_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
17627 | #define BIF_CFG_DEV1_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
17628 | #define BIF_CFG_DEV1_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
17629 | #define BIF_CFG_DEV1_EPF1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
17630 | //BIF_CFG_DEV1_EPF1_ADAPTER_ID_W |
17631 | #define BIF_CFG_DEV1_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
17632 | #define BIF_CFG_DEV1_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
17633 | #define BIF_CFG_DEV1_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
17634 | #define BIF_CFG_DEV1_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
17635 | //BIF_CFG_DEV1_EPF1_PMI_CAP_LIST |
17636 | #define BIF_CFG_DEV1_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
17637 | #define BIF_CFG_DEV1_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
17638 | #define BIF_CFG_DEV1_EPF1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
17639 | #define BIF_CFG_DEV1_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
17640 | //BIF_CFG_DEV1_EPF1_PMI_CAP |
17641 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__VERSION__SHIFT 0x0 |
17642 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
17643 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
17644 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
17645 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
17646 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
17647 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
17648 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
17649 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__VERSION_MASK 0x0007L |
17650 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
17651 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
17652 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
17653 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
17654 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
17655 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
17656 | #define BIF_CFG_DEV1_EPF1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
17657 | //BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL |
17658 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
17659 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
17660 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
17661 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
17662 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
17663 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
17664 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
17665 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
17666 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
17667 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
17668 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
17669 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
17670 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
17671 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
17672 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
17673 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
17674 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
17675 | #define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
17676 | //BIF_CFG_DEV1_EPF1_SBRN |
17677 | #define BIF_CFG_DEV1_EPF1_SBRN__SBRN__SHIFT 0x0 |
17678 | #define BIF_CFG_DEV1_EPF1_SBRN__SBRN_MASK 0xFFL |
17679 | //BIF_CFG_DEV1_EPF1_FLADJ |
17680 | #define BIF_CFG_DEV1_EPF1_FLADJ__FLADJ__SHIFT 0x0 |
17681 | #define BIF_CFG_DEV1_EPF1_FLADJ__NFC__SHIFT 0x6 |
17682 | #define BIF_CFG_DEV1_EPF1_FLADJ__FLADJ_MASK 0x3FL |
17683 | #define BIF_CFG_DEV1_EPF1_FLADJ__NFC_MASK 0x40L |
17684 | //BIF_CFG_DEV1_EPF1_DBESL_DBESLD |
17685 | #define BIF_CFG_DEV1_EPF1_DBESL_DBESLD__DBESL__SHIFT 0x0 |
17686 | #define BIF_CFG_DEV1_EPF1_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
17687 | #define BIF_CFG_DEV1_EPF1_DBESL_DBESLD__DBESL_MASK 0x0FL |
17688 | #define BIF_CFG_DEV1_EPF1_DBESL_DBESLD__DBESLD_MASK 0xF0L |
17689 | //BIF_CFG_DEV1_EPF1_PCIE_CAP_LIST |
17690 | #define BIF_CFG_DEV1_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
17691 | #define BIF_CFG_DEV1_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
17692 | #define BIF_CFG_DEV1_EPF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
17693 | #define BIF_CFG_DEV1_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
17694 | //BIF_CFG_DEV1_EPF1_PCIE_CAP |
17695 | #define BIF_CFG_DEV1_EPF1_PCIE_CAP__VERSION__SHIFT 0x0 |
17696 | #define BIF_CFG_DEV1_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
17697 | #define BIF_CFG_DEV1_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
17698 | #define BIF_CFG_DEV1_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
17699 | #define BIF_CFG_DEV1_EPF1_PCIE_CAP__VERSION_MASK 0x000FL |
17700 | #define BIF_CFG_DEV1_EPF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
17701 | #define BIF_CFG_DEV1_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
17702 | #define BIF_CFG_DEV1_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
17703 | //BIF_CFG_DEV1_EPF1_DEVICE_CAP |
17704 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
17705 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
17706 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
17707 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
17708 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
17709 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
17710 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
17711 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
17712 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
17713 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
17714 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
17715 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
17716 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
17717 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
17718 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
17719 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
17720 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
17721 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
17722 | //BIF_CFG_DEV1_EPF1_DEVICE_CNTL |
17723 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
17724 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
17725 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
17726 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
17727 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
17728 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
17729 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
17730 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
17731 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
17732 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
17733 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
17734 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
17735 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
17736 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
17737 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
17738 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
17739 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
17740 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
17741 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
17742 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
17743 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
17744 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
17745 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
17746 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
17747 | //BIF_CFG_DEV1_EPF1_DEVICE_STATUS |
17748 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
17749 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
17750 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
17751 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
17752 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
17753 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
17754 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
17755 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
17756 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
17757 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
17758 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
17759 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
17760 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
17761 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
17762 | //BIF_CFG_DEV1_EPF1_LINK_CAP |
17763 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
17764 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
17765 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
17766 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
17767 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
17768 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
17769 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
17770 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
17771 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
17772 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
17773 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
17774 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
17775 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
17776 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
17777 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
17778 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
17779 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
17780 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
17781 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
17782 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
17783 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
17784 | #define BIF_CFG_DEV1_EPF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
17785 | //BIF_CFG_DEV1_EPF1_LINK_CNTL |
17786 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
17787 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
17788 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
17789 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
17790 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
17791 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
17792 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
17793 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
17794 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
17795 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
17796 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
17797 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
17798 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
17799 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
17800 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
17801 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
17802 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
17803 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
17804 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
17805 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
17806 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
17807 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
17808 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
17809 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
17810 | //BIF_CFG_DEV1_EPF1_LINK_STATUS |
17811 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
17812 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
17813 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
17814 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
17815 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
17816 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
17817 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
17818 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
17819 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
17820 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
17821 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
17822 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
17823 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
17824 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
17825 | //BIF_CFG_DEV1_EPF1_DEVICE_CAP2 |
17826 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
17827 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
17828 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
17829 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
17830 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
17831 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
17832 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
17833 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
17834 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
17835 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
17836 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
17837 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
17838 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
17839 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
17840 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
17841 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
17842 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
17843 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
17844 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
17845 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
17846 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
17847 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
17848 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
17849 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
17850 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
17851 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
17852 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
17853 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
17854 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
17855 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
17856 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
17857 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
17858 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
17859 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
17860 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
17861 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
17862 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
17863 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
17864 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
17865 | #define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
17866 | //BIF_CFG_DEV1_EPF1_DEVICE_CNTL2 |
17867 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
17868 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
17869 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
17870 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
17871 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
17872 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
17873 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
17874 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
17875 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
17876 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
17877 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
17878 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
17879 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
17880 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
17881 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
17882 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
17883 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
17884 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
17885 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
17886 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
17887 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
17888 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
17889 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
17890 | #define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
17891 | //BIF_CFG_DEV1_EPF1_DEVICE_STATUS2 |
17892 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
17893 | #define BIF_CFG_DEV1_EPF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
17894 | //BIF_CFG_DEV1_EPF1_LINK_CAP2 |
17895 | #define BIF_CFG_DEV1_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
17896 | #define BIF_CFG_DEV1_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
17897 | #define BIF_CFG_DEV1_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
17898 | #define BIF_CFG_DEV1_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
17899 | #define BIF_CFG_DEV1_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
17900 | #define BIF_CFG_DEV1_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
17901 | #define BIF_CFG_DEV1_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
17902 | #define BIF_CFG_DEV1_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
17903 | #define BIF_CFG_DEV1_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
17904 | #define BIF_CFG_DEV1_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
17905 | #define BIF_CFG_DEV1_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
17906 | #define BIF_CFG_DEV1_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
17907 | #define BIF_CFG_DEV1_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
17908 | #define BIF_CFG_DEV1_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
17909 | //BIF_CFG_DEV1_EPF1_LINK_CNTL2 |
17910 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
17911 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
17912 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
17913 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
17914 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
17915 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
17916 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
17917 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
17918 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
17919 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
17920 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
17921 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
17922 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
17923 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
17924 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
17925 | #define BIF_CFG_DEV1_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
17926 | //BIF_CFG_DEV1_EPF1_LINK_STATUS2 |
17927 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
17928 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
17929 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
17930 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
17931 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
17932 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
17933 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
17934 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
17935 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
17936 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
17937 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
17938 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
17939 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
17940 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
17941 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
17942 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
17943 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
17944 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
17945 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
17946 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
17947 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
17948 | #define BIF_CFG_DEV1_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
17949 | //BIF_CFG_DEV1_EPF1_MSI_CAP_LIST |
17950 | #define BIF_CFG_DEV1_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
17951 | #define BIF_CFG_DEV1_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
17952 | #define BIF_CFG_DEV1_EPF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
17953 | #define BIF_CFG_DEV1_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
17954 | //BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL |
17955 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
17956 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
17957 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
17958 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
17959 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
17960 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
17961 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
17962 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
17963 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
17964 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
17965 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
17966 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
17967 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
17968 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
17969 | //BIF_CFG_DEV1_EPF1_MSI_MSG_ADDR_LO |
17970 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
17971 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
17972 | //BIF_CFG_DEV1_EPF1_MSI_MSG_ADDR_HI |
17973 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
17974 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
17975 | //BIF_CFG_DEV1_EPF1_MSI_MSG_DATA |
17976 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
17977 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
17978 | //BIF_CFG_DEV1_EPF1_MSI_EXT_MSG_DATA |
17979 | #define BIF_CFG_DEV1_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
17980 | #define BIF_CFG_DEV1_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
17981 | //BIF_CFG_DEV1_EPF1_MSI_MASK |
17982 | #define BIF_CFG_DEV1_EPF1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
17983 | #define BIF_CFG_DEV1_EPF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
17984 | //BIF_CFG_DEV1_EPF1_MSI_MSG_DATA_64 |
17985 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
17986 | #define BIF_CFG_DEV1_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
17987 | //BIF_CFG_DEV1_EPF1_MSI_EXT_MSG_DATA_64 |
17988 | #define BIF_CFG_DEV1_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
17989 | #define BIF_CFG_DEV1_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
17990 | //BIF_CFG_DEV1_EPF1_MSI_MASK_64 |
17991 | #define BIF_CFG_DEV1_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
17992 | #define BIF_CFG_DEV1_EPF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
17993 | //BIF_CFG_DEV1_EPF1_MSI_PENDING |
17994 | #define BIF_CFG_DEV1_EPF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
17995 | #define BIF_CFG_DEV1_EPF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
17996 | //BIF_CFG_DEV1_EPF1_MSI_PENDING_64 |
17997 | #define BIF_CFG_DEV1_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
17998 | #define BIF_CFG_DEV1_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
17999 | //BIF_CFG_DEV1_EPF1_MSIX_CAP_LIST |
18000 | #define BIF_CFG_DEV1_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
18001 | #define BIF_CFG_DEV1_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
18002 | #define BIF_CFG_DEV1_EPF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
18003 | #define BIF_CFG_DEV1_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
18004 | //BIF_CFG_DEV1_EPF1_MSIX_MSG_CNTL |
18005 | #define BIF_CFG_DEV1_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
18006 | #define BIF_CFG_DEV1_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
18007 | #define BIF_CFG_DEV1_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
18008 | #define BIF_CFG_DEV1_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
18009 | #define BIF_CFG_DEV1_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
18010 | #define BIF_CFG_DEV1_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
18011 | //BIF_CFG_DEV1_EPF1_MSIX_TABLE |
18012 | #define BIF_CFG_DEV1_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
18013 | #define BIF_CFG_DEV1_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
18014 | #define BIF_CFG_DEV1_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
18015 | #define BIF_CFG_DEV1_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
18016 | //BIF_CFG_DEV1_EPF1_MSIX_PBA |
18017 | #define BIF_CFG_DEV1_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
18018 | #define BIF_CFG_DEV1_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
18019 | #define BIF_CFG_DEV1_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
18020 | #define BIF_CFG_DEV1_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
18021 | //BIF_CFG_DEV1_EPF1_SATA_CAP_0 |
18022 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
18023 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
18024 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
18025 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
18026 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
18027 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
18028 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
18029 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
18030 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
18031 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
18032 | //BIF_CFG_DEV1_EPF1_SATA_CAP_1 |
18033 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
18034 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
18035 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
18036 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
18037 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
18038 | #define BIF_CFG_DEV1_EPF1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
18039 | //BIF_CFG_DEV1_EPF1_SATA_IDP_INDEX |
18040 | #define BIF_CFG_DEV1_EPF1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
18041 | #define BIF_CFG_DEV1_EPF1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
18042 | #define BIF_CFG_DEV1_EPF1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
18043 | #define BIF_CFG_DEV1_EPF1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
18044 | #define BIF_CFG_DEV1_EPF1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
18045 | #define BIF_CFG_DEV1_EPF1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
18046 | //BIF_CFG_DEV1_EPF1_SATA_IDP_DATA |
18047 | #define BIF_CFG_DEV1_EPF1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
18048 | #define BIF_CFG_DEV1_EPF1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
18049 | //BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
18050 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
18051 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
18052 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
18053 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
18054 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
18055 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
18056 | //BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_HDR |
18057 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
18058 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
18059 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
18060 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
18061 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
18062 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
18063 | //BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC1 |
18064 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
18065 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
18066 | //BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC2 |
18067 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
18068 | #define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
18069 | //BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
18070 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
18071 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
18072 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
18073 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
18074 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
18075 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
18076 | //BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS |
18077 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
18078 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
18079 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
18080 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
18081 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
18082 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
18083 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
18084 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
18085 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
18086 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
18087 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
18088 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
18089 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
18090 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
18091 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
18092 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
18093 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
18094 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
18095 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
18096 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
18097 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
18098 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
18099 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
18100 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
18101 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
18102 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
18103 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
18104 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
18105 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
18106 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
18107 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
18108 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
18109 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
18110 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
18111 | //BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK |
18112 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
18113 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
18114 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
18115 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
18116 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
18117 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
18118 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
18119 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
18120 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
18121 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
18122 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
18123 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
18124 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
18125 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
18126 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
18127 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
18128 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
18129 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
18130 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
18131 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
18132 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
18133 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
18134 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
18135 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
18136 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
18137 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
18138 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
18139 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
18140 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
18141 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
18142 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
18143 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
18144 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
18145 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
18146 | //BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY |
18147 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
18148 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
18149 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
18150 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
18151 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
18152 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
18153 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
18154 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
18155 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
18156 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
18157 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
18158 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
18159 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
18160 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
18161 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
18162 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
18163 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
18164 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
18165 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
18166 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
18167 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
18168 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
18169 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
18170 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
18171 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
18172 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
18173 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
18174 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
18175 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
18176 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
18177 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
18178 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
18179 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
18180 | #define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
18181 | //BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS |
18182 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
18183 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
18184 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
18185 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
18186 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
18187 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
18188 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
18189 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
18190 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
18191 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
18192 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
18193 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
18194 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
18195 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
18196 | //BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK |
18197 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
18198 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
18199 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
18200 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
18201 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
18202 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
18203 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
18204 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
18205 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
18206 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
18207 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
18208 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
18209 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
18210 | #define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
18211 | //BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL |
18212 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
18213 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
18214 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
18215 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
18216 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
18217 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
18218 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
18219 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
18220 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
18221 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
18222 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
18223 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
18224 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
18225 | #define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
18226 | //BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG0 |
18227 | #define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
18228 | #define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
18229 | //BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG1 |
18230 | #define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
18231 | #define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
18232 | //BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG2 |
18233 | #define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
18234 | #define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
18235 | //BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG3 |
18236 | #define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
18237 | #define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
18238 | //BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG0 |
18239 | #define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
18240 | #define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
18241 | //BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG1 |
18242 | #define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
18243 | #define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
18244 | //BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG2 |
18245 | #define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
18246 | #define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
18247 | //BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG3 |
18248 | #define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
18249 | #define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
18250 | //BIF_CFG_DEV1_EPF1_PCIE_BAR_ENH_CAP_LIST |
18251 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
18252 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
18253 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
18254 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
18255 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
18256 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
18257 | //BIF_CFG_DEV1_EPF1_PCIE_BAR1_CAP |
18258 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
18259 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
18260 | //BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL |
18261 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
18262 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
18263 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
18264 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
18265 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
18266 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
18267 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
18268 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
18269 | //BIF_CFG_DEV1_EPF1_PCIE_BAR2_CAP |
18270 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
18271 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
18272 | //BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL |
18273 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
18274 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
18275 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
18276 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
18277 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
18278 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
18279 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
18280 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
18281 | //BIF_CFG_DEV1_EPF1_PCIE_BAR3_CAP |
18282 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
18283 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
18284 | //BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL |
18285 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
18286 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
18287 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
18288 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
18289 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
18290 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
18291 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
18292 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
18293 | //BIF_CFG_DEV1_EPF1_PCIE_BAR4_CAP |
18294 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
18295 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
18296 | //BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL |
18297 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
18298 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
18299 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
18300 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
18301 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
18302 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
18303 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
18304 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
18305 | //BIF_CFG_DEV1_EPF1_PCIE_BAR5_CAP |
18306 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
18307 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
18308 | //BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL |
18309 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
18310 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
18311 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
18312 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
18313 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
18314 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
18315 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
18316 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
18317 | //BIF_CFG_DEV1_EPF1_PCIE_BAR6_CAP |
18318 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
18319 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
18320 | //BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL |
18321 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
18322 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
18323 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
18324 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
18325 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
18326 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
18327 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
18328 | #define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
18329 | //BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
18330 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
18331 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
18332 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
18333 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
18334 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
18335 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
18336 | //BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA_SELECT |
18337 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
18338 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
18339 | //BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA |
18340 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
18341 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
18342 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
18343 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
18344 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
18345 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
18346 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
18347 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
18348 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
18349 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
18350 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
18351 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
18352 | //BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_CAP |
18353 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
18354 | #define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
18355 | //BIF_CFG_DEV1_EPF1_PCIE_DPA_ENH_CAP_LIST |
18356 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
18357 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
18358 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
18359 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
18360 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
18361 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
18362 | //BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP |
18363 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
18364 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
18365 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
18366 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
18367 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
18368 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
18369 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
18370 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
18371 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
18372 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
18373 | //BIF_CFG_DEV1_EPF1_PCIE_DPA_LATENCY_INDICATOR |
18374 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
18375 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
18376 | //BIF_CFG_DEV1_EPF1_PCIE_DPA_STATUS |
18377 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
18378 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
18379 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
18380 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
18381 | //BIF_CFG_DEV1_EPF1_PCIE_DPA_CNTL |
18382 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
18383 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
18384 | //BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
18385 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
18386 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
18387 | //BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
18388 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
18389 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
18390 | //BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
18391 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
18392 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
18393 | //BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
18394 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
18395 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
18396 | //BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
18397 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
18398 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
18399 | //BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
18400 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
18401 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
18402 | //BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
18403 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
18404 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
18405 | //BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
18406 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
18407 | #define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
18408 | //BIF_CFG_DEV1_EPF1_PCIE_ACS_ENH_CAP_LIST |
18409 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
18410 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
18411 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
18412 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
18413 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
18414 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
18415 | //BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP |
18416 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
18417 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
18418 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
18419 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
18420 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
18421 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
18422 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
18423 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
18424 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
18425 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
18426 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
18427 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
18428 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
18429 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
18430 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
18431 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
18432 | //BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL |
18433 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
18434 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
18435 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
18436 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
18437 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
18438 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
18439 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
18440 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
18441 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
18442 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
18443 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
18444 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
18445 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
18446 | #define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
18447 | //BIF_CFG_DEV1_EPF1_PCIE_PASID_ENH_CAP_LIST |
18448 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
18449 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
18450 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
18451 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
18452 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
18453 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
18454 | //BIF_CFG_DEV1_EPF1_PCIE_PASID_CAP |
18455 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
18456 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
18457 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
18458 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
18459 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
18460 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
18461 | //BIF_CFG_DEV1_EPF1_PCIE_PASID_CNTL |
18462 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
18463 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
18464 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
18465 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
18466 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
18467 | #define BIF_CFG_DEV1_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
18468 | //BIF_CFG_DEV1_EPF1_PCIE_ARI_ENH_CAP_LIST |
18469 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
18470 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
18471 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
18472 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
18473 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
18474 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
18475 | //BIF_CFG_DEV1_EPF1_PCIE_ARI_CAP |
18476 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
18477 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
18478 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
18479 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
18480 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
18481 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
18482 | //BIF_CFG_DEV1_EPF1_PCIE_ARI_CNTL |
18483 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
18484 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
18485 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
18486 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
18487 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
18488 | #define BIF_CFG_DEV1_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
18489 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_ENH_CAP_LIST |
18490 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
18491 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
18492 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
18493 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
18494 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
18495 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
18496 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CAP |
18497 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
18498 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 |
18499 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
18500 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L |
18501 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL |
18502 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
18503 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
18504 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
18505 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 |
18506 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
18507 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
18508 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
18509 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L |
18510 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_STATUS |
18511 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_INITIAL_VFS |
18512 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
18513 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
18514 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_TOTAL_VFS |
18515 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
18516 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
18517 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_NUM_VFS |
18518 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
18519 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
18520 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_FUNC_DEP_LINK |
18521 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
18522 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL |
18523 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET |
18524 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
18525 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
18526 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_STRIDE |
18527 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
18528 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
18529 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_DEVICE_ID |
18530 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
18531 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
18532 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
18533 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
18534 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
18535 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
18536 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
18537 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
18538 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 |
18539 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
18540 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
18541 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 |
18542 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
18543 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
18544 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 |
18545 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
18546 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
18547 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 |
18548 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
18549 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
18550 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 |
18551 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
18552 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
18553 | //BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 |
18554 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
18555 | #define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
18556 | //BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST |
18557 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
18558 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
18559 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
18560 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
18561 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
18562 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
18563 | //BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CAP |
18564 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
18565 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
18566 | //BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL |
18567 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
18568 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
18569 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
18570 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
18571 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
18572 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
18573 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
18574 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
18575 | //BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CAP |
18576 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
18577 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
18578 | //BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL |
18579 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
18580 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
18581 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
18582 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
18583 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
18584 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
18585 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
18586 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
18587 | //BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CAP |
18588 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
18589 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
18590 | //BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL |
18591 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
18592 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
18593 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
18594 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
18595 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
18596 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
18597 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
18598 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
18599 | //BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CAP |
18600 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
18601 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
18602 | //BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL |
18603 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
18604 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
18605 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
18606 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
18607 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
18608 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
18609 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
18610 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
18611 | //BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CAP |
18612 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
18613 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
18614 | //BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL |
18615 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
18616 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
18617 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
18618 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
18619 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
18620 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
18621 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
18622 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
18623 | //BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CAP |
18624 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
18625 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
18626 | //BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL |
18627 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
18628 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
18629 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
18630 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
18631 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
18632 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
18633 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
18634 | #define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
18635 | //BIF_CFG_DEV1_EPF1_PCIE_RTR_ENH_CAP_LIST |
18636 | #define BIF_CFG_DEV1_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
18637 | #define BIF_CFG_DEV1_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
18638 | #define BIF_CFG_DEV1_EPF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
18639 | #define BIF_CFG_DEV1_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
18640 | #define BIF_CFG_DEV1_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
18641 | #define BIF_CFG_DEV1_EPF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
18642 | //BIF_CFG_DEV1_EPF1_RTR_DATA1 |
18643 | #define BIF_CFG_DEV1_EPF1_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
18644 | #define BIF_CFG_DEV1_EPF1_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
18645 | #define BIF_CFG_DEV1_EPF1_RTR_DATA1__VALID__SHIFT 0x1f |
18646 | #define BIF_CFG_DEV1_EPF1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
18647 | #define BIF_CFG_DEV1_EPF1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
18648 | #define BIF_CFG_DEV1_EPF1_RTR_DATA1__VALID_MASK 0x80000000L |
18649 | //BIF_CFG_DEV1_EPF1_RTR_DATA2 |
18650 | #define BIF_CFG_DEV1_EPF1_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
18651 | #define BIF_CFG_DEV1_EPF1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
18652 | #define BIF_CFG_DEV1_EPF1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
18653 | #define BIF_CFG_DEV1_EPF1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
18654 | |
18655 | |
18656 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp |
18657 | //BIF_CFG_DEV0_EPF6_VENDOR_ID |
18658 | #define BIF_CFG_DEV0_EPF6_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
18659 | #define BIF_CFG_DEV0_EPF6_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
18660 | //BIF_CFG_DEV0_EPF6_DEVICE_ID |
18661 | #define BIF_CFG_DEV0_EPF6_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
18662 | #define BIF_CFG_DEV0_EPF6_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
18663 | //BIF_CFG_DEV0_EPF6_COMMAND |
18664 | #define BIF_CFG_DEV0_EPF6_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
18665 | #define BIF_CFG_DEV0_EPF6_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
18666 | #define BIF_CFG_DEV0_EPF6_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
18667 | #define BIF_CFG_DEV0_EPF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
18668 | #define BIF_CFG_DEV0_EPF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
18669 | #define BIF_CFG_DEV0_EPF6_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
18670 | #define BIF_CFG_DEV0_EPF6_COMMAND__AD_STEPPING__SHIFT 0x7 |
18671 | #define BIF_CFG_DEV0_EPF6_COMMAND__SERR_EN__SHIFT 0x8 |
18672 | #define BIF_CFG_DEV0_EPF6_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
18673 | #define BIF_CFG_DEV0_EPF6_COMMAND__INT_DIS__SHIFT 0xa |
18674 | #define BIF_CFG_DEV0_EPF6_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
18675 | #define BIF_CFG_DEV0_EPF6_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
18676 | #define BIF_CFG_DEV0_EPF6_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
18677 | #define BIF_CFG_DEV0_EPF6_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
18678 | #define BIF_CFG_DEV0_EPF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
18679 | #define BIF_CFG_DEV0_EPF6_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
18680 | #define BIF_CFG_DEV0_EPF6_COMMAND__AD_STEPPING_MASK 0x0080L |
18681 | #define BIF_CFG_DEV0_EPF6_COMMAND__SERR_EN_MASK 0x0100L |
18682 | #define BIF_CFG_DEV0_EPF6_COMMAND__FAST_B2B_EN_MASK 0x0200L |
18683 | #define BIF_CFG_DEV0_EPF6_COMMAND__INT_DIS_MASK 0x0400L |
18684 | //BIF_CFG_DEV0_EPF6_STATUS |
18685 | #define BIF_CFG_DEV0_EPF6_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
18686 | #define BIF_CFG_DEV0_EPF6_STATUS__INT_STATUS__SHIFT 0x3 |
18687 | #define BIF_CFG_DEV0_EPF6_STATUS__CAP_LIST__SHIFT 0x4 |
18688 | #define BIF_CFG_DEV0_EPF6_STATUS__PCI_66_CAP__SHIFT 0x5 |
18689 | #define BIF_CFG_DEV0_EPF6_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
18690 | #define BIF_CFG_DEV0_EPF6_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
18691 | #define BIF_CFG_DEV0_EPF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
18692 | #define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
18693 | #define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
18694 | #define BIF_CFG_DEV0_EPF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
18695 | #define BIF_CFG_DEV0_EPF6_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
18696 | #define BIF_CFG_DEV0_EPF6_STATUS__INT_STATUS_MASK 0x0008L |
18697 | #define BIF_CFG_DEV0_EPF6_STATUS__CAP_LIST_MASK 0x0010L |
18698 | #define BIF_CFG_DEV0_EPF6_STATUS__PCI_66_CAP_MASK 0x0020L |
18699 | #define BIF_CFG_DEV0_EPF6_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
18700 | #define BIF_CFG_DEV0_EPF6_STATUS__DEVSEL_TIMING_MASK 0x0600L |
18701 | #define BIF_CFG_DEV0_EPF6_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
18702 | #define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
18703 | #define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
18704 | #define BIF_CFG_DEV0_EPF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
18705 | //BIF_CFG_DEV0_EPF6_REVISION_ID |
18706 | #define BIF_CFG_DEV0_EPF6_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
18707 | #define BIF_CFG_DEV0_EPF6_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
18708 | #define BIF_CFG_DEV0_EPF6_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
18709 | #define BIF_CFG_DEV0_EPF6_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
18710 | //BIF_CFG_DEV0_EPF6_PROG_INTERFACE |
18711 | #define BIF_CFG_DEV0_EPF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
18712 | #define BIF_CFG_DEV0_EPF6_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
18713 | //BIF_CFG_DEV0_EPF6_SUB_CLASS |
18714 | #define BIF_CFG_DEV0_EPF6_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
18715 | #define BIF_CFG_DEV0_EPF6_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
18716 | //BIF_CFG_DEV0_EPF6_BASE_CLASS |
18717 | #define BIF_CFG_DEV0_EPF6_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
18718 | #define BIF_CFG_DEV0_EPF6_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
18719 | //BIF_CFG_DEV0_EPF6_CACHE_LINE |
18720 | #define BIF_CFG_DEV0_EPF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
18721 | #define BIF_CFG_DEV0_EPF6_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
18722 | //BIF_CFG_DEV0_EPF6_LATENCY |
18723 | #define BIF_CFG_DEV0_EPF6_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
18724 | #define BIF_CFG_DEV0_EPF6_LATENCY__LATENCY_TIMER_MASK 0xFFL |
18725 | //BIF_CFG_DEV0_EPF6_HEADER |
18726 | #define 0x0 |
18727 | #define 0x7 |
18728 | #define 0x7FL |
18729 | #define 0x80L |
18730 | //BIF_CFG_DEV0_EPF6_BIST |
18731 | #define BIF_CFG_DEV0_EPF6_BIST__BIST_COMP__SHIFT 0x0 |
18732 | #define BIF_CFG_DEV0_EPF6_BIST__BIST_STRT__SHIFT 0x6 |
18733 | #define BIF_CFG_DEV0_EPF6_BIST__BIST_CAP__SHIFT 0x7 |
18734 | #define BIF_CFG_DEV0_EPF6_BIST__BIST_COMP_MASK 0x0FL |
18735 | #define BIF_CFG_DEV0_EPF6_BIST__BIST_STRT_MASK 0x40L |
18736 | #define BIF_CFG_DEV0_EPF6_BIST__BIST_CAP_MASK 0x80L |
18737 | //BIF_CFG_DEV0_EPF6_BASE_ADDR_1 |
18738 | #define BIF_CFG_DEV0_EPF6_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
18739 | #define BIF_CFG_DEV0_EPF6_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
18740 | //BIF_CFG_DEV0_EPF6_BASE_ADDR_2 |
18741 | #define BIF_CFG_DEV0_EPF6_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
18742 | #define BIF_CFG_DEV0_EPF6_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
18743 | //BIF_CFG_DEV0_EPF6_BASE_ADDR_3 |
18744 | #define BIF_CFG_DEV0_EPF6_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
18745 | #define BIF_CFG_DEV0_EPF6_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
18746 | //BIF_CFG_DEV0_EPF6_BASE_ADDR_4 |
18747 | #define BIF_CFG_DEV0_EPF6_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
18748 | #define BIF_CFG_DEV0_EPF6_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
18749 | //BIF_CFG_DEV0_EPF6_BASE_ADDR_5 |
18750 | #define BIF_CFG_DEV0_EPF6_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
18751 | #define BIF_CFG_DEV0_EPF6_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
18752 | //BIF_CFG_DEV0_EPF6_BASE_ADDR_6 |
18753 | #define BIF_CFG_DEV0_EPF6_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
18754 | #define BIF_CFG_DEV0_EPF6_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
18755 | //BIF_CFG_DEV0_EPF6_ADAPTER_ID |
18756 | #define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
18757 | #define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
18758 | #define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
18759 | #define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
18760 | //BIF_CFG_DEV0_EPF6_ROM_BASE_ADDR |
18761 | #define BIF_CFG_DEV0_EPF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
18762 | #define BIF_CFG_DEV0_EPF6_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
18763 | //BIF_CFG_DEV0_EPF6_CAP_PTR |
18764 | #define BIF_CFG_DEV0_EPF6_CAP_PTR__CAP_PTR__SHIFT 0x0 |
18765 | #define BIF_CFG_DEV0_EPF6_CAP_PTR__CAP_PTR_MASK 0xFFL |
18766 | //BIF_CFG_DEV0_EPF6_INTERRUPT_LINE |
18767 | #define BIF_CFG_DEV0_EPF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
18768 | #define BIF_CFG_DEV0_EPF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
18769 | //BIF_CFG_DEV0_EPF6_INTERRUPT_PIN |
18770 | #define BIF_CFG_DEV0_EPF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
18771 | #define BIF_CFG_DEV0_EPF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
18772 | //BIF_CFG_DEV0_EPF6_MIN_GRANT |
18773 | #define BIF_CFG_DEV0_EPF6_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
18774 | #define BIF_CFG_DEV0_EPF6_MIN_GRANT__MIN_GNT_MASK 0xFFL |
18775 | //BIF_CFG_DEV0_EPF6_MAX_LATENCY |
18776 | #define BIF_CFG_DEV0_EPF6_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
18777 | #define BIF_CFG_DEV0_EPF6_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
18778 | //BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST |
18779 | #define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
18780 | #define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
18781 | #define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
18782 | #define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
18783 | #define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
18784 | #define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
18785 | //BIF_CFG_DEV0_EPF6_ADAPTER_ID_W |
18786 | #define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
18787 | #define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
18788 | #define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
18789 | #define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
18790 | //BIF_CFG_DEV0_EPF6_PMI_CAP_LIST |
18791 | #define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
18792 | #define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
18793 | #define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
18794 | #define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
18795 | //BIF_CFG_DEV0_EPF6_PMI_CAP |
18796 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__VERSION__SHIFT 0x0 |
18797 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
18798 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
18799 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
18800 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
18801 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
18802 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
18803 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
18804 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__VERSION_MASK 0x0007L |
18805 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_CLOCK_MASK 0x0008L |
18806 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
18807 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
18808 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
18809 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
18810 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
18811 | #define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
18812 | //BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL |
18813 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
18814 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
18815 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
18816 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
18817 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
18818 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
18819 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
18820 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
18821 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
18822 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
18823 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
18824 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
18825 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
18826 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
18827 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
18828 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
18829 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
18830 | #define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
18831 | //BIF_CFG_DEV0_EPF6_SBRN |
18832 | #define BIF_CFG_DEV0_EPF6_SBRN__SBRN__SHIFT 0x0 |
18833 | #define BIF_CFG_DEV0_EPF6_SBRN__SBRN_MASK 0xFFL |
18834 | //BIF_CFG_DEV0_EPF6_FLADJ |
18835 | #define BIF_CFG_DEV0_EPF6_FLADJ__FLADJ__SHIFT 0x0 |
18836 | #define BIF_CFG_DEV0_EPF6_FLADJ__NFC__SHIFT 0x6 |
18837 | #define BIF_CFG_DEV0_EPF6_FLADJ__FLADJ_MASK 0x3FL |
18838 | #define BIF_CFG_DEV0_EPF6_FLADJ__NFC_MASK 0x40L |
18839 | //BIF_CFG_DEV0_EPF6_DBESL_DBESLD |
18840 | #define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESL__SHIFT 0x0 |
18841 | #define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
18842 | #define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESL_MASK 0x0FL |
18843 | #define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESLD_MASK 0xF0L |
18844 | //BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST |
18845 | #define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
18846 | #define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
18847 | #define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
18848 | #define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
18849 | //BIF_CFG_DEV0_EPF6_PCIE_CAP |
18850 | #define BIF_CFG_DEV0_EPF6_PCIE_CAP__VERSION__SHIFT 0x0 |
18851 | #define BIF_CFG_DEV0_EPF6_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
18852 | #define BIF_CFG_DEV0_EPF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
18853 | #define BIF_CFG_DEV0_EPF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
18854 | #define BIF_CFG_DEV0_EPF6_PCIE_CAP__VERSION_MASK 0x000FL |
18855 | #define BIF_CFG_DEV0_EPF6_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
18856 | #define BIF_CFG_DEV0_EPF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
18857 | #define BIF_CFG_DEV0_EPF6_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
18858 | //BIF_CFG_DEV0_EPF6_DEVICE_CAP |
18859 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
18860 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
18861 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
18862 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
18863 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
18864 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
18865 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
18866 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
18867 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
18868 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
18869 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
18870 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
18871 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
18872 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
18873 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
18874 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
18875 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
18876 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
18877 | //BIF_CFG_DEV0_EPF6_DEVICE_CNTL |
18878 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
18879 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
18880 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
18881 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
18882 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
18883 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
18884 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
18885 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
18886 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
18887 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
18888 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
18889 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
18890 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
18891 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
18892 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
18893 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
18894 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
18895 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
18896 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
18897 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
18898 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
18899 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
18900 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
18901 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
18902 | //BIF_CFG_DEV0_EPF6_DEVICE_STATUS |
18903 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
18904 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
18905 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
18906 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
18907 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
18908 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
18909 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
18910 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
18911 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
18912 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
18913 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
18914 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
18915 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
18916 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
18917 | //BIF_CFG_DEV0_EPF6_LINK_CAP |
18918 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
18919 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
18920 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
18921 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
18922 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
18923 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
18924 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
18925 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
18926 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
18927 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
18928 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
18929 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
18930 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
18931 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
18932 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
18933 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
18934 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
18935 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
18936 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
18937 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
18938 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
18939 | #define BIF_CFG_DEV0_EPF6_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
18940 | //BIF_CFG_DEV0_EPF6_LINK_CNTL |
18941 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
18942 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
18943 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
18944 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
18945 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
18946 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
18947 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
18948 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
18949 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
18950 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
18951 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
18952 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
18953 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
18954 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
18955 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
18956 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_DIS_MASK 0x0010L |
18957 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
18958 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
18959 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
18960 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
18961 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
18962 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
18963 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
18964 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
18965 | //BIF_CFG_DEV0_EPF6_LINK_STATUS |
18966 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
18967 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
18968 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
18969 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
18970 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
18971 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
18972 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
18973 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
18974 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
18975 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
18976 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
18977 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
18978 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
18979 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
18980 | //BIF_CFG_DEV0_EPF6_DEVICE_CAP2 |
18981 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
18982 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
18983 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
18984 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
18985 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
18986 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
18987 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
18988 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
18989 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
18990 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
18991 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
18992 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
18993 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
18994 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
18995 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
18996 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
18997 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
18998 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
18999 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
19000 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
19001 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
19002 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
19003 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
19004 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
19005 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
19006 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
19007 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
19008 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
19009 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
19010 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
19011 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
19012 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
19013 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
19014 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
19015 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
19016 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
19017 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
19018 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
19019 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
19020 | #define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
19021 | //BIF_CFG_DEV0_EPF6_DEVICE_CNTL2 |
19022 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
19023 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
19024 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
19025 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
19026 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
19027 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
19028 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
19029 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
19030 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
19031 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
19032 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
19033 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
19034 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
19035 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
19036 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
19037 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
19038 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
19039 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
19040 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
19041 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
19042 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
19043 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
19044 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
19045 | #define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
19046 | //BIF_CFG_DEV0_EPF6_DEVICE_STATUS2 |
19047 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
19048 | #define BIF_CFG_DEV0_EPF6_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
19049 | //BIF_CFG_DEV0_EPF6_LINK_CAP2 |
19050 | #define BIF_CFG_DEV0_EPF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
19051 | #define BIF_CFG_DEV0_EPF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
19052 | #define BIF_CFG_DEV0_EPF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
19053 | #define BIF_CFG_DEV0_EPF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
19054 | #define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
19055 | #define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
19056 | #define BIF_CFG_DEV0_EPF6_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
19057 | #define BIF_CFG_DEV0_EPF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
19058 | #define BIF_CFG_DEV0_EPF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
19059 | #define BIF_CFG_DEV0_EPF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
19060 | #define BIF_CFG_DEV0_EPF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
19061 | #define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
19062 | #define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
19063 | #define BIF_CFG_DEV0_EPF6_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
19064 | //BIF_CFG_DEV0_EPF6_LINK_CNTL2 |
19065 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
19066 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
19067 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
19068 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
19069 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
19070 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
19071 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
19072 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
19073 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
19074 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
19075 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
19076 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
19077 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
19078 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
19079 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
19080 | #define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
19081 | //BIF_CFG_DEV0_EPF6_LINK_STATUS2 |
19082 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
19083 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
19084 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
19085 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
19086 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
19087 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
19088 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
19089 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
19090 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
19091 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
19092 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
19093 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
19094 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
19095 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
19096 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
19097 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
19098 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
19099 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
19100 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
19101 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
19102 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
19103 | #define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
19104 | //BIF_CFG_DEV0_EPF6_MSI_CAP_LIST |
19105 | #define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
19106 | #define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
19107 | #define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
19108 | #define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
19109 | //BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL |
19110 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
19111 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
19112 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
19113 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
19114 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
19115 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
19116 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
19117 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
19118 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
19119 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
19120 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
19121 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
19122 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
19123 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
19124 | //BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_LO |
19125 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
19126 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
19127 | //BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_HI |
19128 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
19129 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
19130 | //BIF_CFG_DEV0_EPF6_MSI_MSG_DATA |
19131 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
19132 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
19133 | //BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA |
19134 | #define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
19135 | #define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
19136 | //BIF_CFG_DEV0_EPF6_MSI_MASK |
19137 | #define BIF_CFG_DEV0_EPF6_MSI_MASK__MSI_MASK__SHIFT 0x0 |
19138 | #define BIF_CFG_DEV0_EPF6_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
19139 | //BIF_CFG_DEV0_EPF6_MSI_MSG_DATA_64 |
19140 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
19141 | #define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
19142 | //BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA_64 |
19143 | #define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
19144 | #define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
19145 | //BIF_CFG_DEV0_EPF6_MSI_MASK_64 |
19146 | #define BIF_CFG_DEV0_EPF6_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
19147 | #define BIF_CFG_DEV0_EPF6_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
19148 | //BIF_CFG_DEV0_EPF6_MSI_PENDING |
19149 | #define BIF_CFG_DEV0_EPF6_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
19150 | #define BIF_CFG_DEV0_EPF6_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
19151 | //BIF_CFG_DEV0_EPF6_MSI_PENDING_64 |
19152 | #define BIF_CFG_DEV0_EPF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
19153 | #define BIF_CFG_DEV0_EPF6_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
19154 | //BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST |
19155 | #define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
19156 | #define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
19157 | #define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
19158 | #define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
19159 | //BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL |
19160 | #define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
19161 | #define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
19162 | #define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
19163 | #define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
19164 | #define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
19165 | #define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
19166 | //BIF_CFG_DEV0_EPF6_MSIX_TABLE |
19167 | #define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
19168 | #define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
19169 | #define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
19170 | #define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
19171 | //BIF_CFG_DEV0_EPF6_MSIX_PBA |
19172 | #define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
19173 | #define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
19174 | #define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
19175 | #define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
19176 | //BIF_CFG_DEV0_EPF6_SATA_CAP_0 |
19177 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
19178 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
19179 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
19180 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
19181 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
19182 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
19183 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
19184 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
19185 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
19186 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
19187 | //BIF_CFG_DEV0_EPF6_SATA_CAP_1 |
19188 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
19189 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
19190 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
19191 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
19192 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
19193 | #define BIF_CFG_DEV0_EPF6_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
19194 | //BIF_CFG_DEV0_EPF6_SATA_IDP_INDEX |
19195 | #define BIF_CFG_DEV0_EPF6_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
19196 | #define BIF_CFG_DEV0_EPF6_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
19197 | #define BIF_CFG_DEV0_EPF6_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
19198 | #define BIF_CFG_DEV0_EPF6_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
19199 | #define BIF_CFG_DEV0_EPF6_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
19200 | #define BIF_CFG_DEV0_EPF6_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
19201 | //BIF_CFG_DEV0_EPF6_SATA_IDP_DATA |
19202 | #define BIF_CFG_DEV0_EPF6_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
19203 | #define BIF_CFG_DEV0_EPF6_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
19204 | //BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
19205 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19206 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19207 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19208 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19209 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19210 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19211 | //BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR |
19212 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
19213 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
19214 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
19215 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
19216 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
19217 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
19218 | //BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC1 |
19219 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
19220 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
19221 | //BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC2 |
19222 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
19223 | #define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
19224 | //BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
19225 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19226 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19227 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19228 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19229 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19230 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19231 | //BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS |
19232 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
19233 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
19234 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
19235 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
19236 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
19237 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
19238 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
19239 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
19240 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
19241 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
19242 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
19243 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
19244 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
19245 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
19246 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
19247 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
19248 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
19249 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
19250 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
19251 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
19252 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
19253 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
19254 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
19255 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
19256 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
19257 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
19258 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
19259 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
19260 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
19261 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
19262 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
19263 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
19264 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
19265 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
19266 | //BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK |
19267 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
19268 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
19269 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
19270 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
19271 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
19272 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
19273 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
19274 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
19275 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
19276 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
19277 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
19278 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
19279 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
19280 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
19281 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
19282 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
19283 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
19284 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
19285 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
19286 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
19287 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
19288 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
19289 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
19290 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
19291 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
19292 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
19293 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
19294 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
19295 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
19296 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
19297 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
19298 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
19299 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
19300 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
19301 | //BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY |
19302 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
19303 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
19304 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
19305 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
19306 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
19307 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
19308 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
19309 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
19310 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
19311 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
19312 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
19313 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
19314 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
19315 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
19316 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
19317 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
19318 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
19319 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
19320 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
19321 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
19322 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
19323 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
19324 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
19325 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
19326 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
19327 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
19328 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
19329 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
19330 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
19331 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
19332 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
19333 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
19334 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
19335 | #define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
19336 | //BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS |
19337 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
19338 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
19339 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
19340 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
19341 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
19342 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
19343 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
19344 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
19345 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
19346 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
19347 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
19348 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
19349 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
19350 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
19351 | //BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK |
19352 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
19353 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
19354 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
19355 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
19356 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
19357 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
19358 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
19359 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
19360 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
19361 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
19362 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
19363 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
19364 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
19365 | #define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
19366 | //BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL |
19367 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
19368 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
19369 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
19370 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
19371 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
19372 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
19373 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
19374 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
19375 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
19376 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
19377 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
19378 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
19379 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
19380 | #define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
19381 | //BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG0 |
19382 | #define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
19383 | #define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
19384 | //BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG1 |
19385 | #define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
19386 | #define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
19387 | //BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG2 |
19388 | #define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
19389 | #define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
19390 | //BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG3 |
19391 | #define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
19392 | #define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
19393 | //BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG0 |
19394 | #define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
19395 | #define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
19396 | //BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG1 |
19397 | #define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
19398 | #define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
19399 | //BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG2 |
19400 | #define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
19401 | #define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
19402 | //BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG3 |
19403 | #define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
19404 | #define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
19405 | //BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST |
19406 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19407 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19408 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19409 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19410 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19411 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19412 | //BIF_CFG_DEV0_EPF6_PCIE_BAR1_CAP |
19413 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
19414 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
19415 | //BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL |
19416 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
19417 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
19418 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
19419 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
19420 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
19421 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
19422 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
19423 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
19424 | //BIF_CFG_DEV0_EPF6_PCIE_BAR2_CAP |
19425 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
19426 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
19427 | //BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL |
19428 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
19429 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
19430 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
19431 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
19432 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
19433 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
19434 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
19435 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
19436 | //BIF_CFG_DEV0_EPF6_PCIE_BAR3_CAP |
19437 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
19438 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
19439 | //BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL |
19440 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
19441 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
19442 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
19443 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
19444 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
19445 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
19446 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
19447 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
19448 | //BIF_CFG_DEV0_EPF6_PCIE_BAR4_CAP |
19449 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
19450 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
19451 | //BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL |
19452 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
19453 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
19454 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
19455 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
19456 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
19457 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
19458 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
19459 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
19460 | //BIF_CFG_DEV0_EPF6_PCIE_BAR5_CAP |
19461 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
19462 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
19463 | //BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL |
19464 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
19465 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
19466 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
19467 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
19468 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
19469 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
19470 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
19471 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
19472 | //BIF_CFG_DEV0_EPF6_PCIE_BAR6_CAP |
19473 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
19474 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
19475 | //BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL |
19476 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
19477 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
19478 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
19479 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
19480 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
19481 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
19482 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
19483 | #define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
19484 | //BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST |
19485 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19486 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19487 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19488 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19489 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19490 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19491 | //BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA_SELECT |
19492 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
19493 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
19494 | //BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA |
19495 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
19496 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
19497 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
19498 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
19499 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
19500 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
19501 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
19502 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
19503 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
19504 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
19505 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
19506 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
19507 | //BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_CAP |
19508 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
19509 | #define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
19510 | //BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST |
19511 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19512 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19513 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19514 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19515 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19516 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19517 | //BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP |
19518 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
19519 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
19520 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
19521 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
19522 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
19523 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
19524 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
19525 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
19526 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
19527 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
19528 | //BIF_CFG_DEV0_EPF6_PCIE_DPA_LATENCY_INDICATOR |
19529 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
19530 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
19531 | //BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS |
19532 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
19533 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
19534 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
19535 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
19536 | //BIF_CFG_DEV0_EPF6_PCIE_DPA_CNTL |
19537 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
19538 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
19539 | //BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
19540 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
19541 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
19542 | //BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
19543 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
19544 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
19545 | //BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
19546 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
19547 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
19548 | //BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
19549 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
19550 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
19551 | //BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
19552 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
19553 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
19554 | //BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
19555 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
19556 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
19557 | //BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
19558 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
19559 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
19560 | //BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
19561 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
19562 | #define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
19563 | //BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST |
19564 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19565 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19566 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19567 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19568 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19569 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19570 | //BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP |
19571 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
19572 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
19573 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
19574 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
19575 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
19576 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
19577 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
19578 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
19579 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
19580 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
19581 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
19582 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
19583 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
19584 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
19585 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
19586 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
19587 | //BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL |
19588 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
19589 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
19590 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
19591 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
19592 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
19593 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
19594 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
19595 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
19596 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
19597 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
19598 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
19599 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
19600 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
19601 | #define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
19602 | //BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST |
19603 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19604 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19605 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19606 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19607 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19608 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19609 | //BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP |
19610 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
19611 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
19612 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
19613 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
19614 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
19615 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
19616 | //BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL |
19617 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
19618 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
19619 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
19620 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
19621 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
19622 | #define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
19623 | //BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST |
19624 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19625 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19626 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19627 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19628 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19629 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19630 | //BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP |
19631 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
19632 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
19633 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
19634 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
19635 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
19636 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
19637 | //BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL |
19638 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
19639 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
19640 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
19641 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
19642 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
19643 | #define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
19644 | //BIF_CFG_DEV0_EPF6_PCIE_RTR_ENH_CAP_LIST |
19645 | #define BIF_CFG_DEV0_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
19646 | #define BIF_CFG_DEV0_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
19647 | #define BIF_CFG_DEV0_EPF6_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
19648 | #define BIF_CFG_DEV0_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
19649 | #define BIF_CFG_DEV0_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
19650 | #define BIF_CFG_DEV0_EPF6_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
19651 | //BIF_CFG_DEV0_EPF6_RTR_DATA1 |
19652 | #define BIF_CFG_DEV0_EPF6_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
19653 | #define BIF_CFG_DEV0_EPF6_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
19654 | #define BIF_CFG_DEV0_EPF6_RTR_DATA1__VALID__SHIFT 0x1f |
19655 | #define BIF_CFG_DEV0_EPF6_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
19656 | #define BIF_CFG_DEV0_EPF6_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
19657 | #define BIF_CFG_DEV0_EPF6_RTR_DATA1__VALID_MASK 0x80000000L |
19658 | //BIF_CFG_DEV0_EPF6_RTR_DATA2 |
19659 | #define BIF_CFG_DEV0_EPF6_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
19660 | #define BIF_CFG_DEV0_EPF6_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
19661 | #define BIF_CFG_DEV0_EPF6_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
19662 | #define BIF_CFG_DEV0_EPF6_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
19663 | |
19664 | |
19665 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp |
19666 | //BIF_CFG_DEV0_EPF7_VENDOR_ID |
19667 | #define BIF_CFG_DEV0_EPF7_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
19668 | #define BIF_CFG_DEV0_EPF7_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
19669 | //BIF_CFG_DEV0_EPF7_DEVICE_ID |
19670 | #define BIF_CFG_DEV0_EPF7_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
19671 | #define BIF_CFG_DEV0_EPF7_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
19672 | //BIF_CFG_DEV0_EPF7_COMMAND |
19673 | #define BIF_CFG_DEV0_EPF7_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
19674 | #define BIF_CFG_DEV0_EPF7_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
19675 | #define BIF_CFG_DEV0_EPF7_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
19676 | #define BIF_CFG_DEV0_EPF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
19677 | #define BIF_CFG_DEV0_EPF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
19678 | #define BIF_CFG_DEV0_EPF7_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
19679 | #define BIF_CFG_DEV0_EPF7_COMMAND__AD_STEPPING__SHIFT 0x7 |
19680 | #define BIF_CFG_DEV0_EPF7_COMMAND__SERR_EN__SHIFT 0x8 |
19681 | #define BIF_CFG_DEV0_EPF7_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
19682 | #define BIF_CFG_DEV0_EPF7_COMMAND__INT_DIS__SHIFT 0xa |
19683 | #define BIF_CFG_DEV0_EPF7_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
19684 | #define BIF_CFG_DEV0_EPF7_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
19685 | #define BIF_CFG_DEV0_EPF7_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
19686 | #define BIF_CFG_DEV0_EPF7_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
19687 | #define BIF_CFG_DEV0_EPF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
19688 | #define BIF_CFG_DEV0_EPF7_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
19689 | #define BIF_CFG_DEV0_EPF7_COMMAND__AD_STEPPING_MASK 0x0080L |
19690 | #define BIF_CFG_DEV0_EPF7_COMMAND__SERR_EN_MASK 0x0100L |
19691 | #define BIF_CFG_DEV0_EPF7_COMMAND__FAST_B2B_EN_MASK 0x0200L |
19692 | #define BIF_CFG_DEV0_EPF7_COMMAND__INT_DIS_MASK 0x0400L |
19693 | //BIF_CFG_DEV0_EPF7_STATUS |
19694 | #define BIF_CFG_DEV0_EPF7_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
19695 | #define BIF_CFG_DEV0_EPF7_STATUS__INT_STATUS__SHIFT 0x3 |
19696 | #define BIF_CFG_DEV0_EPF7_STATUS__CAP_LIST__SHIFT 0x4 |
19697 | #define BIF_CFG_DEV0_EPF7_STATUS__PCI_66_CAP__SHIFT 0x5 |
19698 | #define BIF_CFG_DEV0_EPF7_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
19699 | #define BIF_CFG_DEV0_EPF7_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
19700 | #define BIF_CFG_DEV0_EPF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
19701 | #define BIF_CFG_DEV0_EPF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
19702 | #define BIF_CFG_DEV0_EPF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
19703 | #define BIF_CFG_DEV0_EPF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
19704 | #define BIF_CFG_DEV0_EPF7_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
19705 | #define BIF_CFG_DEV0_EPF7_STATUS__INT_STATUS_MASK 0x0008L |
19706 | #define BIF_CFG_DEV0_EPF7_STATUS__CAP_LIST_MASK 0x0010L |
19707 | #define BIF_CFG_DEV0_EPF7_STATUS__PCI_66_CAP_MASK 0x0020L |
19708 | #define BIF_CFG_DEV0_EPF7_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
19709 | #define BIF_CFG_DEV0_EPF7_STATUS__DEVSEL_TIMING_MASK 0x0600L |
19710 | #define BIF_CFG_DEV0_EPF7_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
19711 | #define BIF_CFG_DEV0_EPF7_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
19712 | #define BIF_CFG_DEV0_EPF7_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
19713 | #define BIF_CFG_DEV0_EPF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
19714 | //BIF_CFG_DEV0_EPF7_REVISION_ID |
19715 | #define BIF_CFG_DEV0_EPF7_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
19716 | #define BIF_CFG_DEV0_EPF7_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
19717 | #define BIF_CFG_DEV0_EPF7_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
19718 | #define BIF_CFG_DEV0_EPF7_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
19719 | //BIF_CFG_DEV0_EPF7_PROG_INTERFACE |
19720 | #define BIF_CFG_DEV0_EPF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
19721 | #define BIF_CFG_DEV0_EPF7_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
19722 | //BIF_CFG_DEV0_EPF7_SUB_CLASS |
19723 | #define BIF_CFG_DEV0_EPF7_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
19724 | #define BIF_CFG_DEV0_EPF7_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
19725 | //BIF_CFG_DEV0_EPF7_BASE_CLASS |
19726 | #define BIF_CFG_DEV0_EPF7_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
19727 | #define BIF_CFG_DEV0_EPF7_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
19728 | //BIF_CFG_DEV0_EPF7_CACHE_LINE |
19729 | #define BIF_CFG_DEV0_EPF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
19730 | #define BIF_CFG_DEV0_EPF7_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
19731 | //BIF_CFG_DEV0_EPF7_LATENCY |
19732 | #define BIF_CFG_DEV0_EPF7_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
19733 | #define BIF_CFG_DEV0_EPF7_LATENCY__LATENCY_TIMER_MASK 0xFFL |
19734 | //BIF_CFG_DEV0_EPF7_HEADER |
19735 | #define 0x0 |
19736 | #define 0x7 |
19737 | #define 0x7FL |
19738 | #define 0x80L |
19739 | //BIF_CFG_DEV0_EPF7_BIST |
19740 | #define BIF_CFG_DEV0_EPF7_BIST__BIST_COMP__SHIFT 0x0 |
19741 | #define BIF_CFG_DEV0_EPF7_BIST__BIST_STRT__SHIFT 0x6 |
19742 | #define BIF_CFG_DEV0_EPF7_BIST__BIST_CAP__SHIFT 0x7 |
19743 | #define BIF_CFG_DEV0_EPF7_BIST__BIST_COMP_MASK 0x0FL |
19744 | #define BIF_CFG_DEV0_EPF7_BIST__BIST_STRT_MASK 0x40L |
19745 | #define BIF_CFG_DEV0_EPF7_BIST__BIST_CAP_MASK 0x80L |
19746 | //BIF_CFG_DEV0_EPF7_BASE_ADDR_1 |
19747 | #define BIF_CFG_DEV0_EPF7_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
19748 | #define BIF_CFG_DEV0_EPF7_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
19749 | //BIF_CFG_DEV0_EPF7_BASE_ADDR_2 |
19750 | #define BIF_CFG_DEV0_EPF7_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
19751 | #define BIF_CFG_DEV0_EPF7_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
19752 | //BIF_CFG_DEV0_EPF7_BASE_ADDR_3 |
19753 | #define BIF_CFG_DEV0_EPF7_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
19754 | #define BIF_CFG_DEV0_EPF7_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
19755 | //BIF_CFG_DEV0_EPF7_BASE_ADDR_4 |
19756 | #define BIF_CFG_DEV0_EPF7_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
19757 | #define BIF_CFG_DEV0_EPF7_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
19758 | //BIF_CFG_DEV0_EPF7_BASE_ADDR_5 |
19759 | #define BIF_CFG_DEV0_EPF7_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
19760 | #define BIF_CFG_DEV0_EPF7_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
19761 | //BIF_CFG_DEV0_EPF7_BASE_ADDR_6 |
19762 | #define BIF_CFG_DEV0_EPF7_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
19763 | #define BIF_CFG_DEV0_EPF7_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
19764 | //BIF_CFG_DEV0_EPF7_ADAPTER_ID |
19765 | #define BIF_CFG_DEV0_EPF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
19766 | #define BIF_CFG_DEV0_EPF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
19767 | #define BIF_CFG_DEV0_EPF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
19768 | #define BIF_CFG_DEV0_EPF7_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
19769 | //BIF_CFG_DEV0_EPF7_ROM_BASE_ADDR |
19770 | #define BIF_CFG_DEV0_EPF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
19771 | #define BIF_CFG_DEV0_EPF7_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
19772 | //BIF_CFG_DEV0_EPF7_CAP_PTR |
19773 | #define BIF_CFG_DEV0_EPF7_CAP_PTR__CAP_PTR__SHIFT 0x0 |
19774 | #define BIF_CFG_DEV0_EPF7_CAP_PTR__CAP_PTR_MASK 0xFFL |
19775 | //BIF_CFG_DEV0_EPF7_INTERRUPT_LINE |
19776 | #define BIF_CFG_DEV0_EPF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
19777 | #define BIF_CFG_DEV0_EPF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
19778 | //BIF_CFG_DEV0_EPF7_INTERRUPT_PIN |
19779 | #define BIF_CFG_DEV0_EPF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
19780 | #define BIF_CFG_DEV0_EPF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
19781 | //BIF_CFG_DEV0_EPF7_MIN_GRANT |
19782 | #define BIF_CFG_DEV0_EPF7_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
19783 | #define BIF_CFG_DEV0_EPF7_MIN_GRANT__MIN_GNT_MASK 0xFFL |
19784 | //BIF_CFG_DEV0_EPF7_MAX_LATENCY |
19785 | #define BIF_CFG_DEV0_EPF7_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
19786 | #define BIF_CFG_DEV0_EPF7_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
19787 | //BIF_CFG_DEV0_EPF7_VENDOR_CAP_LIST |
19788 | #define BIF_CFG_DEV0_EPF7_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
19789 | #define BIF_CFG_DEV0_EPF7_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
19790 | #define BIF_CFG_DEV0_EPF7_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
19791 | #define BIF_CFG_DEV0_EPF7_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
19792 | #define BIF_CFG_DEV0_EPF7_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
19793 | #define BIF_CFG_DEV0_EPF7_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
19794 | //BIF_CFG_DEV0_EPF7_ADAPTER_ID_W |
19795 | #define BIF_CFG_DEV0_EPF7_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
19796 | #define BIF_CFG_DEV0_EPF7_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
19797 | #define BIF_CFG_DEV0_EPF7_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
19798 | #define BIF_CFG_DEV0_EPF7_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
19799 | //BIF_CFG_DEV0_EPF7_PMI_CAP_LIST |
19800 | #define BIF_CFG_DEV0_EPF7_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
19801 | #define BIF_CFG_DEV0_EPF7_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
19802 | #define BIF_CFG_DEV0_EPF7_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
19803 | #define BIF_CFG_DEV0_EPF7_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
19804 | //BIF_CFG_DEV0_EPF7_PMI_CAP |
19805 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__VERSION__SHIFT 0x0 |
19806 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
19807 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
19808 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
19809 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
19810 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
19811 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
19812 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
19813 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__VERSION_MASK 0x0007L |
19814 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__PME_CLOCK_MASK 0x0008L |
19815 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
19816 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
19817 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
19818 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
19819 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
19820 | #define BIF_CFG_DEV0_EPF7_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
19821 | //BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL |
19822 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
19823 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
19824 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
19825 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
19826 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
19827 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
19828 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
19829 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
19830 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
19831 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
19832 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
19833 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
19834 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
19835 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
19836 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
19837 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
19838 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
19839 | #define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
19840 | //BIF_CFG_DEV0_EPF7_SBRN |
19841 | #define BIF_CFG_DEV0_EPF7_SBRN__SBRN__SHIFT 0x0 |
19842 | #define BIF_CFG_DEV0_EPF7_SBRN__SBRN_MASK 0xFFL |
19843 | //BIF_CFG_DEV0_EPF7_FLADJ |
19844 | #define BIF_CFG_DEV0_EPF7_FLADJ__FLADJ__SHIFT 0x0 |
19845 | #define BIF_CFG_DEV0_EPF7_FLADJ__NFC__SHIFT 0x6 |
19846 | #define BIF_CFG_DEV0_EPF7_FLADJ__FLADJ_MASK 0x3FL |
19847 | #define BIF_CFG_DEV0_EPF7_FLADJ__NFC_MASK 0x40L |
19848 | //BIF_CFG_DEV0_EPF7_DBESL_DBESLD |
19849 | #define BIF_CFG_DEV0_EPF7_DBESL_DBESLD__DBESL__SHIFT 0x0 |
19850 | #define BIF_CFG_DEV0_EPF7_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
19851 | #define BIF_CFG_DEV0_EPF7_DBESL_DBESLD__DBESL_MASK 0x0FL |
19852 | #define BIF_CFG_DEV0_EPF7_DBESL_DBESLD__DBESLD_MASK 0xF0L |
19853 | //BIF_CFG_DEV0_EPF7_PCIE_CAP_LIST |
19854 | #define BIF_CFG_DEV0_EPF7_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
19855 | #define BIF_CFG_DEV0_EPF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
19856 | #define BIF_CFG_DEV0_EPF7_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
19857 | #define BIF_CFG_DEV0_EPF7_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
19858 | //BIF_CFG_DEV0_EPF7_PCIE_CAP |
19859 | #define BIF_CFG_DEV0_EPF7_PCIE_CAP__VERSION__SHIFT 0x0 |
19860 | #define BIF_CFG_DEV0_EPF7_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
19861 | #define BIF_CFG_DEV0_EPF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
19862 | #define BIF_CFG_DEV0_EPF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
19863 | #define BIF_CFG_DEV0_EPF7_PCIE_CAP__VERSION_MASK 0x000FL |
19864 | #define BIF_CFG_DEV0_EPF7_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
19865 | #define BIF_CFG_DEV0_EPF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
19866 | #define BIF_CFG_DEV0_EPF7_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
19867 | //BIF_CFG_DEV0_EPF7_DEVICE_CAP |
19868 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
19869 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
19870 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
19871 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
19872 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
19873 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
19874 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
19875 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
19876 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
19877 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
19878 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
19879 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
19880 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
19881 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
19882 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
19883 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
19884 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
19885 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
19886 | //BIF_CFG_DEV0_EPF7_DEVICE_CNTL |
19887 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
19888 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
19889 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
19890 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
19891 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
19892 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
19893 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
19894 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
19895 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
19896 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
19897 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
19898 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
19899 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
19900 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
19901 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
19902 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
19903 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
19904 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
19905 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
19906 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
19907 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
19908 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
19909 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
19910 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
19911 | //BIF_CFG_DEV0_EPF7_DEVICE_STATUS |
19912 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
19913 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
19914 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
19915 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
19916 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
19917 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
19918 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
19919 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
19920 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
19921 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
19922 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
19923 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
19924 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
19925 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
19926 | //BIF_CFG_DEV0_EPF7_LINK_CAP |
19927 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
19928 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
19929 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
19930 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
19931 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
19932 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
19933 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
19934 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
19935 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
19936 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
19937 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
19938 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
19939 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
19940 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
19941 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
19942 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
19943 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
19944 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
19945 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
19946 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
19947 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
19948 | #define BIF_CFG_DEV0_EPF7_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
19949 | //BIF_CFG_DEV0_EPF7_LINK_CNTL |
19950 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
19951 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
19952 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
19953 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
19954 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
19955 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
19956 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
19957 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
19958 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
19959 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
19960 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
19961 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
19962 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
19963 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
19964 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
19965 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__LINK_DIS_MASK 0x0010L |
19966 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
19967 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
19968 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
19969 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
19970 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
19971 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
19972 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
19973 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
19974 | //BIF_CFG_DEV0_EPF7_LINK_STATUS |
19975 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
19976 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
19977 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
19978 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
19979 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
19980 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
19981 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
19982 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
19983 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
19984 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
19985 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
19986 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
19987 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
19988 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
19989 | //BIF_CFG_DEV0_EPF7_DEVICE_CAP2 |
19990 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
19991 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
19992 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
19993 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
19994 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
19995 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
19996 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
19997 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
19998 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
19999 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
20000 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
20001 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
20002 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
20003 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
20004 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
20005 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
20006 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
20007 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
20008 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
20009 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
20010 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
20011 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
20012 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
20013 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
20014 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
20015 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
20016 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
20017 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
20018 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
20019 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
20020 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
20021 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
20022 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
20023 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
20024 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
20025 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
20026 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
20027 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
20028 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
20029 | #define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
20030 | //BIF_CFG_DEV0_EPF7_DEVICE_CNTL2 |
20031 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
20032 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
20033 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
20034 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
20035 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
20036 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
20037 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
20038 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
20039 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
20040 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
20041 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
20042 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
20043 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
20044 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
20045 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
20046 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
20047 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
20048 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
20049 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
20050 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
20051 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
20052 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
20053 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
20054 | #define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
20055 | //BIF_CFG_DEV0_EPF7_DEVICE_STATUS2 |
20056 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
20057 | #define BIF_CFG_DEV0_EPF7_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
20058 | //BIF_CFG_DEV0_EPF7_LINK_CAP2 |
20059 | #define BIF_CFG_DEV0_EPF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
20060 | #define BIF_CFG_DEV0_EPF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
20061 | #define BIF_CFG_DEV0_EPF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
20062 | #define BIF_CFG_DEV0_EPF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
20063 | #define BIF_CFG_DEV0_EPF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
20064 | #define BIF_CFG_DEV0_EPF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
20065 | #define BIF_CFG_DEV0_EPF7_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
20066 | #define BIF_CFG_DEV0_EPF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
20067 | #define BIF_CFG_DEV0_EPF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
20068 | #define BIF_CFG_DEV0_EPF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
20069 | #define BIF_CFG_DEV0_EPF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
20070 | #define BIF_CFG_DEV0_EPF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
20071 | #define BIF_CFG_DEV0_EPF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
20072 | #define BIF_CFG_DEV0_EPF7_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
20073 | //BIF_CFG_DEV0_EPF7_LINK_CNTL2 |
20074 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
20075 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
20076 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
20077 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
20078 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
20079 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
20080 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
20081 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
20082 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
20083 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
20084 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
20085 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
20086 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
20087 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
20088 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
20089 | #define BIF_CFG_DEV0_EPF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
20090 | //BIF_CFG_DEV0_EPF7_LINK_STATUS2 |
20091 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
20092 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
20093 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
20094 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
20095 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
20096 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
20097 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
20098 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
20099 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
20100 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
20101 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
20102 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
20103 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
20104 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
20105 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
20106 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
20107 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
20108 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
20109 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
20110 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
20111 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
20112 | #define BIF_CFG_DEV0_EPF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
20113 | //BIF_CFG_DEV0_EPF7_MSI_CAP_LIST |
20114 | #define BIF_CFG_DEV0_EPF7_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
20115 | #define BIF_CFG_DEV0_EPF7_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
20116 | #define BIF_CFG_DEV0_EPF7_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
20117 | #define BIF_CFG_DEV0_EPF7_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
20118 | //BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL |
20119 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
20120 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
20121 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
20122 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
20123 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
20124 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
20125 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
20126 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
20127 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
20128 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
20129 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
20130 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
20131 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
20132 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
20133 | //BIF_CFG_DEV0_EPF7_MSI_MSG_ADDR_LO |
20134 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
20135 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
20136 | //BIF_CFG_DEV0_EPF7_MSI_MSG_ADDR_HI |
20137 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
20138 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
20139 | //BIF_CFG_DEV0_EPF7_MSI_MSG_DATA |
20140 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
20141 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
20142 | //BIF_CFG_DEV0_EPF7_MSI_EXT_MSG_DATA |
20143 | #define BIF_CFG_DEV0_EPF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
20144 | #define BIF_CFG_DEV0_EPF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
20145 | //BIF_CFG_DEV0_EPF7_MSI_MASK |
20146 | #define BIF_CFG_DEV0_EPF7_MSI_MASK__MSI_MASK__SHIFT 0x0 |
20147 | #define BIF_CFG_DEV0_EPF7_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
20148 | //BIF_CFG_DEV0_EPF7_MSI_MSG_DATA_64 |
20149 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
20150 | #define BIF_CFG_DEV0_EPF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
20151 | //BIF_CFG_DEV0_EPF7_MSI_EXT_MSG_DATA_64 |
20152 | #define BIF_CFG_DEV0_EPF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
20153 | #define BIF_CFG_DEV0_EPF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
20154 | //BIF_CFG_DEV0_EPF7_MSI_MASK_64 |
20155 | #define BIF_CFG_DEV0_EPF7_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
20156 | #define BIF_CFG_DEV0_EPF7_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
20157 | //BIF_CFG_DEV0_EPF7_MSI_PENDING |
20158 | #define BIF_CFG_DEV0_EPF7_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
20159 | #define BIF_CFG_DEV0_EPF7_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
20160 | //BIF_CFG_DEV0_EPF7_MSI_PENDING_64 |
20161 | #define BIF_CFG_DEV0_EPF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
20162 | #define BIF_CFG_DEV0_EPF7_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
20163 | //BIF_CFG_DEV0_EPF7_MSIX_CAP_LIST |
20164 | #define BIF_CFG_DEV0_EPF7_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
20165 | #define BIF_CFG_DEV0_EPF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
20166 | #define BIF_CFG_DEV0_EPF7_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
20167 | #define BIF_CFG_DEV0_EPF7_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
20168 | //BIF_CFG_DEV0_EPF7_MSIX_MSG_CNTL |
20169 | #define BIF_CFG_DEV0_EPF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
20170 | #define BIF_CFG_DEV0_EPF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
20171 | #define BIF_CFG_DEV0_EPF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
20172 | #define BIF_CFG_DEV0_EPF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
20173 | #define BIF_CFG_DEV0_EPF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
20174 | #define BIF_CFG_DEV0_EPF7_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
20175 | //BIF_CFG_DEV0_EPF7_MSIX_TABLE |
20176 | #define BIF_CFG_DEV0_EPF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
20177 | #define BIF_CFG_DEV0_EPF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
20178 | #define BIF_CFG_DEV0_EPF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
20179 | #define BIF_CFG_DEV0_EPF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
20180 | //BIF_CFG_DEV0_EPF7_MSIX_PBA |
20181 | #define BIF_CFG_DEV0_EPF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
20182 | #define BIF_CFG_DEV0_EPF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
20183 | #define BIF_CFG_DEV0_EPF7_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
20184 | #define BIF_CFG_DEV0_EPF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
20185 | //BIF_CFG_DEV0_EPF7_SATA_CAP_0 |
20186 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
20187 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
20188 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
20189 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
20190 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
20191 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
20192 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
20193 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
20194 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
20195 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
20196 | //BIF_CFG_DEV0_EPF7_SATA_CAP_1 |
20197 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
20198 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
20199 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
20200 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
20201 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
20202 | #define BIF_CFG_DEV0_EPF7_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
20203 | //BIF_CFG_DEV0_EPF7_SATA_IDP_INDEX |
20204 | #define BIF_CFG_DEV0_EPF7_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
20205 | #define BIF_CFG_DEV0_EPF7_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
20206 | #define BIF_CFG_DEV0_EPF7_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
20207 | #define BIF_CFG_DEV0_EPF7_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
20208 | #define BIF_CFG_DEV0_EPF7_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
20209 | #define BIF_CFG_DEV0_EPF7_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
20210 | //BIF_CFG_DEV0_EPF7_SATA_IDP_DATA |
20211 | #define BIF_CFG_DEV0_EPF7_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
20212 | #define BIF_CFG_DEV0_EPF7_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
20213 | //BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
20214 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
20215 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
20216 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
20217 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
20218 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
20219 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
20220 | //BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_HDR |
20221 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
20222 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
20223 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
20224 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
20225 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
20226 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
20227 | //BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC1 |
20228 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
20229 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
20230 | //BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC2 |
20231 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
20232 | #define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
20233 | //BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
20234 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
20235 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
20236 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
20237 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
20238 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
20239 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
20240 | //BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS |
20241 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
20242 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
20243 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
20244 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
20245 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
20246 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
20247 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
20248 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
20249 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
20250 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
20251 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
20252 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
20253 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
20254 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
20255 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
20256 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
20257 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
20258 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
20259 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
20260 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
20261 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
20262 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
20263 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
20264 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
20265 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
20266 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
20267 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
20268 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
20269 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
20270 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
20271 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
20272 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
20273 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
20274 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
20275 | //BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK |
20276 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
20277 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
20278 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
20279 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
20280 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
20281 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
20282 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
20283 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
20284 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
20285 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
20286 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
20287 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
20288 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
20289 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
20290 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
20291 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
20292 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
20293 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
20294 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
20295 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
20296 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
20297 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
20298 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
20299 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
20300 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
20301 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
20302 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
20303 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
20304 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
20305 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
20306 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
20307 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
20308 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
20309 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
20310 | //BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY |
20311 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
20312 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
20313 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
20314 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
20315 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
20316 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
20317 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
20318 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
20319 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
20320 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
20321 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
20322 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
20323 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
20324 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
20325 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
20326 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
20327 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
20328 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
20329 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
20330 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
20331 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
20332 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
20333 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
20334 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
20335 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
20336 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
20337 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
20338 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
20339 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
20340 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
20341 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
20342 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
20343 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
20344 | #define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
20345 | //BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS |
20346 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
20347 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
20348 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
20349 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
20350 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
20351 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
20352 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
20353 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
20354 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
20355 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
20356 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
20357 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
20358 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
20359 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
20360 | //BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK |
20361 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
20362 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
20363 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
20364 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
20365 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
20366 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
20367 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
20368 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
20369 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
20370 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
20371 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
20372 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
20373 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
20374 | #define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
20375 | //BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL |
20376 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
20377 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
20378 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
20379 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
20380 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
20381 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
20382 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
20383 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
20384 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
20385 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
20386 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
20387 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
20388 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
20389 | #define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
20390 | //BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG0 |
20391 | #define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
20392 | #define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
20393 | //BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG1 |
20394 | #define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
20395 | #define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
20396 | //BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG2 |
20397 | #define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
20398 | #define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
20399 | //BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG3 |
20400 | #define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
20401 | #define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
20402 | //BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG0 |
20403 | #define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
20404 | #define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
20405 | //BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG1 |
20406 | #define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
20407 | #define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
20408 | //BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG2 |
20409 | #define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
20410 | #define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
20411 | //BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG3 |
20412 | #define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
20413 | #define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
20414 | //BIF_CFG_DEV0_EPF7_PCIE_BAR_ENH_CAP_LIST |
20415 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
20416 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
20417 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
20418 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
20419 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
20420 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
20421 | //BIF_CFG_DEV0_EPF7_PCIE_BAR1_CAP |
20422 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
20423 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
20424 | //BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL |
20425 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
20426 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
20427 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
20428 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
20429 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
20430 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
20431 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
20432 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
20433 | //BIF_CFG_DEV0_EPF7_PCIE_BAR2_CAP |
20434 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
20435 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
20436 | //BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL |
20437 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
20438 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
20439 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
20440 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
20441 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
20442 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
20443 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
20444 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
20445 | //BIF_CFG_DEV0_EPF7_PCIE_BAR3_CAP |
20446 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
20447 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
20448 | //BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL |
20449 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
20450 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
20451 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
20452 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
20453 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
20454 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
20455 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
20456 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
20457 | //BIF_CFG_DEV0_EPF7_PCIE_BAR4_CAP |
20458 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
20459 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
20460 | //BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL |
20461 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
20462 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
20463 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
20464 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
20465 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
20466 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
20467 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
20468 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
20469 | //BIF_CFG_DEV0_EPF7_PCIE_BAR5_CAP |
20470 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
20471 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
20472 | //BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL |
20473 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
20474 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
20475 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
20476 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
20477 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
20478 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
20479 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
20480 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
20481 | //BIF_CFG_DEV0_EPF7_PCIE_BAR6_CAP |
20482 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
20483 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
20484 | //BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL |
20485 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
20486 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
20487 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
20488 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
20489 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
20490 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
20491 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
20492 | #define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
20493 | //BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_ENH_CAP_LIST |
20494 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
20495 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
20496 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
20497 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
20498 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
20499 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
20500 | //BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA_SELECT |
20501 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
20502 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
20503 | //BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA |
20504 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
20505 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
20506 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
20507 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
20508 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
20509 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
20510 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
20511 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
20512 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
20513 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
20514 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
20515 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
20516 | //BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_CAP |
20517 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
20518 | #define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
20519 | //BIF_CFG_DEV0_EPF7_PCIE_DPA_ENH_CAP_LIST |
20520 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
20521 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
20522 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
20523 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
20524 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
20525 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
20526 | //BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP |
20527 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
20528 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
20529 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
20530 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
20531 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
20532 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
20533 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
20534 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
20535 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
20536 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
20537 | //BIF_CFG_DEV0_EPF7_PCIE_DPA_LATENCY_INDICATOR |
20538 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
20539 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
20540 | //BIF_CFG_DEV0_EPF7_PCIE_DPA_STATUS |
20541 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
20542 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
20543 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
20544 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
20545 | //BIF_CFG_DEV0_EPF7_PCIE_DPA_CNTL |
20546 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
20547 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
20548 | //BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
20549 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
20550 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
20551 | //BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
20552 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
20553 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
20554 | //BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
20555 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
20556 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
20557 | //BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
20558 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
20559 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
20560 | //BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
20561 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
20562 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
20563 | //BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
20564 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
20565 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
20566 | //BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
20567 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
20568 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
20569 | //BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
20570 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
20571 | #define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
20572 | //BIF_CFG_DEV0_EPF7_PCIE_ACS_ENH_CAP_LIST |
20573 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
20574 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
20575 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
20576 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
20577 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
20578 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
20579 | //BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP |
20580 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
20581 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
20582 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
20583 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
20584 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
20585 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
20586 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
20587 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
20588 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
20589 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
20590 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
20591 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
20592 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
20593 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
20594 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
20595 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
20596 | //BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL |
20597 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
20598 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
20599 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
20600 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
20601 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
20602 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
20603 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
20604 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
20605 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
20606 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
20607 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
20608 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
20609 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
20610 | #define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
20611 | //BIF_CFG_DEV0_EPF7_PCIE_PASID_ENH_CAP_LIST |
20612 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
20613 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
20614 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
20615 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
20616 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
20617 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
20618 | //BIF_CFG_DEV0_EPF7_PCIE_PASID_CAP |
20619 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
20620 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
20621 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
20622 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
20623 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
20624 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
20625 | //BIF_CFG_DEV0_EPF7_PCIE_PASID_CNTL |
20626 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
20627 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
20628 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
20629 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
20630 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
20631 | #define BIF_CFG_DEV0_EPF7_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
20632 | //BIF_CFG_DEV0_EPF7_PCIE_ARI_ENH_CAP_LIST |
20633 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
20634 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
20635 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
20636 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
20637 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
20638 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
20639 | //BIF_CFG_DEV0_EPF7_PCIE_ARI_CAP |
20640 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
20641 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
20642 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
20643 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
20644 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
20645 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
20646 | //BIF_CFG_DEV0_EPF7_PCIE_ARI_CNTL |
20647 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
20648 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
20649 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
20650 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
20651 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
20652 | #define BIF_CFG_DEV0_EPF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
20653 | //BIF_CFG_DEV0_EPF7_PCIE_RTR_ENH_CAP_LIST |
20654 | #define BIF_CFG_DEV0_EPF7_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
20655 | #define BIF_CFG_DEV0_EPF7_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
20656 | #define BIF_CFG_DEV0_EPF7_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
20657 | #define BIF_CFG_DEV0_EPF7_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
20658 | #define BIF_CFG_DEV0_EPF7_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
20659 | #define BIF_CFG_DEV0_EPF7_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
20660 | //BIF_CFG_DEV0_EPF7_RTR_DATA1 |
20661 | #define BIF_CFG_DEV0_EPF7_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
20662 | #define BIF_CFG_DEV0_EPF7_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
20663 | #define BIF_CFG_DEV0_EPF7_RTR_DATA1__VALID__SHIFT 0x1f |
20664 | #define BIF_CFG_DEV0_EPF7_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
20665 | #define BIF_CFG_DEV0_EPF7_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
20666 | #define BIF_CFG_DEV0_EPF7_RTR_DATA1__VALID_MASK 0x80000000L |
20667 | //BIF_CFG_DEV0_EPF7_RTR_DATA2 |
20668 | #define BIF_CFG_DEV0_EPF7_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
20669 | #define BIF_CFG_DEV0_EPF7_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
20670 | #define BIF_CFG_DEV0_EPF7_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
20671 | #define BIF_CFG_DEV0_EPF7_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
20672 | |
20673 | |
20674 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp |
20675 | //BIF_CFG_DEV1_EPF0_VENDOR_ID |
20676 | #define BIF_CFG_DEV1_EPF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
20677 | #define BIF_CFG_DEV1_EPF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
20678 | //BIF_CFG_DEV1_EPF0_DEVICE_ID |
20679 | #define BIF_CFG_DEV1_EPF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
20680 | #define BIF_CFG_DEV1_EPF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
20681 | //BIF_CFG_DEV1_EPF0_COMMAND |
20682 | #define BIF_CFG_DEV1_EPF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
20683 | #define BIF_CFG_DEV1_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
20684 | #define BIF_CFG_DEV1_EPF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
20685 | #define BIF_CFG_DEV1_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
20686 | #define BIF_CFG_DEV1_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
20687 | #define BIF_CFG_DEV1_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
20688 | #define BIF_CFG_DEV1_EPF0_COMMAND__AD_STEPPING__SHIFT 0x7 |
20689 | #define BIF_CFG_DEV1_EPF0_COMMAND__SERR_EN__SHIFT 0x8 |
20690 | #define BIF_CFG_DEV1_EPF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
20691 | #define BIF_CFG_DEV1_EPF0_COMMAND__INT_DIS__SHIFT 0xa |
20692 | #define BIF_CFG_DEV1_EPF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
20693 | #define BIF_CFG_DEV1_EPF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
20694 | #define BIF_CFG_DEV1_EPF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
20695 | #define BIF_CFG_DEV1_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
20696 | #define BIF_CFG_DEV1_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
20697 | #define BIF_CFG_DEV1_EPF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
20698 | #define BIF_CFG_DEV1_EPF0_COMMAND__AD_STEPPING_MASK 0x0080L |
20699 | #define BIF_CFG_DEV1_EPF0_COMMAND__SERR_EN_MASK 0x0100L |
20700 | #define BIF_CFG_DEV1_EPF0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
20701 | #define BIF_CFG_DEV1_EPF0_COMMAND__INT_DIS_MASK 0x0400L |
20702 | //BIF_CFG_DEV1_EPF0_STATUS |
20703 | #define BIF_CFG_DEV1_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
20704 | #define BIF_CFG_DEV1_EPF0_STATUS__INT_STATUS__SHIFT 0x3 |
20705 | #define BIF_CFG_DEV1_EPF0_STATUS__CAP_LIST__SHIFT 0x4 |
20706 | #define BIF_CFG_DEV1_EPF0_STATUS__PCI_66_CAP__SHIFT 0x5 |
20707 | #define BIF_CFG_DEV1_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
20708 | #define BIF_CFG_DEV1_EPF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
20709 | #define BIF_CFG_DEV1_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
20710 | #define BIF_CFG_DEV1_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
20711 | #define BIF_CFG_DEV1_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
20712 | #define BIF_CFG_DEV1_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
20713 | #define BIF_CFG_DEV1_EPF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
20714 | #define BIF_CFG_DEV1_EPF0_STATUS__INT_STATUS_MASK 0x0008L |
20715 | #define BIF_CFG_DEV1_EPF0_STATUS__CAP_LIST_MASK 0x0010L |
20716 | #define BIF_CFG_DEV1_EPF0_STATUS__PCI_66_CAP_MASK 0x0020L |
20717 | #define BIF_CFG_DEV1_EPF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
20718 | #define BIF_CFG_DEV1_EPF0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
20719 | #define BIF_CFG_DEV1_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
20720 | #define BIF_CFG_DEV1_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
20721 | #define BIF_CFG_DEV1_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
20722 | #define BIF_CFG_DEV1_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
20723 | //BIF_CFG_DEV1_EPF0_REVISION_ID |
20724 | #define BIF_CFG_DEV1_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
20725 | #define BIF_CFG_DEV1_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
20726 | #define BIF_CFG_DEV1_EPF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
20727 | #define BIF_CFG_DEV1_EPF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
20728 | //BIF_CFG_DEV1_EPF0_PROG_INTERFACE |
20729 | #define BIF_CFG_DEV1_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
20730 | #define BIF_CFG_DEV1_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
20731 | //BIF_CFG_DEV1_EPF0_SUB_CLASS |
20732 | #define BIF_CFG_DEV1_EPF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
20733 | #define BIF_CFG_DEV1_EPF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
20734 | //BIF_CFG_DEV1_EPF0_BASE_CLASS |
20735 | #define BIF_CFG_DEV1_EPF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
20736 | #define BIF_CFG_DEV1_EPF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
20737 | //BIF_CFG_DEV1_EPF0_CACHE_LINE |
20738 | #define BIF_CFG_DEV1_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
20739 | #define BIF_CFG_DEV1_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
20740 | //BIF_CFG_DEV1_EPF0_LATENCY |
20741 | #define BIF_CFG_DEV1_EPF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
20742 | #define BIF_CFG_DEV1_EPF0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
20743 | //BIF_CFG_DEV1_EPF0_HEADER |
20744 | #define 0x0 |
20745 | #define 0x7 |
20746 | #define 0x7FL |
20747 | #define 0x80L |
20748 | //BIF_CFG_DEV1_EPF0_BIST |
20749 | #define BIF_CFG_DEV1_EPF0_BIST__BIST_COMP__SHIFT 0x0 |
20750 | #define BIF_CFG_DEV1_EPF0_BIST__BIST_STRT__SHIFT 0x6 |
20751 | #define BIF_CFG_DEV1_EPF0_BIST__BIST_CAP__SHIFT 0x7 |
20752 | #define BIF_CFG_DEV1_EPF0_BIST__BIST_COMP_MASK 0x0FL |
20753 | #define BIF_CFG_DEV1_EPF0_BIST__BIST_STRT_MASK 0x40L |
20754 | #define BIF_CFG_DEV1_EPF0_BIST__BIST_CAP_MASK 0x80L |
20755 | //BIF_CFG_DEV1_EPF0_BASE_ADDR_1 |
20756 | #define BIF_CFG_DEV1_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
20757 | #define BIF_CFG_DEV1_EPF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
20758 | //BIF_CFG_DEV1_EPF0_BASE_ADDR_2 |
20759 | #define BIF_CFG_DEV1_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
20760 | #define BIF_CFG_DEV1_EPF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
20761 | //BIF_CFG_DEV1_EPF0_BASE_ADDR_3 |
20762 | #define BIF_CFG_DEV1_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
20763 | #define BIF_CFG_DEV1_EPF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
20764 | //BIF_CFG_DEV1_EPF0_BASE_ADDR_4 |
20765 | #define BIF_CFG_DEV1_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
20766 | #define BIF_CFG_DEV1_EPF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
20767 | //BIF_CFG_DEV1_EPF0_BASE_ADDR_5 |
20768 | #define BIF_CFG_DEV1_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
20769 | #define BIF_CFG_DEV1_EPF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
20770 | //BIF_CFG_DEV1_EPF0_BASE_ADDR_6 |
20771 | #define BIF_CFG_DEV1_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
20772 | #define BIF_CFG_DEV1_EPF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
20773 | //BIF_CFG_DEV1_EPF0_ADAPTER_ID |
20774 | #define BIF_CFG_DEV1_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
20775 | #define BIF_CFG_DEV1_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
20776 | #define BIF_CFG_DEV1_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
20777 | #define BIF_CFG_DEV1_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
20778 | //BIF_CFG_DEV1_EPF0_ROM_BASE_ADDR |
20779 | #define BIF_CFG_DEV1_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
20780 | #define BIF_CFG_DEV1_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
20781 | //BIF_CFG_DEV1_EPF0_CAP_PTR |
20782 | #define BIF_CFG_DEV1_EPF0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
20783 | #define BIF_CFG_DEV1_EPF0_CAP_PTR__CAP_PTR_MASK 0xFFL |
20784 | //BIF_CFG_DEV1_EPF0_INTERRUPT_LINE |
20785 | #define BIF_CFG_DEV1_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
20786 | #define BIF_CFG_DEV1_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
20787 | //BIF_CFG_DEV1_EPF0_INTERRUPT_PIN |
20788 | #define BIF_CFG_DEV1_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
20789 | #define BIF_CFG_DEV1_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
20790 | //BIF_CFG_DEV1_EPF0_MIN_GRANT |
20791 | #define BIF_CFG_DEV1_EPF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
20792 | #define BIF_CFG_DEV1_EPF0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
20793 | //BIF_CFG_DEV1_EPF0_MAX_LATENCY |
20794 | #define BIF_CFG_DEV1_EPF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
20795 | #define BIF_CFG_DEV1_EPF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
20796 | //BIF_CFG_DEV1_EPF0_VENDOR_CAP_LIST |
20797 | #define BIF_CFG_DEV1_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
20798 | #define BIF_CFG_DEV1_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
20799 | #define BIF_CFG_DEV1_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
20800 | #define BIF_CFG_DEV1_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
20801 | #define BIF_CFG_DEV1_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
20802 | #define BIF_CFG_DEV1_EPF0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
20803 | //BIF_CFG_DEV1_EPF0_ADAPTER_ID_W |
20804 | #define BIF_CFG_DEV1_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
20805 | #define BIF_CFG_DEV1_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
20806 | #define BIF_CFG_DEV1_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
20807 | #define BIF_CFG_DEV1_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
20808 | //BIF_CFG_DEV1_EPF0_PMI_CAP_LIST |
20809 | #define BIF_CFG_DEV1_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
20810 | #define BIF_CFG_DEV1_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
20811 | #define BIF_CFG_DEV1_EPF0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
20812 | #define BIF_CFG_DEV1_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
20813 | //BIF_CFG_DEV1_EPF0_PMI_CAP |
20814 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__VERSION__SHIFT 0x0 |
20815 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
20816 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
20817 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
20818 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
20819 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
20820 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
20821 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
20822 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__VERSION_MASK 0x0007L |
20823 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
20824 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
20825 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
20826 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
20827 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
20828 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
20829 | #define BIF_CFG_DEV1_EPF0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
20830 | //BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL |
20831 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
20832 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
20833 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
20834 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
20835 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
20836 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
20837 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
20838 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
20839 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
20840 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
20841 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
20842 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
20843 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
20844 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
20845 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
20846 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
20847 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
20848 | #define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
20849 | //BIF_CFG_DEV1_EPF0_SBRN |
20850 | #define BIF_CFG_DEV1_EPF0_SBRN__SBRN__SHIFT 0x0 |
20851 | #define BIF_CFG_DEV1_EPF0_SBRN__SBRN_MASK 0xFFL |
20852 | //BIF_CFG_DEV1_EPF0_FLADJ |
20853 | #define BIF_CFG_DEV1_EPF0_FLADJ__FLADJ__SHIFT 0x0 |
20854 | #define BIF_CFG_DEV1_EPF0_FLADJ__NFC__SHIFT 0x6 |
20855 | #define BIF_CFG_DEV1_EPF0_FLADJ__FLADJ_MASK 0x3FL |
20856 | #define BIF_CFG_DEV1_EPF0_FLADJ__NFC_MASK 0x40L |
20857 | //BIF_CFG_DEV1_EPF0_DBESL_DBESLD |
20858 | #define BIF_CFG_DEV1_EPF0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
20859 | #define BIF_CFG_DEV1_EPF0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
20860 | #define BIF_CFG_DEV1_EPF0_DBESL_DBESLD__DBESL_MASK 0x0FL |
20861 | #define BIF_CFG_DEV1_EPF0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
20862 | //BIF_CFG_DEV1_EPF0_PCIE_CAP_LIST |
20863 | #define BIF_CFG_DEV1_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
20864 | #define BIF_CFG_DEV1_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
20865 | #define BIF_CFG_DEV1_EPF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
20866 | #define BIF_CFG_DEV1_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
20867 | //BIF_CFG_DEV1_EPF0_PCIE_CAP |
20868 | #define BIF_CFG_DEV1_EPF0_PCIE_CAP__VERSION__SHIFT 0x0 |
20869 | #define BIF_CFG_DEV1_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
20870 | #define BIF_CFG_DEV1_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
20871 | #define BIF_CFG_DEV1_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
20872 | #define BIF_CFG_DEV1_EPF0_PCIE_CAP__VERSION_MASK 0x000FL |
20873 | #define BIF_CFG_DEV1_EPF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
20874 | #define BIF_CFG_DEV1_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
20875 | #define BIF_CFG_DEV1_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
20876 | //BIF_CFG_DEV1_EPF0_DEVICE_CAP |
20877 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
20878 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
20879 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
20880 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
20881 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
20882 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
20883 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
20884 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
20885 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
20886 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
20887 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
20888 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
20889 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
20890 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
20891 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
20892 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
20893 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
20894 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
20895 | //BIF_CFG_DEV1_EPF0_DEVICE_CNTL |
20896 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
20897 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
20898 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
20899 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
20900 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
20901 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
20902 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
20903 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
20904 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
20905 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
20906 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
20907 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
20908 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
20909 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
20910 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
20911 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
20912 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
20913 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
20914 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
20915 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
20916 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
20917 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
20918 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
20919 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
20920 | //BIF_CFG_DEV1_EPF0_DEVICE_STATUS |
20921 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
20922 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
20923 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
20924 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
20925 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
20926 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
20927 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
20928 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
20929 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
20930 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
20931 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
20932 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
20933 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
20934 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
20935 | //BIF_CFG_DEV1_EPF0_LINK_CAP |
20936 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
20937 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
20938 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
20939 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
20940 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
20941 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
20942 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
20943 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
20944 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
20945 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
20946 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
20947 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
20948 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
20949 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
20950 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
20951 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
20952 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
20953 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
20954 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
20955 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
20956 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
20957 | #define BIF_CFG_DEV1_EPF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
20958 | //BIF_CFG_DEV1_EPF0_LINK_CNTL |
20959 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
20960 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
20961 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
20962 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
20963 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
20964 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
20965 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
20966 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
20967 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
20968 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
20969 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
20970 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
20971 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
20972 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
20973 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
20974 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
20975 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
20976 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
20977 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
20978 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
20979 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
20980 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
20981 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
20982 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
20983 | //BIF_CFG_DEV1_EPF0_LINK_STATUS |
20984 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
20985 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
20986 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
20987 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
20988 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
20989 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
20990 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
20991 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
20992 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
20993 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
20994 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
20995 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
20996 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
20997 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
20998 | //BIF_CFG_DEV1_EPF0_DEVICE_CAP2 |
20999 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
21000 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
21001 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
21002 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
21003 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
21004 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
21005 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
21006 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
21007 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
21008 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
21009 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
21010 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
21011 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
21012 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
21013 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
21014 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
21015 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
21016 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
21017 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
21018 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
21019 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
21020 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
21021 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
21022 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
21023 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
21024 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
21025 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
21026 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
21027 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
21028 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
21029 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
21030 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
21031 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
21032 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
21033 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
21034 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
21035 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
21036 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
21037 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
21038 | #define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
21039 | //BIF_CFG_DEV1_EPF0_DEVICE_CNTL2 |
21040 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
21041 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
21042 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
21043 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
21044 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
21045 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
21046 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
21047 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
21048 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
21049 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
21050 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
21051 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
21052 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
21053 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
21054 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
21055 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
21056 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
21057 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
21058 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
21059 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
21060 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
21061 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
21062 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
21063 | #define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
21064 | //BIF_CFG_DEV1_EPF0_DEVICE_STATUS2 |
21065 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
21066 | #define BIF_CFG_DEV1_EPF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
21067 | //BIF_CFG_DEV1_EPF0_LINK_CAP2 |
21068 | #define BIF_CFG_DEV1_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
21069 | #define BIF_CFG_DEV1_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
21070 | #define BIF_CFG_DEV1_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
21071 | #define BIF_CFG_DEV1_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
21072 | #define BIF_CFG_DEV1_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
21073 | #define BIF_CFG_DEV1_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
21074 | #define BIF_CFG_DEV1_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
21075 | #define BIF_CFG_DEV1_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
21076 | #define BIF_CFG_DEV1_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
21077 | #define BIF_CFG_DEV1_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
21078 | #define BIF_CFG_DEV1_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
21079 | #define BIF_CFG_DEV1_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
21080 | #define BIF_CFG_DEV1_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
21081 | #define BIF_CFG_DEV1_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
21082 | //BIF_CFG_DEV1_EPF0_LINK_CNTL2 |
21083 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
21084 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
21085 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
21086 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
21087 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
21088 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
21089 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
21090 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
21091 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
21092 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
21093 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
21094 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
21095 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
21096 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
21097 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
21098 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
21099 | //BIF_CFG_DEV1_EPF0_LINK_STATUS2 |
21100 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
21101 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
21102 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
21103 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
21104 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
21105 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
21106 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
21107 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
21108 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
21109 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
21110 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
21111 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
21112 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
21113 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
21114 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
21115 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
21116 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
21117 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
21118 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
21119 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
21120 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
21121 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
21122 | //BIF_CFG_DEV1_EPF0_MSI_CAP_LIST |
21123 | #define BIF_CFG_DEV1_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
21124 | #define BIF_CFG_DEV1_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
21125 | #define BIF_CFG_DEV1_EPF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
21126 | #define BIF_CFG_DEV1_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
21127 | //BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL |
21128 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
21129 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
21130 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
21131 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
21132 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
21133 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
21134 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
21135 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
21136 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
21137 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
21138 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
21139 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
21140 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
21141 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
21142 | //BIF_CFG_DEV1_EPF0_MSI_MSG_ADDR_LO |
21143 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
21144 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
21145 | //BIF_CFG_DEV1_EPF0_MSI_MSG_ADDR_HI |
21146 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
21147 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
21148 | //BIF_CFG_DEV1_EPF0_MSI_MSG_DATA |
21149 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
21150 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
21151 | //BIF_CFG_DEV1_EPF0_MSI_EXT_MSG_DATA |
21152 | #define BIF_CFG_DEV1_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
21153 | #define BIF_CFG_DEV1_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
21154 | //BIF_CFG_DEV1_EPF0_MSI_MASK |
21155 | #define BIF_CFG_DEV1_EPF0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
21156 | #define BIF_CFG_DEV1_EPF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
21157 | //BIF_CFG_DEV1_EPF0_MSI_MSG_DATA_64 |
21158 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
21159 | #define BIF_CFG_DEV1_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
21160 | //BIF_CFG_DEV1_EPF0_MSI_EXT_MSG_DATA_64 |
21161 | #define BIF_CFG_DEV1_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
21162 | #define BIF_CFG_DEV1_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
21163 | //BIF_CFG_DEV1_EPF0_MSI_MASK_64 |
21164 | #define BIF_CFG_DEV1_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
21165 | #define BIF_CFG_DEV1_EPF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
21166 | //BIF_CFG_DEV1_EPF0_MSI_PENDING |
21167 | #define BIF_CFG_DEV1_EPF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
21168 | #define BIF_CFG_DEV1_EPF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
21169 | //BIF_CFG_DEV1_EPF0_MSI_PENDING_64 |
21170 | #define BIF_CFG_DEV1_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
21171 | #define BIF_CFG_DEV1_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
21172 | //BIF_CFG_DEV1_EPF0_MSIX_CAP_LIST |
21173 | #define BIF_CFG_DEV1_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
21174 | #define BIF_CFG_DEV1_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
21175 | #define BIF_CFG_DEV1_EPF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
21176 | #define BIF_CFG_DEV1_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
21177 | //BIF_CFG_DEV1_EPF0_MSIX_MSG_CNTL |
21178 | #define BIF_CFG_DEV1_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
21179 | #define BIF_CFG_DEV1_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
21180 | #define BIF_CFG_DEV1_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
21181 | #define BIF_CFG_DEV1_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
21182 | #define BIF_CFG_DEV1_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
21183 | #define BIF_CFG_DEV1_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
21184 | //BIF_CFG_DEV1_EPF0_MSIX_TABLE |
21185 | #define BIF_CFG_DEV1_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
21186 | #define BIF_CFG_DEV1_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
21187 | #define BIF_CFG_DEV1_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
21188 | #define BIF_CFG_DEV1_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
21189 | //BIF_CFG_DEV1_EPF0_MSIX_PBA |
21190 | #define BIF_CFG_DEV1_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
21191 | #define BIF_CFG_DEV1_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
21192 | #define BIF_CFG_DEV1_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
21193 | #define BIF_CFG_DEV1_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
21194 | //BIF_CFG_DEV1_EPF0_SATA_CAP_0 |
21195 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
21196 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
21197 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
21198 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
21199 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
21200 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
21201 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
21202 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
21203 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
21204 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
21205 | //BIF_CFG_DEV1_EPF0_SATA_CAP_1 |
21206 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
21207 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
21208 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
21209 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
21210 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
21211 | #define BIF_CFG_DEV1_EPF0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
21212 | //BIF_CFG_DEV1_EPF0_SATA_IDP_INDEX |
21213 | #define BIF_CFG_DEV1_EPF0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
21214 | #define BIF_CFG_DEV1_EPF0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
21215 | #define BIF_CFG_DEV1_EPF0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
21216 | #define BIF_CFG_DEV1_EPF0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
21217 | #define BIF_CFG_DEV1_EPF0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
21218 | #define BIF_CFG_DEV1_EPF0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
21219 | //BIF_CFG_DEV1_EPF0_SATA_IDP_DATA |
21220 | #define BIF_CFG_DEV1_EPF0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
21221 | #define BIF_CFG_DEV1_EPF0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
21222 | //BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
21223 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21224 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21225 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21226 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21227 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21228 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21229 | //BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_HDR |
21230 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
21231 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
21232 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
21233 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
21234 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
21235 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
21236 | //BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC1 |
21237 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
21238 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
21239 | //BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC2 |
21240 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
21241 | #define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
21242 | //BIF_CFG_DEV1_EPF0_PCIE_VC_ENH_CAP_LIST |
21243 | #define BIF_CFG_DEV1_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21244 | #define BIF_CFG_DEV1_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21245 | #define BIF_CFG_DEV1_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21246 | #define BIF_CFG_DEV1_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21247 | #define BIF_CFG_DEV1_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21248 | #define BIF_CFG_DEV1_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21249 | //BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1 |
21250 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
21251 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
21252 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
21253 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
21254 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
21255 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
21256 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
21257 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
21258 | //BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG2 |
21259 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
21260 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
21261 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
21262 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
21263 | //BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CNTL |
21264 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
21265 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
21266 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
21267 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
21268 | //BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_STATUS |
21269 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
21270 | #define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
21271 | //BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP |
21272 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
21273 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
21274 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
21275 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
21276 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
21277 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
21278 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
21279 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
21280 | //BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL |
21281 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
21282 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
21283 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
21284 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
21285 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
21286 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
21287 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
21288 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
21289 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
21290 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
21291 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
21292 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
21293 | //BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_STATUS |
21294 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
21295 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
21296 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
21297 | #define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
21298 | //BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP |
21299 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
21300 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
21301 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
21302 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
21303 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
21304 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
21305 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
21306 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
21307 | //BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL |
21308 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
21309 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
21310 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
21311 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
21312 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
21313 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
21314 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
21315 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
21316 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
21317 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
21318 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
21319 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
21320 | //BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_STATUS |
21321 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
21322 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
21323 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
21324 | #define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
21325 | //BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
21326 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21327 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21328 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21329 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21330 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21331 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21332 | //BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS |
21333 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
21334 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
21335 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
21336 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
21337 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
21338 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
21339 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
21340 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
21341 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
21342 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
21343 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
21344 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
21345 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
21346 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
21347 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
21348 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
21349 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
21350 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
21351 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
21352 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
21353 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
21354 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
21355 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
21356 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
21357 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
21358 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
21359 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
21360 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
21361 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
21362 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
21363 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
21364 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
21365 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
21366 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
21367 | //BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK |
21368 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
21369 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
21370 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
21371 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
21372 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
21373 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
21374 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
21375 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
21376 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
21377 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
21378 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
21379 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
21380 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
21381 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
21382 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
21383 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
21384 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
21385 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
21386 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
21387 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
21388 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
21389 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
21390 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
21391 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
21392 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
21393 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
21394 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
21395 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
21396 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
21397 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
21398 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
21399 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
21400 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
21401 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
21402 | //BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY |
21403 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
21404 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
21405 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
21406 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
21407 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
21408 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
21409 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
21410 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
21411 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
21412 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
21413 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
21414 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
21415 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
21416 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
21417 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
21418 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
21419 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
21420 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
21421 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
21422 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
21423 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
21424 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
21425 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
21426 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
21427 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
21428 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
21429 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
21430 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
21431 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
21432 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
21433 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
21434 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
21435 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
21436 | #define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
21437 | //BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS |
21438 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
21439 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
21440 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
21441 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
21442 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
21443 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
21444 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
21445 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
21446 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
21447 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
21448 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
21449 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
21450 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
21451 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
21452 | //BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK |
21453 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
21454 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
21455 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
21456 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
21457 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
21458 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
21459 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
21460 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
21461 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
21462 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
21463 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
21464 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
21465 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
21466 | #define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
21467 | //BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL |
21468 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
21469 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
21470 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
21471 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
21472 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
21473 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
21474 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
21475 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
21476 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
21477 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
21478 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
21479 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
21480 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
21481 | #define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
21482 | //BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG0 |
21483 | #define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
21484 | #define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
21485 | //BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG1 |
21486 | #define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
21487 | #define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
21488 | //BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG2 |
21489 | #define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
21490 | #define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
21491 | //BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG3 |
21492 | #define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
21493 | #define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
21494 | //BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG0 |
21495 | #define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
21496 | #define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
21497 | //BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG1 |
21498 | #define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
21499 | #define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
21500 | //BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG2 |
21501 | #define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
21502 | #define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
21503 | //BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG3 |
21504 | #define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
21505 | #define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
21506 | //BIF_CFG_DEV1_EPF0_PCIE_BAR_ENH_CAP_LIST |
21507 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21508 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21509 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21510 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21511 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21512 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21513 | //BIF_CFG_DEV1_EPF0_PCIE_BAR1_CAP |
21514 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
21515 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
21516 | //BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL |
21517 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
21518 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
21519 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
21520 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
21521 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
21522 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
21523 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
21524 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
21525 | //BIF_CFG_DEV1_EPF0_PCIE_BAR2_CAP |
21526 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
21527 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
21528 | //BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL |
21529 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
21530 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
21531 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
21532 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
21533 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
21534 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
21535 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
21536 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
21537 | //BIF_CFG_DEV1_EPF0_PCIE_BAR3_CAP |
21538 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
21539 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
21540 | //BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL |
21541 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
21542 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
21543 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
21544 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
21545 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
21546 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
21547 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
21548 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
21549 | //BIF_CFG_DEV1_EPF0_PCIE_BAR4_CAP |
21550 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
21551 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
21552 | //BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL |
21553 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
21554 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
21555 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
21556 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
21557 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
21558 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
21559 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
21560 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
21561 | //BIF_CFG_DEV1_EPF0_PCIE_BAR5_CAP |
21562 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
21563 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
21564 | //BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL |
21565 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
21566 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
21567 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
21568 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
21569 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
21570 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
21571 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
21572 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
21573 | //BIF_CFG_DEV1_EPF0_PCIE_BAR6_CAP |
21574 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
21575 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
21576 | //BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL |
21577 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
21578 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
21579 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
21580 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
21581 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
21582 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
21583 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
21584 | #define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
21585 | //BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
21586 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21587 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21588 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21589 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21590 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21591 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21592 | //BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA_SELECT |
21593 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
21594 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
21595 | //BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA |
21596 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
21597 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
21598 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
21599 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
21600 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
21601 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
21602 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
21603 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
21604 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
21605 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
21606 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
21607 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
21608 | //BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_CAP |
21609 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
21610 | #define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
21611 | //BIF_CFG_DEV1_EPF0_PCIE_DPA_ENH_CAP_LIST |
21612 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21613 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21614 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21615 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21616 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21617 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21618 | //BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP |
21619 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
21620 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
21621 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
21622 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
21623 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
21624 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
21625 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
21626 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
21627 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
21628 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
21629 | //BIF_CFG_DEV1_EPF0_PCIE_DPA_LATENCY_INDICATOR |
21630 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
21631 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
21632 | //BIF_CFG_DEV1_EPF0_PCIE_DPA_STATUS |
21633 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
21634 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
21635 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
21636 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
21637 | //BIF_CFG_DEV1_EPF0_PCIE_DPA_CNTL |
21638 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
21639 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
21640 | //BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
21641 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
21642 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
21643 | //BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
21644 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
21645 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
21646 | //BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
21647 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
21648 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
21649 | //BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
21650 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
21651 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
21652 | //BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
21653 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
21654 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
21655 | //BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
21656 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
21657 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
21658 | //BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
21659 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
21660 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
21661 | //BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
21662 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
21663 | #define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
21664 | //BIF_CFG_DEV1_EPF0_PCIE_SECONDARY_ENH_CAP_LIST |
21665 | #define BIF_CFG_DEV1_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21666 | #define BIF_CFG_DEV1_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21667 | #define BIF_CFG_DEV1_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21668 | #define BIF_CFG_DEV1_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21669 | #define BIF_CFG_DEV1_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21670 | #define BIF_CFG_DEV1_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21671 | //BIF_CFG_DEV1_EPF0_PCIE_LINK_CNTL3 |
21672 | #define BIF_CFG_DEV1_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
21673 | #define BIF_CFG_DEV1_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
21674 | #define BIF_CFG_DEV1_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
21675 | #define BIF_CFG_DEV1_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
21676 | #define BIF_CFG_DEV1_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
21677 | #define BIF_CFG_DEV1_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
21678 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_ERROR_STATUS |
21679 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
21680 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
21681 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL |
21682 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21683 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21684 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21685 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21686 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21687 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21688 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21689 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21690 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL |
21691 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21692 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21693 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21694 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21695 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21696 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21697 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21698 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21699 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL |
21700 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21701 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21702 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21703 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21704 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21705 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21706 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21707 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21708 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL |
21709 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21710 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21711 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21712 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21713 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21714 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21715 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21716 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21717 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL |
21718 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21719 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21720 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21721 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21722 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21723 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21724 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21725 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21726 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL |
21727 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21728 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21729 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21730 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21731 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21732 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21733 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21734 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21735 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL |
21736 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21737 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21738 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21739 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21740 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21741 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21742 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21743 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21744 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL |
21745 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21746 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21747 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21748 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21749 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21750 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21751 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21752 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21753 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL |
21754 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21755 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21756 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21757 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21758 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21759 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21760 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21761 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21762 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL |
21763 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21764 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21765 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21766 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21767 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21768 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21769 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21770 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21771 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL |
21772 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21773 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21774 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21775 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21776 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21777 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21778 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21779 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21780 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL |
21781 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21782 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21783 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21784 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21785 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21786 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21787 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21788 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21789 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL |
21790 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21791 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21792 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21793 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21794 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21795 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21796 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21797 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21798 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL |
21799 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21800 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21801 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21802 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21803 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21804 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21805 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21806 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21807 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL |
21808 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21809 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21810 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21811 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21812 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21813 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21814 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21815 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21816 | //BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL |
21817 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
21818 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
21819 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
21820 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
21821 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
21822 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
21823 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
21824 | #define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
21825 | //BIF_CFG_DEV1_EPF0_PCIE_ACS_ENH_CAP_LIST |
21826 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21827 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21828 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21829 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21830 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21831 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21832 | //BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP |
21833 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
21834 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
21835 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
21836 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
21837 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
21838 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
21839 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
21840 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
21841 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
21842 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
21843 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
21844 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
21845 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
21846 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
21847 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
21848 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
21849 | //BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL |
21850 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
21851 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
21852 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
21853 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
21854 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
21855 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
21856 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
21857 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
21858 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
21859 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
21860 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
21861 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
21862 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
21863 | #define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
21864 | //BIF_CFG_DEV1_EPF0_PCIE_PASID_ENH_CAP_LIST |
21865 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21866 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21867 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21868 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21869 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21870 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21871 | //BIF_CFG_DEV1_EPF0_PCIE_PASID_CAP |
21872 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
21873 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
21874 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
21875 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
21876 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
21877 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
21878 | //BIF_CFG_DEV1_EPF0_PCIE_PASID_CNTL |
21879 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
21880 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
21881 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
21882 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
21883 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
21884 | #define BIF_CFG_DEV1_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
21885 | //BIF_CFG_DEV1_EPF0_PCIE_LTR_ENH_CAP_LIST |
21886 | #define BIF_CFG_DEV1_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21887 | #define BIF_CFG_DEV1_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21888 | #define BIF_CFG_DEV1_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21889 | #define BIF_CFG_DEV1_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21890 | #define BIF_CFG_DEV1_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21891 | #define BIF_CFG_DEV1_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21892 | //BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP |
21893 | #define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
21894 | #define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
21895 | #define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
21896 | #define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
21897 | #define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
21898 | #define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
21899 | #define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
21900 | #define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
21901 | //BIF_CFG_DEV1_EPF0_PCIE_ARI_ENH_CAP_LIST |
21902 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21903 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21904 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21905 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21906 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21907 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21908 | //BIF_CFG_DEV1_EPF0_PCIE_ARI_CAP |
21909 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
21910 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
21911 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
21912 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
21913 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
21914 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
21915 | //BIF_CFG_DEV1_EPF0_PCIE_ARI_CNTL |
21916 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
21917 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
21918 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
21919 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
21920 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
21921 | #define BIF_CFG_DEV1_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
21922 | //BIF_CFG_DEV1_EPF0_PCIE_DLF_ENH_CAP_LIST |
21923 | #define BIF_CFG_DEV1_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21924 | #define BIF_CFG_DEV1_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21925 | #define BIF_CFG_DEV1_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21926 | #define BIF_CFG_DEV1_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21927 | #define BIF_CFG_DEV1_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21928 | #define BIF_CFG_DEV1_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21929 | //BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_CAP |
21930 | #define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
21931 | #define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
21932 | #define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
21933 | #define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
21934 | //BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_STATUS |
21935 | #define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
21936 | #define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
21937 | #define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
21938 | #define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
21939 | //BIF_CFG_DEV1_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST |
21940 | #define BIF_CFG_DEV1_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
21941 | #define BIF_CFG_DEV1_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
21942 | #define BIF_CFG_DEV1_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
21943 | #define BIF_CFG_DEV1_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
21944 | #define BIF_CFG_DEV1_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
21945 | #define BIF_CFG_DEV1_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
21946 | //BIF_CFG_DEV1_EPF0_LINK_CAP_16GT |
21947 | #define BIF_CFG_DEV1_EPF0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
21948 | #define BIF_CFG_DEV1_EPF0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
21949 | //BIF_CFG_DEV1_EPF0_LINK_CNTL_16GT |
21950 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
21951 | #define BIF_CFG_DEV1_EPF0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
21952 | //BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT |
21953 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
21954 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
21955 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
21956 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
21957 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
21958 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
21959 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
21960 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
21961 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
21962 | #define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
21963 | //BIF_CFG_DEV1_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT |
21964 | #define BIF_CFG_DEV1_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
21965 | #define BIF_CFG_DEV1_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
21966 | //BIF_CFG_DEV1_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT |
21967 | #define BIF_CFG_DEV1_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
21968 | #define BIF_CFG_DEV1_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
21969 | //BIF_CFG_DEV1_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT |
21970 | #define BIF_CFG_DEV1_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
21971 | #define BIF_CFG_DEV1_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
21972 | //BIF_CFG_DEV1_EPF0_LANE_0_EQUALIZATION_CNTL_16GT |
21973 | #define BIF_CFG_DEV1_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
21974 | #define BIF_CFG_DEV1_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
21975 | #define BIF_CFG_DEV1_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
21976 | #define BIF_CFG_DEV1_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
21977 | //BIF_CFG_DEV1_EPF0_LANE_1_EQUALIZATION_CNTL_16GT |
21978 | #define BIF_CFG_DEV1_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
21979 | #define BIF_CFG_DEV1_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
21980 | #define BIF_CFG_DEV1_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
21981 | #define BIF_CFG_DEV1_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
21982 | //BIF_CFG_DEV1_EPF0_LANE_2_EQUALIZATION_CNTL_16GT |
21983 | #define BIF_CFG_DEV1_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
21984 | #define BIF_CFG_DEV1_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
21985 | #define BIF_CFG_DEV1_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
21986 | #define BIF_CFG_DEV1_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
21987 | //BIF_CFG_DEV1_EPF0_LANE_3_EQUALIZATION_CNTL_16GT |
21988 | #define BIF_CFG_DEV1_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
21989 | #define BIF_CFG_DEV1_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
21990 | #define BIF_CFG_DEV1_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
21991 | #define BIF_CFG_DEV1_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
21992 | //BIF_CFG_DEV1_EPF0_LANE_4_EQUALIZATION_CNTL_16GT |
21993 | #define BIF_CFG_DEV1_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
21994 | #define BIF_CFG_DEV1_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
21995 | #define BIF_CFG_DEV1_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
21996 | #define BIF_CFG_DEV1_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
21997 | //BIF_CFG_DEV1_EPF0_LANE_5_EQUALIZATION_CNTL_16GT |
21998 | #define BIF_CFG_DEV1_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
21999 | #define BIF_CFG_DEV1_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
22000 | #define BIF_CFG_DEV1_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
22001 | #define BIF_CFG_DEV1_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
22002 | //BIF_CFG_DEV1_EPF0_LANE_6_EQUALIZATION_CNTL_16GT |
22003 | #define BIF_CFG_DEV1_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
22004 | #define BIF_CFG_DEV1_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
22005 | #define BIF_CFG_DEV1_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
22006 | #define BIF_CFG_DEV1_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
22007 | //BIF_CFG_DEV1_EPF0_LANE_7_EQUALIZATION_CNTL_16GT |
22008 | #define BIF_CFG_DEV1_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
22009 | #define BIF_CFG_DEV1_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
22010 | #define BIF_CFG_DEV1_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
22011 | #define BIF_CFG_DEV1_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
22012 | //BIF_CFG_DEV1_EPF0_LANE_8_EQUALIZATION_CNTL_16GT |
22013 | #define BIF_CFG_DEV1_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
22014 | #define BIF_CFG_DEV1_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
22015 | #define BIF_CFG_DEV1_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
22016 | #define BIF_CFG_DEV1_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
22017 | //BIF_CFG_DEV1_EPF0_LANE_9_EQUALIZATION_CNTL_16GT |
22018 | #define BIF_CFG_DEV1_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
22019 | #define BIF_CFG_DEV1_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
22020 | #define BIF_CFG_DEV1_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
22021 | #define BIF_CFG_DEV1_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
22022 | //BIF_CFG_DEV1_EPF0_LANE_10_EQUALIZATION_CNTL_16GT |
22023 | #define BIF_CFG_DEV1_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
22024 | #define BIF_CFG_DEV1_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
22025 | #define BIF_CFG_DEV1_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
22026 | #define BIF_CFG_DEV1_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
22027 | //BIF_CFG_DEV1_EPF0_LANE_11_EQUALIZATION_CNTL_16GT |
22028 | #define BIF_CFG_DEV1_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
22029 | #define BIF_CFG_DEV1_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
22030 | #define BIF_CFG_DEV1_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
22031 | #define BIF_CFG_DEV1_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
22032 | //BIF_CFG_DEV1_EPF0_LANE_12_EQUALIZATION_CNTL_16GT |
22033 | #define BIF_CFG_DEV1_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
22034 | #define BIF_CFG_DEV1_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
22035 | #define BIF_CFG_DEV1_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
22036 | #define BIF_CFG_DEV1_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
22037 | //BIF_CFG_DEV1_EPF0_LANE_13_EQUALIZATION_CNTL_16GT |
22038 | #define BIF_CFG_DEV1_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
22039 | #define BIF_CFG_DEV1_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
22040 | #define BIF_CFG_DEV1_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
22041 | #define BIF_CFG_DEV1_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
22042 | //BIF_CFG_DEV1_EPF0_LANE_14_EQUALIZATION_CNTL_16GT |
22043 | #define BIF_CFG_DEV1_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
22044 | #define BIF_CFG_DEV1_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
22045 | #define BIF_CFG_DEV1_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
22046 | #define BIF_CFG_DEV1_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
22047 | //BIF_CFG_DEV1_EPF0_LANE_15_EQUALIZATION_CNTL_16GT |
22048 | #define BIF_CFG_DEV1_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
22049 | #define BIF_CFG_DEV1_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
22050 | #define BIF_CFG_DEV1_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
22051 | #define BIF_CFG_DEV1_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
22052 | //BIF_CFG_DEV1_EPF0_PCIE_MARGINING_ENH_CAP_LIST |
22053 | #define BIF_CFG_DEV1_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
22054 | #define BIF_CFG_DEV1_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
22055 | #define BIF_CFG_DEV1_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
22056 | #define BIF_CFG_DEV1_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
22057 | #define BIF_CFG_DEV1_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
22058 | #define BIF_CFG_DEV1_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
22059 | //BIF_CFG_DEV1_EPF0_MARGINING_PORT_CAP |
22060 | #define BIF_CFG_DEV1_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
22061 | #define BIF_CFG_DEV1_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
22062 | //BIF_CFG_DEV1_EPF0_MARGINING_PORT_STATUS |
22063 | #define BIF_CFG_DEV1_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
22064 | #define BIF_CFG_DEV1_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
22065 | #define BIF_CFG_DEV1_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
22066 | #define BIF_CFG_DEV1_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
22067 | //BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL |
22068 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
22069 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
22070 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
22071 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
22072 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
22073 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
22074 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
22075 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
22076 | //BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS |
22077 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22078 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22079 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
22080 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22081 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22082 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
22083 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
22084 | #define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22085 | //BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL |
22086 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
22087 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
22088 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
22089 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
22090 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
22091 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
22092 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
22093 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
22094 | //BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS |
22095 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22096 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22097 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
22098 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22099 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22100 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
22101 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
22102 | #define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22103 | //BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL |
22104 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
22105 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
22106 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
22107 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
22108 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
22109 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
22110 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
22111 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
22112 | //BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS |
22113 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22114 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22115 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
22116 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22117 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22118 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
22119 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
22120 | #define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22121 | //BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL |
22122 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
22123 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
22124 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
22125 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
22126 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
22127 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
22128 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
22129 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
22130 | //BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS |
22131 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22132 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22133 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
22134 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22135 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22136 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
22137 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
22138 | #define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22139 | //BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL |
22140 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
22141 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
22142 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
22143 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
22144 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
22145 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
22146 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
22147 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
22148 | //BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS |
22149 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22150 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22151 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
22152 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22153 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22154 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
22155 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
22156 | #define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22157 | //BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL |
22158 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
22159 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
22160 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
22161 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
22162 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
22163 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
22164 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
22165 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
22166 | //BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS |
22167 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22168 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22169 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
22170 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22171 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22172 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
22173 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
22174 | #define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22175 | //BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL |
22176 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
22177 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
22178 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
22179 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
22180 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
22181 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
22182 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
22183 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
22184 | //BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS |
22185 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22186 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22187 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
22188 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22189 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22190 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
22191 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
22192 | #define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22193 | //BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL |
22194 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
22195 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
22196 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
22197 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
22198 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
22199 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
22200 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
22201 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
22202 | //BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS |
22203 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22204 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22205 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
22206 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22207 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22208 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
22209 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
22210 | #define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22211 | //BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL |
22212 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
22213 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
22214 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
22215 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
22216 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
22217 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
22218 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
22219 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
22220 | //BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS |
22221 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22222 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22223 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
22224 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22225 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22226 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
22227 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
22228 | #define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22229 | //BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL |
22230 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
22231 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
22232 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
22233 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
22234 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
22235 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
22236 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
22237 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
22238 | //BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS |
22239 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22240 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22241 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
22242 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22243 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22244 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
22245 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
22246 | #define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22247 | //BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL |
22248 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
22249 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
22250 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
22251 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
22252 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
22253 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
22254 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
22255 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
22256 | //BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS |
22257 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22258 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22259 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
22260 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22261 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22262 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
22263 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
22264 | #define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22265 | //BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL |
22266 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
22267 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
22268 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
22269 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
22270 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
22271 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
22272 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
22273 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
22274 | //BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS |
22275 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22276 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22277 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
22278 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22279 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22280 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
22281 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
22282 | #define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22283 | //BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL |
22284 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
22285 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
22286 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
22287 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
22288 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
22289 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
22290 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
22291 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
22292 | //BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS |
22293 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22294 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22295 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
22296 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22297 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22298 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
22299 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
22300 | #define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22301 | //BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL |
22302 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
22303 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
22304 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
22305 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
22306 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
22307 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
22308 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
22309 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
22310 | //BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS |
22311 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22312 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22313 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
22314 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22315 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22316 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
22317 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
22318 | #define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22319 | //BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL |
22320 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
22321 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
22322 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
22323 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
22324 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
22325 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
22326 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
22327 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
22328 | //BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS |
22329 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22330 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22331 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
22332 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22333 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22334 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
22335 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
22336 | #define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22337 | //BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL |
22338 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
22339 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
22340 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
22341 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
22342 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
22343 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
22344 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
22345 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
22346 | //BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS |
22347 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
22348 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
22349 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
22350 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
22351 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
22352 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
22353 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
22354 | #define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
22355 | //BIF_CFG_DEV1_EPF0_PCIE_RTR_ENH_CAP_LIST |
22356 | #define BIF_CFG_DEV1_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
22357 | #define BIF_CFG_DEV1_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
22358 | #define BIF_CFG_DEV1_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
22359 | #define BIF_CFG_DEV1_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
22360 | #define BIF_CFG_DEV1_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
22361 | #define BIF_CFG_DEV1_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
22362 | //BIF_CFG_DEV1_EPF0_RTR_DATA1 |
22363 | #define BIF_CFG_DEV1_EPF0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
22364 | #define BIF_CFG_DEV1_EPF0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
22365 | #define BIF_CFG_DEV1_EPF0_RTR_DATA1__VALID__SHIFT 0x1f |
22366 | #define BIF_CFG_DEV1_EPF0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
22367 | #define BIF_CFG_DEV1_EPF0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
22368 | #define BIF_CFG_DEV1_EPF0_RTR_DATA1__VALID_MASK 0x80000000L |
22369 | //BIF_CFG_DEV1_EPF0_RTR_DATA2 |
22370 | #define BIF_CFG_DEV1_EPF0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
22371 | #define BIF_CFG_DEV1_EPF0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
22372 | #define BIF_CFG_DEV1_EPF0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
22373 | #define BIF_CFG_DEV1_EPF0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
22374 | |
22375 | |
22376 | // addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec |
22377 | //NB_NBCFG0_NB_VENDOR_ID |
22378 | #define NB_NBCFG0_NB_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
22379 | #define NB_NBCFG0_NB_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
22380 | //NB_NBCFG0_NB_DEVICE_ID |
22381 | #define NB_NBCFG0_NB_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
22382 | #define NB_NBCFG0_NB_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
22383 | //NB_NBCFG0_NB_COMMAND |
22384 | #define NB_NBCFG0_NB_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
22385 | #define NB_NBCFG0_NB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
22386 | #define NB_NBCFG0_NB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
22387 | #define NB_NBCFG0_NB_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
22388 | #define NB_NBCFG0_NB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
22389 | #define NB_NBCFG0_NB_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
22390 | //NB_NBCFG0_NB_STATUS |
22391 | #define NB_NBCFG0_NB_STATUS__CAP_LIST__SHIFT 0x4 |
22392 | #define NB_NBCFG0_NB_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
22393 | #define NB_NBCFG0_NB_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
22394 | #define NB_NBCFG0_NB_STATUS__CAP_LIST_MASK 0x0010L |
22395 | #define NB_NBCFG0_NB_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
22396 | #define NB_NBCFG0_NB_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
22397 | //NB_NBCFG0_NB_SUB_CLASS |
22398 | #define NB_NBCFG0_NB_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0 |
22399 | #define NB_NBCFG0_NB_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL |
22400 | //NB_NBCFG0_NB_BASE_CODE |
22401 | #define NB_NBCFG0_NB_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0 |
22402 | #define NB_NBCFG0_NB_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL |
22403 | //NB_NBCFG0_NB_CACHE_LINE |
22404 | #define NB_NBCFG0_NB_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
22405 | #define NB_NBCFG0_NB_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
22406 | //NB_NBCFG0_NB_LATENCY |
22407 | #define NB_NBCFG0_NB_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
22408 | #define NB_NBCFG0_NB_LATENCY__LATENCY_TIMER_MASK 0xFFL |
22409 | //NB_NBCFG0_NB_HEADER |
22410 | #define 0x0 |
22411 | #define 0x7 |
22412 | #define 0x7FL |
22413 | #define 0x80L |
22414 | //NB_NBCFG0_NB_ADAPTER_ID |
22415 | #define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
22416 | #define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
22417 | #define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
22418 | #define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
22419 | //NB_NBCFG0_NB_CAPABILITIES_PTR |
22420 | #define NB_NBCFG0_NB_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0 |
22421 | #define NB_NBCFG0_NB_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL |
22422 | //NB_NBCFG0_NB_HEADER_W |
22423 | #define 0x7 |
22424 | #define 0x00000080L |
22425 | //NB_NBCFG0_NB_PCI_CTRL |
22426 | #define NB_NBCFG0_NB_PCI_CTRL__PMEDis__SHIFT 0x4 |
22427 | #define NB_NBCFG0_NB_PCI_CTRL__SErrDis__SHIFT 0x5 |
22428 | #define NB_NBCFG0_NB_PCI_CTRL__MMIOEnable__SHIFT 0x17 |
22429 | #define NB_NBCFG0_NB_PCI_CTRL__HPDis__SHIFT 0x1a |
22430 | #define NB_NBCFG0_NB_PCI_CTRL__PMEDis_MASK 0x00000010L |
22431 | #define NB_NBCFG0_NB_PCI_CTRL__SErrDis_MASK 0x00000020L |
22432 | #define NB_NBCFG0_NB_PCI_CTRL__MMIOEnable_MASK 0x00800000L |
22433 | #define NB_NBCFG0_NB_PCI_CTRL__HPDis_MASK 0x04000000L |
22434 | //NB_NBCFG0_NB_ADAPTER_ID_W |
22435 | #define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
22436 | #define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
22437 | #define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
22438 | #define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
22439 | //NB_NBCFG0_NBCFG_SCRATCH_0 |
22440 | #define NB_NBCFG0_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0__SHIFT 0x0 |
22441 | #define NB_NBCFG0_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0_MASK 0xFFFFFFFFL |
22442 | //NB_NBCFG0_NBCFG_SCRATCH_1 |
22443 | #define NB_NBCFG0_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1__SHIFT 0x0 |
22444 | #define NB_NBCFG0_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1_MASK 0xFFFFFFFFL |
22445 | //NB_NBCFG0_NBCFG_SCRATCH_2 |
22446 | #define NB_NBCFG0_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2__SHIFT 0x0 |
22447 | #define NB_NBCFG0_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2_MASK 0xFFFFFFFFL |
22448 | //NB_NBCFG0_NBCFG_SCRATCH_3 |
22449 | #define NB_NBCFG0_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3__SHIFT 0x0 |
22450 | #define NB_NBCFG0_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3_MASK 0xFFFFFFFFL |
22451 | //NB_NBCFG0_NBCFG_SCRATCH_4 |
22452 | #define NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT 0x0 |
22453 | #define NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK 0xFFFFFFFFL |
22454 | //NB_NBCFG0_NB_PCI_ARB |
22455 | #define NB_NBCFG0_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 |
22456 | #define NB_NBCFG0_NB_PCI_ARB__PMEMode__SHIFT 0x8 |
22457 | #define NB_NBCFG0_NB_PCI_ARB__PMETurnOff__SHIFT 0x9 |
22458 | #define NB_NBCFG0_NB_PCI_ARB__PMETOAckStatus__SHIFT 0xa |
22459 | #define NB_NBCFG0_NB_PCI_ARB__PMETarget__SHIFT 0x10 |
22460 | #define NB_NBCFG0_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L |
22461 | #define NB_NBCFG0_NB_PCI_ARB__PMEMode_MASK 0x00000100L |
22462 | #define NB_NBCFG0_NB_PCI_ARB__PMETurnOff_MASK 0x00000200L |
22463 | #define NB_NBCFG0_NB_PCI_ARB__PMETOAckStatus_MASK 0x00000400L |
22464 | #define NB_NBCFG0_NB_PCI_ARB__PMETarget_MASK 0x00FF0000L |
22465 | //NB_NBCFG0_NB_DRAM_SLOT1_BASE |
22466 | #define NB_NBCFG0_NB_DRAM_SLOT1_BASE__DRAM_BASE__SHIFT 0x17 |
22467 | #define NB_NBCFG0_NB_DRAM_SLOT1_BASE__DRAM_BASE_MASK 0xFF800000L |
22468 | //NB_NBCFG0_NB_INDEX_DATA_MUTEX0 |
22469 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0__SHIFT 0x0 |
22470 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK__SHIFT 0x1f |
22471 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_MASK 0x7FFFFFFFL |
22472 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK_MASK 0x80000000L |
22473 | //NB_NBCFG0_NB_INDEX_DATA_MUTEX1 |
22474 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1__SHIFT 0x0 |
22475 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK__SHIFT 0x1f |
22476 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_MASK 0x7FFFFFFFL |
22477 | #define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK_MASK 0x80000000L |
22478 | //NB_NBCFG0_NB_VENDOR_ID_W |
22479 | #define NB_NBCFG0_NB_VENDOR_ID_W__VENDOR_ID__SHIFT 0x0 |
22480 | #define NB_NBCFG0_NB_VENDOR_ID_W__VENDOR_ID_MASK 0xFFFFL |
22481 | //NB_NBCFG0_NB_DEVICE_ID_W |
22482 | #define NB_NBCFG0_NB_DEVICE_ID_W__DEVICE_ID__SHIFT 0x0 |
22483 | #define NB_NBCFG0_NB_DEVICE_ID_W__DEVICE_ID_MASK 0xFFFFL |
22484 | |
22485 | |
22486 | // addressBlock: nbio_iohub_nb_fastreg_fastreg_cfgdec |
22487 | //FASTREG_APERTURE |
22488 | #define FASTREG_APERTURE__FASTREG_APERTURE_ID__SHIFT 0x0 |
22489 | #define FASTREG_APERTURE__FASTREG_NODE_ID__SHIFT 0x10 |
22490 | #define FASTREG_APERTURE__FASTREG_TRAN_POSTED__SHIFT 0x1f |
22491 | #define FASTREG_APERTURE__FASTREG_APERTURE_ID_MASK 0x00000FFFL |
22492 | #define FASTREG_APERTURE__FASTREG_NODE_ID_MASK 0x000F0000L |
22493 | #define FASTREG_APERTURE__FASTREG_TRAN_POSTED_MASK 0x80000000L |
22494 | |
22495 | |
22496 | // addressBlock: nbio_iohub_nb_misc_misc_cfgdec |
22497 | //NB_CNTL |
22498 | #define NB_CNTL__HWINIT_WR_LOCK__SHIFT 0x7 |
22499 | #define NB_CNTL__HWINIT_WR_LOCK_MASK 0x00000080L |
22500 | //NB_SPARE1 |
22501 | #define NB_SPARE1__NB_SPARE1_RW__SHIFT 0x0 |
22502 | #define NB_SPARE1__NB_SPARE1_RW_MASK 0xFFFFFFFFL |
22503 | //NB_SPARE2 |
22504 | #define NB_SPARE2__NB_SPARE2_RW1C_0__SHIFT 0x0 |
22505 | #define NB_SPARE2__NB_SPARE2_RW1C_1__SHIFT 0x1 |
22506 | #define NB_SPARE2__NB_SPARE2_RW1C_2__SHIFT 0x2 |
22507 | #define NB_SPARE2__NB_SPARE2_RW1C_3__SHIFT 0x3 |
22508 | #define NB_SPARE2__NB_SPARE2_RW1C_4__SHIFT 0x4 |
22509 | #define NB_SPARE2__NB_SPARE2_RW1C_5__SHIFT 0x5 |
22510 | #define NB_SPARE2__NB_SPARE2_RW1C_6__SHIFT 0x6 |
22511 | #define NB_SPARE2__NB_SPARE2_RW1C_7__SHIFT 0x7 |
22512 | #define NB_SPARE2__NB_SPARE2_RW1C_8__SHIFT 0x8 |
22513 | #define NB_SPARE2__NB_SPARE2_RW1C_9__SHIFT 0x9 |
22514 | #define NB_SPARE2__NB_SPARE2_RW1C_10__SHIFT 0xa |
22515 | #define NB_SPARE2__NB_SPARE2_RW1C_11__SHIFT 0xb |
22516 | #define NB_SPARE2__NB_SPARE2_RW1C_12__SHIFT 0xc |
22517 | #define NB_SPARE2__NB_SPARE2_RW1C_13__SHIFT 0xd |
22518 | #define NB_SPARE2__NB_SPARE2_RW1C_14__SHIFT 0xe |
22519 | #define NB_SPARE2__NB_SPARE2_RW1C_15__SHIFT 0xf |
22520 | #define NB_SPARE2__NB_SPARE2_RW1C_16__SHIFT 0x10 |
22521 | #define NB_SPARE2__NB_SPARE2_RW1C_17__SHIFT 0x11 |
22522 | #define NB_SPARE2__NB_SPARE2_RW1C_18__SHIFT 0x12 |
22523 | #define NB_SPARE2__NB_SPARE2_RW1C_19__SHIFT 0x13 |
22524 | #define NB_SPARE2__NB_SPARE2_RW1C_20__SHIFT 0x14 |
22525 | #define NB_SPARE2__NB_SPARE2_RW1C_21__SHIFT 0x15 |
22526 | #define NB_SPARE2__NB_SPARE2_RW1C_22__SHIFT 0x16 |
22527 | #define NB_SPARE2__NB_SPARE2_RW1C_23__SHIFT 0x17 |
22528 | #define NB_SPARE2__NB_SPARE2_RW1C_24__SHIFT 0x18 |
22529 | #define NB_SPARE2__NB_SPARE2_RW1C_25__SHIFT 0x19 |
22530 | #define NB_SPARE2__NB_SPARE2_RW1C_26__SHIFT 0x1a |
22531 | #define NB_SPARE2__NB_SPARE2_RW1C_27__SHIFT 0x1b |
22532 | #define NB_SPARE2__NB_SPARE2_RW1C_28__SHIFT 0x1c |
22533 | #define NB_SPARE2__NB_SPARE2_RW1C_29__SHIFT 0x1d |
22534 | #define NB_SPARE2__NB_SPARE2_RW1C_30__SHIFT 0x1e |
22535 | #define NB_SPARE2__NB_SPARE2_RW1C_31__SHIFT 0x1f |
22536 | #define NB_SPARE2__NB_SPARE2_RW1C_0_MASK 0x00000001L |
22537 | #define NB_SPARE2__NB_SPARE2_RW1C_1_MASK 0x00000002L |
22538 | #define NB_SPARE2__NB_SPARE2_RW1C_2_MASK 0x00000004L |
22539 | #define NB_SPARE2__NB_SPARE2_RW1C_3_MASK 0x00000008L |
22540 | #define NB_SPARE2__NB_SPARE2_RW1C_4_MASK 0x00000010L |
22541 | #define NB_SPARE2__NB_SPARE2_RW1C_5_MASK 0x00000020L |
22542 | #define NB_SPARE2__NB_SPARE2_RW1C_6_MASK 0x00000040L |
22543 | #define NB_SPARE2__NB_SPARE2_RW1C_7_MASK 0x00000080L |
22544 | #define NB_SPARE2__NB_SPARE2_RW1C_8_MASK 0x00000100L |
22545 | #define NB_SPARE2__NB_SPARE2_RW1C_9_MASK 0x00000200L |
22546 | #define NB_SPARE2__NB_SPARE2_RW1C_10_MASK 0x00000400L |
22547 | #define NB_SPARE2__NB_SPARE2_RW1C_11_MASK 0x00000800L |
22548 | #define NB_SPARE2__NB_SPARE2_RW1C_12_MASK 0x00001000L |
22549 | #define NB_SPARE2__NB_SPARE2_RW1C_13_MASK 0x00002000L |
22550 | #define NB_SPARE2__NB_SPARE2_RW1C_14_MASK 0x00004000L |
22551 | #define NB_SPARE2__NB_SPARE2_RW1C_15_MASK 0x00008000L |
22552 | #define NB_SPARE2__NB_SPARE2_RW1C_16_MASK 0x00010000L |
22553 | #define NB_SPARE2__NB_SPARE2_RW1C_17_MASK 0x00020000L |
22554 | #define NB_SPARE2__NB_SPARE2_RW1C_18_MASK 0x00040000L |
22555 | #define NB_SPARE2__NB_SPARE2_RW1C_19_MASK 0x00080000L |
22556 | #define NB_SPARE2__NB_SPARE2_RW1C_20_MASK 0x00100000L |
22557 | #define NB_SPARE2__NB_SPARE2_RW1C_21_MASK 0x00200000L |
22558 | #define NB_SPARE2__NB_SPARE2_RW1C_22_MASK 0x00400000L |
22559 | #define NB_SPARE2__NB_SPARE2_RW1C_23_MASK 0x00800000L |
22560 | #define NB_SPARE2__NB_SPARE2_RW1C_24_MASK 0x01000000L |
22561 | #define NB_SPARE2__NB_SPARE2_RW1C_25_MASK 0x02000000L |
22562 | #define NB_SPARE2__NB_SPARE2_RW1C_26_MASK 0x04000000L |
22563 | #define NB_SPARE2__NB_SPARE2_RW1C_27_MASK 0x08000000L |
22564 | #define NB_SPARE2__NB_SPARE2_RW1C_28_MASK 0x10000000L |
22565 | #define NB_SPARE2__NB_SPARE2_RW1C_29_MASK 0x20000000L |
22566 | #define NB_SPARE2__NB_SPARE2_RW1C_30_MASK 0x40000000L |
22567 | #define NB_SPARE2__NB_SPARE2_RW1C_31_MASK 0x80000000L |
22568 | //NB_REVID |
22569 | #define NB_REVID__REVISION_ID__SHIFT 0x0 |
22570 | #define NB_REVID__REVISION_ID_MASK 0x000003FFL |
22571 | //NBIO_LCLK_DS_MASK |
22572 | #define NBIO_LCLK_DS_MASK__LCLK_DS_MASK__SHIFT 0x0 |
22573 | #define NBIO_LCLK_DS_MASK__LCLK_DS_MASK_MASK 0xFFFFFFFFL |
22574 | //NB_BUS_NUM_CNTL |
22575 | #define NB_BUS_NUM_CNTL__NB_BUS_NUM__SHIFT 0x0 |
22576 | #define NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode__SHIFT 0x8 |
22577 | #define NB_BUS_NUM_CNTL__NB_BUS_NUM_MASK 0x000000FFL |
22578 | #define NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode_MASK 0x00000100L |
22579 | //NB_MMIOBASE |
22580 | #define NB_MMIOBASE__MMIOBASE__SHIFT 0x0 |
22581 | #define NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL |
22582 | //NB_MMIOLIMIT |
22583 | #define NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 |
22584 | #define NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL |
22585 | //NB_LOWER_TOP_OF_DRAM2 |
22586 | #define NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 |
22587 | #define NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 |
22588 | #define NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L |
22589 | #define NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L |
22590 | //NB_UPPER_TOP_OF_DRAM2 |
22591 | #define NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 |
22592 | #define NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x000001FFL |
22593 | //NB_LOWER_DRAM2_BASE |
22594 | #define NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE__SHIFT 0x17 |
22595 | #define NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE_MASK 0xFF800000L |
22596 | //NB_UPPER_DRAM2_BASE |
22597 | #define NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE__SHIFT 0x0 |
22598 | #define NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE_MASK 0x000001FFL |
22599 | //SB_LOCATION |
22600 | #define SB_LOCATION__SBlocated_Port__SHIFT 0x0 |
22601 | #define SB_LOCATION__SBlocated_Core__SHIFT 0x10 |
22602 | #define SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL |
22603 | #define SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L |
22604 | //SW_US_LOCATION |
22605 | #define SW_US_LOCATION__SW_USlocated_Port__SHIFT 0x0 |
22606 | #define SW_US_LOCATION__SW_USlocated_Core__SHIFT 0x10 |
22607 | #define SW_US_LOCATION__SW_USlocated_Port_MASK 0x0000FFFFL |
22608 | #define SW_US_LOCATION__SW_USlocated_Core_MASK 0xFFFF0000L |
22609 | //SW_NMI_CNTL |
22610 | #define SW_NMI_CNTL__SW_NMI_Status__SHIFT 0x0 |
22611 | #define SW_NMI_CNTL__SW_NMI_Status_MASK 0xFFFFFFFFL |
22612 | //SW_SMI_CNTL |
22613 | #define SW_SMI_CNTL__SW_SMI_Status__SHIFT 0x0 |
22614 | #define SW_SMI_CNTL__SW_SMI_Status_MASK 0xFFFFFFFFL |
22615 | //SW_SCI_CNTL |
22616 | #define SW_SCI_CNTL__SW_SCI_Status__SHIFT 0x0 |
22617 | #define SW_SCI_CNTL__SW_SCI_Status_MASK 0xFFFFFFFFL |
22618 | //APML_SW_STATUS |
22619 | #define APML_SW_STATUS__APML_NMI_STATUS__SHIFT 0x0 |
22620 | #define APML_SW_STATUS__APML_NMI_STATUS_MASK 0x00000001L |
22621 | //SW_GIC_SPI_CNTL |
22622 | #define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector__SHIFT 0x0 |
22623 | #define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector__SHIFT 0x8 |
22624 | #define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector__SHIFT 0x10 |
22625 | #define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector_MASK 0x000000FFL |
22626 | #define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector_MASK 0x0000FF00L |
22627 | #define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector_MASK 0x00FF0000L |
22628 | //SW_SYNCFLOOD_CNTL |
22629 | #define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE__SHIFT 0x0 |
22630 | #define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML__SHIFT 0x1 |
22631 | #define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE_MASK 0x00000001L |
22632 | #define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML_MASK 0x00000002L |
22633 | //NB_TOP_OF_DRAM3 |
22634 | #define NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT 0x0 |
22635 | #define NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT 0x1f |
22636 | #define NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK 0x3FFFFFFFL |
22637 | #define NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK 0x80000000L |
22638 | //CAM_CONTROL |
22639 | #define CAM_CONTROL__CAM_En__SHIFT 0x0 |
22640 | #define CAM_CONTROL__Op__SHIFT 0x1 |
22641 | #define CAM_CONTROL__AccessType__SHIFT 0x2 |
22642 | #define CAM_CONTROL__DataMatchEn__SHIFT 0x3 |
22643 | #define CAM_CONTROL__VC__SHIFT 0x4 |
22644 | #define CAM_CONTROL__CrossTrigger__SHIFT 0x8 |
22645 | #define CAM_CONTROL__CAM_En_MASK 0x00000001L |
22646 | #define CAM_CONTROL__Op_MASK 0x00000002L |
22647 | #define CAM_CONTROL__AccessType_MASK 0x00000004L |
22648 | #define CAM_CONTROL__DataMatchEn_MASK 0x00000008L |
22649 | #define CAM_CONTROL__VC_MASK 0x00000070L |
22650 | #define CAM_CONTROL__CrossTrigger_MASK 0x00000F00L |
22651 | //CAM_TARGET_INDEX_ADDR_BOTTOM |
22652 | #define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom__SHIFT 0x0 |
22653 | #define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom_MASK 0xFFFFFFFFL |
22654 | //CAM_TARGET_INDEX_ADDR_TOP |
22655 | #define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop__SHIFT 0x0 |
22656 | #define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop_MASK 0xFFFFFFFFL |
22657 | //CAM_TARGET_INDEX_DATA |
22658 | #define CAM_TARGET_INDEX_DATA__IndexData__SHIFT 0x0 |
22659 | #define CAM_TARGET_INDEX_DATA__IndexData_MASK 0xFFFFFFFFL |
22660 | //CAM_TARGET_INDEX_DATA_MASK |
22661 | #define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask__SHIFT 0x0 |
22662 | #define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask_MASK 0xFFFFFFFFL |
22663 | //CAM_TARGET_DATA_ADDR_BOTTOM |
22664 | #define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom__SHIFT 0x0 |
22665 | #define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom_MASK 0xFFFFFFFFL |
22666 | //CAM_TARGET_DATA_ADDR_TOP |
22667 | #define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop__SHIFT 0x0 |
22668 | #define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop_MASK 0xFFFFFFFFL |
22669 | //CAM_TARGET_DATA |
22670 | #define CAM_TARGET_DATA__Data__SHIFT 0x0 |
22671 | #define CAM_TARGET_DATA__Data_MASK 0xFFFFFFFFL |
22672 | //CAM_TARGET_DATA_MASK |
22673 | #define CAM_TARGET_DATA_MASK__DataMask__SHIFT 0x0 |
22674 | #define CAM_TARGET_DATA_MASK__DataMask_MASK 0xFFFFFFFFL |
22675 | //PCIE_VDM_NODE0_CTRL4 |
22676 | #define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE__SHIFT 0x0 |
22677 | #define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT__SHIFT 0x8 |
22678 | #define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT__SHIFT 0x1f |
22679 | #define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE_MASK 0x000000FFL |
22680 | #define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT_MASK 0x0000FF00L |
22681 | #define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT_MASK 0x80000000L |
22682 | //PCIE_VDM_CNTL2 |
22683 | #define PCIE_VDM_CNTL2__VdmP2pMode__SHIFT 0x0 |
22684 | #define PCIE_VDM_CNTL2__MCTPT2SMUEn__SHIFT 0x4 |
22685 | #define PCIE_VDM_CNTL2__AMDVDM2SMUEn__SHIFT 0x5 |
22686 | #define PCIE_VDM_CNTL2__OtherVDM2SMUEn__SHIFT 0x6 |
22687 | #define PCIE_VDM_CNTL2__MCTPMasterValid__SHIFT 0xf |
22688 | #define PCIE_VDM_CNTL2__MCTPMasterID__SHIFT 0x10 |
22689 | #define PCIE_VDM_CNTL2__VdmP2pMode_MASK 0x00000003L |
22690 | #define PCIE_VDM_CNTL2__MCTPT2SMUEn_MASK 0x00000010L |
22691 | #define PCIE_VDM_CNTL2__AMDVDM2SMUEn_MASK 0x00000020L |
22692 | #define PCIE_VDM_CNTL2__OtherVDM2SMUEn_MASK 0x00000040L |
22693 | #define PCIE_VDM_CNTL2__MCTPMasterValid_MASK 0x00008000L |
22694 | #define PCIE_VDM_CNTL2__MCTPMasterID_MASK 0xFFFF0000L |
22695 | //PCIE_VDM_CNTL3 |
22696 | #define PCIE_VDM_CNTL3__APMTPMasterValid__SHIFT 0xf |
22697 | #define PCIE_VDM_CNTL3__APMTPMasterID__SHIFT 0x10 |
22698 | #define PCIE_VDM_CNTL3__APMTPMasterValid_MASK 0x00008000L |
22699 | #define PCIE_VDM_CNTL3__APMTPMasterID_MASK 0xFFFF0000L |
22700 | //STALL_CONTROL_XBARPORT0_0 |
22701 | #define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn__SHIFT 0x0 |
22702 | #define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn__SHIFT 0x4 |
22703 | #define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn__SHIFT 0x8 |
22704 | #define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn__SHIFT 0xc |
22705 | #define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn__SHIFT 0x10 |
22706 | #define STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn__SHIFT 0x14 |
22707 | #define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn__SHIFT 0x1c |
22708 | #define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn_MASK 0x00000003L |
22709 | #define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn_MASK 0x00000030L |
22710 | #define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn_MASK 0x00000300L |
22711 | #define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn_MASK 0x00003000L |
22712 | #define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn_MASK 0x00030000L |
22713 | #define STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn_MASK 0x00300000L |
22714 | #define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn_MASK 0x30000000L |
22715 | //STALL_CONTROL_XBARPORT0_1 |
22716 | #define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn__SHIFT 0x0 |
22717 | #define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn__SHIFT 0x4 |
22718 | #define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn__SHIFT 0x8 |
22719 | #define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn__SHIFT 0xc |
22720 | #define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn__SHIFT 0x10 |
22721 | #define STALL_CONTROL_XBARPORT0_1__StallVC5RspEn__SHIFT 0x14 |
22722 | #define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn__SHIFT 0x1c |
22723 | #define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn_MASK 0x00000003L |
22724 | #define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn_MASK 0x00000030L |
22725 | #define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn_MASK 0x00000300L |
22726 | #define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn_MASK 0x00003000L |
22727 | #define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn_MASK 0x00030000L |
22728 | #define STALL_CONTROL_XBARPORT0_1__StallVC5RspEn_MASK 0x00300000L |
22729 | #define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn_MASK 0x30000000L |
22730 | //STALL_CONTROL_XBARPORT1_0 |
22731 | #define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn__SHIFT 0x0 |
22732 | #define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn__SHIFT 0x4 |
22733 | #define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn__SHIFT 0x8 |
22734 | #define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn__SHIFT 0xc |
22735 | #define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn__SHIFT 0x10 |
22736 | #define STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn__SHIFT 0x14 |
22737 | #define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn__SHIFT 0x1c |
22738 | #define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn_MASK 0x00000003L |
22739 | #define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn_MASK 0x00000030L |
22740 | #define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn_MASK 0x00000300L |
22741 | #define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn_MASK 0x00003000L |
22742 | #define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn_MASK 0x00030000L |
22743 | #define STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn_MASK 0x00300000L |
22744 | #define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn_MASK 0x30000000L |
22745 | //STALL_CONTROL_XBARPORT1_1 |
22746 | #define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn__SHIFT 0x0 |
22747 | #define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn__SHIFT 0x4 |
22748 | #define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn__SHIFT 0x8 |
22749 | #define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn__SHIFT 0xc |
22750 | #define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn__SHIFT 0x10 |
22751 | #define STALL_CONTROL_XBARPORT1_1__StallVC5RspEn__SHIFT 0x14 |
22752 | #define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn__SHIFT 0x1c |
22753 | #define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn_MASK 0x00000003L |
22754 | #define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn_MASK 0x00000030L |
22755 | #define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn_MASK 0x00000300L |
22756 | #define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn_MASK 0x00003000L |
22757 | #define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn_MASK 0x00030000L |
22758 | #define STALL_CONTROL_XBARPORT1_1__StallVC5RspEn_MASK 0x00300000L |
22759 | #define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn_MASK 0x30000000L |
22760 | //STALL_CONTROL_XBARPORT2_0 |
22761 | #define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn__SHIFT 0x0 |
22762 | #define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn__SHIFT 0x4 |
22763 | #define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn__SHIFT 0x8 |
22764 | #define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn__SHIFT 0xc |
22765 | #define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn__SHIFT 0x10 |
22766 | #define STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn__SHIFT 0x14 |
22767 | #define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn__SHIFT 0x1c |
22768 | #define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn_MASK 0x00000003L |
22769 | #define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn_MASK 0x00000030L |
22770 | #define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn_MASK 0x00000300L |
22771 | #define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn_MASK 0x00003000L |
22772 | #define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn_MASK 0x00030000L |
22773 | #define STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn_MASK 0x00300000L |
22774 | #define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn_MASK 0x30000000L |
22775 | //STALL_CONTROL_XBARPORT2_1 |
22776 | #define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn__SHIFT 0x0 |
22777 | #define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn__SHIFT 0x4 |
22778 | #define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn__SHIFT 0x8 |
22779 | #define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn__SHIFT 0xc |
22780 | #define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn__SHIFT 0x10 |
22781 | #define STALL_CONTROL_XBARPORT2_1__StallVC5RspEn__SHIFT 0x14 |
22782 | #define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn__SHIFT 0x1c |
22783 | #define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn_MASK 0x00000003L |
22784 | #define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn_MASK 0x00000030L |
22785 | #define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn_MASK 0x00000300L |
22786 | #define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn_MASK 0x00003000L |
22787 | #define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn_MASK 0x00030000L |
22788 | #define STALL_CONTROL_XBARPORT2_1__StallVC5RspEn_MASK 0x00300000L |
22789 | #define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn_MASK 0x30000000L |
22790 | //STALL_CONTROL_XBARPORT3_0 |
22791 | #define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn__SHIFT 0x0 |
22792 | #define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn__SHIFT 0x4 |
22793 | #define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn__SHIFT 0x8 |
22794 | #define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn__SHIFT 0xc |
22795 | #define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn__SHIFT 0x10 |
22796 | #define STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn__SHIFT 0x14 |
22797 | #define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn__SHIFT 0x1c |
22798 | #define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn_MASK 0x00000003L |
22799 | #define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn_MASK 0x00000030L |
22800 | #define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn_MASK 0x00000300L |
22801 | #define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn_MASK 0x00003000L |
22802 | #define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn_MASK 0x00030000L |
22803 | #define STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn_MASK 0x00300000L |
22804 | #define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn_MASK 0x30000000L |
22805 | //STALL_CONTROL_XBARPORT3_1 |
22806 | #define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn__SHIFT 0x0 |
22807 | #define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn__SHIFT 0x4 |
22808 | #define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn__SHIFT 0x8 |
22809 | #define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn__SHIFT 0xc |
22810 | #define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn__SHIFT 0x10 |
22811 | #define STALL_CONTROL_XBARPORT3_1__StallVC5RspEn__SHIFT 0x14 |
22812 | #define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn__SHIFT 0x1c |
22813 | #define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn_MASK 0x00000003L |
22814 | #define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn_MASK 0x00000030L |
22815 | #define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn_MASK 0x00000300L |
22816 | #define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn_MASK 0x00003000L |
22817 | #define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn_MASK 0x00030000L |
22818 | #define STALL_CONTROL_XBARPORT3_1__StallVC5RspEn_MASK 0x00300000L |
22819 | #define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn_MASK 0x30000000L |
22820 | //STALL_CONTROL_XBARPORT4_0 |
22821 | #define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn__SHIFT 0x0 |
22822 | #define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn__SHIFT 0x4 |
22823 | #define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn__SHIFT 0x8 |
22824 | #define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn__SHIFT 0xc |
22825 | #define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn__SHIFT 0x10 |
22826 | #define STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn__SHIFT 0x14 |
22827 | #define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn__SHIFT 0x1c |
22828 | #define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn_MASK 0x00000003L |
22829 | #define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn_MASK 0x00000030L |
22830 | #define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn_MASK 0x00000300L |
22831 | #define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn_MASK 0x00003000L |
22832 | #define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn_MASK 0x00030000L |
22833 | #define STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn_MASK 0x00300000L |
22834 | #define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn_MASK 0x30000000L |
22835 | //STALL_CONTROL_XBARPORT4_1 |
22836 | #define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn__SHIFT 0x0 |
22837 | #define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn__SHIFT 0x4 |
22838 | #define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn__SHIFT 0x8 |
22839 | #define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn__SHIFT 0xc |
22840 | #define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn__SHIFT 0x10 |
22841 | #define STALL_CONTROL_XBARPORT4_1__StallVC5RspEn__SHIFT 0x14 |
22842 | #define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn__SHIFT 0x1c |
22843 | #define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn_MASK 0x00000003L |
22844 | #define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn_MASK 0x00000030L |
22845 | #define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn_MASK 0x00000300L |
22846 | #define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn_MASK 0x00003000L |
22847 | #define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn_MASK 0x00030000L |
22848 | #define STALL_CONTROL_XBARPORT4_1__StallVC5RspEn_MASK 0x00300000L |
22849 | #define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn_MASK 0x30000000L |
22850 | //STALL_CONTROL_XBARPORT5_0 |
22851 | #define STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn__SHIFT 0x0 |
22852 | #define STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn__SHIFT 0x4 |
22853 | #define STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn__SHIFT 0x8 |
22854 | #define STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn__SHIFT 0xc |
22855 | #define STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn__SHIFT 0x10 |
22856 | #define STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn__SHIFT 0x14 |
22857 | #define STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn__SHIFT 0x1c |
22858 | #define STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn_MASK 0x00000003L |
22859 | #define STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn_MASK 0x00000030L |
22860 | #define STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn_MASK 0x00000300L |
22861 | #define STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn_MASK 0x00003000L |
22862 | #define STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn_MASK 0x00030000L |
22863 | #define STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn_MASK 0x00300000L |
22864 | #define STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn_MASK 0x30000000L |
22865 | //STALL_CONTROL_XBARPORT5_1 |
22866 | #define STALL_CONTROL_XBARPORT5_1__StallVC0RspEn__SHIFT 0x0 |
22867 | #define STALL_CONTROL_XBARPORT5_1__StallVC1RspEn__SHIFT 0x4 |
22868 | #define STALL_CONTROL_XBARPORT5_1__StallVC2RspEn__SHIFT 0x8 |
22869 | #define STALL_CONTROL_XBARPORT5_1__StallVC3RspEn__SHIFT 0xc |
22870 | #define STALL_CONTROL_XBARPORT5_1__StallVC4RspEn__SHIFT 0x10 |
22871 | #define STALL_CONTROL_XBARPORT5_1__StallVC5RspEn__SHIFT 0x14 |
22872 | #define STALL_CONTROL_XBARPORT5_1__StallVC7RspEn__SHIFT 0x1c |
22873 | #define STALL_CONTROL_XBARPORT5_1__StallVC0RspEn_MASK 0x00000003L |
22874 | #define STALL_CONTROL_XBARPORT5_1__StallVC1RspEn_MASK 0x00000030L |
22875 | #define STALL_CONTROL_XBARPORT5_1__StallVC2RspEn_MASK 0x00000300L |
22876 | #define STALL_CONTROL_XBARPORT5_1__StallVC3RspEn_MASK 0x00003000L |
22877 | #define STALL_CONTROL_XBARPORT5_1__StallVC4RspEn_MASK 0x00030000L |
22878 | #define STALL_CONTROL_XBARPORT5_1__StallVC5RspEn_MASK 0x00300000L |
22879 | #define STALL_CONTROL_XBARPORT5_1__StallVC7RspEn_MASK 0x30000000L |
22880 | //NB_DRAM3_BASE |
22881 | #define NB_DRAM3_BASE__DRAM3_BASE__SHIFT 0x0 |
22882 | #define NB_DRAM3_BASE__DRAM3_BASE_MASK 0x3FFFFFFFL |
22883 | //PSP_BASE_ADDR_LO |
22884 | #define PSP_BASE_ADDR_LO__PSP_MMIO_EN__SHIFT 0x0 |
22885 | #define PSP_BASE_ADDR_LO__PSP_MMIO_LOCK__SHIFT 0x8 |
22886 | #define PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO__SHIFT 0x14 |
22887 | #define PSP_BASE_ADDR_LO__PSP_MMIO_EN_MASK 0x00000001L |
22888 | #define PSP_BASE_ADDR_LO__PSP_MMIO_LOCK_MASK 0x00000100L |
22889 | #define PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO_MASK 0xFFF00000L |
22890 | //PSP_BASE_ADDR_HI |
22891 | #define PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI__SHIFT 0x0 |
22892 | #define PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI_MASK 0x0000FFFFL |
22893 | //SMU_BASE_ADDR_LO |
22894 | #define SMU_BASE_ADDR_LO__SMU_MMIO_EN__SHIFT 0x0 |
22895 | #define SMU_BASE_ADDR_LO__SMU_MMIO_LOCK__SHIFT 0x1 |
22896 | #define SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO__SHIFT 0x14 |
22897 | #define SMU_BASE_ADDR_LO__SMU_MMIO_EN_MASK 0x00000001L |
22898 | #define SMU_BASE_ADDR_LO__SMU_MMIO_LOCK_MASK 0x00000002L |
22899 | #define SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO_MASK 0xFFF00000L |
22900 | //SMU_BASE_ADDR_HI |
22901 | #define SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI__SHIFT 0x0 |
22902 | #define SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI_MASK 0x0000FFFFL |
22903 | //FASTREG_BASE_ADDR_LO |
22904 | #define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_EN__SHIFT 0x0 |
22905 | #define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_LOCK__SHIFT 0x1 |
22906 | #define FASTREG_BASE_ADDR_LO__FASTREG_BASE_ADDR_LO__SHIFT 0x14 |
22907 | #define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_EN_MASK 0x00000001L |
22908 | #define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_LOCK_MASK 0x00000002L |
22909 | #define FASTREG_BASE_ADDR_LO__FASTREG_BASE_ADDR_LO_MASK 0xFFF00000L |
22910 | //FASTREG_BASE_ADDR_HI |
22911 | #define FASTREG_BASE_ADDR_HI__FASTREG_BASE_ADDR_HI__SHIFT 0x0 |
22912 | #define FASTREG_BASE_ADDR_HI__FASTREG_BASE_ADDR_HI_MASK 0x0000FFFFL |
22913 | //FASTREGCNTL_BASE_ADDR_LO |
22914 | #define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_EN__SHIFT 0x0 |
22915 | #define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_LOCK__SHIFT 0x1 |
22916 | #define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_BASE_ADDR_LO__SHIFT 0xc |
22917 | #define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_EN_MASK 0x00000001L |
22918 | #define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_LOCK_MASK 0x00000002L |
22919 | #define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_BASE_ADDR_LO_MASK 0xFFFFF000L |
22920 | //FASTREGCNTL_BASE_ADDR_HI |
22921 | #define FASTREGCNTL_BASE_ADDR_HI__FASTREGCNTL_BASE_ADDR_HI__SHIFT 0x0 |
22922 | #define FASTREGCNTL_BASE_ADDR_HI__FASTREGCNTL_BASE_ADDR_HI_MASK 0x0000FFFFL |
22923 | //MISC0_BASE_ADDR_LO |
22924 | #define MISC0_BASE_ADDR_LO__MISC0_MMIO_EN__SHIFT 0x0 |
22925 | #define MISC0_BASE_ADDR_LO__MISC0_MMIO_LOCK__SHIFT 0x1 |
22926 | #define MISC0_BASE_ADDR_LO__MISC0_BASE_ADDR_LO__SHIFT 0x14 |
22927 | #define MISC0_BASE_ADDR_LO__MISC0_MMIO_EN_MASK 0x00000001L |
22928 | #define MISC0_BASE_ADDR_LO__MISC0_MMIO_LOCK_MASK 0x00000002L |
22929 | #define MISC0_BASE_ADDR_LO__MISC0_BASE_ADDR_LO_MASK 0xFFF00000L |
22930 | //MISC0_BASE_ADDR_HI |
22931 | #define MISC0_BASE_ADDR_HI__MISC0_BASE_ADDR_HI__SHIFT 0x0 |
22932 | #define MISC0_BASE_ADDR_HI__MISC0_BASE_ADDR_HI_MASK 0x0000FFFFL |
22933 | //MISC1_BASE_ADDR_LO |
22934 | #define MISC1_BASE_ADDR_LO__MISC1_MMIO_EN__SHIFT 0x0 |
22935 | #define MISC1_BASE_ADDR_LO__MISC1_MMIO_LOCK__SHIFT 0x1 |
22936 | #define MISC1_BASE_ADDR_LO__MISC1_BASE_ADDR_LO__SHIFT 0x14 |
22937 | #define MISC1_BASE_ADDR_LO__MISC1_MMIO_EN_MASK 0x00000001L |
22938 | #define MISC1_BASE_ADDR_LO__MISC1_MMIO_LOCK_MASK 0x00000002L |
22939 | #define MISC1_BASE_ADDR_LO__MISC1_BASE_ADDR_LO_MASK 0xFFF00000L |
22940 | //MISC1_BASE_ADDR_HI |
22941 | #define MISC1_BASE_ADDR_HI__MISC1_BASE_ADDR_HI__SHIFT 0x0 |
22942 | #define MISC1_BASE_ADDR_HI__MISC1_BASE_ADDR_HI_MASK 0x0000FFFFL |
22943 | //MISC2_BASE_ADDR_LO |
22944 | #define MISC2_BASE_ADDR_LO__MISC2_MMIO_EN__SHIFT 0x0 |
22945 | #define MISC2_BASE_ADDR_LO__MISC2_MMIO_LOCK__SHIFT 0x1 |
22946 | #define MISC2_BASE_ADDR_LO__MISC2_BASE_ADDR_LO__SHIFT 0x14 |
22947 | #define MISC2_BASE_ADDR_LO__MISC2_MMIO_EN_MASK 0x00000001L |
22948 | #define MISC2_BASE_ADDR_LO__MISC2_MMIO_LOCK_MASK 0x00000002L |
22949 | #define MISC2_BASE_ADDR_LO__MISC2_BASE_ADDR_LO_MASK 0xFFF00000L |
22950 | //MISC2_BASE_ADDR_HI |
22951 | #define MISC2_BASE_ADDR_HI__MISC2_BASE_ADDR_HI__SHIFT 0x0 |
22952 | #define MISC2_BASE_ADDR_HI__MISC2_BASE_ADDR_HI_MASK 0x0000FFFFL |
22953 | //MISC3_BASE_ADDR_LO |
22954 | #define MISC3_BASE_ADDR_LO__MISC3_MMIO_EN__SHIFT 0x0 |
22955 | #define MISC3_BASE_ADDR_LO__MISC3_MMIO_LOCK__SHIFT 0x1 |
22956 | #define MISC3_BASE_ADDR_LO__MISC3_BASE_ADDR_LO__SHIFT 0x14 |
22957 | #define MISC3_BASE_ADDR_LO__MISC3_MMIO_EN_MASK 0x00000001L |
22958 | #define MISC3_BASE_ADDR_LO__MISC3_MMIO_LOCK_MASK 0x00000002L |
22959 | #define MISC3_BASE_ADDR_LO__MISC3_BASE_ADDR_LO_MASK 0xFFF00000L |
22960 | //MISC3_BASE_ADDR_HI |
22961 | #define MISC3_BASE_ADDR_HI__MISC3_BASE_ADDR_HI__SHIFT 0x0 |
22962 | #define MISC3_BASE_ADDR_HI__MISC3_BASE_ADDR_HI_MASK 0x0000FFFFL |
22963 | //SCRATCH_4 |
22964 | #define SCRATCH_4__SCRATCH_4__SHIFT 0x0 |
22965 | #define SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL |
22966 | //SCRATCH_5 |
22967 | #define SCRATCH_5__SCRATCH_5__SHIFT 0x0 |
22968 | #define SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL |
22969 | //SMU_BLOCK_CPU |
22970 | #define SMU_BLOCK_CPU__SMUBlockCPU_Valid__SHIFT 0x0 |
22971 | #define SMU_BLOCK_CPU__SMUBlockCPU_Valid_MASK 0x00000001L |
22972 | //SMU_BLOCK_CPU_STATUS |
22973 | #define SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status__SHIFT 0x0 |
22974 | #define SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status_MASK 0x00000001L |
22975 | //TRAP_STATUS |
22976 | #define TRAP_STATUS__TrapReqValid__SHIFT 0x0 |
22977 | #define TRAP_STATUS__TrapNumber__SHIFT 0x8 |
22978 | #define TRAP_STATUS__TrapReqValid_MASK 0x00000001L |
22979 | #define TRAP_STATUS__TrapNumber_MASK 0x00000F00L |
22980 | //TRAP_REQUEST0 |
22981 | #define TRAP_REQUEST0__TrapReqAddrLo__SHIFT 0x2 |
22982 | #define TRAP_REQUEST0__TrapReqAddrLo_MASK 0xFFFFFFFCL |
22983 | //TRAP_REQUEST1 |
22984 | #define TRAP_REQUEST1__TrapReqAddrHi__SHIFT 0x0 |
22985 | #define TRAP_REQUEST1__TrapReqAddrHi_MASK 0xFFFFFFFFL |
22986 | //TRAP_REQUEST2 |
22987 | #define TRAP_REQUEST2__TrapReqCmd__SHIFT 0x0 |
22988 | #define TRAP_REQUEST2__TrapAttr__SHIFT 0x8 |
22989 | #define TRAP_REQUEST2__TrapReqLen__SHIFT 0x10 |
22990 | #define TRAP_REQUEST2__TrapReqCmd_MASK 0x0000003FL |
22991 | #define TRAP_REQUEST2__TrapAttr_MASK 0x0000FF00L |
22992 | #define TRAP_REQUEST2__TrapReqLen_MASK 0x003F0000L |
22993 | //TRAP_REQUEST3 |
22994 | #define TRAP_REQUEST3__TrapReqVC__SHIFT 0x0 |
22995 | #define TRAP_REQUEST3__TrapReqBlockLevel__SHIFT 0x4 |
22996 | #define TRAP_REQUEST3__TrapReqChain__SHIFT 0x6 |
22997 | #define TRAP_REQUEST3__TrapReqIO__SHIFT 0x7 |
22998 | #define TRAP_REQUEST3__TrapReqPassPW__SHIFT 0x8 |
22999 | #define TRAP_REQUEST3__TrapReqRspPassPW__SHIFT 0x9 |
23000 | #define TRAP_REQUEST3__TrapReqUnitID__SHIFT 0x10 |
23001 | #define TRAP_REQUEST3__TrapReqVC_MASK 0x00000007L |
23002 | #define TRAP_REQUEST3__TrapReqBlockLevel_MASK 0x00000030L |
23003 | #define TRAP_REQUEST3__TrapReqChain_MASK 0x00000040L |
23004 | #define TRAP_REQUEST3__TrapReqIO_MASK 0x00000080L |
23005 | #define TRAP_REQUEST3__TrapReqPassPW_MASK 0x00000100L |
23006 | #define TRAP_REQUEST3__TrapReqRspPassPW_MASK 0x00000200L |
23007 | #define TRAP_REQUEST3__TrapReqUnitID_MASK 0x003F0000L |
23008 | //TRAP_REQUEST4 |
23009 | #define TRAP_REQUEST4__TrapReqSecLevel__SHIFT 0x0 |
23010 | #define TRAP_REQUEST4__TrapReqSecLevel_MASK 0x0000000FL |
23011 | //TRAP_REQUEST5 |
23012 | #define TRAP_REQUEST5__TrapReqDataVC__SHIFT 0x0 |
23013 | #define TRAP_REQUEST5__TrapReqDataErr__SHIFT 0x4 |
23014 | #define TRAP_REQUEST5__TrapReqDataParity__SHIFT 0x8 |
23015 | #define TRAP_REQUEST5__TrapReqDataVC_MASK 0x00000007L |
23016 | #define TRAP_REQUEST5__TrapReqDataErr_MASK 0x00000010L |
23017 | #define TRAP_REQUEST5__TrapReqDataParity_MASK 0x0000FF00L |
23018 | //TRAP_REQUEST_DATASTRB0 |
23019 | #define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0__SHIFT 0x0 |
23020 | #define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0_MASK 0xFFFFFFFFL |
23021 | //TRAP_REQUEST_DATASTRB1 |
23022 | #define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1__SHIFT 0x0 |
23023 | #define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1_MASK 0xFFFFFFFFL |
23024 | //TRAP_REQUEST_DATA0 |
23025 | #define TRAP_REQUEST_DATA0__TrapReqData0__SHIFT 0x0 |
23026 | #define TRAP_REQUEST_DATA0__TrapReqData0_MASK 0xFFFFFFFFL |
23027 | //TRAP_REQUEST_DATA1 |
23028 | #define TRAP_REQUEST_DATA1__TrapReqData1__SHIFT 0x0 |
23029 | #define TRAP_REQUEST_DATA1__TrapReqData1_MASK 0xFFFFFFFFL |
23030 | //TRAP_REQUEST_DATA2 |
23031 | #define TRAP_REQUEST_DATA2__TrapReqData2__SHIFT 0x0 |
23032 | #define TRAP_REQUEST_DATA2__TrapReqData2_MASK 0xFFFFFFFFL |
23033 | //TRAP_REQUEST_DATA3 |
23034 | #define TRAP_REQUEST_DATA3__TrapReqData3__SHIFT 0x0 |
23035 | #define TRAP_REQUEST_DATA3__TrapReqData3_MASK 0xFFFFFFFFL |
23036 | //TRAP_REQUEST_DATA4 |
23037 | #define TRAP_REQUEST_DATA4__TrapReqData4__SHIFT 0x0 |
23038 | #define TRAP_REQUEST_DATA4__TrapReqData4_MASK 0xFFFFFFFFL |
23039 | //TRAP_REQUEST_DATA5 |
23040 | #define TRAP_REQUEST_DATA5__TrapReqData5__SHIFT 0x0 |
23041 | #define TRAP_REQUEST_DATA5__TrapReqData5_MASK 0xFFFFFFFFL |
23042 | //TRAP_REQUEST_DATA6 |
23043 | #define TRAP_REQUEST_DATA6__TrapReqData6__SHIFT 0x0 |
23044 | #define TRAP_REQUEST_DATA6__TrapReqData6_MASK 0xFFFFFFFFL |
23045 | //TRAP_REQUEST_DATA7 |
23046 | #define TRAP_REQUEST_DATA7__TrapReqData7__SHIFT 0x0 |
23047 | #define TRAP_REQUEST_DATA7__TrapReqData7_MASK 0xFFFFFFFFL |
23048 | //TRAP_REQUEST_DATA8 |
23049 | #define TRAP_REQUEST_DATA8__TrapReqData8__SHIFT 0x0 |
23050 | #define TRAP_REQUEST_DATA8__TrapReqData8_MASK 0xFFFFFFFFL |
23051 | //TRAP_REQUEST_DATA9 |
23052 | #define TRAP_REQUEST_DATA9__TrapReqData9__SHIFT 0x0 |
23053 | #define TRAP_REQUEST_DATA9__TrapReqData9_MASK 0xFFFFFFFFL |
23054 | //TRAP_REQUEST_DATA10 |
23055 | #define TRAP_REQUEST_DATA10__TrapReqData10__SHIFT 0x0 |
23056 | #define TRAP_REQUEST_DATA10__TrapReqData10_MASK 0xFFFFFFFFL |
23057 | //TRAP_REQUEST_DATA11 |
23058 | #define TRAP_REQUEST_DATA11__TrapReqData11__SHIFT 0x0 |
23059 | #define TRAP_REQUEST_DATA11__TrapReqData11_MASK 0xFFFFFFFFL |
23060 | //TRAP_REQUEST_DATA12 |
23061 | #define TRAP_REQUEST_DATA12__TrapReqData12__SHIFT 0x0 |
23062 | #define TRAP_REQUEST_DATA12__TrapReqData12_MASK 0xFFFFFFFFL |
23063 | //TRAP_REQUEST_DATA13 |
23064 | #define TRAP_REQUEST_DATA13__TrapReqData13__SHIFT 0x0 |
23065 | #define TRAP_REQUEST_DATA13__TrapReqData13_MASK 0xFFFFFFFFL |
23066 | //TRAP_REQUEST_DATA14 |
23067 | #define TRAP_REQUEST_DATA14__TrapReqData14__SHIFT 0x0 |
23068 | #define TRAP_REQUEST_DATA14__TrapReqData14_MASK 0xFFFFFFFFL |
23069 | //TRAP_REQUEST_DATA15 |
23070 | #define TRAP_REQUEST_DATA15__TrapReqData15__SHIFT 0x0 |
23071 | #define TRAP_REQUEST_DATA15__TrapReqData15_MASK 0xFFFFFFFFL |
23072 | //TRAP_RESPONSE_CONTROL |
23073 | #define TRAP_RESPONSE_CONTROL__TrapRspTrigger__SHIFT 0x0 |
23074 | #define TRAP_RESPONSE_CONTROL__TrapRspReqPassthru__SHIFT 0x1 |
23075 | #define TRAP_RESPONSE_CONTROL__TrapRspTrigger_MASK 0x00000001L |
23076 | #define TRAP_RESPONSE_CONTROL__TrapRspReqPassthru_MASK 0x00000002L |
23077 | //TRAP_RESPONSE0 |
23078 | #define TRAP_RESPONSE0__TrapRspPassPW__SHIFT 0x0 |
23079 | #define TRAP_RESPONSE0__TrapRspStatus__SHIFT 0x4 |
23080 | #define TRAP_RESPONSE0__TrapRspDataStatus__SHIFT 0x10 |
23081 | #define TRAP_RESPONSE0__TrapRspPassPW_MASK 0x00000001L |
23082 | #define TRAP_RESPONSE0__TrapRspStatus_MASK 0x000000F0L |
23083 | #define TRAP_RESPONSE0__TrapRspDataStatus_MASK 0x00FF0000L |
23084 | //TRAP_RESPONSE_DATA0 |
23085 | #define TRAP_RESPONSE_DATA0__TrapRdRspData0__SHIFT 0x0 |
23086 | #define TRAP_RESPONSE_DATA0__TrapRdRspData0_MASK 0xFFFFFFFFL |
23087 | //TRAP_RESPONSE_DATA1 |
23088 | #define TRAP_RESPONSE_DATA1__TrapRdRspData1__SHIFT 0x0 |
23089 | #define TRAP_RESPONSE_DATA1__TrapRdRspData1_MASK 0xFFFFFFFFL |
23090 | //TRAP_RESPONSE_DATA2 |
23091 | #define TRAP_RESPONSE_DATA2__TrapRdRspData2__SHIFT 0x0 |
23092 | #define TRAP_RESPONSE_DATA2__TrapRdRspData2_MASK 0xFFFFFFFFL |
23093 | //TRAP_RESPONSE_DATA3 |
23094 | #define TRAP_RESPONSE_DATA3__TrapRdRspData3__SHIFT 0x0 |
23095 | #define TRAP_RESPONSE_DATA3__TrapRdRspData3_MASK 0xFFFFFFFFL |
23096 | //TRAP_RESPONSE_DATA4 |
23097 | #define TRAP_RESPONSE_DATA4__TrapRdRspData4__SHIFT 0x0 |
23098 | #define TRAP_RESPONSE_DATA4__TrapRdRspData4_MASK 0xFFFFFFFFL |
23099 | //TRAP_RESPONSE_DATA5 |
23100 | #define TRAP_RESPONSE_DATA5__TrapRdRspData5__SHIFT 0x0 |
23101 | #define TRAP_RESPONSE_DATA5__TrapRdRspData5_MASK 0xFFFFFFFFL |
23102 | //TRAP_RESPONSE_DATA6 |
23103 | #define TRAP_RESPONSE_DATA6__TrapRdRspData6__SHIFT 0x0 |
23104 | #define TRAP_RESPONSE_DATA6__TrapRdRspData6_MASK 0xFFFFFFFFL |
23105 | //TRAP_RESPONSE_DATA7 |
23106 | #define TRAP_RESPONSE_DATA7__TrapRdRspData7__SHIFT 0x0 |
23107 | #define TRAP_RESPONSE_DATA7__TrapRdRspData7_MASK 0xFFFFFFFFL |
23108 | //TRAP_RESPONSE_DATA8 |
23109 | #define TRAP_RESPONSE_DATA8__TrapRdRspData8__SHIFT 0x0 |
23110 | #define TRAP_RESPONSE_DATA8__TrapRdRspData8_MASK 0xFFFFFFFFL |
23111 | //TRAP_RESPONSE_DATA9 |
23112 | #define TRAP_RESPONSE_DATA9__TrapRdRspData9__SHIFT 0x0 |
23113 | #define TRAP_RESPONSE_DATA9__TrapRdRspData9_MASK 0xFFFFFFFFL |
23114 | //TRAP_RESPONSE_DATA10 |
23115 | #define TRAP_RESPONSE_DATA10__TrapRdRspData10__SHIFT 0x0 |
23116 | #define TRAP_RESPONSE_DATA10__TrapRdRspData10_MASK 0xFFFFFFFFL |
23117 | //TRAP_RESPONSE_DATA11 |
23118 | #define TRAP_RESPONSE_DATA11__TrapRdRspData11__SHIFT 0x0 |
23119 | #define TRAP_RESPONSE_DATA11__TrapRdRspData11_MASK 0xFFFFFFFFL |
23120 | //TRAP_RESPONSE_DATA12 |
23121 | #define TRAP_RESPONSE_DATA12__TrapRdRspData12__SHIFT 0x0 |
23122 | #define TRAP_RESPONSE_DATA12__TrapRdRspData12_MASK 0xFFFFFFFFL |
23123 | //TRAP_RESPONSE_DATA13 |
23124 | #define TRAP_RESPONSE_DATA13__TrapRdRspData13__SHIFT 0x0 |
23125 | #define TRAP_RESPONSE_DATA13__TrapRdRspData13_MASK 0xFFFFFFFFL |
23126 | //TRAP_RESPONSE_DATA14 |
23127 | #define TRAP_RESPONSE_DATA14__TrapRdRspData14__SHIFT 0x0 |
23128 | #define TRAP_RESPONSE_DATA14__TrapRdRspData14_MASK 0xFFFFFFFFL |
23129 | //TRAP_RESPONSE_DATA15 |
23130 | #define TRAP_RESPONSE_DATA15__TrapRdRspData15__SHIFT 0x0 |
23131 | #define TRAP_RESPONSE_DATA15__TrapRdRspData15_MASK 0xFFFFFFFFL |
23132 | //TRAP0_CONTROL0 |
23133 | #define TRAP0_CONTROL0__Trap0En__SHIFT 0x0 |
23134 | #define TRAP0_CONTROL0__Trap0SMUIntr__SHIFT 0x3 |
23135 | #define TRAP0_CONTROL0__Trap0CrossTrigger__SHIFT 0x18 |
23136 | #define TRAP0_CONTROL0__Trap0En_MASK 0x00000001L |
23137 | #define TRAP0_CONTROL0__Trap0SMUIntr_MASK 0x00000008L |
23138 | #define TRAP0_CONTROL0__Trap0CrossTrigger_MASK 0x0F000000L |
23139 | //TRAP0_ADDRESS_LO |
23140 | #define TRAP0_ADDRESS_LO__Trap0AddrLo__SHIFT 0x2 |
23141 | #define TRAP0_ADDRESS_LO__Trap0AddrLo_MASK 0xFFFFFFFCL |
23142 | //TRAP0_ADDRESS_HI |
23143 | #define TRAP0_ADDRESS_HI__Trap0AddrHi__SHIFT 0x0 |
23144 | #define TRAP0_ADDRESS_HI__Trap0AddrHi_MASK 0xFFFFFFFFL |
23145 | //TRAP0_COMMAND |
23146 | #define TRAP0_COMMAND__Trap0Cmd0__SHIFT 0x0 |
23147 | #define TRAP0_COMMAND__Trap0Cmd1__SHIFT 0x8 |
23148 | #define TRAP0_COMMAND__Trap0Cmd0_MASK 0x0000003FL |
23149 | #define TRAP0_COMMAND__Trap0Cmd1_MASK 0x00003F00L |
23150 | //TRAP0_ADDRESS_LO_MASK |
23151 | #define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask__SHIFT 0x2 |
23152 | #define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask_MASK 0xFFFFFFFCL |
23153 | //TRAP0_ADDRESS_HI_MASK |
23154 | #define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask__SHIFT 0x0 |
23155 | #define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask_MASK 0xFFFFFFFFL |
23156 | //TRAP0_COMMAND_MASK |
23157 | #define TRAP0_COMMAND_MASK__Trap0Cmd0Mask__SHIFT 0x0 |
23158 | #define TRAP0_COMMAND_MASK__Trap0Cmd1Mask__SHIFT 0x8 |
23159 | #define TRAP0_COMMAND_MASK__Trap0Cmd0Mask_MASK 0x0000003FL |
23160 | #define TRAP0_COMMAND_MASK__Trap0Cmd1Mask_MASK 0x00003F00L |
23161 | //TRAP1_CONTROL0 |
23162 | #define TRAP1_CONTROL0__Trap1En__SHIFT 0x0 |
23163 | #define TRAP1_CONTROL0__Trap1SMUIntr__SHIFT 0x3 |
23164 | #define TRAP1_CONTROL0__Trap1CrossTrigger__SHIFT 0x18 |
23165 | #define TRAP1_CONTROL0__Trap1En_MASK 0x00000001L |
23166 | #define TRAP1_CONTROL0__Trap1SMUIntr_MASK 0x00000008L |
23167 | #define TRAP1_CONTROL0__Trap1CrossTrigger_MASK 0x0F000000L |
23168 | //TRAP1_ADDRESS_LO |
23169 | #define TRAP1_ADDRESS_LO__Trap1AddrLo__SHIFT 0x2 |
23170 | #define TRAP1_ADDRESS_LO__Trap1AddrLo_MASK 0xFFFFFFFCL |
23171 | //TRAP1_ADDRESS_HI |
23172 | #define TRAP1_ADDRESS_HI__Trap1AddrHi__SHIFT 0x0 |
23173 | #define TRAP1_ADDRESS_HI__Trap1AddrHi_MASK 0xFFFFFFFFL |
23174 | //TRAP1_COMMAND |
23175 | #define TRAP1_COMMAND__Trap1Cmd0__SHIFT 0x0 |
23176 | #define TRAP1_COMMAND__Trap1Cmd1__SHIFT 0x8 |
23177 | #define TRAP1_COMMAND__Trap1Cmd0_MASK 0x0000003FL |
23178 | #define TRAP1_COMMAND__Trap1Cmd1_MASK 0x00003F00L |
23179 | //TRAP1_ADDRESS_LO_MASK |
23180 | #define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask__SHIFT 0x2 |
23181 | #define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask_MASK 0xFFFFFFFCL |
23182 | //TRAP1_ADDRESS_HI_MASK |
23183 | #define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask__SHIFT 0x0 |
23184 | #define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask_MASK 0xFFFFFFFFL |
23185 | //TRAP1_COMMAND_MASK |
23186 | #define TRAP1_COMMAND_MASK__Trap1Cmd0Mask__SHIFT 0x0 |
23187 | #define TRAP1_COMMAND_MASK__Trap1Cmd1Mask__SHIFT 0x8 |
23188 | #define TRAP1_COMMAND_MASK__Trap1Cmd0Mask_MASK 0x0000003FL |
23189 | #define TRAP1_COMMAND_MASK__Trap1Cmd1Mask_MASK 0x00003F00L |
23190 | //TRAP2_CONTROL0 |
23191 | #define TRAP2_CONTROL0__Trap2En__SHIFT 0x0 |
23192 | #define TRAP2_CONTROL0__Trap2SMUIntr__SHIFT 0x3 |
23193 | #define TRAP2_CONTROL0__Trap2CrossTrigger__SHIFT 0x18 |
23194 | #define TRAP2_CONTROL0__Trap2En_MASK 0x00000001L |
23195 | #define TRAP2_CONTROL0__Trap2SMUIntr_MASK 0x00000008L |
23196 | #define TRAP2_CONTROL0__Trap2CrossTrigger_MASK 0x0F000000L |
23197 | //TRAP2_ADDRESS_LO |
23198 | #define TRAP2_ADDRESS_LO__Trap2AddrLo__SHIFT 0x2 |
23199 | #define TRAP2_ADDRESS_LO__Trap2AddrLo_MASK 0xFFFFFFFCL |
23200 | //TRAP2_ADDRESS_HI |
23201 | #define TRAP2_ADDRESS_HI__Trap2AddrHi__SHIFT 0x0 |
23202 | #define TRAP2_ADDRESS_HI__Trap2AddrHi_MASK 0xFFFFFFFFL |
23203 | //TRAP2_COMMAND |
23204 | #define TRAP2_COMMAND__Trap2Cmd0__SHIFT 0x0 |
23205 | #define TRAP2_COMMAND__Trap2Cmd1__SHIFT 0x8 |
23206 | #define TRAP2_COMMAND__Trap2Cmd0_MASK 0x0000003FL |
23207 | #define TRAP2_COMMAND__Trap2Cmd1_MASK 0x00003F00L |
23208 | //TRAP2_ADDRESS_LO_MASK |
23209 | #define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask__SHIFT 0x2 |
23210 | #define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask_MASK 0xFFFFFFFCL |
23211 | //TRAP2_ADDRESS_HI_MASK |
23212 | #define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask__SHIFT 0x0 |
23213 | #define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask_MASK 0xFFFFFFFFL |
23214 | //TRAP2_COMMAND_MASK |
23215 | #define TRAP2_COMMAND_MASK__Trap2Cmd0Mask__SHIFT 0x0 |
23216 | #define TRAP2_COMMAND_MASK__Trap2Cmd1Mask__SHIFT 0x8 |
23217 | #define TRAP2_COMMAND_MASK__Trap2Cmd0Mask_MASK 0x0000003FL |
23218 | #define TRAP2_COMMAND_MASK__Trap2Cmd1Mask_MASK 0x00003F00L |
23219 | //TRAP3_CONTROL0 |
23220 | #define TRAP3_CONTROL0__Trap3En__SHIFT 0x0 |
23221 | #define TRAP3_CONTROL0__Trap3SMUIntr__SHIFT 0x3 |
23222 | #define TRAP3_CONTROL0__Trap3CrossTrigger__SHIFT 0x18 |
23223 | #define TRAP3_CONTROL0__Trap3En_MASK 0x00000001L |
23224 | #define TRAP3_CONTROL0__Trap3SMUIntr_MASK 0x00000008L |
23225 | #define TRAP3_CONTROL0__Trap3CrossTrigger_MASK 0x0F000000L |
23226 | //TRAP3_ADDRESS_LO |
23227 | #define TRAP3_ADDRESS_LO__Trap3AddrLo__SHIFT 0x2 |
23228 | #define TRAP3_ADDRESS_LO__Trap3AddrLo_MASK 0xFFFFFFFCL |
23229 | //TRAP3_ADDRESS_HI |
23230 | #define TRAP3_ADDRESS_HI__Trap3AddrHi__SHIFT 0x0 |
23231 | #define TRAP3_ADDRESS_HI__Trap3AddrHi_MASK 0xFFFFFFFFL |
23232 | //TRAP3_COMMAND |
23233 | #define TRAP3_COMMAND__Trap3Cmd0__SHIFT 0x0 |
23234 | #define TRAP3_COMMAND__Trap3Cmd1__SHIFT 0x8 |
23235 | #define TRAP3_COMMAND__Trap3Cmd0_MASK 0x0000003FL |
23236 | #define TRAP3_COMMAND__Trap3Cmd1_MASK 0x00003F00L |
23237 | //TRAP3_ADDRESS_LO_MASK |
23238 | #define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask__SHIFT 0x2 |
23239 | #define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask_MASK 0xFFFFFFFCL |
23240 | //TRAP3_ADDRESS_HI_MASK |
23241 | #define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask__SHIFT 0x0 |
23242 | #define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask_MASK 0xFFFFFFFFL |
23243 | //TRAP3_COMMAND_MASK |
23244 | #define TRAP3_COMMAND_MASK__Trap3Cmd0Mask__SHIFT 0x0 |
23245 | #define TRAP3_COMMAND_MASK__Trap3Cmd1Mask__SHIFT 0x8 |
23246 | #define TRAP3_COMMAND_MASK__Trap3Cmd0Mask_MASK 0x0000003FL |
23247 | #define TRAP3_COMMAND_MASK__Trap3Cmd1Mask_MASK 0x00003F00L |
23248 | //TRAP4_CONTROL0 |
23249 | #define TRAP4_CONTROL0__Trap4En__SHIFT 0x0 |
23250 | #define TRAP4_CONTROL0__Trap4SMUIntr__SHIFT 0x3 |
23251 | #define TRAP4_CONTROL0__Trap4CrossTrigger__SHIFT 0x18 |
23252 | #define TRAP4_CONTROL0__Trap4En_MASK 0x00000001L |
23253 | #define TRAP4_CONTROL0__Trap4SMUIntr_MASK 0x00000008L |
23254 | #define TRAP4_CONTROL0__Trap4CrossTrigger_MASK 0x0F000000L |
23255 | //TRAP4_ADDRESS_LO |
23256 | #define TRAP4_ADDRESS_LO__Trap4AddrLo__SHIFT 0x2 |
23257 | #define TRAP4_ADDRESS_LO__Trap4AddrLo_MASK 0xFFFFFFFCL |
23258 | //TRAP4_ADDRESS_HI |
23259 | #define TRAP4_ADDRESS_HI__Trap4AddrHi__SHIFT 0x0 |
23260 | #define TRAP4_ADDRESS_HI__Trap4AddrHi_MASK 0xFFFFFFFFL |
23261 | //TRAP4_COMMAND |
23262 | #define TRAP4_COMMAND__Trap4Cmd0__SHIFT 0x0 |
23263 | #define TRAP4_COMMAND__Trap4Cmd1__SHIFT 0x8 |
23264 | #define TRAP4_COMMAND__Trap4Cmd0_MASK 0x0000003FL |
23265 | #define TRAP4_COMMAND__Trap4Cmd1_MASK 0x00003F00L |
23266 | //TRAP4_ADDRESS_LO_MASK |
23267 | #define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask__SHIFT 0x2 |
23268 | #define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask_MASK 0xFFFFFFFCL |
23269 | //TRAP4_ADDRESS_HI_MASK |
23270 | #define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask__SHIFT 0x0 |
23271 | #define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask_MASK 0xFFFFFFFFL |
23272 | //TRAP4_COMMAND_MASK |
23273 | #define TRAP4_COMMAND_MASK__Trap4Cmd0Mask__SHIFT 0x0 |
23274 | #define TRAP4_COMMAND_MASK__Trap4Cmd1Mask__SHIFT 0x8 |
23275 | #define TRAP4_COMMAND_MASK__Trap4Cmd0Mask_MASK 0x0000003FL |
23276 | #define TRAP4_COMMAND_MASK__Trap4Cmd1Mask_MASK 0x00003F00L |
23277 | //TRAP5_CONTROL0 |
23278 | #define TRAP5_CONTROL0__Trap5En__SHIFT 0x0 |
23279 | #define TRAP5_CONTROL0__Trap5SMUIntr__SHIFT 0x3 |
23280 | #define TRAP5_CONTROL0__Trap5CrossTrigger__SHIFT 0x18 |
23281 | #define TRAP5_CONTROL0__Trap5En_MASK 0x00000001L |
23282 | #define TRAP5_CONTROL0__Trap5SMUIntr_MASK 0x00000008L |
23283 | #define TRAP5_CONTROL0__Trap5CrossTrigger_MASK 0x0F000000L |
23284 | //TRAP5_ADDRESS_LO |
23285 | #define TRAP5_ADDRESS_LO__Trap5AddrLo__SHIFT 0x2 |
23286 | #define TRAP5_ADDRESS_LO__Trap5AddrLo_MASK 0xFFFFFFFCL |
23287 | //TRAP5_ADDRESS_HI |
23288 | #define TRAP5_ADDRESS_HI__Trap5AddrHi__SHIFT 0x0 |
23289 | #define TRAP5_ADDRESS_HI__Trap5AddrHi_MASK 0xFFFFFFFFL |
23290 | //TRAP5_COMMAND |
23291 | #define TRAP5_COMMAND__Trap5Cmd0__SHIFT 0x0 |
23292 | #define TRAP5_COMMAND__Trap5Cmd1__SHIFT 0x8 |
23293 | #define TRAP5_COMMAND__Trap5Cmd0_MASK 0x0000003FL |
23294 | #define TRAP5_COMMAND__Trap5Cmd1_MASK 0x00003F00L |
23295 | //TRAP5_ADDRESS_LO_MASK |
23296 | #define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask__SHIFT 0x2 |
23297 | #define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask_MASK 0xFFFFFFFCL |
23298 | //TRAP5_ADDRESS_HI_MASK |
23299 | #define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask__SHIFT 0x0 |
23300 | #define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask_MASK 0xFFFFFFFFL |
23301 | //TRAP5_COMMAND_MASK |
23302 | #define TRAP5_COMMAND_MASK__Trap5Cmd0Mask__SHIFT 0x0 |
23303 | #define TRAP5_COMMAND_MASK__Trap5Cmd1Mask__SHIFT 0x8 |
23304 | #define TRAP5_COMMAND_MASK__Trap5Cmd0Mask_MASK 0x0000003FL |
23305 | #define TRAP5_COMMAND_MASK__Trap5Cmd1Mask_MASK 0x00003F00L |
23306 | //TRAP6_CONTROL0 |
23307 | #define TRAP6_CONTROL0__Trap6En__SHIFT 0x0 |
23308 | #define TRAP6_CONTROL0__Trap6SMUIntr__SHIFT 0x3 |
23309 | #define TRAP6_CONTROL0__Trap6CrossTrigger__SHIFT 0x18 |
23310 | #define TRAP6_CONTROL0__Trap6En_MASK 0x00000001L |
23311 | #define TRAP6_CONTROL0__Trap6SMUIntr_MASK 0x00000008L |
23312 | #define TRAP6_CONTROL0__Trap6CrossTrigger_MASK 0x0F000000L |
23313 | //TRAP6_ADDRESS_LO |
23314 | #define TRAP6_ADDRESS_LO__Trap6AddrLo__SHIFT 0x2 |
23315 | #define TRAP6_ADDRESS_LO__Trap6AddrLo_MASK 0xFFFFFFFCL |
23316 | //TRAP6_ADDRESS_HI |
23317 | #define TRAP6_ADDRESS_HI__Trap6AddrHi__SHIFT 0x0 |
23318 | #define TRAP6_ADDRESS_HI__Trap6AddrHi_MASK 0xFFFFFFFFL |
23319 | //TRAP6_COMMAND |
23320 | #define TRAP6_COMMAND__Trap6Cmd0__SHIFT 0x0 |
23321 | #define TRAP6_COMMAND__Trap6Cmd1__SHIFT 0x8 |
23322 | #define TRAP6_COMMAND__Trap6Cmd0_MASK 0x0000003FL |
23323 | #define TRAP6_COMMAND__Trap6Cmd1_MASK 0x00003F00L |
23324 | //TRAP6_ADDRESS_LO_MASK |
23325 | #define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask__SHIFT 0x2 |
23326 | #define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask_MASK 0xFFFFFFFCL |
23327 | //TRAP6_ADDRESS_HI_MASK |
23328 | #define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask__SHIFT 0x0 |
23329 | #define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask_MASK 0xFFFFFFFFL |
23330 | //TRAP6_COMMAND_MASK |
23331 | #define TRAP6_COMMAND_MASK__Trap6Cmd0Mask__SHIFT 0x0 |
23332 | #define TRAP6_COMMAND_MASK__Trap6Cmd1Mask__SHIFT 0x8 |
23333 | #define TRAP6_COMMAND_MASK__Trap6Cmd0Mask_MASK 0x0000003FL |
23334 | #define TRAP6_COMMAND_MASK__Trap6Cmd1Mask_MASK 0x00003F00L |
23335 | //TRAP7_CONTROL0 |
23336 | #define TRAP7_CONTROL0__Trap7En__SHIFT 0x0 |
23337 | #define TRAP7_CONTROL0__Trap7SMUIntr__SHIFT 0x3 |
23338 | #define TRAP7_CONTROL0__Trap7CrossTrigger__SHIFT 0x18 |
23339 | #define TRAP7_CONTROL0__Trap7En_MASK 0x00000001L |
23340 | #define TRAP7_CONTROL0__Trap7SMUIntr_MASK 0x00000008L |
23341 | #define TRAP7_CONTROL0__Trap7CrossTrigger_MASK 0x0F000000L |
23342 | //TRAP7_ADDRESS_LO |
23343 | #define TRAP7_ADDRESS_LO__Trap7AddrLo__SHIFT 0x2 |
23344 | #define TRAP7_ADDRESS_LO__Trap7AddrLo_MASK 0xFFFFFFFCL |
23345 | //TRAP7_ADDRESS_HI |
23346 | #define TRAP7_ADDRESS_HI__Trap7AddrHi__SHIFT 0x0 |
23347 | #define TRAP7_ADDRESS_HI__Trap7AddrHi_MASK 0xFFFFFFFFL |
23348 | //TRAP7_COMMAND |
23349 | #define TRAP7_COMMAND__Trap7Cmd0__SHIFT 0x0 |
23350 | #define TRAP7_COMMAND__Trap7Cmd1__SHIFT 0x8 |
23351 | #define TRAP7_COMMAND__Trap7Cmd0_MASK 0x0000003FL |
23352 | #define TRAP7_COMMAND__Trap7Cmd1_MASK 0x00003F00L |
23353 | //TRAP7_ADDRESS_LO_MASK |
23354 | #define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask__SHIFT 0x2 |
23355 | #define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask_MASK 0xFFFFFFFCL |
23356 | //TRAP7_ADDRESS_HI_MASK |
23357 | #define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask__SHIFT 0x0 |
23358 | #define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask_MASK 0xFFFFFFFFL |
23359 | //TRAP7_COMMAND_MASK |
23360 | #define TRAP7_COMMAND_MASK__Trap7Cmd0Mask__SHIFT 0x0 |
23361 | #define TRAP7_COMMAND_MASK__Trap7Cmd1Mask__SHIFT 0x8 |
23362 | #define TRAP7_COMMAND_MASK__Trap7Cmd0Mask_MASK 0x0000003FL |
23363 | #define TRAP7_COMMAND_MASK__Trap7Cmd1Mask_MASK 0x00003F00L |
23364 | //TRAP8_CONTROL0 |
23365 | #define TRAP8_CONTROL0__Trap8En__SHIFT 0x0 |
23366 | #define TRAP8_CONTROL0__Trap8SMUIntr__SHIFT 0x3 |
23367 | #define TRAP8_CONTROL0__Trap8CrossTrigger__SHIFT 0x18 |
23368 | #define TRAP8_CONTROL0__Trap8En_MASK 0x00000001L |
23369 | #define TRAP8_CONTROL0__Trap8SMUIntr_MASK 0x00000008L |
23370 | #define TRAP8_CONTROL0__Trap8CrossTrigger_MASK 0x0F000000L |
23371 | //TRAP8_ADDRESS_LO |
23372 | #define TRAP8_ADDRESS_LO__Trap8AddrLo__SHIFT 0x2 |
23373 | #define TRAP8_ADDRESS_LO__Trap8AddrLo_MASK 0xFFFFFFFCL |
23374 | //TRAP8_ADDRESS_HI |
23375 | #define TRAP8_ADDRESS_HI__Trap8AddrHi__SHIFT 0x0 |
23376 | #define TRAP8_ADDRESS_HI__Trap8AddrHi_MASK 0xFFFFFFFFL |
23377 | //TRAP8_COMMAND |
23378 | #define TRAP8_COMMAND__Trap8Cmd0__SHIFT 0x0 |
23379 | #define TRAP8_COMMAND__Trap8Cmd1__SHIFT 0x8 |
23380 | #define TRAP8_COMMAND__Trap8Cmd0_MASK 0x0000003FL |
23381 | #define TRAP8_COMMAND__Trap8Cmd1_MASK 0x00003F00L |
23382 | //TRAP8_ADDRESS_LO_MASK |
23383 | #define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask__SHIFT 0x2 |
23384 | #define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask_MASK 0xFFFFFFFCL |
23385 | //TRAP8_ADDRESS_HI_MASK |
23386 | #define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask__SHIFT 0x0 |
23387 | #define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask_MASK 0xFFFFFFFFL |
23388 | //TRAP8_COMMAND_MASK |
23389 | #define TRAP8_COMMAND_MASK__Trap8Cmd0Mask__SHIFT 0x0 |
23390 | #define TRAP8_COMMAND_MASK__Trap8Cmd1Mask__SHIFT 0x8 |
23391 | #define TRAP8_COMMAND_MASK__Trap8Cmd0Mask_MASK 0x0000003FL |
23392 | #define TRAP8_COMMAND_MASK__Trap8Cmd1Mask_MASK 0x00003F00L |
23393 | //TRAP9_CONTROL0 |
23394 | #define TRAP9_CONTROL0__Trap9En__SHIFT 0x0 |
23395 | #define TRAP9_CONTROL0__Trap9SMUIntr__SHIFT 0x3 |
23396 | #define TRAP9_CONTROL0__Trap9CrossTrigger__SHIFT 0x18 |
23397 | #define TRAP9_CONTROL0__Trap9En_MASK 0x00000001L |
23398 | #define TRAP9_CONTROL0__Trap9SMUIntr_MASK 0x00000008L |
23399 | #define TRAP9_CONTROL0__Trap9CrossTrigger_MASK 0x0F000000L |
23400 | //TRAP9_ADDRESS_LO |
23401 | #define TRAP9_ADDRESS_LO__Trap9AddrLo__SHIFT 0x2 |
23402 | #define TRAP9_ADDRESS_LO__Trap9AddrLo_MASK 0xFFFFFFFCL |
23403 | //TRAP9_ADDRESS_HI |
23404 | #define TRAP9_ADDRESS_HI__Trap9AddrHi__SHIFT 0x0 |
23405 | #define TRAP9_ADDRESS_HI__Trap9AddrHi_MASK 0xFFFFFFFFL |
23406 | //TRAP9_COMMAND |
23407 | #define TRAP9_COMMAND__Trap9Cmd0__SHIFT 0x0 |
23408 | #define TRAP9_COMMAND__Trap9Cmd1__SHIFT 0x8 |
23409 | #define TRAP9_COMMAND__Trap9Cmd0_MASK 0x0000003FL |
23410 | #define TRAP9_COMMAND__Trap9Cmd1_MASK 0x00003F00L |
23411 | //TRAP9_ADDRESS_LO_MASK |
23412 | #define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask__SHIFT 0x2 |
23413 | #define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask_MASK 0xFFFFFFFCL |
23414 | //TRAP9_ADDRESS_HI_MASK |
23415 | #define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask__SHIFT 0x0 |
23416 | #define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask_MASK 0xFFFFFFFFL |
23417 | //TRAP9_COMMAND_MASK |
23418 | #define TRAP9_COMMAND_MASK__Trap9Cmd0Mask__SHIFT 0x0 |
23419 | #define TRAP9_COMMAND_MASK__Trap9Cmd1Mask__SHIFT 0x8 |
23420 | #define TRAP9_COMMAND_MASK__Trap9Cmd0Mask_MASK 0x0000003FL |
23421 | #define TRAP9_COMMAND_MASK__Trap9Cmd1Mask_MASK 0x00003F00L |
23422 | //TRAP10_CONTROL0 |
23423 | #define TRAP10_CONTROL0__Trap10En__SHIFT 0x0 |
23424 | #define TRAP10_CONTROL0__Trap10SMUIntr__SHIFT 0x3 |
23425 | #define TRAP10_CONTROL0__Trap10CrossTrigger__SHIFT 0x18 |
23426 | #define TRAP10_CONTROL0__Trap10En_MASK 0x00000001L |
23427 | #define TRAP10_CONTROL0__Trap10SMUIntr_MASK 0x00000008L |
23428 | #define TRAP10_CONTROL0__Trap10CrossTrigger_MASK 0x0F000000L |
23429 | //TRAP10_ADDRESS_LO |
23430 | #define TRAP10_ADDRESS_LO__Trap10AddrLo__SHIFT 0x2 |
23431 | #define TRAP10_ADDRESS_LO__Trap10AddrLo_MASK 0xFFFFFFFCL |
23432 | //TRAP10_ADDRESS_HI |
23433 | #define TRAP10_ADDRESS_HI__Trap10AddrHi__SHIFT 0x0 |
23434 | #define TRAP10_ADDRESS_HI__Trap10AddrHi_MASK 0xFFFFFFFFL |
23435 | //TRAP10_COMMAND |
23436 | #define TRAP10_COMMAND__Trap10Cmd0__SHIFT 0x0 |
23437 | #define TRAP10_COMMAND__Trap10Cmd1__SHIFT 0x8 |
23438 | #define TRAP10_COMMAND__Trap10Cmd0_MASK 0x0000003FL |
23439 | #define TRAP10_COMMAND__Trap10Cmd1_MASK 0x00003F00L |
23440 | //TRAP10_ADDRESS_LO_MASK |
23441 | #define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask__SHIFT 0x2 |
23442 | #define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask_MASK 0xFFFFFFFCL |
23443 | //TRAP10_ADDRESS_HI_MASK |
23444 | #define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask__SHIFT 0x0 |
23445 | #define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask_MASK 0xFFFFFFFFL |
23446 | //TRAP10_COMMAND_MASK |
23447 | #define TRAP10_COMMAND_MASK__Trap10Cmd0Mask__SHIFT 0x0 |
23448 | #define TRAP10_COMMAND_MASK__Trap10Cmd1Mask__SHIFT 0x8 |
23449 | #define TRAP10_COMMAND_MASK__Trap10Cmd0Mask_MASK 0x0000003FL |
23450 | #define TRAP10_COMMAND_MASK__Trap10Cmd1Mask_MASK 0x00003F00L |
23451 | //TRAP11_CONTROL0 |
23452 | #define TRAP11_CONTROL0__Trap11En__SHIFT 0x0 |
23453 | #define TRAP11_CONTROL0__Trap11SMUIntr__SHIFT 0x3 |
23454 | #define TRAP11_CONTROL0__Trap11CrossTrigger__SHIFT 0x18 |
23455 | #define TRAP11_CONTROL0__Trap11En_MASK 0x00000001L |
23456 | #define TRAP11_CONTROL0__Trap11SMUIntr_MASK 0x00000008L |
23457 | #define TRAP11_CONTROL0__Trap11CrossTrigger_MASK 0x0F000000L |
23458 | //TRAP11_ADDRESS_LO |
23459 | #define TRAP11_ADDRESS_LO__Trap11AddrLo__SHIFT 0x2 |
23460 | #define TRAP11_ADDRESS_LO__Trap11AddrLo_MASK 0xFFFFFFFCL |
23461 | //TRAP11_ADDRESS_HI |
23462 | #define TRAP11_ADDRESS_HI__Trap11AddrHi__SHIFT 0x0 |
23463 | #define TRAP11_ADDRESS_HI__Trap11AddrHi_MASK 0xFFFFFFFFL |
23464 | //TRAP11_COMMAND |
23465 | #define TRAP11_COMMAND__Trap11Cmd0__SHIFT 0x0 |
23466 | #define TRAP11_COMMAND__Trap11Cmd1__SHIFT 0x8 |
23467 | #define TRAP11_COMMAND__Trap11Cmd0_MASK 0x0000003FL |
23468 | #define TRAP11_COMMAND__Trap11Cmd1_MASK 0x00003F00L |
23469 | //TRAP11_ADDRESS_LO_MASK |
23470 | #define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask__SHIFT 0x2 |
23471 | #define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask_MASK 0xFFFFFFFCL |
23472 | //TRAP11_ADDRESS_HI_MASK |
23473 | #define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask__SHIFT 0x0 |
23474 | #define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask_MASK 0xFFFFFFFFL |
23475 | //TRAP11_COMMAND_MASK |
23476 | #define TRAP11_COMMAND_MASK__Trap11Cmd0Mask__SHIFT 0x0 |
23477 | #define TRAP11_COMMAND_MASK__Trap11Cmd1Mask__SHIFT 0x8 |
23478 | #define TRAP11_COMMAND_MASK__Trap11Cmd0Mask_MASK 0x0000003FL |
23479 | #define TRAP11_COMMAND_MASK__Trap11Cmd1Mask_MASK 0x00003F00L |
23480 | //TRAP12_CONTROL0 |
23481 | #define TRAP12_CONTROL0__Trap12En__SHIFT 0x0 |
23482 | #define TRAP12_CONTROL0__Trap12SMUIntr__SHIFT 0x3 |
23483 | #define TRAP12_CONTROL0__Trap12CrossTrigger__SHIFT 0x18 |
23484 | #define TRAP12_CONTROL0__Trap12En_MASK 0x00000001L |
23485 | #define TRAP12_CONTROL0__Trap12SMUIntr_MASK 0x00000008L |
23486 | #define TRAP12_CONTROL0__Trap12CrossTrigger_MASK 0x0F000000L |
23487 | //TRAP12_ADDRESS_LO |
23488 | #define TRAP12_ADDRESS_LO__Trap12AddrLo__SHIFT 0x2 |
23489 | #define TRAP12_ADDRESS_LO__Trap12AddrLo_MASK 0xFFFFFFFCL |
23490 | //TRAP12_ADDRESS_HI |
23491 | #define TRAP12_ADDRESS_HI__Trap12AddrHi__SHIFT 0x0 |
23492 | #define TRAP12_ADDRESS_HI__Trap12AddrHi_MASK 0xFFFFFFFFL |
23493 | //TRAP12_COMMAND |
23494 | #define TRAP12_COMMAND__Trap12Cmd0__SHIFT 0x0 |
23495 | #define TRAP12_COMMAND__Trap12Cmd1__SHIFT 0x8 |
23496 | #define TRAP12_COMMAND__Trap12Cmd0_MASK 0x0000003FL |
23497 | #define TRAP12_COMMAND__Trap12Cmd1_MASK 0x00003F00L |
23498 | //TRAP12_ADDRESS_LO_MASK |
23499 | #define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask__SHIFT 0x2 |
23500 | #define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask_MASK 0xFFFFFFFCL |
23501 | //TRAP12_ADDRESS_HI_MASK |
23502 | #define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask__SHIFT 0x0 |
23503 | #define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask_MASK 0xFFFFFFFFL |
23504 | //TRAP12_COMMAND_MASK |
23505 | #define TRAP12_COMMAND_MASK__Trap12Cmd0Mask__SHIFT 0x0 |
23506 | #define TRAP12_COMMAND_MASK__Trap12Cmd1Mask__SHIFT 0x8 |
23507 | #define TRAP12_COMMAND_MASK__Trap12Cmd0Mask_MASK 0x0000003FL |
23508 | #define TRAP12_COMMAND_MASK__Trap12Cmd1Mask_MASK 0x00003F00L |
23509 | //TRAP13_CONTROL0 |
23510 | #define TRAP13_CONTROL0__Trap13En__SHIFT 0x0 |
23511 | #define TRAP13_CONTROL0__Trap13SMUIntr__SHIFT 0x3 |
23512 | #define TRAP13_CONTROL0__Trap13CrossTrigger__SHIFT 0x18 |
23513 | #define TRAP13_CONTROL0__Trap13En_MASK 0x00000001L |
23514 | #define TRAP13_CONTROL0__Trap13SMUIntr_MASK 0x00000008L |
23515 | #define TRAP13_CONTROL0__Trap13CrossTrigger_MASK 0x0F000000L |
23516 | //TRAP13_ADDRESS_LO |
23517 | #define TRAP13_ADDRESS_LO__Trap13AddrLo__SHIFT 0x2 |
23518 | #define TRAP13_ADDRESS_LO__Trap13AddrLo_MASK 0xFFFFFFFCL |
23519 | //TRAP13_ADDRESS_HI |
23520 | #define TRAP13_ADDRESS_HI__Trap13AddrHi__SHIFT 0x0 |
23521 | #define TRAP13_ADDRESS_HI__Trap13AddrHi_MASK 0xFFFFFFFFL |
23522 | //TRAP13_COMMAND |
23523 | #define TRAP13_COMMAND__Trap13Cmd0__SHIFT 0x0 |
23524 | #define TRAP13_COMMAND__Trap13Cmd1__SHIFT 0x8 |
23525 | #define TRAP13_COMMAND__Trap13Cmd0_MASK 0x0000003FL |
23526 | #define TRAP13_COMMAND__Trap13Cmd1_MASK 0x00003F00L |
23527 | //TRAP13_ADDRESS_LO_MASK |
23528 | #define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask__SHIFT 0x2 |
23529 | #define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask_MASK 0xFFFFFFFCL |
23530 | //TRAP13_ADDRESS_HI_MASK |
23531 | #define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask__SHIFT 0x0 |
23532 | #define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask_MASK 0xFFFFFFFFL |
23533 | //TRAP13_COMMAND_MASK |
23534 | #define TRAP13_COMMAND_MASK__Trap13Cmd0Mask__SHIFT 0x0 |
23535 | #define TRAP13_COMMAND_MASK__Trap13Cmd1Mask__SHIFT 0x8 |
23536 | #define TRAP13_COMMAND_MASK__Trap13Cmd0Mask_MASK 0x0000003FL |
23537 | #define TRAP13_COMMAND_MASK__Trap13Cmd1Mask_MASK 0x00003F00L |
23538 | //TRAP14_CONTROL0 |
23539 | #define TRAP14_CONTROL0__Trap14En__SHIFT 0x0 |
23540 | #define TRAP14_CONTROL0__Trap14SMUIntr__SHIFT 0x3 |
23541 | #define TRAP14_CONTROL0__Trap14CrossTrigger__SHIFT 0x18 |
23542 | #define TRAP14_CONTROL0__Trap14En_MASK 0x00000001L |
23543 | #define TRAP14_CONTROL0__Trap14SMUIntr_MASK 0x00000008L |
23544 | #define TRAP14_CONTROL0__Trap14CrossTrigger_MASK 0x0F000000L |
23545 | //TRAP14_ADDRESS_LO |
23546 | #define TRAP14_ADDRESS_LO__Trap14AddrLo__SHIFT 0x2 |
23547 | #define TRAP14_ADDRESS_LO__Trap14AddrLo_MASK 0xFFFFFFFCL |
23548 | //TRAP14_ADDRESS_HI |
23549 | #define TRAP14_ADDRESS_HI__Trap14AddrHi__SHIFT 0x0 |
23550 | #define TRAP14_ADDRESS_HI__Trap14AddrHi_MASK 0xFFFFFFFFL |
23551 | //TRAP14_COMMAND |
23552 | #define TRAP14_COMMAND__Trap14Cmd0__SHIFT 0x0 |
23553 | #define TRAP14_COMMAND__Trap14Cmd1__SHIFT 0x8 |
23554 | #define TRAP14_COMMAND__Trap14Cmd0_MASK 0x0000003FL |
23555 | #define TRAP14_COMMAND__Trap14Cmd1_MASK 0x00003F00L |
23556 | //TRAP14_ADDRESS_LO_MASK |
23557 | #define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask__SHIFT 0x2 |
23558 | #define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask_MASK 0xFFFFFFFCL |
23559 | //TRAP14_ADDRESS_HI_MASK |
23560 | #define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask__SHIFT 0x0 |
23561 | #define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask_MASK 0xFFFFFFFFL |
23562 | //TRAP14_COMMAND_MASK |
23563 | #define TRAP14_COMMAND_MASK__Trap14Cmd0Mask__SHIFT 0x0 |
23564 | #define TRAP14_COMMAND_MASK__Trap14Cmd1Mask__SHIFT 0x8 |
23565 | #define TRAP14_COMMAND_MASK__Trap14Cmd0Mask_MASK 0x0000003FL |
23566 | #define TRAP14_COMMAND_MASK__Trap14Cmd1Mask_MASK 0x00003F00L |
23567 | //TRAP15_CONTROL0 |
23568 | #define TRAP15_CONTROL0__Trap15En__SHIFT 0x0 |
23569 | #define TRAP15_CONTROL0__Trap15SMUIntr__SHIFT 0x3 |
23570 | #define TRAP15_CONTROL0__Trap15CrossTrigger__SHIFT 0x18 |
23571 | #define TRAP15_CONTROL0__Trap15En_MASK 0x00000001L |
23572 | #define TRAP15_CONTROL0__Trap15SMUIntr_MASK 0x00000008L |
23573 | #define TRAP15_CONTROL0__Trap15CrossTrigger_MASK 0x0F000000L |
23574 | //TRAP15_ADDRESS_LO |
23575 | #define TRAP15_ADDRESS_LO__Trap15AddrLo__SHIFT 0x2 |
23576 | #define TRAP15_ADDRESS_LO__Trap15AddrLo_MASK 0xFFFFFFFCL |
23577 | //TRAP15_ADDRESS_HI |
23578 | #define TRAP15_ADDRESS_HI__Trap15AddrHi__SHIFT 0x0 |
23579 | #define TRAP15_ADDRESS_HI__Trap15AddrHi_MASK 0xFFFFFFFFL |
23580 | //TRAP15_COMMAND |
23581 | #define TRAP15_COMMAND__Trap15Cmd0__SHIFT 0x0 |
23582 | #define TRAP15_COMMAND__Trap15Cmd1__SHIFT 0x8 |
23583 | #define TRAP15_COMMAND__Trap15Cmd0_MASK 0x0000003FL |
23584 | #define TRAP15_COMMAND__Trap15Cmd1_MASK 0x00003F00L |
23585 | //TRAP15_ADDRESS_LO_MASK |
23586 | #define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask__SHIFT 0x2 |
23587 | #define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask_MASK 0xFFFFFFFCL |
23588 | //TRAP15_ADDRESS_HI_MASK |
23589 | #define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask__SHIFT 0x0 |
23590 | #define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask_MASK 0xFFFFFFFFL |
23591 | //TRAP15_COMMAND_MASK |
23592 | #define TRAP15_COMMAND_MASK__Trap15Cmd0Mask__SHIFT 0x0 |
23593 | #define TRAP15_COMMAND_MASK__Trap15Cmd1Mask__SHIFT 0x8 |
23594 | #define TRAP15_COMMAND_MASK__Trap15Cmd0Mask_MASK 0x0000003FL |
23595 | #define TRAP15_COMMAND_MASK__Trap15Cmd1Mask_MASK 0x00003F00L |
23596 | //SB_COMMAND |
23597 | #define SB_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
23598 | #define SB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
23599 | #define SB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
23600 | #define SB_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
23601 | #define SB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
23602 | #define SB_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
23603 | //SB_SUB_BUS_NUMBER_LATENCY |
23604 | #define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
23605 | #define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
23606 | #define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
23607 | #define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
23608 | //SB_IO_BASE_LIMIT |
23609 | #define SB_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
23610 | #define SB_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
23611 | #define SB_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
23612 | #define SB_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
23613 | //SB_MEM_BASE_LIMIT |
23614 | #define SB_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
23615 | #define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
23616 | #define SB_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
23617 | #define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
23618 | //SB_PREF_BASE_LIMIT |
23619 | #define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
23620 | #define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
23621 | #define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
23622 | #define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
23623 | //SB_PREF_BASE_UPPER |
23624 | #define SB_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
23625 | #define SB_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
23626 | //SB_PREF_LIMIT_UPPER |
23627 | #define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
23628 | #define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
23629 | //SB_IO_BASE_LIMIT_HI |
23630 | #define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
23631 | #define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
23632 | #define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
23633 | #define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
23634 | //SB_IRQ_BRIDGE_CNTL |
23635 | #define SB_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
23636 | #define SB_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
23637 | #define SB_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
23638 | #define SB_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
23639 | #define SB_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
23640 | #define SB_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
23641 | //SB_EXT_BRIDGE_CNTL |
23642 | #define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
23643 | #define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
23644 | //SB_PMI_STATUS_CNTL |
23645 | #define SB_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
23646 | #define SB_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L |
23647 | //SB_SLOT_CAP |
23648 | #define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
23649 | #define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
23650 | #define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
23651 | #define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
23652 | //SB_ROOT_CNTL |
23653 | #define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
23654 | #define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
23655 | //SB_DEVICE_CNTL2 |
23656 | #define SB_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
23657 | #define SB_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
23658 | //USB_QoS_CNTL |
23659 | #define USB_QoS_CNTL__UnitID0__SHIFT 0x0 |
23660 | #define USB_QoS_CNTL__UnitID0QoSPriority__SHIFT 0x8 |
23661 | #define USB_QoS_CNTL__UnitID0Enable__SHIFT 0xc |
23662 | #define USB_QoS_CNTL__UnitID1__SHIFT 0x10 |
23663 | #define USB_QoS_CNTL__UnitID1QoSPriority__SHIFT 0x18 |
23664 | #define USB_QoS_CNTL__UnitID1Enable__SHIFT 0x1c |
23665 | #define USB_QoS_CNTL__UnitID0_MASK 0x0000007FL |
23666 | #define USB_QoS_CNTL__UnitID0QoSPriority_MASK 0x00000F00L |
23667 | #define USB_QoS_CNTL__UnitID0Enable_MASK 0x00001000L |
23668 | #define USB_QoS_CNTL__UnitID1_MASK 0x007F0000L |
23669 | #define USB_QoS_CNTL__UnitID1QoSPriority_MASK 0x0F000000L |
23670 | #define USB_QoS_CNTL__UnitID1Enable_MASK 0x10000000L |
23671 | //MCA_SMN_INT_REQ_ADDR |
23672 | #define MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR__SHIFT 0x0 |
23673 | #define MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR_MASK 0x000FFFFFL |
23674 | //MCA_SMN_INT_MCM_ADDR |
23675 | #define MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR__SHIFT 0x0 |
23676 | #define MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR_MASK 0x0000000FL |
23677 | //MCA_SMN_INT_APERTUREID |
23678 | #define MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID__SHIFT 0x0 |
23679 | #define MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID_MASK 0x00000FFFL |
23680 | //MCA_SMN_INT_CONTROL |
23681 | #define MCA_SMN_INT_CONTROL__MCACrossTrigger__SHIFT 0x0 |
23682 | #define MCA_SMN_INT_CONTROL__MCACrossTrigger_MASK 0x0000000FL |
23683 | |
23684 | |
23685 | // addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec |
23686 | //PARITY_CONTROL_0 |
23687 | #define PARITY_CONTROL_0__ParityCorrThreshold__SHIFT 0x0 |
23688 | #define PARITY_CONTROL_0__ParityUCPThreshold__SHIFT 0x10 |
23689 | #define PARITY_CONTROL_0__ParityCorrThreshold_MASK 0x0000FFFFL |
23690 | #define PARITY_CONTROL_0__ParityUCPThreshold_MASK 0xFFFF0000L |
23691 | //PARITY_CONTROL_1 |
23692 | #define PARITY_CONTROL_1__ParityErrGenGroupSel__SHIFT 0x0 |
23693 | #define PARITY_CONTROL_1__ParityErrGenGroupTypeSel__SHIFT 0x8 |
23694 | #define PARITY_CONTROL_1__ParityErrGenIdSel__SHIFT 0xb |
23695 | #define PARITY_CONTROL_1__ParityErrGenCmd__SHIFT 0x10 |
23696 | #define PARITY_CONTROL_1__ParityErrGenTrigger__SHIFT 0x1e |
23697 | #define PARITY_CONTROL_1__ParityErrGenInjectAllow__SHIFT 0x1f |
23698 | #define PARITY_CONTROL_1__ParityErrGenGroupSel_MASK 0x000000FFL |
23699 | #define PARITY_CONTROL_1__ParityErrGenGroupTypeSel_MASK 0x00000100L |
23700 | #define PARITY_CONTROL_1__ParityErrGenIdSel_MASK 0x0000F800L |
23701 | #define PARITY_CONTROL_1__ParityErrGenCmd_MASK 0x000F0000L |
23702 | #define PARITY_CONTROL_1__ParityErrGenTrigger_MASK 0x40000000L |
23703 | #define PARITY_CONTROL_1__ParityErrGenInjectAllow_MASK 0x80000000L |
23704 | //PARITY_SEVERITY_CONTROL_UNCORR_0 |
23705 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0__SHIFT 0x0 |
23706 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1__SHIFT 0x2 |
23707 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2__SHIFT 0x4 |
23708 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3__SHIFT 0x6 |
23709 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4__SHIFT 0x8 |
23710 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5__SHIFT 0xa |
23711 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6__SHIFT 0xc |
23712 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7__SHIFT 0xe |
23713 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp8__SHIFT 0x10 |
23714 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0_MASK 0x00000003L |
23715 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1_MASK 0x0000000CL |
23716 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2_MASK 0x00000030L |
23717 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3_MASK 0x000000C0L |
23718 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4_MASK 0x00000300L |
23719 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5_MASK 0x00000C00L |
23720 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6_MASK 0x00003000L |
23721 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7_MASK 0x0000C000L |
23722 | #define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp8_MASK 0x00030000L |
23723 | //PARITY_SEVERITY_CONTROL_CORR_0 |
23724 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0__SHIFT 0x0 |
23725 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1__SHIFT 0x2 |
23726 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2__SHIFT 0x4 |
23727 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3__SHIFT 0x6 |
23728 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4__SHIFT 0x8 |
23729 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5__SHIFT 0xa |
23730 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6__SHIFT 0xc |
23731 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7__SHIFT 0xe |
23732 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp8__SHIFT 0x10 |
23733 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0_MASK 0x00000003L |
23734 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1_MASK 0x0000000CL |
23735 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2_MASK 0x00000030L |
23736 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3_MASK 0x000000C0L |
23737 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4_MASK 0x00000300L |
23738 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5_MASK 0x00000C00L |
23739 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6_MASK 0x00003000L |
23740 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7_MASK 0x0000C000L |
23741 | #define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp8_MASK 0x00030000L |
23742 | //PARITY_SEVERITY_CONTROL_UCP_0 |
23743 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0__SHIFT 0x0 |
23744 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1__SHIFT 0x2 |
23745 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2__SHIFT 0x4 |
23746 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3__SHIFT 0x6 |
23747 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4__SHIFT 0x8 |
23748 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5__SHIFT 0xa |
23749 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6__SHIFT 0xc |
23750 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7__SHIFT 0xe |
23751 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp8__SHIFT 0x10 |
23752 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0_MASK 0x00000003L |
23753 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1_MASK 0x0000000CL |
23754 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2_MASK 0x00000030L |
23755 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3_MASK 0x000000C0L |
23756 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4_MASK 0x00000300L |
23757 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5_MASK 0x00000C00L |
23758 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6_MASK 0x00003000L |
23759 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7_MASK 0x0000C000L |
23760 | #define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp8_MASK 0x00030000L |
23761 | //MISC_SEVERITY_CONTROL |
23762 | #define MISC_SEVERITY_CONTROL__ErrEventErrSev__SHIFT 0x4 |
23763 | #define MISC_SEVERITY_CONTROL__PcieParityErrSev__SHIFT 0x6 |
23764 | #define MISC_SEVERITY_CONTROL__ErrEventErrSev_MASK 0x00000030L |
23765 | #define MISC_SEVERITY_CONTROL__PcieParityErrSev_MASK 0x000000C0L |
23766 | //MISC_RAS_CONTROL |
23767 | #define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En__SHIFT 0x2 |
23768 | #define MISC_RAS_CONTROL__GNB_SB_LinkNeverDis__SHIFT 0x3 |
23769 | #define MISC_RAS_CONTROL__InterruptOutputDis__SHIFT 0x9 |
23770 | #define MISC_RAS_CONTROL__LinkDisOutputDis__SHIFT 0xa |
23771 | #define MISC_RAS_CONTROL__SyncFldOutputDis__SHIFT 0xb |
23772 | #define MISC_RAS_CONTROL__PCIe_NMI_En__SHIFT 0xc |
23773 | #define MISC_RAS_CONTROL__PCIe_SCI_En__SHIFT 0xd |
23774 | #define MISC_RAS_CONTROL__PCIe_SMI_En__SHIFT 0xe |
23775 | #define MISC_RAS_CONTROL__SW_SCI_En__SHIFT 0xf |
23776 | #define MISC_RAS_CONTROL__SW_SMI_En__SHIFT 0x10 |
23777 | #define MISC_RAS_CONTROL__SW_NMI_En__SHIFT 0x11 |
23778 | #define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En_MASK 0x00000004L |
23779 | #define MISC_RAS_CONTROL__GNB_SB_LinkNeverDis_MASK 0x00000008L |
23780 | #define MISC_RAS_CONTROL__InterruptOutputDis_MASK 0x00000200L |
23781 | #define MISC_RAS_CONTROL__LinkDisOutputDis_MASK 0x00000400L |
23782 | #define MISC_RAS_CONTROL__SyncFldOutputDis_MASK 0x00000800L |
23783 | #define MISC_RAS_CONTROL__PCIe_NMI_En_MASK 0x00001000L |
23784 | #define MISC_RAS_CONTROL__PCIe_SCI_En_MASK 0x00002000L |
23785 | #define MISC_RAS_CONTROL__PCIe_SMI_En_MASK 0x00004000L |
23786 | #define MISC_RAS_CONTROL__SW_SCI_En_MASK 0x00008000L |
23787 | #define MISC_RAS_CONTROL__SW_SMI_En_MASK 0x00010000L |
23788 | #define MISC_RAS_CONTROL__SW_NMI_En_MASK 0x00020000L |
23789 | //RAS_SCRATCH_0 |
23790 | #define RAS_SCRATCH_0__SCRATCH_0__SHIFT 0x0 |
23791 | #define RAS_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL |
23792 | //RAS_SCRATCH_1 |
23793 | #define RAS_SCRATCH_1__SCRATCH_1__SHIFT 0x0 |
23794 | #define RAS_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL |
23795 | //SYNCFLOOD_STATUS |
23796 | #define SYNCFLOOD_STATUS__SyncfloodFromRASCntl__SHIFT 0x0 |
23797 | #define SYNCFLOOD_STATUS__SyncfloodFromAPML__SHIFT 0x1 |
23798 | #define SYNCFLOOD_STATUS__SyncfloodFromPin__SHIFT 0x2 |
23799 | #define SYNCFLOOD_STATUS__SyncfloodFromPrivate__SHIFT 0x4 |
23800 | #define SYNCFLOOD_STATUS__SyncfloodFromMCA__SHIFT 0x5 |
23801 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_8__SHIFT 0x8 |
23802 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_9__SHIFT 0x9 |
23803 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_10__SHIFT 0xa |
23804 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_11__SHIFT 0xb |
23805 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_12__SHIFT 0xc |
23806 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_13__SHIFT 0xd |
23807 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_14__SHIFT 0xe |
23808 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_15__SHIFT 0xf |
23809 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_16__SHIFT 0x10 |
23810 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_17__SHIFT 0x11 |
23811 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_18__SHIFT 0x12 |
23812 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_19__SHIFT 0x13 |
23813 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_20__SHIFT 0x14 |
23814 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_21__SHIFT 0x15 |
23815 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_22__SHIFT 0x16 |
23816 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_23__SHIFT 0x17 |
23817 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_24__SHIFT 0x18 |
23818 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_25__SHIFT 0x19 |
23819 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_26__SHIFT 0x1a |
23820 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_27__SHIFT 0x1b |
23821 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_28__SHIFT 0x1c |
23822 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_29__SHIFT 0x1d |
23823 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_30__SHIFT 0x1e |
23824 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_31__SHIFT 0x1f |
23825 | #define SYNCFLOOD_STATUS__SyncfloodFromRASCntl_MASK 0x00000001L |
23826 | #define SYNCFLOOD_STATUS__SyncfloodFromAPML_MASK 0x00000002L |
23827 | #define SYNCFLOOD_STATUS__SyncfloodFromPin_MASK 0x00000004L |
23828 | #define SYNCFLOOD_STATUS__SyncfloodFromPrivate_MASK 0x00000010L |
23829 | #define SYNCFLOOD_STATUS__SyncfloodFromMCA_MASK 0x00000020L |
23830 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_8_MASK 0x00000100L |
23831 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_9_MASK 0x00000200L |
23832 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_10_MASK 0x00000400L |
23833 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_11_MASK 0x00000800L |
23834 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_12_MASK 0x00001000L |
23835 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_13_MASK 0x00002000L |
23836 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_14_MASK 0x00004000L |
23837 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_15_MASK 0x00008000L |
23838 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_16_MASK 0x00010000L |
23839 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_17_MASK 0x00020000L |
23840 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_18_MASK 0x00040000L |
23841 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_19_MASK 0x00080000L |
23842 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_20_MASK 0x00100000L |
23843 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_21_MASK 0x00200000L |
23844 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_22_MASK 0x00400000L |
23845 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_23_MASK 0x00800000L |
23846 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_24_MASK 0x01000000L |
23847 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_25_MASK 0x02000000L |
23848 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_26_MASK 0x04000000L |
23849 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_27_MASK 0x08000000L |
23850 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_28_MASK 0x10000000L |
23851 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_29_MASK 0x20000000L |
23852 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_30_MASK 0x40000000L |
23853 | #define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_31_MASK 0x80000000L |
23854 | //NMI_STATUS |
23855 | #define NMI_STATUS__NMIFromPin__SHIFT 0x0 |
23856 | #define NMI_STATUS__NMIFromPin_MASK 0x00000001L |
23857 | //INTERNAL_POISON_STATUS |
23858 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_0__SHIFT 0x0 |
23859 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_1__SHIFT 0x1 |
23860 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_2__SHIFT 0x2 |
23861 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_3__SHIFT 0x3 |
23862 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_4__SHIFT 0x4 |
23863 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_5__SHIFT 0x5 |
23864 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_6__SHIFT 0x6 |
23865 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_7__SHIFT 0x7 |
23866 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_0_MASK 0x00000001L |
23867 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_1_MASK 0x00000002L |
23868 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_2_MASK 0x00000004L |
23869 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_3_MASK 0x00000008L |
23870 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_4_MASK 0x00000010L |
23871 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_5_MASK 0x00000020L |
23872 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_6_MASK 0x00000040L |
23873 | #define INTERNAL_POISON_STATUS__IntPoisonStatus_7_MASK 0x00000080L |
23874 | //INTERNAL_POISON_MASK |
23875 | #define INTERNAL_POISON_MASK__IntPoisonMask__SHIFT 0x0 |
23876 | #define INTERNAL_POISON_MASK__IntPoisonMask_MASK 0x000000FFL |
23877 | //EGRESS_POISON_STATUS_LO |
23878 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0__SHIFT 0x0 |
23879 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1__SHIFT 0x1 |
23880 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2__SHIFT 0x2 |
23881 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3__SHIFT 0x3 |
23882 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4__SHIFT 0x4 |
23883 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5__SHIFT 0x5 |
23884 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6__SHIFT 0x6 |
23885 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7__SHIFT 0x7 |
23886 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8__SHIFT 0x8 |
23887 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9__SHIFT 0x9 |
23888 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10__SHIFT 0xa |
23889 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11__SHIFT 0xb |
23890 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12__SHIFT 0xc |
23891 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13__SHIFT 0xd |
23892 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14__SHIFT 0xe |
23893 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15__SHIFT 0xf |
23894 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16__SHIFT 0x10 |
23895 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17__SHIFT 0x11 |
23896 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18__SHIFT 0x12 |
23897 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19__SHIFT 0x13 |
23898 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20__SHIFT 0x14 |
23899 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21__SHIFT 0x15 |
23900 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22__SHIFT 0x16 |
23901 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23__SHIFT 0x17 |
23902 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24__SHIFT 0x18 |
23903 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25__SHIFT 0x19 |
23904 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26__SHIFT 0x1a |
23905 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27__SHIFT 0x1b |
23906 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28__SHIFT 0x1c |
23907 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29__SHIFT 0x1d |
23908 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30__SHIFT 0x1e |
23909 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31__SHIFT 0x1f |
23910 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0_MASK 0x00000001L |
23911 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1_MASK 0x00000002L |
23912 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2_MASK 0x00000004L |
23913 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3_MASK 0x00000008L |
23914 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4_MASK 0x00000010L |
23915 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5_MASK 0x00000020L |
23916 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6_MASK 0x00000040L |
23917 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7_MASK 0x00000080L |
23918 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8_MASK 0x00000100L |
23919 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9_MASK 0x00000200L |
23920 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10_MASK 0x00000400L |
23921 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11_MASK 0x00000800L |
23922 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12_MASK 0x00001000L |
23923 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13_MASK 0x00002000L |
23924 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14_MASK 0x00004000L |
23925 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15_MASK 0x00008000L |
23926 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16_MASK 0x00010000L |
23927 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17_MASK 0x00020000L |
23928 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18_MASK 0x00040000L |
23929 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19_MASK 0x00080000L |
23930 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20_MASK 0x00100000L |
23931 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21_MASK 0x00200000L |
23932 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22_MASK 0x00400000L |
23933 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23_MASK 0x00800000L |
23934 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24_MASK 0x01000000L |
23935 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25_MASK 0x02000000L |
23936 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26_MASK 0x04000000L |
23937 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27_MASK 0x08000000L |
23938 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28_MASK 0x10000000L |
23939 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29_MASK 0x20000000L |
23940 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30_MASK 0x40000000L |
23941 | #define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31_MASK 0x80000000L |
23942 | //EGRESS_POISON_STATUS_HI |
23943 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0__SHIFT 0x0 |
23944 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1__SHIFT 0x1 |
23945 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2__SHIFT 0x2 |
23946 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3__SHIFT 0x3 |
23947 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4__SHIFT 0x4 |
23948 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5__SHIFT 0x5 |
23949 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6__SHIFT 0x6 |
23950 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7__SHIFT 0x7 |
23951 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8__SHIFT 0x8 |
23952 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9__SHIFT 0x9 |
23953 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10__SHIFT 0xa |
23954 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11__SHIFT 0xb |
23955 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12__SHIFT 0xc |
23956 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13__SHIFT 0xd |
23957 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14__SHIFT 0xe |
23958 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15__SHIFT 0xf |
23959 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16__SHIFT 0x10 |
23960 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17__SHIFT 0x11 |
23961 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18__SHIFT 0x12 |
23962 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19__SHIFT 0x13 |
23963 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20__SHIFT 0x14 |
23964 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21__SHIFT 0x15 |
23965 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22__SHIFT 0x16 |
23966 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23__SHIFT 0x17 |
23967 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24__SHIFT 0x18 |
23968 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25__SHIFT 0x19 |
23969 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26__SHIFT 0x1a |
23970 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27__SHIFT 0x1b |
23971 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28__SHIFT 0x1c |
23972 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29__SHIFT 0x1d |
23973 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30__SHIFT 0x1e |
23974 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31__SHIFT 0x1f |
23975 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0_MASK 0x00000001L |
23976 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1_MASK 0x00000002L |
23977 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2_MASK 0x00000004L |
23978 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3_MASK 0x00000008L |
23979 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4_MASK 0x00000010L |
23980 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5_MASK 0x00000020L |
23981 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6_MASK 0x00000040L |
23982 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7_MASK 0x00000080L |
23983 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8_MASK 0x00000100L |
23984 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9_MASK 0x00000200L |
23985 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10_MASK 0x00000400L |
23986 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11_MASK 0x00000800L |
23987 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12_MASK 0x00001000L |
23988 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13_MASK 0x00002000L |
23989 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14_MASK 0x00004000L |
23990 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15_MASK 0x00008000L |
23991 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16_MASK 0x00010000L |
23992 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17_MASK 0x00020000L |
23993 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18_MASK 0x00040000L |
23994 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19_MASK 0x00080000L |
23995 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20_MASK 0x00100000L |
23996 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21_MASK 0x00200000L |
23997 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22_MASK 0x00400000L |
23998 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23_MASK 0x00800000L |
23999 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24_MASK 0x01000000L |
24000 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25_MASK 0x02000000L |
24001 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26_MASK 0x04000000L |
24002 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27_MASK 0x08000000L |
24003 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28_MASK 0x10000000L |
24004 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29_MASK 0x20000000L |
24005 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30_MASK 0x40000000L |
24006 | #define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31_MASK 0x80000000L |
24007 | //EGRESS_POISON_MASK_LO |
24008 | #define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo__SHIFT 0x0 |
24009 | #define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo_MASK 0xFFFFFFFFL |
24010 | //EGRESS_POISON_MASK_HI |
24011 | #define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi__SHIFT 0x0 |
24012 | #define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi_MASK 0xFFFFFFFFL |
24013 | //EGRESS_POISON_SEVERITY_DOWN |
24014 | #define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown__SHIFT 0x0 |
24015 | #define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown_MASK 0xFFFFFFFFL |
24016 | //EGRESS_POISON_SEVERITY_UPPER |
24017 | #define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper__SHIFT 0x0 |
24018 | #define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper_MASK 0xFFFFFFFFL |
24019 | //APML_STATUS |
24020 | #define APML_STATUS__APML_Corr__SHIFT 0x0 |
24021 | #define APML_STATUS__APML_NonFatal__SHIFT 0x1 |
24022 | #define APML_STATUS__APML_Fatal__SHIFT 0x2 |
24023 | #define APML_STATUS__APML_Serr__SHIFT 0x3 |
24024 | #define APML_STATUS__APML_IntPoisonErr__SHIFT 0x4 |
24025 | #define APML_STATUS__APML_EgressPoisonErrLo__SHIFT 0x5 |
24026 | #define APML_STATUS__APML_EgressPoisonErrHi__SHIFT 0x6 |
24027 | #define APML_STATUS__APML_Corr_MASK 0x00000001L |
24028 | #define APML_STATUS__APML_NonFatal_MASK 0x00000002L |
24029 | #define APML_STATUS__APML_Fatal_MASK 0x00000004L |
24030 | #define APML_STATUS__APML_Serr_MASK 0x00000008L |
24031 | #define APML_STATUS__APML_IntPoisonErr_MASK 0x00000010L |
24032 | #define APML_STATUS__APML_EgressPoisonErrLo_MASK 0x00000020L |
24033 | #define APML_STATUS__APML_EgressPoisonErrHi_MASK 0x00000040L |
24034 | //APML_CONTROL |
24035 | #define APML_CONTROL__APML_NMI_En__SHIFT 0x0 |
24036 | #define APML_CONTROL__APML_SyncFlood_En__SHIFT 0x1 |
24037 | #define APML_CONTROL__APML_OutputDis__SHIFT 0x8 |
24038 | #define APML_CONTROL__APML_NMI_En_MASK 0x00000001L |
24039 | #define APML_CONTROL__APML_SyncFlood_En_MASK 0x00000002L |
24040 | #define APML_CONTROL__APML_OutputDis_MASK 0x00000100L |
24041 | //APML_TRIGGER |
24042 | #define APML_TRIGGER__APML_NMI_TRIGGER__SHIFT 0x0 |
24043 | #define APML_TRIGGER__APML_NMI_TRIGGER_MASK 0x00000001L |
24044 | |
24045 | |
24046 | // addressBlock: nbio_iohub_nb_psprascfg_pspras_cfgdec |
24047 | //PSP_INTERNAL_POISON_STATUS |
24048 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_0__SHIFT 0x0 |
24049 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_1__SHIFT 0x1 |
24050 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_2__SHIFT 0x2 |
24051 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_3__SHIFT 0x3 |
24052 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_4__SHIFT 0x4 |
24053 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_5__SHIFT 0x5 |
24054 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_6__SHIFT 0x6 |
24055 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_7__SHIFT 0x7 |
24056 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_0_MASK 0x00000001L |
24057 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_1_MASK 0x00000002L |
24058 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_2_MASK 0x00000004L |
24059 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_3_MASK 0x00000008L |
24060 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_4_MASK 0x00000010L |
24061 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_5_MASK 0x00000020L |
24062 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_6_MASK 0x00000040L |
24063 | #define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_7_MASK 0x00000080L |
24064 | //PSP_EGRESS_POISON_STATUS_LO |
24065 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_0__SHIFT 0x0 |
24066 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_1__SHIFT 0x1 |
24067 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_2__SHIFT 0x2 |
24068 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_3__SHIFT 0x3 |
24069 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_4__SHIFT 0x4 |
24070 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_5__SHIFT 0x5 |
24071 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_6__SHIFT 0x6 |
24072 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_7__SHIFT 0x7 |
24073 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_8__SHIFT 0x8 |
24074 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_9__SHIFT 0x9 |
24075 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_10__SHIFT 0xa |
24076 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_11__SHIFT 0xb |
24077 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_12__SHIFT 0xc |
24078 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_13__SHIFT 0xd |
24079 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_14__SHIFT 0xe |
24080 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_15__SHIFT 0xf |
24081 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_16__SHIFT 0x10 |
24082 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_17__SHIFT 0x11 |
24083 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_18__SHIFT 0x12 |
24084 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_19__SHIFT 0x13 |
24085 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_20__SHIFT 0x14 |
24086 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_21__SHIFT 0x15 |
24087 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_22__SHIFT 0x16 |
24088 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_23__SHIFT 0x17 |
24089 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_24__SHIFT 0x18 |
24090 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_25__SHIFT 0x19 |
24091 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_26__SHIFT 0x1a |
24092 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_27__SHIFT 0x1b |
24093 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_28__SHIFT 0x1c |
24094 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_29__SHIFT 0x1d |
24095 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_30__SHIFT 0x1e |
24096 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_31__SHIFT 0x1f |
24097 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_0_MASK 0x00000001L |
24098 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_1_MASK 0x00000002L |
24099 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_2_MASK 0x00000004L |
24100 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_3_MASK 0x00000008L |
24101 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_4_MASK 0x00000010L |
24102 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_5_MASK 0x00000020L |
24103 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_6_MASK 0x00000040L |
24104 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_7_MASK 0x00000080L |
24105 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_8_MASK 0x00000100L |
24106 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_9_MASK 0x00000200L |
24107 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_10_MASK 0x00000400L |
24108 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_11_MASK 0x00000800L |
24109 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_12_MASK 0x00001000L |
24110 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_13_MASK 0x00002000L |
24111 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_14_MASK 0x00004000L |
24112 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_15_MASK 0x00008000L |
24113 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_16_MASK 0x00010000L |
24114 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_17_MASK 0x00020000L |
24115 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_18_MASK 0x00040000L |
24116 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_19_MASK 0x00080000L |
24117 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_20_MASK 0x00100000L |
24118 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_21_MASK 0x00200000L |
24119 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_22_MASK 0x00400000L |
24120 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_23_MASK 0x00800000L |
24121 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_24_MASK 0x01000000L |
24122 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_25_MASK 0x02000000L |
24123 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_26_MASK 0x04000000L |
24124 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_27_MASK 0x08000000L |
24125 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_28_MASK 0x10000000L |
24126 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_29_MASK 0x20000000L |
24127 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_30_MASK 0x40000000L |
24128 | #define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_31_MASK 0x80000000L |
24129 | //PSP_EGRESS_POISON_STATUS_HI |
24130 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_0__SHIFT 0x0 |
24131 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_1__SHIFT 0x1 |
24132 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_2__SHIFT 0x2 |
24133 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_3__SHIFT 0x3 |
24134 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_4__SHIFT 0x4 |
24135 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_5__SHIFT 0x5 |
24136 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_6__SHIFT 0x6 |
24137 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_7__SHIFT 0x7 |
24138 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_8__SHIFT 0x8 |
24139 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_9__SHIFT 0x9 |
24140 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_10__SHIFT 0xa |
24141 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_11__SHIFT 0xb |
24142 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_12__SHIFT 0xc |
24143 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_13__SHIFT 0xd |
24144 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_14__SHIFT 0xe |
24145 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_15__SHIFT 0xf |
24146 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_16__SHIFT 0x10 |
24147 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_17__SHIFT 0x11 |
24148 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_18__SHIFT 0x12 |
24149 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_19__SHIFT 0x13 |
24150 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_20__SHIFT 0x14 |
24151 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_21__SHIFT 0x15 |
24152 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_22__SHIFT 0x16 |
24153 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_23__SHIFT 0x17 |
24154 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_24__SHIFT 0x18 |
24155 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_25__SHIFT 0x19 |
24156 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_26__SHIFT 0x1a |
24157 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_27__SHIFT 0x1b |
24158 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_28__SHIFT 0x1c |
24159 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_29__SHIFT 0x1d |
24160 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_30__SHIFT 0x1e |
24161 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_31__SHIFT 0x1f |
24162 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_0_MASK 0x00000001L |
24163 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_1_MASK 0x00000002L |
24164 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_2_MASK 0x00000004L |
24165 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_3_MASK 0x00000008L |
24166 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_4_MASK 0x00000010L |
24167 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_5_MASK 0x00000020L |
24168 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_6_MASK 0x00000040L |
24169 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_7_MASK 0x00000080L |
24170 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_8_MASK 0x00000100L |
24171 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_9_MASK 0x00000200L |
24172 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_10_MASK 0x00000400L |
24173 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_11_MASK 0x00000800L |
24174 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_12_MASK 0x00001000L |
24175 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_13_MASK 0x00002000L |
24176 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_14_MASK 0x00004000L |
24177 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_15_MASK 0x00008000L |
24178 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_16_MASK 0x00010000L |
24179 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_17_MASK 0x00020000L |
24180 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_18_MASK 0x00040000L |
24181 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_19_MASK 0x00080000L |
24182 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_20_MASK 0x00100000L |
24183 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_21_MASK 0x00200000L |
24184 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_22_MASK 0x00400000L |
24185 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_23_MASK 0x00800000L |
24186 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_24_MASK 0x01000000L |
24187 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_25_MASK 0x02000000L |
24188 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_26_MASK 0x04000000L |
24189 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_27_MASK 0x08000000L |
24190 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_28_MASK 0x10000000L |
24191 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_29_MASK 0x20000000L |
24192 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_30_MASK 0x40000000L |
24193 | #define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_31_MASK 0x80000000L |
24194 | |
24195 | |
24196 | // addressBlock: nbio_iohub_nb_intSBdevindcfg0_devind_cfgdecp |
24197 | //NB_INTSBDEVINDCFG0_STEERING_CNTL |
24198 | #define NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0 |
24199 | #define NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8 |
24200 | #define NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L |
24201 | #define NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L |
24202 | //NB_INTSBDEVINDCFG0_SW_LATENCY |
24203 | #define NB_INTSBDEVINDCFG0_SW_LATENCY__SwitchLatency__SHIFT 0x0 |
24204 | #define NB_INTSBDEVINDCFG0_SW_LATENCY__SwitchLatency_MASK 0x000003FFL |
24205 | |
24206 | |
24207 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg0_pciercbdgind_cfgdec |
24208 | //NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX |
24209 | #define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 |
24210 | #define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL |
24211 | //NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA |
24212 | #define NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 |
24213 | #define NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL |
24214 | |
24215 | |
24216 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg1_pciercbdgind_cfgdec |
24217 | //NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX |
24218 | #define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 |
24219 | #define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL |
24220 | //NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA |
24221 | #define NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 |
24222 | #define NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL |
24223 | |
24224 | |
24225 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg2_pciercbdgind_cfgdec |
24226 | //NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX |
24227 | #define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 |
24228 | #define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL |
24229 | //NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA |
24230 | #define NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 |
24231 | #define NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL |
24232 | |
24233 | |
24234 | // addressBlock: nbio_iohub_iommu_l2a_l2acfg |
24235 | //L2_PERF_CNTL_0 |
24236 | #define L2_PERF_CNTL_0__L2PerfEvent0__SHIFT 0x0 |
24237 | #define L2_PERF_CNTL_0__L2PerfEvent1__SHIFT 0x8 |
24238 | #define L2_PERF_CNTL_0__L2PerfCountUpper0__SHIFT 0x10 |
24239 | #define L2_PERF_CNTL_0__L2PerfCountUpper1__SHIFT 0x18 |
24240 | #define L2_PERF_CNTL_0__L2PerfEvent0_MASK 0x000000FFL |
24241 | #define L2_PERF_CNTL_0__L2PerfEvent1_MASK 0x0000FF00L |
24242 | #define L2_PERF_CNTL_0__L2PerfCountUpper0_MASK 0x00FF0000L |
24243 | #define L2_PERF_CNTL_0__L2PerfCountUpper1_MASK 0xFF000000L |
24244 | //L2_PERF_COUNT_0 |
24245 | #define L2_PERF_COUNT_0__L2PerfCount0__SHIFT 0x0 |
24246 | #define L2_PERF_COUNT_0__L2PerfCount0_MASK 0xFFFFFFFFL |
24247 | //L2_PERF_COUNT_1 |
24248 | #define L2_PERF_COUNT_1__L2PerfCount1__SHIFT 0x0 |
24249 | #define L2_PERF_COUNT_1__L2PerfCount1_MASK 0xFFFFFFFFL |
24250 | //L2_PERF_CNTL_1 |
24251 | #define L2_PERF_CNTL_1__L2PerfEvent2__SHIFT 0x0 |
24252 | #define L2_PERF_CNTL_1__L2PerfEvent3__SHIFT 0x8 |
24253 | #define L2_PERF_CNTL_1__L2PerfCountUpper2__SHIFT 0x10 |
24254 | #define L2_PERF_CNTL_1__L2PerfCountUpper3__SHIFT 0x18 |
24255 | #define L2_PERF_CNTL_1__L2PerfEvent2_MASK 0x000000FFL |
24256 | #define L2_PERF_CNTL_1__L2PerfEvent3_MASK 0x0000FF00L |
24257 | #define L2_PERF_CNTL_1__L2PerfCountUpper2_MASK 0x00FF0000L |
24258 | #define L2_PERF_CNTL_1__L2PerfCountUpper3_MASK 0xFF000000L |
24259 | //L2_PERF_COUNT_2 |
24260 | #define L2_PERF_COUNT_2__L2PerfCount2__SHIFT 0x0 |
24261 | #define L2_PERF_COUNT_2__L2PerfCount2_MASK 0xFFFFFFFFL |
24262 | //L2_PERF_COUNT_3 |
24263 | #define L2_PERF_COUNT_3__L2PerfCount3__SHIFT 0x0 |
24264 | #define L2_PERF_COUNT_3__L2PerfCount3_MASK 0xFFFFFFFFL |
24265 | //L2_STATUS_0 |
24266 | #define L2_STATUS_0__L2STATUS0__SHIFT 0x0 |
24267 | #define L2_STATUS_0__L2STATUS0_MASK 0xFFFFFFFFL |
24268 | //L2_CONTROL_0 |
24269 | #define L2_CONTROL_0__AllowL1CacheVZero__SHIFT 0x1 |
24270 | #define L2_CONTROL_0__AllowL1CacheATSRsp__SHIFT 0x2 |
24271 | #define L2_CONTROL_0__DTCHitVZeroOrIVZero__SHIFT 0x3 |
24272 | #define L2_CONTROL_0__L1CacheATSRsp_Enable__SHIFT 0x4 |
24273 | #define L2_CONTROL_0__L1CacheATSRsp_L1ID__SHIFT 0x5 |
24274 | #define L2_CONTROL_0__SIDEPTEOnUntransExcl__SHIFT 0xa |
24275 | #define L2_CONTROL_0__SIDEPTEOnAddrTransExcl__SHIFT 0xb |
24276 | #define L2_CONTROL_0__Allow_nonats_u_bit__SHIFT 0xc |
24277 | #define L2_CONTROL_0__DTE_I_MASK_ENABLE__SHIFT 0xd |
24278 | #define L2_CONTROL_0__DTE_I_MASK_L1ID__SHIFT 0xe |
24279 | #define L2_CONTROL_0__FLTCMBPriority__SHIFT 0x12 |
24280 | #define L2_CONTROL_0__AllowL1CacheLargePagemode0__SHIFT 0x13 |
24281 | #define L2_CONTROL_0__IFifoBurstLength__SHIFT 0x14 |
24282 | #define L2_CONTROL_0__IFifoClientPriority__SHIFT 0x18 |
24283 | #define L2_CONTROL_0__AllowL1CacheVZero_MASK 0x00000002L |
24284 | #define L2_CONTROL_0__AllowL1CacheATSRsp_MASK 0x00000004L |
24285 | #define L2_CONTROL_0__DTCHitVZeroOrIVZero_MASK 0x00000008L |
24286 | #define L2_CONTROL_0__L1CacheATSRsp_Enable_MASK 0x00000010L |
24287 | #define L2_CONTROL_0__L1CacheATSRsp_L1ID_MASK 0x000000E0L |
24288 | #define L2_CONTROL_0__SIDEPTEOnUntransExcl_MASK 0x00000400L |
24289 | #define L2_CONTROL_0__SIDEPTEOnAddrTransExcl_MASK 0x00000800L |
24290 | #define L2_CONTROL_0__Allow_nonats_u_bit_MASK 0x00001000L |
24291 | #define L2_CONTROL_0__DTE_I_MASK_ENABLE_MASK 0x00002000L |
24292 | #define L2_CONTROL_0__DTE_I_MASK_L1ID_MASK 0x0001C000L |
24293 | #define L2_CONTROL_0__FLTCMBPriority_MASK 0x00040000L |
24294 | #define L2_CONTROL_0__AllowL1CacheLargePagemode0_MASK 0x00080000L |
24295 | #define L2_CONTROL_0__IFifoBurstLength_MASK 0x00F00000L |
24296 | #define L2_CONTROL_0__IFifoClientPriority_MASK 0xFF000000L |
24297 | //L2_CONTROL_1 |
24298 | #define L2_CONTROL_1__SeqInvBurstLimitInv__SHIFT 0x0 |
24299 | #define L2_CONTROL_1__SeqInvBurstLimitL2Req__SHIFT 0x8 |
24300 | #define L2_CONTROL_1__SeqInvBurstLimitEn__SHIFT 0x10 |
24301 | #define L2_CONTROL_1__PerfThreshold__SHIFT 0x18 |
24302 | #define L2_CONTROL_1__SeqInvBurstLimitInv_MASK 0x000000FFL |
24303 | #define L2_CONTROL_1__SeqInvBurstLimitL2Req_MASK 0x0000FF00L |
24304 | #define L2_CONTROL_1__SeqInvBurstLimitEn_MASK 0x00010000L |
24305 | #define L2_CONTROL_1__PerfThreshold_MASK 0xFF000000L |
24306 | //L2_DTC_CONTROL |
24307 | #define L2_DTC_CONTROL__DTCLRUUpdatePri__SHIFT 0x3 |
24308 | #define L2_DTC_CONTROL__DTCParityEn__SHIFT 0x4 |
24309 | #define L2_DTC_CONTROL__DTCInvalidationSel__SHIFT 0x8 |
24310 | #define L2_DTC_CONTROL__DTCSoftInvalidate__SHIFT 0xa |
24311 | #define L2_DTC_CONTROL__DTCBypass__SHIFT 0xd |
24312 | #define L2_DTC_CONTROL__DTCParitySupport__SHIFT 0xf |
24313 | #define L2_DTC_CONTROL__DTCWays__SHIFT 0x10 |
24314 | #define L2_DTC_CONTROL__DTCEntries__SHIFT 0x1c |
24315 | #define L2_DTC_CONTROL__DTCLRUUpdatePri_MASK 0x00000008L |
24316 | #define L2_DTC_CONTROL__DTCParityEn_MASK 0x00000010L |
24317 | #define L2_DTC_CONTROL__DTCInvalidationSel_MASK 0x00000300L |
24318 | #define L2_DTC_CONTROL__DTCSoftInvalidate_MASK 0x00000400L |
24319 | #define L2_DTC_CONTROL__DTCBypass_MASK 0x00002000L |
24320 | #define L2_DTC_CONTROL__DTCParitySupport_MASK 0x00008000L |
24321 | #define L2_DTC_CONTROL__DTCWays_MASK 0x00FF0000L |
24322 | #define L2_DTC_CONTROL__DTCEntries_MASK 0xF0000000L |
24323 | //L2_DTC_HASH_CONTROL |
24324 | #define L2_DTC_HASH_CONTROL__DTCAddressMask__SHIFT 0x10 |
24325 | #define L2_DTC_HASH_CONTROL__DTCAddressMask_MASK 0xFFFF0000L |
24326 | //L2_DTC_WAY_CONTROL |
24327 | #define L2_DTC_WAY_CONTROL__DTCWayDisable__SHIFT 0x0 |
24328 | #define L2_DTC_WAY_CONTROL__DTCWayAccessDisable__SHIFT 0x10 |
24329 | #define L2_DTC_WAY_CONTROL__DTCWayDisable_MASK 0x0000FFFFL |
24330 | #define L2_DTC_WAY_CONTROL__DTCWayAccessDisable_MASK 0xFFFF0000L |
24331 | //L2_ITC_CONTROL |
24332 | #define L2_ITC_CONTROL__ITCLRUUpdatePri__SHIFT 0x3 |
24333 | #define L2_ITC_CONTROL__ITCParityEn__SHIFT 0x4 |
24334 | #define L2_ITC_CONTROL__ITCInvalidationSel__SHIFT 0x8 |
24335 | #define L2_ITC_CONTROL__ITCSoftInvalidate__SHIFT 0xa |
24336 | #define L2_ITC_CONTROL__ITCBypass__SHIFT 0xd |
24337 | #define L2_ITC_CONTROL__ITCParitySupport__SHIFT 0xf |
24338 | #define L2_ITC_CONTROL__ITCWays__SHIFT 0x10 |
24339 | #define L2_ITC_CONTROL__ITCEntries__SHIFT 0x1c |
24340 | #define L2_ITC_CONTROL__ITCLRUUpdatePri_MASK 0x00000008L |
24341 | #define L2_ITC_CONTROL__ITCParityEn_MASK 0x00000010L |
24342 | #define L2_ITC_CONTROL__ITCInvalidationSel_MASK 0x00000300L |
24343 | #define L2_ITC_CONTROL__ITCSoftInvalidate_MASK 0x00000400L |
24344 | #define L2_ITC_CONTROL__ITCBypass_MASK 0x00002000L |
24345 | #define L2_ITC_CONTROL__ITCParitySupport_MASK 0x00008000L |
24346 | #define L2_ITC_CONTROL__ITCWays_MASK 0x00FF0000L |
24347 | #define L2_ITC_CONTROL__ITCEntries_MASK 0xF0000000L |
24348 | //L2_ITC_HASH_CONTROL |
24349 | #define L2_ITC_HASH_CONTROL__ITCAddressMask__SHIFT 0x10 |
24350 | #define L2_ITC_HASH_CONTROL__ITCAddressMask_MASK 0xFFFF0000L |
24351 | //L2_ITC_WAY_CONTROL |
24352 | #define L2_ITC_WAY_CONTROL__ITCWayDisable__SHIFT 0x0 |
24353 | #define L2_ITC_WAY_CONTROL__ITCWayAccessDisable__SHIFT 0x10 |
24354 | #define L2_ITC_WAY_CONTROL__ITCWayDisable_MASK 0x0000FFFFL |
24355 | #define L2_ITC_WAY_CONTROL__ITCWayAccessDisable_MASK 0xFFFF0000L |
24356 | //L2_PTC_A_CONTROL |
24357 | #define L2_PTC_A_CONTROL__PTCAStoreFinalATSeperate__SHIFT 0x1 |
24358 | #define L2_PTC_A_CONTROL__PTCAStorePartialATSeperate__SHIFT 0x2 |
24359 | #define L2_PTC_A_CONTROL__PTCALRUUpdatePri__SHIFT 0x3 |
24360 | #define L2_PTC_A_CONTROL__PTCAParityEn__SHIFT 0x4 |
24361 | #define L2_PTC_A_CONTROL__PTCAInvalidationSel__SHIFT 0x8 |
24362 | #define L2_PTC_A_CONTROL__PTCASoftInvalidate__SHIFT 0xa |
24363 | #define L2_PTC_A_CONTROL__PTCA2MMode__SHIFT 0xb |
24364 | #define L2_PTC_A_CONTROL__PTCABypass__SHIFT 0xd |
24365 | #define L2_PTC_A_CONTROL__PTCAParitySupport__SHIFT 0xf |
24366 | #define L2_PTC_A_CONTROL__PTCAWays__SHIFT 0x10 |
24367 | #define L2_PTC_A_CONTROL__PTCAEntries__SHIFT 0x1c |
24368 | #define L2_PTC_A_CONTROL__PTCAStoreFinalATSeperate_MASK 0x00000002L |
24369 | #define L2_PTC_A_CONTROL__PTCAStorePartialATSeperate_MASK 0x00000004L |
24370 | #define L2_PTC_A_CONTROL__PTCALRUUpdatePri_MASK 0x00000008L |
24371 | #define L2_PTC_A_CONTROL__PTCAParityEn_MASK 0x00000010L |
24372 | #define L2_PTC_A_CONTROL__PTCAInvalidationSel_MASK 0x00000300L |
24373 | #define L2_PTC_A_CONTROL__PTCASoftInvalidate_MASK 0x00000400L |
24374 | #define L2_PTC_A_CONTROL__PTCA2MMode_MASK 0x00000800L |
24375 | #define L2_PTC_A_CONTROL__PTCABypass_MASK 0x00002000L |
24376 | #define L2_PTC_A_CONTROL__PTCAParitySupport_MASK 0x00008000L |
24377 | #define L2_PTC_A_CONTROL__PTCAWays_MASK 0x00FF0000L |
24378 | #define L2_PTC_A_CONTROL__PTCAEntries_MASK 0xF0000000L |
24379 | //L2_PTC_A_HASH_CONTROL |
24380 | #define L2_PTC_A_HASH_CONTROL__PTCAAddressMask__SHIFT 0x10 |
24381 | #define L2_PTC_A_HASH_CONTROL__PTCAAddressMask_MASK 0xFFFF0000L |
24382 | //L2_PTC_A_WAY_CONTROL |
24383 | #define L2_PTC_A_WAY_CONTROL__PTCAWayDisable__SHIFT 0x0 |
24384 | #define L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable__SHIFT 0x10 |
24385 | #define L2_PTC_A_WAY_CONTROL__PTCAWayDisable_MASK 0x0000FFFFL |
24386 | #define L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable_MASK 0xFFFF0000L |
24387 | //L2_CREDIT_CONTROL_2 |
24388 | #define L2_CREDIT_CONTROL_2__QUEUECredits__SHIFT 0x0 |
24389 | #define L2_CREDIT_CONTROL_2__QUEUEOverride__SHIFT 0x7 |
24390 | #define L2_CREDIT_CONTROL_2__FLTCMBCredits__SHIFT 0x8 |
24391 | #define L2_CREDIT_CONTROL_2__FLTCMBOverride__SHIFT 0xf |
24392 | #define L2_CREDIT_CONTROL_2__FCELCredits__SHIFT 0x10 |
24393 | #define L2_CREDIT_CONTROL_2__FCELOverride__SHIFT 0x17 |
24394 | #define L2_CREDIT_CONTROL_2__PPR_logger_credits__SHIFT 0x18 |
24395 | #define L2_CREDIT_CONTROL_2__QUEUECredits_MASK 0x0000003FL |
24396 | #define L2_CREDIT_CONTROL_2__QUEUEOverride_MASK 0x00000080L |
24397 | #define L2_CREDIT_CONTROL_2__FLTCMBCredits_MASK 0x00003F00L |
24398 | #define L2_CREDIT_CONTROL_2__FLTCMBOverride_MASK 0x00008000L |
24399 | #define L2_CREDIT_CONTROL_2__FCELCredits_MASK 0x003F0000L |
24400 | #define L2_CREDIT_CONTROL_2__FCELOverride_MASK 0x00800000L |
24401 | #define L2_CREDIT_CONTROL_2__PPR_logger_credits_MASK 0x0F000000L |
24402 | //L2A_UPDATE_FILTER_CNTL |
24403 | #define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass__SHIFT 0x0 |
24404 | #define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency__SHIFT 0x1 |
24405 | #define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass_MASK 0x00000001L |
24406 | #define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency_MASK 0x0000001EL |
24407 | //L2_ERR_RULE_CONTROL_3 |
24408 | #define L2_ERR_RULE_CONTROL_3__ERRRuleLock1__SHIFT 0x0 |
24409 | #define L2_ERR_RULE_CONTROL_3__ERRRuleDisable3__SHIFT 0x4 |
24410 | #define L2_ERR_RULE_CONTROL_3__ERRRuleLock1_MASK 0x00000001L |
24411 | #define L2_ERR_RULE_CONTROL_3__ERRRuleDisable3_MASK 0xFFFFFFF0L |
24412 | //L2_ERR_RULE_CONTROL_4 |
24413 | #define L2_ERR_RULE_CONTROL_4__ERRRuleDisable4__SHIFT 0x0 |
24414 | #define L2_ERR_RULE_CONTROL_4__ERRRuleDisable4_MASK 0xFFFFFFFFL |
24415 | //L2_ERR_RULE_CONTROL_5 |
24416 | #define L2_ERR_RULE_CONTROL_5__ERRRuleDisable5__SHIFT 0x0 |
24417 | #define L2_ERR_RULE_CONTROL_5__ERRRuleDisable5_MASK 0xFFFFFFFFL |
24418 | //L2_L2A_PGSIZE_CONTROL |
24419 | #define L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE__SHIFT 0x0 |
24420 | #define L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE__SHIFT 0x8 |
24421 | #define L2_L2A_PGSIZE_CONTROL__L2AREG_PTCSCAN_MODE__SHIFT 0x11 |
24422 | #define L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE_MASK 0x0000007FL |
24423 | #define L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE_MASK 0x00007F00L |
24424 | #define L2_L2A_PGSIZE_CONTROL__L2AREG_PTCSCAN_MODE_MASK 0x000E0000L |
24425 | //L2_L2A_MEMPWR_GATE_1 |
24426 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_LS_EN__SHIFT 0x0 |
24427 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_DS_EN__SHIFT 0x1 |
24428 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_SD_EN__SHIFT 0x2 |
24429 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_CACHE_PGMEM_SEL__SHIFT 0x4 |
24430 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_LS_EN_MASK 0x00000001L |
24431 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_DS_EN_MASK 0x00000002L |
24432 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_SD_EN_MASK 0x00000004L |
24433 | #define L2_L2A_MEMPWR_GATE_1__L2AREG_CACHE_PGMEM_SEL_MASK 0x00000010L |
24434 | //L2_L2A_MEMPWR_GATE_2 |
24435 | #define L2_L2A_MEMPWR_GATE_2__L2AREG_LS_thres__SHIFT 0x0 |
24436 | #define L2_L2A_MEMPWR_GATE_2__L2AREG_LS_thres_MASK 0xFFFFFFFFL |
24437 | //L2_L2A_MEMPWR_GATE_3 |
24438 | #define L2_L2A_MEMPWR_GATE_3__L2AREG_DS_thres__SHIFT 0x0 |
24439 | #define L2_L2A_MEMPWR_GATE_3__L2AREG_DS_thres_MASK 0xFFFFFFFFL |
24440 | //L2_L2A_MEMPWR_GATE_4 |
24441 | #define L2_L2A_MEMPWR_GATE_4__L2AREG_SD_thres__SHIFT 0x0 |
24442 | #define L2_L2A_MEMPWR_GATE_4__L2AREG_SD_thres_MASK 0xFFFFFFFFL |
24443 | //L2_L2A_MEMPWR_GATE_5 |
24444 | #define L2_L2A_MEMPWR_GATE_5__L2AREG_LS_Req_Maintain_Cnt__SHIFT 0x0 |
24445 | #define L2_L2A_MEMPWR_GATE_5__L2AREG_LS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL |
24446 | //L2_L2A_MEMPWR_GATE_6 |
24447 | #define L2_L2A_MEMPWR_GATE_6__L2AREG_LS_Exit_Maintain_Cnt__SHIFT 0x0 |
24448 | #define L2_L2A_MEMPWR_GATE_6__L2AREG_LS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL |
24449 | //L2_L2A_MEMPWR_GATE_7 |
24450 | #define L2_L2A_MEMPWR_GATE_7__L2AREG_DS_Req_Maintain_Cnt__SHIFT 0x0 |
24451 | #define L2_L2A_MEMPWR_GATE_7__L2AREG_DS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL |
24452 | //L2_L2A_MEMPWR_GATE_8 |
24453 | #define L2_L2A_MEMPWR_GATE_8__L2AREG_DS_Exit_Maintain_Cnt__SHIFT 0x0 |
24454 | #define L2_L2A_MEMPWR_GATE_8__L2AREG_DS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL |
24455 | //L2_L2A_MEMPWR_GATE_9 |
24456 | #define L2_L2A_MEMPWR_GATE_9__L2AREG_SD_Req_Maintain_Cnt__SHIFT 0x0 |
24457 | #define L2_L2A_MEMPWR_GATE_9__L2AREG_SD_Req_Maintain_Cnt_MASK 0xFFFFFFFFL |
24458 | //L2_L2A_MEMPWR_GATE_10 |
24459 | #define L2_L2A_MEMPWR_GATE_10__L2AREG_SD_Exit_Maintain_Cnt__SHIFT 0x0 |
24460 | #define L2_L2A_MEMPWR_GATE_10__L2AREG_SD_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL |
24461 | //L2_ECO_CNTRL_0 |
24462 | #define L2_ECO_CNTRL_0__L2_ECO_0__SHIFT 0x0 |
24463 | #define L2_ECO_CNTRL_0__L2_ECO_0_MASK 0xFFFFFFFFL |
24464 | |
24465 | |
24466 | // addressBlock: nbio_iohub_nb_ioapiccfg_ioapic_cfgdec |
24467 | //FEATURES_ENABLE |
24468 | #define FEATURES_ENABLE__Ioapic_id_ext_en__SHIFT 0x2 |
24469 | #define FEATURES_ENABLE__Ioapic_sb_feature_en__SHIFT 0x4 |
24470 | #define FEATURES_ENABLE__Ioapic_secondary_en__SHIFT 0x5 |
24471 | #define FEATURES_ENABLE__Ioapic_processor_mode__SHIFT 0x8 |
24472 | #define FEATURES_ENABLE__INTx_LevelOnlyMode__SHIFT 0x9 |
24473 | #define FEATURES_ENABLE__Ioapic_id_ext_en_MASK 0x00000004L |
24474 | #define FEATURES_ENABLE__Ioapic_sb_feature_en_MASK 0x00000010L |
24475 | #define FEATURES_ENABLE__Ioapic_secondary_en_MASK 0x00000020L |
24476 | #define FEATURES_ENABLE__Ioapic_processor_mode_MASK 0x00000100L |
24477 | #define FEATURES_ENABLE__INTx_LevelOnlyMode_MASK 0x00000200L |
24478 | |
24479 | |
24480 | // addressBlock: nbio_pcie0_pciedir |
24481 | //PCIE_USB4_TXAL_CNTL1 |
24482 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TX_CREDITS__SHIFT 0x0 |
24483 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_REQ_FLUSH_ON_PERST_EN__SHIFT 0x8 |
24484 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_IGNORE_PERST_ON_PE__SHIFT 0x9 |
24485 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_SAVE_OS_DATA__SHIFT 0xa |
24486 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_DLLP2_EN__SHIFT 0xb |
24487 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_CLKSW_WAIT_EN__SHIFT 0xc |
24488 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_PRELOAD_FIX_DIS__SHIFT 0xd |
24489 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_REQ_FLUSH_ON_RESET__SHIFT 0x10 |
24490 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_TEARDOWN_FIX_DIS__SHIFT 0x11 |
24491 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_WAIT_FOR_TXAL_FLUSH_DIS__SHIFT 0x12 |
24492 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_DLLP_REQ_HOLD_OLD__SHIFT 0x13 |
24493 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_HP_HALT_FIX_DIS__SHIFT 0x14 |
24494 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_FLUSH_DISC_DIS__SHIFT 0x15 |
24495 | #define PCIE_USB4_TXAL_CNTL1__TXAL_REQ_DROP_ON_RESET_DIS__SHIFT 0x16 |
24496 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_TPI_FLUSH_DIS__SHIFT 0x17 |
24497 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TX_CREDITS_MASK 0x000000FFL |
24498 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_REQ_FLUSH_ON_PERST_EN_MASK 0x00000100L |
24499 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_IGNORE_PERST_ON_PE_MASK 0x00000200L |
24500 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_SAVE_OS_DATA_MASK 0x00000400L |
24501 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_DLLP2_EN_MASK 0x00000800L |
24502 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_CLKSW_WAIT_EN_MASK 0x00001000L |
24503 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_PRELOAD_FIX_DIS_MASK 0x00002000L |
24504 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_REQ_FLUSH_ON_RESET_MASK 0x00010000L |
24505 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_TEARDOWN_FIX_DIS_MASK 0x00020000L |
24506 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_WAIT_FOR_TXAL_FLUSH_DIS_MASK 0x00040000L |
24507 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_DLLP_REQ_HOLD_OLD_MASK 0x00080000L |
24508 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_HP_HALT_FIX_DIS_MASK 0x00100000L |
24509 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_FLUSH_DISC_DIS_MASK 0x00200000L |
24510 | #define PCIE_USB4_TXAL_CNTL1__TXAL_REQ_DROP_ON_RESET_DIS_MASK 0x00400000L |
24511 | #define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_TPI_FLUSH_DIS_MASK 0x00800000L |
24512 | //PCIE_USB4_RXAL_CNTL1 |
24513 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_DLLP_TLP_DECODE_EN__SHIFT 0x0 |
24514 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXEI_WAIT_RXAL_EMPTY_EN__SHIFT 0x1 |
24515 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXEI_WAIT_RXAL_IDLE_EN__SHIFT 0x2 |
24516 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_IDLE_WAIT_FOR_TPI_RESET__SHIFT 0x3 |
24517 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_IDLE_WAIT_FOR_PATH_ENABLE__SHIFT 0x4 |
24518 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_CHK_PASS__SHIFT 0x8 |
24519 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_SUPPID_PASS__SHIFT 0x9 |
24520 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_PDF_PASS__SHIFT 0xa |
24521 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_LEN_PASS__SHIFT 0xb |
24522 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_DLLP2_EN__SHIFT 0xc |
24523 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_PDF_ERR_EN__SHIFT 0xd |
24524 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FLUSH_ON_PE_EN__SHIFT 0xe |
24525 | #define PCIE_USB4_RXAL_CNTL1__USB_62_164_FIX_DIS__SHIFT 0xf |
24526 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_DLLP_TLP_DECODE_EN_MASK 0x00000001L |
24527 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXEI_WAIT_RXAL_EMPTY_EN_MASK 0x00000002L |
24528 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXEI_WAIT_RXAL_IDLE_EN_MASK 0x00000004L |
24529 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_IDLE_WAIT_FOR_TPI_RESET_MASK 0x00000008L |
24530 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_IDLE_WAIT_FOR_PATH_ENABLE_MASK 0x00000010L |
24531 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_CHK_PASS_MASK 0x00000100L |
24532 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_SUPPID_PASS_MASK 0x00000200L |
24533 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_PDF_PASS_MASK 0x00000400L |
24534 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_LEN_PASS_MASK 0x00000800L |
24535 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_DLLP2_EN_MASK 0x00001000L |
24536 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_PDF_ERR_EN_MASK 0x00002000L |
24537 | #define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FLUSH_ON_PE_EN_MASK 0x00004000L |
24538 | #define PCIE_USB4_RXAL_CNTL1__USB_62_164_FIX_DIS_MASK 0x00008000L |
24539 | //PCIE_USB4_AL_CNTL1 |
24540 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_TXAL_IDLE_IGNORE_EN__SHIFT 0x2 |
24541 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_RXAL_IDLE_IGNORE_EN__SHIFT 0x3 |
24542 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_AL_IDLE_IGNORE_EN__SHIFT 0x4 |
24543 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_TXAL_GATE_EN__SHIFT 0x5 |
24544 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_RXAL_GATE_EN__SHIFT 0x6 |
24545 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_AL_GATE_EN__SHIFT 0x7 |
24546 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_IGNORE_HW_PATH_ENABLE__SHIFT 0x9 |
24547 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_AL_IGNORE_CLK_SWITCH_EN__SHIFT 0xa |
24548 | #define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_OVERRIDE_EN__SHIFT 0xb |
24549 | #define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_PCIE_CIO_RST_REQ_VALUE__SHIFT 0xc |
24550 | #define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_CIO_PCIE_RST_RDY_VALUE__SHIFT 0xd |
24551 | #define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_READY_VALUE__SHIFT 0xe |
24552 | #define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_ON_PATH_EN_DIS__SHIFT 0xf |
24553 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_HW_PE_OVERRIDE_EN__SHIFT 0x10 |
24554 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_HW_PE_BLOCK_IN_TUNNEL_DISABLE_EN__SHIFT 0x11 |
24555 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_DISC_IN_SLEEP__SHIFT 0x12 |
24556 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_PG_IN_L23__SHIFT 0x13 |
24557 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_PG_IN_PE_DIS__SHIFT 0x14 |
24558 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_AL_TXCLK_UNGATE_DIS__SHIFT 0x15 |
24559 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_RECONFIG_ON_PE__SHIFT 0x17 |
24560 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_FORCE_AL_RECONFIG_ACK__SHIFT 0x18 |
24561 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_RECONFIG_IGNORE_AL__SHIFT 0x19 |
24562 | #define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_ON_RECONFIG_EN__SHIFT 0x1a |
24563 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_PARTIAL_DISC_EN__SHIFT 0x1b |
24564 | #define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_ON_LOW_CHECK_DIS__SHIFT 0x1c |
24565 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_AL_MNTR_WAKE_REQ_DIS__SHIFT 0x1d |
24566 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_BYPASS_PCS_HOLD__SHIFT 0x1e |
24567 | #define PCIE_USB4_AL_CNTL1__PCIE_CIO_PART_CONN_EN__SHIFT 0x1f |
24568 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_TXAL_IDLE_IGNORE_EN_MASK 0x00000004L |
24569 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_RXAL_IDLE_IGNORE_EN_MASK 0x00000008L |
24570 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_AL_IDLE_IGNORE_EN_MASK 0x00000010L |
24571 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_TXAL_GATE_EN_MASK 0x00000020L |
24572 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_RXAL_GATE_EN_MASK 0x00000040L |
24573 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_AL_GATE_EN_MASK 0x00000080L |
24574 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_IGNORE_HW_PATH_ENABLE_MASK 0x00000200L |
24575 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_AL_IGNORE_CLK_SWITCH_EN_MASK 0x00000400L |
24576 | #define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_OVERRIDE_EN_MASK 0x00000800L |
24577 | #define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_PCIE_CIO_RST_REQ_VALUE_MASK 0x00001000L |
24578 | #define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_CIO_PCIE_RST_RDY_VALUE_MASK 0x00002000L |
24579 | #define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_READY_VALUE_MASK 0x00004000L |
24580 | #define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_ON_PATH_EN_DIS_MASK 0x00008000L |
24581 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_HW_PE_OVERRIDE_EN_MASK 0x00010000L |
24582 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_HW_PE_BLOCK_IN_TUNNEL_DISABLE_EN_MASK 0x00020000L |
24583 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_DISC_IN_SLEEP_MASK 0x00040000L |
24584 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_PG_IN_L23_MASK 0x00080000L |
24585 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_PG_IN_PE_DIS_MASK 0x00100000L |
24586 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_AL_TXCLK_UNGATE_DIS_MASK 0x00200000L |
24587 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_RECONFIG_ON_PE_MASK 0x00800000L |
24588 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_FORCE_AL_RECONFIG_ACK_MASK 0x01000000L |
24589 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_RECONFIG_IGNORE_AL_MASK 0x02000000L |
24590 | #define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_ON_RECONFIG_EN_MASK 0x04000000L |
24591 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_PARTIAL_DISC_EN_MASK 0x08000000L |
24592 | #define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_ON_LOW_CHECK_DIS_MASK 0x10000000L |
24593 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_AL_MNTR_WAKE_REQ_DIS_MASK 0x20000000L |
24594 | #define PCIE_USB4_AL_CNTL1__PCIE_USB_BYPASS_PCS_HOLD_MASK 0x40000000L |
24595 | #define PCIE_USB4_AL_CNTL1__PCIE_CIO_PART_CONN_EN_MASK 0x80000000L |
24596 | //PCIE_USB4_AL_CNTL2 |
24597 | #define PCIE_USB4_AL_CNTL2__PCIE_USB_AL_PG_IGNORE_SIDEBAND__SHIFT 0x0 |
24598 | #define PCIE_USB4_AL_CNTL2__PCIE_USB_PG_HT_CHECK_AL_DIS__SHIFT 0x8 |
24599 | #define PCIE_USB4_AL_CNTL2__PCIE_USB_PG_IGNORE_HT__SHIFT 0x9 |
24600 | #define PCIE_USB4_AL_CNTL2__PCIE_AL_TPI_RESET_HANDSHAKE_DIS__SHIFT 0xa |
24601 | #define PCIE_USB4_AL_CNTL2__PCIE_AL_RXAL_RESET_HANDSHAKE_DIS__SHIFT 0xb |
24602 | #define PCIE_USB4_AL_CNTL2__PCIE_AL_TXAL_RESET_HANDSHAKE_DIS__SHIFT 0xc |
24603 | #define PCIE_USB4_AL_CNTL2__PCIE_TPI_RESET_BLOCK_TXAL_EN__SHIFT 0xe |
24604 | #define PCIE_USB4_AL_CNTL2__PCIE_TXAL_LOCAL_RESET_EN__SHIFT 0xf |
24605 | #define PCIE_USB4_AL_CNTL2__PCIE_TXAL_PERST_INACT_INIT_BY_TPIRST_EN__SHIFT 0x10 |
24606 | #define PCIE_USB4_AL_CNTL2__PCIE_USB4_ALL_CLKREQ_IDLE_NODELAY_AL_TEARDOWN_COMPLETE_EN__SHIFT 0x11 |
24607 | #define PCIE_USB4_AL_CNTL2__PCIE_USB_AL_PG_IGNORE_SIDEBAND_MASK 0x000000FFL |
24608 | #define PCIE_USB4_AL_CNTL2__PCIE_USB_PG_HT_CHECK_AL_DIS_MASK 0x00000100L |
24609 | #define PCIE_USB4_AL_CNTL2__PCIE_USB_PG_IGNORE_HT_MASK 0x00000200L |
24610 | #define PCIE_USB4_AL_CNTL2__PCIE_AL_TPI_RESET_HANDSHAKE_DIS_MASK 0x00000400L |
24611 | #define PCIE_USB4_AL_CNTL2__PCIE_AL_RXAL_RESET_HANDSHAKE_DIS_MASK 0x00000800L |
24612 | #define PCIE_USB4_AL_CNTL2__PCIE_AL_TXAL_RESET_HANDSHAKE_DIS_MASK 0x00001000L |
24613 | #define PCIE_USB4_AL_CNTL2__PCIE_TPI_RESET_BLOCK_TXAL_EN_MASK 0x00004000L |
24614 | #define PCIE_USB4_AL_CNTL2__PCIE_TXAL_LOCAL_RESET_EN_MASK 0x00008000L |
24615 | #define PCIE_USB4_AL_CNTL2__PCIE_TXAL_PERST_INACT_INIT_BY_TPIRST_EN_MASK 0x00010000L |
24616 | #define PCIE_USB4_AL_CNTL2__PCIE_USB4_ALL_CLKREQ_IDLE_NODELAY_AL_TEARDOWN_COMPLETE_EN_MASK 0x00020000L |
24617 | //PCIE_USB4_AL_HYSTERESIS |
24618 | #define PCIE_USB4_AL_HYSTERESIS__PCIE_CIO_RESET_HYSTERESIS__SHIFT 0x0 |
24619 | #define PCIE_USB4_AL_HYSTERESIS__PCIE_CIO_INIT_HYSTERESIS__SHIFT 0x8 |
24620 | #define PCIE_USB4_AL_HYSTERESIS__PCIE_CIO_TEARDOWN_HYSTERESIS__SHIFT 0x10 |
24621 | #define PCIE_USB4_AL_HYSTERESIS__PCIE_CIO_RESET_HYSTERESIS_MASK 0x000000FFL |
24622 | #define PCIE_USB4_AL_HYSTERESIS__PCIE_CIO_INIT_HYSTERESIS_MASK 0x0000FF00L |
24623 | #define PCIE_USB4_AL_HYSTERESIS__PCIE_CIO_TEARDOWN_HYSTERESIS_MASK 0x00FF0000L |
24624 | //PCIE_USB4_AL_HYSTERESIS_2 |
24625 | #define PCIE_USB4_AL_HYSTERESIS_2__PCIE_USB_RXAL_RESET_HYSTERESIS__SHIFT 0x8 |
24626 | #define PCIE_USB4_AL_HYSTERESIS_2__PCIE_USB_TXAL_IDLE_HYSTERESIS__SHIFT 0x10 |
24627 | #define PCIE_USB4_AL_HYSTERESIS_2__PCIE_USB_RXAL_IDLE_HYSTERESIS__SHIFT 0x18 |
24628 | #define PCIE_USB4_AL_HYSTERESIS_2__PCIE_USB_RXAL_RESET_HYSTERESIS_MASK 0x0000FF00L |
24629 | #define PCIE_USB4_AL_HYSTERESIS_2__PCIE_USB_TXAL_IDLE_HYSTERESIS_MASK 0x00FF0000L |
24630 | #define PCIE_USB4_AL_HYSTERESIS_2__PCIE_USB_RXAL_IDLE_HYSTERESIS_MASK 0xFF000000L |
24631 | //PCIE_USB4_ERR_CNTL5 |
24632 | #define PCIE_USB4_ERR_CNTL5__PCIE_USB_RXAL_ERR_RECORD_MODE__SHIFT 0x0 |
24633 | #define PCIE_USB4_ERR_CNTL5__PCIE_USB_RXAL_ERR_RECORD_MODE_MASK 0x00000001L |
24634 | //PCIE_USB4_LC_CNTL1 |
24635 | #define PCIE_USB4_LC_CNTL1__PCIE_USB_ROUTER_CLEAR_PATH_MODE__SHIFT 0x0 |
24636 | #define PCIE_USB4_LC_CNTL1__PCIE_USB_ROUTER_CLEAR_PATH_MODE_MASK 0x00000001L |
24637 | //BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL |
24638 | #define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L |
24639 | #define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L |
24640 | #define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x00000020L |
24641 | #define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x00000040L |
24642 | #define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x00000080L |
24643 | #define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L |
24644 | //BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2 |
24645 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L |
24646 | //BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1 |
24647 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L |
24648 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L |
24649 | //BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3 |
24650 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x8 |
24651 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x9 |
24652 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_10BIT_TAG_EN_OVERRIDE__SHIFT 0xb |
24653 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_10BIT_TAG_EN_OVERRIDE__SHIFT 0xd |
24654 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__MST_DROP_SYNC_FLOOD_EN__SHIFT 0xf |
24655 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10 |
24656 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11 |
24657 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14 |
24658 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15 |
24659 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_SAFE_MODE__SHIFT 0x18 |
24660 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
24661 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1b |
24662 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT 0x1c |
24663 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x1e |
24664 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK 0x00000100L |
24665 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK 0x00000600L |
24666 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_10BIT_TAG_EN_OVERRIDE_MASK 0x00001800L |
24667 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_10BIT_TAG_EN_OVERRIDE_MASK 0x00006000L |
24668 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__MST_DROP_SYNC_FLOOD_EN_MASK 0x00008000L |
24669 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x00010000L |
24670 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0x000E0000L |
24671 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x00100000L |
24672 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0x00E00000L |
24673 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_SAFE_MODE_MASK 0x01000000L |
24674 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
24675 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK 0x08000000L |
24676 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK 0x30000000L |
24677 | #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK 0xC0000000L |
24678 | |
24679 | // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp |
24680 | //BIF_CFG_DEV0_RC0_VENDOR_ID |
24681 | #define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
24682 | #define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
24683 | //BIF_CFG_DEV0_RC0_DEVICE_ID |
24684 | #define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
24685 | #define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
24686 | //BIF_CFG_DEV0_RC0_COMMAND |
24687 | #define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT 0x0 |
24688 | #define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT 0x1 |
24689 | #define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
24690 | #define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
24691 | #define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
24692 | #define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
24693 | #define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT 0x7 |
24694 | #define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT 0x8 |
24695 | #define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
24696 | #define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT 0xa |
24697 | #define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK 0x0001L |
24698 | #define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK 0x0002L |
24699 | #define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
24700 | #define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
24701 | #define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
24702 | #define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
24703 | #define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK 0x0080L |
24704 | #define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK 0x0100L |
24705 | #define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
24706 | #define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK 0x0400L |
24707 | //BIF_CFG_DEV0_RC0_STATUS |
24708 | #define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
24709 | #define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT 0x3 |
24710 | #define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT 0x4 |
24711 | #define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP__SHIFT 0x5 |
24712 | #define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
24713 | #define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
24714 | #define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
24715 | #define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
24716 | #define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
24717 | #define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
24718 | #define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
24719 | #define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK 0x0008L |
24720 | #define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK 0x0010L |
24721 | #define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP_MASK 0x0020L |
24722 | #define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
24723 | #define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
24724 | #define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
24725 | #define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
24726 | #define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
24727 | #define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
24728 | //BIF_CFG_DEV0_RC0_REVISION_ID |
24729 | #define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
24730 | #define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
24731 | #define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
24732 | #define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
24733 | //BIF_CFG_DEV0_RC0_PROG_INTERFACE |
24734 | #define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
24735 | #define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
24736 | //BIF_CFG_DEV0_RC0_SUB_CLASS |
24737 | #define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
24738 | #define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
24739 | //BIF_CFG_DEV0_RC0_BASE_CLASS |
24740 | #define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
24741 | #define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
24742 | //BIF_CFG_DEV0_RC0_CACHE_LINE |
24743 | #define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
24744 | #define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
24745 | //BIF_CFG_DEV0_RC0_LATENCY |
24746 | #define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
24747 | #define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
24748 | //BIF_CFG_DEV0_RC0_HEADER |
24749 | #define 0x0 |
24750 | #define 0x7 |
24751 | #define 0x7FL |
24752 | #define 0x80L |
24753 | //BIF_CFG_DEV0_RC0_BIST |
24754 | #define BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT 0x0 |
24755 | #define BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT 0x6 |
24756 | #define BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT 0x7 |
24757 | #define BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK 0x0FL |
24758 | #define BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK 0x40L |
24759 | #define BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK 0x80L |
24760 | //BIF_CFG_DEV0_RC0_BASE_ADDR_1 |
24761 | #define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
24762 | #define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
24763 | //BIF_CFG_DEV0_RC0_BASE_ADDR_2 |
24764 | #define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
24765 | #define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
24766 | //BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY |
24767 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
24768 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
24769 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
24770 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
24771 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
24772 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
24773 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
24774 | #define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
24775 | //BIF_CFG_DEV0_RC0_IO_BASE_LIMIT |
24776 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
24777 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
24778 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
24779 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
24780 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
24781 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
24782 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
24783 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
24784 | //BIF_CFG_DEV0_RC0_SECONDARY_STATUS |
24785 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 |
24786 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
24787 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
24788 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
24789 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
24790 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
24791 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
24792 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L |
24793 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
24794 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
24795 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
24796 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
24797 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
24798 | #define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
24799 | //BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT |
24800 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
24801 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
24802 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
24803 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
24804 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
24805 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
24806 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
24807 | #define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
24808 | //BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT |
24809 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
24810 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
24811 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
24812 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
24813 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
24814 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
24815 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
24816 | #define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
24817 | //BIF_CFG_DEV0_RC0_PREF_BASE_UPPER |
24818 | #define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
24819 | #define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
24820 | //BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER |
24821 | #define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
24822 | #define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
24823 | //BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI |
24824 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
24825 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
24826 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
24827 | #define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
24828 | //BIF_CFG_DEV0_RC0_CAP_PTR |
24829 | #define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
24830 | #define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK 0xFFL |
24831 | //BIF_CFG_DEV0_RC0_ROM_BASE_ADDR |
24832 | #define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
24833 | #define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
24834 | //BIF_CFG_DEV0_RC0_INTERRUPT_LINE |
24835 | #define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
24836 | #define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
24837 | //BIF_CFG_DEV0_RC0_INTERRUPT_PIN |
24838 | #define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
24839 | #define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
24840 | //BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL |
24841 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
24842 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
24843 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
24844 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
24845 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
24846 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
24847 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
24848 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
24849 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 |
24850 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 |
24851 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa |
24852 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb |
24853 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
24854 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
24855 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
24856 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
24857 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
24858 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
24859 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
24860 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
24861 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L |
24862 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L |
24863 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L |
24864 | #define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L |
24865 | //BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL |
24866 | #define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
24867 | #define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
24868 | //BIF_CFG_DEV0_RC0_PMI_CAP_LIST |
24869 | #define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
24870 | #define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
24871 | #define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
24872 | #define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
24873 | //BIF_CFG_DEV0_RC0_PMI_CAP |
24874 | #define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT 0x0 |
24875 | #define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
24876 | #define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
24877 | #define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
24878 | #define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
24879 | #define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
24880 | #define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
24881 | #define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
24882 | #define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK 0x0007L |
24883 | #define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
24884 | #define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
24885 | #define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
24886 | #define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
24887 | #define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
24888 | #define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
24889 | #define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
24890 | //BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL |
24891 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
24892 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
24893 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
24894 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
24895 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
24896 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
24897 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
24898 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
24899 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
24900 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
24901 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
24902 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
24903 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
24904 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
24905 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
24906 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
24907 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
24908 | #define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
24909 | //BIF_CFG_DEV0_RC0_PCIE_CAP_LIST |
24910 | #define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
24911 | #define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
24912 | #define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
24913 | #define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
24914 | //BIF_CFG_DEV0_RC0_PCIE_CAP |
24915 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT 0x0 |
24916 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
24917 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
24918 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
24919 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK 0x000FL |
24920 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
24921 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
24922 | #define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
24923 | //BIF_CFG_DEV0_RC0_DEVICE_CAP |
24924 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
24925 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
24926 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
24927 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
24928 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
24929 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
24930 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
24931 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
24932 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
24933 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
24934 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
24935 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
24936 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
24937 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
24938 | //BIF_CFG_DEV0_RC0_DEVICE_CNTL |
24939 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
24940 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
24941 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
24942 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
24943 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
24944 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
24945 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
24946 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
24947 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
24948 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
24949 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
24950 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
24951 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
24952 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
24953 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
24954 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
24955 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
24956 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
24957 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
24958 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
24959 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
24960 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
24961 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
24962 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
24963 | //BIF_CFG_DEV0_RC0_DEVICE_STATUS |
24964 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
24965 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
24966 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
24967 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
24968 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
24969 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
24970 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
24971 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
24972 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
24973 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
24974 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
24975 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
24976 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
24977 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
24978 | //BIF_CFG_DEV0_RC0_LINK_CAP |
24979 | #define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
24980 | #define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
24981 | #define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
24982 | #define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
24983 | #define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
24984 | #define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
24985 | #define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
24986 | #define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
24987 | #define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
24988 | #define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
24989 | #define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
24990 | #define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
24991 | #define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
24992 | #define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
24993 | #define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
24994 | #define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
24995 | #define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
24996 | #define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
24997 | #define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
24998 | #define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
24999 | #define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
25000 | #define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
25001 | //BIF_CFG_DEV0_RC0_LINK_CNTL |
25002 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
25003 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
25004 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
25005 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
25006 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
25007 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
25008 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
25009 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
25010 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
25011 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
25012 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
25013 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
25014 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
25015 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
25016 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
25017 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
25018 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
25019 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
25020 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
25021 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
25022 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
25023 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
25024 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
25025 | #define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
25026 | //BIF_CFG_DEV0_RC0_LINK_STATUS |
25027 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
25028 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
25029 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
25030 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
25031 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
25032 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
25033 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
25034 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
25035 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
25036 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
25037 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
25038 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
25039 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
25040 | #define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
25041 | //BIF_CFG_DEV0_RC0_SLOT_CAP |
25042 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
25043 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
25044 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
25045 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
25046 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
25047 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
25048 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
25049 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
25050 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
25051 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
25052 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
25053 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
25054 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
25055 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
25056 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
25057 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
25058 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
25059 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
25060 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
25061 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
25062 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
25063 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
25064 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
25065 | #define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
25066 | //BIF_CFG_DEV0_RC0_SLOT_CNTL |
25067 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
25068 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
25069 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
25070 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
25071 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
25072 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
25073 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
25074 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
25075 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
25076 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
25077 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
25078 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
25079 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
25080 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
25081 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
25082 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
25083 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
25084 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
25085 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
25086 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
25087 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
25088 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
25089 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
25090 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
25091 | //BIF_CFG_DEV0_RC0_SLOT_STATUS |
25092 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
25093 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
25094 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
25095 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
25096 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
25097 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
25098 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
25099 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
25100 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
25101 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
25102 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
25103 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
25104 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
25105 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
25106 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
25107 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
25108 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
25109 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
25110 | //BIF_CFG_DEV0_RC0_ROOT_CNTL |
25111 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
25112 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
25113 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
25114 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
25115 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
25116 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
25117 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
25118 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
25119 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
25120 | #define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
25121 | //BIF_CFG_DEV0_RC0_ROOT_CAP |
25122 | #define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
25123 | #define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
25124 | //BIF_CFG_DEV0_RC0_ROOT_STATUS |
25125 | #define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
25126 | #define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
25127 | #define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
25128 | #define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
25129 | #define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
25130 | #define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
25131 | //BIF_CFG_DEV0_RC0_DEVICE_CAP2 |
25132 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
25133 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
25134 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
25135 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
25136 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
25137 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
25138 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
25139 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
25140 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
25141 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
25142 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
25143 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
25144 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
25145 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
25146 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
25147 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
25148 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
25149 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
25150 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
25151 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
25152 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
25153 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
25154 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
25155 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
25156 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
25157 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
25158 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
25159 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
25160 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
25161 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
25162 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
25163 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
25164 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
25165 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
25166 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
25167 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
25168 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
25169 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
25170 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
25171 | #define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
25172 | //BIF_CFG_DEV0_RC0_DEVICE_CNTL2 |
25173 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
25174 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
25175 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
25176 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
25177 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
25178 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
25179 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
25180 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
25181 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
25182 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
25183 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
25184 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
25185 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
25186 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
25187 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
25188 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
25189 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
25190 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
25191 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
25192 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
25193 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
25194 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
25195 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
25196 | #define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
25197 | //BIF_CFG_DEV0_RC0_DEVICE_STATUS2 |
25198 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
25199 | #define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
25200 | //BIF_CFG_DEV0_RC0_LINK_CAP2 |
25201 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
25202 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
25203 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
25204 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
25205 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
25206 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
25207 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
25208 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
25209 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
25210 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
25211 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
25212 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
25213 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
25214 | #define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
25215 | //BIF_CFG_DEV0_RC0_LINK_CNTL2 |
25216 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
25217 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
25218 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
25219 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
25220 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
25221 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
25222 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
25223 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
25224 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
25225 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
25226 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
25227 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
25228 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
25229 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
25230 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
25231 | #define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
25232 | //BIF_CFG_DEV0_RC0_LINK_STATUS2 |
25233 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
25234 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
25235 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
25236 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
25237 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
25238 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
25239 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
25240 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
25241 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
25242 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
25243 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
25244 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
25245 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
25246 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
25247 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
25248 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
25249 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
25250 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
25251 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
25252 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
25253 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
25254 | #define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
25255 | //BIF_CFG_DEV0_RC0_SLOT_CAP2 |
25256 | #define BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
25257 | #define BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
25258 | //BIF_CFG_DEV0_RC0_SLOT_CNTL2 |
25259 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
25260 | #define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
25261 | //BIF_CFG_DEV0_RC0_SLOT_STATUS2 |
25262 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
25263 | #define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
25264 | //BIF_CFG_DEV0_RC0_MSI_CAP_LIST |
25265 | #define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
25266 | #define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
25267 | #define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
25268 | #define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
25269 | //BIF_CFG_DEV0_RC0_MSI_MSG_CNTL |
25270 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
25271 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
25272 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
25273 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
25274 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
25275 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
25276 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
25277 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
25278 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
25279 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
25280 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
25281 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
25282 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
25283 | #define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
25284 | //BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO |
25285 | #define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
25286 | #define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
25287 | //BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI |
25288 | #define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
25289 | #define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
25290 | //BIF_CFG_DEV0_RC0_MSI_MSG_DATA |
25291 | #define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
25292 | #define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
25293 | //BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA |
25294 | #define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
25295 | #define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
25296 | //BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 |
25297 | #define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
25298 | #define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
25299 | //BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 |
25300 | #define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
25301 | #define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
25302 | //BIF_CFG_DEV0_RC0_SSID_CAP_LIST |
25303 | #define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
25304 | #define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
25305 | #define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
25306 | #define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
25307 | //BIF_CFG_DEV0_RC0_SSID_CAP |
25308 | #define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
25309 | #define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
25310 | #define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
25311 | #define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
25312 | //BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST |
25313 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
25314 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
25315 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
25316 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
25317 | //BIF_CFG_DEV0_RC0_MSI_MAP_CAP |
25318 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN__SHIFT 0x0 |
25319 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
25320 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
25321 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN_MASK 0x0001L |
25322 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD_MASK 0x0002L |
25323 | #define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
25324 | //BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
25325 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
25326 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
25327 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
25328 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
25329 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
25330 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
25331 | //BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR |
25332 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
25333 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
25334 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
25335 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
25336 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
25337 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
25338 | //BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 |
25339 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
25340 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
25341 | //BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 |
25342 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
25343 | #define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
25344 | //BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST |
25345 | #define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
25346 | #define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
25347 | #define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
25348 | #define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
25349 | #define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
25350 | #define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
25351 | //BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 |
25352 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
25353 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
25354 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
25355 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
25356 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
25357 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
25358 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
25359 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
25360 | //BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 |
25361 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
25362 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
25363 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
25364 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
25365 | //BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL |
25366 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
25367 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
25368 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
25369 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
25370 | //BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS |
25371 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
25372 | #define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
25373 | //BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP |
25374 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
25375 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
25376 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
25377 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
25378 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
25379 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
25380 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
25381 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
25382 | //BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL |
25383 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
25384 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
25385 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
25386 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
25387 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
25388 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
25389 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
25390 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
25391 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
25392 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
25393 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
25394 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
25395 | //BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS |
25396 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
25397 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
25398 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
25399 | #define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
25400 | //BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP |
25401 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
25402 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
25403 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
25404 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
25405 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
25406 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
25407 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
25408 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
25409 | //BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL |
25410 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
25411 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
25412 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
25413 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
25414 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
25415 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
25416 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
25417 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
25418 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
25419 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
25420 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
25421 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
25422 | //BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS |
25423 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
25424 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
25425 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
25426 | #define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
25427 | //BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
25428 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
25429 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
25430 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
25431 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
25432 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
25433 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
25434 | //BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 |
25435 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
25436 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
25437 | //BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 |
25438 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
25439 | #define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
25440 | //BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
25441 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
25442 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
25443 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
25444 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
25445 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
25446 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
25447 | //BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS |
25448 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
25449 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
25450 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
25451 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
25452 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
25453 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
25454 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
25455 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
25456 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
25457 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
25458 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
25459 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
25460 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
25461 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
25462 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
25463 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
25464 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
25465 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
25466 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
25467 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
25468 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
25469 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
25470 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
25471 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
25472 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
25473 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
25474 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
25475 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
25476 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
25477 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
25478 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
25479 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
25480 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
25481 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
25482 | //BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK |
25483 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
25484 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
25485 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
25486 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
25487 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
25488 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
25489 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
25490 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
25491 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
25492 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
25493 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
25494 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
25495 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
25496 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
25497 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
25498 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
25499 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
25500 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
25501 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
25502 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
25503 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
25504 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
25505 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
25506 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
25507 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
25508 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
25509 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
25510 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
25511 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
25512 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
25513 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
25514 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
25515 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
25516 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
25517 | //BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY |
25518 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
25519 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
25520 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
25521 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
25522 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
25523 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
25524 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
25525 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
25526 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
25527 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
25528 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
25529 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
25530 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
25531 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
25532 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
25533 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
25534 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
25535 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
25536 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
25537 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
25538 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
25539 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
25540 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
25541 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
25542 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
25543 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
25544 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
25545 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
25546 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
25547 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
25548 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
25549 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
25550 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
25551 | #define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
25552 | //BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS |
25553 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
25554 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
25555 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
25556 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
25557 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
25558 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
25559 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
25560 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
25561 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
25562 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
25563 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
25564 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
25565 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
25566 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
25567 | //BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK |
25568 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
25569 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
25570 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
25571 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
25572 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
25573 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
25574 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
25575 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
25576 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
25577 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
25578 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
25579 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
25580 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
25581 | #define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
25582 | //BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL |
25583 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
25584 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
25585 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
25586 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
25587 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
25588 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
25589 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
25590 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
25591 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
25592 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
25593 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
25594 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
25595 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
25596 | #define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
25597 | //BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 |
25598 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
25599 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
25600 | //BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 |
25601 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
25602 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
25603 | //BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 |
25604 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
25605 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
25606 | //BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 |
25607 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
25608 | #define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
25609 | //BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD |
25610 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
25611 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
25612 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
25613 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
25614 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
25615 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
25616 | //BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS |
25617 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
25618 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
25619 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
25620 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
25621 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
25622 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
25623 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
25624 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
25625 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
25626 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
25627 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
25628 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
25629 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
25630 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
25631 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
25632 | #define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
25633 | //BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID |
25634 | #define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
25635 | #define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
25636 | #define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
25637 | #define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
25638 | //BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 |
25639 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
25640 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
25641 | //BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 |
25642 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
25643 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
25644 | //BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 |
25645 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
25646 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
25647 | //BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 |
25648 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
25649 | #define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
25650 | //BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST |
25651 | #define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
25652 | #define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
25653 | #define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
25654 | #define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
25655 | #define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
25656 | #define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
25657 | //BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 |
25658 | #define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
25659 | #define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
25660 | #define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
25661 | #define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
25662 | #define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
25663 | #define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
25664 | //BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS |
25665 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
25666 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
25667 | //BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL |
25668 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25669 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25670 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25671 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25672 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25673 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25674 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25675 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25676 | //BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL |
25677 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25678 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25679 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25680 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25681 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25682 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25683 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25684 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25685 | //BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL |
25686 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25687 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25688 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25689 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25690 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25691 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25692 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25693 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25694 | //BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL |
25695 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25696 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25697 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25698 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25699 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25700 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25701 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25702 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25703 | //BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL |
25704 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25705 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25706 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25707 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25708 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25709 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25710 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25711 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25712 | //BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL |
25713 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25714 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25715 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25716 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25717 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25718 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25719 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25720 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25721 | //BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL |
25722 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25723 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25724 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25725 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25726 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25727 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25728 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25729 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25730 | //BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL |
25731 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25732 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25733 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25734 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25735 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25736 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25737 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25738 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25739 | //BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL |
25740 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25741 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25742 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25743 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25744 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25745 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25746 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25747 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25748 | //BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL |
25749 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25750 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25751 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25752 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25753 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25754 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25755 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25756 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25757 | //BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL |
25758 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25759 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25760 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25761 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25762 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25763 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25764 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25765 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25766 | //BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL |
25767 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25768 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25769 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25770 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25771 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25772 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25773 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25774 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25775 | //BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL |
25776 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25777 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25778 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25779 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25780 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25781 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25782 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25783 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25784 | //BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL |
25785 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25786 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25787 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25788 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25789 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25790 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25791 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25792 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25793 | //BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL |
25794 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25795 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25796 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25797 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25798 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25799 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25800 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25801 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25802 | //BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL |
25803 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
25804 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
25805 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
25806 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
25807 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
25808 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
25809 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
25810 | #define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
25811 | //BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST |
25812 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
25813 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
25814 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
25815 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
25816 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
25817 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
25818 | //BIF_CFG_DEV0_RC0_PCIE_ACS_CAP |
25819 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
25820 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
25821 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
25822 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
25823 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
25824 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
25825 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
25826 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
25827 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
25828 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
25829 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
25830 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
25831 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
25832 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
25833 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
25834 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
25835 | //BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL |
25836 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
25837 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
25838 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
25839 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
25840 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
25841 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
25842 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
25843 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
25844 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
25845 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
25846 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
25847 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
25848 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
25849 | #define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
25850 | //BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST |
25851 | #define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
25852 | #define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
25853 | #define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
25854 | #define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
25855 | #define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
25856 | #define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
25857 | //BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP |
25858 | #define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
25859 | #define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
25860 | #define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
25861 | #define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
25862 | //BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS |
25863 | #define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
25864 | #define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
25865 | #define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
25866 | #define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
25867 | //BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST |
25868 | #define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
25869 | #define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
25870 | #define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
25871 | #define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
25872 | #define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
25873 | #define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
25874 | //BIF_CFG_DEV0_RC0_LINK_CAP_16GT |
25875 | #define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
25876 | #define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
25877 | //BIF_CFG_DEV0_RC0_LINK_CNTL_16GT |
25878 | #define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
25879 | #define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
25880 | //BIF_CFG_DEV0_RC0_LINK_STATUS_16GT |
25881 | #define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
25882 | #define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
25883 | #define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
25884 | #define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
25885 | #define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
25886 | #define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
25887 | #define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
25888 | #define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
25889 | #define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
25890 | #define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
25891 | //BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT |
25892 | #define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
25893 | #define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
25894 | //BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT |
25895 | #define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
25896 | #define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
25897 | //BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT |
25898 | #define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
25899 | #define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
25900 | //BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT |
25901 | #define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25902 | #define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
25903 | #define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
25904 | #define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
25905 | //BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT |
25906 | #define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25907 | #define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
25908 | #define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
25909 | #define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
25910 | //BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT |
25911 | #define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25912 | #define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
25913 | #define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
25914 | #define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
25915 | //BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT |
25916 | #define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25917 | #define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
25918 | #define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
25919 | #define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
25920 | //BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT |
25921 | #define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25922 | #define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
25923 | #define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
25924 | #define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
25925 | //BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT |
25926 | #define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25927 | #define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
25928 | #define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
25929 | #define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
25930 | //BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT |
25931 | #define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25932 | #define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
25933 | #define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
25934 | #define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
25935 | //BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT |
25936 | #define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25937 | #define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
25938 | #define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
25939 | #define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
25940 | //BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT |
25941 | #define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25942 | #define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
25943 | #define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
25944 | #define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
25945 | //BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT |
25946 | #define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25947 | #define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
25948 | #define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
25949 | #define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
25950 | //BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT |
25951 | #define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25952 | #define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
25953 | #define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
25954 | #define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
25955 | //BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT |
25956 | #define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25957 | #define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
25958 | #define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
25959 | #define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
25960 | //BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT |
25961 | #define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25962 | #define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
25963 | #define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
25964 | #define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
25965 | //BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT |
25966 | #define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25967 | #define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
25968 | #define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
25969 | #define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
25970 | //BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT |
25971 | #define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25972 | #define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
25973 | #define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
25974 | #define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
25975 | //BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT |
25976 | #define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
25977 | #define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
25978 | #define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
25979 | #define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
25980 | //BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST |
25981 | #define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
25982 | #define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
25983 | #define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
25984 | #define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
25985 | #define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
25986 | #define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
25987 | //BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP |
25988 | #define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
25989 | #define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
25990 | //BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS |
25991 | #define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
25992 | #define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
25993 | #define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
25994 | #define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
25995 | //BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL |
25996 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
25997 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
25998 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
25999 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
26000 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
26001 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
26002 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
26003 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
26004 | //BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS |
26005 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26006 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26007 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
26008 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26009 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26010 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
26011 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
26012 | #define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26013 | //BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL |
26014 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
26015 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
26016 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
26017 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
26018 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
26019 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
26020 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
26021 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
26022 | //BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS |
26023 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26024 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26025 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
26026 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26027 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26028 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
26029 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
26030 | #define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26031 | //BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL |
26032 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
26033 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
26034 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
26035 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
26036 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
26037 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
26038 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
26039 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
26040 | //BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS |
26041 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26042 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26043 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
26044 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26045 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26046 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
26047 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
26048 | #define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26049 | //BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL |
26050 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
26051 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
26052 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
26053 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
26054 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
26055 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
26056 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
26057 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
26058 | //BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS |
26059 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26060 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26061 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
26062 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26063 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26064 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
26065 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
26066 | #define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26067 | //BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL |
26068 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
26069 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
26070 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
26071 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
26072 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
26073 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
26074 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
26075 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
26076 | //BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS |
26077 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26078 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26079 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
26080 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26081 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26082 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
26083 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
26084 | #define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26085 | //BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL |
26086 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
26087 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
26088 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
26089 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
26090 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
26091 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
26092 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
26093 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
26094 | //BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS |
26095 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26096 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26097 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
26098 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26099 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26100 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
26101 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
26102 | #define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26103 | //BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL |
26104 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
26105 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
26106 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
26107 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
26108 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
26109 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
26110 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
26111 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
26112 | //BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS |
26113 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26114 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26115 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
26116 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26117 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26118 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
26119 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
26120 | #define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26121 | //BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL |
26122 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
26123 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
26124 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
26125 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
26126 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
26127 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
26128 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
26129 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
26130 | //BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS |
26131 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26132 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26133 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
26134 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26135 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26136 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
26137 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
26138 | #define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26139 | //BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL |
26140 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
26141 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
26142 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
26143 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
26144 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
26145 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
26146 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
26147 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
26148 | //BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS |
26149 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26150 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26151 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
26152 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26153 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26154 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
26155 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
26156 | #define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26157 | //BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL |
26158 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
26159 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
26160 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
26161 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
26162 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
26163 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
26164 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
26165 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
26166 | //BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS |
26167 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26168 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26169 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
26170 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26171 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26172 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
26173 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
26174 | #define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26175 | //BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL |
26176 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
26177 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
26178 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
26179 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
26180 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
26181 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
26182 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
26183 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
26184 | //BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS |
26185 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26186 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26187 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
26188 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26189 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26190 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
26191 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
26192 | #define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26193 | //BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL |
26194 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
26195 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
26196 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
26197 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
26198 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
26199 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
26200 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
26201 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
26202 | //BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS |
26203 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26204 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26205 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
26206 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26207 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26208 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
26209 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
26210 | #define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26211 | //BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL |
26212 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
26213 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
26214 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
26215 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
26216 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
26217 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
26218 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
26219 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
26220 | //BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS |
26221 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26222 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26223 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
26224 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26225 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26226 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
26227 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
26228 | #define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26229 | //BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL |
26230 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
26231 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
26232 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
26233 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
26234 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
26235 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
26236 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
26237 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
26238 | //BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS |
26239 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26240 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26241 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
26242 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26243 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26244 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
26245 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
26246 | #define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26247 | //BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL |
26248 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
26249 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
26250 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
26251 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
26252 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
26253 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
26254 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
26255 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
26256 | //BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS |
26257 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26258 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26259 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
26260 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26261 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26262 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
26263 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
26264 | #define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26265 | //BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL |
26266 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
26267 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
26268 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
26269 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
26270 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
26271 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
26272 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
26273 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
26274 | //BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS |
26275 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
26276 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
26277 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
26278 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
26279 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
26280 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
26281 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
26282 | #define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
26283 | //BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST |
26284 | #define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
26285 | #define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
26286 | #define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
26287 | #define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
26288 | #define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
26289 | #define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
26290 | //BIF_CFG_DEV0_RC0_RTR_DATA1 |
26291 | #define BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
26292 | #define BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
26293 | #define BIF_CFG_DEV0_RC0_RTR_DATA1__VALID__SHIFT 0x1f |
26294 | #define BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
26295 | #define BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
26296 | #define BIF_CFG_DEV0_RC0_RTR_DATA1__VALID_MASK 0x80000000L |
26297 | //BIF_CFG_DEV0_RC0_RTR_DATA2 |
26298 | #define BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
26299 | #define BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
26300 | #define BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
26301 | #define BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
26302 | |
26303 | |
26304 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp |
26305 | //BIF_CFG_DEV0_EPF0_0_VENDOR_ID |
26306 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
26307 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
26308 | //BIF_CFG_DEV0_EPF0_0_DEVICE_ID |
26309 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
26310 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
26311 | //BIF_CFG_DEV0_EPF0_0_COMMAND |
26312 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
26313 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
26314 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
26315 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
26316 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
26317 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
26318 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
26319 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8 |
26320 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
26321 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa |
26322 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
26323 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
26324 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
26325 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
26326 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
26327 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
26328 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L |
26329 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L |
26330 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
26331 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L |
26332 | //BIF_CFG_DEV0_EPF0_0_STATUS |
26333 | #define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
26334 | #define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3 |
26335 | #define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4 |
26336 | #define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
26337 | #define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
26338 | #define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
26339 | #define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
26340 | #define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
26341 | #define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
26342 | #define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
26343 | #define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
26344 | #define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L |
26345 | #define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L |
26346 | #define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK 0x0020L |
26347 | #define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
26348 | #define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
26349 | #define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
26350 | #define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
26351 | #define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
26352 | #define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
26353 | //BIF_CFG_DEV0_EPF0_0_REVISION_ID |
26354 | #define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
26355 | #define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
26356 | #define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
26357 | #define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
26358 | //BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE |
26359 | #define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
26360 | #define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
26361 | //BIF_CFG_DEV0_EPF0_0_SUB_CLASS |
26362 | #define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
26363 | #define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
26364 | //BIF_CFG_DEV0_EPF0_0_BASE_CLASS |
26365 | #define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
26366 | #define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
26367 | //BIF_CFG_DEV0_EPF0_0_CACHE_LINE |
26368 | #define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
26369 | #define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
26370 | //BIF_CFG_DEV0_EPF0_0_LATENCY |
26371 | #define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
26372 | #define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
26373 | //BIF_CFG_DEV0_EPF0_0_HEADER |
26374 | #define 0x0 |
26375 | #define 0x7 |
26376 | #define 0x7FL |
26377 | #define 0x80L |
26378 | //BIF_CFG_DEV0_EPF0_0_BIST |
26379 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT 0x0 |
26380 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT 0x6 |
26381 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT 0x7 |
26382 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK 0x0FL |
26383 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK 0x40L |
26384 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK 0x80L |
26385 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 |
26386 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
26387 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
26388 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 |
26389 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
26390 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
26391 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 |
26392 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
26393 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
26394 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 |
26395 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
26396 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
26397 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 |
26398 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
26399 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
26400 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 |
26401 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
26402 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
26403 | //BIF_CFG_DEV0_EPF0_0_ADAPTER_ID |
26404 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
26405 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
26406 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
26407 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
26408 | //BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR |
26409 | #define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
26410 | #define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
26411 | //BIF_CFG_DEV0_EPF0_0_CAP_PTR |
26412 | #define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
26413 | #define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
26414 | //BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE |
26415 | #define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
26416 | #define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
26417 | //BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN |
26418 | #define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
26419 | #define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
26420 | //BIF_CFG_DEV0_EPF0_0_MIN_GRANT |
26421 | #define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
26422 | #define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
26423 | //BIF_CFG_DEV0_EPF0_0_MAX_LATENCY |
26424 | #define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
26425 | #define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
26426 | //BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST |
26427 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
26428 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
26429 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
26430 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
26431 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
26432 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
26433 | //BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W |
26434 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
26435 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
26436 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
26437 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
26438 | //BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST |
26439 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
26440 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
26441 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
26442 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
26443 | //BIF_CFG_DEV0_EPF0_0_PMI_CAP |
26444 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0 |
26445 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
26446 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
26447 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
26448 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
26449 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
26450 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
26451 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
26452 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L |
26453 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
26454 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
26455 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
26456 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
26457 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
26458 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
26459 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
26460 | //BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL |
26461 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
26462 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
26463 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
26464 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
26465 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
26466 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
26467 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
26468 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
26469 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
26470 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
26471 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
26472 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
26473 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
26474 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
26475 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
26476 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
26477 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
26478 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
26479 | //BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST |
26480 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
26481 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
26482 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
26483 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
26484 | //BIF_CFG_DEV0_EPF0_0_PCIE_CAP |
26485 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0 |
26486 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
26487 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
26488 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
26489 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL |
26490 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
26491 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
26492 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
26493 | //BIF_CFG_DEV0_EPF0_0_DEVICE_CAP |
26494 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
26495 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
26496 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
26497 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
26498 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
26499 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
26500 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
26501 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
26502 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
26503 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
26504 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
26505 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
26506 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
26507 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
26508 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
26509 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
26510 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
26511 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
26512 | //BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL |
26513 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
26514 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
26515 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
26516 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
26517 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
26518 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
26519 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
26520 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
26521 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
26522 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
26523 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
26524 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
26525 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
26526 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
26527 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
26528 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
26529 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
26530 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
26531 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
26532 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
26533 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
26534 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
26535 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
26536 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
26537 | //BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS |
26538 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
26539 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
26540 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
26541 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
26542 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
26543 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
26544 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
26545 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
26546 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
26547 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
26548 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
26549 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
26550 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
26551 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
26552 | //BIF_CFG_DEV0_EPF0_0_LINK_CAP |
26553 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
26554 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
26555 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
26556 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
26557 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
26558 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
26559 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
26560 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
26561 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
26562 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
26563 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
26564 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
26565 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
26566 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
26567 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
26568 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
26569 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
26570 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
26571 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
26572 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
26573 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
26574 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
26575 | //BIF_CFG_DEV0_EPF0_0_LINK_CNTL |
26576 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
26577 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
26578 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
26579 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
26580 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
26581 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
26582 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
26583 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
26584 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
26585 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
26586 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
26587 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
26588 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
26589 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
26590 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
26591 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
26592 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
26593 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
26594 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
26595 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
26596 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
26597 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
26598 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
26599 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
26600 | //BIF_CFG_DEV0_EPF0_0_LINK_STATUS |
26601 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
26602 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
26603 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
26604 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
26605 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
26606 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
26607 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
26608 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
26609 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
26610 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
26611 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
26612 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
26613 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
26614 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
26615 | //BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 |
26616 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
26617 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
26618 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
26619 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
26620 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
26621 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
26622 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
26623 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
26624 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
26625 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
26626 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
26627 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
26628 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
26629 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
26630 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
26631 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
26632 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
26633 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
26634 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
26635 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
26636 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
26637 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
26638 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
26639 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
26640 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
26641 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
26642 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
26643 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
26644 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
26645 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
26646 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
26647 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
26648 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
26649 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
26650 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
26651 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
26652 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
26653 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
26654 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
26655 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
26656 | //BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 |
26657 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
26658 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
26659 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
26660 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
26661 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
26662 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
26663 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
26664 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
26665 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
26666 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
26667 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
26668 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
26669 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
26670 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
26671 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
26672 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
26673 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
26674 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
26675 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
26676 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
26677 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
26678 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
26679 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
26680 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
26681 | //BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 |
26682 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
26683 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
26684 | //BIF_CFG_DEV0_EPF0_0_LINK_CAP2 |
26685 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
26686 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
26687 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
26688 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
26689 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
26690 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
26691 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
26692 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
26693 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
26694 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
26695 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
26696 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
26697 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
26698 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
26699 | //BIF_CFG_DEV0_EPF0_0_LINK_CNTL2 |
26700 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
26701 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
26702 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
26703 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
26704 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
26705 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
26706 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
26707 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
26708 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
26709 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
26710 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
26711 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
26712 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
26713 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
26714 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
26715 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
26716 | //BIF_CFG_DEV0_EPF0_0_LINK_STATUS2 |
26717 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
26718 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
26719 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
26720 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
26721 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
26722 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
26723 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
26724 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
26725 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
26726 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
26727 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
26728 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
26729 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
26730 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
26731 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
26732 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
26733 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
26734 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
26735 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
26736 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
26737 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
26738 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
26739 | //BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST |
26740 | #define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
26741 | #define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
26742 | #define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
26743 | #define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
26744 | //BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL |
26745 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
26746 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
26747 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
26748 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
26749 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
26750 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
26751 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
26752 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
26753 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
26754 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
26755 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
26756 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
26757 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
26758 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
26759 | //BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO |
26760 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
26761 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
26762 | //BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI |
26763 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
26764 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
26765 | //BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA |
26766 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
26767 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
26768 | //BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA |
26769 | #define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
26770 | #define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
26771 | //BIF_CFG_DEV0_EPF0_0_MSI_MASK |
26772 | #define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
26773 | #define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
26774 | //BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 |
26775 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
26776 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
26777 | //BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 |
26778 | #define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
26779 | #define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
26780 | //BIF_CFG_DEV0_EPF0_0_MSI_MASK_64 |
26781 | #define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
26782 | #define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
26783 | //BIF_CFG_DEV0_EPF0_0_MSI_PENDING |
26784 | #define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
26785 | #define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
26786 | //BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 |
26787 | #define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
26788 | #define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
26789 | //BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST |
26790 | #define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
26791 | #define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
26792 | #define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
26793 | #define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
26794 | //BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL |
26795 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
26796 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
26797 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
26798 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
26799 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
26800 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
26801 | //BIF_CFG_DEV0_EPF0_0_MSIX_TABLE |
26802 | #define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
26803 | #define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
26804 | #define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
26805 | #define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
26806 | //BIF_CFG_DEV0_EPF0_0_MSIX_PBA |
26807 | #define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
26808 | #define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
26809 | #define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
26810 | #define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
26811 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
26812 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
26813 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
26814 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
26815 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
26816 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
26817 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
26818 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR |
26819 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
26820 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
26821 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
26822 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
26823 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
26824 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
26825 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 |
26826 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
26827 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
26828 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 |
26829 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
26830 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
26831 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST |
26832 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
26833 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
26834 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
26835 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
26836 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
26837 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
26838 | //BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 |
26839 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
26840 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
26841 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
26842 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
26843 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
26844 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
26845 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
26846 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
26847 | //BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 |
26848 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
26849 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
26850 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
26851 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
26852 | //BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL |
26853 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
26854 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
26855 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
26856 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
26857 | //BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS |
26858 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
26859 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
26860 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP |
26861 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
26862 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
26863 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
26864 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
26865 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
26866 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
26867 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
26868 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
26869 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL |
26870 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
26871 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
26872 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
26873 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
26874 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
26875 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
26876 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
26877 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
26878 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
26879 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
26880 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
26881 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
26882 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS |
26883 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
26884 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
26885 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
26886 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
26887 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP |
26888 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
26889 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
26890 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
26891 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
26892 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
26893 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
26894 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
26895 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
26896 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL |
26897 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
26898 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
26899 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
26900 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
26901 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
26902 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
26903 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
26904 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
26905 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
26906 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
26907 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
26908 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
26909 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS |
26910 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
26911 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
26912 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
26913 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
26914 | //BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
26915 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
26916 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
26917 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
26918 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
26919 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
26920 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
26921 | //BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 |
26922 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
26923 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
26924 | //BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 |
26925 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
26926 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
26927 | //BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
26928 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
26929 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
26930 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
26931 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
26932 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
26933 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
26934 | //BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS |
26935 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
26936 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
26937 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
26938 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
26939 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
26940 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
26941 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
26942 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
26943 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
26944 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
26945 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
26946 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
26947 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
26948 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
26949 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
26950 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
26951 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
26952 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
26953 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
26954 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
26955 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
26956 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
26957 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
26958 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
26959 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
26960 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
26961 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
26962 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
26963 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
26964 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
26965 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
26966 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
26967 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
26968 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
26969 | //BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK |
26970 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
26971 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
26972 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
26973 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
26974 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
26975 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
26976 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
26977 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
26978 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
26979 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
26980 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
26981 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
26982 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
26983 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
26984 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
26985 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
26986 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
26987 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
26988 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
26989 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
26990 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
26991 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
26992 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
26993 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
26994 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
26995 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
26996 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
26997 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
26998 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
26999 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
27000 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
27001 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
27002 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
27003 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
27004 | //BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY |
27005 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
27006 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
27007 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
27008 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
27009 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
27010 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
27011 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
27012 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
27013 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
27014 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
27015 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
27016 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
27017 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
27018 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
27019 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
27020 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
27021 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
27022 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
27023 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
27024 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
27025 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
27026 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
27027 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
27028 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
27029 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
27030 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
27031 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
27032 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
27033 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
27034 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
27035 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
27036 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
27037 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
27038 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
27039 | //BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS |
27040 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
27041 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
27042 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
27043 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
27044 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
27045 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
27046 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
27047 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
27048 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
27049 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
27050 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
27051 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
27052 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
27053 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
27054 | //BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK |
27055 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
27056 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
27057 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
27058 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
27059 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
27060 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
27061 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
27062 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
27063 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
27064 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
27065 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
27066 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
27067 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
27068 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
27069 | //BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL |
27070 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
27071 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
27072 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
27073 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
27074 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
27075 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
27076 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
27077 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
27078 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
27079 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
27080 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
27081 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
27082 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
27083 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
27084 | //BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 |
27085 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
27086 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
27087 | //BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 |
27088 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
27089 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
27090 | //BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 |
27091 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
27092 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
27093 | //BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 |
27094 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
27095 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
27096 | //BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 |
27097 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
27098 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
27099 | //BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 |
27100 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
27101 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
27102 | //BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 |
27103 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
27104 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
27105 | //BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 |
27106 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
27107 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
27108 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST |
27109 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27110 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27111 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27112 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27113 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27114 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27115 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP |
27116 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
27117 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
27118 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL |
27119 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
27120 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
27121 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
27122 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
27123 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
27124 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
27125 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
27126 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
27127 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP |
27128 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
27129 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
27130 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL |
27131 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
27132 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
27133 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
27134 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
27135 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
27136 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
27137 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
27138 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
27139 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP |
27140 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
27141 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
27142 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL |
27143 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
27144 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
27145 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
27146 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
27147 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
27148 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
27149 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
27150 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
27151 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP |
27152 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
27153 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
27154 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL |
27155 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
27156 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
27157 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
27158 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
27159 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
27160 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
27161 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
27162 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
27163 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP |
27164 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
27165 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
27166 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL |
27167 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
27168 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
27169 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
27170 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
27171 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
27172 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
27173 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
27174 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
27175 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP |
27176 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
27177 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
27178 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL |
27179 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
27180 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
27181 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
27182 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
27183 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
27184 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
27185 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
27186 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
27187 | //BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
27188 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27189 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27190 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27191 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27192 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27193 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27194 | //BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT |
27195 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
27196 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
27197 | //BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA |
27198 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
27199 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
27200 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
27201 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
27202 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
27203 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
27204 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
27205 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
27206 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
27207 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
27208 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
27209 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
27210 | //BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP |
27211 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
27212 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
27213 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST |
27214 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27215 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27216 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27217 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27218 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27219 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27220 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP |
27221 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
27222 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
27223 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
27224 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
27225 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
27226 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
27227 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
27228 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
27229 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
27230 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
27231 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR |
27232 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
27233 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
27234 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS |
27235 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
27236 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
27237 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
27238 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
27239 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL |
27240 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
27241 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
27242 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
27243 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
27244 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
27245 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
27246 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
27247 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
27248 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
27249 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
27250 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
27251 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
27252 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
27253 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
27254 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
27255 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
27256 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
27257 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
27258 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
27259 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
27260 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
27261 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
27262 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
27263 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
27264 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
27265 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
27266 | //BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST |
27267 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27268 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27269 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27270 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27271 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27272 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27273 | //BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 |
27274 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
27275 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
27276 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
27277 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
27278 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
27279 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
27280 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS |
27281 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
27282 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
27283 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL |
27284 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27285 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27286 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27287 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27288 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27289 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27290 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27291 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27292 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL |
27293 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27294 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27295 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27296 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27297 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27298 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27299 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27300 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27301 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL |
27302 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27303 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27304 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27305 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27306 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27307 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27308 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27309 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27310 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL |
27311 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27312 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27313 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27314 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27315 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27316 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27317 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27318 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27319 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL |
27320 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27321 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27322 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27323 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27324 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27325 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27326 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27327 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27328 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL |
27329 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27330 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27331 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27332 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27333 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27334 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27335 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27336 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27337 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL |
27338 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27339 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27340 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27341 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27342 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27343 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27344 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27345 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27346 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL |
27347 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27348 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27349 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27350 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27351 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27352 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27353 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27354 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27355 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL |
27356 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27357 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27358 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27359 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27360 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27361 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27362 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27363 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27364 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL |
27365 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27366 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27367 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27368 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27369 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27370 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27371 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27372 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27373 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL |
27374 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27375 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27376 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27377 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27378 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27379 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27380 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27381 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27382 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL |
27383 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27384 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27385 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27386 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27387 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27388 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27389 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27390 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27391 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL |
27392 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27393 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27394 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27395 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27396 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27397 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27398 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27399 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27400 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL |
27401 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27402 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27403 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27404 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27405 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27406 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27407 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27408 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27409 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL |
27410 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27411 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27412 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27413 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27414 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27415 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27416 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27417 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27418 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL |
27419 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
27420 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
27421 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
27422 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
27423 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
27424 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
27425 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
27426 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
27427 | //BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST |
27428 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27429 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27430 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27431 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27432 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27433 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27434 | //BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP |
27435 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
27436 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
27437 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
27438 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
27439 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
27440 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
27441 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
27442 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
27443 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
27444 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
27445 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
27446 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
27447 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
27448 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
27449 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
27450 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
27451 | //BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL |
27452 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
27453 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
27454 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
27455 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
27456 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
27457 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
27458 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
27459 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
27460 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
27461 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
27462 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
27463 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
27464 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
27465 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
27466 | //BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST |
27467 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27468 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27469 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27470 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27471 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27472 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27473 | //BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP |
27474 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
27475 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
27476 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
27477 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 |
27478 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
27479 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
27480 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
27481 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L |
27482 | //BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL |
27483 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
27484 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
27485 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
27486 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
27487 | //BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST |
27488 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27489 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27490 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27491 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27492 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27493 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27494 | //BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL |
27495 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
27496 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
27497 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
27498 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
27499 | //BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS |
27500 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
27501 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
27502 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
27503 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
27504 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
27505 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
27506 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
27507 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
27508 | //BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
27509 | #define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
27510 | #define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
27511 | //BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
27512 | #define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
27513 | #define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
27514 | //BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST |
27515 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27516 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27517 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27518 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27519 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27520 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27521 | //BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP |
27522 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
27523 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
27524 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
27525 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
27526 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
27527 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
27528 | //BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL |
27529 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
27530 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
27531 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
27532 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
27533 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
27534 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
27535 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST |
27536 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27537 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27538 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27539 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27540 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27541 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27542 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP |
27543 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
27544 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
27545 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
27546 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
27547 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
27548 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
27549 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL |
27550 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
27551 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
27552 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
27553 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
27554 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 |
27555 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
27556 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
27557 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
27558 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
27559 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 |
27560 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
27561 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
27562 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 |
27563 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
27564 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
27565 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 |
27566 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
27567 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
27568 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 |
27569 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
27570 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
27571 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 |
27572 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
27573 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
27574 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
27575 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
27576 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
27577 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
27578 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
27579 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
27580 | //BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST |
27581 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27582 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27583 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27584 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27585 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27586 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27587 | //BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP |
27588 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
27589 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
27590 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
27591 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
27592 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
27593 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
27594 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
27595 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
27596 | //BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST |
27597 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27598 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27599 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27600 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27601 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27602 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27603 | //BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP |
27604 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
27605 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
27606 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
27607 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
27608 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
27609 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
27610 | //BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL |
27611 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
27612 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
27613 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
27614 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
27615 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
27616 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
27617 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST |
27618 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27619 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27620 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27621 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27622 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27623 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27624 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP |
27625 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
27626 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 |
27627 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
27628 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L |
27629 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL |
27630 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
27631 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
27632 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
27633 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 |
27634 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
27635 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
27636 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
27637 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L |
27638 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS |
27639 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS |
27640 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
27641 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
27642 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS |
27643 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
27644 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
27645 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS |
27646 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
27647 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
27648 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK |
27649 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
27650 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL |
27651 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET |
27652 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
27653 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
27654 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE |
27655 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
27656 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
27657 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID |
27658 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
27659 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
27660 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
27661 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
27662 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
27663 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
27664 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
27665 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
27666 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 |
27667 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
27668 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
27669 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 |
27670 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
27671 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
27672 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 |
27673 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
27674 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
27675 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 |
27676 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
27677 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
27678 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 |
27679 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
27680 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
27681 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 |
27682 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
27683 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
27684 | //BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST |
27685 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27686 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27687 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27688 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27689 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27690 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27691 | //BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP |
27692 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
27693 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
27694 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
27695 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
27696 | //BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS |
27697 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
27698 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
27699 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
27700 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
27701 | //BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST |
27702 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27703 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27704 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27705 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27706 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27707 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27708 | //BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT |
27709 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
27710 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
27711 | //BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT |
27712 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
27713 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
27714 | //BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT |
27715 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
27716 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
27717 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
27718 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
27719 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
27720 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
27721 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
27722 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
27723 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
27724 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
27725 | //BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT |
27726 | #define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
27727 | #define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
27728 | //BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT |
27729 | #define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
27730 | #define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
27731 | //BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT |
27732 | #define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
27733 | #define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
27734 | //BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT |
27735 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27736 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
27737 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
27738 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
27739 | //BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT |
27740 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27741 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
27742 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
27743 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
27744 | //BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT |
27745 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27746 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
27747 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
27748 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
27749 | //BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT |
27750 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27751 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
27752 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
27753 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
27754 | //BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT |
27755 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27756 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
27757 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
27758 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
27759 | //BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT |
27760 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27761 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
27762 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
27763 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
27764 | //BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT |
27765 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27766 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
27767 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
27768 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
27769 | //BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT |
27770 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27771 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
27772 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
27773 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
27774 | //BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT |
27775 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27776 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
27777 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
27778 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
27779 | //BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT |
27780 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27781 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
27782 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
27783 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
27784 | //BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT |
27785 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27786 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
27787 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
27788 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
27789 | //BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT |
27790 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27791 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
27792 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
27793 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
27794 | //BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT |
27795 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27796 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
27797 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
27798 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
27799 | //BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT |
27800 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27801 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
27802 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
27803 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
27804 | //BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT |
27805 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27806 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
27807 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
27808 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
27809 | //BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT |
27810 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
27811 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
27812 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
27813 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
27814 | //BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST |
27815 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
27816 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
27817 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
27818 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
27819 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
27820 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
27821 | //BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP |
27822 | #define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
27823 | #define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
27824 | //BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS |
27825 | #define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
27826 | #define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
27827 | #define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
27828 | #define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
27829 | //BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL |
27830 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
27831 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
27832 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
27833 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
27834 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
27835 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
27836 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
27837 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
27838 | //BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS |
27839 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
27840 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
27841 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
27842 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
27843 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
27844 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
27845 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
27846 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
27847 | //BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL |
27848 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
27849 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
27850 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
27851 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
27852 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
27853 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
27854 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
27855 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
27856 | //BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS |
27857 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
27858 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
27859 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
27860 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
27861 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
27862 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
27863 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
27864 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
27865 | //BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL |
27866 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
27867 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
27868 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
27869 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
27870 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
27871 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
27872 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
27873 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
27874 | //BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS |
27875 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
27876 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
27877 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
27878 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
27879 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
27880 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
27881 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
27882 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
27883 | //BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL |
27884 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
27885 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
27886 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
27887 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
27888 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
27889 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
27890 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
27891 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
27892 | //BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS |
27893 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
27894 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
27895 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
27896 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
27897 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
27898 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
27899 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
27900 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
27901 | //BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL |
27902 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
27903 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
27904 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
27905 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
27906 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
27907 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
27908 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
27909 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
27910 | //BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS |
27911 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
27912 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
27913 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
27914 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
27915 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
27916 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
27917 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
27918 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
27919 | //BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL |
27920 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
27921 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
27922 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
27923 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
27924 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
27925 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
27926 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
27927 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
27928 | //BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS |
27929 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
27930 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
27931 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
27932 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
27933 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
27934 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
27935 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
27936 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
27937 | //BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL |
27938 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
27939 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
27940 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
27941 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
27942 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
27943 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
27944 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
27945 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
27946 | //BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS |
27947 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
27948 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
27949 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
27950 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
27951 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
27952 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
27953 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
27954 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
27955 | //BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL |
27956 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
27957 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
27958 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
27959 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
27960 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
27961 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
27962 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
27963 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
27964 | //BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS |
27965 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
27966 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
27967 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
27968 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
27969 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
27970 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
27971 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
27972 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
27973 | //BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL |
27974 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
27975 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
27976 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
27977 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
27978 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
27979 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
27980 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
27981 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
27982 | //BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS |
27983 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
27984 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
27985 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
27986 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
27987 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
27988 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
27989 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
27990 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
27991 | //BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL |
27992 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
27993 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
27994 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
27995 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
27996 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
27997 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
27998 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
27999 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
28000 | //BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS |
28001 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
28002 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
28003 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
28004 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
28005 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
28006 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
28007 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
28008 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
28009 | //BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL |
28010 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
28011 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
28012 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
28013 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
28014 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
28015 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
28016 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
28017 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
28018 | //BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS |
28019 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
28020 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
28021 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
28022 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
28023 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
28024 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
28025 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
28026 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
28027 | //BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL |
28028 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
28029 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
28030 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
28031 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
28032 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
28033 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
28034 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
28035 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
28036 | //BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS |
28037 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
28038 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
28039 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
28040 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
28041 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
28042 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
28043 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
28044 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
28045 | //BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL |
28046 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
28047 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
28048 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
28049 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
28050 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
28051 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
28052 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
28053 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
28054 | //BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS |
28055 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
28056 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
28057 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
28058 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
28059 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
28060 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
28061 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
28062 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
28063 | //BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL |
28064 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
28065 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
28066 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
28067 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
28068 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
28069 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
28070 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
28071 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
28072 | //BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS |
28073 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
28074 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
28075 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
28076 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
28077 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
28078 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
28079 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
28080 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
28081 | //BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL |
28082 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
28083 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
28084 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
28085 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
28086 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
28087 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
28088 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
28089 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
28090 | //BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS |
28091 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
28092 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
28093 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
28094 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
28095 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
28096 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
28097 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
28098 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
28099 | //BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL |
28100 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
28101 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
28102 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
28103 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
28104 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
28105 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
28106 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
28107 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
28108 | //BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS |
28109 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
28110 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
28111 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
28112 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
28113 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
28114 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
28115 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
28116 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
28117 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST |
28118 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
28119 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
28120 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
28121 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
28122 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
28123 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
28124 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP |
28125 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
28126 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
28127 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL |
28128 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
28129 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
28130 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
28131 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
28132 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
28133 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
28134 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
28135 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
28136 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP |
28137 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
28138 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
28139 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL |
28140 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
28141 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
28142 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
28143 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
28144 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
28145 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
28146 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
28147 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
28148 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP |
28149 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
28150 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
28151 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL |
28152 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
28153 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
28154 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
28155 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
28156 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
28157 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
28158 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
28159 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
28160 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP |
28161 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
28162 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
28163 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL |
28164 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
28165 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
28166 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
28167 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
28168 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
28169 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
28170 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
28171 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
28172 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP |
28173 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
28174 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
28175 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL |
28176 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
28177 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
28178 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
28179 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
28180 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
28181 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
28182 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
28183 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
28184 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP |
28185 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
28186 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
28187 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL |
28188 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
28189 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
28190 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
28191 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
28192 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
28193 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
28194 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
28195 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
28196 | //BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST |
28197 | #define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
28198 | #define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
28199 | #define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
28200 | #define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
28201 | #define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
28202 | #define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
28203 | //BIF_CFG_DEV0_EPF0_0_RTR_DATA1 |
28204 | #define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
28205 | #define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
28206 | #define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__VALID__SHIFT 0x1f |
28207 | #define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
28208 | #define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
28209 | #define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__VALID_MASK 0x80000000L |
28210 | //BIF_CFG_DEV0_EPF0_0_RTR_DATA2 |
28211 | #define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
28212 | #define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
28213 | #define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
28214 | #define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
28215 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV |
28216 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
28217 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
28218 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
28219 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL |
28220 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L |
28221 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L |
28222 | |
28223 | |
28224 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp |
28225 | //BIF_CFG_DEV0_EPF1_0_VENDOR_ID |
28226 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
28227 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
28228 | //BIF_CFG_DEV0_EPF1_0_DEVICE_ID |
28229 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
28230 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
28231 | //BIF_CFG_DEV0_EPF1_0_COMMAND |
28232 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
28233 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
28234 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
28235 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
28236 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
28237 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
28238 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
28239 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8 |
28240 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
28241 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa |
28242 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
28243 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
28244 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
28245 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
28246 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
28247 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
28248 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L |
28249 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L |
28250 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
28251 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L |
28252 | //BIF_CFG_DEV0_EPF1_0_STATUS |
28253 | #define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
28254 | #define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3 |
28255 | #define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4 |
28256 | #define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
28257 | #define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
28258 | #define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
28259 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
28260 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
28261 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
28262 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
28263 | #define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
28264 | #define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L |
28265 | #define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L |
28266 | #define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP_MASK 0x0020L |
28267 | #define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
28268 | #define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
28269 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
28270 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
28271 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
28272 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
28273 | //BIF_CFG_DEV0_EPF1_0_REVISION_ID |
28274 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
28275 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
28276 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
28277 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
28278 | //BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE |
28279 | #define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
28280 | #define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
28281 | //BIF_CFG_DEV0_EPF1_0_SUB_CLASS |
28282 | #define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
28283 | #define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
28284 | //BIF_CFG_DEV0_EPF1_0_BASE_CLASS |
28285 | #define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
28286 | #define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
28287 | //BIF_CFG_DEV0_EPF1_0_CACHE_LINE |
28288 | #define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
28289 | #define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
28290 | //BIF_CFG_DEV0_EPF1_0_LATENCY |
28291 | #define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
28292 | #define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
28293 | //BIF_CFG_DEV0_EPF1_0_HEADER |
28294 | #define 0x0 |
28295 | #define 0x7 |
28296 | #define 0x7FL |
28297 | #define 0x80L |
28298 | //BIF_CFG_DEV0_EPF1_0_BIST |
28299 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT 0x0 |
28300 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT 0x6 |
28301 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT 0x7 |
28302 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK 0x0FL |
28303 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK 0x40L |
28304 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK 0x80L |
28305 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 |
28306 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
28307 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
28308 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 |
28309 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
28310 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
28311 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 |
28312 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
28313 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
28314 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 |
28315 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
28316 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
28317 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 |
28318 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
28319 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
28320 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 |
28321 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
28322 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
28323 | //BIF_CFG_DEV0_EPF1_0_ADAPTER_ID |
28324 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
28325 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
28326 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
28327 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
28328 | //BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR |
28329 | #define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
28330 | #define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
28331 | //BIF_CFG_DEV0_EPF1_0_CAP_PTR |
28332 | #define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
28333 | #define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
28334 | //BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE |
28335 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
28336 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
28337 | //BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN |
28338 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
28339 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
28340 | //BIF_CFG_DEV0_EPF1_0_MIN_GRANT |
28341 | #define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
28342 | #define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
28343 | //BIF_CFG_DEV0_EPF1_0_MAX_LATENCY |
28344 | #define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
28345 | #define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
28346 | //BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST |
28347 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
28348 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
28349 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
28350 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
28351 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
28352 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
28353 | //BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W |
28354 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
28355 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
28356 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
28357 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
28358 | //BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST |
28359 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
28360 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
28361 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
28362 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
28363 | //BIF_CFG_DEV0_EPF1_0_PMI_CAP |
28364 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0 |
28365 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
28366 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
28367 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
28368 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
28369 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
28370 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
28371 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
28372 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L |
28373 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
28374 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
28375 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
28376 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
28377 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
28378 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
28379 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
28380 | //BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL |
28381 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
28382 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
28383 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
28384 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
28385 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
28386 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
28387 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
28388 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
28389 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
28390 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
28391 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
28392 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
28393 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
28394 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
28395 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
28396 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
28397 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
28398 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
28399 | //BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST |
28400 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
28401 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
28402 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
28403 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
28404 | //BIF_CFG_DEV0_EPF1_0_PCIE_CAP |
28405 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0 |
28406 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
28407 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
28408 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
28409 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL |
28410 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
28411 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
28412 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
28413 | //BIF_CFG_DEV0_EPF1_0_DEVICE_CAP |
28414 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
28415 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
28416 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
28417 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
28418 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
28419 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
28420 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
28421 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
28422 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
28423 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
28424 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
28425 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
28426 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
28427 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
28428 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
28429 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
28430 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
28431 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
28432 | //BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL |
28433 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
28434 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
28435 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
28436 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
28437 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
28438 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
28439 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
28440 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
28441 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
28442 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
28443 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
28444 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
28445 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
28446 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
28447 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
28448 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
28449 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
28450 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
28451 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
28452 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
28453 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
28454 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
28455 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
28456 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
28457 | //BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS |
28458 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
28459 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
28460 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
28461 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
28462 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
28463 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
28464 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
28465 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
28466 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
28467 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
28468 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
28469 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
28470 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
28471 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
28472 | //BIF_CFG_DEV0_EPF1_0_LINK_CAP |
28473 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
28474 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
28475 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
28476 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
28477 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
28478 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
28479 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
28480 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
28481 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
28482 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
28483 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
28484 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
28485 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
28486 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
28487 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
28488 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
28489 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
28490 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
28491 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
28492 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
28493 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
28494 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
28495 | //BIF_CFG_DEV0_EPF1_0_LINK_CNTL |
28496 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
28497 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
28498 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
28499 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
28500 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
28501 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
28502 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
28503 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
28504 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
28505 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
28506 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
28507 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
28508 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
28509 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
28510 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
28511 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
28512 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
28513 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
28514 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
28515 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
28516 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
28517 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
28518 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
28519 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
28520 | //BIF_CFG_DEV0_EPF1_0_LINK_STATUS |
28521 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
28522 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
28523 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
28524 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
28525 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
28526 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
28527 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
28528 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
28529 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
28530 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
28531 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
28532 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
28533 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
28534 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
28535 | //BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 |
28536 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
28537 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
28538 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
28539 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
28540 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
28541 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
28542 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
28543 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
28544 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
28545 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
28546 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
28547 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
28548 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
28549 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
28550 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
28551 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
28552 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
28553 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
28554 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
28555 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
28556 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
28557 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
28558 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
28559 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
28560 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
28561 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
28562 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
28563 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
28564 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
28565 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
28566 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
28567 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
28568 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
28569 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
28570 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
28571 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
28572 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
28573 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
28574 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
28575 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
28576 | //BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 |
28577 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
28578 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
28579 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
28580 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
28581 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
28582 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
28583 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
28584 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
28585 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
28586 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
28587 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
28588 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
28589 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
28590 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
28591 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
28592 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
28593 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
28594 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
28595 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
28596 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
28597 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
28598 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
28599 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
28600 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
28601 | //BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 |
28602 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
28603 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
28604 | //BIF_CFG_DEV0_EPF1_0_LINK_CAP2 |
28605 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
28606 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
28607 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
28608 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
28609 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
28610 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
28611 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
28612 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
28613 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
28614 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
28615 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
28616 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
28617 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
28618 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
28619 | //BIF_CFG_DEV0_EPF1_0_LINK_CNTL2 |
28620 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
28621 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
28622 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
28623 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
28624 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
28625 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
28626 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
28627 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
28628 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
28629 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
28630 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
28631 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
28632 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
28633 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
28634 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
28635 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
28636 | //BIF_CFG_DEV0_EPF1_0_LINK_STATUS2 |
28637 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
28638 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
28639 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
28640 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
28641 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
28642 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
28643 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
28644 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
28645 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
28646 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
28647 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
28648 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
28649 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
28650 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
28651 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
28652 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
28653 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
28654 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
28655 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
28656 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
28657 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
28658 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
28659 | //BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST |
28660 | #define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
28661 | #define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
28662 | #define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
28663 | #define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
28664 | //BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL |
28665 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
28666 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
28667 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
28668 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
28669 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
28670 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
28671 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
28672 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
28673 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
28674 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
28675 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
28676 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
28677 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
28678 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
28679 | //BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO |
28680 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
28681 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
28682 | //BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI |
28683 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
28684 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
28685 | //BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA |
28686 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
28687 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
28688 | //BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA |
28689 | #define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
28690 | #define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
28691 | //BIF_CFG_DEV0_EPF1_0_MSI_MASK |
28692 | #define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
28693 | #define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
28694 | //BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 |
28695 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
28696 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
28697 | //BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64 |
28698 | #define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
28699 | #define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
28700 | //BIF_CFG_DEV0_EPF1_0_MSI_MASK_64 |
28701 | #define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
28702 | #define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
28703 | //BIF_CFG_DEV0_EPF1_0_MSI_PENDING |
28704 | #define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
28705 | #define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
28706 | //BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 |
28707 | #define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
28708 | #define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
28709 | //BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST |
28710 | #define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
28711 | #define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
28712 | #define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
28713 | #define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
28714 | //BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL |
28715 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
28716 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
28717 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
28718 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
28719 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
28720 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
28721 | //BIF_CFG_DEV0_EPF1_0_MSIX_TABLE |
28722 | #define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
28723 | #define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
28724 | #define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
28725 | #define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
28726 | //BIF_CFG_DEV0_EPF1_0_MSIX_PBA |
28727 | #define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
28728 | #define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
28729 | #define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
28730 | #define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
28731 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
28732 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
28733 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
28734 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
28735 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
28736 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
28737 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
28738 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR |
28739 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
28740 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
28741 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
28742 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
28743 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
28744 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
28745 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 |
28746 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
28747 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
28748 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 |
28749 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
28750 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
28751 | //BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
28752 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
28753 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
28754 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
28755 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
28756 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
28757 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
28758 | //BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 |
28759 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
28760 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
28761 | //BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 |
28762 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
28763 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
28764 | //BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
28765 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
28766 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
28767 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
28768 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
28769 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
28770 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
28771 | //BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS |
28772 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
28773 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
28774 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
28775 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
28776 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
28777 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
28778 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
28779 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
28780 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
28781 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
28782 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
28783 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
28784 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
28785 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
28786 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
28787 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
28788 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
28789 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
28790 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
28791 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
28792 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
28793 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
28794 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
28795 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
28796 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
28797 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
28798 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
28799 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
28800 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
28801 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
28802 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
28803 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
28804 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
28805 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
28806 | //BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK |
28807 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
28808 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
28809 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
28810 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
28811 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
28812 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
28813 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
28814 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
28815 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
28816 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
28817 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
28818 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
28819 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
28820 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
28821 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
28822 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
28823 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
28824 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
28825 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
28826 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
28827 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
28828 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
28829 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
28830 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
28831 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
28832 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
28833 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
28834 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
28835 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
28836 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
28837 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
28838 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
28839 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
28840 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
28841 | //BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY |
28842 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
28843 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
28844 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
28845 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
28846 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
28847 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
28848 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
28849 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
28850 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
28851 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
28852 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
28853 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
28854 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
28855 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
28856 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
28857 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
28858 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
28859 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
28860 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
28861 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
28862 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
28863 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
28864 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
28865 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
28866 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
28867 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
28868 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
28869 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
28870 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
28871 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
28872 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
28873 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
28874 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
28875 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
28876 | //BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS |
28877 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
28878 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
28879 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
28880 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
28881 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
28882 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
28883 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
28884 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
28885 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
28886 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
28887 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
28888 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
28889 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
28890 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
28891 | //BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK |
28892 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
28893 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
28894 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
28895 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
28896 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
28897 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
28898 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
28899 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
28900 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
28901 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
28902 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
28903 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
28904 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
28905 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
28906 | //BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL |
28907 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
28908 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
28909 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
28910 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
28911 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
28912 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
28913 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
28914 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
28915 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
28916 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
28917 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
28918 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
28919 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
28920 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
28921 | //BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 |
28922 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
28923 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
28924 | //BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 |
28925 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
28926 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
28927 | //BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 |
28928 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
28929 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
28930 | //BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 |
28931 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
28932 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
28933 | //BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 |
28934 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
28935 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
28936 | //BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 |
28937 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
28938 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
28939 | //BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 |
28940 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
28941 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
28942 | //BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 |
28943 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
28944 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
28945 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST |
28946 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
28947 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
28948 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
28949 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
28950 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
28951 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
28952 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP |
28953 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
28954 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
28955 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL |
28956 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
28957 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
28958 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
28959 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
28960 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
28961 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
28962 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
28963 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
28964 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP |
28965 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
28966 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
28967 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL |
28968 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
28969 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
28970 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
28971 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
28972 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
28973 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
28974 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
28975 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
28976 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP |
28977 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
28978 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
28979 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL |
28980 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
28981 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
28982 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
28983 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
28984 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
28985 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
28986 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
28987 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
28988 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP |
28989 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
28990 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
28991 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL |
28992 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
28993 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
28994 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
28995 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
28996 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
28997 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
28998 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
28999 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
29000 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP |
29001 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
29002 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
29003 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL |
29004 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
29005 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
29006 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
29007 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
29008 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
29009 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
29010 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
29011 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
29012 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP |
29013 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
29014 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
29015 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL |
29016 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
29017 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
29018 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
29019 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
29020 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
29021 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
29022 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
29023 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
29024 | //BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
29025 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
29026 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
29027 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
29028 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
29029 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
29030 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
29031 | //BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT |
29032 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
29033 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
29034 | //BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA |
29035 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
29036 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
29037 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
29038 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
29039 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
29040 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
29041 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
29042 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
29043 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
29044 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
29045 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
29046 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
29047 | //BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP |
29048 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
29049 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
29050 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST |
29051 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
29052 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
29053 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
29054 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
29055 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
29056 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
29057 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP |
29058 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
29059 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
29060 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
29061 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
29062 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
29063 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
29064 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
29065 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
29066 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
29067 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
29068 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR |
29069 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
29070 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
29071 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS |
29072 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
29073 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
29074 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
29075 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
29076 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL |
29077 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
29078 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
29079 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
29080 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
29081 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
29082 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
29083 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
29084 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
29085 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
29086 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
29087 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
29088 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
29089 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
29090 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
29091 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
29092 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
29093 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
29094 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
29095 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
29096 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
29097 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
29098 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
29099 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
29100 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
29101 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
29102 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
29103 | //BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST |
29104 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
29105 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
29106 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
29107 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
29108 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
29109 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
29110 | //BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 |
29111 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
29112 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
29113 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
29114 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
29115 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
29116 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
29117 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS |
29118 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
29119 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
29120 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL |
29121 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29122 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29123 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29124 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29125 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29126 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29127 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29128 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29129 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL |
29130 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29131 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29132 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29133 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29134 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29135 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29136 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29137 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29138 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL |
29139 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29140 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29141 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29142 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29143 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29144 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29145 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29146 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29147 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL |
29148 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29149 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29150 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29151 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29152 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29153 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29154 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29155 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29156 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL |
29157 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29158 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29159 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29160 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29161 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29162 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29163 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29164 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29165 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL |
29166 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29167 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29168 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29169 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29170 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29171 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29172 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29173 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29174 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL |
29175 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29176 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29177 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29178 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29179 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29180 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29181 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29182 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29183 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL |
29184 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29185 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29186 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29187 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29188 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29189 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29190 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29191 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29192 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL |
29193 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29194 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29195 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29196 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29197 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29198 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29199 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29200 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29201 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL |
29202 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29203 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29204 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29205 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29206 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29207 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29208 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29209 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29210 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL |
29211 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29212 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29213 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29214 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29215 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29216 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29217 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29218 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29219 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL |
29220 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29221 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29222 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29223 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29224 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29225 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29226 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29227 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29228 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL |
29229 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29230 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29231 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29232 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29233 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29234 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29235 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29236 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29237 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL |
29238 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29239 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29240 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29241 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29242 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29243 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29244 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29245 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29246 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL |
29247 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29248 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29249 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29250 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29251 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29252 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29253 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29254 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29255 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL |
29256 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
29257 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
29258 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
29259 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
29260 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
29261 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
29262 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
29263 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
29264 | //BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST |
29265 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
29266 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
29267 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
29268 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
29269 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
29270 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
29271 | //BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP |
29272 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
29273 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
29274 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
29275 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
29276 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
29277 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
29278 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
29279 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
29280 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
29281 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
29282 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
29283 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
29284 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
29285 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
29286 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
29287 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
29288 | //BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL |
29289 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
29290 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
29291 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
29292 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
29293 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
29294 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
29295 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
29296 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
29297 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
29298 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
29299 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
29300 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
29301 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
29302 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
29303 | //BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST |
29304 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
29305 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
29306 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
29307 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
29308 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
29309 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
29310 | //BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP |
29311 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
29312 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
29313 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
29314 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 |
29315 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
29316 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
29317 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
29318 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L |
29319 | //BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL |
29320 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
29321 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
29322 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
29323 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
29324 | //BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST |
29325 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
29326 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
29327 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
29328 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
29329 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
29330 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
29331 | //BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL |
29332 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
29333 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
29334 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
29335 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
29336 | //BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS |
29337 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
29338 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
29339 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
29340 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
29341 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
29342 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
29343 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
29344 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
29345 | //BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
29346 | #define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
29347 | #define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
29348 | //BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
29349 | #define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
29350 | #define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
29351 | //BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST |
29352 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
29353 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
29354 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
29355 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
29356 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
29357 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
29358 | //BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP |
29359 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
29360 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
29361 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
29362 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
29363 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
29364 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
29365 | //BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL |
29366 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
29367 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
29368 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
29369 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
29370 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
29371 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
29372 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST |
29373 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
29374 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
29375 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
29376 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
29377 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
29378 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
29379 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP |
29380 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
29381 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
29382 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
29383 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
29384 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
29385 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
29386 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL |
29387 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
29388 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
29389 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
29390 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
29391 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 |
29392 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
29393 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
29394 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
29395 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
29396 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 |
29397 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
29398 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
29399 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 |
29400 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
29401 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
29402 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 |
29403 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
29404 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
29405 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 |
29406 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
29407 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
29408 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 |
29409 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
29410 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
29411 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
29412 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
29413 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
29414 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
29415 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
29416 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
29417 | //BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST |
29418 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
29419 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
29420 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
29421 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
29422 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
29423 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
29424 | //BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP |
29425 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
29426 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
29427 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
29428 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
29429 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
29430 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
29431 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
29432 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
29433 | //BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST |
29434 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
29435 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
29436 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
29437 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
29438 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
29439 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
29440 | //BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP |
29441 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
29442 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
29443 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
29444 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
29445 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
29446 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
29447 | //BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL |
29448 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
29449 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
29450 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
29451 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
29452 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
29453 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
29454 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST |
29455 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
29456 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
29457 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
29458 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
29459 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
29460 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
29461 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP |
29462 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
29463 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 |
29464 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
29465 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L |
29466 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL |
29467 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
29468 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
29469 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
29470 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 |
29471 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
29472 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
29473 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
29474 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L |
29475 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS |
29476 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS |
29477 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
29478 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
29479 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS |
29480 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
29481 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
29482 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS |
29483 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
29484 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
29485 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK |
29486 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
29487 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL |
29488 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET |
29489 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
29490 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
29491 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE |
29492 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
29493 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
29494 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID |
29495 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
29496 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
29497 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
29498 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
29499 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
29500 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
29501 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
29502 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
29503 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 |
29504 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
29505 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
29506 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 |
29507 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
29508 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
29509 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 |
29510 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
29511 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
29512 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 |
29513 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
29514 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
29515 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 |
29516 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
29517 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
29518 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 |
29519 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
29520 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
29521 | //BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST |
29522 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
29523 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
29524 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
29525 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
29526 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
29527 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
29528 | //BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP |
29529 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
29530 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
29531 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
29532 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
29533 | //BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS |
29534 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
29535 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
29536 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
29537 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
29538 | //BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST |
29539 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
29540 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
29541 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
29542 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
29543 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
29544 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
29545 | //BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT |
29546 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
29547 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
29548 | //BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT |
29549 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
29550 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
29551 | //BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT |
29552 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
29553 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
29554 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
29555 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
29556 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
29557 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
29558 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
29559 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
29560 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
29561 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
29562 | //BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT |
29563 | #define BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
29564 | #define BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
29565 | //BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT |
29566 | #define BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
29567 | #define BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
29568 | //BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT |
29569 | #define BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
29570 | #define BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
29571 | //BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT |
29572 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29573 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
29574 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
29575 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
29576 | //BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT |
29577 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29578 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
29579 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
29580 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
29581 | //BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT |
29582 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29583 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
29584 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
29585 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
29586 | //BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT |
29587 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29588 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
29589 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
29590 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
29591 | //BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT |
29592 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29593 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
29594 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
29595 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
29596 | //BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT |
29597 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29598 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
29599 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
29600 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
29601 | //BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT |
29602 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29603 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
29604 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
29605 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
29606 | //BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT |
29607 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29608 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
29609 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
29610 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
29611 | //BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT |
29612 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29613 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
29614 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
29615 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
29616 | //BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT |
29617 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29618 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
29619 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
29620 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
29621 | //BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT |
29622 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29623 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
29624 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
29625 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
29626 | //BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT |
29627 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29628 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
29629 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
29630 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
29631 | //BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT |
29632 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29633 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
29634 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
29635 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
29636 | //BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT |
29637 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29638 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
29639 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
29640 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
29641 | //BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT |
29642 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29643 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
29644 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
29645 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
29646 | //BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT |
29647 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
29648 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
29649 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
29650 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
29651 | //BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST |
29652 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
29653 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
29654 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
29655 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
29656 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
29657 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
29658 | //BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP |
29659 | #define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
29660 | #define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
29661 | //BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS |
29662 | #define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
29663 | #define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
29664 | #define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
29665 | #define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
29666 | //BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL |
29667 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
29668 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
29669 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
29670 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
29671 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
29672 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
29673 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
29674 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
29675 | //BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS |
29676 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29677 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29678 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
29679 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29680 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29681 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
29682 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
29683 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29684 | //BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL |
29685 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
29686 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
29687 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
29688 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
29689 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
29690 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
29691 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
29692 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
29693 | //BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS |
29694 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29695 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29696 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
29697 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29698 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29699 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
29700 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
29701 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29702 | //BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL |
29703 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
29704 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
29705 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
29706 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
29707 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
29708 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
29709 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
29710 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
29711 | //BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS |
29712 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29713 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29714 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
29715 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29716 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29717 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
29718 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
29719 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29720 | //BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL |
29721 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
29722 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
29723 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
29724 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
29725 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
29726 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
29727 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
29728 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
29729 | //BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS |
29730 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29731 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29732 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
29733 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29734 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29735 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
29736 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
29737 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29738 | //BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL |
29739 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
29740 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
29741 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
29742 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
29743 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
29744 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
29745 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
29746 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
29747 | //BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS |
29748 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29749 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29750 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
29751 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29752 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29753 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
29754 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
29755 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29756 | //BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL |
29757 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
29758 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
29759 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
29760 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
29761 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
29762 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
29763 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
29764 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
29765 | //BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS |
29766 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29767 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29768 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
29769 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29770 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29771 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
29772 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
29773 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29774 | //BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL |
29775 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
29776 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
29777 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
29778 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
29779 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
29780 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
29781 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
29782 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
29783 | //BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS |
29784 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29785 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29786 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
29787 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29788 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29789 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
29790 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
29791 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29792 | //BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL |
29793 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
29794 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
29795 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
29796 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
29797 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
29798 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
29799 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
29800 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
29801 | //BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS |
29802 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29803 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29804 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
29805 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29806 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29807 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
29808 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
29809 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29810 | //BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL |
29811 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
29812 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
29813 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
29814 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
29815 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
29816 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
29817 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
29818 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
29819 | //BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS |
29820 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29821 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29822 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
29823 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29824 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29825 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
29826 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
29827 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29828 | //BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL |
29829 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
29830 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
29831 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
29832 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
29833 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
29834 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
29835 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
29836 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
29837 | //BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS |
29838 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29839 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29840 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
29841 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29842 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29843 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
29844 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
29845 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29846 | //BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL |
29847 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
29848 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
29849 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
29850 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
29851 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
29852 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
29853 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
29854 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
29855 | //BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS |
29856 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29857 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29858 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
29859 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29860 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29861 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
29862 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
29863 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29864 | //BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL |
29865 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
29866 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
29867 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
29868 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
29869 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
29870 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
29871 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
29872 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
29873 | //BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS |
29874 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29875 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29876 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
29877 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29878 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29879 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
29880 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
29881 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29882 | //BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL |
29883 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
29884 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
29885 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
29886 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
29887 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
29888 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
29889 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
29890 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
29891 | //BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS |
29892 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29893 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29894 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
29895 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29896 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29897 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
29898 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
29899 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29900 | //BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL |
29901 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
29902 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
29903 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
29904 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
29905 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
29906 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
29907 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
29908 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
29909 | //BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS |
29910 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29911 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29912 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
29913 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29914 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29915 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
29916 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
29917 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29918 | //BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL |
29919 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
29920 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
29921 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
29922 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
29923 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
29924 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
29925 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
29926 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
29927 | //BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS |
29928 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29929 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29930 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
29931 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29932 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29933 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
29934 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
29935 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29936 | //BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL |
29937 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
29938 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
29939 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
29940 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
29941 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
29942 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
29943 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
29944 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
29945 | //BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS |
29946 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
29947 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
29948 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
29949 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
29950 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
29951 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
29952 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
29953 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
29954 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST |
29955 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
29956 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
29957 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
29958 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
29959 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
29960 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
29961 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP |
29962 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
29963 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
29964 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL |
29965 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
29966 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
29967 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
29968 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
29969 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
29970 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
29971 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
29972 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
29973 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP |
29974 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
29975 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
29976 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL |
29977 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
29978 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
29979 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
29980 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
29981 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
29982 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
29983 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
29984 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
29985 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP |
29986 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
29987 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
29988 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL |
29989 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
29990 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
29991 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
29992 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
29993 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
29994 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
29995 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
29996 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
29997 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP |
29998 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
29999 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
30000 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL |
30001 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
30002 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
30003 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
30004 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
30005 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
30006 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
30007 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
30008 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
30009 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP |
30010 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
30011 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
30012 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL |
30013 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
30014 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
30015 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
30016 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
30017 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
30018 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
30019 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
30020 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
30021 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP |
30022 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
30023 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
30024 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL |
30025 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
30026 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
30027 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
30028 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
30029 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
30030 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
30031 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
30032 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
30033 | //BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST |
30034 | #define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
30035 | #define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
30036 | #define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
30037 | #define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
30038 | #define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
30039 | #define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
30040 | //BIF_CFG_DEV0_EPF1_0_RTR_DATA1 |
30041 | #define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
30042 | #define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
30043 | #define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__VALID__SHIFT 0x1f |
30044 | #define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
30045 | #define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
30046 | #define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__VALID_MASK 0x80000000L |
30047 | //BIF_CFG_DEV0_EPF1_0_RTR_DATA2 |
30048 | #define BIF_CFG_DEV0_EPF1_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
30049 | #define BIF_CFG_DEV0_EPF1_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
30050 | #define BIF_CFG_DEV0_EPF1_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
30051 | #define BIF_CFG_DEV0_EPF1_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
30052 | |
30053 | |
30054 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp |
30055 | //BIF_CFG_DEV0_EPF2_0_VENDOR_ID |
30056 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
30057 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
30058 | //BIF_CFG_DEV0_EPF2_0_DEVICE_ID |
30059 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
30060 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
30061 | //BIF_CFG_DEV0_EPF2_0_COMMAND |
30062 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
30063 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
30064 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
30065 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
30066 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
30067 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
30068 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
30069 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN__SHIFT 0x8 |
30070 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
30071 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS__SHIFT 0xa |
30072 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
30073 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
30074 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
30075 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
30076 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
30077 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
30078 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING_MASK 0x0080L |
30079 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN_MASK 0x0100L |
30080 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
30081 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS_MASK 0x0400L |
30082 | //BIF_CFG_DEV0_EPF2_0_STATUS |
30083 | #define BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
30084 | #define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS__SHIFT 0x3 |
30085 | #define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST__SHIFT 0x4 |
30086 | #define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
30087 | #define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
30088 | #define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
30089 | #define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
30090 | #define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
30091 | #define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
30092 | #define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
30093 | #define BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
30094 | #define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS_MASK 0x0008L |
30095 | #define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST_MASK 0x0010L |
30096 | #define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP_MASK 0x0020L |
30097 | #define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
30098 | #define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
30099 | #define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
30100 | #define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
30101 | #define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
30102 | #define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
30103 | //BIF_CFG_DEV0_EPF2_0_REVISION_ID |
30104 | #define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
30105 | #define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
30106 | #define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
30107 | #define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
30108 | //BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE |
30109 | #define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
30110 | #define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
30111 | //BIF_CFG_DEV0_EPF2_0_SUB_CLASS |
30112 | #define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
30113 | #define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
30114 | //BIF_CFG_DEV0_EPF2_0_BASE_CLASS |
30115 | #define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
30116 | #define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
30117 | //BIF_CFG_DEV0_EPF2_0_CACHE_LINE |
30118 | #define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
30119 | #define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
30120 | //BIF_CFG_DEV0_EPF2_0_LATENCY |
30121 | #define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
30122 | #define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
30123 | //BIF_CFG_DEV0_EPF2_0_HEADER |
30124 | #define 0x0 |
30125 | #define 0x7 |
30126 | #define 0x7FL |
30127 | #define 0x80L |
30128 | //BIF_CFG_DEV0_EPF2_0_BIST |
30129 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP__SHIFT 0x0 |
30130 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT__SHIFT 0x6 |
30131 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP__SHIFT 0x7 |
30132 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP_MASK 0x0FL |
30133 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT_MASK 0x40L |
30134 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP_MASK 0x80L |
30135 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 |
30136 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
30137 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
30138 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 |
30139 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
30140 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
30141 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 |
30142 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
30143 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
30144 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 |
30145 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
30146 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
30147 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 |
30148 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
30149 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
30150 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 |
30151 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
30152 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
30153 | //BIF_CFG_DEV0_EPF2_0_ADAPTER_ID |
30154 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
30155 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
30156 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
30157 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
30158 | //BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR |
30159 | #define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
30160 | #define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
30161 | //BIF_CFG_DEV0_EPF2_0_CAP_PTR |
30162 | #define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
30163 | #define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
30164 | //BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE |
30165 | #define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
30166 | #define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
30167 | //BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN |
30168 | #define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
30169 | #define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
30170 | //BIF_CFG_DEV0_EPF2_0_MIN_GRANT |
30171 | #define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
30172 | #define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
30173 | //BIF_CFG_DEV0_EPF2_0_MAX_LATENCY |
30174 | #define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
30175 | #define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
30176 | //BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST |
30177 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
30178 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
30179 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
30180 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
30181 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
30182 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
30183 | //BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W |
30184 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
30185 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
30186 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
30187 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
30188 | //BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST |
30189 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
30190 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
30191 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
30192 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
30193 | //BIF_CFG_DEV0_EPF2_0_PMI_CAP |
30194 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION__SHIFT 0x0 |
30195 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
30196 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
30197 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
30198 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
30199 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
30200 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
30201 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
30202 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION_MASK 0x0007L |
30203 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
30204 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
30205 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
30206 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
30207 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
30208 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
30209 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
30210 | //BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL |
30211 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
30212 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
30213 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
30214 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
30215 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
30216 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
30217 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
30218 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
30219 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
30220 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
30221 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
30222 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
30223 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
30224 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
30225 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
30226 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
30227 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
30228 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
30229 | //BIF_CFG_DEV0_EPF2_0_SBRN |
30230 | #define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN__SHIFT 0x0 |
30231 | #define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN_MASK 0xFFL |
30232 | //BIF_CFG_DEV0_EPF2_0_FLADJ |
30233 | #define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ__SHIFT 0x0 |
30234 | #define BIF_CFG_DEV0_EPF2_0_FLADJ__NFC__SHIFT 0x6 |
30235 | #define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ_MASK 0x3FL |
30236 | #define BIF_CFG_DEV0_EPF2_0_FLADJ__NFC_MASK 0x40L |
30237 | //BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD |
30238 | #define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
30239 | #define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
30240 | #define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
30241 | #define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
30242 | //BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST |
30243 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
30244 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
30245 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
30246 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
30247 | //BIF_CFG_DEV0_EPF2_0_PCIE_CAP |
30248 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION__SHIFT 0x0 |
30249 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
30250 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
30251 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
30252 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION_MASK 0x000FL |
30253 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
30254 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
30255 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
30256 | //BIF_CFG_DEV0_EPF2_0_DEVICE_CAP |
30257 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
30258 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
30259 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
30260 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
30261 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
30262 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
30263 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
30264 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
30265 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
30266 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
30267 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
30268 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
30269 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
30270 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
30271 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
30272 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
30273 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
30274 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
30275 | //BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL |
30276 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
30277 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
30278 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
30279 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
30280 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
30281 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
30282 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
30283 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
30284 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
30285 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
30286 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
30287 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
30288 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
30289 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
30290 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
30291 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
30292 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
30293 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
30294 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
30295 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
30296 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
30297 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
30298 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
30299 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
30300 | //BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS |
30301 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
30302 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
30303 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
30304 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
30305 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
30306 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
30307 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
30308 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
30309 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
30310 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
30311 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
30312 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
30313 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
30314 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
30315 | //BIF_CFG_DEV0_EPF2_0_LINK_CAP |
30316 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
30317 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
30318 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
30319 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
30320 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
30321 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
30322 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
30323 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
30324 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
30325 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
30326 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
30327 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
30328 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
30329 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
30330 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
30331 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
30332 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
30333 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
30334 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
30335 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
30336 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
30337 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
30338 | //BIF_CFG_DEV0_EPF2_0_LINK_CNTL |
30339 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
30340 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
30341 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
30342 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
30343 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
30344 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
30345 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
30346 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
30347 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
30348 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
30349 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
30350 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
30351 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
30352 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
30353 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
30354 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
30355 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
30356 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
30357 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
30358 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
30359 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
30360 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
30361 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
30362 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
30363 | //BIF_CFG_DEV0_EPF2_0_LINK_STATUS |
30364 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
30365 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
30366 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
30367 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
30368 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
30369 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
30370 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
30371 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
30372 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
30373 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
30374 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
30375 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
30376 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
30377 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
30378 | //BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 |
30379 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
30380 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
30381 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
30382 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
30383 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
30384 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
30385 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
30386 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
30387 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
30388 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
30389 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
30390 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
30391 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
30392 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
30393 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
30394 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
30395 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
30396 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
30397 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
30398 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
30399 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
30400 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
30401 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
30402 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
30403 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
30404 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
30405 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
30406 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
30407 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
30408 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
30409 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
30410 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
30411 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
30412 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
30413 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
30414 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
30415 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
30416 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
30417 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
30418 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
30419 | //BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 |
30420 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
30421 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
30422 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
30423 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
30424 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
30425 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
30426 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
30427 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
30428 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
30429 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
30430 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
30431 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
30432 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
30433 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
30434 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
30435 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
30436 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
30437 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
30438 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
30439 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
30440 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
30441 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
30442 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
30443 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
30444 | //BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 |
30445 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
30446 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
30447 | //BIF_CFG_DEV0_EPF2_0_LINK_CAP2 |
30448 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
30449 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
30450 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
30451 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
30452 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
30453 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
30454 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
30455 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
30456 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
30457 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
30458 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
30459 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
30460 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
30461 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
30462 | //BIF_CFG_DEV0_EPF2_0_LINK_CNTL2 |
30463 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
30464 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
30465 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
30466 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
30467 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
30468 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
30469 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
30470 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
30471 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
30472 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
30473 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
30474 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
30475 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
30476 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
30477 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
30478 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
30479 | //BIF_CFG_DEV0_EPF2_0_LINK_STATUS2 |
30480 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
30481 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
30482 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
30483 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
30484 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
30485 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
30486 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
30487 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
30488 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
30489 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
30490 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
30491 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
30492 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
30493 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
30494 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
30495 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
30496 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
30497 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
30498 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
30499 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
30500 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
30501 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
30502 | //BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST |
30503 | #define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
30504 | #define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
30505 | #define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
30506 | #define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
30507 | //BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL |
30508 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
30509 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
30510 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
30511 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
30512 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
30513 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
30514 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
30515 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
30516 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
30517 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
30518 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
30519 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
30520 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
30521 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
30522 | //BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO |
30523 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
30524 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
30525 | //BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI |
30526 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
30527 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
30528 | //BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA |
30529 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
30530 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
30531 | //BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA |
30532 | #define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
30533 | #define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
30534 | //BIF_CFG_DEV0_EPF2_0_MSI_MASK |
30535 | #define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
30536 | #define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
30537 | //BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 |
30538 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
30539 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
30540 | //BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64 |
30541 | #define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
30542 | #define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
30543 | //BIF_CFG_DEV0_EPF2_0_MSI_MASK_64 |
30544 | #define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
30545 | #define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
30546 | //BIF_CFG_DEV0_EPF2_0_MSI_PENDING |
30547 | #define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
30548 | #define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
30549 | //BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 |
30550 | #define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
30551 | #define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
30552 | //BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST |
30553 | #define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
30554 | #define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
30555 | #define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
30556 | #define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
30557 | //BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL |
30558 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
30559 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
30560 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
30561 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
30562 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
30563 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
30564 | //BIF_CFG_DEV0_EPF2_0_MSIX_TABLE |
30565 | #define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
30566 | #define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
30567 | #define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
30568 | #define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
30569 | //BIF_CFG_DEV0_EPF2_0_MSIX_PBA |
30570 | #define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
30571 | #define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
30572 | #define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
30573 | #define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
30574 | //BIF_CFG_DEV0_EPF2_0_SATA_CAP_0 |
30575 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
30576 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
30577 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
30578 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
30579 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
30580 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
30581 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
30582 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
30583 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
30584 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
30585 | //BIF_CFG_DEV0_EPF2_0_SATA_CAP_1 |
30586 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
30587 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
30588 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
30589 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
30590 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
30591 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
30592 | //BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX |
30593 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
30594 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
30595 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
30596 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
30597 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
30598 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
30599 | //BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA |
30600 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
30601 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
30602 | //BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
30603 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
30604 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
30605 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
30606 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
30607 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
30608 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
30609 | //BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR |
30610 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
30611 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
30612 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
30613 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
30614 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
30615 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
30616 | //BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 |
30617 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
30618 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
30619 | //BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 |
30620 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
30621 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
30622 | //BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
30623 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
30624 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
30625 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
30626 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
30627 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
30628 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
30629 | //BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS |
30630 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
30631 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
30632 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
30633 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
30634 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
30635 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
30636 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
30637 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
30638 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
30639 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
30640 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
30641 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
30642 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
30643 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
30644 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
30645 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
30646 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
30647 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
30648 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
30649 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
30650 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
30651 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
30652 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
30653 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
30654 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
30655 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
30656 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
30657 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
30658 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
30659 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
30660 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
30661 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
30662 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
30663 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
30664 | //BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK |
30665 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
30666 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
30667 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
30668 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
30669 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
30670 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
30671 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
30672 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
30673 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
30674 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
30675 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
30676 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
30677 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
30678 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
30679 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
30680 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
30681 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
30682 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
30683 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
30684 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
30685 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
30686 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
30687 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
30688 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
30689 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
30690 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
30691 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
30692 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
30693 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
30694 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
30695 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
30696 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
30697 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
30698 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
30699 | //BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY |
30700 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
30701 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
30702 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
30703 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
30704 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
30705 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
30706 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
30707 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
30708 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
30709 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
30710 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
30711 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
30712 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
30713 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
30714 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
30715 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
30716 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
30717 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
30718 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
30719 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
30720 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
30721 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
30722 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
30723 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
30724 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
30725 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
30726 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
30727 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
30728 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
30729 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
30730 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
30731 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
30732 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
30733 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
30734 | //BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS |
30735 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
30736 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
30737 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
30738 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
30739 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
30740 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
30741 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
30742 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
30743 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
30744 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
30745 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
30746 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
30747 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
30748 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
30749 | //BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK |
30750 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
30751 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
30752 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
30753 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
30754 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
30755 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
30756 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
30757 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
30758 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
30759 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
30760 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
30761 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
30762 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
30763 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
30764 | //BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL |
30765 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
30766 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
30767 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
30768 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
30769 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
30770 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
30771 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
30772 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
30773 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
30774 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
30775 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
30776 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
30777 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
30778 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
30779 | //BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 |
30780 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
30781 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
30782 | //BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 |
30783 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
30784 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
30785 | //BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 |
30786 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
30787 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
30788 | //BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 |
30789 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
30790 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
30791 | //BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 |
30792 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
30793 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
30794 | //BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 |
30795 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
30796 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
30797 | //BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 |
30798 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
30799 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
30800 | //BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 |
30801 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
30802 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
30803 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST |
30804 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
30805 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
30806 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
30807 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
30808 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
30809 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
30810 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP |
30811 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
30812 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
30813 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL |
30814 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
30815 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
30816 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
30817 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
30818 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
30819 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
30820 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
30821 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
30822 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP |
30823 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
30824 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
30825 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL |
30826 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
30827 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
30828 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
30829 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
30830 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
30831 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
30832 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
30833 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
30834 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP |
30835 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
30836 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
30837 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL |
30838 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
30839 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
30840 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
30841 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
30842 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
30843 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
30844 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
30845 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
30846 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP |
30847 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
30848 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
30849 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL |
30850 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
30851 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
30852 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
30853 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
30854 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
30855 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
30856 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
30857 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
30858 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP |
30859 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
30860 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
30861 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL |
30862 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
30863 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
30864 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
30865 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
30866 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
30867 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
30868 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
30869 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
30870 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP |
30871 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
30872 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
30873 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL |
30874 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
30875 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
30876 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
30877 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
30878 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
30879 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
30880 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
30881 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
30882 | //BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
30883 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
30884 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
30885 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
30886 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
30887 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
30888 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
30889 | //BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT |
30890 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
30891 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
30892 | //BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA |
30893 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
30894 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
30895 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
30896 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
30897 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
30898 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
30899 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
30900 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
30901 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
30902 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
30903 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
30904 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
30905 | //BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP |
30906 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
30907 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
30908 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST |
30909 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
30910 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
30911 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
30912 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
30913 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
30914 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
30915 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP |
30916 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
30917 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
30918 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
30919 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
30920 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
30921 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
30922 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
30923 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
30924 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
30925 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
30926 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR |
30927 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
30928 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
30929 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS |
30930 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
30931 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
30932 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
30933 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
30934 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL |
30935 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
30936 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
30937 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
30938 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
30939 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
30940 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
30941 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
30942 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
30943 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
30944 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
30945 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
30946 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
30947 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
30948 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
30949 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
30950 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
30951 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
30952 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
30953 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
30954 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
30955 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
30956 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
30957 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
30958 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
30959 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
30960 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
30961 | //BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST |
30962 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
30963 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
30964 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
30965 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
30966 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
30967 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
30968 | //BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP |
30969 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
30970 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
30971 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
30972 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
30973 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
30974 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
30975 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
30976 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
30977 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
30978 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
30979 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
30980 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
30981 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
30982 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
30983 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
30984 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
30985 | //BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL |
30986 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
30987 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
30988 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
30989 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
30990 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
30991 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
30992 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
30993 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
30994 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
30995 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
30996 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
30997 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
30998 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
30999 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
31000 | //BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST |
31001 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
31002 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
31003 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
31004 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
31005 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
31006 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
31007 | //BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP |
31008 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
31009 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
31010 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
31011 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
31012 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
31013 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
31014 | //BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL |
31015 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
31016 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
31017 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
31018 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
31019 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
31020 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
31021 | //BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST |
31022 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
31023 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
31024 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
31025 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
31026 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
31027 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
31028 | //BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP |
31029 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
31030 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
31031 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
31032 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
31033 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
31034 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
31035 | //BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL |
31036 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
31037 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
31038 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
31039 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
31040 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
31041 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
31042 | //BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST |
31043 | #define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
31044 | #define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
31045 | #define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
31046 | #define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
31047 | #define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
31048 | #define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
31049 | //BIF_CFG_DEV0_EPF2_0_RTR_DATA1 |
31050 | #define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
31051 | #define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
31052 | #define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__VALID__SHIFT 0x1f |
31053 | #define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
31054 | #define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
31055 | #define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__VALID_MASK 0x80000000L |
31056 | //BIF_CFG_DEV0_EPF2_0_RTR_DATA2 |
31057 | #define BIF_CFG_DEV0_EPF2_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
31058 | #define BIF_CFG_DEV0_EPF2_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
31059 | #define BIF_CFG_DEV0_EPF2_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
31060 | #define BIF_CFG_DEV0_EPF2_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
31061 | |
31062 | |
31063 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp |
31064 | //BIF_CFG_DEV0_EPF3_0_VENDOR_ID |
31065 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
31066 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
31067 | //BIF_CFG_DEV0_EPF3_0_DEVICE_ID |
31068 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
31069 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
31070 | //BIF_CFG_DEV0_EPF3_0_COMMAND |
31071 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
31072 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
31073 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
31074 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
31075 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
31076 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
31077 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
31078 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN__SHIFT 0x8 |
31079 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
31080 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS__SHIFT 0xa |
31081 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
31082 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
31083 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
31084 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
31085 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
31086 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
31087 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING_MASK 0x0080L |
31088 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN_MASK 0x0100L |
31089 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
31090 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS_MASK 0x0400L |
31091 | //BIF_CFG_DEV0_EPF3_0_STATUS |
31092 | #define BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
31093 | #define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS__SHIFT 0x3 |
31094 | #define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST__SHIFT 0x4 |
31095 | #define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
31096 | #define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
31097 | #define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
31098 | #define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
31099 | #define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
31100 | #define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
31101 | #define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
31102 | #define BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
31103 | #define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS_MASK 0x0008L |
31104 | #define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST_MASK 0x0010L |
31105 | #define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP_MASK 0x0020L |
31106 | #define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
31107 | #define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
31108 | #define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
31109 | #define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
31110 | #define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
31111 | #define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
31112 | //BIF_CFG_DEV0_EPF3_0_REVISION_ID |
31113 | #define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
31114 | #define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
31115 | #define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
31116 | #define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
31117 | //BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE |
31118 | #define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
31119 | #define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
31120 | //BIF_CFG_DEV0_EPF3_0_SUB_CLASS |
31121 | #define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
31122 | #define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
31123 | //BIF_CFG_DEV0_EPF3_0_BASE_CLASS |
31124 | #define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
31125 | #define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
31126 | //BIF_CFG_DEV0_EPF3_0_CACHE_LINE |
31127 | #define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
31128 | #define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
31129 | //BIF_CFG_DEV0_EPF3_0_LATENCY |
31130 | #define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
31131 | #define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
31132 | //BIF_CFG_DEV0_EPF3_0_HEADER |
31133 | #define 0x0 |
31134 | #define 0x7 |
31135 | #define 0x7FL |
31136 | #define 0x80L |
31137 | //BIF_CFG_DEV0_EPF3_0_BIST |
31138 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP__SHIFT 0x0 |
31139 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT__SHIFT 0x6 |
31140 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP__SHIFT 0x7 |
31141 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP_MASK 0x0FL |
31142 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT_MASK 0x40L |
31143 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP_MASK 0x80L |
31144 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 |
31145 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
31146 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
31147 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 |
31148 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
31149 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
31150 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 |
31151 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
31152 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
31153 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 |
31154 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
31155 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
31156 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 |
31157 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
31158 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
31159 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 |
31160 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
31161 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
31162 | //BIF_CFG_DEV0_EPF3_0_ADAPTER_ID |
31163 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
31164 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
31165 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
31166 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
31167 | //BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR |
31168 | #define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
31169 | #define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
31170 | //BIF_CFG_DEV0_EPF3_0_CAP_PTR |
31171 | #define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
31172 | #define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
31173 | //BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE |
31174 | #define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
31175 | #define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
31176 | //BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN |
31177 | #define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
31178 | #define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
31179 | //BIF_CFG_DEV0_EPF3_0_MIN_GRANT |
31180 | #define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
31181 | #define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
31182 | //BIF_CFG_DEV0_EPF3_0_MAX_LATENCY |
31183 | #define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
31184 | #define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
31185 | //BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST |
31186 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
31187 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
31188 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
31189 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
31190 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
31191 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
31192 | //BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W |
31193 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
31194 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
31195 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
31196 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
31197 | //BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST |
31198 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
31199 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
31200 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
31201 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
31202 | //BIF_CFG_DEV0_EPF3_0_PMI_CAP |
31203 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION__SHIFT 0x0 |
31204 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
31205 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
31206 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
31207 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
31208 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
31209 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
31210 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
31211 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION_MASK 0x0007L |
31212 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
31213 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
31214 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
31215 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
31216 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
31217 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
31218 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
31219 | //BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL |
31220 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
31221 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
31222 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
31223 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
31224 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
31225 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
31226 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
31227 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
31228 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
31229 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
31230 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
31231 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
31232 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
31233 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
31234 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
31235 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
31236 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
31237 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
31238 | //BIF_CFG_DEV0_EPF3_0_SBRN |
31239 | #define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN__SHIFT 0x0 |
31240 | #define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN_MASK 0xFFL |
31241 | //BIF_CFG_DEV0_EPF3_0_FLADJ |
31242 | #define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ__SHIFT 0x0 |
31243 | #define BIF_CFG_DEV0_EPF3_0_FLADJ__NFC__SHIFT 0x6 |
31244 | #define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ_MASK 0x3FL |
31245 | #define BIF_CFG_DEV0_EPF3_0_FLADJ__NFC_MASK 0x40L |
31246 | //BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD |
31247 | #define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
31248 | #define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
31249 | #define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
31250 | #define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
31251 | //BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST |
31252 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
31253 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
31254 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
31255 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
31256 | //BIF_CFG_DEV0_EPF3_0_PCIE_CAP |
31257 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION__SHIFT 0x0 |
31258 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
31259 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
31260 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
31261 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION_MASK 0x000FL |
31262 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
31263 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
31264 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
31265 | //BIF_CFG_DEV0_EPF3_0_DEVICE_CAP |
31266 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
31267 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
31268 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
31269 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
31270 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
31271 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
31272 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
31273 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
31274 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
31275 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
31276 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
31277 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
31278 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
31279 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
31280 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
31281 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
31282 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
31283 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
31284 | //BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL |
31285 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
31286 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
31287 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
31288 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
31289 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
31290 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
31291 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
31292 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
31293 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
31294 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
31295 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
31296 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
31297 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
31298 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
31299 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
31300 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
31301 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
31302 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
31303 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
31304 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
31305 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
31306 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
31307 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
31308 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
31309 | //BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS |
31310 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
31311 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
31312 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
31313 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
31314 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
31315 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
31316 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
31317 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
31318 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
31319 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
31320 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
31321 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
31322 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
31323 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
31324 | //BIF_CFG_DEV0_EPF3_0_LINK_CAP |
31325 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
31326 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
31327 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
31328 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
31329 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
31330 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
31331 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
31332 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
31333 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
31334 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
31335 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
31336 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
31337 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
31338 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
31339 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
31340 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
31341 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
31342 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
31343 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
31344 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
31345 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
31346 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
31347 | //BIF_CFG_DEV0_EPF3_0_LINK_CNTL |
31348 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
31349 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
31350 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
31351 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
31352 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
31353 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
31354 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
31355 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
31356 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
31357 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
31358 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
31359 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
31360 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
31361 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
31362 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
31363 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
31364 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
31365 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
31366 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
31367 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
31368 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
31369 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
31370 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
31371 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
31372 | //BIF_CFG_DEV0_EPF3_0_LINK_STATUS |
31373 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
31374 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
31375 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
31376 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
31377 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
31378 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
31379 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
31380 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
31381 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
31382 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
31383 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
31384 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
31385 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
31386 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
31387 | //BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 |
31388 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
31389 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
31390 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
31391 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
31392 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
31393 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
31394 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
31395 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
31396 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
31397 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
31398 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
31399 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
31400 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
31401 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
31402 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
31403 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
31404 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
31405 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
31406 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
31407 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
31408 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
31409 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
31410 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
31411 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
31412 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
31413 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
31414 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
31415 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
31416 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
31417 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
31418 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
31419 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
31420 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
31421 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
31422 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
31423 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
31424 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
31425 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
31426 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
31427 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
31428 | //BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 |
31429 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
31430 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
31431 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
31432 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
31433 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
31434 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
31435 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
31436 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
31437 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
31438 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
31439 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
31440 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
31441 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
31442 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
31443 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
31444 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
31445 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
31446 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
31447 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
31448 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
31449 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
31450 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
31451 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
31452 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
31453 | //BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 |
31454 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
31455 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
31456 | //BIF_CFG_DEV0_EPF3_0_LINK_CAP2 |
31457 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
31458 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
31459 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
31460 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
31461 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
31462 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
31463 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
31464 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
31465 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
31466 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
31467 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
31468 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
31469 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
31470 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
31471 | //BIF_CFG_DEV0_EPF3_0_LINK_CNTL2 |
31472 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
31473 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
31474 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
31475 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
31476 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
31477 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
31478 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
31479 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
31480 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
31481 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
31482 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
31483 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
31484 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
31485 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
31486 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
31487 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
31488 | //BIF_CFG_DEV0_EPF3_0_LINK_STATUS2 |
31489 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
31490 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
31491 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
31492 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
31493 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
31494 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
31495 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
31496 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
31497 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
31498 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
31499 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
31500 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
31501 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
31502 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
31503 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
31504 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
31505 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
31506 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
31507 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
31508 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
31509 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
31510 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
31511 | //BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST |
31512 | #define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
31513 | #define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
31514 | #define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
31515 | #define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
31516 | //BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL |
31517 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
31518 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
31519 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
31520 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
31521 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
31522 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
31523 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
31524 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
31525 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
31526 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
31527 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
31528 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
31529 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
31530 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
31531 | //BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO |
31532 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
31533 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
31534 | //BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI |
31535 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
31536 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
31537 | //BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA |
31538 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
31539 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
31540 | //BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA |
31541 | #define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
31542 | #define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
31543 | //BIF_CFG_DEV0_EPF3_0_MSI_MASK |
31544 | #define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
31545 | #define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
31546 | //BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 |
31547 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
31548 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
31549 | //BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64 |
31550 | #define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
31551 | #define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
31552 | //BIF_CFG_DEV0_EPF3_0_MSI_MASK_64 |
31553 | #define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
31554 | #define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
31555 | //BIF_CFG_DEV0_EPF3_0_MSI_PENDING |
31556 | #define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
31557 | #define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
31558 | //BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 |
31559 | #define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
31560 | #define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
31561 | //BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST |
31562 | #define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
31563 | #define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
31564 | #define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
31565 | #define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
31566 | //BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL |
31567 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
31568 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
31569 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
31570 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
31571 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
31572 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
31573 | //BIF_CFG_DEV0_EPF3_0_MSIX_TABLE |
31574 | #define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
31575 | #define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
31576 | #define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
31577 | #define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
31578 | //BIF_CFG_DEV0_EPF3_0_MSIX_PBA |
31579 | #define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
31580 | #define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
31581 | #define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
31582 | #define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
31583 | //BIF_CFG_DEV0_EPF3_0_SATA_CAP_0 |
31584 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
31585 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
31586 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
31587 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
31588 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
31589 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
31590 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
31591 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
31592 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
31593 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
31594 | //BIF_CFG_DEV0_EPF3_0_SATA_CAP_1 |
31595 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
31596 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
31597 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
31598 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
31599 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
31600 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
31601 | //BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX |
31602 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
31603 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
31604 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
31605 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
31606 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
31607 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
31608 | //BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA |
31609 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
31610 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
31611 | //BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
31612 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
31613 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
31614 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
31615 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
31616 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
31617 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
31618 | //BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR |
31619 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
31620 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
31621 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
31622 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
31623 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
31624 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
31625 | //BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 |
31626 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
31627 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
31628 | //BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 |
31629 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
31630 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
31631 | //BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
31632 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
31633 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
31634 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
31635 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
31636 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
31637 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
31638 | //BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS |
31639 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
31640 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
31641 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
31642 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
31643 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
31644 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
31645 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
31646 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
31647 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
31648 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
31649 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
31650 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
31651 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
31652 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
31653 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
31654 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
31655 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
31656 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
31657 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
31658 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
31659 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
31660 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
31661 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
31662 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
31663 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
31664 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
31665 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
31666 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
31667 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
31668 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
31669 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
31670 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
31671 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
31672 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
31673 | //BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK |
31674 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
31675 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
31676 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
31677 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
31678 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
31679 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
31680 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
31681 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
31682 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
31683 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
31684 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
31685 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
31686 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
31687 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
31688 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
31689 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
31690 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
31691 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
31692 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
31693 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
31694 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
31695 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
31696 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
31697 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
31698 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
31699 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
31700 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
31701 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
31702 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
31703 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
31704 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
31705 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
31706 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
31707 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
31708 | //BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY |
31709 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
31710 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
31711 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
31712 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
31713 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
31714 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
31715 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
31716 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
31717 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
31718 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
31719 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
31720 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
31721 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
31722 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
31723 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
31724 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
31725 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
31726 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
31727 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
31728 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
31729 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
31730 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
31731 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
31732 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
31733 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
31734 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
31735 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
31736 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
31737 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
31738 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
31739 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
31740 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
31741 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
31742 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
31743 | //BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS |
31744 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
31745 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
31746 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
31747 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
31748 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
31749 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
31750 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
31751 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
31752 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
31753 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
31754 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
31755 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
31756 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
31757 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
31758 | //BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK |
31759 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
31760 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
31761 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
31762 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
31763 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
31764 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
31765 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
31766 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
31767 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
31768 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
31769 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
31770 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
31771 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
31772 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
31773 | //BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL |
31774 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
31775 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
31776 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
31777 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
31778 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
31779 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
31780 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
31781 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
31782 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
31783 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
31784 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
31785 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
31786 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
31787 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
31788 | //BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 |
31789 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
31790 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
31791 | //BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 |
31792 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
31793 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
31794 | //BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 |
31795 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
31796 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
31797 | //BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 |
31798 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
31799 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
31800 | //BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 |
31801 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
31802 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
31803 | //BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 |
31804 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
31805 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
31806 | //BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 |
31807 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
31808 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
31809 | //BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 |
31810 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
31811 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
31812 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST |
31813 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
31814 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
31815 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
31816 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
31817 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
31818 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
31819 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP |
31820 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
31821 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
31822 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL |
31823 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
31824 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
31825 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
31826 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
31827 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
31828 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
31829 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
31830 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
31831 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP |
31832 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
31833 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
31834 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL |
31835 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
31836 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
31837 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
31838 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
31839 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
31840 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
31841 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
31842 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
31843 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP |
31844 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
31845 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
31846 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL |
31847 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
31848 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
31849 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
31850 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
31851 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
31852 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
31853 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
31854 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
31855 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP |
31856 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
31857 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
31858 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL |
31859 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
31860 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
31861 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
31862 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
31863 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
31864 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
31865 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
31866 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
31867 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP |
31868 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
31869 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
31870 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL |
31871 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
31872 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
31873 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
31874 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
31875 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
31876 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
31877 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
31878 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
31879 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP |
31880 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
31881 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
31882 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL |
31883 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
31884 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
31885 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
31886 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
31887 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
31888 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
31889 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
31890 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
31891 | //BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
31892 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
31893 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
31894 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
31895 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
31896 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
31897 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
31898 | //BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT |
31899 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
31900 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
31901 | //BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA |
31902 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
31903 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
31904 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
31905 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
31906 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
31907 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
31908 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
31909 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
31910 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
31911 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
31912 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
31913 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
31914 | //BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP |
31915 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
31916 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
31917 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST |
31918 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
31919 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
31920 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
31921 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
31922 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
31923 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
31924 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP |
31925 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
31926 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
31927 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
31928 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
31929 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
31930 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
31931 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
31932 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
31933 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
31934 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
31935 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR |
31936 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
31937 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
31938 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS |
31939 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
31940 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
31941 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
31942 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
31943 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL |
31944 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
31945 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
31946 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
31947 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
31948 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
31949 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
31950 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
31951 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
31952 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
31953 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
31954 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
31955 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
31956 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
31957 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
31958 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
31959 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
31960 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
31961 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
31962 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
31963 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
31964 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
31965 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
31966 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
31967 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
31968 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
31969 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
31970 | //BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST |
31971 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
31972 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
31973 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
31974 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
31975 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
31976 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
31977 | //BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP |
31978 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
31979 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
31980 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
31981 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
31982 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
31983 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
31984 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
31985 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
31986 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
31987 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
31988 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
31989 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
31990 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
31991 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
31992 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
31993 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
31994 | //BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL |
31995 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
31996 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
31997 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
31998 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
31999 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
32000 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
32001 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
32002 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
32003 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
32004 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
32005 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
32006 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
32007 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
32008 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
32009 | //BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST |
32010 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
32011 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
32012 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
32013 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
32014 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
32015 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
32016 | //BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP |
32017 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
32018 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
32019 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
32020 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
32021 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
32022 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
32023 | //BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL |
32024 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
32025 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
32026 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
32027 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
32028 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
32029 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
32030 | //BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST |
32031 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
32032 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
32033 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
32034 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
32035 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
32036 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
32037 | //BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP |
32038 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
32039 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
32040 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
32041 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
32042 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
32043 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
32044 | //BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL |
32045 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
32046 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
32047 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
32048 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
32049 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
32050 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
32051 | //BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST |
32052 | #define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
32053 | #define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
32054 | #define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
32055 | #define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
32056 | #define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
32057 | #define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
32058 | //BIF_CFG_DEV0_EPF3_0_RTR_DATA1 |
32059 | #define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
32060 | #define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
32061 | #define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__VALID__SHIFT 0x1f |
32062 | #define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
32063 | #define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
32064 | #define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__VALID_MASK 0x80000000L |
32065 | //BIF_CFG_DEV0_EPF3_0_RTR_DATA2 |
32066 | #define BIF_CFG_DEV0_EPF3_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
32067 | #define BIF_CFG_DEV0_EPF3_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
32068 | #define BIF_CFG_DEV0_EPF3_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
32069 | #define BIF_CFG_DEV0_EPF3_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
32070 | |
32071 | |
32072 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp |
32073 | //BIF_CFG_DEV0_EPF4_0_VENDOR_ID |
32074 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
32075 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
32076 | //BIF_CFG_DEV0_EPF4_0_DEVICE_ID |
32077 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
32078 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
32079 | //BIF_CFG_DEV0_EPF4_0_COMMAND |
32080 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
32081 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
32082 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
32083 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
32084 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
32085 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
32086 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
32087 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN__SHIFT 0x8 |
32088 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
32089 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS__SHIFT 0xa |
32090 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
32091 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
32092 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
32093 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
32094 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
32095 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
32096 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING_MASK 0x0080L |
32097 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN_MASK 0x0100L |
32098 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
32099 | #define BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS_MASK 0x0400L |
32100 | //BIF_CFG_DEV0_EPF4_0_STATUS |
32101 | #define BIF_CFG_DEV0_EPF4_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
32102 | #define BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS__SHIFT 0x3 |
32103 | #define BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST__SHIFT 0x4 |
32104 | #define BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
32105 | #define BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
32106 | #define BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
32107 | #define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
32108 | #define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
32109 | #define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
32110 | #define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
32111 | #define BIF_CFG_DEV0_EPF4_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
32112 | #define BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS_MASK 0x0008L |
32113 | #define BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST_MASK 0x0010L |
32114 | #define BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_CAP_MASK 0x0020L |
32115 | #define BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
32116 | #define BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
32117 | #define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
32118 | #define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
32119 | #define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
32120 | #define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
32121 | //BIF_CFG_DEV0_EPF4_0_REVISION_ID |
32122 | #define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
32123 | #define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
32124 | #define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
32125 | #define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
32126 | //BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE |
32127 | #define BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
32128 | #define BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
32129 | //BIF_CFG_DEV0_EPF4_0_SUB_CLASS |
32130 | #define BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
32131 | #define BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
32132 | //BIF_CFG_DEV0_EPF4_0_BASE_CLASS |
32133 | #define BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
32134 | #define BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
32135 | //BIF_CFG_DEV0_EPF4_0_CACHE_LINE |
32136 | #define BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
32137 | #define BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
32138 | //BIF_CFG_DEV0_EPF4_0_LATENCY |
32139 | #define BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
32140 | #define BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
32141 | //BIF_CFG_DEV0_EPF4_0_HEADER |
32142 | #define 0x0 |
32143 | #define 0x7 |
32144 | #define 0x7FL |
32145 | #define 0x80L |
32146 | //BIF_CFG_DEV0_EPF4_0_BIST |
32147 | #define BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP__SHIFT 0x0 |
32148 | #define BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT__SHIFT 0x6 |
32149 | #define BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP__SHIFT 0x7 |
32150 | #define BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP_MASK 0x0FL |
32151 | #define BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT_MASK 0x40L |
32152 | #define BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP_MASK 0x80L |
32153 | //BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1 |
32154 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
32155 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
32156 | //BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2 |
32157 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
32158 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
32159 | //BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3 |
32160 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
32161 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
32162 | //BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4 |
32163 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
32164 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
32165 | //BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5 |
32166 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
32167 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
32168 | //BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6 |
32169 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
32170 | #define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
32171 | //BIF_CFG_DEV0_EPF4_0_ADAPTER_ID |
32172 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
32173 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
32174 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
32175 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
32176 | //BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR |
32177 | #define BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
32178 | #define BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
32179 | //BIF_CFG_DEV0_EPF4_0_CAP_PTR |
32180 | #define BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
32181 | #define BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
32182 | //BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE |
32183 | #define BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
32184 | #define BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
32185 | //BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN |
32186 | #define BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
32187 | #define BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
32188 | //BIF_CFG_DEV0_EPF4_0_MIN_GRANT |
32189 | #define BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
32190 | #define BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
32191 | //BIF_CFG_DEV0_EPF4_0_MAX_LATENCY |
32192 | #define BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
32193 | #define BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
32194 | //BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST |
32195 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
32196 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
32197 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
32198 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
32199 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
32200 | #define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
32201 | //BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W |
32202 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
32203 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
32204 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
32205 | #define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
32206 | //BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST |
32207 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
32208 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
32209 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
32210 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
32211 | //BIF_CFG_DEV0_EPF4_0_PMI_CAP |
32212 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION__SHIFT 0x0 |
32213 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
32214 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
32215 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
32216 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
32217 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
32218 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
32219 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
32220 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION_MASK 0x0007L |
32221 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
32222 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
32223 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
32224 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
32225 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
32226 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
32227 | #define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
32228 | //BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL |
32229 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
32230 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
32231 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
32232 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
32233 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
32234 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
32235 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
32236 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
32237 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
32238 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
32239 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
32240 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
32241 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
32242 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
32243 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
32244 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
32245 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
32246 | #define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
32247 | //BIF_CFG_DEV0_EPF4_0_SBRN |
32248 | #define BIF_CFG_DEV0_EPF4_0_SBRN__SBRN__SHIFT 0x0 |
32249 | #define BIF_CFG_DEV0_EPF4_0_SBRN__SBRN_MASK 0xFFL |
32250 | //BIF_CFG_DEV0_EPF4_0_FLADJ |
32251 | #define BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ__SHIFT 0x0 |
32252 | #define BIF_CFG_DEV0_EPF4_0_FLADJ__NFC__SHIFT 0x6 |
32253 | #define BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ_MASK 0x3FL |
32254 | #define BIF_CFG_DEV0_EPF4_0_FLADJ__NFC_MASK 0x40L |
32255 | //BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD |
32256 | #define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
32257 | #define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
32258 | #define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
32259 | #define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
32260 | //BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST |
32261 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
32262 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
32263 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
32264 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
32265 | //BIF_CFG_DEV0_EPF4_0_PCIE_CAP |
32266 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION__SHIFT 0x0 |
32267 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
32268 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
32269 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
32270 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION_MASK 0x000FL |
32271 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
32272 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
32273 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
32274 | //BIF_CFG_DEV0_EPF4_0_DEVICE_CAP |
32275 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
32276 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
32277 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
32278 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
32279 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
32280 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
32281 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
32282 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
32283 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
32284 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
32285 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
32286 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
32287 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
32288 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
32289 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
32290 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
32291 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
32292 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
32293 | //BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL |
32294 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
32295 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
32296 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
32297 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
32298 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
32299 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
32300 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
32301 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
32302 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
32303 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
32304 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
32305 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
32306 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
32307 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
32308 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
32309 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
32310 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
32311 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
32312 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
32313 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
32314 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
32315 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
32316 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
32317 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
32318 | //BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS |
32319 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
32320 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
32321 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
32322 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
32323 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
32324 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
32325 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
32326 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
32327 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
32328 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
32329 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
32330 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
32331 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
32332 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
32333 | //BIF_CFG_DEV0_EPF4_0_LINK_CAP |
32334 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
32335 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
32336 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
32337 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
32338 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
32339 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
32340 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
32341 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
32342 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
32343 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
32344 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
32345 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
32346 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
32347 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
32348 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
32349 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
32350 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
32351 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
32352 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
32353 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
32354 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
32355 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
32356 | //BIF_CFG_DEV0_EPF4_0_LINK_CNTL |
32357 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
32358 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
32359 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
32360 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
32361 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
32362 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
32363 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
32364 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
32365 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
32366 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
32367 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
32368 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
32369 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
32370 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
32371 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
32372 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
32373 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
32374 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
32375 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
32376 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
32377 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
32378 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
32379 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
32380 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
32381 | //BIF_CFG_DEV0_EPF4_0_LINK_STATUS |
32382 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
32383 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
32384 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
32385 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
32386 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
32387 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
32388 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
32389 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
32390 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
32391 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
32392 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
32393 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
32394 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
32395 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
32396 | //BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2 |
32397 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
32398 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
32399 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
32400 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
32401 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
32402 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
32403 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
32404 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
32405 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
32406 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
32407 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
32408 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
32409 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
32410 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
32411 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
32412 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
32413 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
32414 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
32415 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
32416 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
32417 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
32418 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
32419 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
32420 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
32421 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
32422 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
32423 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
32424 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
32425 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
32426 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
32427 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
32428 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
32429 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
32430 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
32431 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
32432 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
32433 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
32434 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
32435 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
32436 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
32437 | //BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2 |
32438 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
32439 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
32440 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
32441 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
32442 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
32443 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
32444 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
32445 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
32446 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
32447 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
32448 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
32449 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
32450 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
32451 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
32452 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
32453 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
32454 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
32455 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
32456 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
32457 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
32458 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
32459 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
32460 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
32461 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
32462 | //BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2 |
32463 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
32464 | #define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
32465 | //BIF_CFG_DEV0_EPF4_0_LINK_CAP2 |
32466 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
32467 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
32468 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
32469 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
32470 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
32471 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
32472 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
32473 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
32474 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
32475 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
32476 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
32477 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
32478 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
32479 | #define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
32480 | //BIF_CFG_DEV0_EPF4_0_LINK_CNTL2 |
32481 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
32482 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
32483 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
32484 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
32485 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
32486 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
32487 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
32488 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
32489 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
32490 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
32491 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
32492 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
32493 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
32494 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
32495 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
32496 | #define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
32497 | //BIF_CFG_DEV0_EPF4_0_LINK_STATUS2 |
32498 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
32499 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
32500 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
32501 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
32502 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
32503 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
32504 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
32505 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
32506 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
32507 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
32508 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
32509 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
32510 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
32511 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
32512 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
32513 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
32514 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
32515 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
32516 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
32517 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
32518 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
32519 | #define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
32520 | //BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST |
32521 | #define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
32522 | #define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
32523 | #define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
32524 | #define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
32525 | //BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL |
32526 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
32527 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
32528 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
32529 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
32530 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
32531 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
32532 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
32533 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
32534 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
32535 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
32536 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
32537 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
32538 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
32539 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
32540 | //BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO |
32541 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
32542 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
32543 | //BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI |
32544 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
32545 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
32546 | //BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA |
32547 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
32548 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
32549 | //BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA |
32550 | #define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
32551 | #define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
32552 | //BIF_CFG_DEV0_EPF4_0_MSI_MASK |
32553 | #define BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
32554 | #define BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
32555 | //BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64 |
32556 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
32557 | #define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
32558 | //BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64 |
32559 | #define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
32560 | #define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
32561 | //BIF_CFG_DEV0_EPF4_0_MSI_MASK_64 |
32562 | #define BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
32563 | #define BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
32564 | //BIF_CFG_DEV0_EPF4_0_MSI_PENDING |
32565 | #define BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
32566 | #define BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
32567 | //BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64 |
32568 | #define BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
32569 | #define BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
32570 | //BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST |
32571 | #define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
32572 | #define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
32573 | #define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
32574 | #define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
32575 | //BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL |
32576 | #define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
32577 | #define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
32578 | #define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
32579 | #define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
32580 | #define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
32581 | #define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
32582 | //BIF_CFG_DEV0_EPF4_0_MSIX_TABLE |
32583 | #define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
32584 | #define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
32585 | #define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
32586 | #define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
32587 | //BIF_CFG_DEV0_EPF4_0_MSIX_PBA |
32588 | #define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
32589 | #define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
32590 | #define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
32591 | #define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
32592 | //BIF_CFG_DEV0_EPF4_0_SATA_CAP_0 |
32593 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
32594 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
32595 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
32596 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
32597 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
32598 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
32599 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
32600 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
32601 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
32602 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
32603 | //BIF_CFG_DEV0_EPF4_0_SATA_CAP_1 |
32604 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
32605 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
32606 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
32607 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
32608 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
32609 | #define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
32610 | //BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX |
32611 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
32612 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
32613 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
32614 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
32615 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
32616 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
32617 | //BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA |
32618 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
32619 | #define BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
32620 | //BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
32621 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
32622 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
32623 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
32624 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
32625 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
32626 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
32627 | //BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR |
32628 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
32629 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
32630 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
32631 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
32632 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
32633 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
32634 | //BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1 |
32635 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
32636 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
32637 | //BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2 |
32638 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
32639 | #define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
32640 | //BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
32641 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
32642 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
32643 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
32644 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
32645 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
32646 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
32647 | //BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS |
32648 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
32649 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
32650 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
32651 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
32652 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
32653 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
32654 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
32655 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
32656 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
32657 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
32658 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
32659 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
32660 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
32661 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
32662 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
32663 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
32664 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
32665 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
32666 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
32667 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
32668 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
32669 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
32670 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
32671 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
32672 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
32673 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
32674 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
32675 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
32676 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
32677 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
32678 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
32679 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
32680 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
32681 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
32682 | //BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK |
32683 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
32684 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
32685 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
32686 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
32687 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
32688 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
32689 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
32690 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
32691 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
32692 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
32693 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
32694 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
32695 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
32696 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
32697 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
32698 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
32699 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
32700 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
32701 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
32702 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
32703 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
32704 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
32705 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
32706 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
32707 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
32708 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
32709 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
32710 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
32711 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
32712 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
32713 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
32714 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
32715 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
32716 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
32717 | //BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY |
32718 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
32719 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
32720 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
32721 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
32722 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
32723 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
32724 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
32725 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
32726 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
32727 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
32728 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
32729 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
32730 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
32731 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
32732 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
32733 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
32734 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
32735 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
32736 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
32737 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
32738 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
32739 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
32740 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
32741 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
32742 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
32743 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
32744 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
32745 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
32746 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
32747 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
32748 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
32749 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
32750 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
32751 | #define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
32752 | //BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS |
32753 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
32754 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
32755 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
32756 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
32757 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
32758 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
32759 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
32760 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
32761 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
32762 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
32763 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
32764 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
32765 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
32766 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
32767 | //BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK |
32768 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
32769 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
32770 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
32771 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
32772 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
32773 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
32774 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
32775 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
32776 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
32777 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
32778 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
32779 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
32780 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
32781 | #define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
32782 | //BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL |
32783 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
32784 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
32785 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
32786 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
32787 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
32788 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
32789 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
32790 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
32791 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
32792 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
32793 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
32794 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
32795 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
32796 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
32797 | //BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0 |
32798 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
32799 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
32800 | //BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1 |
32801 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
32802 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
32803 | //BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2 |
32804 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
32805 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
32806 | //BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3 |
32807 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
32808 | #define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
32809 | //BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0 |
32810 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
32811 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
32812 | //BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1 |
32813 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
32814 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
32815 | //BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2 |
32816 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
32817 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
32818 | //BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3 |
32819 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
32820 | #define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
32821 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST |
32822 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
32823 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
32824 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
32825 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
32826 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
32827 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
32828 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP |
32829 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
32830 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
32831 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL |
32832 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
32833 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
32834 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
32835 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
32836 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
32837 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
32838 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
32839 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
32840 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP |
32841 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
32842 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
32843 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL |
32844 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
32845 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
32846 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
32847 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
32848 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
32849 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
32850 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
32851 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
32852 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP |
32853 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
32854 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
32855 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL |
32856 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
32857 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
32858 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
32859 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
32860 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
32861 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
32862 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
32863 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
32864 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP |
32865 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
32866 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
32867 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL |
32868 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
32869 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
32870 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
32871 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
32872 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
32873 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
32874 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
32875 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
32876 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP |
32877 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
32878 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
32879 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL |
32880 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
32881 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
32882 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
32883 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
32884 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
32885 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
32886 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
32887 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
32888 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP |
32889 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
32890 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
32891 | //BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL |
32892 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
32893 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
32894 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
32895 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
32896 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
32897 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
32898 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
32899 | #define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
32900 | //BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
32901 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
32902 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
32903 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
32904 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
32905 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
32906 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
32907 | //BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT |
32908 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
32909 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
32910 | //BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA |
32911 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
32912 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
32913 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
32914 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
32915 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
32916 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
32917 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
32918 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
32919 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
32920 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
32921 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
32922 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
32923 | //BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP |
32924 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
32925 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
32926 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST |
32927 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
32928 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
32929 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
32930 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
32931 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
32932 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
32933 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP |
32934 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
32935 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
32936 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
32937 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
32938 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
32939 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
32940 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
32941 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
32942 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
32943 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
32944 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR |
32945 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
32946 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
32947 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS |
32948 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
32949 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
32950 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
32951 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
32952 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL |
32953 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
32954 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
32955 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
32956 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
32957 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
32958 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
32959 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
32960 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
32961 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
32962 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
32963 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
32964 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
32965 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
32966 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
32967 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
32968 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
32969 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
32970 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
32971 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
32972 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
32973 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
32974 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
32975 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
32976 | //BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
32977 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
32978 | #define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
32979 | //BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST |
32980 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
32981 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
32982 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
32983 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
32984 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
32985 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
32986 | //BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP |
32987 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
32988 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
32989 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
32990 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
32991 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
32992 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
32993 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
32994 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
32995 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
32996 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
32997 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
32998 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
32999 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
33000 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
33001 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
33002 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
33003 | //BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL |
33004 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
33005 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
33006 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
33007 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
33008 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
33009 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
33010 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
33011 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
33012 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
33013 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
33014 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
33015 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
33016 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
33017 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
33018 | //BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST |
33019 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
33020 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
33021 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
33022 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
33023 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
33024 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
33025 | //BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP |
33026 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
33027 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
33028 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
33029 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
33030 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
33031 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
33032 | //BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL |
33033 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
33034 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
33035 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
33036 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
33037 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
33038 | #define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
33039 | //BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST |
33040 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
33041 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
33042 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
33043 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
33044 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
33045 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
33046 | //BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP |
33047 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
33048 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
33049 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
33050 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
33051 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
33052 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
33053 | //BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL |
33054 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
33055 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
33056 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
33057 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
33058 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
33059 | #define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
33060 | //BIF_CFG_DEV0_EPF4_0_PCIE_RTR_ENH_CAP_LIST |
33061 | #define BIF_CFG_DEV0_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
33062 | #define BIF_CFG_DEV0_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
33063 | #define BIF_CFG_DEV0_EPF4_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
33064 | #define BIF_CFG_DEV0_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
33065 | #define BIF_CFG_DEV0_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
33066 | #define BIF_CFG_DEV0_EPF4_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
33067 | //BIF_CFG_DEV0_EPF4_0_RTR_DATA1 |
33068 | #define BIF_CFG_DEV0_EPF4_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
33069 | #define BIF_CFG_DEV0_EPF4_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
33070 | #define BIF_CFG_DEV0_EPF4_0_RTR_DATA1__VALID__SHIFT 0x1f |
33071 | #define BIF_CFG_DEV0_EPF4_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
33072 | #define BIF_CFG_DEV0_EPF4_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
33073 | #define BIF_CFG_DEV0_EPF4_0_RTR_DATA1__VALID_MASK 0x80000000L |
33074 | //BIF_CFG_DEV0_EPF4_0_RTR_DATA2 |
33075 | #define BIF_CFG_DEV0_EPF4_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
33076 | #define BIF_CFG_DEV0_EPF4_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
33077 | #define BIF_CFG_DEV0_EPF4_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
33078 | #define BIF_CFG_DEV0_EPF4_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
33079 | |
33080 | |
33081 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp |
33082 | //BIF_CFG_DEV0_EPF5_0_VENDOR_ID |
33083 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
33084 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
33085 | //BIF_CFG_DEV0_EPF5_0_DEVICE_ID |
33086 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
33087 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
33088 | //BIF_CFG_DEV0_EPF5_0_COMMAND |
33089 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
33090 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
33091 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
33092 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
33093 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
33094 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
33095 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
33096 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN__SHIFT 0x8 |
33097 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
33098 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS__SHIFT 0xa |
33099 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
33100 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
33101 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
33102 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
33103 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
33104 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
33105 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING_MASK 0x0080L |
33106 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN_MASK 0x0100L |
33107 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
33108 | #define BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS_MASK 0x0400L |
33109 | //BIF_CFG_DEV0_EPF5_0_STATUS |
33110 | #define BIF_CFG_DEV0_EPF5_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
33111 | #define BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS__SHIFT 0x3 |
33112 | #define BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST__SHIFT 0x4 |
33113 | #define BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
33114 | #define BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
33115 | #define BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
33116 | #define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
33117 | #define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
33118 | #define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
33119 | #define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
33120 | #define BIF_CFG_DEV0_EPF5_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
33121 | #define BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS_MASK 0x0008L |
33122 | #define BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST_MASK 0x0010L |
33123 | #define BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_CAP_MASK 0x0020L |
33124 | #define BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
33125 | #define BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
33126 | #define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
33127 | #define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
33128 | #define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
33129 | #define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
33130 | //BIF_CFG_DEV0_EPF5_0_REVISION_ID |
33131 | #define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
33132 | #define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
33133 | #define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
33134 | #define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
33135 | //BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE |
33136 | #define BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
33137 | #define BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
33138 | //BIF_CFG_DEV0_EPF5_0_SUB_CLASS |
33139 | #define BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
33140 | #define BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
33141 | //BIF_CFG_DEV0_EPF5_0_BASE_CLASS |
33142 | #define BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
33143 | #define BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
33144 | //BIF_CFG_DEV0_EPF5_0_CACHE_LINE |
33145 | #define BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
33146 | #define BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
33147 | //BIF_CFG_DEV0_EPF5_0_LATENCY |
33148 | #define BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
33149 | #define BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
33150 | //BIF_CFG_DEV0_EPF5_0_HEADER |
33151 | #define 0x0 |
33152 | #define 0x7 |
33153 | #define 0x7FL |
33154 | #define 0x80L |
33155 | //BIF_CFG_DEV0_EPF5_0_BIST |
33156 | #define BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP__SHIFT 0x0 |
33157 | #define BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT__SHIFT 0x6 |
33158 | #define BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP__SHIFT 0x7 |
33159 | #define BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP_MASK 0x0FL |
33160 | #define BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT_MASK 0x40L |
33161 | #define BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP_MASK 0x80L |
33162 | //BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1 |
33163 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
33164 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
33165 | //BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2 |
33166 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
33167 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
33168 | //BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3 |
33169 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
33170 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
33171 | //BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4 |
33172 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
33173 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
33174 | //BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5 |
33175 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
33176 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
33177 | //BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6 |
33178 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
33179 | #define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
33180 | //BIF_CFG_DEV0_EPF5_0_ADAPTER_ID |
33181 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
33182 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
33183 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
33184 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
33185 | //BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR |
33186 | #define BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
33187 | #define BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
33188 | //BIF_CFG_DEV0_EPF5_0_CAP_PTR |
33189 | #define BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
33190 | #define BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
33191 | //BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE |
33192 | #define BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
33193 | #define BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
33194 | //BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN |
33195 | #define BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
33196 | #define BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
33197 | //BIF_CFG_DEV0_EPF5_0_MIN_GRANT |
33198 | #define BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
33199 | #define BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
33200 | //BIF_CFG_DEV0_EPF5_0_MAX_LATENCY |
33201 | #define BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
33202 | #define BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
33203 | //BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST |
33204 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
33205 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
33206 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
33207 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
33208 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
33209 | #define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
33210 | //BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W |
33211 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
33212 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
33213 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
33214 | #define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
33215 | //BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST |
33216 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
33217 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
33218 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
33219 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
33220 | //BIF_CFG_DEV0_EPF5_0_PMI_CAP |
33221 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION__SHIFT 0x0 |
33222 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
33223 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
33224 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
33225 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
33226 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
33227 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
33228 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
33229 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION_MASK 0x0007L |
33230 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
33231 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
33232 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
33233 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
33234 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
33235 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
33236 | #define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
33237 | //BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL |
33238 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
33239 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
33240 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
33241 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
33242 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
33243 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
33244 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
33245 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
33246 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
33247 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
33248 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
33249 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
33250 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
33251 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
33252 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
33253 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
33254 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
33255 | #define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
33256 | //BIF_CFG_DEV0_EPF5_0_SBRN |
33257 | #define BIF_CFG_DEV0_EPF5_0_SBRN__SBRN__SHIFT 0x0 |
33258 | #define BIF_CFG_DEV0_EPF5_0_SBRN__SBRN_MASK 0xFFL |
33259 | //BIF_CFG_DEV0_EPF5_0_FLADJ |
33260 | #define BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ__SHIFT 0x0 |
33261 | #define BIF_CFG_DEV0_EPF5_0_FLADJ__NFC__SHIFT 0x6 |
33262 | #define BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ_MASK 0x3FL |
33263 | #define BIF_CFG_DEV0_EPF5_0_FLADJ__NFC_MASK 0x40L |
33264 | //BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD |
33265 | #define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
33266 | #define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
33267 | #define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
33268 | #define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
33269 | //BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST |
33270 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
33271 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
33272 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
33273 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
33274 | //BIF_CFG_DEV0_EPF5_0_PCIE_CAP |
33275 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION__SHIFT 0x0 |
33276 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
33277 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
33278 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
33279 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION_MASK 0x000FL |
33280 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
33281 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
33282 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
33283 | //BIF_CFG_DEV0_EPF5_0_DEVICE_CAP |
33284 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
33285 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
33286 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
33287 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
33288 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
33289 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
33290 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
33291 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
33292 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
33293 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
33294 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
33295 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
33296 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
33297 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
33298 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
33299 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
33300 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
33301 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
33302 | //BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL |
33303 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
33304 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
33305 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
33306 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
33307 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
33308 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
33309 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
33310 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
33311 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
33312 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
33313 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
33314 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
33315 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
33316 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
33317 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
33318 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
33319 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
33320 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
33321 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
33322 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
33323 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
33324 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
33325 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
33326 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
33327 | //BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS |
33328 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
33329 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
33330 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
33331 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
33332 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
33333 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
33334 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
33335 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
33336 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
33337 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
33338 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
33339 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
33340 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
33341 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
33342 | //BIF_CFG_DEV0_EPF5_0_LINK_CAP |
33343 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
33344 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
33345 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
33346 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
33347 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
33348 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
33349 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
33350 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
33351 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
33352 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
33353 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
33354 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
33355 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
33356 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
33357 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
33358 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
33359 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
33360 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
33361 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
33362 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
33363 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
33364 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
33365 | //BIF_CFG_DEV0_EPF5_0_LINK_CNTL |
33366 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
33367 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
33368 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
33369 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
33370 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
33371 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
33372 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
33373 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
33374 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
33375 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
33376 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
33377 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
33378 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
33379 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
33380 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
33381 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
33382 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
33383 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
33384 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
33385 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
33386 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
33387 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
33388 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
33389 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
33390 | //BIF_CFG_DEV0_EPF5_0_LINK_STATUS |
33391 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
33392 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
33393 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
33394 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
33395 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
33396 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
33397 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
33398 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
33399 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
33400 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
33401 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
33402 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
33403 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
33404 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
33405 | //BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2 |
33406 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
33407 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
33408 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
33409 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
33410 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
33411 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
33412 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
33413 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
33414 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
33415 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
33416 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
33417 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
33418 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
33419 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
33420 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
33421 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
33422 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
33423 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
33424 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
33425 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
33426 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
33427 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
33428 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
33429 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
33430 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
33431 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
33432 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
33433 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
33434 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
33435 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
33436 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
33437 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
33438 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
33439 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
33440 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
33441 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
33442 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
33443 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
33444 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
33445 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
33446 | //BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2 |
33447 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
33448 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
33449 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
33450 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
33451 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
33452 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
33453 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
33454 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
33455 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
33456 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
33457 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
33458 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
33459 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
33460 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
33461 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
33462 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
33463 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
33464 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
33465 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
33466 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
33467 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
33468 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
33469 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
33470 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
33471 | //BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2 |
33472 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
33473 | #define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
33474 | //BIF_CFG_DEV0_EPF5_0_LINK_CAP2 |
33475 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
33476 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
33477 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
33478 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
33479 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
33480 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
33481 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
33482 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
33483 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
33484 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
33485 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
33486 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
33487 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
33488 | #define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
33489 | //BIF_CFG_DEV0_EPF5_0_LINK_CNTL2 |
33490 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
33491 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
33492 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
33493 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
33494 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
33495 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
33496 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
33497 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
33498 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
33499 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
33500 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
33501 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
33502 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
33503 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
33504 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
33505 | #define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
33506 | //BIF_CFG_DEV0_EPF5_0_LINK_STATUS2 |
33507 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
33508 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
33509 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
33510 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
33511 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
33512 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
33513 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
33514 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
33515 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
33516 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
33517 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
33518 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
33519 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
33520 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
33521 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
33522 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
33523 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
33524 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
33525 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
33526 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
33527 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
33528 | #define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
33529 | //BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST |
33530 | #define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
33531 | #define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
33532 | #define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
33533 | #define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
33534 | //BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL |
33535 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
33536 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
33537 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
33538 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
33539 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
33540 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
33541 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
33542 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
33543 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
33544 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
33545 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
33546 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
33547 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
33548 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
33549 | //BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO |
33550 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
33551 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
33552 | //BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI |
33553 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
33554 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
33555 | //BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA |
33556 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
33557 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
33558 | //BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA |
33559 | #define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
33560 | #define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
33561 | //BIF_CFG_DEV0_EPF5_0_MSI_MASK |
33562 | #define BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
33563 | #define BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
33564 | //BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64 |
33565 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
33566 | #define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
33567 | //BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64 |
33568 | #define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
33569 | #define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
33570 | //BIF_CFG_DEV0_EPF5_0_MSI_MASK_64 |
33571 | #define BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
33572 | #define BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
33573 | //BIF_CFG_DEV0_EPF5_0_MSI_PENDING |
33574 | #define BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
33575 | #define BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
33576 | //BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64 |
33577 | #define BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
33578 | #define BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
33579 | //BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST |
33580 | #define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
33581 | #define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
33582 | #define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
33583 | #define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
33584 | //BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL |
33585 | #define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
33586 | #define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
33587 | #define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
33588 | #define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
33589 | #define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
33590 | #define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
33591 | //BIF_CFG_DEV0_EPF5_0_MSIX_TABLE |
33592 | #define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
33593 | #define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
33594 | #define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
33595 | #define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
33596 | //BIF_CFG_DEV0_EPF5_0_MSIX_PBA |
33597 | #define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
33598 | #define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
33599 | #define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
33600 | #define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
33601 | //BIF_CFG_DEV0_EPF5_0_SATA_CAP_0 |
33602 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
33603 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
33604 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
33605 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
33606 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
33607 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
33608 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
33609 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
33610 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
33611 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
33612 | //BIF_CFG_DEV0_EPF5_0_SATA_CAP_1 |
33613 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
33614 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
33615 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
33616 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
33617 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
33618 | #define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
33619 | //BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX |
33620 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
33621 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
33622 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
33623 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
33624 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
33625 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
33626 | //BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA |
33627 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
33628 | #define BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
33629 | //BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
33630 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
33631 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
33632 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
33633 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
33634 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
33635 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
33636 | //BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR |
33637 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
33638 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
33639 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
33640 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
33641 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
33642 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
33643 | //BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1 |
33644 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
33645 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
33646 | //BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2 |
33647 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
33648 | #define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
33649 | //BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
33650 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
33651 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
33652 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
33653 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
33654 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
33655 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
33656 | //BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS |
33657 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
33658 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
33659 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
33660 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
33661 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
33662 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
33663 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
33664 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
33665 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
33666 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
33667 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
33668 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
33669 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
33670 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
33671 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
33672 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
33673 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
33674 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
33675 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
33676 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
33677 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
33678 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
33679 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
33680 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
33681 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
33682 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
33683 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
33684 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
33685 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
33686 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
33687 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
33688 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
33689 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
33690 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
33691 | //BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK |
33692 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
33693 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
33694 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
33695 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
33696 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
33697 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
33698 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
33699 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
33700 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
33701 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
33702 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
33703 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
33704 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
33705 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
33706 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
33707 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
33708 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
33709 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
33710 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
33711 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
33712 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
33713 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
33714 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
33715 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
33716 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
33717 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
33718 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
33719 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
33720 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
33721 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
33722 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
33723 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
33724 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
33725 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
33726 | //BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY |
33727 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
33728 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
33729 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
33730 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
33731 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
33732 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
33733 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
33734 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
33735 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
33736 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
33737 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
33738 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
33739 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
33740 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
33741 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
33742 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
33743 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
33744 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
33745 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
33746 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
33747 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
33748 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
33749 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
33750 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
33751 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
33752 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
33753 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
33754 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
33755 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
33756 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
33757 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
33758 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
33759 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
33760 | #define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
33761 | //BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS |
33762 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
33763 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
33764 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
33765 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
33766 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
33767 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
33768 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
33769 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
33770 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
33771 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
33772 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
33773 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
33774 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
33775 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
33776 | //BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK |
33777 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
33778 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
33779 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
33780 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
33781 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
33782 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
33783 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
33784 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
33785 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
33786 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
33787 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
33788 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
33789 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
33790 | #define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
33791 | //BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL |
33792 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
33793 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
33794 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
33795 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
33796 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
33797 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
33798 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
33799 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
33800 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
33801 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
33802 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
33803 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
33804 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
33805 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
33806 | //BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0 |
33807 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
33808 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
33809 | //BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1 |
33810 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
33811 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
33812 | //BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2 |
33813 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
33814 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
33815 | //BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3 |
33816 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
33817 | #define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
33818 | //BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0 |
33819 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
33820 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
33821 | //BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1 |
33822 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
33823 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
33824 | //BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2 |
33825 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
33826 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
33827 | //BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3 |
33828 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
33829 | #define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
33830 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST |
33831 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
33832 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
33833 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
33834 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
33835 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
33836 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
33837 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP |
33838 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
33839 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
33840 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL |
33841 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
33842 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
33843 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
33844 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
33845 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
33846 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
33847 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
33848 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
33849 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP |
33850 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
33851 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
33852 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL |
33853 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
33854 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
33855 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
33856 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
33857 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
33858 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
33859 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
33860 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
33861 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP |
33862 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
33863 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
33864 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL |
33865 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
33866 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
33867 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
33868 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
33869 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
33870 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
33871 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
33872 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
33873 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP |
33874 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
33875 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
33876 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL |
33877 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
33878 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
33879 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
33880 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
33881 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
33882 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
33883 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
33884 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
33885 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP |
33886 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
33887 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
33888 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL |
33889 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
33890 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
33891 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
33892 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
33893 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
33894 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
33895 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
33896 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
33897 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP |
33898 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
33899 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
33900 | //BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL |
33901 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
33902 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
33903 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
33904 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
33905 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
33906 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
33907 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
33908 | #define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
33909 | //BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
33910 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
33911 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
33912 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
33913 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
33914 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
33915 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
33916 | //BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT |
33917 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
33918 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
33919 | //BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA |
33920 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
33921 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
33922 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
33923 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
33924 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
33925 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
33926 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
33927 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
33928 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
33929 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
33930 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
33931 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
33932 | //BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP |
33933 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
33934 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
33935 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST |
33936 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
33937 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
33938 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
33939 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
33940 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
33941 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
33942 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP |
33943 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
33944 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
33945 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
33946 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
33947 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
33948 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
33949 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
33950 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
33951 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
33952 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
33953 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR |
33954 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
33955 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
33956 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS |
33957 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
33958 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
33959 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
33960 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
33961 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL |
33962 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
33963 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
33964 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
33965 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33966 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33967 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
33968 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33969 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33970 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
33971 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33972 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33973 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
33974 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33975 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33976 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
33977 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33978 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33979 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
33980 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33981 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33982 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
33983 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33984 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33985 | //BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
33986 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
33987 | #define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
33988 | //BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST |
33989 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
33990 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
33991 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
33992 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
33993 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
33994 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
33995 | //BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP |
33996 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
33997 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
33998 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
33999 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
34000 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
34001 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
34002 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
34003 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
34004 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
34005 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
34006 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
34007 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
34008 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
34009 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
34010 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
34011 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
34012 | //BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL |
34013 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
34014 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
34015 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
34016 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
34017 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
34018 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
34019 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
34020 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
34021 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
34022 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
34023 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
34024 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
34025 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
34026 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
34027 | //BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST |
34028 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
34029 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
34030 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
34031 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
34032 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
34033 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
34034 | //BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP |
34035 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
34036 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
34037 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
34038 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
34039 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
34040 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
34041 | //BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL |
34042 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
34043 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
34044 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
34045 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
34046 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
34047 | #define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
34048 | //BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST |
34049 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
34050 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
34051 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
34052 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
34053 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
34054 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
34055 | //BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP |
34056 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
34057 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
34058 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
34059 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
34060 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
34061 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
34062 | //BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL |
34063 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
34064 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
34065 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
34066 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
34067 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
34068 | #define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
34069 | //BIF_CFG_DEV0_EPF5_0_PCIE_RTR_ENH_CAP_LIST |
34070 | #define BIF_CFG_DEV0_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
34071 | #define BIF_CFG_DEV0_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
34072 | #define BIF_CFG_DEV0_EPF5_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
34073 | #define BIF_CFG_DEV0_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
34074 | #define BIF_CFG_DEV0_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
34075 | #define BIF_CFG_DEV0_EPF5_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
34076 | //BIF_CFG_DEV0_EPF5_0_RTR_DATA1 |
34077 | #define BIF_CFG_DEV0_EPF5_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
34078 | #define BIF_CFG_DEV0_EPF5_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
34079 | #define BIF_CFG_DEV0_EPF5_0_RTR_DATA1__VALID__SHIFT 0x1f |
34080 | #define BIF_CFG_DEV0_EPF5_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
34081 | #define BIF_CFG_DEV0_EPF5_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
34082 | #define BIF_CFG_DEV0_EPF5_0_RTR_DATA1__VALID_MASK 0x80000000L |
34083 | //BIF_CFG_DEV0_EPF5_0_RTR_DATA2 |
34084 | #define BIF_CFG_DEV0_EPF5_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
34085 | #define BIF_CFG_DEV0_EPF5_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
34086 | #define BIF_CFG_DEV0_EPF5_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
34087 | #define BIF_CFG_DEV0_EPF5_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
34088 | |
34089 | |
34090 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp |
34091 | //BIF_CFG_DEV0_EPF6_0_VENDOR_ID |
34092 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
34093 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
34094 | //BIF_CFG_DEV0_EPF6_0_DEVICE_ID |
34095 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
34096 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
34097 | //BIF_CFG_DEV0_EPF6_0_COMMAND |
34098 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
34099 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
34100 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
34101 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
34102 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
34103 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
34104 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
34105 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN__SHIFT 0x8 |
34106 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
34107 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS__SHIFT 0xa |
34108 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
34109 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
34110 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
34111 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
34112 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
34113 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
34114 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING_MASK 0x0080L |
34115 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN_MASK 0x0100L |
34116 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
34117 | #define BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS_MASK 0x0400L |
34118 | //BIF_CFG_DEV0_EPF6_0_STATUS |
34119 | #define BIF_CFG_DEV0_EPF6_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
34120 | #define BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS__SHIFT 0x3 |
34121 | #define BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST__SHIFT 0x4 |
34122 | #define BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
34123 | #define BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
34124 | #define BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
34125 | #define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
34126 | #define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
34127 | #define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
34128 | #define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
34129 | #define BIF_CFG_DEV0_EPF6_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
34130 | #define BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS_MASK 0x0008L |
34131 | #define BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST_MASK 0x0010L |
34132 | #define BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_CAP_MASK 0x0020L |
34133 | #define BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
34134 | #define BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
34135 | #define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
34136 | #define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
34137 | #define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
34138 | #define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
34139 | //BIF_CFG_DEV0_EPF6_0_REVISION_ID |
34140 | #define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
34141 | #define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
34142 | #define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
34143 | #define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
34144 | //BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE |
34145 | #define BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
34146 | #define BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
34147 | //BIF_CFG_DEV0_EPF6_0_SUB_CLASS |
34148 | #define BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
34149 | #define BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
34150 | //BIF_CFG_DEV0_EPF6_0_BASE_CLASS |
34151 | #define BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
34152 | #define BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
34153 | //BIF_CFG_DEV0_EPF6_0_CACHE_LINE |
34154 | #define BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
34155 | #define BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
34156 | //BIF_CFG_DEV0_EPF6_0_LATENCY |
34157 | #define BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
34158 | #define BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
34159 | //BIF_CFG_DEV0_EPF6_0_HEADER |
34160 | #define 0x0 |
34161 | #define 0x7 |
34162 | #define 0x7FL |
34163 | #define 0x80L |
34164 | //BIF_CFG_DEV0_EPF6_0_BIST |
34165 | #define BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP__SHIFT 0x0 |
34166 | #define BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT__SHIFT 0x6 |
34167 | #define BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP__SHIFT 0x7 |
34168 | #define BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP_MASK 0x0FL |
34169 | #define BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT_MASK 0x40L |
34170 | #define BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP_MASK 0x80L |
34171 | //BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1 |
34172 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
34173 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
34174 | //BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2 |
34175 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
34176 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
34177 | //BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3 |
34178 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
34179 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
34180 | //BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4 |
34181 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
34182 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
34183 | //BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5 |
34184 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
34185 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
34186 | //BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6 |
34187 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
34188 | #define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
34189 | //BIF_CFG_DEV0_EPF6_0_ADAPTER_ID |
34190 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
34191 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
34192 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
34193 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
34194 | //BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR |
34195 | #define BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
34196 | #define BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
34197 | //BIF_CFG_DEV0_EPF6_0_CAP_PTR |
34198 | #define BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
34199 | #define BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
34200 | //BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE |
34201 | #define BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
34202 | #define BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
34203 | //BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN |
34204 | #define BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
34205 | #define BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
34206 | //BIF_CFG_DEV0_EPF6_0_MIN_GRANT |
34207 | #define BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
34208 | #define BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
34209 | //BIF_CFG_DEV0_EPF6_0_MAX_LATENCY |
34210 | #define BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
34211 | #define BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
34212 | //BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST |
34213 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
34214 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
34215 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
34216 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
34217 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
34218 | #define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
34219 | //BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W |
34220 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
34221 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
34222 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
34223 | #define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
34224 | //BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST |
34225 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
34226 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
34227 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
34228 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
34229 | //BIF_CFG_DEV0_EPF6_0_PMI_CAP |
34230 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION__SHIFT 0x0 |
34231 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
34232 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
34233 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
34234 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
34235 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
34236 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
34237 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
34238 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION_MASK 0x0007L |
34239 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
34240 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
34241 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
34242 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
34243 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
34244 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
34245 | #define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
34246 | //BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL |
34247 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
34248 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
34249 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
34250 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
34251 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
34252 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
34253 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
34254 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
34255 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
34256 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
34257 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
34258 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
34259 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
34260 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
34261 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
34262 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
34263 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
34264 | #define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
34265 | //BIF_CFG_DEV0_EPF6_0_SBRN |
34266 | #define BIF_CFG_DEV0_EPF6_0_SBRN__SBRN__SHIFT 0x0 |
34267 | #define BIF_CFG_DEV0_EPF6_0_SBRN__SBRN_MASK 0xFFL |
34268 | //BIF_CFG_DEV0_EPF6_0_FLADJ |
34269 | #define BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ__SHIFT 0x0 |
34270 | #define BIF_CFG_DEV0_EPF6_0_FLADJ__NFC__SHIFT 0x6 |
34271 | #define BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ_MASK 0x3FL |
34272 | #define BIF_CFG_DEV0_EPF6_0_FLADJ__NFC_MASK 0x40L |
34273 | //BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD |
34274 | #define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
34275 | #define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
34276 | #define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
34277 | #define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
34278 | //BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST |
34279 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
34280 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
34281 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
34282 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
34283 | //BIF_CFG_DEV0_EPF6_0_PCIE_CAP |
34284 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION__SHIFT 0x0 |
34285 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
34286 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
34287 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
34288 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION_MASK 0x000FL |
34289 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
34290 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
34291 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
34292 | //BIF_CFG_DEV0_EPF6_0_DEVICE_CAP |
34293 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
34294 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
34295 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
34296 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
34297 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
34298 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
34299 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
34300 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
34301 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
34302 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
34303 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
34304 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
34305 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
34306 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
34307 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
34308 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
34309 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
34310 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
34311 | //BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL |
34312 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
34313 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
34314 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
34315 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
34316 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
34317 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
34318 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
34319 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
34320 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
34321 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
34322 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
34323 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
34324 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
34325 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
34326 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
34327 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
34328 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
34329 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
34330 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
34331 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
34332 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
34333 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
34334 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
34335 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
34336 | //BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS |
34337 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
34338 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
34339 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
34340 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
34341 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
34342 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
34343 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
34344 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
34345 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
34346 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
34347 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
34348 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
34349 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
34350 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
34351 | //BIF_CFG_DEV0_EPF6_0_LINK_CAP |
34352 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
34353 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
34354 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
34355 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
34356 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
34357 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
34358 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
34359 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
34360 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
34361 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
34362 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
34363 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
34364 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
34365 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
34366 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
34367 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
34368 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
34369 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
34370 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
34371 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
34372 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
34373 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
34374 | //BIF_CFG_DEV0_EPF6_0_LINK_CNTL |
34375 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
34376 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
34377 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
34378 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
34379 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
34380 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
34381 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
34382 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
34383 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
34384 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
34385 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
34386 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
34387 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
34388 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
34389 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
34390 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
34391 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
34392 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
34393 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
34394 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
34395 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
34396 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
34397 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
34398 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
34399 | //BIF_CFG_DEV0_EPF6_0_LINK_STATUS |
34400 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
34401 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
34402 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
34403 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
34404 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
34405 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
34406 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
34407 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
34408 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
34409 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
34410 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
34411 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
34412 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
34413 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
34414 | //BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2 |
34415 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
34416 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
34417 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
34418 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
34419 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
34420 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
34421 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
34422 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
34423 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
34424 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
34425 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
34426 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
34427 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
34428 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
34429 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
34430 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
34431 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
34432 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
34433 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
34434 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
34435 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
34436 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
34437 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
34438 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
34439 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
34440 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
34441 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
34442 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
34443 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
34444 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
34445 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
34446 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
34447 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
34448 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
34449 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
34450 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
34451 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
34452 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
34453 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
34454 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
34455 | //BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2 |
34456 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
34457 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
34458 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
34459 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
34460 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
34461 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
34462 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
34463 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
34464 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
34465 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
34466 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
34467 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
34468 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
34469 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
34470 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
34471 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
34472 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
34473 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
34474 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
34475 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
34476 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
34477 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
34478 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
34479 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
34480 | //BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2 |
34481 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
34482 | #define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
34483 | //BIF_CFG_DEV0_EPF6_0_LINK_CAP2 |
34484 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
34485 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
34486 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
34487 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
34488 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
34489 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
34490 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
34491 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
34492 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
34493 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
34494 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
34495 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
34496 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
34497 | #define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
34498 | //BIF_CFG_DEV0_EPF6_0_LINK_CNTL2 |
34499 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
34500 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
34501 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
34502 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
34503 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
34504 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
34505 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
34506 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
34507 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
34508 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
34509 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
34510 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
34511 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
34512 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
34513 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
34514 | #define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
34515 | //BIF_CFG_DEV0_EPF6_0_LINK_STATUS2 |
34516 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
34517 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
34518 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
34519 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
34520 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
34521 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
34522 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
34523 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
34524 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
34525 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
34526 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
34527 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
34528 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
34529 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
34530 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
34531 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
34532 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
34533 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
34534 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
34535 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
34536 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
34537 | #define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
34538 | //BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST |
34539 | #define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
34540 | #define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
34541 | #define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
34542 | #define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
34543 | //BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL |
34544 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
34545 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
34546 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
34547 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
34548 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
34549 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
34550 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
34551 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
34552 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
34553 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
34554 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
34555 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
34556 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
34557 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
34558 | //BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO |
34559 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
34560 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
34561 | //BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI |
34562 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
34563 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
34564 | //BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA |
34565 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
34566 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
34567 | //BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA |
34568 | #define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
34569 | #define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
34570 | //BIF_CFG_DEV0_EPF6_0_MSI_MASK |
34571 | #define BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
34572 | #define BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
34573 | //BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64 |
34574 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
34575 | #define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
34576 | //BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64 |
34577 | #define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
34578 | #define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
34579 | //BIF_CFG_DEV0_EPF6_0_MSI_MASK_64 |
34580 | #define BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
34581 | #define BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
34582 | //BIF_CFG_DEV0_EPF6_0_MSI_PENDING |
34583 | #define BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
34584 | #define BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
34585 | //BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64 |
34586 | #define BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
34587 | #define BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
34588 | //BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST |
34589 | #define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
34590 | #define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
34591 | #define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
34592 | #define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
34593 | //BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL |
34594 | #define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
34595 | #define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
34596 | #define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
34597 | #define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
34598 | #define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
34599 | #define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
34600 | //BIF_CFG_DEV0_EPF6_0_MSIX_TABLE |
34601 | #define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
34602 | #define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
34603 | #define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
34604 | #define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
34605 | //BIF_CFG_DEV0_EPF6_0_MSIX_PBA |
34606 | #define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
34607 | #define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
34608 | #define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
34609 | #define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
34610 | //BIF_CFG_DEV0_EPF6_0_SATA_CAP_0 |
34611 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
34612 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
34613 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
34614 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
34615 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
34616 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
34617 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
34618 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
34619 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
34620 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
34621 | //BIF_CFG_DEV0_EPF6_0_SATA_CAP_1 |
34622 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
34623 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
34624 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
34625 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
34626 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
34627 | #define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
34628 | //BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX |
34629 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
34630 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
34631 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
34632 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
34633 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
34634 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
34635 | //BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA |
34636 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
34637 | #define BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
34638 | //BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
34639 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
34640 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
34641 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
34642 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
34643 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
34644 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
34645 | //BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR |
34646 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
34647 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
34648 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
34649 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
34650 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
34651 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
34652 | //BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1 |
34653 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
34654 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
34655 | //BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2 |
34656 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
34657 | #define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
34658 | //BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
34659 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
34660 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
34661 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
34662 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
34663 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
34664 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
34665 | //BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS |
34666 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
34667 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
34668 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
34669 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
34670 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
34671 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
34672 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
34673 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
34674 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
34675 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
34676 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
34677 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
34678 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
34679 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
34680 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
34681 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
34682 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
34683 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
34684 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
34685 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
34686 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
34687 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
34688 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
34689 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
34690 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
34691 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
34692 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
34693 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
34694 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
34695 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
34696 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
34697 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
34698 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
34699 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
34700 | //BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK |
34701 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
34702 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
34703 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
34704 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
34705 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
34706 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
34707 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
34708 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
34709 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
34710 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
34711 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
34712 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
34713 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
34714 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
34715 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
34716 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
34717 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
34718 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
34719 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
34720 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
34721 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
34722 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
34723 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
34724 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
34725 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
34726 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
34727 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
34728 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
34729 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
34730 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
34731 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
34732 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
34733 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
34734 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
34735 | //BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY |
34736 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
34737 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
34738 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
34739 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
34740 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
34741 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
34742 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
34743 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
34744 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
34745 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
34746 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
34747 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
34748 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
34749 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
34750 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
34751 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
34752 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
34753 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
34754 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
34755 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
34756 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
34757 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
34758 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
34759 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
34760 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
34761 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
34762 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
34763 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
34764 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
34765 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
34766 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
34767 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
34768 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
34769 | #define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
34770 | //BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS |
34771 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
34772 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
34773 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
34774 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
34775 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
34776 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
34777 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
34778 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
34779 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
34780 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
34781 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
34782 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
34783 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
34784 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
34785 | //BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK |
34786 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
34787 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
34788 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
34789 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
34790 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
34791 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
34792 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
34793 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
34794 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
34795 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
34796 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
34797 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
34798 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
34799 | #define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
34800 | //BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL |
34801 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
34802 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
34803 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
34804 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
34805 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
34806 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
34807 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
34808 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
34809 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
34810 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
34811 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
34812 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
34813 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
34814 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
34815 | //BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0 |
34816 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
34817 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
34818 | //BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1 |
34819 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
34820 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
34821 | //BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2 |
34822 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
34823 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
34824 | //BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3 |
34825 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
34826 | #define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
34827 | //BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0 |
34828 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
34829 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
34830 | //BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1 |
34831 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
34832 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
34833 | //BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2 |
34834 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
34835 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
34836 | //BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3 |
34837 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
34838 | #define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
34839 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST |
34840 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
34841 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
34842 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
34843 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
34844 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
34845 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
34846 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP |
34847 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
34848 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
34849 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL |
34850 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
34851 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
34852 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
34853 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
34854 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
34855 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
34856 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
34857 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
34858 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP |
34859 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
34860 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
34861 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL |
34862 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
34863 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
34864 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
34865 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
34866 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
34867 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
34868 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
34869 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
34870 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP |
34871 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
34872 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
34873 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL |
34874 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
34875 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
34876 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
34877 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
34878 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
34879 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
34880 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
34881 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
34882 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP |
34883 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
34884 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
34885 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL |
34886 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
34887 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
34888 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
34889 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
34890 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
34891 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
34892 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
34893 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
34894 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP |
34895 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
34896 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
34897 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL |
34898 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
34899 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
34900 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
34901 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
34902 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
34903 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
34904 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
34905 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
34906 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP |
34907 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
34908 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
34909 | //BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL |
34910 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
34911 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
34912 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
34913 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
34914 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
34915 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
34916 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
34917 | #define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
34918 | //BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
34919 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
34920 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
34921 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
34922 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
34923 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
34924 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
34925 | //BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT |
34926 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
34927 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
34928 | //BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA |
34929 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
34930 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
34931 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
34932 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
34933 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
34934 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
34935 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
34936 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
34937 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
34938 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
34939 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
34940 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
34941 | //BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP |
34942 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
34943 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
34944 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST |
34945 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
34946 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
34947 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
34948 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
34949 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
34950 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
34951 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP |
34952 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
34953 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
34954 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
34955 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
34956 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
34957 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
34958 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
34959 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
34960 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
34961 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
34962 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR |
34963 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
34964 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
34965 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS |
34966 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
34967 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
34968 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
34969 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
34970 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL |
34971 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
34972 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
34973 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
34974 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34975 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34976 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
34977 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34978 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34979 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
34980 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34981 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34982 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
34983 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34984 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34985 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
34986 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34987 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34988 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
34989 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34990 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34991 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
34992 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34993 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34994 | //BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
34995 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
34996 | #define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
34997 | //BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST |
34998 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
34999 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
35000 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
35001 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
35002 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
35003 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
35004 | //BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP |
35005 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
35006 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
35007 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
35008 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
35009 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
35010 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
35011 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
35012 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
35013 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
35014 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
35015 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
35016 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
35017 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
35018 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
35019 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
35020 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
35021 | //BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL |
35022 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
35023 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
35024 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
35025 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
35026 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
35027 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
35028 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
35029 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
35030 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
35031 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
35032 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
35033 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
35034 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
35035 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
35036 | //BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST |
35037 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
35038 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
35039 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
35040 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
35041 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
35042 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
35043 | //BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP |
35044 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
35045 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
35046 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
35047 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
35048 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
35049 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
35050 | //BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL |
35051 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
35052 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
35053 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
35054 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
35055 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
35056 | #define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
35057 | //BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST |
35058 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
35059 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
35060 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
35061 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
35062 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
35063 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
35064 | //BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP |
35065 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
35066 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
35067 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
35068 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
35069 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
35070 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
35071 | //BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL |
35072 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
35073 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
35074 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
35075 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
35076 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
35077 | #define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
35078 | //BIF_CFG_DEV0_EPF6_0_PCIE_RTR_ENH_CAP_LIST |
35079 | #define BIF_CFG_DEV0_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
35080 | #define BIF_CFG_DEV0_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
35081 | #define BIF_CFG_DEV0_EPF6_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
35082 | #define BIF_CFG_DEV0_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
35083 | #define BIF_CFG_DEV0_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
35084 | #define BIF_CFG_DEV0_EPF6_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
35085 | //BIF_CFG_DEV0_EPF6_0_RTR_DATA1 |
35086 | #define BIF_CFG_DEV0_EPF6_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
35087 | #define BIF_CFG_DEV0_EPF6_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
35088 | #define BIF_CFG_DEV0_EPF6_0_RTR_DATA1__VALID__SHIFT 0x1f |
35089 | #define BIF_CFG_DEV0_EPF6_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
35090 | #define BIF_CFG_DEV0_EPF6_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
35091 | #define BIF_CFG_DEV0_EPF6_0_RTR_DATA1__VALID_MASK 0x80000000L |
35092 | //BIF_CFG_DEV0_EPF6_0_RTR_DATA2 |
35093 | #define BIF_CFG_DEV0_EPF6_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
35094 | #define BIF_CFG_DEV0_EPF6_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
35095 | #define BIF_CFG_DEV0_EPF6_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
35096 | #define BIF_CFG_DEV0_EPF6_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
35097 | |
35098 | |
35099 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp |
35100 | //BIF_CFG_DEV0_EPF7_0_VENDOR_ID |
35101 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
35102 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
35103 | //BIF_CFG_DEV0_EPF7_0_DEVICE_ID |
35104 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
35105 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
35106 | //BIF_CFG_DEV0_EPF7_0_COMMAND |
35107 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
35108 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
35109 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
35110 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
35111 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
35112 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
35113 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
35114 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN__SHIFT 0x8 |
35115 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
35116 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS__SHIFT 0xa |
35117 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
35118 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
35119 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
35120 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
35121 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
35122 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
35123 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING_MASK 0x0080L |
35124 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN_MASK 0x0100L |
35125 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
35126 | #define BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS_MASK 0x0400L |
35127 | //BIF_CFG_DEV0_EPF7_0_STATUS |
35128 | #define BIF_CFG_DEV0_EPF7_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
35129 | #define BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS__SHIFT 0x3 |
35130 | #define BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST__SHIFT 0x4 |
35131 | #define BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
35132 | #define BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
35133 | #define BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
35134 | #define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
35135 | #define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
35136 | #define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
35137 | #define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
35138 | #define BIF_CFG_DEV0_EPF7_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
35139 | #define BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS_MASK 0x0008L |
35140 | #define BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST_MASK 0x0010L |
35141 | #define BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_CAP_MASK 0x0020L |
35142 | #define BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
35143 | #define BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
35144 | #define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
35145 | #define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
35146 | #define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
35147 | #define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
35148 | //BIF_CFG_DEV0_EPF7_0_REVISION_ID |
35149 | #define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
35150 | #define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
35151 | #define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
35152 | #define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
35153 | //BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE |
35154 | #define BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
35155 | #define BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
35156 | //BIF_CFG_DEV0_EPF7_0_SUB_CLASS |
35157 | #define BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
35158 | #define BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
35159 | //BIF_CFG_DEV0_EPF7_0_BASE_CLASS |
35160 | #define BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
35161 | #define BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
35162 | //BIF_CFG_DEV0_EPF7_0_CACHE_LINE |
35163 | #define BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
35164 | #define BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
35165 | //BIF_CFG_DEV0_EPF7_0_LATENCY |
35166 | #define BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
35167 | #define BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
35168 | //BIF_CFG_DEV0_EPF7_0_HEADER |
35169 | #define 0x0 |
35170 | #define 0x7 |
35171 | #define 0x7FL |
35172 | #define 0x80L |
35173 | //BIF_CFG_DEV0_EPF7_0_BIST |
35174 | #define BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP__SHIFT 0x0 |
35175 | #define BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT__SHIFT 0x6 |
35176 | #define BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP__SHIFT 0x7 |
35177 | #define BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP_MASK 0x0FL |
35178 | #define BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT_MASK 0x40L |
35179 | #define BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP_MASK 0x80L |
35180 | //BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1 |
35181 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
35182 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
35183 | //BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2 |
35184 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
35185 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
35186 | //BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3 |
35187 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
35188 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
35189 | //BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4 |
35190 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
35191 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
35192 | //BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5 |
35193 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
35194 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
35195 | //BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6 |
35196 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
35197 | #define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
35198 | //BIF_CFG_DEV0_EPF7_0_ADAPTER_ID |
35199 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
35200 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
35201 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
35202 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
35203 | //BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR |
35204 | #define BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
35205 | #define BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
35206 | //BIF_CFG_DEV0_EPF7_0_CAP_PTR |
35207 | #define BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
35208 | #define BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
35209 | //BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE |
35210 | #define BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
35211 | #define BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
35212 | //BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN |
35213 | #define BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
35214 | #define BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
35215 | //BIF_CFG_DEV0_EPF7_0_MIN_GRANT |
35216 | #define BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
35217 | #define BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
35218 | //BIF_CFG_DEV0_EPF7_0_MAX_LATENCY |
35219 | #define BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
35220 | #define BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
35221 | //BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST |
35222 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
35223 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
35224 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
35225 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
35226 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
35227 | #define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
35228 | //BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W |
35229 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
35230 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
35231 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
35232 | #define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
35233 | //BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST |
35234 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
35235 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
35236 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
35237 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
35238 | //BIF_CFG_DEV0_EPF7_0_PMI_CAP |
35239 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION__SHIFT 0x0 |
35240 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
35241 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
35242 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
35243 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
35244 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
35245 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
35246 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
35247 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION_MASK 0x0007L |
35248 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
35249 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
35250 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
35251 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
35252 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
35253 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
35254 | #define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
35255 | //BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL |
35256 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
35257 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
35258 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
35259 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
35260 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
35261 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
35262 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
35263 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
35264 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
35265 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
35266 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
35267 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
35268 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
35269 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
35270 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
35271 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
35272 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
35273 | #define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
35274 | //BIF_CFG_DEV0_EPF7_0_SBRN |
35275 | #define BIF_CFG_DEV0_EPF7_0_SBRN__SBRN__SHIFT 0x0 |
35276 | #define BIF_CFG_DEV0_EPF7_0_SBRN__SBRN_MASK 0xFFL |
35277 | //BIF_CFG_DEV0_EPF7_0_FLADJ |
35278 | #define BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ__SHIFT 0x0 |
35279 | #define BIF_CFG_DEV0_EPF7_0_FLADJ__NFC__SHIFT 0x6 |
35280 | #define BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ_MASK 0x3FL |
35281 | #define BIF_CFG_DEV0_EPF7_0_FLADJ__NFC_MASK 0x40L |
35282 | //BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD |
35283 | #define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
35284 | #define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
35285 | #define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
35286 | #define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
35287 | //BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST |
35288 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
35289 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
35290 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
35291 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
35292 | //BIF_CFG_DEV0_EPF7_0_PCIE_CAP |
35293 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION__SHIFT 0x0 |
35294 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
35295 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
35296 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
35297 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION_MASK 0x000FL |
35298 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
35299 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
35300 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
35301 | //BIF_CFG_DEV0_EPF7_0_DEVICE_CAP |
35302 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
35303 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
35304 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
35305 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
35306 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
35307 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
35308 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
35309 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
35310 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
35311 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
35312 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
35313 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
35314 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
35315 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
35316 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
35317 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
35318 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
35319 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
35320 | //BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL |
35321 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
35322 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
35323 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
35324 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
35325 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
35326 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
35327 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
35328 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
35329 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
35330 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
35331 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
35332 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
35333 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
35334 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
35335 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
35336 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
35337 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
35338 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
35339 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
35340 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
35341 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
35342 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
35343 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
35344 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
35345 | //BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS |
35346 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
35347 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
35348 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
35349 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
35350 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
35351 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
35352 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
35353 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
35354 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
35355 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
35356 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
35357 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
35358 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
35359 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
35360 | //BIF_CFG_DEV0_EPF7_0_LINK_CAP |
35361 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
35362 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
35363 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
35364 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
35365 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
35366 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
35367 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
35368 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
35369 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
35370 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
35371 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
35372 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
35373 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
35374 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
35375 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
35376 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
35377 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
35378 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
35379 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
35380 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
35381 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
35382 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
35383 | //BIF_CFG_DEV0_EPF7_0_LINK_CNTL |
35384 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
35385 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
35386 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
35387 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
35388 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
35389 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
35390 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
35391 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
35392 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
35393 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
35394 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
35395 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
35396 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
35397 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
35398 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
35399 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
35400 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
35401 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
35402 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
35403 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
35404 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
35405 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
35406 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
35407 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
35408 | //BIF_CFG_DEV0_EPF7_0_LINK_STATUS |
35409 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
35410 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
35411 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
35412 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
35413 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
35414 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
35415 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
35416 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
35417 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
35418 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
35419 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
35420 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
35421 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
35422 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
35423 | //BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2 |
35424 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
35425 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
35426 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
35427 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
35428 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
35429 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
35430 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
35431 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
35432 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
35433 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
35434 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
35435 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
35436 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
35437 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
35438 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
35439 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
35440 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
35441 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
35442 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
35443 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
35444 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
35445 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
35446 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
35447 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
35448 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
35449 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
35450 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
35451 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
35452 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
35453 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
35454 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
35455 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
35456 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
35457 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
35458 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
35459 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
35460 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
35461 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
35462 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
35463 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
35464 | //BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2 |
35465 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
35466 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
35467 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
35468 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
35469 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
35470 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
35471 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
35472 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
35473 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
35474 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
35475 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
35476 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
35477 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
35478 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
35479 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
35480 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
35481 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
35482 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
35483 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
35484 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
35485 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
35486 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
35487 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
35488 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
35489 | //BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2 |
35490 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
35491 | #define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
35492 | //BIF_CFG_DEV0_EPF7_0_LINK_CAP2 |
35493 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
35494 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
35495 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
35496 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
35497 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
35498 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
35499 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
35500 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
35501 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
35502 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
35503 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
35504 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
35505 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
35506 | #define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
35507 | //BIF_CFG_DEV0_EPF7_0_LINK_CNTL2 |
35508 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
35509 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
35510 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
35511 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
35512 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
35513 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
35514 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
35515 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
35516 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
35517 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
35518 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
35519 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
35520 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
35521 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
35522 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
35523 | #define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
35524 | //BIF_CFG_DEV0_EPF7_0_LINK_STATUS2 |
35525 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
35526 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
35527 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
35528 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
35529 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
35530 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
35531 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
35532 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
35533 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
35534 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
35535 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
35536 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
35537 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
35538 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
35539 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
35540 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
35541 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
35542 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
35543 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
35544 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
35545 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
35546 | #define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
35547 | //BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST |
35548 | #define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
35549 | #define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
35550 | #define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
35551 | #define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
35552 | //BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL |
35553 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
35554 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
35555 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
35556 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
35557 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
35558 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
35559 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
35560 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
35561 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
35562 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
35563 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
35564 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
35565 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
35566 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
35567 | //BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO |
35568 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
35569 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
35570 | //BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI |
35571 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
35572 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
35573 | //BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA |
35574 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
35575 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
35576 | //BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA |
35577 | #define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
35578 | #define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
35579 | //BIF_CFG_DEV0_EPF7_0_MSI_MASK |
35580 | #define BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
35581 | #define BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
35582 | //BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64 |
35583 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
35584 | #define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
35585 | //BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64 |
35586 | #define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
35587 | #define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
35588 | //BIF_CFG_DEV0_EPF7_0_MSI_MASK_64 |
35589 | #define BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
35590 | #define BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
35591 | //BIF_CFG_DEV0_EPF7_0_MSI_PENDING |
35592 | #define BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
35593 | #define BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
35594 | //BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64 |
35595 | #define BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
35596 | #define BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
35597 | //BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST |
35598 | #define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
35599 | #define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
35600 | #define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
35601 | #define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
35602 | //BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL |
35603 | #define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
35604 | #define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
35605 | #define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
35606 | #define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
35607 | #define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
35608 | #define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
35609 | //BIF_CFG_DEV0_EPF7_0_MSIX_TABLE |
35610 | #define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
35611 | #define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
35612 | #define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
35613 | #define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
35614 | //BIF_CFG_DEV0_EPF7_0_MSIX_PBA |
35615 | #define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
35616 | #define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
35617 | #define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
35618 | #define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
35619 | //BIF_CFG_DEV0_EPF7_0_SATA_CAP_0 |
35620 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
35621 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
35622 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
35623 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
35624 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
35625 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
35626 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
35627 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
35628 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
35629 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
35630 | //BIF_CFG_DEV0_EPF7_0_SATA_CAP_1 |
35631 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
35632 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
35633 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
35634 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
35635 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
35636 | #define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
35637 | //BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX |
35638 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
35639 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
35640 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
35641 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
35642 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
35643 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
35644 | //BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA |
35645 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
35646 | #define BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
35647 | //BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
35648 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
35649 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
35650 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
35651 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
35652 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
35653 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
35654 | //BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR |
35655 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
35656 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
35657 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
35658 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
35659 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
35660 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
35661 | //BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1 |
35662 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
35663 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
35664 | //BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2 |
35665 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
35666 | #define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
35667 | //BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
35668 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
35669 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
35670 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
35671 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
35672 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
35673 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
35674 | //BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS |
35675 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
35676 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
35677 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
35678 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
35679 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
35680 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
35681 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
35682 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
35683 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
35684 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
35685 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
35686 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
35687 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
35688 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
35689 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
35690 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
35691 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
35692 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
35693 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
35694 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
35695 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
35696 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
35697 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
35698 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
35699 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
35700 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
35701 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
35702 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
35703 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
35704 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
35705 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
35706 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
35707 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
35708 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
35709 | //BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK |
35710 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
35711 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
35712 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
35713 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
35714 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
35715 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
35716 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
35717 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
35718 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
35719 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
35720 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
35721 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
35722 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
35723 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
35724 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
35725 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
35726 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
35727 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
35728 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
35729 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
35730 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
35731 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
35732 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
35733 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
35734 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
35735 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
35736 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
35737 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
35738 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
35739 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
35740 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
35741 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
35742 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
35743 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
35744 | //BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY |
35745 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
35746 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
35747 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
35748 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
35749 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
35750 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
35751 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
35752 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
35753 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
35754 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
35755 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
35756 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
35757 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
35758 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
35759 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
35760 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
35761 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
35762 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
35763 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
35764 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
35765 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
35766 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
35767 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
35768 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
35769 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
35770 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
35771 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
35772 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
35773 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
35774 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
35775 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
35776 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
35777 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
35778 | #define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
35779 | //BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS |
35780 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
35781 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
35782 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
35783 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
35784 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
35785 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
35786 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
35787 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
35788 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
35789 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
35790 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
35791 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
35792 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
35793 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
35794 | //BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK |
35795 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
35796 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
35797 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
35798 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
35799 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
35800 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
35801 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
35802 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
35803 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
35804 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
35805 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
35806 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
35807 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
35808 | #define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
35809 | //BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL |
35810 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
35811 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
35812 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
35813 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
35814 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
35815 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
35816 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
35817 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
35818 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
35819 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
35820 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
35821 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
35822 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
35823 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
35824 | //BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0 |
35825 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
35826 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
35827 | //BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1 |
35828 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
35829 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
35830 | //BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2 |
35831 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
35832 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
35833 | //BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3 |
35834 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
35835 | #define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
35836 | //BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0 |
35837 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
35838 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
35839 | //BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1 |
35840 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
35841 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
35842 | //BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2 |
35843 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
35844 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
35845 | //BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3 |
35846 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
35847 | #define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
35848 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST |
35849 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
35850 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
35851 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
35852 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
35853 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
35854 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
35855 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP |
35856 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
35857 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
35858 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL |
35859 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
35860 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
35861 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
35862 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
35863 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
35864 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
35865 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
35866 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
35867 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP |
35868 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
35869 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
35870 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL |
35871 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
35872 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
35873 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
35874 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
35875 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
35876 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
35877 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
35878 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
35879 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP |
35880 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
35881 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
35882 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL |
35883 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
35884 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
35885 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
35886 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
35887 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
35888 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
35889 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
35890 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
35891 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP |
35892 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
35893 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
35894 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL |
35895 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
35896 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
35897 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
35898 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
35899 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
35900 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
35901 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
35902 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
35903 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP |
35904 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
35905 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
35906 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL |
35907 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
35908 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
35909 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
35910 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
35911 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
35912 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
35913 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
35914 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
35915 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP |
35916 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
35917 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
35918 | //BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL |
35919 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
35920 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
35921 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
35922 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
35923 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
35924 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
35925 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
35926 | #define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
35927 | //BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
35928 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
35929 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
35930 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
35931 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
35932 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
35933 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
35934 | //BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT |
35935 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
35936 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
35937 | //BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA |
35938 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
35939 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
35940 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
35941 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
35942 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
35943 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
35944 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
35945 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
35946 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
35947 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
35948 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
35949 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
35950 | //BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP |
35951 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
35952 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
35953 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST |
35954 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
35955 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
35956 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
35957 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
35958 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
35959 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
35960 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP |
35961 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
35962 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
35963 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
35964 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
35965 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
35966 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
35967 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
35968 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
35969 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
35970 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
35971 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR |
35972 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
35973 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
35974 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS |
35975 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
35976 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
35977 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
35978 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
35979 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL |
35980 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
35981 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
35982 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
35983 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
35984 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
35985 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
35986 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
35987 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
35988 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
35989 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
35990 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
35991 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
35992 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
35993 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
35994 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
35995 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
35996 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
35997 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
35998 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
35999 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
36000 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
36001 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
36002 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
36003 | //BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
36004 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
36005 | #define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
36006 | //BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST |
36007 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
36008 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
36009 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
36010 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
36011 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
36012 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
36013 | //BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP |
36014 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
36015 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
36016 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
36017 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
36018 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
36019 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
36020 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
36021 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
36022 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
36023 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
36024 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
36025 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
36026 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
36027 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
36028 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
36029 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
36030 | //BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL |
36031 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
36032 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
36033 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
36034 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
36035 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
36036 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
36037 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
36038 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
36039 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
36040 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
36041 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
36042 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
36043 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
36044 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
36045 | //BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST |
36046 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
36047 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
36048 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
36049 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
36050 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
36051 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
36052 | //BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP |
36053 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
36054 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
36055 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
36056 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
36057 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
36058 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
36059 | //BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL |
36060 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
36061 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
36062 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
36063 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
36064 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
36065 | #define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
36066 | //BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST |
36067 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
36068 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
36069 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
36070 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
36071 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
36072 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
36073 | //BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP |
36074 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
36075 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
36076 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
36077 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
36078 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
36079 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
36080 | //BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL |
36081 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
36082 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
36083 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
36084 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
36085 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
36086 | #define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
36087 | //BIF_CFG_DEV0_EPF7_0_PCIE_RTR_ENH_CAP_LIST |
36088 | #define BIF_CFG_DEV0_EPF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
36089 | #define BIF_CFG_DEV0_EPF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
36090 | #define BIF_CFG_DEV0_EPF7_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
36091 | #define BIF_CFG_DEV0_EPF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
36092 | #define BIF_CFG_DEV0_EPF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
36093 | #define BIF_CFG_DEV0_EPF7_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
36094 | //BIF_CFG_DEV0_EPF7_0_RTR_DATA1 |
36095 | #define BIF_CFG_DEV0_EPF7_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
36096 | #define BIF_CFG_DEV0_EPF7_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
36097 | #define BIF_CFG_DEV0_EPF7_0_RTR_DATA1__VALID__SHIFT 0x1f |
36098 | #define BIF_CFG_DEV0_EPF7_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
36099 | #define BIF_CFG_DEV0_EPF7_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
36100 | #define BIF_CFG_DEV0_EPF7_0_RTR_DATA1__VALID_MASK 0x80000000L |
36101 | //BIF_CFG_DEV0_EPF7_0_RTR_DATA2 |
36102 | #define BIF_CFG_DEV0_EPF7_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
36103 | #define BIF_CFG_DEV0_EPF7_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
36104 | #define BIF_CFG_DEV0_EPF7_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
36105 | #define BIF_CFG_DEV0_EPF7_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
36106 | |
36107 | |
36108 | // addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp |
36109 | //BIF_CFG_DEV1_RC0_VENDOR_ID |
36110 | #define BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
36111 | #define BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
36112 | //BIF_CFG_DEV1_RC0_DEVICE_ID |
36113 | #define BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
36114 | #define BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
36115 | //BIF_CFG_DEV1_RC0_COMMAND |
36116 | #define BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN__SHIFT 0x0 |
36117 | #define BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN__SHIFT 0x1 |
36118 | #define BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
36119 | #define BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
36120 | #define BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
36121 | #define BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
36122 | #define BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING__SHIFT 0x7 |
36123 | #define BIF_CFG_DEV1_RC0_COMMAND__SERR_EN__SHIFT 0x8 |
36124 | #define BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
36125 | #define BIF_CFG_DEV1_RC0_COMMAND__INT_DIS__SHIFT 0xa |
36126 | #define BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN_MASK 0x0001L |
36127 | #define BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN_MASK 0x0002L |
36128 | #define BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
36129 | #define BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
36130 | #define BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
36131 | #define BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
36132 | #define BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING_MASK 0x0080L |
36133 | #define BIF_CFG_DEV1_RC0_COMMAND__SERR_EN_MASK 0x0100L |
36134 | #define BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
36135 | #define BIF_CFG_DEV1_RC0_COMMAND__INT_DIS_MASK 0x0400L |
36136 | //BIF_CFG_DEV1_RC0_STATUS |
36137 | #define BIF_CFG_DEV1_RC0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
36138 | #define BIF_CFG_DEV1_RC0_STATUS__INT_STATUS__SHIFT 0x3 |
36139 | #define BIF_CFG_DEV1_RC0_STATUS__CAP_LIST__SHIFT 0x4 |
36140 | #define BIF_CFG_DEV1_RC0_STATUS__PCI_66_CAP__SHIFT 0x5 |
36141 | #define BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
36142 | #define BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
36143 | #define BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
36144 | #define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
36145 | #define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
36146 | #define BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
36147 | #define BIF_CFG_DEV1_RC0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
36148 | #define BIF_CFG_DEV1_RC0_STATUS__INT_STATUS_MASK 0x0008L |
36149 | #define BIF_CFG_DEV1_RC0_STATUS__CAP_LIST_MASK 0x0010L |
36150 | #define BIF_CFG_DEV1_RC0_STATUS__PCI_66_CAP_MASK 0x0020L |
36151 | #define BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
36152 | #define BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
36153 | #define BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
36154 | #define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
36155 | #define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
36156 | #define BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
36157 | //BIF_CFG_DEV1_RC0_REVISION_ID |
36158 | #define BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
36159 | #define BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
36160 | #define BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
36161 | #define BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
36162 | //BIF_CFG_DEV1_RC0_PROG_INTERFACE |
36163 | #define BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
36164 | #define BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
36165 | //BIF_CFG_DEV1_RC0_SUB_CLASS |
36166 | #define BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
36167 | #define BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
36168 | //BIF_CFG_DEV1_RC0_BASE_CLASS |
36169 | #define BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
36170 | #define BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
36171 | //BIF_CFG_DEV1_RC0_CACHE_LINE |
36172 | #define BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
36173 | #define BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
36174 | //BIF_CFG_DEV1_RC0_LATENCY |
36175 | #define BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
36176 | #define BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
36177 | //BIF_CFG_DEV1_RC0_HEADER |
36178 | #define 0x0 |
36179 | #define 0x7 |
36180 | #define 0x7FL |
36181 | #define 0x80L |
36182 | //BIF_CFG_DEV1_RC0_BIST |
36183 | #define BIF_CFG_DEV1_RC0_BIST__BIST_COMP__SHIFT 0x0 |
36184 | #define BIF_CFG_DEV1_RC0_BIST__BIST_STRT__SHIFT 0x6 |
36185 | #define BIF_CFG_DEV1_RC0_BIST__BIST_CAP__SHIFT 0x7 |
36186 | #define BIF_CFG_DEV1_RC0_BIST__BIST_COMP_MASK 0x0FL |
36187 | #define BIF_CFG_DEV1_RC0_BIST__BIST_STRT_MASK 0x40L |
36188 | #define BIF_CFG_DEV1_RC0_BIST__BIST_CAP_MASK 0x80L |
36189 | //BIF_CFG_DEV1_RC0_BASE_ADDR_1 |
36190 | #define BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
36191 | #define BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
36192 | //BIF_CFG_DEV1_RC0_BASE_ADDR_2 |
36193 | #define BIF_CFG_DEV1_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
36194 | #define BIF_CFG_DEV1_RC0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
36195 | //BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY |
36196 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
36197 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
36198 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
36199 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
36200 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
36201 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
36202 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
36203 | #define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
36204 | //BIF_CFG_DEV1_RC0_IO_BASE_LIMIT |
36205 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
36206 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
36207 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
36208 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
36209 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
36210 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
36211 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
36212 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
36213 | //BIF_CFG_DEV1_RC0_SECONDARY_STATUS |
36214 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 |
36215 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
36216 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
36217 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
36218 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
36219 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
36220 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
36221 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L |
36222 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
36223 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
36224 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
36225 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
36226 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
36227 | #define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
36228 | //BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT |
36229 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
36230 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
36231 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
36232 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
36233 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
36234 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
36235 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
36236 | #define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
36237 | //BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT |
36238 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
36239 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
36240 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
36241 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
36242 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
36243 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
36244 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
36245 | #define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
36246 | //BIF_CFG_DEV1_RC0_PREF_BASE_UPPER |
36247 | #define BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
36248 | #define BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
36249 | //BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER |
36250 | #define BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
36251 | #define BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
36252 | //BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI |
36253 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
36254 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
36255 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
36256 | #define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
36257 | //BIF_CFG_DEV1_RC0_CAP_PTR |
36258 | #define BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
36259 | #define BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR_MASK 0xFFL |
36260 | //BIF_CFG_DEV1_RC0_ROM_BASE_ADDR |
36261 | #define BIF_CFG_DEV1_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
36262 | #define BIF_CFG_DEV1_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
36263 | //BIF_CFG_DEV1_RC0_INTERRUPT_LINE |
36264 | #define BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
36265 | #define BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
36266 | //BIF_CFG_DEV1_RC0_INTERRUPT_PIN |
36267 | #define BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
36268 | #define BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
36269 | //BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL |
36270 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
36271 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
36272 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
36273 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
36274 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
36275 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
36276 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
36277 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
36278 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 |
36279 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 |
36280 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa |
36281 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb |
36282 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
36283 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
36284 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
36285 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
36286 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
36287 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
36288 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
36289 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
36290 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L |
36291 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L |
36292 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L |
36293 | #define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L |
36294 | //BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL |
36295 | #define BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
36296 | #define BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
36297 | //BIF_CFG_DEV1_RC0_PMI_CAP_LIST |
36298 | #define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
36299 | #define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
36300 | #define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
36301 | #define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
36302 | //BIF_CFG_DEV1_RC0_PMI_CAP |
36303 | #define BIF_CFG_DEV1_RC0_PMI_CAP__VERSION__SHIFT 0x0 |
36304 | #define BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
36305 | #define BIF_CFG_DEV1_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
36306 | #define BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
36307 | #define BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
36308 | #define BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
36309 | #define BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
36310 | #define BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
36311 | #define BIF_CFG_DEV1_RC0_PMI_CAP__VERSION_MASK 0x0007L |
36312 | #define BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
36313 | #define BIF_CFG_DEV1_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
36314 | #define BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
36315 | #define BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
36316 | #define BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
36317 | #define BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
36318 | #define BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
36319 | //BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL |
36320 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
36321 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
36322 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
36323 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
36324 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
36325 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
36326 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
36327 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
36328 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
36329 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
36330 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
36331 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
36332 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
36333 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
36334 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
36335 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
36336 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
36337 | #define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
36338 | //BIF_CFG_DEV1_RC0_PCIE_CAP_LIST |
36339 | #define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
36340 | #define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
36341 | #define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
36342 | #define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
36343 | //BIF_CFG_DEV1_RC0_PCIE_CAP |
36344 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION__SHIFT 0x0 |
36345 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
36346 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
36347 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
36348 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION_MASK 0x000FL |
36349 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
36350 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
36351 | #define BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
36352 | //BIF_CFG_DEV1_RC0_DEVICE_CAP |
36353 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
36354 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
36355 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
36356 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
36357 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
36358 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
36359 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
36360 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
36361 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
36362 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
36363 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
36364 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
36365 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
36366 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
36367 | //BIF_CFG_DEV1_RC0_DEVICE_CNTL |
36368 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
36369 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
36370 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
36371 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
36372 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
36373 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
36374 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
36375 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
36376 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
36377 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
36378 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
36379 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
36380 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
36381 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
36382 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
36383 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
36384 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
36385 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
36386 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
36387 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
36388 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
36389 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
36390 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
36391 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
36392 | //BIF_CFG_DEV1_RC0_DEVICE_STATUS |
36393 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
36394 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
36395 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
36396 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
36397 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
36398 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
36399 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
36400 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
36401 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
36402 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
36403 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
36404 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
36405 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
36406 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
36407 | //BIF_CFG_DEV1_RC0_LINK_CAP |
36408 | #define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
36409 | #define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
36410 | #define BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
36411 | #define BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
36412 | #define BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
36413 | #define BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
36414 | #define BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
36415 | #define BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
36416 | #define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
36417 | #define BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
36418 | #define BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
36419 | #define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
36420 | #define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
36421 | #define BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
36422 | #define BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
36423 | #define BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
36424 | #define BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
36425 | #define BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
36426 | #define BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
36427 | #define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
36428 | #define BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
36429 | #define BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
36430 | //BIF_CFG_DEV1_RC0_LINK_CNTL |
36431 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
36432 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
36433 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
36434 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
36435 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
36436 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
36437 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
36438 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
36439 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
36440 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
36441 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
36442 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
36443 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
36444 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
36445 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
36446 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
36447 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
36448 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
36449 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
36450 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
36451 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
36452 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
36453 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
36454 | #define BIF_CFG_DEV1_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
36455 | //BIF_CFG_DEV1_RC0_LINK_STATUS |
36456 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
36457 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
36458 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
36459 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
36460 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
36461 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
36462 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
36463 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
36464 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
36465 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
36466 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
36467 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
36468 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
36469 | #define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
36470 | //BIF_CFG_DEV1_RC0_SLOT_CAP |
36471 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
36472 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
36473 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
36474 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
36475 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
36476 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
36477 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
36478 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
36479 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
36480 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
36481 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
36482 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
36483 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
36484 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
36485 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
36486 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
36487 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
36488 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
36489 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
36490 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
36491 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
36492 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
36493 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
36494 | #define BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
36495 | //BIF_CFG_DEV1_RC0_SLOT_CNTL |
36496 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
36497 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
36498 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
36499 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
36500 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
36501 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
36502 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
36503 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
36504 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
36505 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
36506 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
36507 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
36508 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
36509 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
36510 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
36511 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
36512 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
36513 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
36514 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
36515 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
36516 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
36517 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
36518 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
36519 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
36520 | //BIF_CFG_DEV1_RC0_SLOT_STATUS |
36521 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
36522 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
36523 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
36524 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
36525 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
36526 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
36527 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
36528 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
36529 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
36530 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
36531 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
36532 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
36533 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
36534 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
36535 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
36536 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
36537 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
36538 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
36539 | //BIF_CFG_DEV1_RC0_ROOT_CNTL |
36540 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
36541 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
36542 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
36543 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
36544 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
36545 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
36546 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
36547 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
36548 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
36549 | #define BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
36550 | //BIF_CFG_DEV1_RC0_ROOT_CAP |
36551 | #define BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
36552 | #define BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
36553 | //BIF_CFG_DEV1_RC0_ROOT_STATUS |
36554 | #define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
36555 | #define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
36556 | #define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
36557 | #define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
36558 | #define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
36559 | #define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
36560 | //BIF_CFG_DEV1_RC0_DEVICE_CAP2 |
36561 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
36562 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
36563 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
36564 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
36565 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
36566 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
36567 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
36568 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
36569 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
36570 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
36571 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
36572 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
36573 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
36574 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
36575 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
36576 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
36577 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
36578 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
36579 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
36580 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
36581 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
36582 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
36583 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
36584 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
36585 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
36586 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
36587 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
36588 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
36589 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
36590 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
36591 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
36592 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
36593 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
36594 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
36595 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
36596 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
36597 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
36598 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
36599 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
36600 | #define BIF_CFG_DEV1_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
36601 | //BIF_CFG_DEV1_RC0_DEVICE_CNTL2 |
36602 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
36603 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
36604 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
36605 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
36606 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
36607 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
36608 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
36609 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
36610 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
36611 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
36612 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
36613 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
36614 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
36615 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
36616 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
36617 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
36618 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
36619 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
36620 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
36621 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
36622 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
36623 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
36624 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
36625 | #define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
36626 | //BIF_CFG_DEV1_RC0_DEVICE_STATUS2 |
36627 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
36628 | #define BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
36629 | //BIF_CFG_DEV1_RC0_LINK_CAP2 |
36630 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
36631 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
36632 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
36633 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
36634 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
36635 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
36636 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
36637 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
36638 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
36639 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
36640 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
36641 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
36642 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
36643 | #define BIF_CFG_DEV1_RC0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
36644 | //BIF_CFG_DEV1_RC0_LINK_CNTL2 |
36645 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
36646 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
36647 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
36648 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
36649 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
36650 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
36651 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
36652 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
36653 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
36654 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
36655 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
36656 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
36657 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
36658 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
36659 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
36660 | #define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
36661 | //BIF_CFG_DEV1_RC0_LINK_STATUS2 |
36662 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
36663 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
36664 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
36665 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
36666 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
36667 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
36668 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
36669 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
36670 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
36671 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
36672 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
36673 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
36674 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
36675 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
36676 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
36677 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
36678 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
36679 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
36680 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
36681 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
36682 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
36683 | #define BIF_CFG_DEV1_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
36684 | //BIF_CFG_DEV1_RC0_SLOT_CAP2 |
36685 | #define BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
36686 | #define BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
36687 | //BIF_CFG_DEV1_RC0_SLOT_CNTL2 |
36688 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
36689 | #define BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
36690 | //BIF_CFG_DEV1_RC0_SLOT_STATUS2 |
36691 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
36692 | #define BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
36693 | //BIF_CFG_DEV1_RC0_MSI_CAP_LIST |
36694 | #define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
36695 | #define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
36696 | #define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
36697 | #define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
36698 | //BIF_CFG_DEV1_RC0_MSI_MSG_CNTL |
36699 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
36700 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
36701 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
36702 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
36703 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
36704 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
36705 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
36706 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
36707 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
36708 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
36709 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
36710 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
36711 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
36712 | #define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
36713 | //BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO |
36714 | #define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
36715 | #define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
36716 | //BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI |
36717 | #define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
36718 | #define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
36719 | //BIF_CFG_DEV1_RC0_MSI_MSG_DATA |
36720 | #define BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
36721 | #define BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
36722 | //BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA |
36723 | #define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
36724 | #define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
36725 | //BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64 |
36726 | #define BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
36727 | #define BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
36728 | //BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64 |
36729 | #define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
36730 | #define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
36731 | //BIF_CFG_DEV1_RC0_SSID_CAP_LIST |
36732 | #define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
36733 | #define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
36734 | #define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
36735 | #define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
36736 | //BIF_CFG_DEV1_RC0_SSID_CAP |
36737 | #define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
36738 | #define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
36739 | #define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
36740 | #define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
36741 | //BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST |
36742 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
36743 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
36744 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
36745 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
36746 | //BIF_CFG_DEV1_RC0_MSI_MAP_CAP |
36747 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN__SHIFT 0x0 |
36748 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
36749 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
36750 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN_MASK 0x0001L |
36751 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD_MASK 0x0002L |
36752 | #define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
36753 | //BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
36754 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
36755 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
36756 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
36757 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
36758 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
36759 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
36760 | //BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR |
36761 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
36762 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
36763 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
36764 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
36765 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
36766 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
36767 | //BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1 |
36768 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
36769 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
36770 | //BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2 |
36771 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
36772 | #define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
36773 | //BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST |
36774 | #define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
36775 | #define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
36776 | #define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
36777 | #define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
36778 | #define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
36779 | #define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
36780 | //BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1 |
36781 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
36782 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
36783 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
36784 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
36785 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
36786 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
36787 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
36788 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
36789 | //BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2 |
36790 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
36791 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
36792 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
36793 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
36794 | //BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL |
36795 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
36796 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
36797 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
36798 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
36799 | //BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS |
36800 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
36801 | #define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
36802 | //BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP |
36803 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
36804 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
36805 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
36806 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
36807 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
36808 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
36809 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
36810 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
36811 | //BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL |
36812 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
36813 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
36814 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
36815 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
36816 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
36817 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
36818 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
36819 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
36820 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
36821 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
36822 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
36823 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
36824 | //BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS |
36825 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
36826 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
36827 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
36828 | #define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
36829 | //BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP |
36830 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
36831 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
36832 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
36833 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
36834 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
36835 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
36836 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
36837 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
36838 | //BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL |
36839 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
36840 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
36841 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
36842 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
36843 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
36844 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
36845 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
36846 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
36847 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
36848 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
36849 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
36850 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
36851 | //BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS |
36852 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
36853 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
36854 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
36855 | #define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
36856 | //BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
36857 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
36858 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
36859 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
36860 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
36861 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
36862 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
36863 | //BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1 |
36864 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
36865 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
36866 | //BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2 |
36867 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
36868 | #define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
36869 | //BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
36870 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
36871 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
36872 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
36873 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
36874 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
36875 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
36876 | //BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS |
36877 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
36878 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
36879 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
36880 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
36881 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
36882 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
36883 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
36884 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
36885 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
36886 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
36887 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
36888 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
36889 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
36890 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
36891 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
36892 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
36893 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
36894 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
36895 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
36896 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
36897 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
36898 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
36899 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
36900 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
36901 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
36902 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
36903 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
36904 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
36905 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
36906 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
36907 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
36908 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
36909 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
36910 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
36911 | //BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK |
36912 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
36913 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
36914 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
36915 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
36916 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
36917 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
36918 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
36919 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
36920 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
36921 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
36922 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
36923 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
36924 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
36925 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
36926 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
36927 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
36928 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
36929 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
36930 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
36931 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
36932 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
36933 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
36934 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
36935 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
36936 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
36937 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
36938 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
36939 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
36940 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
36941 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
36942 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
36943 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
36944 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
36945 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
36946 | //BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY |
36947 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
36948 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
36949 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
36950 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
36951 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
36952 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
36953 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
36954 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
36955 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
36956 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
36957 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
36958 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
36959 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
36960 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
36961 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
36962 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
36963 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
36964 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
36965 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
36966 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
36967 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
36968 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
36969 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
36970 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
36971 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
36972 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
36973 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
36974 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
36975 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
36976 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
36977 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
36978 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
36979 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
36980 | #define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
36981 | //BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS |
36982 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
36983 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
36984 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
36985 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
36986 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
36987 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
36988 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
36989 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
36990 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
36991 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
36992 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
36993 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
36994 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
36995 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
36996 | //BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK |
36997 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
36998 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
36999 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
37000 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
37001 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
37002 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
37003 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
37004 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
37005 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
37006 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
37007 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
37008 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
37009 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
37010 | #define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
37011 | //BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL |
37012 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
37013 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
37014 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
37015 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
37016 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
37017 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
37018 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
37019 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
37020 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
37021 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
37022 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
37023 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
37024 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
37025 | #define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
37026 | //BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0 |
37027 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
37028 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
37029 | //BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1 |
37030 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
37031 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
37032 | //BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2 |
37033 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
37034 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
37035 | //BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3 |
37036 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
37037 | #define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
37038 | //BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD |
37039 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
37040 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
37041 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
37042 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
37043 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
37044 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
37045 | //BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS |
37046 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
37047 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
37048 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
37049 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
37050 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
37051 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
37052 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
37053 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
37054 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
37055 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
37056 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
37057 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
37058 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
37059 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
37060 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
37061 | #define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
37062 | //BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID |
37063 | #define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
37064 | #define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
37065 | #define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
37066 | #define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
37067 | //BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0 |
37068 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
37069 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
37070 | //BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1 |
37071 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
37072 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
37073 | //BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2 |
37074 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
37075 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
37076 | //BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3 |
37077 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
37078 | #define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
37079 | //BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST |
37080 | #define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
37081 | #define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
37082 | #define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
37083 | #define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
37084 | #define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
37085 | #define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
37086 | //BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3 |
37087 | #define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
37088 | #define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
37089 | #define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
37090 | #define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
37091 | #define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
37092 | #define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
37093 | //BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS |
37094 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
37095 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
37096 | //BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL |
37097 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37098 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37099 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37100 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37101 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37102 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37103 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37104 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37105 | //BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL |
37106 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37107 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37108 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37109 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37110 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37111 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37112 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37113 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37114 | //BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL |
37115 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37116 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37117 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37118 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37119 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37120 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37121 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37122 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37123 | //BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL |
37124 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37125 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37126 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37127 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37128 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37129 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37130 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37131 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37132 | //BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL |
37133 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37134 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37135 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37136 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37137 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37138 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37139 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37140 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37141 | //BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL |
37142 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37143 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37144 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37145 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37146 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37147 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37148 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37149 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37150 | //BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL |
37151 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37152 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37153 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37154 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37155 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37156 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37157 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37158 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37159 | //BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL |
37160 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37161 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37162 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37163 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37164 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37165 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37166 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37167 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37168 | //BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL |
37169 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37170 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37171 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37172 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37173 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37174 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37175 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37176 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37177 | //BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL |
37178 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37179 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37180 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37181 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37182 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37183 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37184 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37185 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37186 | //BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL |
37187 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37188 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37189 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37190 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37191 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37192 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37193 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37194 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37195 | //BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL |
37196 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37197 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37198 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37199 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37200 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37201 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37202 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37203 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37204 | //BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL |
37205 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37206 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37207 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37208 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37209 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37210 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37211 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37212 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37213 | //BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL |
37214 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37215 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37216 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37217 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37218 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37219 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37220 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37221 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37222 | //BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL |
37223 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37224 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37225 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37226 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37227 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37228 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37229 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37230 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37231 | //BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL |
37232 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
37233 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
37234 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
37235 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
37236 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
37237 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
37238 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
37239 | #define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
37240 | //BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST |
37241 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
37242 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
37243 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
37244 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
37245 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
37246 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
37247 | //BIF_CFG_DEV1_RC0_PCIE_ACS_CAP |
37248 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
37249 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
37250 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
37251 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
37252 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
37253 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
37254 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
37255 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
37256 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
37257 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
37258 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
37259 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
37260 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
37261 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
37262 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
37263 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
37264 | //BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL |
37265 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
37266 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
37267 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
37268 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
37269 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
37270 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
37271 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
37272 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
37273 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
37274 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
37275 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
37276 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
37277 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
37278 | #define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
37279 | //BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST |
37280 | #define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
37281 | #define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
37282 | #define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
37283 | #define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
37284 | #define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
37285 | #define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
37286 | //BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP |
37287 | #define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
37288 | #define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
37289 | #define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
37290 | #define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
37291 | //BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS |
37292 | #define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
37293 | #define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
37294 | #define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
37295 | #define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
37296 | //BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST |
37297 | #define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
37298 | #define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
37299 | #define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
37300 | #define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
37301 | #define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
37302 | #define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
37303 | //BIF_CFG_DEV1_RC0_LINK_CAP_16GT |
37304 | #define BIF_CFG_DEV1_RC0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
37305 | #define BIF_CFG_DEV1_RC0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
37306 | //BIF_CFG_DEV1_RC0_LINK_CNTL_16GT |
37307 | #define BIF_CFG_DEV1_RC0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
37308 | #define BIF_CFG_DEV1_RC0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
37309 | //BIF_CFG_DEV1_RC0_LINK_STATUS_16GT |
37310 | #define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
37311 | #define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
37312 | #define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
37313 | #define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
37314 | #define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
37315 | #define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
37316 | #define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
37317 | #define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
37318 | #define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
37319 | #define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
37320 | //BIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT |
37321 | #define BIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
37322 | #define BIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
37323 | //BIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT |
37324 | #define BIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
37325 | #define BIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
37326 | //BIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT |
37327 | #define BIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
37328 | #define BIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
37329 | //BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT |
37330 | #define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37331 | #define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
37332 | #define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
37333 | #define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
37334 | //BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT |
37335 | #define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37336 | #define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
37337 | #define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
37338 | #define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
37339 | //BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT |
37340 | #define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37341 | #define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
37342 | #define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
37343 | #define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
37344 | //BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT |
37345 | #define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37346 | #define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
37347 | #define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
37348 | #define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
37349 | //BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT |
37350 | #define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37351 | #define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
37352 | #define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
37353 | #define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
37354 | //BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT |
37355 | #define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37356 | #define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
37357 | #define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
37358 | #define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
37359 | //BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT |
37360 | #define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37361 | #define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
37362 | #define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
37363 | #define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
37364 | //BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT |
37365 | #define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37366 | #define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
37367 | #define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
37368 | #define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
37369 | //BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT |
37370 | #define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37371 | #define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
37372 | #define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
37373 | #define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
37374 | //BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT |
37375 | #define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37376 | #define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
37377 | #define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
37378 | #define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
37379 | //BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT |
37380 | #define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37381 | #define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
37382 | #define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
37383 | #define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
37384 | //BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT |
37385 | #define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37386 | #define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
37387 | #define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
37388 | #define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
37389 | //BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT |
37390 | #define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37391 | #define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
37392 | #define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
37393 | #define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
37394 | //BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT |
37395 | #define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37396 | #define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
37397 | #define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
37398 | #define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
37399 | //BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT |
37400 | #define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37401 | #define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
37402 | #define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
37403 | #define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
37404 | //BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT |
37405 | #define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
37406 | #define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
37407 | #define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
37408 | #define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
37409 | //BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST |
37410 | #define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
37411 | #define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
37412 | #define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
37413 | #define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
37414 | #define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
37415 | #define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
37416 | //BIF_CFG_DEV1_RC0_MARGINING_PORT_CAP |
37417 | #define BIF_CFG_DEV1_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
37418 | #define BIF_CFG_DEV1_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
37419 | //BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS |
37420 | #define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
37421 | #define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
37422 | #define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
37423 | #define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
37424 | //BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL |
37425 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
37426 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
37427 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
37428 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
37429 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
37430 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
37431 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
37432 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
37433 | //BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS |
37434 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37435 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37436 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
37437 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37438 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37439 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
37440 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
37441 | #define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37442 | //BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL |
37443 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
37444 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
37445 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
37446 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
37447 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
37448 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
37449 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
37450 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
37451 | //BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS |
37452 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37453 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37454 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
37455 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37456 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37457 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
37458 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
37459 | #define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37460 | //BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL |
37461 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
37462 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
37463 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
37464 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
37465 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
37466 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
37467 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
37468 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
37469 | //BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS |
37470 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37471 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37472 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
37473 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37474 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37475 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
37476 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
37477 | #define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37478 | //BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL |
37479 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
37480 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
37481 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
37482 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
37483 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
37484 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
37485 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
37486 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
37487 | //BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS |
37488 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37489 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37490 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
37491 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37492 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37493 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
37494 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
37495 | #define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37496 | //BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL |
37497 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
37498 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
37499 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
37500 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
37501 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
37502 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
37503 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
37504 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
37505 | //BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS |
37506 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37507 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37508 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
37509 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37510 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37511 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
37512 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
37513 | #define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37514 | //BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL |
37515 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
37516 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
37517 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
37518 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
37519 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
37520 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
37521 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
37522 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
37523 | //BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS |
37524 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37525 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37526 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
37527 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37528 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37529 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
37530 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
37531 | #define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37532 | //BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL |
37533 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
37534 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
37535 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
37536 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
37537 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
37538 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
37539 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
37540 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
37541 | //BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS |
37542 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37543 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37544 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
37545 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37546 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37547 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
37548 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
37549 | #define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37550 | //BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL |
37551 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
37552 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
37553 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
37554 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
37555 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
37556 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
37557 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
37558 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
37559 | //BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS |
37560 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37561 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37562 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
37563 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37564 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37565 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
37566 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
37567 | #define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37568 | //BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL |
37569 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
37570 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
37571 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
37572 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
37573 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
37574 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
37575 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
37576 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
37577 | //BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS |
37578 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37579 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37580 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
37581 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37582 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37583 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
37584 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
37585 | #define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37586 | //BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL |
37587 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
37588 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
37589 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
37590 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
37591 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
37592 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
37593 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
37594 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
37595 | //BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS |
37596 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37597 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37598 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
37599 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37600 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37601 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
37602 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
37603 | #define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37604 | //BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL |
37605 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
37606 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
37607 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
37608 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
37609 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
37610 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
37611 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
37612 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
37613 | //BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS |
37614 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37615 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37616 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
37617 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37618 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37619 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
37620 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
37621 | #define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37622 | //BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL |
37623 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
37624 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
37625 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
37626 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
37627 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
37628 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
37629 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
37630 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
37631 | //BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS |
37632 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37633 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37634 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
37635 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37636 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37637 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
37638 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
37639 | #define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37640 | //BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL |
37641 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
37642 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
37643 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
37644 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
37645 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
37646 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
37647 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
37648 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
37649 | //BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS |
37650 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37651 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37652 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
37653 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37654 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37655 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
37656 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
37657 | #define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37658 | //BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL |
37659 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
37660 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
37661 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
37662 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
37663 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
37664 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
37665 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
37666 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
37667 | //BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS |
37668 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37669 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37670 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
37671 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37672 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37673 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
37674 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
37675 | #define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37676 | //BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL |
37677 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
37678 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
37679 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
37680 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
37681 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
37682 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
37683 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
37684 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
37685 | //BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS |
37686 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37687 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37688 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
37689 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37690 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37691 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
37692 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
37693 | #define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37694 | //BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL |
37695 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
37696 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
37697 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
37698 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
37699 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
37700 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
37701 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
37702 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
37703 | //BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS |
37704 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
37705 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
37706 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
37707 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
37708 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
37709 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
37710 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
37711 | #define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
37712 | //BIF_CFG_DEV1_RC0_PCIE_RTR_ENH_CAP_LIST |
37713 | #define BIF_CFG_DEV1_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
37714 | #define BIF_CFG_DEV1_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
37715 | #define BIF_CFG_DEV1_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
37716 | #define BIF_CFG_DEV1_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
37717 | #define BIF_CFG_DEV1_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
37718 | #define BIF_CFG_DEV1_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
37719 | //BIF_CFG_DEV1_RC0_RTR_DATA1 |
37720 | #define BIF_CFG_DEV1_RC0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
37721 | #define BIF_CFG_DEV1_RC0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
37722 | #define BIF_CFG_DEV1_RC0_RTR_DATA1__VALID__SHIFT 0x1f |
37723 | #define BIF_CFG_DEV1_RC0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
37724 | #define BIF_CFG_DEV1_RC0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
37725 | #define BIF_CFG_DEV1_RC0_RTR_DATA1__VALID_MASK 0x80000000L |
37726 | //BIF_CFG_DEV1_RC0_RTR_DATA2 |
37727 | #define BIF_CFG_DEV1_RC0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
37728 | #define BIF_CFG_DEV1_RC0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
37729 | #define BIF_CFG_DEV1_RC0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
37730 | #define BIF_CFG_DEV1_RC0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
37731 | |
37732 | |
37733 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp |
37734 | //BIF_CFG_DEV1_EPF0_0_VENDOR_ID |
37735 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
37736 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
37737 | //BIF_CFG_DEV1_EPF0_0_DEVICE_ID |
37738 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
37739 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
37740 | //BIF_CFG_DEV1_EPF0_0_COMMAND |
37741 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
37742 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
37743 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
37744 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
37745 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
37746 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
37747 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
37748 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8 |
37749 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
37750 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa |
37751 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
37752 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
37753 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
37754 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
37755 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
37756 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
37757 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L |
37758 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L |
37759 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
37760 | #define BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L |
37761 | //BIF_CFG_DEV1_EPF0_0_STATUS |
37762 | #define BIF_CFG_DEV1_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
37763 | #define BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3 |
37764 | #define BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4 |
37765 | #define BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
37766 | #define BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
37767 | #define BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
37768 | #define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
37769 | #define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
37770 | #define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
37771 | #define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
37772 | #define BIF_CFG_DEV1_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
37773 | #define BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L |
37774 | #define BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L |
37775 | #define BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_CAP_MASK 0x0020L |
37776 | #define BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
37777 | #define BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
37778 | #define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
37779 | #define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
37780 | #define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
37781 | #define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
37782 | //BIF_CFG_DEV1_EPF0_0_REVISION_ID |
37783 | #define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
37784 | #define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
37785 | #define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
37786 | #define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
37787 | //BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE |
37788 | #define BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
37789 | #define BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
37790 | //BIF_CFG_DEV1_EPF0_0_SUB_CLASS |
37791 | #define BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
37792 | #define BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
37793 | //BIF_CFG_DEV1_EPF0_0_BASE_CLASS |
37794 | #define BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
37795 | #define BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
37796 | //BIF_CFG_DEV1_EPF0_0_CACHE_LINE |
37797 | #define BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
37798 | #define BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
37799 | //BIF_CFG_DEV1_EPF0_0_LATENCY |
37800 | #define BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
37801 | #define BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
37802 | //BIF_CFG_DEV1_EPF0_0_HEADER |
37803 | #define 0x0 |
37804 | #define 0x7 |
37805 | #define 0x7FL |
37806 | #define 0x80L |
37807 | //BIF_CFG_DEV1_EPF0_0_BIST |
37808 | #define BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP__SHIFT 0x0 |
37809 | #define BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT__SHIFT 0x6 |
37810 | #define BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP__SHIFT 0x7 |
37811 | #define BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP_MASK 0x0FL |
37812 | #define BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT_MASK 0x40L |
37813 | #define BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP_MASK 0x80L |
37814 | //BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1 |
37815 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
37816 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
37817 | //BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2 |
37818 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
37819 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
37820 | //BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3 |
37821 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
37822 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
37823 | //BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4 |
37824 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
37825 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
37826 | //BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5 |
37827 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
37828 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
37829 | //BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6 |
37830 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
37831 | #define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
37832 | //BIF_CFG_DEV1_EPF0_0_ADAPTER_ID |
37833 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
37834 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
37835 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
37836 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
37837 | //BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR |
37838 | #define BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
37839 | #define BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
37840 | //BIF_CFG_DEV1_EPF0_0_CAP_PTR |
37841 | #define BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
37842 | #define BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
37843 | //BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE |
37844 | #define BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
37845 | #define BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
37846 | //BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN |
37847 | #define BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
37848 | #define BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
37849 | //BIF_CFG_DEV1_EPF0_0_MIN_GRANT |
37850 | #define BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
37851 | #define BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
37852 | //BIF_CFG_DEV1_EPF0_0_MAX_LATENCY |
37853 | #define BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
37854 | #define BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
37855 | //BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST |
37856 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
37857 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
37858 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
37859 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
37860 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
37861 | #define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
37862 | //BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W |
37863 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
37864 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
37865 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
37866 | #define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
37867 | //BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST |
37868 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
37869 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
37870 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
37871 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
37872 | //BIF_CFG_DEV1_EPF0_0_PMI_CAP |
37873 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0 |
37874 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
37875 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
37876 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
37877 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
37878 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
37879 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
37880 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
37881 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L |
37882 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
37883 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
37884 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
37885 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
37886 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
37887 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
37888 | #define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
37889 | //BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL |
37890 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
37891 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
37892 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
37893 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
37894 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
37895 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
37896 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
37897 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
37898 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
37899 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
37900 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
37901 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
37902 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
37903 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
37904 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
37905 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
37906 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
37907 | #define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
37908 | //BIF_CFG_DEV1_EPF0_0_SBRN |
37909 | #define BIF_CFG_DEV1_EPF0_0_SBRN__SBRN__SHIFT 0x0 |
37910 | #define BIF_CFG_DEV1_EPF0_0_SBRN__SBRN_MASK 0xFFL |
37911 | //BIF_CFG_DEV1_EPF0_0_FLADJ |
37912 | #define BIF_CFG_DEV1_EPF0_0_FLADJ__FLADJ__SHIFT 0x0 |
37913 | #define BIF_CFG_DEV1_EPF0_0_FLADJ__NFC__SHIFT 0x6 |
37914 | #define BIF_CFG_DEV1_EPF0_0_FLADJ__FLADJ_MASK 0x3FL |
37915 | #define BIF_CFG_DEV1_EPF0_0_FLADJ__NFC_MASK 0x40L |
37916 | //BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD |
37917 | #define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
37918 | #define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
37919 | #define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
37920 | #define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
37921 | //BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST |
37922 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
37923 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
37924 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
37925 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
37926 | //BIF_CFG_DEV1_EPF0_0_PCIE_CAP |
37927 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0 |
37928 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
37929 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
37930 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
37931 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL |
37932 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
37933 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
37934 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
37935 | //BIF_CFG_DEV1_EPF0_0_DEVICE_CAP |
37936 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
37937 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
37938 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
37939 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
37940 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
37941 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
37942 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
37943 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
37944 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
37945 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
37946 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
37947 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
37948 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
37949 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
37950 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
37951 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
37952 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
37953 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
37954 | //BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL |
37955 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
37956 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
37957 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
37958 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
37959 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
37960 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
37961 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
37962 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
37963 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
37964 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
37965 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
37966 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
37967 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
37968 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
37969 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
37970 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
37971 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
37972 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
37973 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
37974 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
37975 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
37976 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
37977 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
37978 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
37979 | //BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS |
37980 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
37981 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
37982 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
37983 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
37984 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
37985 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
37986 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
37987 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
37988 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
37989 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
37990 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
37991 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
37992 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
37993 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
37994 | //BIF_CFG_DEV1_EPF0_0_LINK_CAP |
37995 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
37996 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
37997 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
37998 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
37999 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
38000 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
38001 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
38002 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
38003 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
38004 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
38005 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
38006 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
38007 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
38008 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
38009 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
38010 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
38011 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
38012 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
38013 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
38014 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
38015 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
38016 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
38017 | //BIF_CFG_DEV1_EPF0_0_LINK_CNTL |
38018 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
38019 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
38020 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
38021 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
38022 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
38023 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
38024 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
38025 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
38026 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
38027 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
38028 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
38029 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
38030 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
38031 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
38032 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
38033 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
38034 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
38035 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
38036 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
38037 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
38038 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
38039 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
38040 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
38041 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
38042 | //BIF_CFG_DEV1_EPF0_0_LINK_STATUS |
38043 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
38044 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
38045 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
38046 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
38047 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
38048 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
38049 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
38050 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
38051 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
38052 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
38053 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
38054 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
38055 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
38056 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
38057 | //BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2 |
38058 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
38059 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
38060 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
38061 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
38062 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
38063 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
38064 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
38065 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
38066 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
38067 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
38068 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
38069 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
38070 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
38071 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
38072 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
38073 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
38074 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
38075 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
38076 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
38077 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
38078 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
38079 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
38080 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
38081 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
38082 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
38083 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
38084 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
38085 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
38086 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
38087 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
38088 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
38089 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
38090 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
38091 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
38092 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
38093 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
38094 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
38095 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
38096 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
38097 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
38098 | //BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2 |
38099 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
38100 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
38101 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
38102 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
38103 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
38104 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
38105 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
38106 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
38107 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
38108 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
38109 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
38110 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
38111 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
38112 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
38113 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
38114 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
38115 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
38116 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
38117 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
38118 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
38119 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
38120 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
38121 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
38122 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
38123 | //BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2 |
38124 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
38125 | #define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
38126 | //BIF_CFG_DEV1_EPF0_0_LINK_CAP2 |
38127 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
38128 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
38129 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
38130 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
38131 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
38132 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
38133 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
38134 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
38135 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
38136 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
38137 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
38138 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
38139 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
38140 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
38141 | //BIF_CFG_DEV1_EPF0_0_LINK_CNTL2 |
38142 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
38143 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
38144 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
38145 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
38146 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
38147 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
38148 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
38149 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
38150 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
38151 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
38152 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
38153 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
38154 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
38155 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
38156 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
38157 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
38158 | //BIF_CFG_DEV1_EPF0_0_LINK_STATUS2 |
38159 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
38160 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
38161 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
38162 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
38163 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
38164 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
38165 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
38166 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
38167 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
38168 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
38169 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
38170 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
38171 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
38172 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
38173 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
38174 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
38175 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
38176 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
38177 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
38178 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
38179 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
38180 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
38181 | //BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST |
38182 | #define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
38183 | #define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
38184 | #define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
38185 | #define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
38186 | //BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL |
38187 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
38188 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
38189 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
38190 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
38191 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
38192 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
38193 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
38194 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
38195 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
38196 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
38197 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
38198 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
38199 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
38200 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
38201 | //BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO |
38202 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
38203 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
38204 | //BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI |
38205 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
38206 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
38207 | //BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA |
38208 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
38209 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
38210 | //BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA |
38211 | #define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
38212 | #define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
38213 | //BIF_CFG_DEV1_EPF0_0_MSI_MASK |
38214 | #define BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
38215 | #define BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
38216 | //BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64 |
38217 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
38218 | #define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
38219 | //BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64 |
38220 | #define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
38221 | #define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
38222 | //BIF_CFG_DEV1_EPF0_0_MSI_MASK_64 |
38223 | #define BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
38224 | #define BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
38225 | //BIF_CFG_DEV1_EPF0_0_MSI_PENDING |
38226 | #define BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
38227 | #define BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
38228 | //BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64 |
38229 | #define BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
38230 | #define BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
38231 | //BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST |
38232 | #define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
38233 | #define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
38234 | #define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
38235 | #define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
38236 | //BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL |
38237 | #define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
38238 | #define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
38239 | #define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
38240 | #define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
38241 | #define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
38242 | #define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
38243 | //BIF_CFG_DEV1_EPF0_0_MSIX_TABLE |
38244 | #define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
38245 | #define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
38246 | #define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
38247 | #define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
38248 | //BIF_CFG_DEV1_EPF0_0_MSIX_PBA |
38249 | #define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
38250 | #define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
38251 | #define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
38252 | #define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
38253 | //BIF_CFG_DEV1_EPF0_0_SATA_CAP_0 |
38254 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
38255 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
38256 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
38257 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
38258 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
38259 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
38260 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
38261 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
38262 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
38263 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
38264 | //BIF_CFG_DEV1_EPF0_0_SATA_CAP_1 |
38265 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
38266 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
38267 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
38268 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
38269 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
38270 | #define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
38271 | //BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX |
38272 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
38273 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
38274 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
38275 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
38276 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
38277 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
38278 | //BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA |
38279 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
38280 | #define BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
38281 | //BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
38282 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38283 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38284 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38285 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38286 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38287 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38288 | //BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR |
38289 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
38290 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
38291 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
38292 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
38293 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
38294 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
38295 | //BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1 |
38296 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
38297 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
38298 | //BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2 |
38299 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
38300 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
38301 | //BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST |
38302 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38303 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38304 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38305 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38306 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38307 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38308 | //BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1 |
38309 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
38310 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
38311 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
38312 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
38313 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
38314 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
38315 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
38316 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
38317 | //BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2 |
38318 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
38319 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
38320 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
38321 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
38322 | //BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL |
38323 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
38324 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
38325 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
38326 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
38327 | //BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS |
38328 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
38329 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
38330 | //BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP |
38331 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
38332 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
38333 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
38334 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
38335 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
38336 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
38337 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
38338 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
38339 | //BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL |
38340 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
38341 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
38342 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
38343 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
38344 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
38345 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
38346 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
38347 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
38348 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
38349 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
38350 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
38351 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
38352 | //BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS |
38353 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
38354 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
38355 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
38356 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
38357 | //BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP |
38358 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
38359 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
38360 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
38361 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
38362 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
38363 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
38364 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
38365 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
38366 | //BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL |
38367 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
38368 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
38369 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
38370 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
38371 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
38372 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
38373 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
38374 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
38375 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
38376 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
38377 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
38378 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
38379 | //BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS |
38380 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
38381 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
38382 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
38383 | #define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
38384 | //BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
38385 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38386 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38387 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38388 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38389 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38390 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38391 | //BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS |
38392 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
38393 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
38394 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
38395 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
38396 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
38397 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
38398 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
38399 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
38400 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
38401 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
38402 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
38403 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
38404 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
38405 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
38406 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
38407 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
38408 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
38409 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
38410 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
38411 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
38412 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
38413 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
38414 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
38415 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
38416 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
38417 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
38418 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
38419 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
38420 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
38421 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
38422 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
38423 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
38424 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
38425 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
38426 | //BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK |
38427 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
38428 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
38429 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
38430 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
38431 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
38432 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
38433 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
38434 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
38435 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
38436 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
38437 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
38438 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
38439 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
38440 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
38441 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
38442 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
38443 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
38444 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
38445 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
38446 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
38447 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
38448 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
38449 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
38450 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
38451 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
38452 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
38453 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
38454 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
38455 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
38456 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
38457 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
38458 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
38459 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
38460 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
38461 | //BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY |
38462 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
38463 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
38464 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
38465 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
38466 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
38467 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
38468 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
38469 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
38470 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
38471 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
38472 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
38473 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
38474 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
38475 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
38476 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
38477 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
38478 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
38479 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
38480 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
38481 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
38482 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
38483 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
38484 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
38485 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
38486 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
38487 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
38488 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
38489 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
38490 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
38491 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
38492 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
38493 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
38494 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
38495 | #define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
38496 | //BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS |
38497 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
38498 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
38499 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
38500 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
38501 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
38502 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
38503 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
38504 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
38505 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
38506 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
38507 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
38508 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
38509 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
38510 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
38511 | //BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK |
38512 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
38513 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
38514 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
38515 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
38516 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
38517 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
38518 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
38519 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
38520 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
38521 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
38522 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
38523 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
38524 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
38525 | #define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
38526 | //BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL |
38527 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
38528 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
38529 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
38530 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
38531 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
38532 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
38533 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
38534 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
38535 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
38536 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
38537 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
38538 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
38539 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
38540 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
38541 | //BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0 |
38542 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
38543 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
38544 | //BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1 |
38545 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
38546 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
38547 | //BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2 |
38548 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
38549 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
38550 | //BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3 |
38551 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
38552 | #define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
38553 | //BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0 |
38554 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
38555 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
38556 | //BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1 |
38557 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
38558 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
38559 | //BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2 |
38560 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
38561 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
38562 | //BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3 |
38563 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
38564 | #define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
38565 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST |
38566 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38567 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38568 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38569 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38570 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38571 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38572 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP |
38573 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
38574 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
38575 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL |
38576 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
38577 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
38578 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
38579 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
38580 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
38581 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
38582 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
38583 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
38584 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP |
38585 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
38586 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
38587 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL |
38588 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
38589 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
38590 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
38591 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
38592 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
38593 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
38594 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
38595 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
38596 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP |
38597 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
38598 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
38599 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL |
38600 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
38601 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
38602 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
38603 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
38604 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
38605 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
38606 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
38607 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
38608 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP |
38609 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
38610 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
38611 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL |
38612 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
38613 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
38614 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
38615 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
38616 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
38617 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
38618 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
38619 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
38620 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP |
38621 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
38622 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
38623 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL |
38624 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
38625 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
38626 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
38627 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
38628 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
38629 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
38630 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
38631 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
38632 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP |
38633 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
38634 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
38635 | //BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL |
38636 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
38637 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
38638 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
38639 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
38640 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
38641 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
38642 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
38643 | #define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
38644 | //BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
38645 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38646 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38647 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38648 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38649 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38650 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38651 | //BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT |
38652 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
38653 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
38654 | //BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA |
38655 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
38656 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
38657 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
38658 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
38659 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
38660 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
38661 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
38662 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
38663 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
38664 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
38665 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
38666 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
38667 | //BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP |
38668 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
38669 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
38670 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST |
38671 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38672 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38673 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38674 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38675 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38676 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38677 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP |
38678 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
38679 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
38680 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
38681 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
38682 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
38683 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
38684 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
38685 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
38686 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
38687 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
38688 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR |
38689 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
38690 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
38691 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS |
38692 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
38693 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
38694 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
38695 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
38696 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL |
38697 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
38698 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
38699 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
38700 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
38701 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
38702 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
38703 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
38704 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
38705 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
38706 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
38707 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
38708 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
38709 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
38710 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
38711 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
38712 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
38713 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
38714 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
38715 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
38716 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
38717 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
38718 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
38719 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
38720 | //BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
38721 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
38722 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
38723 | //BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST |
38724 | #define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38725 | #define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38726 | #define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38727 | #define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38728 | #define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38729 | #define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38730 | //BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3 |
38731 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
38732 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
38733 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
38734 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
38735 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
38736 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
38737 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS |
38738 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
38739 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
38740 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL |
38741 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38742 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38743 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38744 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38745 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38746 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38747 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38748 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38749 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL |
38750 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38751 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38752 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38753 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38754 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38755 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38756 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38757 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38758 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL |
38759 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38760 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38761 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38762 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38763 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38764 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38765 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38766 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38767 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL |
38768 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38769 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38770 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38771 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38772 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38773 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38774 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38775 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38776 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL |
38777 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38778 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38779 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38780 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38781 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38782 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38783 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38784 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38785 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL |
38786 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38787 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38788 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38789 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38790 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38791 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38792 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38793 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38794 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL |
38795 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38796 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38797 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38798 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38799 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38800 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38801 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38802 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38803 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL |
38804 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38805 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38806 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38807 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38808 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38809 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38810 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38811 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38812 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL |
38813 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38814 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38815 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38816 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38817 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38818 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38819 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38820 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38821 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL |
38822 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38823 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38824 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38825 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38826 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38827 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38828 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38829 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38830 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL |
38831 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38832 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38833 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38834 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38835 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38836 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38837 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38838 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38839 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL |
38840 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38841 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38842 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38843 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38844 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38845 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38846 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38847 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38848 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL |
38849 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38850 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38851 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38852 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38853 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38854 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38855 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38856 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38857 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL |
38858 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38859 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38860 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38861 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38862 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38863 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38864 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38865 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38866 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL |
38867 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38868 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38869 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38870 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38871 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38872 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38873 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38874 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38875 | //BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL |
38876 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
38877 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
38878 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
38879 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
38880 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
38881 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
38882 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
38883 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
38884 | //BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST |
38885 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38886 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38887 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38888 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38889 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38890 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38891 | //BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP |
38892 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
38893 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
38894 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
38895 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
38896 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
38897 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
38898 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
38899 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
38900 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
38901 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
38902 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
38903 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
38904 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
38905 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
38906 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
38907 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
38908 | //BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL |
38909 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
38910 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
38911 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
38912 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
38913 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
38914 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
38915 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
38916 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
38917 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
38918 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
38919 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
38920 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
38921 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
38922 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
38923 | //BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST |
38924 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38925 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38926 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38927 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38928 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38929 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38930 | //BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP |
38931 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
38932 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
38933 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
38934 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
38935 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
38936 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
38937 | //BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL |
38938 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
38939 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
38940 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
38941 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
38942 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
38943 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
38944 | //BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST |
38945 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38946 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38947 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38948 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38949 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38950 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38951 | //BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP |
38952 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
38953 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
38954 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
38955 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
38956 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
38957 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
38958 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
38959 | #define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
38960 | //BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST |
38961 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38962 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38963 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38964 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38965 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38966 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38967 | //BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP |
38968 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
38969 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
38970 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
38971 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
38972 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
38973 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
38974 | //BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL |
38975 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
38976 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
38977 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
38978 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
38979 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
38980 | #define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
38981 | //BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST |
38982 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
38983 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
38984 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
38985 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
38986 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
38987 | #define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
38988 | //BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP |
38989 | #define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
38990 | #define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
38991 | #define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
38992 | #define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
38993 | //BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS |
38994 | #define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
38995 | #define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
38996 | #define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
38997 | #define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
38998 | //BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST |
38999 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39000 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39001 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39002 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39003 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39004 | #define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39005 | //BIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT |
39006 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
39007 | #define BIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
39008 | //BIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT |
39009 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
39010 | #define BIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
39011 | //BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT |
39012 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
39013 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
39014 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
39015 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
39016 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
39017 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
39018 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
39019 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
39020 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
39021 | #define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
39022 | //BIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT |
39023 | #define BIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
39024 | #define BIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
39025 | //BIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT |
39026 | #define BIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
39027 | #define BIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
39028 | //BIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT |
39029 | #define BIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
39030 | #define BIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
39031 | //BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT |
39032 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39033 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
39034 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
39035 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
39036 | //BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT |
39037 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39038 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
39039 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
39040 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
39041 | //BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT |
39042 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39043 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
39044 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
39045 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
39046 | //BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT |
39047 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39048 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
39049 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
39050 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
39051 | //BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT |
39052 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39053 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
39054 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
39055 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
39056 | //BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT |
39057 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39058 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
39059 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
39060 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
39061 | //BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT |
39062 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39063 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
39064 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
39065 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
39066 | //BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT |
39067 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39068 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
39069 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
39070 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
39071 | //BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT |
39072 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39073 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
39074 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
39075 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
39076 | //BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT |
39077 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39078 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
39079 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
39080 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
39081 | //BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT |
39082 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39083 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
39084 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
39085 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
39086 | //BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT |
39087 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39088 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
39089 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
39090 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
39091 | //BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT |
39092 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39093 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
39094 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
39095 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
39096 | //BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT |
39097 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39098 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
39099 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
39100 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
39101 | //BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT |
39102 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39103 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
39104 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
39105 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
39106 | //BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT |
39107 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
39108 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
39109 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
39110 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
39111 | //BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST |
39112 | #define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39113 | #define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39114 | #define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39115 | #define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39116 | #define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39117 | #define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39118 | //BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP |
39119 | #define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
39120 | #define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
39121 | //BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS |
39122 | #define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
39123 | #define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
39124 | #define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
39125 | #define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
39126 | //BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL |
39127 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
39128 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
39129 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
39130 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
39131 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
39132 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
39133 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
39134 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
39135 | //BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS |
39136 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39137 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39138 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
39139 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39140 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39141 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
39142 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
39143 | #define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39144 | //BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL |
39145 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
39146 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
39147 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
39148 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
39149 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
39150 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
39151 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
39152 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
39153 | //BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS |
39154 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39155 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39156 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
39157 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39158 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39159 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
39160 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
39161 | #define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39162 | //BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL |
39163 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
39164 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
39165 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
39166 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
39167 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
39168 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
39169 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
39170 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
39171 | //BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS |
39172 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39173 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39174 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
39175 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39176 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39177 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
39178 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
39179 | #define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39180 | //BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL |
39181 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
39182 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
39183 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
39184 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
39185 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
39186 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
39187 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
39188 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
39189 | //BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS |
39190 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39191 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39192 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
39193 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39194 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39195 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
39196 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
39197 | #define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39198 | //BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL |
39199 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
39200 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
39201 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
39202 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
39203 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
39204 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
39205 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
39206 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
39207 | //BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS |
39208 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39209 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39210 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
39211 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39212 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39213 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
39214 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
39215 | #define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39216 | //BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL |
39217 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
39218 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
39219 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
39220 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
39221 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
39222 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
39223 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
39224 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
39225 | //BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS |
39226 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39227 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39228 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
39229 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39230 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39231 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
39232 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
39233 | #define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39234 | //BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL |
39235 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
39236 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
39237 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
39238 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
39239 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
39240 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
39241 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
39242 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
39243 | //BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS |
39244 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39245 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39246 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
39247 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39248 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39249 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
39250 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
39251 | #define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39252 | //BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL |
39253 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
39254 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
39255 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
39256 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
39257 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
39258 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
39259 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
39260 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
39261 | //BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS |
39262 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39263 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39264 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
39265 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39266 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39267 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
39268 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
39269 | #define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39270 | //BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL |
39271 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
39272 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
39273 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
39274 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
39275 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
39276 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
39277 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
39278 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
39279 | //BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS |
39280 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39281 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39282 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
39283 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39284 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39285 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
39286 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
39287 | #define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39288 | //BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL |
39289 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
39290 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
39291 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
39292 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
39293 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
39294 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
39295 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
39296 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
39297 | //BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS |
39298 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39299 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39300 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
39301 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39302 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39303 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
39304 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
39305 | #define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39306 | //BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL |
39307 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
39308 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
39309 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
39310 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
39311 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
39312 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
39313 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
39314 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
39315 | //BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS |
39316 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39317 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39318 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
39319 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39320 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39321 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
39322 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
39323 | #define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39324 | //BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL |
39325 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
39326 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
39327 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
39328 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
39329 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
39330 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
39331 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
39332 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
39333 | //BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS |
39334 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39335 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39336 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
39337 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39338 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39339 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
39340 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
39341 | #define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39342 | //BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL |
39343 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
39344 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
39345 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
39346 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
39347 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
39348 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
39349 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
39350 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
39351 | //BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS |
39352 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39353 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39354 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
39355 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39356 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39357 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
39358 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
39359 | #define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39360 | //BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL |
39361 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
39362 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
39363 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
39364 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
39365 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
39366 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
39367 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
39368 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
39369 | //BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS |
39370 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39371 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39372 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
39373 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39374 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39375 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
39376 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
39377 | #define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39378 | //BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL |
39379 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
39380 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
39381 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
39382 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
39383 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
39384 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
39385 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
39386 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
39387 | //BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS |
39388 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39389 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39390 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
39391 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39392 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39393 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
39394 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
39395 | #define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39396 | //BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL |
39397 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
39398 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
39399 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
39400 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
39401 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
39402 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
39403 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
39404 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
39405 | //BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS |
39406 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
39407 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
39408 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
39409 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
39410 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
39411 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
39412 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
39413 | #define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
39414 | //BIF_CFG_DEV1_EPF0_0_PCIE_RTR_ENH_CAP_LIST |
39415 | #define BIF_CFG_DEV1_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39416 | #define BIF_CFG_DEV1_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39417 | #define BIF_CFG_DEV1_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39418 | #define BIF_CFG_DEV1_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39419 | #define BIF_CFG_DEV1_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39420 | #define BIF_CFG_DEV1_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39421 | //BIF_CFG_DEV1_EPF0_0_RTR_DATA1 |
39422 | #define BIF_CFG_DEV1_EPF0_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
39423 | #define BIF_CFG_DEV1_EPF0_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
39424 | #define BIF_CFG_DEV1_EPF0_0_RTR_DATA1__VALID__SHIFT 0x1f |
39425 | #define BIF_CFG_DEV1_EPF0_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
39426 | #define BIF_CFG_DEV1_EPF0_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
39427 | #define BIF_CFG_DEV1_EPF0_0_RTR_DATA1__VALID_MASK 0x80000000L |
39428 | //BIF_CFG_DEV1_EPF0_0_RTR_DATA2 |
39429 | #define BIF_CFG_DEV1_EPF0_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
39430 | #define BIF_CFG_DEV1_EPF0_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
39431 | #define BIF_CFG_DEV1_EPF0_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
39432 | #define BIF_CFG_DEV1_EPF0_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
39433 | |
39434 | |
39435 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp |
39436 | //BIF_CFG_DEV1_EPF1_0_VENDOR_ID |
39437 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
39438 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
39439 | //BIF_CFG_DEV1_EPF1_0_DEVICE_ID |
39440 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
39441 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
39442 | //BIF_CFG_DEV1_EPF1_0_COMMAND |
39443 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
39444 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
39445 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
39446 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
39447 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
39448 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
39449 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
39450 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8 |
39451 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
39452 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa |
39453 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
39454 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
39455 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
39456 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
39457 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
39458 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
39459 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L |
39460 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L |
39461 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
39462 | #define BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L |
39463 | //BIF_CFG_DEV1_EPF1_0_STATUS |
39464 | #define BIF_CFG_DEV1_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
39465 | #define BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3 |
39466 | #define BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4 |
39467 | #define BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
39468 | #define BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
39469 | #define BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
39470 | #define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
39471 | #define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
39472 | #define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
39473 | #define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
39474 | #define BIF_CFG_DEV1_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
39475 | #define BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L |
39476 | #define BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L |
39477 | #define BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_CAP_MASK 0x0020L |
39478 | #define BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
39479 | #define BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
39480 | #define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
39481 | #define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
39482 | #define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
39483 | #define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
39484 | //BIF_CFG_DEV1_EPF1_0_REVISION_ID |
39485 | #define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
39486 | #define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
39487 | #define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
39488 | #define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
39489 | //BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE |
39490 | #define BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
39491 | #define BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
39492 | //BIF_CFG_DEV1_EPF1_0_SUB_CLASS |
39493 | #define BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
39494 | #define BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
39495 | //BIF_CFG_DEV1_EPF1_0_BASE_CLASS |
39496 | #define BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
39497 | #define BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
39498 | //BIF_CFG_DEV1_EPF1_0_CACHE_LINE |
39499 | #define BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
39500 | #define BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
39501 | //BIF_CFG_DEV1_EPF1_0_LATENCY |
39502 | #define BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
39503 | #define BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
39504 | //BIF_CFG_DEV1_EPF1_0_HEADER |
39505 | #define 0x0 |
39506 | #define 0x7 |
39507 | #define 0x7FL |
39508 | #define 0x80L |
39509 | //BIF_CFG_DEV1_EPF1_0_BIST |
39510 | #define BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP__SHIFT 0x0 |
39511 | #define BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT__SHIFT 0x6 |
39512 | #define BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP__SHIFT 0x7 |
39513 | #define BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP_MASK 0x0FL |
39514 | #define BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT_MASK 0x40L |
39515 | #define BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP_MASK 0x80L |
39516 | //BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1 |
39517 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
39518 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
39519 | //BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2 |
39520 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
39521 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
39522 | //BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3 |
39523 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
39524 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
39525 | //BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4 |
39526 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
39527 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
39528 | //BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5 |
39529 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
39530 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
39531 | //BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6 |
39532 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
39533 | #define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
39534 | //BIF_CFG_DEV1_EPF1_0_ADAPTER_ID |
39535 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
39536 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
39537 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
39538 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
39539 | //BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR |
39540 | #define BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
39541 | #define BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
39542 | //BIF_CFG_DEV1_EPF1_0_CAP_PTR |
39543 | #define BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
39544 | #define BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
39545 | //BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE |
39546 | #define BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
39547 | #define BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
39548 | //BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN |
39549 | #define BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
39550 | #define BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
39551 | //BIF_CFG_DEV1_EPF1_0_MIN_GRANT |
39552 | #define BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
39553 | #define BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
39554 | //BIF_CFG_DEV1_EPF1_0_MAX_LATENCY |
39555 | #define BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
39556 | #define BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
39557 | //BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST |
39558 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
39559 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
39560 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
39561 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
39562 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
39563 | #define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
39564 | //BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W |
39565 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
39566 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
39567 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
39568 | #define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
39569 | //BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST |
39570 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
39571 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
39572 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
39573 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
39574 | //BIF_CFG_DEV1_EPF1_0_PMI_CAP |
39575 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0 |
39576 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
39577 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
39578 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
39579 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
39580 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
39581 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
39582 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
39583 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L |
39584 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
39585 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
39586 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
39587 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
39588 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
39589 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
39590 | #define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
39591 | //BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL |
39592 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
39593 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
39594 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
39595 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
39596 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
39597 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
39598 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
39599 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
39600 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
39601 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
39602 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
39603 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
39604 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
39605 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
39606 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
39607 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
39608 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
39609 | #define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
39610 | //BIF_CFG_DEV1_EPF1_0_SBRN |
39611 | #define BIF_CFG_DEV1_EPF1_0_SBRN__SBRN__SHIFT 0x0 |
39612 | #define BIF_CFG_DEV1_EPF1_0_SBRN__SBRN_MASK 0xFFL |
39613 | //BIF_CFG_DEV1_EPF1_0_FLADJ |
39614 | #define BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ__SHIFT 0x0 |
39615 | #define BIF_CFG_DEV1_EPF1_0_FLADJ__NFC__SHIFT 0x6 |
39616 | #define BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ_MASK 0x3FL |
39617 | #define BIF_CFG_DEV1_EPF1_0_FLADJ__NFC_MASK 0x40L |
39618 | //BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD |
39619 | #define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
39620 | #define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
39621 | #define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
39622 | #define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
39623 | //BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST |
39624 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
39625 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
39626 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
39627 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
39628 | //BIF_CFG_DEV1_EPF1_0_PCIE_CAP |
39629 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0 |
39630 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
39631 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
39632 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
39633 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL |
39634 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
39635 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
39636 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
39637 | //BIF_CFG_DEV1_EPF1_0_DEVICE_CAP |
39638 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
39639 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
39640 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
39641 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
39642 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
39643 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
39644 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
39645 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
39646 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
39647 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
39648 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
39649 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
39650 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
39651 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
39652 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
39653 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
39654 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
39655 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
39656 | //BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL |
39657 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
39658 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
39659 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
39660 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
39661 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
39662 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
39663 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
39664 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
39665 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
39666 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
39667 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
39668 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
39669 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
39670 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
39671 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
39672 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
39673 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
39674 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
39675 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
39676 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
39677 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
39678 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
39679 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
39680 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
39681 | //BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS |
39682 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
39683 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
39684 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
39685 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
39686 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
39687 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
39688 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
39689 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
39690 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
39691 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
39692 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
39693 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
39694 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
39695 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
39696 | //BIF_CFG_DEV1_EPF1_0_LINK_CAP |
39697 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
39698 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
39699 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
39700 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
39701 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
39702 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
39703 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
39704 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
39705 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
39706 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
39707 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
39708 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
39709 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
39710 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
39711 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
39712 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
39713 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
39714 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
39715 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
39716 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
39717 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
39718 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
39719 | //BIF_CFG_DEV1_EPF1_0_LINK_CNTL |
39720 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
39721 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
39722 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
39723 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
39724 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
39725 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
39726 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
39727 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
39728 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
39729 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
39730 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
39731 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
39732 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
39733 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
39734 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
39735 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
39736 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
39737 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
39738 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
39739 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
39740 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
39741 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
39742 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
39743 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
39744 | //BIF_CFG_DEV1_EPF1_0_LINK_STATUS |
39745 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
39746 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
39747 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
39748 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
39749 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
39750 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
39751 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
39752 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
39753 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
39754 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
39755 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
39756 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
39757 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
39758 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
39759 | //BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2 |
39760 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
39761 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
39762 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
39763 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
39764 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
39765 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
39766 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
39767 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
39768 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
39769 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
39770 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
39771 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
39772 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
39773 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
39774 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
39775 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
39776 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
39777 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
39778 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
39779 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
39780 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
39781 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
39782 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
39783 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
39784 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
39785 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
39786 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
39787 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
39788 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
39789 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
39790 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
39791 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
39792 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
39793 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
39794 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
39795 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
39796 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
39797 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
39798 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
39799 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
39800 | //BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2 |
39801 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
39802 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
39803 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
39804 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
39805 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
39806 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
39807 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
39808 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
39809 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
39810 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
39811 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
39812 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
39813 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
39814 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
39815 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
39816 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
39817 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
39818 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
39819 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
39820 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
39821 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
39822 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
39823 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
39824 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
39825 | //BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2 |
39826 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
39827 | #define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
39828 | //BIF_CFG_DEV1_EPF1_0_LINK_CAP2 |
39829 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
39830 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
39831 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
39832 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
39833 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
39834 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
39835 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
39836 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
39837 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
39838 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
39839 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
39840 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
39841 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
39842 | #define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
39843 | //BIF_CFG_DEV1_EPF1_0_LINK_CNTL2 |
39844 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
39845 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
39846 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
39847 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
39848 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
39849 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
39850 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
39851 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
39852 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
39853 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
39854 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
39855 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
39856 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
39857 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
39858 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
39859 | #define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
39860 | //BIF_CFG_DEV1_EPF1_0_LINK_STATUS2 |
39861 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
39862 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
39863 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
39864 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
39865 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
39866 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
39867 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
39868 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
39869 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
39870 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
39871 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
39872 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
39873 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
39874 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
39875 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
39876 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
39877 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
39878 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
39879 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
39880 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
39881 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
39882 | #define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
39883 | //BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST |
39884 | #define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
39885 | #define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
39886 | #define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
39887 | #define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
39888 | //BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL |
39889 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
39890 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
39891 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
39892 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
39893 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
39894 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
39895 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
39896 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
39897 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
39898 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
39899 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
39900 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
39901 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
39902 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
39903 | //BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO |
39904 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
39905 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
39906 | //BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI |
39907 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
39908 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
39909 | //BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA |
39910 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
39911 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
39912 | //BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA |
39913 | #define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
39914 | #define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
39915 | //BIF_CFG_DEV1_EPF1_0_MSI_MASK |
39916 | #define BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
39917 | #define BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
39918 | //BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64 |
39919 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
39920 | #define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
39921 | //BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64 |
39922 | #define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
39923 | #define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
39924 | //BIF_CFG_DEV1_EPF1_0_MSI_MASK_64 |
39925 | #define BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
39926 | #define BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
39927 | //BIF_CFG_DEV1_EPF1_0_MSI_PENDING |
39928 | #define BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
39929 | #define BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
39930 | //BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64 |
39931 | #define BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
39932 | #define BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
39933 | //BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST |
39934 | #define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
39935 | #define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
39936 | #define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
39937 | #define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
39938 | //BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL |
39939 | #define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
39940 | #define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
39941 | #define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
39942 | #define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
39943 | #define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
39944 | #define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
39945 | //BIF_CFG_DEV1_EPF1_0_MSIX_TABLE |
39946 | #define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
39947 | #define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
39948 | #define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
39949 | #define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
39950 | //BIF_CFG_DEV1_EPF1_0_MSIX_PBA |
39951 | #define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
39952 | #define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
39953 | #define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
39954 | #define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
39955 | //BIF_CFG_DEV1_EPF1_0_SATA_CAP_0 |
39956 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
39957 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
39958 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
39959 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
39960 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
39961 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
39962 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
39963 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
39964 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
39965 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
39966 | //BIF_CFG_DEV1_EPF1_0_SATA_CAP_1 |
39967 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
39968 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
39969 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
39970 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
39971 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
39972 | #define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
39973 | //BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX |
39974 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
39975 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
39976 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
39977 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
39978 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
39979 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
39980 | //BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA |
39981 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
39982 | #define BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
39983 | //BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
39984 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
39985 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
39986 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
39987 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
39988 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
39989 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
39990 | //BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR |
39991 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
39992 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
39993 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
39994 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
39995 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
39996 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
39997 | //BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1 |
39998 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
39999 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
40000 | //BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2 |
40001 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
40002 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
40003 | //BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
40004 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40005 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40006 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40007 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40008 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40009 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40010 | //BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS |
40011 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
40012 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
40013 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
40014 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
40015 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
40016 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
40017 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
40018 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
40019 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
40020 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
40021 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
40022 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
40023 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
40024 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
40025 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
40026 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
40027 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
40028 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
40029 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
40030 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
40031 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
40032 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
40033 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
40034 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
40035 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
40036 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
40037 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
40038 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
40039 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
40040 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
40041 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
40042 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
40043 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
40044 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
40045 | //BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK |
40046 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
40047 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
40048 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
40049 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
40050 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
40051 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
40052 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
40053 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
40054 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
40055 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
40056 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
40057 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
40058 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
40059 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
40060 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
40061 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
40062 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
40063 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
40064 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
40065 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
40066 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
40067 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
40068 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
40069 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
40070 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
40071 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
40072 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
40073 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
40074 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
40075 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
40076 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
40077 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
40078 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
40079 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
40080 | //BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY |
40081 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
40082 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
40083 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
40084 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
40085 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
40086 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
40087 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
40088 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
40089 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
40090 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
40091 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
40092 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
40093 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
40094 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
40095 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
40096 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
40097 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
40098 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
40099 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
40100 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
40101 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
40102 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
40103 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
40104 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
40105 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
40106 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
40107 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
40108 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
40109 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
40110 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
40111 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
40112 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
40113 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
40114 | #define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
40115 | //BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS |
40116 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
40117 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
40118 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
40119 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
40120 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
40121 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
40122 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
40123 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
40124 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
40125 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
40126 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
40127 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
40128 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
40129 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
40130 | //BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK |
40131 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
40132 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
40133 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
40134 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
40135 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
40136 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
40137 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
40138 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
40139 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
40140 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
40141 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
40142 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
40143 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
40144 | #define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
40145 | //BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL |
40146 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
40147 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
40148 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
40149 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
40150 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
40151 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
40152 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
40153 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
40154 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
40155 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
40156 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
40157 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
40158 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
40159 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
40160 | //BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0 |
40161 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
40162 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
40163 | //BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1 |
40164 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
40165 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
40166 | //BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2 |
40167 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
40168 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
40169 | //BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3 |
40170 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
40171 | #define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
40172 | //BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0 |
40173 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
40174 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
40175 | //BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1 |
40176 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
40177 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
40178 | //BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2 |
40179 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
40180 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
40181 | //BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3 |
40182 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
40183 | #define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
40184 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST |
40185 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40186 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40187 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40188 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40189 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40190 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40191 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP |
40192 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40193 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
40194 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL |
40195 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
40196 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
40197 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
40198 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
40199 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
40200 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
40201 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
40202 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
40203 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP |
40204 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40205 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
40206 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL |
40207 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
40208 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
40209 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
40210 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
40211 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
40212 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
40213 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
40214 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
40215 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP |
40216 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40217 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
40218 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL |
40219 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
40220 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
40221 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
40222 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
40223 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
40224 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
40225 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
40226 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
40227 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP |
40228 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40229 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
40230 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL |
40231 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
40232 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
40233 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
40234 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
40235 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
40236 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
40237 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
40238 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
40239 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP |
40240 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40241 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
40242 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL |
40243 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
40244 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
40245 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
40246 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
40247 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
40248 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
40249 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
40250 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
40251 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP |
40252 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40253 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
40254 | //BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL |
40255 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
40256 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
40257 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
40258 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
40259 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
40260 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
40261 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
40262 | #define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
40263 | //BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
40264 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40265 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40266 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40267 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40268 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40269 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40270 | //BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT |
40271 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
40272 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
40273 | //BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA |
40274 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
40275 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
40276 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
40277 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
40278 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
40279 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
40280 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
40281 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
40282 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
40283 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
40284 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
40285 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
40286 | //BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP |
40287 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
40288 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
40289 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST |
40290 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40291 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40292 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40293 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40294 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40295 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40296 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP |
40297 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
40298 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
40299 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
40300 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
40301 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
40302 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
40303 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
40304 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
40305 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
40306 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
40307 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR |
40308 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
40309 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
40310 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS |
40311 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
40312 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
40313 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
40314 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
40315 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL |
40316 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
40317 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
40318 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
40319 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40320 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40321 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
40322 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40323 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40324 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
40325 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40326 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40327 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
40328 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40329 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40330 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
40331 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40332 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40333 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
40334 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40335 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40336 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
40337 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40338 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40339 | //BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
40340 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
40341 | #define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
40342 | //BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST |
40343 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40344 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40345 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40346 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40347 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40348 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40349 | //BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP |
40350 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
40351 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
40352 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
40353 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
40354 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
40355 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
40356 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
40357 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
40358 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
40359 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
40360 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
40361 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
40362 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
40363 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
40364 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
40365 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
40366 | //BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL |
40367 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
40368 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
40369 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
40370 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
40371 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
40372 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
40373 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
40374 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
40375 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
40376 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
40377 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
40378 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
40379 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
40380 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
40381 | //BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST |
40382 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40383 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40384 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40385 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40386 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40387 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40388 | //BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP |
40389 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
40390 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
40391 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
40392 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
40393 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
40394 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
40395 | //BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL |
40396 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
40397 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
40398 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
40399 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
40400 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
40401 | #define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
40402 | //BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST |
40403 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40404 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40405 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40406 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40407 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40408 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40409 | //BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP |
40410 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
40411 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
40412 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
40413 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
40414 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
40415 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
40416 | //BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL |
40417 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
40418 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
40419 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
40420 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
40421 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
40422 | #define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
40423 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST |
40424 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40425 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40426 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40427 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40428 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40429 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40430 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CAP |
40431 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
40432 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 |
40433 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
40434 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L |
40435 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL |
40436 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
40437 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
40438 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
40439 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 |
40440 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
40441 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
40442 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
40443 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L |
40444 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_STATUS |
40445 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_INITIAL_VFS |
40446 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
40447 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
40448 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_TOTAL_VFS |
40449 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
40450 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
40451 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_NUM_VFS |
40452 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
40453 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
40454 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK |
40455 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
40456 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL |
40457 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET |
40458 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
40459 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
40460 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_STRIDE |
40461 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
40462 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
40463 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID |
40464 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
40465 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
40466 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
40467 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
40468 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
40469 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
40470 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
40471 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
40472 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 |
40473 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
40474 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
40475 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 |
40476 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
40477 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
40478 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 |
40479 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
40480 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
40481 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 |
40482 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
40483 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
40484 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 |
40485 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
40486 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
40487 | //BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 |
40488 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
40489 | #define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
40490 | //BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST |
40491 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40492 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40493 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40494 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40495 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40496 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40497 | //BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP |
40498 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40499 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
40500 | //BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL |
40501 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
40502 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
40503 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
40504 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
40505 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
40506 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
40507 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
40508 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
40509 | //BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP |
40510 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40511 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
40512 | //BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL |
40513 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
40514 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
40515 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
40516 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
40517 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
40518 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
40519 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
40520 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
40521 | //BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP |
40522 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40523 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
40524 | //BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL |
40525 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
40526 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
40527 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
40528 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
40529 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
40530 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
40531 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
40532 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
40533 | //BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP |
40534 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40535 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
40536 | //BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL |
40537 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
40538 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
40539 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
40540 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
40541 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
40542 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
40543 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
40544 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
40545 | //BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP |
40546 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40547 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
40548 | //BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL |
40549 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
40550 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
40551 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
40552 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
40553 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
40554 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
40555 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
40556 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
40557 | //BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP |
40558 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
40559 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
40560 | //BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL |
40561 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
40562 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
40563 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
40564 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
40565 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
40566 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
40567 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
40568 | #define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
40569 | //BIF_CFG_DEV1_EPF1_0_PCIE_RTR_ENH_CAP_LIST |
40570 | #define BIF_CFG_DEV1_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
40571 | #define BIF_CFG_DEV1_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
40572 | #define BIF_CFG_DEV1_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
40573 | #define BIF_CFG_DEV1_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
40574 | #define BIF_CFG_DEV1_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
40575 | #define BIF_CFG_DEV1_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
40576 | //BIF_CFG_DEV1_EPF1_0_RTR_DATA1 |
40577 | #define BIF_CFG_DEV1_EPF1_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
40578 | #define BIF_CFG_DEV1_EPF1_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
40579 | #define BIF_CFG_DEV1_EPF1_0_RTR_DATA1__VALID__SHIFT 0x1f |
40580 | #define BIF_CFG_DEV1_EPF1_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
40581 | #define BIF_CFG_DEV1_EPF1_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
40582 | #define BIF_CFG_DEV1_EPF1_0_RTR_DATA1__VALID_MASK 0x80000000L |
40583 | //BIF_CFG_DEV1_EPF1_0_RTR_DATA2 |
40584 | #define BIF_CFG_DEV1_EPF1_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
40585 | #define BIF_CFG_DEV1_EPF1_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
40586 | #define BIF_CFG_DEV1_EPF1_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
40587 | #define BIF_CFG_DEV1_EPF1_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
40588 | |
40589 | |
40590 | // addressBlock: nbio_nbif0_bif_cfg_dev2_rc_bifcfgdecp |
40591 | //BIF_CFG_DEV2_RC0_VENDOR_ID |
40592 | #define BIF_CFG_DEV2_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
40593 | #define BIF_CFG_DEV2_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
40594 | //BIF_CFG_DEV2_RC0_DEVICE_ID |
40595 | #define BIF_CFG_DEV2_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
40596 | #define BIF_CFG_DEV2_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
40597 | //BIF_CFG_DEV2_RC0_COMMAND |
40598 | #define BIF_CFG_DEV2_RC0_COMMAND__IOEN_DN__SHIFT 0x0 |
40599 | #define BIF_CFG_DEV2_RC0_COMMAND__MEMEN_DN__SHIFT 0x1 |
40600 | #define BIF_CFG_DEV2_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
40601 | #define BIF_CFG_DEV2_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
40602 | #define BIF_CFG_DEV2_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
40603 | #define BIF_CFG_DEV2_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
40604 | #define BIF_CFG_DEV2_RC0_COMMAND__AD_STEPPING__SHIFT 0x7 |
40605 | #define BIF_CFG_DEV2_RC0_COMMAND__SERR_EN__SHIFT 0x8 |
40606 | #define BIF_CFG_DEV2_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
40607 | #define BIF_CFG_DEV2_RC0_COMMAND__INT_DIS__SHIFT 0xa |
40608 | #define BIF_CFG_DEV2_RC0_COMMAND__IOEN_DN_MASK 0x0001L |
40609 | #define BIF_CFG_DEV2_RC0_COMMAND__MEMEN_DN_MASK 0x0002L |
40610 | #define BIF_CFG_DEV2_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
40611 | #define BIF_CFG_DEV2_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
40612 | #define BIF_CFG_DEV2_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
40613 | #define BIF_CFG_DEV2_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
40614 | #define BIF_CFG_DEV2_RC0_COMMAND__AD_STEPPING_MASK 0x0080L |
40615 | #define BIF_CFG_DEV2_RC0_COMMAND__SERR_EN_MASK 0x0100L |
40616 | #define BIF_CFG_DEV2_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
40617 | #define BIF_CFG_DEV2_RC0_COMMAND__INT_DIS_MASK 0x0400L |
40618 | //BIF_CFG_DEV2_RC0_STATUS |
40619 | #define BIF_CFG_DEV2_RC0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
40620 | #define BIF_CFG_DEV2_RC0_STATUS__INT_STATUS__SHIFT 0x3 |
40621 | #define BIF_CFG_DEV2_RC0_STATUS__CAP_LIST__SHIFT 0x4 |
40622 | #define BIF_CFG_DEV2_RC0_STATUS__PCI_66_CAP__SHIFT 0x5 |
40623 | #define BIF_CFG_DEV2_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
40624 | #define BIF_CFG_DEV2_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
40625 | #define BIF_CFG_DEV2_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
40626 | #define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
40627 | #define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
40628 | #define BIF_CFG_DEV2_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
40629 | #define BIF_CFG_DEV2_RC0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
40630 | #define BIF_CFG_DEV2_RC0_STATUS__INT_STATUS_MASK 0x0008L |
40631 | #define BIF_CFG_DEV2_RC0_STATUS__CAP_LIST_MASK 0x0010L |
40632 | #define BIF_CFG_DEV2_RC0_STATUS__PCI_66_CAP_MASK 0x0020L |
40633 | #define BIF_CFG_DEV2_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
40634 | #define BIF_CFG_DEV2_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
40635 | #define BIF_CFG_DEV2_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
40636 | #define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
40637 | #define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
40638 | #define BIF_CFG_DEV2_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
40639 | //BIF_CFG_DEV2_RC0_REVISION_ID |
40640 | #define BIF_CFG_DEV2_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
40641 | #define BIF_CFG_DEV2_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
40642 | #define BIF_CFG_DEV2_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
40643 | #define BIF_CFG_DEV2_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
40644 | //BIF_CFG_DEV2_RC0_PROG_INTERFACE |
40645 | #define BIF_CFG_DEV2_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
40646 | #define BIF_CFG_DEV2_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
40647 | //BIF_CFG_DEV2_RC0_SUB_CLASS |
40648 | #define BIF_CFG_DEV2_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
40649 | #define BIF_CFG_DEV2_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
40650 | //BIF_CFG_DEV2_RC0_BASE_CLASS |
40651 | #define BIF_CFG_DEV2_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
40652 | #define BIF_CFG_DEV2_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
40653 | //BIF_CFG_DEV2_RC0_CACHE_LINE |
40654 | #define BIF_CFG_DEV2_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
40655 | #define BIF_CFG_DEV2_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
40656 | //BIF_CFG_DEV2_RC0_LATENCY |
40657 | #define BIF_CFG_DEV2_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
40658 | #define BIF_CFG_DEV2_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
40659 | //BIF_CFG_DEV2_RC0_HEADER |
40660 | #define 0x0 |
40661 | #define 0x7 |
40662 | #define 0x7FL |
40663 | #define 0x80L |
40664 | //BIF_CFG_DEV2_RC0_BIST |
40665 | #define BIF_CFG_DEV2_RC0_BIST__BIST_COMP__SHIFT 0x0 |
40666 | #define BIF_CFG_DEV2_RC0_BIST__BIST_STRT__SHIFT 0x6 |
40667 | #define BIF_CFG_DEV2_RC0_BIST__BIST_CAP__SHIFT 0x7 |
40668 | #define BIF_CFG_DEV2_RC0_BIST__BIST_COMP_MASK 0x0FL |
40669 | #define BIF_CFG_DEV2_RC0_BIST__BIST_STRT_MASK 0x40L |
40670 | #define BIF_CFG_DEV2_RC0_BIST__BIST_CAP_MASK 0x80L |
40671 | //BIF_CFG_DEV2_RC0_BASE_ADDR_1 |
40672 | #define BIF_CFG_DEV2_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
40673 | #define BIF_CFG_DEV2_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
40674 | //BIF_CFG_DEV2_RC0_BASE_ADDR_2 |
40675 | #define BIF_CFG_DEV2_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
40676 | #define BIF_CFG_DEV2_RC0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
40677 | //BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY |
40678 | #define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
40679 | #define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
40680 | #define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
40681 | #define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
40682 | #define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
40683 | #define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
40684 | #define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
40685 | #define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
40686 | //BIF_CFG_DEV2_RC0_IO_BASE_LIMIT |
40687 | #define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
40688 | #define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
40689 | #define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
40690 | #define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
40691 | #define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
40692 | #define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
40693 | #define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
40694 | #define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
40695 | //BIF_CFG_DEV2_RC0_SECONDARY_STATUS |
40696 | #define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 |
40697 | #define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
40698 | #define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
40699 | #define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
40700 | #define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
40701 | #define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
40702 | #define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
40703 | #define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L |
40704 | #define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
40705 | #define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
40706 | #define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
40707 | #define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
40708 | #define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
40709 | #define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
40710 | //BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT |
40711 | #define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
40712 | #define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
40713 | #define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
40714 | #define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
40715 | #define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
40716 | #define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
40717 | #define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
40718 | #define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
40719 | //BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT |
40720 | #define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
40721 | #define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
40722 | #define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
40723 | #define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
40724 | #define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
40725 | #define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
40726 | #define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
40727 | #define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
40728 | //BIF_CFG_DEV2_RC0_PREF_BASE_UPPER |
40729 | #define BIF_CFG_DEV2_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
40730 | #define BIF_CFG_DEV2_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
40731 | //BIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER |
40732 | #define BIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
40733 | #define BIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
40734 | //BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI |
40735 | #define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
40736 | #define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
40737 | #define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
40738 | #define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
40739 | //BIF_CFG_DEV2_RC0_CAP_PTR |
40740 | #define BIF_CFG_DEV2_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
40741 | #define BIF_CFG_DEV2_RC0_CAP_PTR__CAP_PTR_MASK 0xFFL |
40742 | //BIF_CFG_DEV2_RC0_ROM_BASE_ADDR |
40743 | #define BIF_CFG_DEV2_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
40744 | #define BIF_CFG_DEV2_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
40745 | //BIF_CFG_DEV2_RC0_INTERRUPT_LINE |
40746 | #define BIF_CFG_DEV2_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
40747 | #define BIF_CFG_DEV2_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
40748 | //BIF_CFG_DEV2_RC0_INTERRUPT_PIN |
40749 | #define BIF_CFG_DEV2_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
40750 | #define BIF_CFG_DEV2_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
40751 | //BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL |
40752 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
40753 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
40754 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
40755 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
40756 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
40757 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
40758 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
40759 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
40760 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 |
40761 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 |
40762 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa |
40763 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb |
40764 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
40765 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
40766 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
40767 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
40768 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
40769 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
40770 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
40771 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
40772 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L |
40773 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L |
40774 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L |
40775 | #define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L |
40776 | //BIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL |
40777 | #define BIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
40778 | #define BIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
40779 | //BIF_CFG_DEV2_RC0_PMI_CAP_LIST |
40780 | #define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
40781 | #define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
40782 | #define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
40783 | #define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
40784 | //BIF_CFG_DEV2_RC0_PMI_CAP |
40785 | #define BIF_CFG_DEV2_RC0_PMI_CAP__VERSION__SHIFT 0x0 |
40786 | #define BIF_CFG_DEV2_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
40787 | #define BIF_CFG_DEV2_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
40788 | #define BIF_CFG_DEV2_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
40789 | #define BIF_CFG_DEV2_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
40790 | #define BIF_CFG_DEV2_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
40791 | #define BIF_CFG_DEV2_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
40792 | #define BIF_CFG_DEV2_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
40793 | #define BIF_CFG_DEV2_RC0_PMI_CAP__VERSION_MASK 0x0007L |
40794 | #define BIF_CFG_DEV2_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
40795 | #define BIF_CFG_DEV2_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
40796 | #define BIF_CFG_DEV2_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
40797 | #define BIF_CFG_DEV2_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
40798 | #define BIF_CFG_DEV2_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
40799 | #define BIF_CFG_DEV2_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
40800 | #define BIF_CFG_DEV2_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
40801 | //BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL |
40802 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
40803 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
40804 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
40805 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
40806 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
40807 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
40808 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
40809 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
40810 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
40811 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
40812 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
40813 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
40814 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
40815 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
40816 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
40817 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
40818 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
40819 | #define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
40820 | //BIF_CFG_DEV2_RC0_PCIE_CAP_LIST |
40821 | #define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
40822 | #define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
40823 | #define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
40824 | #define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
40825 | //BIF_CFG_DEV2_RC0_PCIE_CAP |
40826 | #define BIF_CFG_DEV2_RC0_PCIE_CAP__VERSION__SHIFT 0x0 |
40827 | #define BIF_CFG_DEV2_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
40828 | #define BIF_CFG_DEV2_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
40829 | #define BIF_CFG_DEV2_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
40830 | #define BIF_CFG_DEV2_RC0_PCIE_CAP__VERSION_MASK 0x000FL |
40831 | #define BIF_CFG_DEV2_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
40832 | #define BIF_CFG_DEV2_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
40833 | #define BIF_CFG_DEV2_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
40834 | //BIF_CFG_DEV2_RC0_DEVICE_CAP |
40835 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
40836 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
40837 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
40838 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
40839 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
40840 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
40841 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
40842 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
40843 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
40844 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
40845 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
40846 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
40847 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
40848 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
40849 | //BIF_CFG_DEV2_RC0_DEVICE_CNTL |
40850 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
40851 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
40852 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
40853 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
40854 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
40855 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
40856 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
40857 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
40858 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
40859 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
40860 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
40861 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
40862 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
40863 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
40864 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
40865 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
40866 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
40867 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
40868 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
40869 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
40870 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
40871 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
40872 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
40873 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
40874 | //BIF_CFG_DEV2_RC0_DEVICE_STATUS |
40875 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
40876 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
40877 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
40878 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
40879 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
40880 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
40881 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
40882 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
40883 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
40884 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
40885 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
40886 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
40887 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
40888 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
40889 | //BIF_CFG_DEV2_RC0_LINK_CAP |
40890 | #define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
40891 | #define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
40892 | #define BIF_CFG_DEV2_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
40893 | #define BIF_CFG_DEV2_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
40894 | #define BIF_CFG_DEV2_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
40895 | #define BIF_CFG_DEV2_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
40896 | #define BIF_CFG_DEV2_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
40897 | #define BIF_CFG_DEV2_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
40898 | #define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
40899 | #define BIF_CFG_DEV2_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
40900 | #define BIF_CFG_DEV2_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
40901 | #define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
40902 | #define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
40903 | #define BIF_CFG_DEV2_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
40904 | #define BIF_CFG_DEV2_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
40905 | #define BIF_CFG_DEV2_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
40906 | #define BIF_CFG_DEV2_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
40907 | #define BIF_CFG_DEV2_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
40908 | #define BIF_CFG_DEV2_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
40909 | #define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
40910 | #define BIF_CFG_DEV2_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
40911 | #define BIF_CFG_DEV2_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
40912 | //BIF_CFG_DEV2_RC0_LINK_CNTL |
40913 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
40914 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
40915 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
40916 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
40917 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
40918 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
40919 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
40920 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
40921 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
40922 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
40923 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
40924 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
40925 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
40926 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
40927 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
40928 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
40929 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
40930 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
40931 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
40932 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
40933 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
40934 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
40935 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
40936 | #define BIF_CFG_DEV2_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
40937 | //BIF_CFG_DEV2_RC0_LINK_STATUS |
40938 | #define BIF_CFG_DEV2_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
40939 | #define BIF_CFG_DEV2_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
40940 | #define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
40941 | #define BIF_CFG_DEV2_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
40942 | #define BIF_CFG_DEV2_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
40943 | #define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
40944 | #define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
40945 | #define BIF_CFG_DEV2_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
40946 | #define BIF_CFG_DEV2_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
40947 | #define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
40948 | #define BIF_CFG_DEV2_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
40949 | #define BIF_CFG_DEV2_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
40950 | #define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
40951 | #define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
40952 | //BIF_CFG_DEV2_RC0_SLOT_CAP |
40953 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
40954 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
40955 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
40956 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
40957 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
40958 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
40959 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
40960 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
40961 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
40962 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
40963 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
40964 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
40965 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
40966 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
40967 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
40968 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
40969 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
40970 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
40971 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
40972 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
40973 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
40974 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
40975 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
40976 | #define BIF_CFG_DEV2_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
40977 | //BIF_CFG_DEV2_RC0_SLOT_CNTL |
40978 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
40979 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
40980 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
40981 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
40982 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
40983 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
40984 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
40985 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
40986 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
40987 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
40988 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
40989 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
40990 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
40991 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
40992 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
40993 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
40994 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
40995 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
40996 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
40997 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
40998 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
40999 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
41000 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
41001 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
41002 | //BIF_CFG_DEV2_RC0_SLOT_STATUS |
41003 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
41004 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
41005 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
41006 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
41007 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
41008 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
41009 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
41010 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
41011 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
41012 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
41013 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
41014 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
41015 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
41016 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
41017 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
41018 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
41019 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
41020 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
41021 | //BIF_CFG_DEV2_RC0_ROOT_CNTL |
41022 | #define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 |
41023 | #define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 |
41024 | #define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 |
41025 | #define BIF_CFG_DEV2_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 |
41026 | #define BIF_CFG_DEV2_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 |
41027 | #define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L |
41028 | #define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L |
41029 | #define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L |
41030 | #define BIF_CFG_DEV2_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L |
41031 | #define BIF_CFG_DEV2_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L |
41032 | //BIF_CFG_DEV2_RC0_ROOT_CAP |
41033 | #define BIF_CFG_DEV2_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 |
41034 | #define BIF_CFG_DEV2_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L |
41035 | //BIF_CFG_DEV2_RC0_ROOT_STATUS |
41036 | #define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 |
41037 | #define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 |
41038 | #define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 |
41039 | #define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL |
41040 | #define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L |
41041 | #define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L |
41042 | //BIF_CFG_DEV2_RC0_DEVICE_CAP2 |
41043 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
41044 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
41045 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
41046 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
41047 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
41048 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
41049 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
41050 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
41051 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
41052 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
41053 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
41054 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
41055 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
41056 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
41057 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
41058 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
41059 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
41060 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
41061 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
41062 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
41063 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
41064 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
41065 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
41066 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
41067 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
41068 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
41069 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
41070 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
41071 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
41072 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
41073 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
41074 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
41075 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
41076 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
41077 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
41078 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
41079 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
41080 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
41081 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
41082 | #define BIF_CFG_DEV2_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
41083 | //BIF_CFG_DEV2_RC0_DEVICE_CNTL2 |
41084 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
41085 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
41086 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
41087 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
41088 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
41089 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
41090 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
41091 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
41092 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
41093 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
41094 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
41095 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
41096 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
41097 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
41098 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
41099 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
41100 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
41101 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
41102 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
41103 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
41104 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
41105 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
41106 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
41107 | #define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
41108 | //BIF_CFG_DEV2_RC0_DEVICE_STATUS2 |
41109 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
41110 | #define BIF_CFG_DEV2_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
41111 | //BIF_CFG_DEV2_RC0_LINK_CAP2 |
41112 | #define BIF_CFG_DEV2_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
41113 | #define BIF_CFG_DEV2_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
41114 | #define BIF_CFG_DEV2_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
41115 | #define BIF_CFG_DEV2_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
41116 | #define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
41117 | #define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
41118 | #define BIF_CFG_DEV2_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
41119 | #define BIF_CFG_DEV2_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
41120 | #define BIF_CFG_DEV2_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
41121 | #define BIF_CFG_DEV2_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
41122 | #define BIF_CFG_DEV2_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
41123 | #define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
41124 | #define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
41125 | #define BIF_CFG_DEV2_RC0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
41126 | //BIF_CFG_DEV2_RC0_LINK_CNTL2 |
41127 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
41128 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
41129 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
41130 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
41131 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
41132 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
41133 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
41134 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
41135 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
41136 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
41137 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
41138 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
41139 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
41140 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
41141 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
41142 | #define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
41143 | //BIF_CFG_DEV2_RC0_LINK_STATUS2 |
41144 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
41145 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
41146 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
41147 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
41148 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
41149 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
41150 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
41151 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
41152 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
41153 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
41154 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
41155 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
41156 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
41157 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
41158 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
41159 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
41160 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
41161 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
41162 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
41163 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
41164 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
41165 | #define BIF_CFG_DEV2_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
41166 | //BIF_CFG_DEV2_RC0_SLOT_CAP2 |
41167 | #define BIF_CFG_DEV2_RC0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
41168 | #define BIF_CFG_DEV2_RC0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
41169 | //BIF_CFG_DEV2_RC0_SLOT_CNTL2 |
41170 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
41171 | #define BIF_CFG_DEV2_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
41172 | //BIF_CFG_DEV2_RC0_SLOT_STATUS2 |
41173 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
41174 | #define BIF_CFG_DEV2_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
41175 | //BIF_CFG_DEV2_RC0_MSI_CAP_LIST |
41176 | #define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
41177 | #define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
41178 | #define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
41179 | #define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
41180 | //BIF_CFG_DEV2_RC0_MSI_MSG_CNTL |
41181 | #define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
41182 | #define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
41183 | #define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
41184 | #define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
41185 | #define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
41186 | #define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
41187 | #define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
41188 | #define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
41189 | #define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
41190 | #define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
41191 | #define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
41192 | #define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
41193 | #define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
41194 | #define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
41195 | //BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO |
41196 | #define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
41197 | #define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
41198 | //BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI |
41199 | #define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
41200 | #define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
41201 | //BIF_CFG_DEV2_RC0_MSI_MSG_DATA |
41202 | #define BIF_CFG_DEV2_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
41203 | #define BIF_CFG_DEV2_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
41204 | //BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA |
41205 | #define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
41206 | #define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
41207 | //BIF_CFG_DEV2_RC0_MSI_MSG_DATA_64 |
41208 | #define BIF_CFG_DEV2_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
41209 | #define BIF_CFG_DEV2_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
41210 | //BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64 |
41211 | #define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
41212 | #define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
41213 | //BIF_CFG_DEV2_RC0_SSID_CAP_LIST |
41214 | #define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
41215 | #define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
41216 | #define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
41217 | #define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
41218 | //BIF_CFG_DEV2_RC0_SSID_CAP |
41219 | #define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
41220 | #define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
41221 | #define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
41222 | #define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
41223 | //BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST |
41224 | #define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
41225 | #define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
41226 | #define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
41227 | #define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
41228 | //BIF_CFG_DEV2_RC0_MSI_MAP_CAP |
41229 | #define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__EN__SHIFT 0x0 |
41230 | #define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
41231 | #define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
41232 | #define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__EN_MASK 0x0001L |
41233 | #define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__FIXD_MASK 0x0002L |
41234 | #define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
41235 | //BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
41236 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41237 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41238 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41239 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41240 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41241 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41242 | //BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR |
41243 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
41244 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
41245 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
41246 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
41247 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
41248 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
41249 | //BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1 |
41250 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
41251 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
41252 | //BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2 |
41253 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
41254 | #define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
41255 | //BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST |
41256 | #define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41257 | #define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41258 | #define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41259 | #define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41260 | #define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41261 | #define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41262 | //BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1 |
41263 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
41264 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
41265 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
41266 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
41267 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
41268 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
41269 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
41270 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
41271 | //BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2 |
41272 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
41273 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
41274 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
41275 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
41276 | //BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL |
41277 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
41278 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
41279 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
41280 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
41281 | //BIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS |
41282 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
41283 | #define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
41284 | //BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP |
41285 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
41286 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
41287 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
41288 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
41289 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
41290 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
41291 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
41292 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
41293 | //BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL |
41294 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
41295 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
41296 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
41297 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
41298 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
41299 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
41300 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
41301 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
41302 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
41303 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
41304 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
41305 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
41306 | //BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS |
41307 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
41308 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
41309 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
41310 | #define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
41311 | //BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP |
41312 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
41313 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
41314 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
41315 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
41316 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
41317 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
41318 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
41319 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
41320 | //BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL |
41321 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
41322 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
41323 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
41324 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
41325 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
41326 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
41327 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
41328 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
41329 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
41330 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
41331 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
41332 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
41333 | //BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS |
41334 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
41335 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
41336 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
41337 | #define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
41338 | //BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
41339 | #define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41340 | #define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41341 | #define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41342 | #define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41343 | #define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41344 | #define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41345 | //BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1 |
41346 | #define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
41347 | #define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
41348 | //BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2 |
41349 | #define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
41350 | #define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
41351 | //BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
41352 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41353 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41354 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41355 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41356 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41357 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41358 | //BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS |
41359 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
41360 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
41361 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
41362 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
41363 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
41364 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
41365 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
41366 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
41367 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
41368 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
41369 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
41370 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
41371 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
41372 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
41373 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
41374 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
41375 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
41376 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
41377 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
41378 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
41379 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
41380 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
41381 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
41382 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
41383 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
41384 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
41385 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
41386 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
41387 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
41388 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
41389 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
41390 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
41391 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
41392 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
41393 | //BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK |
41394 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
41395 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
41396 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
41397 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
41398 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
41399 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
41400 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
41401 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
41402 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
41403 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
41404 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
41405 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
41406 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
41407 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
41408 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
41409 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
41410 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
41411 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
41412 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
41413 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
41414 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
41415 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
41416 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
41417 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
41418 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
41419 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
41420 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
41421 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
41422 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
41423 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
41424 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
41425 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
41426 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
41427 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
41428 | //BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY |
41429 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
41430 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
41431 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
41432 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
41433 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
41434 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
41435 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
41436 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
41437 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
41438 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
41439 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
41440 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
41441 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
41442 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
41443 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
41444 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
41445 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
41446 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
41447 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
41448 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
41449 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
41450 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
41451 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
41452 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
41453 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
41454 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
41455 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
41456 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
41457 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
41458 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
41459 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
41460 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
41461 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
41462 | #define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
41463 | //BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS |
41464 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
41465 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
41466 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
41467 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
41468 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
41469 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
41470 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
41471 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
41472 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
41473 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
41474 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
41475 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
41476 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
41477 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
41478 | //BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK |
41479 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
41480 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
41481 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
41482 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
41483 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
41484 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
41485 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
41486 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
41487 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
41488 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
41489 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
41490 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
41491 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
41492 | #define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
41493 | //BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL |
41494 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
41495 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
41496 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
41497 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
41498 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
41499 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
41500 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
41501 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
41502 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
41503 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
41504 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
41505 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
41506 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
41507 | #define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
41508 | //BIF_CFG_DEV2_RC0_PCIE_HDR_LOG0 |
41509 | #define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
41510 | #define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
41511 | //BIF_CFG_DEV2_RC0_PCIE_HDR_LOG1 |
41512 | #define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
41513 | #define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
41514 | //BIF_CFG_DEV2_RC0_PCIE_HDR_LOG2 |
41515 | #define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
41516 | #define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
41517 | //BIF_CFG_DEV2_RC0_PCIE_HDR_LOG3 |
41518 | #define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
41519 | #define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
41520 | //BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD |
41521 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 |
41522 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 |
41523 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 |
41524 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L |
41525 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L |
41526 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L |
41527 | //BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS |
41528 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 |
41529 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 |
41530 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 |
41531 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 |
41532 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 |
41533 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 |
41534 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 |
41535 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b |
41536 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L |
41537 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L |
41538 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L |
41539 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L |
41540 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L |
41541 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L |
41542 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L |
41543 | #define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L |
41544 | //BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID |
41545 | #define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 |
41546 | #define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 |
41547 | #define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL |
41548 | #define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L |
41549 | //BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0 |
41550 | #define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
41551 | #define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
41552 | //BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1 |
41553 | #define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
41554 | #define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
41555 | //BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2 |
41556 | #define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
41557 | #define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
41558 | //BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3 |
41559 | #define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
41560 | #define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
41561 | //BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST |
41562 | #define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41563 | #define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41564 | #define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41565 | #define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41566 | #define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41567 | #define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41568 | //BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3 |
41569 | #define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
41570 | #define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
41571 | #define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
41572 | #define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
41573 | #define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
41574 | #define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
41575 | //BIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS |
41576 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
41577 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
41578 | //BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL |
41579 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41580 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41581 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41582 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41583 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41584 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41585 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41586 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41587 | //BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL |
41588 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41589 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41590 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41591 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41592 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41593 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41594 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41595 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41596 | //BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL |
41597 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41598 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41599 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41600 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41601 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41602 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41603 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41604 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41605 | //BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL |
41606 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41607 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41608 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41609 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41610 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41611 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41612 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41613 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41614 | //BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL |
41615 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41616 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41617 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41618 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41619 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41620 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41621 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41622 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41623 | //BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL |
41624 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41625 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41626 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41627 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41628 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41629 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41630 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41631 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41632 | //BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL |
41633 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41634 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41635 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41636 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41637 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41638 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41639 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41640 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41641 | //BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL |
41642 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41643 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41644 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41645 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41646 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41647 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41648 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41649 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41650 | //BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL |
41651 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41652 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41653 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41654 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41655 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41656 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41657 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41658 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41659 | //BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL |
41660 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41661 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41662 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41663 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41664 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41665 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41666 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41667 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41668 | //BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL |
41669 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41670 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41671 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41672 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41673 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41674 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41675 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41676 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41677 | //BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL |
41678 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41679 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41680 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41681 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41682 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41683 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41684 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41685 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41686 | //BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL |
41687 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41688 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41689 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41690 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41691 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41692 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41693 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41694 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41695 | //BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL |
41696 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41697 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41698 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41699 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41700 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41701 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41702 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41703 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41704 | //BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL |
41705 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41706 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41707 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41708 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41709 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41710 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41711 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41712 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41713 | //BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL |
41714 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
41715 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
41716 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
41717 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
41718 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
41719 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
41720 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
41721 | #define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
41722 | //BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST |
41723 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41724 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41725 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41726 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41727 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41728 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41729 | //BIF_CFG_DEV2_RC0_PCIE_ACS_CAP |
41730 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
41731 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
41732 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
41733 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
41734 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
41735 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
41736 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
41737 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
41738 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
41739 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
41740 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
41741 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
41742 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
41743 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
41744 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
41745 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
41746 | //BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL |
41747 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
41748 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
41749 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
41750 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
41751 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
41752 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
41753 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
41754 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
41755 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
41756 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
41757 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
41758 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
41759 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
41760 | #define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
41761 | //BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST |
41762 | #define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41763 | #define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41764 | #define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41765 | #define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41766 | #define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41767 | #define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41768 | //BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP |
41769 | #define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
41770 | #define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
41771 | #define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
41772 | #define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
41773 | //BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS |
41774 | #define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
41775 | #define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
41776 | #define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
41777 | #define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
41778 | //BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST |
41779 | #define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41780 | #define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41781 | #define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41782 | #define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41783 | #define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41784 | #define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41785 | //BIF_CFG_DEV2_RC0_LINK_CAP_16GT |
41786 | #define BIF_CFG_DEV2_RC0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
41787 | #define BIF_CFG_DEV2_RC0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
41788 | //BIF_CFG_DEV2_RC0_LINK_CNTL_16GT |
41789 | #define BIF_CFG_DEV2_RC0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
41790 | #define BIF_CFG_DEV2_RC0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
41791 | //BIF_CFG_DEV2_RC0_LINK_STATUS_16GT |
41792 | #define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
41793 | #define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
41794 | #define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
41795 | #define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
41796 | #define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
41797 | #define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
41798 | #define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
41799 | #define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
41800 | #define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
41801 | #define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
41802 | //BIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT |
41803 | #define BIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
41804 | #define BIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
41805 | //BIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT |
41806 | #define BIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
41807 | #define BIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
41808 | //BIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT |
41809 | #define BIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
41810 | #define BIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
41811 | //BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT |
41812 | #define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41813 | #define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
41814 | #define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
41815 | #define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
41816 | //BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT |
41817 | #define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41818 | #define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
41819 | #define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
41820 | #define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
41821 | //BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT |
41822 | #define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41823 | #define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
41824 | #define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
41825 | #define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
41826 | //BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT |
41827 | #define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41828 | #define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
41829 | #define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
41830 | #define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
41831 | //BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT |
41832 | #define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41833 | #define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
41834 | #define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
41835 | #define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
41836 | //BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT |
41837 | #define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41838 | #define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
41839 | #define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
41840 | #define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
41841 | //BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT |
41842 | #define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41843 | #define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
41844 | #define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
41845 | #define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
41846 | //BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT |
41847 | #define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41848 | #define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
41849 | #define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
41850 | #define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
41851 | //BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT |
41852 | #define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41853 | #define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
41854 | #define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
41855 | #define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
41856 | //BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT |
41857 | #define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41858 | #define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
41859 | #define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
41860 | #define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
41861 | //BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT |
41862 | #define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41863 | #define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
41864 | #define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
41865 | #define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
41866 | //BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT |
41867 | #define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41868 | #define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
41869 | #define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
41870 | #define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
41871 | //BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT |
41872 | #define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41873 | #define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
41874 | #define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
41875 | #define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
41876 | //BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT |
41877 | #define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41878 | #define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
41879 | #define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
41880 | #define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
41881 | //BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT |
41882 | #define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41883 | #define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
41884 | #define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
41885 | #define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
41886 | //BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT |
41887 | #define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
41888 | #define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
41889 | #define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
41890 | #define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
41891 | //BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST |
41892 | #define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
41893 | #define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
41894 | #define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
41895 | #define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
41896 | #define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
41897 | #define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
41898 | //BIF_CFG_DEV2_RC0_MARGINING_PORT_CAP |
41899 | #define BIF_CFG_DEV2_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
41900 | #define BIF_CFG_DEV2_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
41901 | //BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS |
41902 | #define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
41903 | #define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
41904 | #define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
41905 | #define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
41906 | //BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL |
41907 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
41908 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
41909 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
41910 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
41911 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
41912 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
41913 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
41914 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
41915 | //BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS |
41916 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
41917 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
41918 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
41919 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
41920 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
41921 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
41922 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
41923 | #define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
41924 | //BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL |
41925 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
41926 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
41927 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
41928 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
41929 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
41930 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
41931 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
41932 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
41933 | //BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS |
41934 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
41935 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
41936 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
41937 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
41938 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
41939 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
41940 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
41941 | #define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
41942 | //BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL |
41943 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
41944 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
41945 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
41946 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
41947 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
41948 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
41949 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
41950 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
41951 | //BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS |
41952 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
41953 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
41954 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
41955 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
41956 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
41957 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
41958 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
41959 | #define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
41960 | //BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL |
41961 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
41962 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
41963 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
41964 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
41965 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
41966 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
41967 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
41968 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
41969 | //BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS |
41970 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
41971 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
41972 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
41973 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
41974 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
41975 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
41976 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
41977 | #define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
41978 | //BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL |
41979 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
41980 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
41981 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
41982 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
41983 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
41984 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
41985 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
41986 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
41987 | //BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS |
41988 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
41989 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
41990 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
41991 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
41992 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
41993 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
41994 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
41995 | #define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
41996 | //BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL |
41997 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
41998 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
41999 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
42000 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
42001 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
42002 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
42003 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
42004 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
42005 | //BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS |
42006 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
42007 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
42008 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
42009 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
42010 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
42011 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
42012 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
42013 | #define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
42014 | //BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL |
42015 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
42016 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
42017 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
42018 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
42019 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
42020 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
42021 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
42022 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
42023 | //BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS |
42024 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
42025 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
42026 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
42027 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
42028 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
42029 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
42030 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
42031 | #define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
42032 | //BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL |
42033 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
42034 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
42035 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
42036 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
42037 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
42038 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
42039 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
42040 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
42041 | //BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS |
42042 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
42043 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
42044 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
42045 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
42046 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
42047 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
42048 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
42049 | #define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
42050 | //BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL |
42051 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
42052 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
42053 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
42054 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
42055 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
42056 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
42057 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
42058 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
42059 | //BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS |
42060 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
42061 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
42062 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
42063 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
42064 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
42065 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
42066 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
42067 | #define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
42068 | //BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL |
42069 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
42070 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
42071 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
42072 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
42073 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
42074 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
42075 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
42076 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
42077 | //BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS |
42078 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
42079 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
42080 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
42081 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
42082 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
42083 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
42084 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
42085 | #define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
42086 | //BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL |
42087 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
42088 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
42089 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
42090 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
42091 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
42092 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
42093 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
42094 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
42095 | //BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS |
42096 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
42097 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
42098 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
42099 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
42100 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
42101 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
42102 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
42103 | #define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
42104 | //BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL |
42105 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
42106 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
42107 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
42108 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
42109 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
42110 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
42111 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
42112 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
42113 | //BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS |
42114 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
42115 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
42116 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
42117 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
42118 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
42119 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
42120 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
42121 | #define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
42122 | //BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL |
42123 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
42124 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
42125 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
42126 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
42127 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
42128 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
42129 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
42130 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
42131 | //BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS |
42132 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
42133 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
42134 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
42135 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
42136 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
42137 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
42138 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
42139 | #define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
42140 | //BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL |
42141 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
42142 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
42143 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
42144 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
42145 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
42146 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
42147 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
42148 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
42149 | //BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS |
42150 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
42151 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
42152 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
42153 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
42154 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
42155 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
42156 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
42157 | #define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
42158 | //BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL |
42159 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
42160 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
42161 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
42162 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
42163 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
42164 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
42165 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
42166 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
42167 | //BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS |
42168 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
42169 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
42170 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
42171 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
42172 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
42173 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
42174 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
42175 | #define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
42176 | //BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL |
42177 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
42178 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
42179 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
42180 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
42181 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
42182 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
42183 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
42184 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
42185 | //BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS |
42186 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
42187 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
42188 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
42189 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
42190 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
42191 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
42192 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
42193 | #define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
42194 | //BIF_CFG_DEV2_RC0_PCIE_RTR_ENH_CAP_LIST |
42195 | #define BIF_CFG_DEV2_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
42196 | #define BIF_CFG_DEV2_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
42197 | #define BIF_CFG_DEV2_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
42198 | #define BIF_CFG_DEV2_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
42199 | #define BIF_CFG_DEV2_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
42200 | #define BIF_CFG_DEV2_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
42201 | //BIF_CFG_DEV2_RC0_RTR_DATA1 |
42202 | #define BIF_CFG_DEV2_RC0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
42203 | #define BIF_CFG_DEV2_RC0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
42204 | #define BIF_CFG_DEV2_RC0_RTR_DATA1__VALID__SHIFT 0x1f |
42205 | #define BIF_CFG_DEV2_RC0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
42206 | #define BIF_CFG_DEV2_RC0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
42207 | #define BIF_CFG_DEV2_RC0_RTR_DATA1__VALID_MASK 0x80000000L |
42208 | //BIF_CFG_DEV2_RC0_RTR_DATA2 |
42209 | #define BIF_CFG_DEV2_RC0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
42210 | #define BIF_CFG_DEV2_RC0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
42211 | #define BIF_CFG_DEV2_RC0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
42212 | #define BIF_CFG_DEV2_RC0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
42213 | |
42214 | |
42215 | // addressBlock: nbio_nbif0_bif_cfg_dev2_epf0_bifcfgdecp |
42216 | //BIF_CFG_DEV2_EPF0_0_VENDOR_ID |
42217 | #define BIF_CFG_DEV2_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
42218 | #define BIF_CFG_DEV2_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
42219 | //BIF_CFG_DEV2_EPF0_0_DEVICE_ID |
42220 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
42221 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
42222 | //BIF_CFG_DEV2_EPF0_0_COMMAND |
42223 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
42224 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
42225 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
42226 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
42227 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
42228 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
42229 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
42230 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8 |
42231 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
42232 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa |
42233 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
42234 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
42235 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
42236 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
42237 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
42238 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
42239 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L |
42240 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L |
42241 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
42242 | #define BIF_CFG_DEV2_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L |
42243 | //BIF_CFG_DEV2_EPF0_0_STATUS |
42244 | #define BIF_CFG_DEV2_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
42245 | #define BIF_CFG_DEV2_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3 |
42246 | #define BIF_CFG_DEV2_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4 |
42247 | #define BIF_CFG_DEV2_EPF0_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
42248 | #define BIF_CFG_DEV2_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
42249 | #define BIF_CFG_DEV2_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
42250 | #define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
42251 | #define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
42252 | #define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
42253 | #define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
42254 | #define BIF_CFG_DEV2_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
42255 | #define BIF_CFG_DEV2_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L |
42256 | #define BIF_CFG_DEV2_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L |
42257 | #define BIF_CFG_DEV2_EPF0_0_STATUS__PCI_66_CAP_MASK 0x0020L |
42258 | #define BIF_CFG_DEV2_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
42259 | #define BIF_CFG_DEV2_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
42260 | #define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
42261 | #define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
42262 | #define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
42263 | #define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
42264 | //BIF_CFG_DEV2_EPF0_0_REVISION_ID |
42265 | #define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
42266 | #define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
42267 | #define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
42268 | #define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
42269 | //BIF_CFG_DEV2_EPF0_0_PROG_INTERFACE |
42270 | #define BIF_CFG_DEV2_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
42271 | #define BIF_CFG_DEV2_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
42272 | //BIF_CFG_DEV2_EPF0_0_SUB_CLASS |
42273 | #define BIF_CFG_DEV2_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
42274 | #define BIF_CFG_DEV2_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
42275 | //BIF_CFG_DEV2_EPF0_0_BASE_CLASS |
42276 | #define BIF_CFG_DEV2_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
42277 | #define BIF_CFG_DEV2_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
42278 | //BIF_CFG_DEV2_EPF0_0_CACHE_LINE |
42279 | #define BIF_CFG_DEV2_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
42280 | #define BIF_CFG_DEV2_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
42281 | //BIF_CFG_DEV2_EPF0_0_LATENCY |
42282 | #define BIF_CFG_DEV2_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
42283 | #define BIF_CFG_DEV2_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
42284 | //BIF_CFG_DEV2_EPF0_0_HEADER |
42285 | #define 0x0 |
42286 | #define 0x7 |
42287 | #define 0x7FL |
42288 | #define 0x80L |
42289 | //BIF_CFG_DEV2_EPF0_0_BIST |
42290 | #define BIF_CFG_DEV2_EPF0_0_BIST__BIST_COMP__SHIFT 0x0 |
42291 | #define BIF_CFG_DEV2_EPF0_0_BIST__BIST_STRT__SHIFT 0x6 |
42292 | #define BIF_CFG_DEV2_EPF0_0_BIST__BIST_CAP__SHIFT 0x7 |
42293 | #define BIF_CFG_DEV2_EPF0_0_BIST__BIST_COMP_MASK 0x0FL |
42294 | #define BIF_CFG_DEV2_EPF0_0_BIST__BIST_STRT_MASK 0x40L |
42295 | #define BIF_CFG_DEV2_EPF0_0_BIST__BIST_CAP_MASK 0x80L |
42296 | //BIF_CFG_DEV2_EPF0_0_BASE_ADDR_1 |
42297 | #define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
42298 | #define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
42299 | //BIF_CFG_DEV2_EPF0_0_BASE_ADDR_2 |
42300 | #define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
42301 | #define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
42302 | //BIF_CFG_DEV2_EPF0_0_BASE_ADDR_3 |
42303 | #define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
42304 | #define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
42305 | //BIF_CFG_DEV2_EPF0_0_BASE_ADDR_4 |
42306 | #define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
42307 | #define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
42308 | //BIF_CFG_DEV2_EPF0_0_BASE_ADDR_5 |
42309 | #define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
42310 | #define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
42311 | //BIF_CFG_DEV2_EPF0_0_BASE_ADDR_6 |
42312 | #define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
42313 | #define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
42314 | //BIF_CFG_DEV2_EPF0_0_ADAPTER_ID |
42315 | #define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
42316 | #define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
42317 | #define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
42318 | #define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
42319 | //BIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR |
42320 | #define BIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
42321 | #define BIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
42322 | //BIF_CFG_DEV2_EPF0_0_CAP_PTR |
42323 | #define BIF_CFG_DEV2_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
42324 | #define BIF_CFG_DEV2_EPF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
42325 | //BIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE |
42326 | #define BIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
42327 | #define BIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
42328 | //BIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN |
42329 | #define BIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
42330 | #define BIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
42331 | //BIF_CFG_DEV2_EPF0_0_MIN_GRANT |
42332 | #define BIF_CFG_DEV2_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
42333 | #define BIF_CFG_DEV2_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
42334 | //BIF_CFG_DEV2_EPF0_0_MAX_LATENCY |
42335 | #define BIF_CFG_DEV2_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
42336 | #define BIF_CFG_DEV2_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
42337 | //BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST |
42338 | #define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
42339 | #define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
42340 | #define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
42341 | #define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
42342 | #define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
42343 | #define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
42344 | //BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W |
42345 | #define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
42346 | #define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
42347 | #define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
42348 | #define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
42349 | //BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST |
42350 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
42351 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
42352 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
42353 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
42354 | //BIF_CFG_DEV2_EPF0_0_PMI_CAP |
42355 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0 |
42356 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
42357 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
42358 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
42359 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
42360 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
42361 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
42362 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
42363 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L |
42364 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
42365 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
42366 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
42367 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
42368 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
42369 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
42370 | #define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
42371 | //BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL |
42372 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
42373 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
42374 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
42375 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
42376 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
42377 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
42378 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
42379 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
42380 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
42381 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
42382 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
42383 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
42384 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
42385 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
42386 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
42387 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
42388 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
42389 | #define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
42390 | //BIF_CFG_DEV2_EPF0_0_SBRN |
42391 | #define BIF_CFG_DEV2_EPF0_0_SBRN__SBRN__SHIFT 0x0 |
42392 | #define BIF_CFG_DEV2_EPF0_0_SBRN__SBRN_MASK 0xFFL |
42393 | //BIF_CFG_DEV2_EPF0_0_FLADJ |
42394 | #define BIF_CFG_DEV2_EPF0_0_FLADJ__FLADJ__SHIFT 0x0 |
42395 | #define BIF_CFG_DEV2_EPF0_0_FLADJ__NFC__SHIFT 0x6 |
42396 | #define BIF_CFG_DEV2_EPF0_0_FLADJ__FLADJ_MASK 0x3FL |
42397 | #define BIF_CFG_DEV2_EPF0_0_FLADJ__NFC_MASK 0x40L |
42398 | //BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD |
42399 | #define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
42400 | #define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
42401 | #define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
42402 | #define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
42403 | //BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST |
42404 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
42405 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
42406 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
42407 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
42408 | //BIF_CFG_DEV2_EPF0_0_PCIE_CAP |
42409 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0 |
42410 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
42411 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
42412 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
42413 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL |
42414 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
42415 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
42416 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
42417 | //BIF_CFG_DEV2_EPF0_0_DEVICE_CAP |
42418 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
42419 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
42420 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
42421 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
42422 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
42423 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
42424 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
42425 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
42426 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
42427 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
42428 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
42429 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
42430 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
42431 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
42432 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
42433 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
42434 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
42435 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
42436 | //BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL |
42437 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
42438 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
42439 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
42440 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
42441 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
42442 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
42443 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
42444 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
42445 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
42446 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
42447 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
42448 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
42449 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
42450 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
42451 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
42452 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
42453 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
42454 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
42455 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
42456 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
42457 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
42458 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
42459 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
42460 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
42461 | //BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS |
42462 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
42463 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
42464 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
42465 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
42466 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
42467 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
42468 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
42469 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
42470 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
42471 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
42472 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
42473 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
42474 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
42475 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
42476 | //BIF_CFG_DEV2_EPF0_0_LINK_CAP |
42477 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
42478 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
42479 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
42480 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
42481 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
42482 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
42483 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
42484 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
42485 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
42486 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
42487 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
42488 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
42489 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
42490 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
42491 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
42492 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
42493 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
42494 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
42495 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
42496 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
42497 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
42498 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
42499 | //BIF_CFG_DEV2_EPF0_0_LINK_CNTL |
42500 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
42501 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
42502 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
42503 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
42504 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
42505 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
42506 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
42507 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
42508 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
42509 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
42510 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
42511 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
42512 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
42513 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
42514 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
42515 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
42516 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
42517 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
42518 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
42519 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
42520 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
42521 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
42522 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
42523 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
42524 | //BIF_CFG_DEV2_EPF0_0_LINK_STATUS |
42525 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
42526 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
42527 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
42528 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
42529 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
42530 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
42531 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
42532 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
42533 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
42534 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
42535 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
42536 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
42537 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
42538 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
42539 | //BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2 |
42540 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
42541 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
42542 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
42543 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
42544 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
42545 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
42546 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
42547 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
42548 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
42549 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
42550 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
42551 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
42552 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
42553 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
42554 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
42555 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
42556 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
42557 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
42558 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
42559 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
42560 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
42561 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
42562 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
42563 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
42564 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
42565 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
42566 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
42567 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
42568 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
42569 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
42570 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
42571 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
42572 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
42573 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
42574 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
42575 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
42576 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
42577 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
42578 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
42579 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
42580 | //BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2 |
42581 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
42582 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
42583 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
42584 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
42585 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
42586 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
42587 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
42588 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
42589 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
42590 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
42591 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
42592 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
42593 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
42594 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
42595 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
42596 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
42597 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
42598 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
42599 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
42600 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
42601 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
42602 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
42603 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
42604 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
42605 | //BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2 |
42606 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
42607 | #define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
42608 | //BIF_CFG_DEV2_EPF0_0_LINK_CAP2 |
42609 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
42610 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
42611 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
42612 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
42613 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
42614 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
42615 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
42616 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
42617 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
42618 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
42619 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
42620 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
42621 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
42622 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
42623 | //BIF_CFG_DEV2_EPF0_0_LINK_CNTL2 |
42624 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
42625 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
42626 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
42627 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
42628 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
42629 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
42630 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
42631 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
42632 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
42633 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
42634 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
42635 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
42636 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
42637 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
42638 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
42639 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
42640 | //BIF_CFG_DEV2_EPF0_0_LINK_STATUS2 |
42641 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
42642 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
42643 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
42644 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
42645 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
42646 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
42647 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
42648 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
42649 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
42650 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
42651 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
42652 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
42653 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
42654 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
42655 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
42656 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
42657 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
42658 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
42659 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
42660 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
42661 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
42662 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
42663 | //BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST |
42664 | #define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
42665 | #define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
42666 | #define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
42667 | #define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
42668 | //BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL |
42669 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
42670 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
42671 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
42672 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
42673 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
42674 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
42675 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
42676 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
42677 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
42678 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
42679 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
42680 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
42681 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
42682 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
42683 | //BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO |
42684 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
42685 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
42686 | //BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI |
42687 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
42688 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
42689 | //BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA |
42690 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
42691 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
42692 | //BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA |
42693 | #define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
42694 | #define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
42695 | //BIF_CFG_DEV2_EPF0_0_MSI_MASK |
42696 | #define BIF_CFG_DEV2_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
42697 | #define BIF_CFG_DEV2_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
42698 | //BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64 |
42699 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
42700 | #define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
42701 | //BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64 |
42702 | #define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
42703 | #define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
42704 | //BIF_CFG_DEV2_EPF0_0_MSI_MASK_64 |
42705 | #define BIF_CFG_DEV2_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
42706 | #define BIF_CFG_DEV2_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
42707 | //BIF_CFG_DEV2_EPF0_0_MSI_PENDING |
42708 | #define BIF_CFG_DEV2_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
42709 | #define BIF_CFG_DEV2_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
42710 | //BIF_CFG_DEV2_EPF0_0_MSI_PENDING_64 |
42711 | #define BIF_CFG_DEV2_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
42712 | #define BIF_CFG_DEV2_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
42713 | //BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST |
42714 | #define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
42715 | #define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
42716 | #define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
42717 | #define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
42718 | //BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL |
42719 | #define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
42720 | #define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
42721 | #define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
42722 | #define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
42723 | #define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
42724 | #define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
42725 | //BIF_CFG_DEV2_EPF0_0_MSIX_TABLE |
42726 | #define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
42727 | #define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
42728 | #define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
42729 | #define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
42730 | //BIF_CFG_DEV2_EPF0_0_MSIX_PBA |
42731 | #define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
42732 | #define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
42733 | #define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
42734 | #define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
42735 | //BIF_CFG_DEV2_EPF0_0_SATA_CAP_0 |
42736 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
42737 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
42738 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
42739 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
42740 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
42741 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
42742 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
42743 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
42744 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
42745 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
42746 | //BIF_CFG_DEV2_EPF0_0_SATA_CAP_1 |
42747 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
42748 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
42749 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
42750 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
42751 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
42752 | #define BIF_CFG_DEV2_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
42753 | //BIF_CFG_DEV2_EPF0_0_SATA_IDP_INDEX |
42754 | #define BIF_CFG_DEV2_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
42755 | #define BIF_CFG_DEV2_EPF0_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
42756 | #define BIF_CFG_DEV2_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
42757 | #define BIF_CFG_DEV2_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
42758 | #define BIF_CFG_DEV2_EPF0_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
42759 | #define BIF_CFG_DEV2_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
42760 | //BIF_CFG_DEV2_EPF0_0_SATA_IDP_DATA |
42761 | #define BIF_CFG_DEV2_EPF0_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
42762 | #define BIF_CFG_DEV2_EPF0_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
42763 | //BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
42764 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
42765 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
42766 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
42767 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
42768 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
42769 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
42770 | //BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR |
42771 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
42772 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
42773 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
42774 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
42775 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
42776 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
42777 | //BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1 |
42778 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
42779 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
42780 | //BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2 |
42781 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
42782 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
42783 | //BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST |
42784 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
42785 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
42786 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
42787 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
42788 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
42789 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
42790 | //BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1 |
42791 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
42792 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
42793 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
42794 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
42795 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
42796 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
42797 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
42798 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
42799 | //BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2 |
42800 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
42801 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
42802 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
42803 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
42804 | //BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL |
42805 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
42806 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
42807 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
42808 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
42809 | //BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS |
42810 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
42811 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
42812 | //BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP |
42813 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
42814 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
42815 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
42816 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
42817 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
42818 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
42819 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
42820 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
42821 | //BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL |
42822 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
42823 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
42824 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
42825 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
42826 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
42827 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
42828 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
42829 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
42830 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
42831 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
42832 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
42833 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
42834 | //BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS |
42835 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
42836 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
42837 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
42838 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
42839 | //BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP |
42840 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
42841 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
42842 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
42843 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
42844 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
42845 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
42846 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
42847 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
42848 | //BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL |
42849 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
42850 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
42851 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
42852 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
42853 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
42854 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
42855 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
42856 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
42857 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
42858 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
42859 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
42860 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
42861 | //BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS |
42862 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
42863 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
42864 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
42865 | #define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
42866 | //BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
42867 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
42868 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
42869 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
42870 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
42871 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
42872 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
42873 | //BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS |
42874 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
42875 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
42876 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
42877 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
42878 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
42879 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
42880 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
42881 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
42882 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
42883 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
42884 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
42885 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
42886 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
42887 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
42888 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
42889 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
42890 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
42891 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
42892 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
42893 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
42894 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
42895 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
42896 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
42897 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
42898 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
42899 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
42900 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
42901 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
42902 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
42903 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
42904 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
42905 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
42906 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
42907 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
42908 | //BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK |
42909 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
42910 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
42911 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
42912 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
42913 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
42914 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
42915 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
42916 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
42917 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
42918 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
42919 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
42920 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
42921 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
42922 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
42923 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
42924 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
42925 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
42926 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
42927 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
42928 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
42929 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
42930 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
42931 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
42932 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
42933 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
42934 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
42935 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
42936 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
42937 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
42938 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
42939 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
42940 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
42941 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
42942 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
42943 | //BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY |
42944 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
42945 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
42946 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
42947 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
42948 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
42949 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
42950 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
42951 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
42952 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
42953 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
42954 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
42955 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
42956 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
42957 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
42958 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
42959 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
42960 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
42961 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
42962 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
42963 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
42964 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
42965 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
42966 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
42967 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
42968 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
42969 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
42970 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
42971 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
42972 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
42973 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
42974 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
42975 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
42976 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
42977 | #define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
42978 | //BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS |
42979 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
42980 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
42981 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
42982 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
42983 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
42984 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
42985 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
42986 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
42987 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
42988 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
42989 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
42990 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
42991 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
42992 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
42993 | //BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK |
42994 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
42995 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
42996 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
42997 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
42998 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
42999 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
43000 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
43001 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
43002 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
43003 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
43004 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
43005 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
43006 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
43007 | #define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
43008 | //BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL |
43009 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
43010 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
43011 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
43012 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
43013 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
43014 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
43015 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
43016 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
43017 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
43018 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
43019 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
43020 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
43021 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
43022 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
43023 | //BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0 |
43024 | #define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
43025 | #define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
43026 | //BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1 |
43027 | #define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
43028 | #define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
43029 | //BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2 |
43030 | #define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
43031 | #define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
43032 | //BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3 |
43033 | #define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
43034 | #define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
43035 | //BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0 |
43036 | #define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
43037 | #define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
43038 | //BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1 |
43039 | #define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
43040 | #define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
43041 | //BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2 |
43042 | #define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
43043 | #define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
43044 | //BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3 |
43045 | #define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
43046 | #define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
43047 | //BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST |
43048 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43049 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43050 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43051 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43052 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43053 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43054 | //BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP |
43055 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
43056 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
43057 | //BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL |
43058 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
43059 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
43060 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
43061 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
43062 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
43063 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
43064 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
43065 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
43066 | //BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP |
43067 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
43068 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
43069 | //BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL |
43070 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
43071 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
43072 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
43073 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
43074 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
43075 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
43076 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
43077 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
43078 | //BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP |
43079 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
43080 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
43081 | //BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL |
43082 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
43083 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
43084 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
43085 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
43086 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
43087 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
43088 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
43089 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
43090 | //BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP |
43091 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
43092 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
43093 | //BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL |
43094 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
43095 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
43096 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
43097 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
43098 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
43099 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
43100 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
43101 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
43102 | //BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP |
43103 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
43104 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
43105 | //BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL |
43106 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
43107 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
43108 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
43109 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
43110 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
43111 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
43112 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
43113 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
43114 | //BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP |
43115 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
43116 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
43117 | //BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL |
43118 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
43119 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
43120 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
43121 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
43122 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
43123 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
43124 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
43125 | #define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
43126 | //BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
43127 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43128 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43129 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43130 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43131 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43132 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43133 | //BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT |
43134 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
43135 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
43136 | //BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA |
43137 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
43138 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
43139 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
43140 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
43141 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
43142 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
43143 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
43144 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
43145 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
43146 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
43147 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
43148 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
43149 | //BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP |
43150 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
43151 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
43152 | //BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST |
43153 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43154 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43155 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43156 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43157 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43158 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43159 | //BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP |
43160 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
43161 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
43162 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
43163 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
43164 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
43165 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
43166 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
43167 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
43168 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
43169 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
43170 | //BIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR |
43171 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
43172 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
43173 | //BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS |
43174 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
43175 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
43176 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
43177 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
43178 | //BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL |
43179 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
43180 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
43181 | //BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
43182 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43183 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43184 | //BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
43185 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43186 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43187 | //BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
43188 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43189 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43190 | //BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
43191 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43192 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43193 | //BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
43194 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43195 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43196 | //BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
43197 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43198 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43199 | //BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
43200 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43201 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43202 | //BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
43203 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
43204 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
43205 | //BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST |
43206 | #define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43207 | #define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43208 | #define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43209 | #define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43210 | #define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43211 | #define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43212 | //BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3 |
43213 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
43214 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
43215 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
43216 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
43217 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
43218 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
43219 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS |
43220 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
43221 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
43222 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL |
43223 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43224 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43225 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43226 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43227 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43228 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43229 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43230 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43231 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL |
43232 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43233 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43234 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43235 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43236 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43237 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43238 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43239 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43240 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL |
43241 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43242 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43243 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43244 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43245 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43246 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43247 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43248 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43249 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL |
43250 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43251 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43252 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43253 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43254 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43255 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43256 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43257 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43258 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL |
43259 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43260 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43261 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43262 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43263 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43264 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43265 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43266 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43267 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL |
43268 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43269 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43270 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43271 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43272 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43273 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43274 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43275 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43276 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL |
43277 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43278 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43279 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43280 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43281 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43282 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43283 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43284 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43285 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL |
43286 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43287 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43288 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43289 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43290 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43291 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43292 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43293 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43294 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL |
43295 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43296 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43297 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43298 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43299 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43300 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43301 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43302 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43303 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL |
43304 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43305 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43306 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43307 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43308 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43309 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43310 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43311 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43312 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL |
43313 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43314 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43315 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43316 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43317 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43318 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43319 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43320 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43321 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL |
43322 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43323 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43324 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43325 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43326 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43327 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43328 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43329 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43330 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL |
43331 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43332 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43333 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43334 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43335 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43336 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43337 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43338 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43339 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL |
43340 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43341 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43342 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43343 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43344 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43345 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43346 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43347 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43348 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL |
43349 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43350 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43351 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43352 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43353 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43354 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43355 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43356 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43357 | //BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL |
43358 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 |
43359 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 |
43360 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 |
43361 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc |
43362 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL |
43363 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L |
43364 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L |
43365 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L |
43366 | //BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST |
43367 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43368 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43369 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43370 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43371 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43372 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43373 | //BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP |
43374 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
43375 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
43376 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
43377 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
43378 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
43379 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
43380 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
43381 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
43382 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
43383 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
43384 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
43385 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
43386 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
43387 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
43388 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
43389 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
43390 | //BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL |
43391 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
43392 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
43393 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
43394 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
43395 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
43396 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
43397 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
43398 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
43399 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
43400 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
43401 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
43402 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
43403 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
43404 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
43405 | //BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST |
43406 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43407 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43408 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43409 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43410 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43411 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43412 | //BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP |
43413 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
43414 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
43415 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
43416 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
43417 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
43418 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
43419 | //BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL |
43420 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
43421 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
43422 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
43423 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
43424 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
43425 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
43426 | //BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST |
43427 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43428 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43429 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43430 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43431 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43432 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43433 | //BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP |
43434 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
43435 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
43436 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
43437 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
43438 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
43439 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
43440 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
43441 | #define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
43442 | //BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST |
43443 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43444 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43445 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43446 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43447 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43448 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43449 | //BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP |
43450 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
43451 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
43452 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
43453 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
43454 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
43455 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
43456 | //BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL |
43457 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
43458 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
43459 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
43460 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
43461 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
43462 | #define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
43463 | //BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST |
43464 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43465 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43466 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43467 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43468 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43469 | #define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43470 | //BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP |
43471 | #define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
43472 | #define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
43473 | #define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
43474 | #define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
43475 | //BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS |
43476 | #define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
43477 | #define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
43478 | #define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
43479 | #define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
43480 | //BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST |
43481 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43482 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43483 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43484 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43485 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43486 | #define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43487 | //BIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT |
43488 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
43489 | #define BIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
43490 | //BIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT |
43491 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
43492 | #define BIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
43493 | //BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT |
43494 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
43495 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
43496 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
43497 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
43498 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
43499 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
43500 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
43501 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
43502 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
43503 | #define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
43504 | //BIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT |
43505 | #define BIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
43506 | #define BIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
43507 | //BIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT |
43508 | #define BIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
43509 | #define BIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
43510 | //BIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT |
43511 | #define BIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
43512 | #define BIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
43513 | //BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT |
43514 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43515 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
43516 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
43517 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
43518 | //BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT |
43519 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43520 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
43521 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
43522 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
43523 | //BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT |
43524 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43525 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
43526 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
43527 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
43528 | //BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT |
43529 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43530 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
43531 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
43532 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
43533 | //BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT |
43534 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43535 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
43536 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
43537 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
43538 | //BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT |
43539 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43540 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
43541 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
43542 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
43543 | //BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT |
43544 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43545 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
43546 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
43547 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
43548 | //BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT |
43549 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43550 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
43551 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
43552 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
43553 | //BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT |
43554 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43555 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
43556 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
43557 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
43558 | //BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT |
43559 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43560 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
43561 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
43562 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
43563 | //BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT |
43564 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43565 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
43566 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
43567 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
43568 | //BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT |
43569 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43570 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
43571 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
43572 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
43573 | //BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT |
43574 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43575 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
43576 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
43577 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
43578 | //BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT |
43579 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43580 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
43581 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
43582 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
43583 | //BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT |
43584 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43585 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
43586 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
43587 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
43588 | //BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT |
43589 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
43590 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
43591 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
43592 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
43593 | //BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST |
43594 | #define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43595 | #define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43596 | #define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43597 | #define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43598 | #define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43599 | #define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43600 | //BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP |
43601 | #define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
43602 | #define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
43603 | //BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS |
43604 | #define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
43605 | #define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
43606 | #define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
43607 | #define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
43608 | //BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL |
43609 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
43610 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
43611 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
43612 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
43613 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
43614 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
43615 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
43616 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
43617 | //BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS |
43618 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43619 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43620 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
43621 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43622 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43623 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
43624 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
43625 | #define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43626 | //BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL |
43627 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
43628 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
43629 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
43630 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
43631 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
43632 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
43633 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
43634 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
43635 | //BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS |
43636 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43637 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43638 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
43639 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43640 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43641 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
43642 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
43643 | #define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43644 | //BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL |
43645 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
43646 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
43647 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
43648 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
43649 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
43650 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
43651 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
43652 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
43653 | //BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS |
43654 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43655 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43656 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
43657 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43658 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43659 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
43660 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
43661 | #define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43662 | //BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL |
43663 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
43664 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
43665 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
43666 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
43667 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
43668 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
43669 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
43670 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
43671 | //BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS |
43672 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43673 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43674 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
43675 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43676 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43677 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
43678 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
43679 | #define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43680 | //BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL |
43681 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
43682 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
43683 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
43684 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
43685 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
43686 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
43687 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
43688 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
43689 | //BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS |
43690 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43691 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43692 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
43693 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43694 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43695 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
43696 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
43697 | #define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43698 | //BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL |
43699 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
43700 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
43701 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
43702 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
43703 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
43704 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
43705 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
43706 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
43707 | //BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS |
43708 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43709 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43710 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
43711 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43712 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43713 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
43714 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
43715 | #define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43716 | //BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL |
43717 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
43718 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
43719 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
43720 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
43721 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
43722 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
43723 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
43724 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
43725 | //BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS |
43726 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43727 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43728 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
43729 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43730 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43731 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
43732 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
43733 | #define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43734 | //BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL |
43735 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
43736 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
43737 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
43738 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
43739 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
43740 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
43741 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
43742 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
43743 | //BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS |
43744 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43745 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43746 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
43747 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43748 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43749 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
43750 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
43751 | #define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43752 | //BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL |
43753 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
43754 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
43755 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
43756 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
43757 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
43758 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
43759 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
43760 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
43761 | //BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS |
43762 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43763 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43764 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
43765 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43766 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43767 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
43768 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
43769 | #define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43770 | //BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL |
43771 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
43772 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
43773 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
43774 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
43775 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
43776 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
43777 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
43778 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
43779 | //BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS |
43780 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43781 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43782 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
43783 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43784 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43785 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
43786 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
43787 | #define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43788 | //BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL |
43789 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
43790 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
43791 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
43792 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
43793 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
43794 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
43795 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
43796 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
43797 | //BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS |
43798 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43799 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43800 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
43801 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43802 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43803 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
43804 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
43805 | #define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43806 | //BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL |
43807 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
43808 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
43809 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
43810 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
43811 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
43812 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
43813 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
43814 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
43815 | //BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS |
43816 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43817 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43818 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
43819 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43820 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43821 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
43822 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
43823 | #define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43824 | //BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL |
43825 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
43826 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
43827 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
43828 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
43829 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
43830 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
43831 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
43832 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
43833 | //BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS |
43834 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43835 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43836 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
43837 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43838 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43839 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
43840 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
43841 | #define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43842 | //BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL |
43843 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
43844 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
43845 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
43846 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
43847 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
43848 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
43849 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
43850 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
43851 | //BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS |
43852 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43853 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43854 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
43855 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43856 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43857 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
43858 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
43859 | #define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43860 | //BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL |
43861 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
43862 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
43863 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
43864 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
43865 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
43866 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
43867 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
43868 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
43869 | //BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS |
43870 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43871 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43872 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
43873 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43874 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43875 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
43876 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
43877 | #define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43878 | //BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL |
43879 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
43880 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
43881 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
43882 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
43883 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
43884 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
43885 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
43886 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
43887 | //BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS |
43888 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
43889 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
43890 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
43891 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
43892 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
43893 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
43894 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
43895 | #define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
43896 | //BIF_CFG_DEV2_EPF0_0_PCIE_RTR_ENH_CAP_LIST |
43897 | #define BIF_CFG_DEV2_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
43898 | #define BIF_CFG_DEV2_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
43899 | #define BIF_CFG_DEV2_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
43900 | #define BIF_CFG_DEV2_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
43901 | #define BIF_CFG_DEV2_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
43902 | #define BIF_CFG_DEV2_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
43903 | //BIF_CFG_DEV2_EPF0_0_RTR_DATA1 |
43904 | #define BIF_CFG_DEV2_EPF0_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
43905 | #define BIF_CFG_DEV2_EPF0_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
43906 | #define BIF_CFG_DEV2_EPF0_0_RTR_DATA1__VALID__SHIFT 0x1f |
43907 | #define BIF_CFG_DEV2_EPF0_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
43908 | #define BIF_CFG_DEV2_EPF0_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
43909 | #define BIF_CFG_DEV2_EPF0_0_RTR_DATA1__VALID_MASK 0x80000000L |
43910 | //BIF_CFG_DEV2_EPF0_0_RTR_DATA2 |
43911 | #define BIF_CFG_DEV2_EPF0_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
43912 | #define BIF_CFG_DEV2_EPF0_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
43913 | #define BIF_CFG_DEV2_EPF0_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
43914 | #define BIF_CFG_DEV2_EPF0_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
43915 | |
43916 | |
43917 | // addressBlock: nbio_nbif0_bif_cfg_dev2_epf1_bifcfgdecp |
43918 | //BIF_CFG_DEV2_EPF1_0_VENDOR_ID |
43919 | #define BIF_CFG_DEV2_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
43920 | #define BIF_CFG_DEV2_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
43921 | //BIF_CFG_DEV2_EPF1_0_DEVICE_ID |
43922 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
43923 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
43924 | //BIF_CFG_DEV2_EPF1_0_COMMAND |
43925 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
43926 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
43927 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
43928 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
43929 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
43930 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
43931 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
43932 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8 |
43933 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
43934 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa |
43935 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
43936 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
43937 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
43938 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
43939 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
43940 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
43941 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L |
43942 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L |
43943 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
43944 | #define BIF_CFG_DEV2_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L |
43945 | //BIF_CFG_DEV2_EPF1_0_STATUS |
43946 | #define BIF_CFG_DEV2_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
43947 | #define BIF_CFG_DEV2_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3 |
43948 | #define BIF_CFG_DEV2_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4 |
43949 | #define BIF_CFG_DEV2_EPF1_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
43950 | #define BIF_CFG_DEV2_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
43951 | #define BIF_CFG_DEV2_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
43952 | #define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
43953 | #define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
43954 | #define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
43955 | #define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
43956 | #define BIF_CFG_DEV2_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
43957 | #define BIF_CFG_DEV2_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L |
43958 | #define BIF_CFG_DEV2_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L |
43959 | #define BIF_CFG_DEV2_EPF1_0_STATUS__PCI_66_CAP_MASK 0x0020L |
43960 | #define BIF_CFG_DEV2_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
43961 | #define BIF_CFG_DEV2_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
43962 | #define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
43963 | #define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
43964 | #define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
43965 | #define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
43966 | //BIF_CFG_DEV2_EPF1_0_REVISION_ID |
43967 | #define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
43968 | #define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
43969 | #define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
43970 | #define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
43971 | //BIF_CFG_DEV2_EPF1_0_PROG_INTERFACE |
43972 | #define BIF_CFG_DEV2_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
43973 | #define BIF_CFG_DEV2_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
43974 | //BIF_CFG_DEV2_EPF1_0_SUB_CLASS |
43975 | #define BIF_CFG_DEV2_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
43976 | #define BIF_CFG_DEV2_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
43977 | //BIF_CFG_DEV2_EPF1_0_BASE_CLASS |
43978 | #define BIF_CFG_DEV2_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
43979 | #define BIF_CFG_DEV2_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
43980 | //BIF_CFG_DEV2_EPF1_0_CACHE_LINE |
43981 | #define BIF_CFG_DEV2_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
43982 | #define BIF_CFG_DEV2_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
43983 | //BIF_CFG_DEV2_EPF1_0_LATENCY |
43984 | #define BIF_CFG_DEV2_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
43985 | #define BIF_CFG_DEV2_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
43986 | //BIF_CFG_DEV2_EPF1_0_HEADER |
43987 | #define 0x0 |
43988 | #define 0x7 |
43989 | #define 0x7FL |
43990 | #define 0x80L |
43991 | //BIF_CFG_DEV2_EPF1_0_BIST |
43992 | #define BIF_CFG_DEV2_EPF1_0_BIST__BIST_COMP__SHIFT 0x0 |
43993 | #define BIF_CFG_DEV2_EPF1_0_BIST__BIST_STRT__SHIFT 0x6 |
43994 | #define BIF_CFG_DEV2_EPF1_0_BIST__BIST_CAP__SHIFT 0x7 |
43995 | #define BIF_CFG_DEV2_EPF1_0_BIST__BIST_COMP_MASK 0x0FL |
43996 | #define BIF_CFG_DEV2_EPF1_0_BIST__BIST_STRT_MASK 0x40L |
43997 | #define BIF_CFG_DEV2_EPF1_0_BIST__BIST_CAP_MASK 0x80L |
43998 | //BIF_CFG_DEV2_EPF1_0_BASE_ADDR_1 |
43999 | #define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
44000 | #define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
44001 | //BIF_CFG_DEV2_EPF1_0_BASE_ADDR_2 |
44002 | #define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
44003 | #define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
44004 | //BIF_CFG_DEV2_EPF1_0_BASE_ADDR_3 |
44005 | #define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
44006 | #define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
44007 | //BIF_CFG_DEV2_EPF1_0_BASE_ADDR_4 |
44008 | #define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
44009 | #define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
44010 | //BIF_CFG_DEV2_EPF1_0_BASE_ADDR_5 |
44011 | #define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
44012 | #define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
44013 | //BIF_CFG_DEV2_EPF1_0_BASE_ADDR_6 |
44014 | #define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
44015 | #define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
44016 | //BIF_CFG_DEV2_EPF1_0_ADAPTER_ID |
44017 | #define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
44018 | #define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
44019 | #define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
44020 | #define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
44021 | //BIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR |
44022 | #define BIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
44023 | #define BIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
44024 | //BIF_CFG_DEV2_EPF1_0_CAP_PTR |
44025 | #define BIF_CFG_DEV2_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
44026 | #define BIF_CFG_DEV2_EPF1_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
44027 | //BIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE |
44028 | #define BIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
44029 | #define BIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
44030 | //BIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN |
44031 | #define BIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
44032 | #define BIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
44033 | //BIF_CFG_DEV2_EPF1_0_MIN_GRANT |
44034 | #define BIF_CFG_DEV2_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
44035 | #define BIF_CFG_DEV2_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
44036 | //BIF_CFG_DEV2_EPF1_0_MAX_LATENCY |
44037 | #define BIF_CFG_DEV2_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
44038 | #define BIF_CFG_DEV2_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
44039 | //BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST |
44040 | #define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
44041 | #define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
44042 | #define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
44043 | #define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
44044 | #define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
44045 | #define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
44046 | //BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W |
44047 | #define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
44048 | #define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
44049 | #define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
44050 | #define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
44051 | //BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST |
44052 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
44053 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
44054 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
44055 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
44056 | //BIF_CFG_DEV2_EPF1_0_PMI_CAP |
44057 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0 |
44058 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
44059 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
44060 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
44061 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
44062 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
44063 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
44064 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
44065 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L |
44066 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
44067 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
44068 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
44069 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
44070 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
44071 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
44072 | #define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
44073 | //BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL |
44074 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
44075 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
44076 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
44077 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
44078 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
44079 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
44080 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
44081 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
44082 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
44083 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
44084 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
44085 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
44086 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
44087 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
44088 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
44089 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
44090 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
44091 | #define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
44092 | //BIF_CFG_DEV2_EPF1_0_SBRN |
44093 | #define BIF_CFG_DEV2_EPF1_0_SBRN__SBRN__SHIFT 0x0 |
44094 | #define BIF_CFG_DEV2_EPF1_0_SBRN__SBRN_MASK 0xFFL |
44095 | //BIF_CFG_DEV2_EPF1_0_FLADJ |
44096 | #define BIF_CFG_DEV2_EPF1_0_FLADJ__FLADJ__SHIFT 0x0 |
44097 | #define BIF_CFG_DEV2_EPF1_0_FLADJ__NFC__SHIFT 0x6 |
44098 | #define BIF_CFG_DEV2_EPF1_0_FLADJ__FLADJ_MASK 0x3FL |
44099 | #define BIF_CFG_DEV2_EPF1_0_FLADJ__NFC_MASK 0x40L |
44100 | //BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD |
44101 | #define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
44102 | #define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
44103 | #define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
44104 | #define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
44105 | //BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST |
44106 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
44107 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
44108 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
44109 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
44110 | //BIF_CFG_DEV2_EPF1_0_PCIE_CAP |
44111 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0 |
44112 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
44113 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
44114 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
44115 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL |
44116 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
44117 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
44118 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
44119 | //BIF_CFG_DEV2_EPF1_0_DEVICE_CAP |
44120 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
44121 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
44122 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
44123 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
44124 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
44125 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
44126 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
44127 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
44128 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
44129 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
44130 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
44131 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
44132 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
44133 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
44134 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
44135 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
44136 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
44137 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
44138 | //BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL |
44139 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
44140 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
44141 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
44142 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
44143 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
44144 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
44145 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
44146 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
44147 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
44148 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
44149 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
44150 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
44151 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
44152 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
44153 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
44154 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
44155 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
44156 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
44157 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
44158 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
44159 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
44160 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
44161 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
44162 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
44163 | //BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS |
44164 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
44165 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
44166 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
44167 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
44168 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
44169 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
44170 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
44171 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
44172 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
44173 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
44174 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
44175 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
44176 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
44177 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
44178 | //BIF_CFG_DEV2_EPF1_0_LINK_CAP |
44179 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
44180 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
44181 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
44182 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
44183 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
44184 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
44185 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
44186 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
44187 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
44188 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
44189 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
44190 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
44191 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
44192 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
44193 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
44194 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
44195 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
44196 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
44197 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
44198 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
44199 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
44200 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
44201 | //BIF_CFG_DEV2_EPF1_0_LINK_CNTL |
44202 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
44203 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
44204 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
44205 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
44206 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
44207 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
44208 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
44209 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
44210 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
44211 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
44212 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
44213 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
44214 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
44215 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
44216 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
44217 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
44218 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
44219 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
44220 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
44221 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
44222 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
44223 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
44224 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
44225 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
44226 | //BIF_CFG_DEV2_EPF1_0_LINK_STATUS |
44227 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
44228 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
44229 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
44230 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
44231 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
44232 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
44233 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
44234 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
44235 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
44236 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
44237 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
44238 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
44239 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
44240 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
44241 | //BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2 |
44242 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
44243 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
44244 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
44245 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
44246 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
44247 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
44248 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
44249 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
44250 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
44251 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
44252 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
44253 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
44254 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
44255 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
44256 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
44257 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
44258 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
44259 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
44260 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
44261 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
44262 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
44263 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
44264 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
44265 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
44266 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
44267 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
44268 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
44269 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
44270 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
44271 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
44272 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
44273 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
44274 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
44275 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
44276 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
44277 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
44278 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
44279 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
44280 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
44281 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
44282 | //BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2 |
44283 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
44284 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
44285 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
44286 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
44287 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
44288 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
44289 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
44290 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
44291 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
44292 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
44293 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
44294 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
44295 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
44296 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
44297 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
44298 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
44299 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
44300 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
44301 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
44302 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
44303 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
44304 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
44305 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
44306 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
44307 | //BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2 |
44308 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
44309 | #define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
44310 | //BIF_CFG_DEV2_EPF1_0_LINK_CAP2 |
44311 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
44312 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
44313 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
44314 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
44315 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
44316 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
44317 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
44318 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
44319 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
44320 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
44321 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
44322 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
44323 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
44324 | #define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
44325 | //BIF_CFG_DEV2_EPF1_0_LINK_CNTL2 |
44326 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
44327 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
44328 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
44329 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
44330 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
44331 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
44332 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
44333 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
44334 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
44335 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
44336 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
44337 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
44338 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
44339 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
44340 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
44341 | #define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
44342 | //BIF_CFG_DEV2_EPF1_0_LINK_STATUS2 |
44343 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
44344 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
44345 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
44346 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
44347 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
44348 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
44349 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
44350 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
44351 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
44352 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
44353 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
44354 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
44355 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
44356 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
44357 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
44358 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
44359 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
44360 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
44361 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
44362 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
44363 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
44364 | #define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
44365 | //BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST |
44366 | #define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
44367 | #define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
44368 | #define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
44369 | #define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
44370 | //BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL |
44371 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
44372 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
44373 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
44374 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
44375 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
44376 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
44377 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
44378 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
44379 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
44380 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
44381 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
44382 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
44383 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
44384 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
44385 | //BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO |
44386 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
44387 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
44388 | //BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI |
44389 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
44390 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
44391 | //BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA |
44392 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
44393 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
44394 | //BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA |
44395 | #define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
44396 | #define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
44397 | //BIF_CFG_DEV2_EPF1_0_MSI_MASK |
44398 | #define BIF_CFG_DEV2_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
44399 | #define BIF_CFG_DEV2_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
44400 | //BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64 |
44401 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
44402 | #define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
44403 | //BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64 |
44404 | #define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
44405 | #define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
44406 | //BIF_CFG_DEV2_EPF1_0_MSI_MASK_64 |
44407 | #define BIF_CFG_DEV2_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
44408 | #define BIF_CFG_DEV2_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
44409 | //BIF_CFG_DEV2_EPF1_0_MSI_PENDING |
44410 | #define BIF_CFG_DEV2_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
44411 | #define BIF_CFG_DEV2_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
44412 | //BIF_CFG_DEV2_EPF1_0_MSI_PENDING_64 |
44413 | #define BIF_CFG_DEV2_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
44414 | #define BIF_CFG_DEV2_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
44415 | //BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST |
44416 | #define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
44417 | #define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
44418 | #define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
44419 | #define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
44420 | //BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL |
44421 | #define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
44422 | #define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
44423 | #define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
44424 | #define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
44425 | #define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
44426 | #define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
44427 | //BIF_CFG_DEV2_EPF1_0_MSIX_TABLE |
44428 | #define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
44429 | #define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
44430 | #define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
44431 | #define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
44432 | //BIF_CFG_DEV2_EPF1_0_MSIX_PBA |
44433 | #define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
44434 | #define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
44435 | #define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
44436 | #define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
44437 | //BIF_CFG_DEV2_EPF1_0_SATA_CAP_0 |
44438 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
44439 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
44440 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
44441 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
44442 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
44443 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
44444 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
44445 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
44446 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
44447 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
44448 | //BIF_CFG_DEV2_EPF1_0_SATA_CAP_1 |
44449 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
44450 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
44451 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
44452 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
44453 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
44454 | #define BIF_CFG_DEV2_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
44455 | //BIF_CFG_DEV2_EPF1_0_SATA_IDP_INDEX |
44456 | #define BIF_CFG_DEV2_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
44457 | #define BIF_CFG_DEV2_EPF1_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
44458 | #define BIF_CFG_DEV2_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
44459 | #define BIF_CFG_DEV2_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
44460 | #define BIF_CFG_DEV2_EPF1_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
44461 | #define BIF_CFG_DEV2_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
44462 | //BIF_CFG_DEV2_EPF1_0_SATA_IDP_DATA |
44463 | #define BIF_CFG_DEV2_EPF1_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
44464 | #define BIF_CFG_DEV2_EPF1_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
44465 | //BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
44466 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44467 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44468 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44469 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44470 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44471 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44472 | //BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR |
44473 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
44474 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
44475 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
44476 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
44477 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
44478 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
44479 | //BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1 |
44480 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
44481 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
44482 | //BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2 |
44483 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
44484 | #define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
44485 | //BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
44486 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44487 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44488 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44489 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44490 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44491 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44492 | //BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS |
44493 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
44494 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
44495 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
44496 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
44497 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
44498 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
44499 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
44500 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
44501 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
44502 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
44503 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
44504 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
44505 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
44506 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
44507 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
44508 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
44509 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
44510 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
44511 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
44512 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
44513 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
44514 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
44515 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
44516 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
44517 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
44518 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
44519 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
44520 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
44521 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
44522 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
44523 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
44524 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
44525 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
44526 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
44527 | //BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK |
44528 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
44529 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
44530 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
44531 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
44532 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
44533 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
44534 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
44535 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
44536 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
44537 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
44538 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
44539 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
44540 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
44541 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
44542 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
44543 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
44544 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
44545 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
44546 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
44547 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
44548 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
44549 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
44550 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
44551 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
44552 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
44553 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
44554 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
44555 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
44556 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
44557 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
44558 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
44559 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
44560 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
44561 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
44562 | //BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY |
44563 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
44564 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
44565 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
44566 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
44567 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
44568 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
44569 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
44570 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
44571 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
44572 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
44573 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
44574 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
44575 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
44576 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
44577 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
44578 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
44579 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
44580 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
44581 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
44582 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
44583 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
44584 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
44585 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
44586 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
44587 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
44588 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
44589 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
44590 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
44591 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
44592 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
44593 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
44594 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
44595 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
44596 | #define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
44597 | //BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS |
44598 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
44599 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
44600 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
44601 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
44602 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
44603 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
44604 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
44605 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
44606 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
44607 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
44608 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
44609 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
44610 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
44611 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
44612 | //BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK |
44613 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
44614 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
44615 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
44616 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
44617 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
44618 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
44619 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
44620 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
44621 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
44622 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
44623 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
44624 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
44625 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
44626 | #define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
44627 | //BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL |
44628 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
44629 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
44630 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
44631 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
44632 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
44633 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
44634 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
44635 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
44636 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
44637 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
44638 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
44639 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
44640 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
44641 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
44642 | //BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0 |
44643 | #define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
44644 | #define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
44645 | //BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1 |
44646 | #define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
44647 | #define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
44648 | //BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2 |
44649 | #define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
44650 | #define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
44651 | //BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3 |
44652 | #define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
44653 | #define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
44654 | //BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0 |
44655 | #define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
44656 | #define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
44657 | //BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1 |
44658 | #define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
44659 | #define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
44660 | //BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2 |
44661 | #define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
44662 | #define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
44663 | //BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3 |
44664 | #define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
44665 | #define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
44666 | //BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST |
44667 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44668 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44669 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44670 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44671 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44672 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44673 | //BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP |
44674 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
44675 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
44676 | //BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL |
44677 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
44678 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
44679 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
44680 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
44681 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
44682 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
44683 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
44684 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
44685 | //BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP |
44686 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
44687 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
44688 | //BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL |
44689 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
44690 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
44691 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
44692 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
44693 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
44694 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
44695 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
44696 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
44697 | //BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP |
44698 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
44699 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
44700 | //BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL |
44701 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
44702 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
44703 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
44704 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
44705 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
44706 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
44707 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
44708 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
44709 | //BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP |
44710 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
44711 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
44712 | //BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL |
44713 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
44714 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
44715 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
44716 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
44717 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
44718 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
44719 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
44720 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
44721 | //BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP |
44722 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
44723 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
44724 | //BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL |
44725 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
44726 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
44727 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
44728 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
44729 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
44730 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
44731 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
44732 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
44733 | //BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP |
44734 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
44735 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
44736 | //BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL |
44737 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
44738 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
44739 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
44740 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
44741 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
44742 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
44743 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
44744 | #define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
44745 | //BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
44746 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44747 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44748 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44749 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44750 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44751 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44752 | //BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT |
44753 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
44754 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
44755 | //BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA |
44756 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
44757 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
44758 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
44759 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
44760 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
44761 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
44762 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
44763 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
44764 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
44765 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
44766 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
44767 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
44768 | //BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP |
44769 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
44770 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
44771 | //BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST |
44772 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44773 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44774 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44775 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44776 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44777 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44778 | //BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP |
44779 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
44780 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
44781 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
44782 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
44783 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
44784 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
44785 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
44786 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
44787 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
44788 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
44789 | //BIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR |
44790 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
44791 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
44792 | //BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS |
44793 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
44794 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
44795 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
44796 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
44797 | //BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL |
44798 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
44799 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
44800 | //BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
44801 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44802 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44803 | //BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
44804 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44805 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44806 | //BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
44807 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44808 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44809 | //BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
44810 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44811 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44812 | //BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
44813 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44814 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44815 | //BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
44816 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44817 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44818 | //BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
44819 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44820 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44821 | //BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
44822 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
44823 | #define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
44824 | //BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST |
44825 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44826 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44827 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44828 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44829 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44830 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44831 | //BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP |
44832 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
44833 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
44834 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
44835 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
44836 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
44837 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
44838 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
44839 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
44840 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
44841 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
44842 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
44843 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
44844 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
44845 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
44846 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
44847 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
44848 | //BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL |
44849 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
44850 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
44851 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
44852 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
44853 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
44854 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
44855 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
44856 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
44857 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
44858 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
44859 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
44860 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
44861 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
44862 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
44863 | //BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST |
44864 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44865 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44866 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44867 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44868 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44869 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44870 | //BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP |
44871 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
44872 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
44873 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
44874 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
44875 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
44876 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
44877 | //BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL |
44878 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
44879 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
44880 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
44881 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
44882 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
44883 | #define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
44884 | //BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST |
44885 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44886 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44887 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44888 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44889 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44890 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44891 | //BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP |
44892 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
44893 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
44894 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
44895 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
44896 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
44897 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
44898 | //BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL |
44899 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
44900 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
44901 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
44902 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
44903 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
44904 | #define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
44905 | //BIF_CFG_DEV2_EPF1_0_PCIE_RTR_ENH_CAP_LIST |
44906 | #define BIF_CFG_DEV2_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
44907 | #define BIF_CFG_DEV2_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
44908 | #define BIF_CFG_DEV2_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
44909 | #define BIF_CFG_DEV2_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
44910 | #define BIF_CFG_DEV2_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
44911 | #define BIF_CFG_DEV2_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
44912 | //BIF_CFG_DEV2_EPF1_0_RTR_DATA1 |
44913 | #define BIF_CFG_DEV2_EPF1_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
44914 | #define BIF_CFG_DEV2_EPF1_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
44915 | #define BIF_CFG_DEV2_EPF1_0_RTR_DATA1__VALID__SHIFT 0x1f |
44916 | #define BIF_CFG_DEV2_EPF1_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
44917 | #define BIF_CFG_DEV2_EPF1_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
44918 | #define BIF_CFG_DEV2_EPF1_0_RTR_DATA1__VALID_MASK 0x80000000L |
44919 | //BIF_CFG_DEV2_EPF1_0_RTR_DATA2 |
44920 | #define BIF_CFG_DEV2_EPF1_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
44921 | #define BIF_CFG_DEV2_EPF1_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
44922 | #define BIF_CFG_DEV2_EPF1_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
44923 | #define BIF_CFG_DEV2_EPF1_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
44924 | |
44925 | |
44926 | // addressBlock: nbio_nbif0_bif_cfg_dev2_epf2_bifcfgdecp |
44927 | //BIF_CFG_DEV2_EPF2_0_VENDOR_ID |
44928 | #define BIF_CFG_DEV2_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
44929 | #define BIF_CFG_DEV2_EPF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
44930 | //BIF_CFG_DEV2_EPF2_0_DEVICE_ID |
44931 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
44932 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
44933 | //BIF_CFG_DEV2_EPF2_0_COMMAND |
44934 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
44935 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
44936 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
44937 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
44938 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
44939 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
44940 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
44941 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__SERR_EN__SHIFT 0x8 |
44942 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
44943 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__INT_DIS__SHIFT 0xa |
44944 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
44945 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
44946 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
44947 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
44948 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
44949 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
44950 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__AD_STEPPING_MASK 0x0080L |
44951 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__SERR_EN_MASK 0x0100L |
44952 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
44953 | #define BIF_CFG_DEV2_EPF2_0_COMMAND__INT_DIS_MASK 0x0400L |
44954 | //BIF_CFG_DEV2_EPF2_0_STATUS |
44955 | #define BIF_CFG_DEV2_EPF2_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
44956 | #define BIF_CFG_DEV2_EPF2_0_STATUS__INT_STATUS__SHIFT 0x3 |
44957 | #define BIF_CFG_DEV2_EPF2_0_STATUS__CAP_LIST__SHIFT 0x4 |
44958 | #define BIF_CFG_DEV2_EPF2_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
44959 | #define BIF_CFG_DEV2_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
44960 | #define BIF_CFG_DEV2_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
44961 | #define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
44962 | #define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
44963 | #define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
44964 | #define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
44965 | #define BIF_CFG_DEV2_EPF2_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
44966 | #define BIF_CFG_DEV2_EPF2_0_STATUS__INT_STATUS_MASK 0x0008L |
44967 | #define BIF_CFG_DEV2_EPF2_0_STATUS__CAP_LIST_MASK 0x0010L |
44968 | #define BIF_CFG_DEV2_EPF2_0_STATUS__PCI_66_CAP_MASK 0x0020L |
44969 | #define BIF_CFG_DEV2_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
44970 | #define BIF_CFG_DEV2_EPF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
44971 | #define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
44972 | #define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
44973 | #define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
44974 | #define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
44975 | //BIF_CFG_DEV2_EPF2_0_REVISION_ID |
44976 | #define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
44977 | #define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
44978 | #define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
44979 | #define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
44980 | //BIF_CFG_DEV2_EPF2_0_PROG_INTERFACE |
44981 | #define BIF_CFG_DEV2_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
44982 | #define BIF_CFG_DEV2_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
44983 | //BIF_CFG_DEV2_EPF2_0_SUB_CLASS |
44984 | #define BIF_CFG_DEV2_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
44985 | #define BIF_CFG_DEV2_EPF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
44986 | //BIF_CFG_DEV2_EPF2_0_BASE_CLASS |
44987 | #define BIF_CFG_DEV2_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
44988 | #define BIF_CFG_DEV2_EPF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
44989 | //BIF_CFG_DEV2_EPF2_0_CACHE_LINE |
44990 | #define BIF_CFG_DEV2_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
44991 | #define BIF_CFG_DEV2_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
44992 | //BIF_CFG_DEV2_EPF2_0_LATENCY |
44993 | #define BIF_CFG_DEV2_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
44994 | #define BIF_CFG_DEV2_EPF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
44995 | //BIF_CFG_DEV2_EPF2_0_HEADER |
44996 | #define 0x0 |
44997 | #define 0x7 |
44998 | #define 0x7FL |
44999 | #define 0x80L |
45000 | //BIF_CFG_DEV2_EPF2_0_BIST |
45001 | #define BIF_CFG_DEV2_EPF2_0_BIST__BIST_COMP__SHIFT 0x0 |
45002 | #define BIF_CFG_DEV2_EPF2_0_BIST__BIST_STRT__SHIFT 0x6 |
45003 | #define BIF_CFG_DEV2_EPF2_0_BIST__BIST_CAP__SHIFT 0x7 |
45004 | #define BIF_CFG_DEV2_EPF2_0_BIST__BIST_COMP_MASK 0x0FL |
45005 | #define BIF_CFG_DEV2_EPF2_0_BIST__BIST_STRT_MASK 0x40L |
45006 | #define BIF_CFG_DEV2_EPF2_0_BIST__BIST_CAP_MASK 0x80L |
45007 | //BIF_CFG_DEV2_EPF2_0_BASE_ADDR_1 |
45008 | #define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
45009 | #define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
45010 | //BIF_CFG_DEV2_EPF2_0_BASE_ADDR_2 |
45011 | #define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
45012 | #define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
45013 | //BIF_CFG_DEV2_EPF2_0_BASE_ADDR_3 |
45014 | #define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
45015 | #define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
45016 | //BIF_CFG_DEV2_EPF2_0_BASE_ADDR_4 |
45017 | #define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
45018 | #define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
45019 | //BIF_CFG_DEV2_EPF2_0_BASE_ADDR_5 |
45020 | #define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
45021 | #define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
45022 | //BIF_CFG_DEV2_EPF2_0_BASE_ADDR_6 |
45023 | #define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
45024 | #define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
45025 | //BIF_CFG_DEV2_EPF2_0_ADAPTER_ID |
45026 | #define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
45027 | #define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
45028 | #define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
45029 | #define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
45030 | //BIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR |
45031 | #define BIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
45032 | #define BIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
45033 | //BIF_CFG_DEV2_EPF2_0_CAP_PTR |
45034 | #define BIF_CFG_DEV2_EPF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
45035 | #define BIF_CFG_DEV2_EPF2_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
45036 | //BIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE |
45037 | #define BIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
45038 | #define BIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
45039 | //BIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN |
45040 | #define BIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
45041 | #define BIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
45042 | //BIF_CFG_DEV2_EPF2_0_MIN_GRANT |
45043 | #define BIF_CFG_DEV2_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
45044 | #define BIF_CFG_DEV2_EPF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
45045 | //BIF_CFG_DEV2_EPF2_0_MAX_LATENCY |
45046 | #define BIF_CFG_DEV2_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
45047 | #define BIF_CFG_DEV2_EPF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
45048 | //BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST |
45049 | #define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
45050 | #define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
45051 | #define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
45052 | #define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
45053 | #define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
45054 | #define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
45055 | //BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W |
45056 | #define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
45057 | #define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
45058 | #define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
45059 | #define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
45060 | //BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST |
45061 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
45062 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
45063 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
45064 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
45065 | //BIF_CFG_DEV2_EPF2_0_PMI_CAP |
45066 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__VERSION__SHIFT 0x0 |
45067 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
45068 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
45069 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
45070 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
45071 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
45072 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
45073 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
45074 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__VERSION_MASK 0x0007L |
45075 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
45076 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
45077 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
45078 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
45079 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
45080 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
45081 | #define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
45082 | //BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL |
45083 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
45084 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
45085 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
45086 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
45087 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
45088 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
45089 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
45090 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
45091 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
45092 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
45093 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
45094 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
45095 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
45096 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
45097 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
45098 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
45099 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
45100 | #define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
45101 | //BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST |
45102 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
45103 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
45104 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
45105 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
45106 | //BIF_CFG_DEV2_EPF2_0_PCIE_CAP |
45107 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__VERSION__SHIFT 0x0 |
45108 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
45109 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
45110 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
45111 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__VERSION_MASK 0x000FL |
45112 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
45113 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
45114 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
45115 | //BIF_CFG_DEV2_EPF2_0_DEVICE_CAP |
45116 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
45117 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
45118 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
45119 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
45120 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
45121 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
45122 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
45123 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
45124 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
45125 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
45126 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
45127 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
45128 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
45129 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
45130 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
45131 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
45132 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
45133 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
45134 | //BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL |
45135 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
45136 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
45137 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
45138 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
45139 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
45140 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
45141 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
45142 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
45143 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
45144 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
45145 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
45146 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
45147 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
45148 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
45149 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
45150 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
45151 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
45152 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
45153 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
45154 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
45155 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
45156 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
45157 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
45158 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
45159 | //BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS |
45160 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
45161 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
45162 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
45163 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
45164 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
45165 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
45166 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
45167 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
45168 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
45169 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
45170 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
45171 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
45172 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
45173 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
45174 | //BIF_CFG_DEV2_EPF2_0_LINK_CAP |
45175 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
45176 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
45177 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
45178 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
45179 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
45180 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
45181 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
45182 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
45183 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
45184 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
45185 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
45186 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
45187 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
45188 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
45189 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
45190 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
45191 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
45192 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
45193 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
45194 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
45195 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
45196 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
45197 | //BIF_CFG_DEV2_EPF2_0_LINK_CNTL |
45198 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
45199 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
45200 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
45201 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
45202 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
45203 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
45204 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
45205 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
45206 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
45207 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
45208 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
45209 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
45210 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
45211 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
45212 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
45213 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
45214 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
45215 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
45216 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
45217 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
45218 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
45219 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
45220 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
45221 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
45222 | //BIF_CFG_DEV2_EPF2_0_LINK_STATUS |
45223 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
45224 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
45225 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
45226 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
45227 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
45228 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
45229 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
45230 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
45231 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
45232 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
45233 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
45234 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
45235 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
45236 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
45237 | //BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2 |
45238 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
45239 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
45240 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
45241 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
45242 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
45243 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
45244 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
45245 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
45246 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
45247 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
45248 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
45249 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
45250 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
45251 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
45252 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
45253 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
45254 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
45255 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
45256 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
45257 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
45258 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
45259 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
45260 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
45261 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
45262 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
45263 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
45264 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
45265 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
45266 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
45267 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
45268 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
45269 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
45270 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
45271 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
45272 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
45273 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
45274 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
45275 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
45276 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
45277 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
45278 | //BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2 |
45279 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
45280 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
45281 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
45282 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
45283 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
45284 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
45285 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
45286 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
45287 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
45288 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
45289 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
45290 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
45291 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
45292 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
45293 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
45294 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
45295 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
45296 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
45297 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
45298 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
45299 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
45300 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
45301 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
45302 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
45303 | //BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2 |
45304 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
45305 | #define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
45306 | //BIF_CFG_DEV2_EPF2_0_LINK_CAP2 |
45307 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
45308 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
45309 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
45310 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
45311 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
45312 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
45313 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
45314 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
45315 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
45316 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
45317 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
45318 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
45319 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
45320 | #define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
45321 | //BIF_CFG_DEV2_EPF2_0_LINK_CNTL2 |
45322 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
45323 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
45324 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
45325 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
45326 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
45327 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
45328 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
45329 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
45330 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
45331 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
45332 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
45333 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
45334 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
45335 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
45336 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
45337 | #define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
45338 | //BIF_CFG_DEV2_EPF2_0_LINK_STATUS2 |
45339 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
45340 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
45341 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
45342 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
45343 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
45344 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
45345 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
45346 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
45347 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
45348 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
45349 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
45350 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
45351 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
45352 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
45353 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
45354 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
45355 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
45356 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
45357 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
45358 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
45359 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
45360 | #define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
45361 | //BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST |
45362 | #define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
45363 | #define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
45364 | #define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
45365 | #define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
45366 | //BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL |
45367 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
45368 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
45369 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
45370 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
45371 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
45372 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
45373 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
45374 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
45375 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
45376 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
45377 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
45378 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
45379 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
45380 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
45381 | //BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO |
45382 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
45383 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
45384 | //BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI |
45385 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
45386 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
45387 | //BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA |
45388 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
45389 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
45390 | //BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA |
45391 | #define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
45392 | #define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
45393 | //BIF_CFG_DEV2_EPF2_0_MSI_MASK |
45394 | #define BIF_CFG_DEV2_EPF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
45395 | #define BIF_CFG_DEV2_EPF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
45396 | //BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64 |
45397 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
45398 | #define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
45399 | //BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64 |
45400 | #define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
45401 | #define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
45402 | //BIF_CFG_DEV2_EPF2_0_MSI_MASK_64 |
45403 | #define BIF_CFG_DEV2_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
45404 | #define BIF_CFG_DEV2_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
45405 | //BIF_CFG_DEV2_EPF2_0_MSI_PENDING |
45406 | #define BIF_CFG_DEV2_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
45407 | #define BIF_CFG_DEV2_EPF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
45408 | //BIF_CFG_DEV2_EPF2_0_MSI_PENDING_64 |
45409 | #define BIF_CFG_DEV2_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
45410 | #define BIF_CFG_DEV2_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
45411 | //BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST |
45412 | #define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
45413 | #define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
45414 | #define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
45415 | #define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
45416 | //BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL |
45417 | #define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
45418 | #define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
45419 | #define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
45420 | #define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
45421 | #define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
45422 | #define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
45423 | //BIF_CFG_DEV2_EPF2_0_MSIX_TABLE |
45424 | #define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
45425 | #define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
45426 | #define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
45427 | #define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
45428 | //BIF_CFG_DEV2_EPF2_0_MSIX_PBA |
45429 | #define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
45430 | #define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
45431 | #define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
45432 | #define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
45433 | //BIF_CFG_DEV2_EPF2_0_SATA_CAP_0 |
45434 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
45435 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
45436 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
45437 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
45438 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
45439 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
45440 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
45441 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
45442 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
45443 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
45444 | //BIF_CFG_DEV2_EPF2_0_SATA_CAP_1 |
45445 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
45446 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
45447 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
45448 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
45449 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
45450 | #define BIF_CFG_DEV2_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
45451 | //BIF_CFG_DEV2_EPF2_0_SATA_IDP_INDEX |
45452 | #define BIF_CFG_DEV2_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
45453 | #define BIF_CFG_DEV2_EPF2_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
45454 | #define BIF_CFG_DEV2_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
45455 | #define BIF_CFG_DEV2_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
45456 | #define BIF_CFG_DEV2_EPF2_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
45457 | #define BIF_CFG_DEV2_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
45458 | //BIF_CFG_DEV2_EPF2_0_SATA_IDP_DATA |
45459 | #define BIF_CFG_DEV2_EPF2_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
45460 | #define BIF_CFG_DEV2_EPF2_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
45461 | //BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
45462 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45463 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45464 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45465 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45466 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45467 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45468 | //BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR |
45469 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
45470 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
45471 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
45472 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
45473 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
45474 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
45475 | //BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1 |
45476 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
45477 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
45478 | //BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2 |
45479 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
45480 | #define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
45481 | //BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
45482 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45483 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45484 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45485 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45486 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45487 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45488 | //BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS |
45489 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
45490 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
45491 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
45492 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
45493 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
45494 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
45495 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
45496 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
45497 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
45498 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
45499 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
45500 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
45501 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
45502 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
45503 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
45504 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
45505 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
45506 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
45507 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
45508 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
45509 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
45510 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
45511 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
45512 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
45513 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
45514 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
45515 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
45516 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
45517 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
45518 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
45519 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
45520 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
45521 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
45522 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
45523 | //BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK |
45524 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
45525 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
45526 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
45527 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
45528 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
45529 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
45530 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
45531 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
45532 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
45533 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
45534 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
45535 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
45536 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
45537 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
45538 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
45539 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
45540 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
45541 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
45542 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
45543 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
45544 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
45545 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
45546 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
45547 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
45548 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
45549 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
45550 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
45551 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
45552 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
45553 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
45554 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
45555 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
45556 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
45557 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
45558 | //BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY |
45559 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
45560 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
45561 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
45562 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
45563 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
45564 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
45565 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
45566 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
45567 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
45568 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
45569 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
45570 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
45571 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
45572 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
45573 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
45574 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
45575 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
45576 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
45577 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
45578 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
45579 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
45580 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
45581 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
45582 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
45583 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
45584 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
45585 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
45586 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
45587 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
45588 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
45589 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
45590 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
45591 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
45592 | #define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
45593 | //BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS |
45594 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
45595 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
45596 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
45597 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
45598 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
45599 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
45600 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
45601 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
45602 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
45603 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
45604 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
45605 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
45606 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
45607 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
45608 | //BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK |
45609 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
45610 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
45611 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
45612 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
45613 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
45614 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
45615 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
45616 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
45617 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
45618 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
45619 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
45620 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
45621 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
45622 | #define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
45623 | //BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL |
45624 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
45625 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
45626 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
45627 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
45628 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
45629 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
45630 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
45631 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
45632 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
45633 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
45634 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
45635 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
45636 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
45637 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
45638 | //BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0 |
45639 | #define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
45640 | #define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
45641 | //BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1 |
45642 | #define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
45643 | #define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
45644 | //BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2 |
45645 | #define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
45646 | #define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
45647 | //BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3 |
45648 | #define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
45649 | #define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
45650 | //BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0 |
45651 | #define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
45652 | #define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
45653 | //BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1 |
45654 | #define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
45655 | #define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
45656 | //BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2 |
45657 | #define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
45658 | #define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
45659 | //BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3 |
45660 | #define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
45661 | #define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
45662 | //BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST |
45663 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45664 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45665 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45666 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45667 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45668 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45669 | //BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP |
45670 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
45671 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
45672 | //BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL |
45673 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
45674 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
45675 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
45676 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
45677 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
45678 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
45679 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
45680 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
45681 | //BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP |
45682 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
45683 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
45684 | //BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL |
45685 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
45686 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
45687 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
45688 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
45689 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
45690 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
45691 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
45692 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
45693 | //BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP |
45694 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
45695 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
45696 | //BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL |
45697 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
45698 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
45699 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
45700 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
45701 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
45702 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
45703 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
45704 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
45705 | //BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP |
45706 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
45707 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
45708 | //BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL |
45709 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
45710 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
45711 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
45712 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
45713 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
45714 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
45715 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
45716 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
45717 | //BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP |
45718 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
45719 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
45720 | //BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL |
45721 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
45722 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
45723 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
45724 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
45725 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
45726 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
45727 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
45728 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
45729 | //BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP |
45730 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
45731 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
45732 | //BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL |
45733 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
45734 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
45735 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
45736 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
45737 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
45738 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
45739 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
45740 | #define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
45741 | //BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
45742 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45743 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45744 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45745 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45746 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45747 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45748 | //BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT |
45749 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
45750 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
45751 | //BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA |
45752 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
45753 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
45754 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
45755 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
45756 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
45757 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
45758 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
45759 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
45760 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
45761 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
45762 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
45763 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
45764 | //BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP |
45765 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
45766 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
45767 | //BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST |
45768 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45769 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45770 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45771 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45772 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45773 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45774 | //BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP |
45775 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
45776 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
45777 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
45778 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
45779 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
45780 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
45781 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
45782 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
45783 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
45784 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
45785 | //BIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR |
45786 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
45787 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
45788 | //BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS |
45789 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
45790 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
45791 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
45792 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
45793 | //BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL |
45794 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
45795 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
45796 | //BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
45797 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45798 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45799 | //BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
45800 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45801 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45802 | //BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
45803 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45804 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45805 | //BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
45806 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45807 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45808 | //BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
45809 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45810 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45811 | //BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
45812 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45813 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45814 | //BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
45815 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45816 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45817 | //BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
45818 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
45819 | #define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
45820 | //BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST |
45821 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45822 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45823 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45824 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45825 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45826 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45827 | //BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP |
45828 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
45829 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
45830 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
45831 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
45832 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
45833 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
45834 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
45835 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
45836 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
45837 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
45838 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
45839 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
45840 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
45841 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
45842 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
45843 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
45844 | //BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL |
45845 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
45846 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
45847 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
45848 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
45849 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
45850 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
45851 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
45852 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
45853 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
45854 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
45855 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
45856 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
45857 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
45858 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
45859 | //BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST |
45860 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45861 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45862 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45863 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45864 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45865 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45866 | //BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP |
45867 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
45868 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
45869 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
45870 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
45871 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
45872 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
45873 | //BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL |
45874 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
45875 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
45876 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
45877 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
45878 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
45879 | #define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
45880 | //BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST |
45881 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45882 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45883 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45884 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45885 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45886 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45887 | //BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP |
45888 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
45889 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
45890 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
45891 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
45892 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
45893 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
45894 | //BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL |
45895 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
45896 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
45897 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
45898 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
45899 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
45900 | #define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
45901 | //BIF_CFG_DEV2_EPF2_0_PCIE_RTR_ENH_CAP_LIST |
45902 | #define BIF_CFG_DEV2_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
45903 | #define BIF_CFG_DEV2_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
45904 | #define BIF_CFG_DEV2_EPF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
45905 | #define BIF_CFG_DEV2_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
45906 | #define BIF_CFG_DEV2_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
45907 | #define BIF_CFG_DEV2_EPF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
45908 | //BIF_CFG_DEV2_EPF2_0_RTR_DATA1 |
45909 | #define BIF_CFG_DEV2_EPF2_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
45910 | #define BIF_CFG_DEV2_EPF2_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
45911 | #define BIF_CFG_DEV2_EPF2_0_RTR_DATA1__VALID__SHIFT 0x1f |
45912 | #define BIF_CFG_DEV2_EPF2_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
45913 | #define BIF_CFG_DEV2_EPF2_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
45914 | #define BIF_CFG_DEV2_EPF2_0_RTR_DATA1__VALID_MASK 0x80000000L |
45915 | //BIF_CFG_DEV2_EPF2_0_RTR_DATA2 |
45916 | #define BIF_CFG_DEV2_EPF2_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
45917 | #define BIF_CFG_DEV2_EPF2_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
45918 | #define BIF_CFG_DEV2_EPF2_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
45919 | #define BIF_CFG_DEV2_EPF2_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
45920 | |
45921 | |
45922 | // addressBlock: nbio_nbif0_bif_cfg_dev2_epf3_bifcfgdecp |
45923 | //BIF_CFG_DEV2_EPF3_0_VENDOR_ID |
45924 | #define BIF_CFG_DEV2_EPF3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
45925 | #define BIF_CFG_DEV2_EPF3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
45926 | //BIF_CFG_DEV2_EPF3_0_DEVICE_ID |
45927 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
45928 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
45929 | //BIF_CFG_DEV2_EPF3_0_COMMAND |
45930 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
45931 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
45932 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
45933 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
45934 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
45935 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
45936 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
45937 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__SERR_EN__SHIFT 0x8 |
45938 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
45939 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__INT_DIS__SHIFT 0xa |
45940 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
45941 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
45942 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
45943 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
45944 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
45945 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
45946 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__AD_STEPPING_MASK 0x0080L |
45947 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__SERR_EN_MASK 0x0100L |
45948 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
45949 | #define BIF_CFG_DEV2_EPF3_0_COMMAND__INT_DIS_MASK 0x0400L |
45950 | //BIF_CFG_DEV2_EPF3_0_STATUS |
45951 | #define BIF_CFG_DEV2_EPF3_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
45952 | #define BIF_CFG_DEV2_EPF3_0_STATUS__INT_STATUS__SHIFT 0x3 |
45953 | #define BIF_CFG_DEV2_EPF3_0_STATUS__CAP_LIST__SHIFT 0x4 |
45954 | #define BIF_CFG_DEV2_EPF3_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
45955 | #define BIF_CFG_DEV2_EPF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
45956 | #define BIF_CFG_DEV2_EPF3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
45957 | #define BIF_CFG_DEV2_EPF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
45958 | #define BIF_CFG_DEV2_EPF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
45959 | #define BIF_CFG_DEV2_EPF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
45960 | #define BIF_CFG_DEV2_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
45961 | #define BIF_CFG_DEV2_EPF3_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
45962 | #define BIF_CFG_DEV2_EPF3_0_STATUS__INT_STATUS_MASK 0x0008L |
45963 | #define BIF_CFG_DEV2_EPF3_0_STATUS__CAP_LIST_MASK 0x0010L |
45964 | #define BIF_CFG_DEV2_EPF3_0_STATUS__PCI_66_CAP_MASK 0x0020L |
45965 | #define BIF_CFG_DEV2_EPF3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
45966 | #define BIF_CFG_DEV2_EPF3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
45967 | #define BIF_CFG_DEV2_EPF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
45968 | #define BIF_CFG_DEV2_EPF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
45969 | #define BIF_CFG_DEV2_EPF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
45970 | #define BIF_CFG_DEV2_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
45971 | //BIF_CFG_DEV2_EPF3_0_REVISION_ID |
45972 | #define BIF_CFG_DEV2_EPF3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
45973 | #define BIF_CFG_DEV2_EPF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
45974 | #define BIF_CFG_DEV2_EPF3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
45975 | #define BIF_CFG_DEV2_EPF3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
45976 | //BIF_CFG_DEV2_EPF3_0_PROG_INTERFACE |
45977 | #define BIF_CFG_DEV2_EPF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
45978 | #define BIF_CFG_DEV2_EPF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
45979 | //BIF_CFG_DEV2_EPF3_0_SUB_CLASS |
45980 | #define BIF_CFG_DEV2_EPF3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
45981 | #define BIF_CFG_DEV2_EPF3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
45982 | //BIF_CFG_DEV2_EPF3_0_BASE_CLASS |
45983 | #define BIF_CFG_DEV2_EPF3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
45984 | #define BIF_CFG_DEV2_EPF3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
45985 | //BIF_CFG_DEV2_EPF3_0_CACHE_LINE |
45986 | #define BIF_CFG_DEV2_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
45987 | #define BIF_CFG_DEV2_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
45988 | //BIF_CFG_DEV2_EPF3_0_LATENCY |
45989 | #define BIF_CFG_DEV2_EPF3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
45990 | #define BIF_CFG_DEV2_EPF3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
45991 | //BIF_CFG_DEV2_EPF3_0_HEADER |
45992 | #define 0x0 |
45993 | #define 0x7 |
45994 | #define 0x7FL |
45995 | #define 0x80L |
45996 | //BIF_CFG_DEV2_EPF3_0_BIST |
45997 | #define BIF_CFG_DEV2_EPF3_0_BIST__BIST_COMP__SHIFT 0x0 |
45998 | #define BIF_CFG_DEV2_EPF3_0_BIST__BIST_STRT__SHIFT 0x6 |
45999 | #define BIF_CFG_DEV2_EPF3_0_BIST__BIST_CAP__SHIFT 0x7 |
46000 | #define BIF_CFG_DEV2_EPF3_0_BIST__BIST_COMP_MASK 0x0FL |
46001 | #define BIF_CFG_DEV2_EPF3_0_BIST__BIST_STRT_MASK 0x40L |
46002 | #define BIF_CFG_DEV2_EPF3_0_BIST__BIST_CAP_MASK 0x80L |
46003 | //BIF_CFG_DEV2_EPF3_0_BASE_ADDR_1 |
46004 | #define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
46005 | #define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
46006 | //BIF_CFG_DEV2_EPF3_0_BASE_ADDR_2 |
46007 | #define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
46008 | #define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
46009 | //BIF_CFG_DEV2_EPF3_0_BASE_ADDR_3 |
46010 | #define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
46011 | #define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
46012 | //BIF_CFG_DEV2_EPF3_0_BASE_ADDR_4 |
46013 | #define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
46014 | #define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
46015 | //BIF_CFG_DEV2_EPF3_0_BASE_ADDR_5 |
46016 | #define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
46017 | #define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
46018 | //BIF_CFG_DEV2_EPF3_0_BASE_ADDR_6 |
46019 | #define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
46020 | #define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
46021 | //BIF_CFG_DEV2_EPF3_0_ADAPTER_ID |
46022 | #define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
46023 | #define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
46024 | #define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
46025 | #define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
46026 | //BIF_CFG_DEV2_EPF3_0_ROM_BASE_ADDR |
46027 | #define BIF_CFG_DEV2_EPF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
46028 | #define BIF_CFG_DEV2_EPF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
46029 | //BIF_CFG_DEV2_EPF3_0_CAP_PTR |
46030 | #define BIF_CFG_DEV2_EPF3_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
46031 | #define BIF_CFG_DEV2_EPF3_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
46032 | //BIF_CFG_DEV2_EPF3_0_INTERRUPT_LINE |
46033 | #define BIF_CFG_DEV2_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
46034 | #define BIF_CFG_DEV2_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
46035 | //BIF_CFG_DEV2_EPF3_0_INTERRUPT_PIN |
46036 | #define BIF_CFG_DEV2_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
46037 | #define BIF_CFG_DEV2_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
46038 | //BIF_CFG_DEV2_EPF3_0_MIN_GRANT |
46039 | #define BIF_CFG_DEV2_EPF3_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
46040 | #define BIF_CFG_DEV2_EPF3_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
46041 | //BIF_CFG_DEV2_EPF3_0_MAX_LATENCY |
46042 | #define BIF_CFG_DEV2_EPF3_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
46043 | #define BIF_CFG_DEV2_EPF3_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
46044 | //BIF_CFG_DEV2_EPF3_0_VENDOR_CAP_LIST |
46045 | #define BIF_CFG_DEV2_EPF3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
46046 | #define BIF_CFG_DEV2_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
46047 | #define BIF_CFG_DEV2_EPF3_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
46048 | #define BIF_CFG_DEV2_EPF3_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
46049 | #define BIF_CFG_DEV2_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
46050 | #define BIF_CFG_DEV2_EPF3_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
46051 | //BIF_CFG_DEV2_EPF3_0_ADAPTER_ID_W |
46052 | #define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
46053 | #define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
46054 | #define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
46055 | #define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
46056 | //BIF_CFG_DEV2_EPF3_0_PMI_CAP_LIST |
46057 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
46058 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
46059 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
46060 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
46061 | //BIF_CFG_DEV2_EPF3_0_PMI_CAP |
46062 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__VERSION__SHIFT 0x0 |
46063 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
46064 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
46065 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
46066 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
46067 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
46068 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
46069 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
46070 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__VERSION_MASK 0x0007L |
46071 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
46072 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
46073 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
46074 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
46075 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
46076 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
46077 | #define BIF_CFG_DEV2_EPF3_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
46078 | //BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL |
46079 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
46080 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
46081 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
46082 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
46083 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
46084 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
46085 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
46086 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
46087 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
46088 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
46089 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
46090 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
46091 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
46092 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
46093 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
46094 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
46095 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
46096 | #define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
46097 | //BIF_CFG_DEV2_EPF3_0_SBRN |
46098 | #define BIF_CFG_DEV2_EPF3_0_SBRN__SBRN__SHIFT 0x0 |
46099 | #define BIF_CFG_DEV2_EPF3_0_SBRN__SBRN_MASK 0xFFL |
46100 | //BIF_CFG_DEV2_EPF3_0_FLADJ |
46101 | #define BIF_CFG_DEV2_EPF3_0_FLADJ__FLADJ__SHIFT 0x0 |
46102 | #define BIF_CFG_DEV2_EPF3_0_FLADJ__NFC__SHIFT 0x6 |
46103 | #define BIF_CFG_DEV2_EPF3_0_FLADJ__FLADJ_MASK 0x3FL |
46104 | #define BIF_CFG_DEV2_EPF3_0_FLADJ__NFC_MASK 0x40L |
46105 | //BIF_CFG_DEV2_EPF3_0_DBESL_DBESLD |
46106 | #define BIF_CFG_DEV2_EPF3_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
46107 | #define BIF_CFG_DEV2_EPF3_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
46108 | #define BIF_CFG_DEV2_EPF3_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
46109 | #define BIF_CFG_DEV2_EPF3_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
46110 | //BIF_CFG_DEV2_EPF3_0_PCIE_CAP_LIST |
46111 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
46112 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
46113 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
46114 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
46115 | //BIF_CFG_DEV2_EPF3_0_PCIE_CAP |
46116 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__VERSION__SHIFT 0x0 |
46117 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
46118 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
46119 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
46120 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__VERSION_MASK 0x000FL |
46121 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
46122 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
46123 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
46124 | //BIF_CFG_DEV2_EPF3_0_DEVICE_CAP |
46125 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
46126 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
46127 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
46128 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
46129 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
46130 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
46131 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
46132 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
46133 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
46134 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
46135 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
46136 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
46137 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
46138 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
46139 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
46140 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
46141 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
46142 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
46143 | //BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL |
46144 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
46145 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
46146 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
46147 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
46148 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
46149 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
46150 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
46151 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
46152 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
46153 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
46154 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
46155 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
46156 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
46157 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
46158 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
46159 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
46160 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
46161 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
46162 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
46163 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
46164 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
46165 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
46166 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
46167 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
46168 | //BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS |
46169 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
46170 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
46171 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
46172 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
46173 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
46174 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
46175 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
46176 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
46177 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
46178 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
46179 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
46180 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
46181 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
46182 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
46183 | //BIF_CFG_DEV2_EPF3_0_LINK_CAP |
46184 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
46185 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
46186 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
46187 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
46188 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
46189 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
46190 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
46191 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
46192 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
46193 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
46194 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
46195 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
46196 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
46197 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
46198 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
46199 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
46200 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
46201 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
46202 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
46203 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
46204 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
46205 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
46206 | //BIF_CFG_DEV2_EPF3_0_LINK_CNTL |
46207 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
46208 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
46209 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
46210 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
46211 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
46212 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
46213 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
46214 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
46215 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
46216 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
46217 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
46218 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
46219 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
46220 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
46221 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
46222 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
46223 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
46224 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
46225 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
46226 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
46227 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
46228 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
46229 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
46230 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
46231 | //BIF_CFG_DEV2_EPF3_0_LINK_STATUS |
46232 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
46233 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
46234 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
46235 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
46236 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
46237 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
46238 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
46239 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
46240 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
46241 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
46242 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
46243 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
46244 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
46245 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
46246 | //BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2 |
46247 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
46248 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
46249 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
46250 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
46251 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
46252 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
46253 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
46254 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
46255 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
46256 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
46257 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
46258 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
46259 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
46260 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
46261 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
46262 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
46263 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
46264 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
46265 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
46266 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
46267 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
46268 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
46269 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
46270 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
46271 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
46272 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
46273 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
46274 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
46275 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
46276 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
46277 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
46278 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
46279 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
46280 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
46281 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
46282 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
46283 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
46284 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
46285 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
46286 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
46287 | //BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2 |
46288 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
46289 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
46290 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
46291 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
46292 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
46293 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
46294 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
46295 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
46296 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
46297 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
46298 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
46299 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
46300 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
46301 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
46302 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
46303 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
46304 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
46305 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
46306 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
46307 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
46308 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
46309 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
46310 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
46311 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
46312 | //BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS2 |
46313 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
46314 | #define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
46315 | //BIF_CFG_DEV2_EPF3_0_LINK_CAP2 |
46316 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
46317 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
46318 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
46319 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
46320 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
46321 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
46322 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
46323 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
46324 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
46325 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
46326 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
46327 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
46328 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
46329 | #define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
46330 | //BIF_CFG_DEV2_EPF3_0_LINK_CNTL2 |
46331 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
46332 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
46333 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
46334 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
46335 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
46336 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
46337 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
46338 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
46339 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
46340 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
46341 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
46342 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
46343 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
46344 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
46345 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
46346 | #define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
46347 | //BIF_CFG_DEV2_EPF3_0_LINK_STATUS2 |
46348 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
46349 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
46350 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
46351 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
46352 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
46353 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
46354 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
46355 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
46356 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
46357 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
46358 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
46359 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
46360 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
46361 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
46362 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
46363 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
46364 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
46365 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
46366 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
46367 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
46368 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
46369 | #define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
46370 | //BIF_CFG_DEV2_EPF3_0_MSI_CAP_LIST |
46371 | #define BIF_CFG_DEV2_EPF3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
46372 | #define BIF_CFG_DEV2_EPF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
46373 | #define BIF_CFG_DEV2_EPF3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
46374 | #define BIF_CFG_DEV2_EPF3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
46375 | //BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL |
46376 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
46377 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
46378 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
46379 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
46380 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
46381 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
46382 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
46383 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
46384 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
46385 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
46386 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
46387 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
46388 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
46389 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
46390 | //BIF_CFG_DEV2_EPF3_0_MSI_MSG_ADDR_LO |
46391 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
46392 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
46393 | //BIF_CFG_DEV2_EPF3_0_MSI_MSG_ADDR_HI |
46394 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
46395 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
46396 | //BIF_CFG_DEV2_EPF3_0_MSI_MSG_DATA |
46397 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
46398 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
46399 | //BIF_CFG_DEV2_EPF3_0_MSI_EXT_MSG_DATA |
46400 | #define BIF_CFG_DEV2_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
46401 | #define BIF_CFG_DEV2_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
46402 | //BIF_CFG_DEV2_EPF3_0_MSI_MASK |
46403 | #define BIF_CFG_DEV2_EPF3_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
46404 | #define BIF_CFG_DEV2_EPF3_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
46405 | //BIF_CFG_DEV2_EPF3_0_MSI_MSG_DATA_64 |
46406 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
46407 | #define BIF_CFG_DEV2_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
46408 | //BIF_CFG_DEV2_EPF3_0_MSI_EXT_MSG_DATA_64 |
46409 | #define BIF_CFG_DEV2_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
46410 | #define BIF_CFG_DEV2_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
46411 | //BIF_CFG_DEV2_EPF3_0_MSI_MASK_64 |
46412 | #define BIF_CFG_DEV2_EPF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
46413 | #define BIF_CFG_DEV2_EPF3_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
46414 | //BIF_CFG_DEV2_EPF3_0_MSI_PENDING |
46415 | #define BIF_CFG_DEV2_EPF3_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
46416 | #define BIF_CFG_DEV2_EPF3_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
46417 | //BIF_CFG_DEV2_EPF3_0_MSI_PENDING_64 |
46418 | #define BIF_CFG_DEV2_EPF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
46419 | #define BIF_CFG_DEV2_EPF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
46420 | //BIF_CFG_DEV2_EPF3_0_MSIX_CAP_LIST |
46421 | #define BIF_CFG_DEV2_EPF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
46422 | #define BIF_CFG_DEV2_EPF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
46423 | #define BIF_CFG_DEV2_EPF3_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
46424 | #define BIF_CFG_DEV2_EPF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
46425 | //BIF_CFG_DEV2_EPF3_0_MSIX_MSG_CNTL |
46426 | #define BIF_CFG_DEV2_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
46427 | #define BIF_CFG_DEV2_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
46428 | #define BIF_CFG_DEV2_EPF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
46429 | #define BIF_CFG_DEV2_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
46430 | #define BIF_CFG_DEV2_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
46431 | #define BIF_CFG_DEV2_EPF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
46432 | //BIF_CFG_DEV2_EPF3_0_MSIX_TABLE |
46433 | #define BIF_CFG_DEV2_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
46434 | #define BIF_CFG_DEV2_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
46435 | #define BIF_CFG_DEV2_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
46436 | #define BIF_CFG_DEV2_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
46437 | //BIF_CFG_DEV2_EPF3_0_MSIX_PBA |
46438 | #define BIF_CFG_DEV2_EPF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
46439 | #define BIF_CFG_DEV2_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
46440 | #define BIF_CFG_DEV2_EPF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
46441 | #define BIF_CFG_DEV2_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
46442 | //BIF_CFG_DEV2_EPF3_0_SATA_CAP_0 |
46443 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
46444 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
46445 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
46446 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
46447 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
46448 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
46449 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
46450 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
46451 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
46452 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
46453 | //BIF_CFG_DEV2_EPF3_0_SATA_CAP_1 |
46454 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
46455 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
46456 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
46457 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
46458 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
46459 | #define BIF_CFG_DEV2_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
46460 | //BIF_CFG_DEV2_EPF3_0_SATA_IDP_INDEX |
46461 | #define BIF_CFG_DEV2_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
46462 | #define BIF_CFG_DEV2_EPF3_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
46463 | #define BIF_CFG_DEV2_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
46464 | #define BIF_CFG_DEV2_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
46465 | #define BIF_CFG_DEV2_EPF3_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
46466 | #define BIF_CFG_DEV2_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
46467 | //BIF_CFG_DEV2_EPF3_0_SATA_IDP_DATA |
46468 | #define BIF_CFG_DEV2_EPF3_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
46469 | #define BIF_CFG_DEV2_EPF3_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
46470 | //BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
46471 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46472 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46473 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46474 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46475 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46476 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46477 | //BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR |
46478 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
46479 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
46480 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
46481 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
46482 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
46483 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
46484 | //BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC1 |
46485 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
46486 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
46487 | //BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC2 |
46488 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
46489 | #define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
46490 | //BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
46491 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46492 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46493 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46494 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46495 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46496 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46497 | //BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS |
46498 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
46499 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
46500 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
46501 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
46502 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
46503 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
46504 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
46505 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
46506 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
46507 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
46508 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
46509 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
46510 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
46511 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
46512 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
46513 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
46514 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
46515 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
46516 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
46517 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
46518 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
46519 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
46520 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
46521 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
46522 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
46523 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
46524 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
46525 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
46526 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
46527 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
46528 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
46529 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
46530 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
46531 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
46532 | //BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK |
46533 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
46534 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
46535 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
46536 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
46537 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
46538 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
46539 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
46540 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
46541 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
46542 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
46543 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
46544 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
46545 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
46546 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
46547 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
46548 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
46549 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
46550 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
46551 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
46552 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
46553 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
46554 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
46555 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
46556 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
46557 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
46558 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
46559 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
46560 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
46561 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
46562 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
46563 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
46564 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
46565 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
46566 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
46567 | //BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY |
46568 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
46569 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
46570 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
46571 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
46572 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
46573 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
46574 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
46575 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
46576 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
46577 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
46578 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
46579 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
46580 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
46581 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
46582 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
46583 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
46584 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
46585 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
46586 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
46587 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
46588 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
46589 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
46590 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
46591 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
46592 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
46593 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
46594 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
46595 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
46596 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
46597 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
46598 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
46599 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
46600 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
46601 | #define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
46602 | //BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS |
46603 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
46604 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
46605 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
46606 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
46607 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
46608 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
46609 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
46610 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
46611 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
46612 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
46613 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
46614 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
46615 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
46616 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
46617 | //BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK |
46618 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
46619 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
46620 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
46621 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
46622 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
46623 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
46624 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
46625 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
46626 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
46627 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
46628 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
46629 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
46630 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
46631 | #define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
46632 | //BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL |
46633 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
46634 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
46635 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
46636 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
46637 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
46638 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
46639 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
46640 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
46641 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
46642 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
46643 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
46644 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
46645 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
46646 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
46647 | //BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG0 |
46648 | #define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
46649 | #define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
46650 | //BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG1 |
46651 | #define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
46652 | #define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
46653 | //BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG2 |
46654 | #define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
46655 | #define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
46656 | //BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG3 |
46657 | #define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
46658 | #define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
46659 | //BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG0 |
46660 | #define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
46661 | #define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
46662 | //BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG1 |
46663 | #define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
46664 | #define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
46665 | //BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG2 |
46666 | #define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
46667 | #define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
46668 | //BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG3 |
46669 | #define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
46670 | #define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
46671 | //BIF_CFG_DEV2_EPF3_0_PCIE_BAR_ENH_CAP_LIST |
46672 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46673 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46674 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46675 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46676 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46677 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46678 | //BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CAP |
46679 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
46680 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
46681 | //BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL |
46682 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
46683 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
46684 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
46685 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
46686 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
46687 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
46688 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
46689 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
46690 | //BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CAP |
46691 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
46692 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
46693 | //BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL |
46694 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
46695 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
46696 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
46697 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
46698 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
46699 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
46700 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
46701 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
46702 | //BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CAP |
46703 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
46704 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
46705 | //BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL |
46706 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
46707 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
46708 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
46709 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
46710 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
46711 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
46712 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
46713 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
46714 | //BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CAP |
46715 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
46716 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
46717 | //BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL |
46718 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
46719 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
46720 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
46721 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
46722 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
46723 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
46724 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
46725 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
46726 | //BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CAP |
46727 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
46728 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
46729 | //BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL |
46730 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
46731 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
46732 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
46733 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
46734 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
46735 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
46736 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
46737 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
46738 | //BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CAP |
46739 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
46740 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
46741 | //BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL |
46742 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
46743 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
46744 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
46745 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
46746 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
46747 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
46748 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
46749 | #define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
46750 | //BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
46751 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46752 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46753 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46754 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46755 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46756 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46757 | //BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT |
46758 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
46759 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
46760 | //BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA |
46761 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
46762 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
46763 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
46764 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
46765 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
46766 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
46767 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
46768 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
46769 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
46770 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
46771 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
46772 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
46773 | //BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_CAP |
46774 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
46775 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
46776 | //BIF_CFG_DEV2_EPF3_0_PCIE_DPA_ENH_CAP_LIST |
46777 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46778 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46779 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46780 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46781 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46782 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46783 | //BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP |
46784 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
46785 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
46786 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
46787 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
46788 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
46789 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
46790 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
46791 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
46792 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
46793 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
46794 | //BIF_CFG_DEV2_EPF3_0_PCIE_DPA_LATENCY_INDICATOR |
46795 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
46796 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
46797 | //BIF_CFG_DEV2_EPF3_0_PCIE_DPA_STATUS |
46798 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
46799 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
46800 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
46801 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
46802 | //BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CNTL |
46803 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
46804 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
46805 | //BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
46806 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46807 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46808 | //BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
46809 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46810 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46811 | //BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
46812 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46813 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46814 | //BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
46815 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46816 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46817 | //BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
46818 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46819 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46820 | //BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
46821 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46822 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46823 | //BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
46824 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46825 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46826 | //BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
46827 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
46828 | #define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
46829 | //BIF_CFG_DEV2_EPF3_0_PCIE_ACS_ENH_CAP_LIST |
46830 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46831 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46832 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46833 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46834 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46835 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46836 | //BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP |
46837 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
46838 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
46839 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
46840 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
46841 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
46842 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
46843 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
46844 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
46845 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
46846 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
46847 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
46848 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
46849 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
46850 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
46851 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
46852 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
46853 | //BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL |
46854 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
46855 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
46856 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
46857 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
46858 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
46859 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
46860 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
46861 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
46862 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
46863 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
46864 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
46865 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
46866 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
46867 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
46868 | //BIF_CFG_DEV2_EPF3_0_PCIE_PASID_ENH_CAP_LIST |
46869 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46870 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46871 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46872 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46873 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46874 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46875 | //BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CAP |
46876 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
46877 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
46878 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
46879 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
46880 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
46881 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
46882 | //BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CNTL |
46883 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
46884 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
46885 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
46886 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
46887 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
46888 | #define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
46889 | //BIF_CFG_DEV2_EPF3_0_PCIE_ARI_ENH_CAP_LIST |
46890 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46891 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46892 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46893 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46894 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46895 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46896 | //BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CAP |
46897 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
46898 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
46899 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
46900 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
46901 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
46902 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
46903 | //BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CNTL |
46904 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
46905 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
46906 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
46907 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
46908 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
46909 | #define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
46910 | //BIF_CFG_DEV2_EPF3_0_PCIE_RTR_ENH_CAP_LIST |
46911 | #define BIF_CFG_DEV2_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
46912 | #define BIF_CFG_DEV2_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
46913 | #define BIF_CFG_DEV2_EPF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
46914 | #define BIF_CFG_DEV2_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
46915 | #define BIF_CFG_DEV2_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
46916 | #define BIF_CFG_DEV2_EPF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
46917 | //BIF_CFG_DEV2_EPF3_0_RTR_DATA1 |
46918 | #define BIF_CFG_DEV2_EPF3_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
46919 | #define BIF_CFG_DEV2_EPF3_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
46920 | #define BIF_CFG_DEV2_EPF3_0_RTR_DATA1__VALID__SHIFT 0x1f |
46921 | #define BIF_CFG_DEV2_EPF3_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
46922 | #define BIF_CFG_DEV2_EPF3_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
46923 | #define BIF_CFG_DEV2_EPF3_0_RTR_DATA1__VALID_MASK 0x80000000L |
46924 | //BIF_CFG_DEV2_EPF3_0_RTR_DATA2 |
46925 | #define BIF_CFG_DEV2_EPF3_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
46926 | #define BIF_CFG_DEV2_EPF3_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
46927 | #define BIF_CFG_DEV2_EPF3_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
46928 | #define BIF_CFG_DEV2_EPF3_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
46929 | |
46930 | |
46931 | // addressBlock: nbio_nbif0_bif_cfg_dev2_epf4_bifcfgdecp |
46932 | //BIF_CFG_DEV2_EPF4_0_VENDOR_ID |
46933 | #define BIF_CFG_DEV2_EPF4_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
46934 | #define BIF_CFG_DEV2_EPF4_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
46935 | //BIF_CFG_DEV2_EPF4_0_DEVICE_ID |
46936 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
46937 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
46938 | //BIF_CFG_DEV2_EPF4_0_COMMAND |
46939 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
46940 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
46941 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
46942 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
46943 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
46944 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
46945 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
46946 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__SERR_EN__SHIFT 0x8 |
46947 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
46948 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__INT_DIS__SHIFT 0xa |
46949 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
46950 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
46951 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
46952 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
46953 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
46954 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
46955 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__AD_STEPPING_MASK 0x0080L |
46956 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__SERR_EN_MASK 0x0100L |
46957 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
46958 | #define BIF_CFG_DEV2_EPF4_0_COMMAND__INT_DIS_MASK 0x0400L |
46959 | //BIF_CFG_DEV2_EPF4_0_STATUS |
46960 | #define BIF_CFG_DEV2_EPF4_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
46961 | #define BIF_CFG_DEV2_EPF4_0_STATUS__INT_STATUS__SHIFT 0x3 |
46962 | #define BIF_CFG_DEV2_EPF4_0_STATUS__CAP_LIST__SHIFT 0x4 |
46963 | #define BIF_CFG_DEV2_EPF4_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
46964 | #define BIF_CFG_DEV2_EPF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
46965 | #define BIF_CFG_DEV2_EPF4_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
46966 | #define BIF_CFG_DEV2_EPF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
46967 | #define BIF_CFG_DEV2_EPF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
46968 | #define BIF_CFG_DEV2_EPF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
46969 | #define BIF_CFG_DEV2_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
46970 | #define BIF_CFG_DEV2_EPF4_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
46971 | #define BIF_CFG_DEV2_EPF4_0_STATUS__INT_STATUS_MASK 0x0008L |
46972 | #define BIF_CFG_DEV2_EPF4_0_STATUS__CAP_LIST_MASK 0x0010L |
46973 | #define BIF_CFG_DEV2_EPF4_0_STATUS__PCI_66_CAP_MASK 0x0020L |
46974 | #define BIF_CFG_DEV2_EPF4_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
46975 | #define BIF_CFG_DEV2_EPF4_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
46976 | #define BIF_CFG_DEV2_EPF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
46977 | #define BIF_CFG_DEV2_EPF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
46978 | #define BIF_CFG_DEV2_EPF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
46979 | #define BIF_CFG_DEV2_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
46980 | //BIF_CFG_DEV2_EPF4_0_REVISION_ID |
46981 | #define BIF_CFG_DEV2_EPF4_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
46982 | #define BIF_CFG_DEV2_EPF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
46983 | #define BIF_CFG_DEV2_EPF4_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
46984 | #define BIF_CFG_DEV2_EPF4_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
46985 | //BIF_CFG_DEV2_EPF4_0_PROG_INTERFACE |
46986 | #define BIF_CFG_DEV2_EPF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
46987 | #define BIF_CFG_DEV2_EPF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
46988 | //BIF_CFG_DEV2_EPF4_0_SUB_CLASS |
46989 | #define BIF_CFG_DEV2_EPF4_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
46990 | #define BIF_CFG_DEV2_EPF4_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
46991 | //BIF_CFG_DEV2_EPF4_0_BASE_CLASS |
46992 | #define BIF_CFG_DEV2_EPF4_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
46993 | #define BIF_CFG_DEV2_EPF4_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
46994 | //BIF_CFG_DEV2_EPF4_0_CACHE_LINE |
46995 | #define BIF_CFG_DEV2_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
46996 | #define BIF_CFG_DEV2_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
46997 | //BIF_CFG_DEV2_EPF4_0_LATENCY |
46998 | #define BIF_CFG_DEV2_EPF4_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
46999 | #define BIF_CFG_DEV2_EPF4_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
47000 | //BIF_CFG_DEV2_EPF4_0_HEADER |
47001 | #define 0x0 |
47002 | #define 0x7 |
47003 | #define 0x7FL |
47004 | #define 0x80L |
47005 | //BIF_CFG_DEV2_EPF4_0_BIST |
47006 | #define BIF_CFG_DEV2_EPF4_0_BIST__BIST_COMP__SHIFT 0x0 |
47007 | #define BIF_CFG_DEV2_EPF4_0_BIST__BIST_STRT__SHIFT 0x6 |
47008 | #define BIF_CFG_DEV2_EPF4_0_BIST__BIST_CAP__SHIFT 0x7 |
47009 | #define BIF_CFG_DEV2_EPF4_0_BIST__BIST_COMP_MASK 0x0FL |
47010 | #define BIF_CFG_DEV2_EPF4_0_BIST__BIST_STRT_MASK 0x40L |
47011 | #define BIF_CFG_DEV2_EPF4_0_BIST__BIST_CAP_MASK 0x80L |
47012 | //BIF_CFG_DEV2_EPF4_0_BASE_ADDR_1 |
47013 | #define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
47014 | #define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
47015 | //BIF_CFG_DEV2_EPF4_0_BASE_ADDR_2 |
47016 | #define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
47017 | #define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
47018 | //BIF_CFG_DEV2_EPF4_0_BASE_ADDR_3 |
47019 | #define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
47020 | #define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
47021 | //BIF_CFG_DEV2_EPF4_0_BASE_ADDR_4 |
47022 | #define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
47023 | #define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
47024 | //BIF_CFG_DEV2_EPF4_0_BASE_ADDR_5 |
47025 | #define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
47026 | #define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
47027 | //BIF_CFG_DEV2_EPF4_0_BASE_ADDR_6 |
47028 | #define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
47029 | #define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
47030 | //BIF_CFG_DEV2_EPF4_0_ADAPTER_ID |
47031 | #define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
47032 | #define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
47033 | #define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
47034 | #define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
47035 | //BIF_CFG_DEV2_EPF4_0_ROM_BASE_ADDR |
47036 | #define BIF_CFG_DEV2_EPF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
47037 | #define BIF_CFG_DEV2_EPF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
47038 | //BIF_CFG_DEV2_EPF4_0_CAP_PTR |
47039 | #define BIF_CFG_DEV2_EPF4_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
47040 | #define BIF_CFG_DEV2_EPF4_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
47041 | //BIF_CFG_DEV2_EPF4_0_INTERRUPT_LINE |
47042 | #define BIF_CFG_DEV2_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
47043 | #define BIF_CFG_DEV2_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
47044 | //BIF_CFG_DEV2_EPF4_0_INTERRUPT_PIN |
47045 | #define BIF_CFG_DEV2_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
47046 | #define BIF_CFG_DEV2_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
47047 | //BIF_CFG_DEV2_EPF4_0_MIN_GRANT |
47048 | #define BIF_CFG_DEV2_EPF4_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
47049 | #define BIF_CFG_DEV2_EPF4_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
47050 | //BIF_CFG_DEV2_EPF4_0_MAX_LATENCY |
47051 | #define BIF_CFG_DEV2_EPF4_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
47052 | #define BIF_CFG_DEV2_EPF4_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
47053 | //BIF_CFG_DEV2_EPF4_0_VENDOR_CAP_LIST |
47054 | #define BIF_CFG_DEV2_EPF4_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
47055 | #define BIF_CFG_DEV2_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
47056 | #define BIF_CFG_DEV2_EPF4_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
47057 | #define BIF_CFG_DEV2_EPF4_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
47058 | #define BIF_CFG_DEV2_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
47059 | #define BIF_CFG_DEV2_EPF4_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
47060 | //BIF_CFG_DEV2_EPF4_0_ADAPTER_ID_W |
47061 | #define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
47062 | #define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
47063 | #define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
47064 | #define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
47065 | //BIF_CFG_DEV2_EPF4_0_PMI_CAP_LIST |
47066 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
47067 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
47068 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
47069 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
47070 | //BIF_CFG_DEV2_EPF4_0_PMI_CAP |
47071 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__VERSION__SHIFT 0x0 |
47072 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
47073 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
47074 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
47075 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
47076 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
47077 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
47078 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
47079 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__VERSION_MASK 0x0007L |
47080 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
47081 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
47082 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
47083 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
47084 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
47085 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
47086 | #define BIF_CFG_DEV2_EPF4_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
47087 | //BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL |
47088 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
47089 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
47090 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
47091 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
47092 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
47093 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
47094 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
47095 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
47096 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
47097 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
47098 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
47099 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
47100 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
47101 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
47102 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
47103 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
47104 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
47105 | #define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
47106 | //BIF_CFG_DEV2_EPF4_0_SBRN |
47107 | #define BIF_CFG_DEV2_EPF4_0_SBRN__SBRN__SHIFT 0x0 |
47108 | #define BIF_CFG_DEV2_EPF4_0_SBRN__SBRN_MASK 0xFFL |
47109 | //BIF_CFG_DEV2_EPF4_0_FLADJ |
47110 | #define BIF_CFG_DEV2_EPF4_0_FLADJ__FLADJ__SHIFT 0x0 |
47111 | #define BIF_CFG_DEV2_EPF4_0_FLADJ__NFC__SHIFT 0x6 |
47112 | #define BIF_CFG_DEV2_EPF4_0_FLADJ__FLADJ_MASK 0x3FL |
47113 | #define BIF_CFG_DEV2_EPF4_0_FLADJ__NFC_MASK 0x40L |
47114 | //BIF_CFG_DEV2_EPF4_0_DBESL_DBESLD |
47115 | #define BIF_CFG_DEV2_EPF4_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
47116 | #define BIF_CFG_DEV2_EPF4_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
47117 | #define BIF_CFG_DEV2_EPF4_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
47118 | #define BIF_CFG_DEV2_EPF4_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
47119 | //BIF_CFG_DEV2_EPF4_0_PCIE_CAP_LIST |
47120 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
47121 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
47122 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
47123 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
47124 | //BIF_CFG_DEV2_EPF4_0_PCIE_CAP |
47125 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__VERSION__SHIFT 0x0 |
47126 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
47127 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
47128 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
47129 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__VERSION_MASK 0x000FL |
47130 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
47131 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
47132 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
47133 | //BIF_CFG_DEV2_EPF4_0_DEVICE_CAP |
47134 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
47135 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
47136 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
47137 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
47138 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
47139 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
47140 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
47141 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
47142 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
47143 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
47144 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
47145 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
47146 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
47147 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
47148 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
47149 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
47150 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
47151 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
47152 | //BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL |
47153 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
47154 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
47155 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
47156 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
47157 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
47158 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
47159 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
47160 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
47161 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
47162 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
47163 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
47164 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
47165 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
47166 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
47167 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
47168 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
47169 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
47170 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
47171 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
47172 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
47173 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
47174 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
47175 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
47176 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
47177 | //BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS |
47178 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
47179 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
47180 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
47181 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
47182 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
47183 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
47184 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
47185 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
47186 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
47187 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
47188 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
47189 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
47190 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
47191 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
47192 | //BIF_CFG_DEV2_EPF4_0_LINK_CAP |
47193 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
47194 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
47195 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
47196 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
47197 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
47198 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
47199 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
47200 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
47201 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
47202 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
47203 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
47204 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
47205 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
47206 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
47207 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
47208 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
47209 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
47210 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
47211 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
47212 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
47213 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
47214 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
47215 | //BIF_CFG_DEV2_EPF4_0_LINK_CNTL |
47216 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
47217 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
47218 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
47219 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
47220 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
47221 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
47222 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
47223 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
47224 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
47225 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
47226 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
47227 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
47228 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
47229 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
47230 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
47231 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
47232 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
47233 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
47234 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
47235 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
47236 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
47237 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
47238 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
47239 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
47240 | //BIF_CFG_DEV2_EPF4_0_LINK_STATUS |
47241 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
47242 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
47243 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
47244 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
47245 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
47246 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
47247 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
47248 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
47249 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
47250 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
47251 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
47252 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
47253 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
47254 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
47255 | //BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2 |
47256 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
47257 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
47258 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
47259 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
47260 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
47261 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
47262 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
47263 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
47264 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
47265 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
47266 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
47267 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
47268 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
47269 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
47270 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
47271 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
47272 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
47273 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
47274 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
47275 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
47276 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
47277 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
47278 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
47279 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
47280 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
47281 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
47282 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
47283 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
47284 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
47285 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
47286 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
47287 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
47288 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
47289 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
47290 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
47291 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
47292 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
47293 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
47294 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
47295 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
47296 | //BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2 |
47297 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
47298 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
47299 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
47300 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
47301 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
47302 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
47303 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
47304 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
47305 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
47306 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
47307 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
47308 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
47309 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
47310 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
47311 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
47312 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
47313 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
47314 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
47315 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
47316 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
47317 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
47318 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
47319 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
47320 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
47321 | //BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS2 |
47322 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
47323 | #define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
47324 | //BIF_CFG_DEV2_EPF4_0_LINK_CAP2 |
47325 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
47326 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
47327 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
47328 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
47329 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
47330 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
47331 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
47332 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
47333 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
47334 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
47335 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
47336 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
47337 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
47338 | #define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
47339 | //BIF_CFG_DEV2_EPF4_0_LINK_CNTL2 |
47340 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
47341 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
47342 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
47343 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
47344 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
47345 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
47346 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
47347 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
47348 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
47349 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
47350 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
47351 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
47352 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
47353 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
47354 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
47355 | #define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
47356 | //BIF_CFG_DEV2_EPF4_0_LINK_STATUS2 |
47357 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
47358 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
47359 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
47360 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
47361 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
47362 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
47363 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
47364 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
47365 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
47366 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
47367 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
47368 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
47369 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
47370 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
47371 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
47372 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
47373 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
47374 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
47375 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
47376 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
47377 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
47378 | #define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
47379 | //BIF_CFG_DEV2_EPF4_0_MSI_CAP_LIST |
47380 | #define BIF_CFG_DEV2_EPF4_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
47381 | #define BIF_CFG_DEV2_EPF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
47382 | #define BIF_CFG_DEV2_EPF4_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
47383 | #define BIF_CFG_DEV2_EPF4_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
47384 | //BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL |
47385 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
47386 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
47387 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
47388 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
47389 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
47390 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
47391 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
47392 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
47393 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
47394 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
47395 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
47396 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
47397 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
47398 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
47399 | //BIF_CFG_DEV2_EPF4_0_MSI_MSG_ADDR_LO |
47400 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
47401 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
47402 | //BIF_CFG_DEV2_EPF4_0_MSI_MSG_ADDR_HI |
47403 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
47404 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
47405 | //BIF_CFG_DEV2_EPF4_0_MSI_MSG_DATA |
47406 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
47407 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
47408 | //BIF_CFG_DEV2_EPF4_0_MSI_EXT_MSG_DATA |
47409 | #define BIF_CFG_DEV2_EPF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
47410 | #define BIF_CFG_DEV2_EPF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
47411 | //BIF_CFG_DEV2_EPF4_0_MSI_MASK |
47412 | #define BIF_CFG_DEV2_EPF4_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
47413 | #define BIF_CFG_DEV2_EPF4_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
47414 | //BIF_CFG_DEV2_EPF4_0_MSI_MSG_DATA_64 |
47415 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
47416 | #define BIF_CFG_DEV2_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
47417 | //BIF_CFG_DEV2_EPF4_0_MSI_EXT_MSG_DATA_64 |
47418 | #define BIF_CFG_DEV2_EPF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
47419 | #define BIF_CFG_DEV2_EPF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
47420 | //BIF_CFG_DEV2_EPF4_0_MSI_MASK_64 |
47421 | #define BIF_CFG_DEV2_EPF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
47422 | #define BIF_CFG_DEV2_EPF4_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
47423 | //BIF_CFG_DEV2_EPF4_0_MSI_PENDING |
47424 | #define BIF_CFG_DEV2_EPF4_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
47425 | #define BIF_CFG_DEV2_EPF4_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
47426 | //BIF_CFG_DEV2_EPF4_0_MSI_PENDING_64 |
47427 | #define BIF_CFG_DEV2_EPF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
47428 | #define BIF_CFG_DEV2_EPF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
47429 | //BIF_CFG_DEV2_EPF4_0_MSIX_CAP_LIST |
47430 | #define BIF_CFG_DEV2_EPF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
47431 | #define BIF_CFG_DEV2_EPF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
47432 | #define BIF_CFG_DEV2_EPF4_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
47433 | #define BIF_CFG_DEV2_EPF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
47434 | //BIF_CFG_DEV2_EPF4_0_MSIX_MSG_CNTL |
47435 | #define BIF_CFG_DEV2_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
47436 | #define BIF_CFG_DEV2_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
47437 | #define BIF_CFG_DEV2_EPF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
47438 | #define BIF_CFG_DEV2_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
47439 | #define BIF_CFG_DEV2_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
47440 | #define BIF_CFG_DEV2_EPF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
47441 | //BIF_CFG_DEV2_EPF4_0_MSIX_TABLE |
47442 | #define BIF_CFG_DEV2_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
47443 | #define BIF_CFG_DEV2_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
47444 | #define BIF_CFG_DEV2_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
47445 | #define BIF_CFG_DEV2_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
47446 | //BIF_CFG_DEV2_EPF4_0_MSIX_PBA |
47447 | #define BIF_CFG_DEV2_EPF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
47448 | #define BIF_CFG_DEV2_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
47449 | #define BIF_CFG_DEV2_EPF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
47450 | #define BIF_CFG_DEV2_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
47451 | //BIF_CFG_DEV2_EPF4_0_SATA_CAP_0 |
47452 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
47453 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
47454 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
47455 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
47456 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
47457 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
47458 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
47459 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
47460 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
47461 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
47462 | //BIF_CFG_DEV2_EPF4_0_SATA_CAP_1 |
47463 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
47464 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
47465 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
47466 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
47467 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
47468 | #define BIF_CFG_DEV2_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
47469 | //BIF_CFG_DEV2_EPF4_0_SATA_IDP_INDEX |
47470 | #define BIF_CFG_DEV2_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
47471 | #define BIF_CFG_DEV2_EPF4_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
47472 | #define BIF_CFG_DEV2_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
47473 | #define BIF_CFG_DEV2_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
47474 | #define BIF_CFG_DEV2_EPF4_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
47475 | #define BIF_CFG_DEV2_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
47476 | //BIF_CFG_DEV2_EPF4_0_SATA_IDP_DATA |
47477 | #define BIF_CFG_DEV2_EPF4_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
47478 | #define BIF_CFG_DEV2_EPF4_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
47479 | //BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
47480 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47481 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47482 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47483 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47484 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47485 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47486 | //BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR |
47487 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
47488 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
47489 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
47490 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
47491 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
47492 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
47493 | //BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC1 |
47494 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
47495 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
47496 | //BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC2 |
47497 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
47498 | #define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
47499 | //BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
47500 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47501 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47502 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47503 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47504 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47505 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47506 | //BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS |
47507 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
47508 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
47509 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
47510 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
47511 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
47512 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
47513 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
47514 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
47515 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
47516 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
47517 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
47518 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
47519 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
47520 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
47521 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
47522 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
47523 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
47524 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
47525 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
47526 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
47527 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
47528 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
47529 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
47530 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
47531 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
47532 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
47533 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
47534 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
47535 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
47536 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
47537 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
47538 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
47539 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
47540 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
47541 | //BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK |
47542 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
47543 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
47544 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
47545 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
47546 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
47547 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
47548 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
47549 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
47550 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
47551 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
47552 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
47553 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
47554 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
47555 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
47556 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
47557 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
47558 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
47559 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
47560 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
47561 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
47562 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
47563 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
47564 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
47565 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
47566 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
47567 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
47568 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
47569 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
47570 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
47571 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
47572 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
47573 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
47574 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
47575 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
47576 | //BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY |
47577 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
47578 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
47579 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
47580 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
47581 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
47582 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
47583 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
47584 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
47585 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
47586 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
47587 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
47588 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
47589 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
47590 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
47591 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
47592 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
47593 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
47594 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
47595 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
47596 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
47597 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
47598 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
47599 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
47600 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
47601 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
47602 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
47603 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
47604 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
47605 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
47606 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
47607 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
47608 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
47609 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
47610 | #define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
47611 | //BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS |
47612 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
47613 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
47614 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
47615 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
47616 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
47617 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
47618 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
47619 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
47620 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
47621 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
47622 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
47623 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
47624 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
47625 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
47626 | //BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK |
47627 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
47628 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
47629 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
47630 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
47631 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
47632 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
47633 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
47634 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
47635 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
47636 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
47637 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
47638 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
47639 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
47640 | #define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
47641 | //BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL |
47642 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
47643 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
47644 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
47645 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
47646 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
47647 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
47648 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
47649 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
47650 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
47651 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
47652 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
47653 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
47654 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
47655 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
47656 | //BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG0 |
47657 | #define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
47658 | #define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
47659 | //BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG1 |
47660 | #define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
47661 | #define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
47662 | //BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG2 |
47663 | #define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
47664 | #define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
47665 | //BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG3 |
47666 | #define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
47667 | #define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
47668 | //BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG0 |
47669 | #define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
47670 | #define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
47671 | //BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG1 |
47672 | #define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
47673 | #define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
47674 | //BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG2 |
47675 | #define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
47676 | #define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
47677 | //BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG3 |
47678 | #define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
47679 | #define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
47680 | //BIF_CFG_DEV2_EPF4_0_PCIE_BAR_ENH_CAP_LIST |
47681 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47682 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47683 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47684 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47685 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47686 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47687 | //BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CAP |
47688 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
47689 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
47690 | //BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL |
47691 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
47692 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
47693 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
47694 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
47695 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
47696 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
47697 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
47698 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
47699 | //BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CAP |
47700 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
47701 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
47702 | //BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL |
47703 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
47704 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
47705 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
47706 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
47707 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
47708 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
47709 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
47710 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
47711 | //BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CAP |
47712 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
47713 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
47714 | //BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL |
47715 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
47716 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
47717 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
47718 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
47719 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
47720 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
47721 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
47722 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
47723 | //BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CAP |
47724 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
47725 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
47726 | //BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL |
47727 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
47728 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
47729 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
47730 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
47731 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
47732 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
47733 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
47734 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
47735 | //BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CAP |
47736 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
47737 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
47738 | //BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL |
47739 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
47740 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
47741 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
47742 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
47743 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
47744 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
47745 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
47746 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
47747 | //BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CAP |
47748 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
47749 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
47750 | //BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL |
47751 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
47752 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
47753 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
47754 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
47755 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
47756 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
47757 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
47758 | #define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
47759 | //BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
47760 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47761 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47762 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47763 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47764 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47765 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47766 | //BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT |
47767 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
47768 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
47769 | //BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA |
47770 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
47771 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
47772 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
47773 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
47774 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
47775 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
47776 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
47777 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
47778 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
47779 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
47780 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
47781 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
47782 | //BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_CAP |
47783 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
47784 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
47785 | //BIF_CFG_DEV2_EPF4_0_PCIE_DPA_ENH_CAP_LIST |
47786 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47787 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47788 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47789 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47790 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47791 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47792 | //BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP |
47793 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
47794 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
47795 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
47796 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
47797 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
47798 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
47799 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
47800 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
47801 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
47802 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
47803 | //BIF_CFG_DEV2_EPF4_0_PCIE_DPA_LATENCY_INDICATOR |
47804 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
47805 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
47806 | //BIF_CFG_DEV2_EPF4_0_PCIE_DPA_STATUS |
47807 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
47808 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
47809 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
47810 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
47811 | //BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CNTL |
47812 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
47813 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
47814 | //BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
47815 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47816 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47817 | //BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
47818 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47819 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47820 | //BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
47821 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47822 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47823 | //BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
47824 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47825 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47826 | //BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
47827 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47828 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47829 | //BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
47830 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47831 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47832 | //BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
47833 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47834 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47835 | //BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
47836 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
47837 | #define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
47838 | //BIF_CFG_DEV2_EPF4_0_PCIE_ACS_ENH_CAP_LIST |
47839 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47840 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47841 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47842 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47843 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47844 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47845 | //BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP |
47846 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
47847 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
47848 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
47849 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
47850 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
47851 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
47852 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
47853 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
47854 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
47855 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
47856 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
47857 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
47858 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
47859 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
47860 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
47861 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
47862 | //BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL |
47863 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
47864 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
47865 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
47866 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
47867 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
47868 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
47869 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
47870 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
47871 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
47872 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
47873 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
47874 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
47875 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
47876 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
47877 | //BIF_CFG_DEV2_EPF4_0_PCIE_PASID_ENH_CAP_LIST |
47878 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47879 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47880 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47881 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47882 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47883 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47884 | //BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CAP |
47885 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
47886 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
47887 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
47888 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
47889 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
47890 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
47891 | //BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CNTL |
47892 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
47893 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
47894 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
47895 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
47896 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
47897 | #define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
47898 | //BIF_CFG_DEV2_EPF4_0_PCIE_ARI_ENH_CAP_LIST |
47899 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47900 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47901 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47902 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47903 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47904 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47905 | //BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CAP |
47906 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
47907 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
47908 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
47909 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
47910 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
47911 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
47912 | //BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CNTL |
47913 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
47914 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
47915 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
47916 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
47917 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
47918 | #define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
47919 | //BIF_CFG_DEV2_EPF4_0_PCIE_RTR_ENH_CAP_LIST |
47920 | #define BIF_CFG_DEV2_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
47921 | #define BIF_CFG_DEV2_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
47922 | #define BIF_CFG_DEV2_EPF4_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
47923 | #define BIF_CFG_DEV2_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
47924 | #define BIF_CFG_DEV2_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
47925 | #define BIF_CFG_DEV2_EPF4_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
47926 | //BIF_CFG_DEV2_EPF4_0_RTR_DATA1 |
47927 | #define BIF_CFG_DEV2_EPF4_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
47928 | #define BIF_CFG_DEV2_EPF4_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
47929 | #define BIF_CFG_DEV2_EPF4_0_RTR_DATA1__VALID__SHIFT 0x1f |
47930 | #define BIF_CFG_DEV2_EPF4_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
47931 | #define BIF_CFG_DEV2_EPF4_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
47932 | #define BIF_CFG_DEV2_EPF4_0_RTR_DATA1__VALID_MASK 0x80000000L |
47933 | //BIF_CFG_DEV2_EPF4_0_RTR_DATA2 |
47934 | #define BIF_CFG_DEV2_EPF4_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
47935 | #define BIF_CFG_DEV2_EPF4_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
47936 | #define BIF_CFG_DEV2_EPF4_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
47937 | #define BIF_CFG_DEV2_EPF4_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
47938 | |
47939 | |
47940 | // addressBlock: nbio_nbif0_bif_cfg_dev2_epf5_bifcfgdecp |
47941 | //BIF_CFG_DEV2_EPF5_0_VENDOR_ID |
47942 | #define BIF_CFG_DEV2_EPF5_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
47943 | #define BIF_CFG_DEV2_EPF5_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
47944 | //BIF_CFG_DEV2_EPF5_0_DEVICE_ID |
47945 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
47946 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
47947 | //BIF_CFG_DEV2_EPF5_0_COMMAND |
47948 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
47949 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
47950 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
47951 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
47952 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
47953 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
47954 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
47955 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__SERR_EN__SHIFT 0x8 |
47956 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
47957 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__INT_DIS__SHIFT 0xa |
47958 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
47959 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
47960 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
47961 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
47962 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
47963 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
47964 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__AD_STEPPING_MASK 0x0080L |
47965 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__SERR_EN_MASK 0x0100L |
47966 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
47967 | #define BIF_CFG_DEV2_EPF5_0_COMMAND__INT_DIS_MASK 0x0400L |
47968 | //BIF_CFG_DEV2_EPF5_0_STATUS |
47969 | #define BIF_CFG_DEV2_EPF5_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
47970 | #define BIF_CFG_DEV2_EPF5_0_STATUS__INT_STATUS__SHIFT 0x3 |
47971 | #define BIF_CFG_DEV2_EPF5_0_STATUS__CAP_LIST__SHIFT 0x4 |
47972 | #define BIF_CFG_DEV2_EPF5_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
47973 | #define BIF_CFG_DEV2_EPF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
47974 | #define BIF_CFG_DEV2_EPF5_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
47975 | #define BIF_CFG_DEV2_EPF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
47976 | #define BIF_CFG_DEV2_EPF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
47977 | #define BIF_CFG_DEV2_EPF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
47978 | #define BIF_CFG_DEV2_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
47979 | #define BIF_CFG_DEV2_EPF5_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
47980 | #define BIF_CFG_DEV2_EPF5_0_STATUS__INT_STATUS_MASK 0x0008L |
47981 | #define BIF_CFG_DEV2_EPF5_0_STATUS__CAP_LIST_MASK 0x0010L |
47982 | #define BIF_CFG_DEV2_EPF5_0_STATUS__PCI_66_CAP_MASK 0x0020L |
47983 | #define BIF_CFG_DEV2_EPF5_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
47984 | #define BIF_CFG_DEV2_EPF5_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
47985 | #define BIF_CFG_DEV2_EPF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
47986 | #define BIF_CFG_DEV2_EPF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
47987 | #define BIF_CFG_DEV2_EPF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
47988 | #define BIF_CFG_DEV2_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
47989 | //BIF_CFG_DEV2_EPF5_0_REVISION_ID |
47990 | #define BIF_CFG_DEV2_EPF5_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
47991 | #define BIF_CFG_DEV2_EPF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
47992 | #define BIF_CFG_DEV2_EPF5_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
47993 | #define BIF_CFG_DEV2_EPF5_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
47994 | //BIF_CFG_DEV2_EPF5_0_PROG_INTERFACE |
47995 | #define BIF_CFG_DEV2_EPF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
47996 | #define BIF_CFG_DEV2_EPF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
47997 | //BIF_CFG_DEV2_EPF5_0_SUB_CLASS |
47998 | #define BIF_CFG_DEV2_EPF5_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
47999 | #define BIF_CFG_DEV2_EPF5_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
48000 | //BIF_CFG_DEV2_EPF5_0_BASE_CLASS |
48001 | #define BIF_CFG_DEV2_EPF5_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
48002 | #define BIF_CFG_DEV2_EPF5_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
48003 | //BIF_CFG_DEV2_EPF5_0_CACHE_LINE |
48004 | #define BIF_CFG_DEV2_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
48005 | #define BIF_CFG_DEV2_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
48006 | //BIF_CFG_DEV2_EPF5_0_LATENCY |
48007 | #define BIF_CFG_DEV2_EPF5_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
48008 | #define BIF_CFG_DEV2_EPF5_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
48009 | //BIF_CFG_DEV2_EPF5_0_HEADER |
48010 | #define 0x0 |
48011 | #define 0x7 |
48012 | #define 0x7FL |
48013 | #define 0x80L |
48014 | //BIF_CFG_DEV2_EPF5_0_BIST |
48015 | #define BIF_CFG_DEV2_EPF5_0_BIST__BIST_COMP__SHIFT 0x0 |
48016 | #define BIF_CFG_DEV2_EPF5_0_BIST__BIST_STRT__SHIFT 0x6 |
48017 | #define BIF_CFG_DEV2_EPF5_0_BIST__BIST_CAP__SHIFT 0x7 |
48018 | #define BIF_CFG_DEV2_EPF5_0_BIST__BIST_COMP_MASK 0x0FL |
48019 | #define BIF_CFG_DEV2_EPF5_0_BIST__BIST_STRT_MASK 0x40L |
48020 | #define BIF_CFG_DEV2_EPF5_0_BIST__BIST_CAP_MASK 0x80L |
48021 | //BIF_CFG_DEV2_EPF5_0_BASE_ADDR_1 |
48022 | #define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
48023 | #define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
48024 | //BIF_CFG_DEV2_EPF5_0_BASE_ADDR_2 |
48025 | #define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
48026 | #define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
48027 | //BIF_CFG_DEV2_EPF5_0_BASE_ADDR_3 |
48028 | #define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
48029 | #define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
48030 | //BIF_CFG_DEV2_EPF5_0_BASE_ADDR_4 |
48031 | #define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
48032 | #define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
48033 | //BIF_CFG_DEV2_EPF5_0_BASE_ADDR_5 |
48034 | #define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
48035 | #define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
48036 | //BIF_CFG_DEV2_EPF5_0_BASE_ADDR_6 |
48037 | #define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
48038 | #define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
48039 | //BIF_CFG_DEV2_EPF5_0_ADAPTER_ID |
48040 | #define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
48041 | #define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
48042 | #define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
48043 | #define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
48044 | //BIF_CFG_DEV2_EPF5_0_ROM_BASE_ADDR |
48045 | #define BIF_CFG_DEV2_EPF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
48046 | #define BIF_CFG_DEV2_EPF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
48047 | //BIF_CFG_DEV2_EPF5_0_CAP_PTR |
48048 | #define BIF_CFG_DEV2_EPF5_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
48049 | #define BIF_CFG_DEV2_EPF5_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
48050 | //BIF_CFG_DEV2_EPF5_0_INTERRUPT_LINE |
48051 | #define BIF_CFG_DEV2_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
48052 | #define BIF_CFG_DEV2_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
48053 | //BIF_CFG_DEV2_EPF5_0_INTERRUPT_PIN |
48054 | #define BIF_CFG_DEV2_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
48055 | #define BIF_CFG_DEV2_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
48056 | //BIF_CFG_DEV2_EPF5_0_MIN_GRANT |
48057 | #define BIF_CFG_DEV2_EPF5_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
48058 | #define BIF_CFG_DEV2_EPF5_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
48059 | //BIF_CFG_DEV2_EPF5_0_MAX_LATENCY |
48060 | #define BIF_CFG_DEV2_EPF5_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
48061 | #define BIF_CFG_DEV2_EPF5_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
48062 | //BIF_CFG_DEV2_EPF5_0_VENDOR_CAP_LIST |
48063 | #define BIF_CFG_DEV2_EPF5_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
48064 | #define BIF_CFG_DEV2_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
48065 | #define BIF_CFG_DEV2_EPF5_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
48066 | #define BIF_CFG_DEV2_EPF5_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
48067 | #define BIF_CFG_DEV2_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
48068 | #define BIF_CFG_DEV2_EPF5_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
48069 | //BIF_CFG_DEV2_EPF5_0_ADAPTER_ID_W |
48070 | #define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
48071 | #define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
48072 | #define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
48073 | #define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
48074 | //BIF_CFG_DEV2_EPF5_0_PMI_CAP_LIST |
48075 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
48076 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
48077 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
48078 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
48079 | //BIF_CFG_DEV2_EPF5_0_PMI_CAP |
48080 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__VERSION__SHIFT 0x0 |
48081 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
48082 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
48083 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
48084 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
48085 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
48086 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
48087 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
48088 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__VERSION_MASK 0x0007L |
48089 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
48090 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
48091 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
48092 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
48093 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
48094 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
48095 | #define BIF_CFG_DEV2_EPF5_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
48096 | //BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL |
48097 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
48098 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
48099 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
48100 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
48101 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
48102 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
48103 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
48104 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
48105 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
48106 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
48107 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
48108 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
48109 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
48110 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
48111 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
48112 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
48113 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
48114 | #define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
48115 | //BIF_CFG_DEV2_EPF5_0_PCIE_CAP_LIST |
48116 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
48117 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
48118 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
48119 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
48120 | //BIF_CFG_DEV2_EPF5_0_PCIE_CAP |
48121 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__VERSION__SHIFT 0x0 |
48122 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
48123 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
48124 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
48125 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__VERSION_MASK 0x000FL |
48126 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
48127 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
48128 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
48129 | //BIF_CFG_DEV2_EPF5_0_DEVICE_CAP |
48130 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
48131 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
48132 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
48133 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
48134 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
48135 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
48136 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
48137 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
48138 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
48139 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
48140 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
48141 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
48142 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
48143 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
48144 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
48145 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
48146 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
48147 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
48148 | //BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL |
48149 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
48150 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
48151 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
48152 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
48153 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
48154 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
48155 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
48156 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
48157 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
48158 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
48159 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
48160 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
48161 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
48162 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
48163 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
48164 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
48165 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
48166 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
48167 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
48168 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
48169 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
48170 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
48171 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
48172 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
48173 | //BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS |
48174 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
48175 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
48176 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
48177 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
48178 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
48179 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
48180 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
48181 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
48182 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
48183 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
48184 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
48185 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
48186 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
48187 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
48188 | //BIF_CFG_DEV2_EPF5_0_LINK_CAP |
48189 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
48190 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
48191 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
48192 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
48193 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
48194 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
48195 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
48196 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
48197 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
48198 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
48199 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
48200 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
48201 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
48202 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
48203 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
48204 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
48205 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
48206 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
48207 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
48208 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
48209 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
48210 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
48211 | //BIF_CFG_DEV2_EPF5_0_LINK_CNTL |
48212 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
48213 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
48214 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
48215 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
48216 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
48217 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
48218 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
48219 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
48220 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
48221 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
48222 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
48223 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
48224 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
48225 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
48226 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
48227 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
48228 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
48229 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
48230 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
48231 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
48232 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
48233 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
48234 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
48235 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
48236 | //BIF_CFG_DEV2_EPF5_0_LINK_STATUS |
48237 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
48238 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
48239 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
48240 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
48241 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
48242 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
48243 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
48244 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
48245 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
48246 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
48247 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
48248 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
48249 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
48250 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
48251 | //BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2 |
48252 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
48253 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
48254 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
48255 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
48256 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
48257 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
48258 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
48259 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
48260 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
48261 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
48262 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
48263 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
48264 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
48265 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
48266 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
48267 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
48268 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
48269 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
48270 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
48271 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
48272 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
48273 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
48274 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
48275 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
48276 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
48277 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
48278 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
48279 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
48280 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
48281 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
48282 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
48283 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
48284 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
48285 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
48286 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
48287 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
48288 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
48289 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
48290 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
48291 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
48292 | //BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2 |
48293 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
48294 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
48295 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
48296 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
48297 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
48298 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
48299 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
48300 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
48301 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
48302 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
48303 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
48304 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
48305 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
48306 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
48307 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
48308 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
48309 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
48310 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
48311 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
48312 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
48313 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
48314 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
48315 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
48316 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
48317 | //BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS2 |
48318 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
48319 | #define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
48320 | //BIF_CFG_DEV2_EPF5_0_LINK_CAP2 |
48321 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
48322 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
48323 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
48324 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
48325 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
48326 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
48327 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
48328 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
48329 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
48330 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
48331 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
48332 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
48333 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
48334 | #define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
48335 | //BIF_CFG_DEV2_EPF5_0_LINK_CNTL2 |
48336 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
48337 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
48338 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
48339 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
48340 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
48341 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
48342 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
48343 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
48344 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
48345 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
48346 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
48347 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
48348 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
48349 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
48350 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
48351 | #define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
48352 | //BIF_CFG_DEV2_EPF5_0_LINK_STATUS2 |
48353 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
48354 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
48355 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
48356 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
48357 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
48358 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
48359 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
48360 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
48361 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
48362 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
48363 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
48364 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
48365 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
48366 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
48367 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
48368 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
48369 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
48370 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
48371 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
48372 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
48373 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
48374 | #define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
48375 | //BIF_CFG_DEV2_EPF5_0_MSI_CAP_LIST |
48376 | #define BIF_CFG_DEV2_EPF5_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
48377 | #define BIF_CFG_DEV2_EPF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
48378 | #define BIF_CFG_DEV2_EPF5_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
48379 | #define BIF_CFG_DEV2_EPF5_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
48380 | //BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL |
48381 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
48382 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
48383 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
48384 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
48385 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
48386 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
48387 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
48388 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
48389 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
48390 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
48391 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
48392 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
48393 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
48394 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
48395 | //BIF_CFG_DEV2_EPF5_0_MSI_MSG_ADDR_LO |
48396 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
48397 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
48398 | //BIF_CFG_DEV2_EPF5_0_MSI_MSG_ADDR_HI |
48399 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
48400 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
48401 | //BIF_CFG_DEV2_EPF5_0_MSI_MSG_DATA |
48402 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
48403 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
48404 | //BIF_CFG_DEV2_EPF5_0_MSI_EXT_MSG_DATA |
48405 | #define BIF_CFG_DEV2_EPF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
48406 | #define BIF_CFG_DEV2_EPF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
48407 | //BIF_CFG_DEV2_EPF5_0_MSI_MASK |
48408 | #define BIF_CFG_DEV2_EPF5_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
48409 | #define BIF_CFG_DEV2_EPF5_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
48410 | //BIF_CFG_DEV2_EPF5_0_MSI_MSG_DATA_64 |
48411 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
48412 | #define BIF_CFG_DEV2_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
48413 | //BIF_CFG_DEV2_EPF5_0_MSI_EXT_MSG_DATA_64 |
48414 | #define BIF_CFG_DEV2_EPF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
48415 | #define BIF_CFG_DEV2_EPF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
48416 | //BIF_CFG_DEV2_EPF5_0_MSI_MASK_64 |
48417 | #define BIF_CFG_DEV2_EPF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
48418 | #define BIF_CFG_DEV2_EPF5_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
48419 | //BIF_CFG_DEV2_EPF5_0_MSI_PENDING |
48420 | #define BIF_CFG_DEV2_EPF5_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
48421 | #define BIF_CFG_DEV2_EPF5_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
48422 | //BIF_CFG_DEV2_EPF5_0_MSI_PENDING_64 |
48423 | #define BIF_CFG_DEV2_EPF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
48424 | #define BIF_CFG_DEV2_EPF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
48425 | //BIF_CFG_DEV2_EPF5_0_MSIX_CAP_LIST |
48426 | #define BIF_CFG_DEV2_EPF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
48427 | #define BIF_CFG_DEV2_EPF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
48428 | #define BIF_CFG_DEV2_EPF5_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
48429 | #define BIF_CFG_DEV2_EPF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
48430 | //BIF_CFG_DEV2_EPF5_0_MSIX_MSG_CNTL |
48431 | #define BIF_CFG_DEV2_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
48432 | #define BIF_CFG_DEV2_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
48433 | #define BIF_CFG_DEV2_EPF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
48434 | #define BIF_CFG_DEV2_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
48435 | #define BIF_CFG_DEV2_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
48436 | #define BIF_CFG_DEV2_EPF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
48437 | //BIF_CFG_DEV2_EPF5_0_MSIX_TABLE |
48438 | #define BIF_CFG_DEV2_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
48439 | #define BIF_CFG_DEV2_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
48440 | #define BIF_CFG_DEV2_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
48441 | #define BIF_CFG_DEV2_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
48442 | //BIF_CFG_DEV2_EPF5_0_MSIX_PBA |
48443 | #define BIF_CFG_DEV2_EPF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
48444 | #define BIF_CFG_DEV2_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
48445 | #define BIF_CFG_DEV2_EPF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
48446 | #define BIF_CFG_DEV2_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
48447 | //BIF_CFG_DEV2_EPF5_0_SATA_CAP_0 |
48448 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
48449 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
48450 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
48451 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
48452 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
48453 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
48454 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
48455 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
48456 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
48457 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
48458 | //BIF_CFG_DEV2_EPF5_0_SATA_CAP_1 |
48459 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
48460 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
48461 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
48462 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
48463 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
48464 | #define BIF_CFG_DEV2_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
48465 | //BIF_CFG_DEV2_EPF5_0_SATA_IDP_INDEX |
48466 | #define BIF_CFG_DEV2_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
48467 | #define BIF_CFG_DEV2_EPF5_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
48468 | #define BIF_CFG_DEV2_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
48469 | #define BIF_CFG_DEV2_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
48470 | #define BIF_CFG_DEV2_EPF5_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
48471 | #define BIF_CFG_DEV2_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
48472 | //BIF_CFG_DEV2_EPF5_0_SATA_IDP_DATA |
48473 | #define BIF_CFG_DEV2_EPF5_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
48474 | #define BIF_CFG_DEV2_EPF5_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
48475 | //BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
48476 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48477 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48478 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48479 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48480 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48481 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48482 | //BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR |
48483 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
48484 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
48485 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
48486 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
48487 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
48488 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
48489 | //BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC1 |
48490 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
48491 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
48492 | //BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC2 |
48493 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
48494 | #define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
48495 | //BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
48496 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48497 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48498 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48499 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48500 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48501 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48502 | //BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS |
48503 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
48504 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
48505 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
48506 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
48507 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
48508 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
48509 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
48510 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
48511 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
48512 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
48513 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
48514 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
48515 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
48516 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
48517 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
48518 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
48519 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
48520 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
48521 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
48522 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
48523 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
48524 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
48525 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
48526 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
48527 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
48528 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
48529 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
48530 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
48531 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
48532 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
48533 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
48534 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
48535 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
48536 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
48537 | //BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK |
48538 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
48539 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
48540 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
48541 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
48542 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
48543 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
48544 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
48545 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
48546 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
48547 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
48548 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
48549 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
48550 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
48551 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
48552 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
48553 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
48554 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
48555 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
48556 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
48557 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
48558 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
48559 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
48560 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
48561 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
48562 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
48563 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
48564 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
48565 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
48566 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
48567 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
48568 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
48569 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
48570 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
48571 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
48572 | //BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY |
48573 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
48574 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
48575 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
48576 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
48577 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
48578 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
48579 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
48580 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
48581 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
48582 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
48583 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
48584 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
48585 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
48586 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
48587 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
48588 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
48589 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
48590 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
48591 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
48592 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
48593 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
48594 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
48595 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
48596 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
48597 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
48598 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
48599 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
48600 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
48601 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
48602 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
48603 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
48604 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
48605 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
48606 | #define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
48607 | //BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS |
48608 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
48609 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
48610 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
48611 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
48612 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
48613 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
48614 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
48615 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
48616 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
48617 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
48618 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
48619 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
48620 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
48621 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
48622 | //BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK |
48623 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
48624 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
48625 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
48626 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
48627 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
48628 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
48629 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
48630 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
48631 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
48632 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
48633 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
48634 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
48635 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
48636 | #define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
48637 | //BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL |
48638 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
48639 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
48640 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
48641 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
48642 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
48643 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
48644 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
48645 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
48646 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
48647 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
48648 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
48649 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
48650 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
48651 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
48652 | //BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG0 |
48653 | #define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
48654 | #define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
48655 | //BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG1 |
48656 | #define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
48657 | #define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
48658 | //BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG2 |
48659 | #define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
48660 | #define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
48661 | //BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG3 |
48662 | #define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
48663 | #define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
48664 | //BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG0 |
48665 | #define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
48666 | #define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
48667 | //BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG1 |
48668 | #define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
48669 | #define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
48670 | //BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG2 |
48671 | #define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
48672 | #define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
48673 | //BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG3 |
48674 | #define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
48675 | #define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
48676 | //BIF_CFG_DEV2_EPF5_0_PCIE_BAR_ENH_CAP_LIST |
48677 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48678 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48679 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48680 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48681 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48682 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48683 | //BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CAP |
48684 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
48685 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
48686 | //BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL |
48687 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
48688 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
48689 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
48690 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
48691 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
48692 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
48693 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
48694 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
48695 | //BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CAP |
48696 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
48697 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
48698 | //BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL |
48699 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
48700 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
48701 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
48702 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
48703 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
48704 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
48705 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
48706 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
48707 | //BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CAP |
48708 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
48709 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
48710 | //BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL |
48711 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
48712 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
48713 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
48714 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
48715 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
48716 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
48717 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
48718 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
48719 | //BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CAP |
48720 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
48721 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
48722 | //BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL |
48723 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
48724 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
48725 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
48726 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
48727 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
48728 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
48729 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
48730 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
48731 | //BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CAP |
48732 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
48733 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
48734 | //BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL |
48735 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
48736 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
48737 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
48738 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
48739 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
48740 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
48741 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
48742 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
48743 | //BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CAP |
48744 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
48745 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
48746 | //BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL |
48747 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
48748 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
48749 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
48750 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
48751 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
48752 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
48753 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
48754 | #define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
48755 | //BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
48756 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48757 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48758 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48759 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48760 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48761 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48762 | //BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT |
48763 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
48764 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
48765 | //BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA |
48766 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
48767 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
48768 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
48769 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
48770 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
48771 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
48772 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
48773 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
48774 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
48775 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
48776 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
48777 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
48778 | //BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_CAP |
48779 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
48780 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
48781 | //BIF_CFG_DEV2_EPF5_0_PCIE_DPA_ENH_CAP_LIST |
48782 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48783 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48784 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48785 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48786 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48787 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48788 | //BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP |
48789 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
48790 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
48791 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
48792 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
48793 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
48794 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
48795 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
48796 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
48797 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
48798 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
48799 | //BIF_CFG_DEV2_EPF5_0_PCIE_DPA_LATENCY_INDICATOR |
48800 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
48801 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
48802 | //BIF_CFG_DEV2_EPF5_0_PCIE_DPA_STATUS |
48803 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
48804 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
48805 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
48806 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
48807 | //BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CNTL |
48808 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
48809 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
48810 | //BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
48811 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48812 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48813 | //BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
48814 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48815 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48816 | //BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
48817 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48818 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48819 | //BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
48820 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48821 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48822 | //BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
48823 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48824 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48825 | //BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
48826 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48827 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48828 | //BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
48829 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48830 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48831 | //BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
48832 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
48833 | #define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
48834 | //BIF_CFG_DEV2_EPF5_0_PCIE_ACS_ENH_CAP_LIST |
48835 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48836 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48837 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48838 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48839 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48840 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48841 | //BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP |
48842 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
48843 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
48844 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
48845 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
48846 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
48847 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
48848 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
48849 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
48850 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
48851 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
48852 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
48853 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
48854 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
48855 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
48856 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
48857 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
48858 | //BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL |
48859 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
48860 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
48861 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
48862 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
48863 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
48864 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
48865 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
48866 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
48867 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
48868 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
48869 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
48870 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
48871 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
48872 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
48873 | //BIF_CFG_DEV2_EPF5_0_PCIE_PASID_ENH_CAP_LIST |
48874 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48875 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48876 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48877 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48878 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48879 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48880 | //BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CAP |
48881 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
48882 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
48883 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
48884 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
48885 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
48886 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
48887 | //BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CNTL |
48888 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
48889 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
48890 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
48891 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
48892 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
48893 | #define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
48894 | //BIF_CFG_DEV2_EPF5_0_PCIE_ARI_ENH_CAP_LIST |
48895 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48896 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48897 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48898 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48899 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48900 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48901 | //BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CAP |
48902 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
48903 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
48904 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
48905 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
48906 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
48907 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
48908 | //BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CNTL |
48909 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
48910 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
48911 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
48912 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
48913 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
48914 | #define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
48915 | //BIF_CFG_DEV2_EPF5_0_PCIE_RTR_ENH_CAP_LIST |
48916 | #define BIF_CFG_DEV2_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
48917 | #define BIF_CFG_DEV2_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
48918 | #define BIF_CFG_DEV2_EPF5_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
48919 | #define BIF_CFG_DEV2_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
48920 | #define BIF_CFG_DEV2_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
48921 | #define BIF_CFG_DEV2_EPF5_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
48922 | //BIF_CFG_DEV2_EPF5_0_RTR_DATA1 |
48923 | #define BIF_CFG_DEV2_EPF5_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
48924 | #define BIF_CFG_DEV2_EPF5_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
48925 | #define BIF_CFG_DEV2_EPF5_0_RTR_DATA1__VALID__SHIFT 0x1f |
48926 | #define BIF_CFG_DEV2_EPF5_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
48927 | #define BIF_CFG_DEV2_EPF5_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
48928 | #define BIF_CFG_DEV2_EPF5_0_RTR_DATA1__VALID_MASK 0x80000000L |
48929 | //BIF_CFG_DEV2_EPF5_0_RTR_DATA2 |
48930 | #define BIF_CFG_DEV2_EPF5_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
48931 | #define BIF_CFG_DEV2_EPF5_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
48932 | #define BIF_CFG_DEV2_EPF5_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
48933 | #define BIF_CFG_DEV2_EPF5_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
48934 | |
48935 | |
48936 | // addressBlock: nbio_nbif0_bif_cfg_dev2_epf6_bifcfgdecp |
48937 | //BIF_CFG_DEV2_EPF6_0_VENDOR_ID |
48938 | #define BIF_CFG_DEV2_EPF6_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
48939 | #define BIF_CFG_DEV2_EPF6_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
48940 | //BIF_CFG_DEV2_EPF6_0_DEVICE_ID |
48941 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
48942 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
48943 | //BIF_CFG_DEV2_EPF6_0_COMMAND |
48944 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
48945 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
48946 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
48947 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
48948 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
48949 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
48950 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
48951 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__SERR_EN__SHIFT 0x8 |
48952 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
48953 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__INT_DIS__SHIFT 0xa |
48954 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
48955 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
48956 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
48957 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
48958 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
48959 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
48960 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__AD_STEPPING_MASK 0x0080L |
48961 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__SERR_EN_MASK 0x0100L |
48962 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
48963 | #define BIF_CFG_DEV2_EPF6_0_COMMAND__INT_DIS_MASK 0x0400L |
48964 | //BIF_CFG_DEV2_EPF6_0_STATUS |
48965 | #define BIF_CFG_DEV2_EPF6_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
48966 | #define BIF_CFG_DEV2_EPF6_0_STATUS__INT_STATUS__SHIFT 0x3 |
48967 | #define BIF_CFG_DEV2_EPF6_0_STATUS__CAP_LIST__SHIFT 0x4 |
48968 | #define BIF_CFG_DEV2_EPF6_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
48969 | #define BIF_CFG_DEV2_EPF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
48970 | #define BIF_CFG_DEV2_EPF6_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
48971 | #define BIF_CFG_DEV2_EPF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
48972 | #define BIF_CFG_DEV2_EPF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
48973 | #define BIF_CFG_DEV2_EPF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
48974 | #define BIF_CFG_DEV2_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
48975 | #define BIF_CFG_DEV2_EPF6_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
48976 | #define BIF_CFG_DEV2_EPF6_0_STATUS__INT_STATUS_MASK 0x0008L |
48977 | #define BIF_CFG_DEV2_EPF6_0_STATUS__CAP_LIST_MASK 0x0010L |
48978 | #define BIF_CFG_DEV2_EPF6_0_STATUS__PCI_66_CAP_MASK 0x0020L |
48979 | #define BIF_CFG_DEV2_EPF6_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
48980 | #define BIF_CFG_DEV2_EPF6_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
48981 | #define BIF_CFG_DEV2_EPF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
48982 | #define BIF_CFG_DEV2_EPF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
48983 | #define BIF_CFG_DEV2_EPF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
48984 | #define BIF_CFG_DEV2_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
48985 | //BIF_CFG_DEV2_EPF6_0_REVISION_ID |
48986 | #define BIF_CFG_DEV2_EPF6_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
48987 | #define BIF_CFG_DEV2_EPF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
48988 | #define BIF_CFG_DEV2_EPF6_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
48989 | #define BIF_CFG_DEV2_EPF6_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
48990 | //BIF_CFG_DEV2_EPF6_0_PROG_INTERFACE |
48991 | #define BIF_CFG_DEV2_EPF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
48992 | #define BIF_CFG_DEV2_EPF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
48993 | //BIF_CFG_DEV2_EPF6_0_SUB_CLASS |
48994 | #define BIF_CFG_DEV2_EPF6_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
48995 | #define BIF_CFG_DEV2_EPF6_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
48996 | //BIF_CFG_DEV2_EPF6_0_BASE_CLASS |
48997 | #define BIF_CFG_DEV2_EPF6_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
48998 | #define BIF_CFG_DEV2_EPF6_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
48999 | //BIF_CFG_DEV2_EPF6_0_CACHE_LINE |
49000 | #define BIF_CFG_DEV2_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
49001 | #define BIF_CFG_DEV2_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
49002 | //BIF_CFG_DEV2_EPF6_0_LATENCY |
49003 | #define BIF_CFG_DEV2_EPF6_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
49004 | #define BIF_CFG_DEV2_EPF6_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
49005 | //BIF_CFG_DEV2_EPF6_0_HEADER |
49006 | #define 0x0 |
49007 | #define 0x7 |
49008 | #define 0x7FL |
49009 | #define 0x80L |
49010 | //BIF_CFG_DEV2_EPF6_0_BIST |
49011 | #define BIF_CFG_DEV2_EPF6_0_BIST__BIST_COMP__SHIFT 0x0 |
49012 | #define BIF_CFG_DEV2_EPF6_0_BIST__BIST_STRT__SHIFT 0x6 |
49013 | #define BIF_CFG_DEV2_EPF6_0_BIST__BIST_CAP__SHIFT 0x7 |
49014 | #define BIF_CFG_DEV2_EPF6_0_BIST__BIST_COMP_MASK 0x0FL |
49015 | #define BIF_CFG_DEV2_EPF6_0_BIST__BIST_STRT_MASK 0x40L |
49016 | #define BIF_CFG_DEV2_EPF6_0_BIST__BIST_CAP_MASK 0x80L |
49017 | //BIF_CFG_DEV2_EPF6_0_BASE_ADDR_1 |
49018 | #define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
49019 | #define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
49020 | //BIF_CFG_DEV2_EPF6_0_BASE_ADDR_2 |
49021 | #define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
49022 | #define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
49023 | //BIF_CFG_DEV2_EPF6_0_BASE_ADDR_3 |
49024 | #define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
49025 | #define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
49026 | //BIF_CFG_DEV2_EPF6_0_BASE_ADDR_4 |
49027 | #define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
49028 | #define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
49029 | //BIF_CFG_DEV2_EPF6_0_BASE_ADDR_5 |
49030 | #define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
49031 | #define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
49032 | //BIF_CFG_DEV2_EPF6_0_BASE_ADDR_6 |
49033 | #define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
49034 | #define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
49035 | //BIF_CFG_DEV2_EPF6_0_ADAPTER_ID |
49036 | #define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
49037 | #define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
49038 | #define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
49039 | #define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
49040 | //BIF_CFG_DEV2_EPF6_0_ROM_BASE_ADDR |
49041 | #define BIF_CFG_DEV2_EPF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
49042 | #define BIF_CFG_DEV2_EPF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
49043 | //BIF_CFG_DEV2_EPF6_0_CAP_PTR |
49044 | #define BIF_CFG_DEV2_EPF6_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
49045 | #define BIF_CFG_DEV2_EPF6_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
49046 | //BIF_CFG_DEV2_EPF6_0_INTERRUPT_LINE |
49047 | #define BIF_CFG_DEV2_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
49048 | #define BIF_CFG_DEV2_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
49049 | //BIF_CFG_DEV2_EPF6_0_INTERRUPT_PIN |
49050 | #define BIF_CFG_DEV2_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
49051 | #define BIF_CFG_DEV2_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
49052 | //BIF_CFG_DEV2_EPF6_0_MIN_GRANT |
49053 | #define BIF_CFG_DEV2_EPF6_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
49054 | #define BIF_CFG_DEV2_EPF6_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
49055 | //BIF_CFG_DEV2_EPF6_0_MAX_LATENCY |
49056 | #define BIF_CFG_DEV2_EPF6_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
49057 | #define BIF_CFG_DEV2_EPF6_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
49058 | //BIF_CFG_DEV2_EPF6_0_VENDOR_CAP_LIST |
49059 | #define BIF_CFG_DEV2_EPF6_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
49060 | #define BIF_CFG_DEV2_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
49061 | #define BIF_CFG_DEV2_EPF6_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
49062 | #define BIF_CFG_DEV2_EPF6_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
49063 | #define BIF_CFG_DEV2_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
49064 | #define BIF_CFG_DEV2_EPF6_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
49065 | //BIF_CFG_DEV2_EPF6_0_ADAPTER_ID_W |
49066 | #define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
49067 | #define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
49068 | #define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
49069 | #define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
49070 | //BIF_CFG_DEV2_EPF6_0_PMI_CAP_LIST |
49071 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
49072 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
49073 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
49074 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
49075 | //BIF_CFG_DEV2_EPF6_0_PMI_CAP |
49076 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__VERSION__SHIFT 0x0 |
49077 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
49078 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
49079 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
49080 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
49081 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
49082 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
49083 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
49084 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__VERSION_MASK 0x0007L |
49085 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
49086 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
49087 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
49088 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
49089 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
49090 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
49091 | #define BIF_CFG_DEV2_EPF6_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
49092 | //BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL |
49093 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
49094 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
49095 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
49096 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
49097 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
49098 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
49099 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
49100 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
49101 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
49102 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
49103 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
49104 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
49105 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
49106 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
49107 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
49108 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
49109 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
49110 | #define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
49111 | //BIF_CFG_DEV2_EPF6_0_PCIE_CAP_LIST |
49112 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
49113 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
49114 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
49115 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
49116 | //BIF_CFG_DEV2_EPF6_0_PCIE_CAP |
49117 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__VERSION__SHIFT 0x0 |
49118 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
49119 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
49120 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
49121 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__VERSION_MASK 0x000FL |
49122 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
49123 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
49124 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
49125 | //BIF_CFG_DEV2_EPF6_0_DEVICE_CAP |
49126 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
49127 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
49128 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
49129 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
49130 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
49131 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
49132 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
49133 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
49134 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
49135 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
49136 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
49137 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
49138 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
49139 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
49140 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
49141 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
49142 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
49143 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
49144 | //BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL |
49145 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
49146 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
49147 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
49148 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
49149 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
49150 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
49151 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
49152 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
49153 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
49154 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
49155 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
49156 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
49157 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
49158 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
49159 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
49160 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
49161 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
49162 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
49163 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
49164 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
49165 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
49166 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
49167 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
49168 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
49169 | //BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS |
49170 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
49171 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
49172 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
49173 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
49174 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
49175 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
49176 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
49177 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
49178 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
49179 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
49180 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
49181 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
49182 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
49183 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
49184 | //BIF_CFG_DEV2_EPF6_0_LINK_CAP |
49185 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
49186 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
49187 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
49188 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
49189 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
49190 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
49191 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
49192 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
49193 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
49194 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
49195 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
49196 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
49197 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
49198 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
49199 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
49200 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
49201 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
49202 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
49203 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
49204 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
49205 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
49206 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
49207 | //BIF_CFG_DEV2_EPF6_0_LINK_CNTL |
49208 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
49209 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 |
49210 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
49211 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
49212 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
49213 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
49214 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
49215 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
49216 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
49217 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
49218 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
49219 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
49220 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
49221 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L |
49222 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
49223 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
49224 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
49225 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
49226 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
49227 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
49228 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
49229 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
49230 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
49231 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
49232 | //BIF_CFG_DEV2_EPF6_0_LINK_STATUS |
49233 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
49234 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
49235 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
49236 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
49237 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
49238 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
49239 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
49240 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
49241 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
49242 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
49243 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
49244 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
49245 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
49246 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
49247 | //BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2 |
49248 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
49249 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
49250 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
49251 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
49252 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
49253 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
49254 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
49255 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
49256 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
49257 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
49258 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
49259 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
49260 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
49261 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
49262 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
49263 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
49264 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
49265 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
49266 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
49267 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
49268 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
49269 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
49270 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
49271 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
49272 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
49273 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
49274 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
49275 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
49276 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
49277 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
49278 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
49279 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
49280 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
49281 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
49282 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
49283 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
49284 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
49285 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
49286 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
49287 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
49288 | //BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2 |
49289 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
49290 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
49291 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
49292 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
49293 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
49294 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
49295 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
49296 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
49297 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
49298 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
49299 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
49300 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
49301 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
49302 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
49303 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
49304 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
49305 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
49306 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
49307 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
49308 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
49309 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
49310 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
49311 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
49312 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
49313 | //BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS2 |
49314 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
49315 | #define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
49316 | //BIF_CFG_DEV2_EPF6_0_LINK_CAP2 |
49317 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
49318 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
49319 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
49320 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
49321 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
49322 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
49323 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
49324 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
49325 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
49326 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
49327 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
49328 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
49329 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
49330 | #define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
49331 | //BIF_CFG_DEV2_EPF6_0_LINK_CNTL2 |
49332 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
49333 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
49334 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
49335 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
49336 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
49337 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
49338 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
49339 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
49340 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
49341 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
49342 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
49343 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
49344 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
49345 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
49346 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
49347 | #define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
49348 | //BIF_CFG_DEV2_EPF6_0_LINK_STATUS2 |
49349 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
49350 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
49351 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
49352 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
49353 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
49354 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
49355 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
49356 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
49357 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
49358 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
49359 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
49360 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
49361 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
49362 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
49363 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
49364 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
49365 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
49366 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
49367 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
49368 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
49369 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
49370 | #define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
49371 | //BIF_CFG_DEV2_EPF6_0_MSI_CAP_LIST |
49372 | #define BIF_CFG_DEV2_EPF6_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
49373 | #define BIF_CFG_DEV2_EPF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
49374 | #define BIF_CFG_DEV2_EPF6_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
49375 | #define BIF_CFG_DEV2_EPF6_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
49376 | //BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL |
49377 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
49378 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
49379 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
49380 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
49381 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
49382 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 |
49383 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa |
49384 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
49385 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
49386 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
49387 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
49388 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
49389 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L |
49390 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L |
49391 | //BIF_CFG_DEV2_EPF6_0_MSI_MSG_ADDR_LO |
49392 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
49393 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
49394 | //BIF_CFG_DEV2_EPF6_0_MSI_MSG_ADDR_HI |
49395 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
49396 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
49397 | //BIF_CFG_DEV2_EPF6_0_MSI_MSG_DATA |
49398 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
49399 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
49400 | //BIF_CFG_DEV2_EPF6_0_MSI_EXT_MSG_DATA |
49401 | #define BIF_CFG_DEV2_EPF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 |
49402 | #define BIF_CFG_DEV2_EPF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL |
49403 | //BIF_CFG_DEV2_EPF6_0_MSI_MASK |
49404 | #define BIF_CFG_DEV2_EPF6_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
49405 | #define BIF_CFG_DEV2_EPF6_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
49406 | //BIF_CFG_DEV2_EPF6_0_MSI_MSG_DATA_64 |
49407 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
49408 | #define BIF_CFG_DEV2_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
49409 | //BIF_CFG_DEV2_EPF6_0_MSI_EXT_MSG_DATA_64 |
49410 | #define BIF_CFG_DEV2_EPF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 |
49411 | #define BIF_CFG_DEV2_EPF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL |
49412 | //BIF_CFG_DEV2_EPF6_0_MSI_MASK_64 |
49413 | #define BIF_CFG_DEV2_EPF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
49414 | #define BIF_CFG_DEV2_EPF6_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
49415 | //BIF_CFG_DEV2_EPF6_0_MSI_PENDING |
49416 | #define BIF_CFG_DEV2_EPF6_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
49417 | #define BIF_CFG_DEV2_EPF6_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
49418 | //BIF_CFG_DEV2_EPF6_0_MSI_PENDING_64 |
49419 | #define BIF_CFG_DEV2_EPF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
49420 | #define BIF_CFG_DEV2_EPF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
49421 | //BIF_CFG_DEV2_EPF6_0_MSIX_CAP_LIST |
49422 | #define BIF_CFG_DEV2_EPF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
49423 | #define BIF_CFG_DEV2_EPF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
49424 | #define BIF_CFG_DEV2_EPF6_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
49425 | #define BIF_CFG_DEV2_EPF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
49426 | //BIF_CFG_DEV2_EPF6_0_MSIX_MSG_CNTL |
49427 | #define BIF_CFG_DEV2_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
49428 | #define BIF_CFG_DEV2_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
49429 | #define BIF_CFG_DEV2_EPF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
49430 | #define BIF_CFG_DEV2_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
49431 | #define BIF_CFG_DEV2_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
49432 | #define BIF_CFG_DEV2_EPF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
49433 | //BIF_CFG_DEV2_EPF6_0_MSIX_TABLE |
49434 | #define BIF_CFG_DEV2_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
49435 | #define BIF_CFG_DEV2_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
49436 | #define BIF_CFG_DEV2_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
49437 | #define BIF_CFG_DEV2_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
49438 | //BIF_CFG_DEV2_EPF6_0_MSIX_PBA |
49439 | #define BIF_CFG_DEV2_EPF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
49440 | #define BIF_CFG_DEV2_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
49441 | #define BIF_CFG_DEV2_EPF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
49442 | #define BIF_CFG_DEV2_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
49443 | //BIF_CFG_DEV2_EPF6_0_SATA_CAP_0 |
49444 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
49445 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
49446 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
49447 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
49448 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
49449 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
49450 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
49451 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
49452 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
49453 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
49454 | //BIF_CFG_DEV2_EPF6_0_SATA_CAP_1 |
49455 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
49456 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
49457 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
49458 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
49459 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
49460 | #define BIF_CFG_DEV2_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
49461 | //BIF_CFG_DEV2_EPF6_0_SATA_IDP_INDEX |
49462 | #define BIF_CFG_DEV2_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
49463 | #define BIF_CFG_DEV2_EPF6_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
49464 | #define BIF_CFG_DEV2_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
49465 | #define BIF_CFG_DEV2_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
49466 | #define BIF_CFG_DEV2_EPF6_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
49467 | #define BIF_CFG_DEV2_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
49468 | //BIF_CFG_DEV2_EPF6_0_SATA_IDP_DATA |
49469 | #define BIF_CFG_DEV2_EPF6_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
49470 | #define BIF_CFG_DEV2_EPF6_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
49471 | //BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
49472 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49473 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49474 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49475 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49476 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49477 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49478 | //BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR |
49479 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
49480 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
49481 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
49482 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
49483 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
49484 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
49485 | //BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC1 |
49486 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
49487 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
49488 | //BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC2 |
49489 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
49490 | #define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
49491 | //BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
49492 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49493 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49494 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49495 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49496 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49497 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49498 | //BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS |
49499 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
49500 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
49501 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
49502 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
49503 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
49504 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
49505 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
49506 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
49507 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
49508 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
49509 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
49510 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
49511 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
49512 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
49513 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
49514 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
49515 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
49516 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
49517 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
49518 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
49519 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
49520 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
49521 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
49522 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
49523 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
49524 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
49525 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
49526 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
49527 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
49528 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
49529 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
49530 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
49531 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
49532 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
49533 | //BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK |
49534 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
49535 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
49536 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
49537 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
49538 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
49539 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
49540 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
49541 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
49542 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
49543 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
49544 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
49545 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
49546 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
49547 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
49548 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
49549 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
49550 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
49551 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
49552 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
49553 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
49554 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
49555 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
49556 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
49557 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
49558 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
49559 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
49560 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
49561 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
49562 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
49563 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
49564 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
49565 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
49566 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
49567 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
49568 | //BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY |
49569 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
49570 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
49571 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
49572 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
49573 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
49574 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
49575 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
49576 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
49577 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
49578 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
49579 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
49580 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
49581 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
49582 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
49583 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
49584 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
49585 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
49586 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
49587 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
49588 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
49589 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
49590 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
49591 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
49592 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
49593 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
49594 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
49595 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
49596 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
49597 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
49598 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
49599 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
49600 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
49601 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
49602 | #define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
49603 | //BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS |
49604 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
49605 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
49606 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
49607 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
49608 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
49609 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
49610 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
49611 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
49612 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
49613 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
49614 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
49615 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
49616 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
49617 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
49618 | //BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK |
49619 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
49620 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
49621 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
49622 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
49623 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
49624 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
49625 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
49626 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
49627 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
49628 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
49629 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
49630 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
49631 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
49632 | #define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
49633 | //BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL |
49634 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
49635 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
49636 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
49637 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
49638 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
49639 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
49640 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
49641 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
49642 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
49643 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
49644 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
49645 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
49646 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
49647 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
49648 | //BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG0 |
49649 | #define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
49650 | #define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
49651 | //BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG1 |
49652 | #define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
49653 | #define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
49654 | //BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG2 |
49655 | #define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
49656 | #define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
49657 | //BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG3 |
49658 | #define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
49659 | #define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
49660 | //BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG0 |
49661 | #define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
49662 | #define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
49663 | //BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG1 |
49664 | #define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
49665 | #define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
49666 | //BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG2 |
49667 | #define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
49668 | #define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
49669 | //BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG3 |
49670 | #define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
49671 | #define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
49672 | //BIF_CFG_DEV2_EPF6_0_PCIE_BAR_ENH_CAP_LIST |
49673 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49674 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49675 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49676 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49677 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49678 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49679 | //BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CAP |
49680 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
49681 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
49682 | //BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL |
49683 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
49684 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
49685 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
49686 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
49687 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
49688 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
49689 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
49690 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
49691 | //BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CAP |
49692 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
49693 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
49694 | //BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL |
49695 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
49696 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
49697 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
49698 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
49699 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
49700 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
49701 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
49702 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
49703 | //BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CAP |
49704 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
49705 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
49706 | //BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL |
49707 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
49708 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
49709 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
49710 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
49711 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
49712 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
49713 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
49714 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
49715 | //BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CAP |
49716 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
49717 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
49718 | //BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL |
49719 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
49720 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
49721 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
49722 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
49723 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
49724 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
49725 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
49726 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
49727 | //BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CAP |
49728 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
49729 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
49730 | //BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL |
49731 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
49732 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
49733 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
49734 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
49735 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
49736 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
49737 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
49738 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
49739 | //BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CAP |
49740 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
49741 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
49742 | //BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL |
49743 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
49744 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
49745 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
49746 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 |
49747 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
49748 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
49749 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
49750 | #define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L |
49751 | //BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
49752 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49753 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49754 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49755 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49756 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49757 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49758 | //BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT |
49759 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
49760 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
49761 | //BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA |
49762 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
49763 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
49764 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
49765 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
49766 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
49767 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
49768 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
49769 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
49770 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
49771 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
49772 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
49773 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
49774 | //BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_CAP |
49775 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
49776 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
49777 | //BIF_CFG_DEV2_EPF6_0_PCIE_DPA_ENH_CAP_LIST |
49778 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49779 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49780 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49781 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49782 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49783 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49784 | //BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP |
49785 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
49786 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
49787 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
49788 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
49789 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
49790 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
49791 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
49792 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
49793 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
49794 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
49795 | //BIF_CFG_DEV2_EPF6_0_PCIE_DPA_LATENCY_INDICATOR |
49796 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
49797 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
49798 | //BIF_CFG_DEV2_EPF6_0_PCIE_DPA_STATUS |
49799 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
49800 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
49801 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
49802 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
49803 | //BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CNTL |
49804 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
49805 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
49806 | //BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
49807 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49808 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49809 | //BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
49810 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49811 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49812 | //BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
49813 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49814 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49815 | //BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
49816 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49817 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49818 | //BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
49819 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49820 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49821 | //BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
49822 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49823 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49824 | //BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
49825 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49826 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49827 | //BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
49828 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
49829 | #define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
49830 | //BIF_CFG_DEV2_EPF6_0_PCIE_ACS_ENH_CAP_LIST |
49831 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49832 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49833 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49834 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49835 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49836 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49837 | //BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP |
49838 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
49839 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
49840 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
49841 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
49842 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
49843 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
49844 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
49845 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
49846 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
49847 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
49848 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
49849 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
49850 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
49851 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
49852 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
49853 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
49854 | //BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL |
49855 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
49856 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
49857 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
49858 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
49859 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
49860 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
49861 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
49862 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
49863 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
49864 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
49865 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
49866 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
49867 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
49868 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
49869 | //BIF_CFG_DEV2_EPF6_0_PCIE_PASID_ENH_CAP_LIST |
49870 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49871 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49872 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49873 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49874 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49875 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49876 | //BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CAP |
49877 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
49878 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
49879 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
49880 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
49881 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
49882 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
49883 | //BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CNTL |
49884 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
49885 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
49886 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
49887 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
49888 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
49889 | #define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
49890 | //BIF_CFG_DEV2_EPF6_0_PCIE_ARI_ENH_CAP_LIST |
49891 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49892 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49893 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49894 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49895 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49896 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49897 | //BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CAP |
49898 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
49899 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
49900 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
49901 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
49902 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
49903 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
49904 | //BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CNTL |
49905 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
49906 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
49907 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
49908 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
49909 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
49910 | #define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
49911 | //BIF_CFG_DEV2_EPF6_0_PCIE_RTR_ENH_CAP_LIST |
49912 | #define BIF_CFG_DEV2_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
49913 | #define BIF_CFG_DEV2_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
49914 | #define BIF_CFG_DEV2_EPF6_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
49915 | #define BIF_CFG_DEV2_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
49916 | #define BIF_CFG_DEV2_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
49917 | #define BIF_CFG_DEV2_EPF6_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
49918 | //BIF_CFG_DEV2_EPF6_0_RTR_DATA1 |
49919 | #define BIF_CFG_DEV2_EPF6_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 |
49920 | #define BIF_CFG_DEV2_EPF6_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc |
49921 | #define BIF_CFG_DEV2_EPF6_0_RTR_DATA1__VALID__SHIFT 0x1f |
49922 | #define BIF_CFG_DEV2_EPF6_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL |
49923 | #define BIF_CFG_DEV2_EPF6_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L |
49924 | #define BIF_CFG_DEV2_EPF6_0_RTR_DATA1__VALID_MASK 0x80000000L |
49925 | //BIF_CFG_DEV2_EPF6_0_RTR_DATA2 |
49926 | #define BIF_CFG_DEV2_EPF6_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 |
49927 | #define BIF_CFG_DEV2_EPF6_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc |
49928 | #define BIF_CFG_DEV2_EPF6_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL |
49929 | #define BIF_CFG_DEV2_EPF6_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L |
49930 | |
49931 | |
49932 | // addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC |
49933 | //RCC_EP_DEV0_0_EP_PCIE_SCRATCH |
49934 | #define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
49935 | #define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
49936 | //RCC_EP_DEV0_0_EP_PCIE_CNTL |
49937 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
49938 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
49939 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
49940 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
49941 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
49942 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
49943 | //RCC_EP_DEV0_0_EP_PCIE_INT_CNTL |
49944 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 |
49945 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 |
49946 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 |
49947 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 |
49948 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 |
49949 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 |
49950 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L |
49951 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L |
49952 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L |
49953 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L |
49954 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L |
49955 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L |
49956 | //RCC_EP_DEV0_0_EP_PCIE_INT_STATUS |
49957 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 |
49958 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 |
49959 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 |
49960 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 |
49961 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 |
49962 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 |
49963 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 |
49964 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L |
49965 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L |
49966 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L |
49967 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L |
49968 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L |
49969 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L |
49970 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L |
49971 | //RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 |
49972 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
49973 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
49974 | //RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL |
49975 | #define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
49976 | #define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
49977 | //RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL |
49978 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
49979 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
49980 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
49981 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
49982 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 |
49983 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
49984 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
49985 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
49986 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
49987 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L |
49988 | //RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL |
49989 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 |
49990 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 |
49991 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 |
49992 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 |
49993 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa |
49994 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd |
49995 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe |
49996 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf |
49997 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 |
49998 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 |
49999 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L |
50000 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L |
50001 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L |
50002 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L |
50003 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L |
50004 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L |
50005 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L |
50006 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L |
50007 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L |
50008 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L |
50009 | //RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP |
50010 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
50011 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
50012 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
50013 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
50014 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
50015 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
50016 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
50017 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
50018 | //RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR |
50019 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
50020 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
50021 | //RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL |
50022 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 |
50023 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 |
50024 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL |
50025 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L |
50026 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 |
50027 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50028 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50029 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 |
50030 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50031 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50032 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 |
50033 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50034 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50035 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 |
50036 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50037 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50038 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 |
50039 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50040 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50041 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 |
50042 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50043 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50044 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 |
50045 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50046 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50047 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 |
50048 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50049 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50050 | //RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL |
50051 | #define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 |
50052 | #define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL |
50053 | //RCC_EP_DEV0_0_EP_PCIEP_RESERVED |
50054 | #define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
50055 | #define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
50056 | //RCC_EP_DEV0_0_EP_PCIE_TX_CNTL |
50057 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
50058 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
50059 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 |
50060 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 |
50061 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a |
50062 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
50063 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
50064 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L |
50065 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L |
50066 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L |
50067 | //RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID |
50068 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
50069 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
50070 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
50071 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
50072 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
50073 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
50074 | //RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL |
50075 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
50076 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
50077 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
50078 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
50079 | //RCC_EP_DEV0_0_EP_PCIE_RX_CNTL |
50080 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
50081 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
50082 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
50083 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
50084 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
50085 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
50086 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
50087 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
50088 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
50089 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
50090 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
50091 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
50092 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
50093 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
50094 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
50095 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
50096 | //RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL |
50097 | |
50098 | |
50099 | // addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC |
50100 | //RCC_DWN_DEV0_0_DN_PCIE_RESERVED |
50101 | #define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
50102 | #define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL |
50103 | //RCC_DWN_DEV0_0_DN_PCIE_SCRATCH |
50104 | #define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
50105 | #define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
50106 | //RCC_DWN_DEV0_0_DN_PCIE_CNTL |
50107 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
50108 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 |
50109 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
50110 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
50111 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L |
50112 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
50113 | //RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL |
50114 | #define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
50115 | #define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
50116 | //RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 |
50117 | #define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
50118 | #define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
50119 | //RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL |
50120 | #define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
50121 | #define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 |
50122 | #define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
50123 | #define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L |
50124 | //RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL |
50125 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
50126 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
50127 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
50128 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
50129 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 |
50130 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
50131 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
50132 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
50133 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
50134 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L |
50135 | |
50136 | |
50137 | // addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC |
50138 | //RCC_DWNP_DEV0_0_PCIE_ERR_CNTL |
50139 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
50140 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
50141 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 |
50142 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 |
50143 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 |
50144 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
50145 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
50146 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L |
50147 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L |
50148 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L |
50149 | //RCC_DWNP_DEV0_0_PCIE_RX_CNTL |
50150 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
50151 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 |
50152 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
50153 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 |
50154 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
50155 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
50156 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L |
50157 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
50158 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L |
50159 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
50160 | //RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL |
50161 | //RCC_DWNP_DEV0_0_PCIE_LC_CNTL2 |
50162 | #define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 |
50163 | #define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
50164 | #define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L |
50165 | #define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
50166 | //RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP |
50167 | #define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 |
50168 | #define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL |
50169 | |
50170 | |
50171 | // addressBlock: nbio_nbif0_rcc_ep_dev1_RCCPORTDEC |
50172 | //RCC_EP_DEV1_EP_PCIE_SCRATCH |
50173 | #define RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
50174 | #define RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
50175 | //RCC_EP_DEV1_EP_PCIE_CNTL |
50176 | #define RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
50177 | #define RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
50178 | #define RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
50179 | #define RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
50180 | #define RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
50181 | #define RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
50182 | //RCC_EP_DEV1_EP_PCIE_INT_CNTL |
50183 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 |
50184 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 |
50185 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 |
50186 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 |
50187 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 |
50188 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 |
50189 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L |
50190 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L |
50191 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L |
50192 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L |
50193 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L |
50194 | #define RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L |
50195 | //RCC_EP_DEV1_EP_PCIE_INT_STATUS |
50196 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 |
50197 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 |
50198 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 |
50199 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 |
50200 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 |
50201 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 |
50202 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 |
50203 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L |
50204 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L |
50205 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L |
50206 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L |
50207 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L |
50208 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L |
50209 | #define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L |
50210 | //RCC_EP_DEV1_EP_PCIE_RX_CNTL2 |
50211 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
50212 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
50213 | //RCC_EP_DEV1_EP_PCIE_BUS_CNTL |
50214 | #define RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
50215 | #define RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
50216 | //RCC_EP_DEV1_EP_PCIE_CFG_CNTL |
50217 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
50218 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
50219 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
50220 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
50221 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 |
50222 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
50223 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
50224 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
50225 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
50226 | #define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L |
50227 | //RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL |
50228 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 |
50229 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 |
50230 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 |
50231 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 |
50232 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa |
50233 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd |
50234 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe |
50235 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf |
50236 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 |
50237 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 |
50238 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L |
50239 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L |
50240 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L |
50241 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L |
50242 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L |
50243 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L |
50244 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L |
50245 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L |
50246 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L |
50247 | #define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L |
50248 | //RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP |
50249 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
50250 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
50251 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
50252 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
50253 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
50254 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
50255 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
50256 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
50257 | //RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR |
50258 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
50259 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
50260 | //RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL |
50261 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 |
50262 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 |
50263 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL |
50264 | #define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L |
50265 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 |
50266 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50267 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50268 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 |
50269 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50270 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50271 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 |
50272 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50273 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50274 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 |
50275 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50276 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50277 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 |
50278 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50279 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50280 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 |
50281 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50282 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50283 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 |
50284 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50285 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50286 | //RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 |
50287 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50288 | #define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50289 | //RCC_EP_DEV1_EP_PCIE_PME_CONTROL |
50290 | #define RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 |
50291 | #define RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL |
50292 | //RCC_EP_DEV1_EP_PCIEP_RESERVED |
50293 | #define RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
50294 | #define RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
50295 | //RCC_EP_DEV1_EP_PCIE_TX_CNTL |
50296 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
50297 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
50298 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 |
50299 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 |
50300 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a |
50301 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
50302 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
50303 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L |
50304 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L |
50305 | #define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L |
50306 | //RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID |
50307 | #define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
50308 | #define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
50309 | #define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
50310 | #define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
50311 | #define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
50312 | #define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
50313 | //RCC_EP_DEV1_EP_PCIE_ERR_CNTL |
50314 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
50315 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
50316 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
50317 | #define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
50318 | //RCC_EP_DEV1_EP_PCIE_RX_CNTL |
50319 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
50320 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
50321 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
50322 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
50323 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
50324 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
50325 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
50326 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
50327 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
50328 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
50329 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
50330 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
50331 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
50332 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
50333 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
50334 | #define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
50335 | //RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL |
50336 | |
50337 | |
50338 | // addressBlock: nbio_nbif0_rcc_dwn_dev1_RCCPORTDEC |
50339 | //RCC_DWN_DEV1_DN_PCIE_RESERVED |
50340 | #define RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
50341 | #define RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL |
50342 | //RCC_DWN_DEV1_DN_PCIE_SCRATCH |
50343 | #define RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
50344 | #define RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
50345 | //RCC_DWN_DEV1_DN_PCIE_CNTL |
50346 | #define RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
50347 | #define RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 |
50348 | #define RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
50349 | #define RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
50350 | #define RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L |
50351 | #define RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
50352 | //RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL |
50353 | #define RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
50354 | #define RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
50355 | //RCC_DWN_DEV1_DN_PCIE_RX_CNTL2 |
50356 | #define RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
50357 | #define RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
50358 | //RCC_DWN_DEV1_DN_PCIE_BUS_CNTL |
50359 | #define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
50360 | #define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 |
50361 | #define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
50362 | #define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L |
50363 | //RCC_DWN_DEV1_DN_PCIE_CFG_CNTL |
50364 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
50365 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
50366 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
50367 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
50368 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 |
50369 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
50370 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
50371 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
50372 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
50373 | #define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L |
50374 | |
50375 | |
50376 | // addressBlock: nbio_nbif0_rcc_dwnp_dev1_RCCPORTDEC |
50377 | //RCC_DWNP_DEV1_PCIE_ERR_CNTL |
50378 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
50379 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
50380 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 |
50381 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 |
50382 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 |
50383 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
50384 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
50385 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L |
50386 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L |
50387 | #define RCC_DWNP_DEV1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L |
50388 | //RCC_DWNP_DEV1_PCIE_RX_CNTL |
50389 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
50390 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 |
50391 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
50392 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 |
50393 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
50394 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
50395 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L |
50396 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
50397 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L |
50398 | #define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
50399 | //RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL |
50400 | //RCC_DWNP_DEV1_PCIE_LC_CNTL2 |
50401 | #define RCC_DWNP_DEV1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 |
50402 | #define RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
50403 | #define RCC_DWNP_DEV1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L |
50404 | #define RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
50405 | //RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP |
50406 | #define RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 |
50407 | #define RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL |
50408 | |
50409 | |
50410 | // addressBlock: nbio_nbif0_rcc_ep_dev2_RCCPORTDEC |
50411 | //RCC_EP_DEV2_EP_PCIE_SCRATCH |
50412 | #define RCC_EP_DEV2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
50413 | #define RCC_EP_DEV2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
50414 | //RCC_EP_DEV2_EP_PCIE_CNTL |
50415 | #define RCC_EP_DEV2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
50416 | #define RCC_EP_DEV2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
50417 | #define RCC_EP_DEV2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
50418 | #define RCC_EP_DEV2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
50419 | #define RCC_EP_DEV2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
50420 | #define RCC_EP_DEV2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
50421 | //RCC_EP_DEV2_EP_PCIE_INT_CNTL |
50422 | #define RCC_EP_DEV2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 |
50423 | #define RCC_EP_DEV2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 |
50424 | #define RCC_EP_DEV2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 |
50425 | #define RCC_EP_DEV2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 |
50426 | #define RCC_EP_DEV2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 |
50427 | #define RCC_EP_DEV2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 |
50428 | #define RCC_EP_DEV2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L |
50429 | #define RCC_EP_DEV2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L |
50430 | #define RCC_EP_DEV2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L |
50431 | #define RCC_EP_DEV2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L |
50432 | #define RCC_EP_DEV2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L |
50433 | #define RCC_EP_DEV2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L |
50434 | //RCC_EP_DEV2_EP_PCIE_INT_STATUS |
50435 | #define RCC_EP_DEV2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 |
50436 | #define RCC_EP_DEV2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 |
50437 | #define RCC_EP_DEV2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 |
50438 | #define RCC_EP_DEV2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 |
50439 | #define RCC_EP_DEV2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 |
50440 | #define RCC_EP_DEV2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 |
50441 | #define RCC_EP_DEV2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 |
50442 | #define RCC_EP_DEV2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L |
50443 | #define RCC_EP_DEV2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L |
50444 | #define RCC_EP_DEV2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L |
50445 | #define RCC_EP_DEV2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L |
50446 | #define RCC_EP_DEV2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L |
50447 | #define RCC_EP_DEV2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L |
50448 | #define RCC_EP_DEV2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L |
50449 | //RCC_EP_DEV2_EP_PCIE_RX_CNTL2 |
50450 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
50451 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
50452 | //RCC_EP_DEV2_EP_PCIE_BUS_CNTL |
50453 | #define RCC_EP_DEV2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
50454 | #define RCC_EP_DEV2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
50455 | //RCC_EP_DEV2_EP_PCIE_CFG_CNTL |
50456 | #define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
50457 | #define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
50458 | #define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
50459 | #define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
50460 | #define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 |
50461 | #define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
50462 | #define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
50463 | #define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
50464 | #define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
50465 | #define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L |
50466 | //RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL |
50467 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 |
50468 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 |
50469 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 |
50470 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 |
50471 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa |
50472 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd |
50473 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe |
50474 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf |
50475 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 |
50476 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 |
50477 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L |
50478 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L |
50479 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L |
50480 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L |
50481 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L |
50482 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L |
50483 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L |
50484 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L |
50485 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L |
50486 | #define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L |
50487 | //RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP |
50488 | #define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
50489 | #define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
50490 | #define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
50491 | #define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
50492 | #define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
50493 | #define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
50494 | #define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
50495 | #define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
50496 | //RCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR |
50497 | #define RCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
50498 | #define RCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
50499 | //RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL |
50500 | #define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 |
50501 | #define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 |
50502 | #define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL |
50503 | #define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L |
50504 | //RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 |
50505 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50506 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50507 | //RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 |
50508 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50509 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50510 | //RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 |
50511 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50512 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50513 | //RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 |
50514 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50515 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50516 | //RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 |
50517 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50518 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50519 | //RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 |
50520 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50521 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50522 | //RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 |
50523 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50524 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50525 | //RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 |
50526 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
50527 | #define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
50528 | //RCC_EP_DEV2_EP_PCIE_PME_CONTROL |
50529 | #define RCC_EP_DEV2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 |
50530 | #define RCC_EP_DEV2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL |
50531 | //RCC_EP_DEV2_EP_PCIEP_RESERVED |
50532 | #define RCC_EP_DEV2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
50533 | #define RCC_EP_DEV2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
50534 | //RCC_EP_DEV2_EP_PCIE_TX_CNTL |
50535 | #define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
50536 | #define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
50537 | #define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 |
50538 | #define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 |
50539 | #define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a |
50540 | #define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
50541 | #define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
50542 | #define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L |
50543 | #define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L |
50544 | #define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L |
50545 | //RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID |
50546 | #define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
50547 | #define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
50548 | #define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
50549 | #define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
50550 | #define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
50551 | #define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
50552 | //RCC_EP_DEV2_EP_PCIE_ERR_CNTL |
50553 | #define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
50554 | #define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
50555 | #define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
50556 | #define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
50557 | //RCC_EP_DEV2_EP_PCIE_RX_CNTL |
50558 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
50559 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
50560 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
50561 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
50562 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
50563 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
50564 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
50565 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
50566 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
50567 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
50568 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
50569 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
50570 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
50571 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
50572 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
50573 | #define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
50574 | //RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL |
50575 | |
50576 | |
50577 | // addressBlock: nbio_nbif0_rcc_dwn_dev2_RCCPORTDEC |
50578 | //RCC_DWN_DEV2_DN_PCIE_RESERVED |
50579 | #define RCC_DWN_DEV2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
50580 | #define RCC_DWN_DEV2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL |
50581 | //RCC_DWN_DEV2_DN_PCIE_SCRATCH |
50582 | #define RCC_DWN_DEV2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
50583 | #define RCC_DWN_DEV2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
50584 | //RCC_DWN_DEV2_DN_PCIE_CNTL |
50585 | #define RCC_DWN_DEV2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
50586 | #define RCC_DWN_DEV2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 |
50587 | #define RCC_DWN_DEV2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
50588 | #define RCC_DWN_DEV2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
50589 | #define RCC_DWN_DEV2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L |
50590 | #define RCC_DWN_DEV2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
50591 | //RCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL |
50592 | #define RCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
50593 | #define RCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
50594 | //RCC_DWN_DEV2_DN_PCIE_RX_CNTL2 |
50595 | #define RCC_DWN_DEV2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
50596 | #define RCC_DWN_DEV2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
50597 | //RCC_DWN_DEV2_DN_PCIE_BUS_CNTL |
50598 | #define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
50599 | #define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 |
50600 | #define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
50601 | #define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L |
50602 | //RCC_DWN_DEV2_DN_PCIE_CFG_CNTL |
50603 | #define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
50604 | #define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
50605 | #define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
50606 | #define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
50607 | #define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 |
50608 | #define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
50609 | #define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
50610 | #define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
50611 | #define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
50612 | #define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L |
50613 | |
50614 | |
50615 | // addressBlock: nbio_nbif0_rcc_dwnp_dev2_RCCPORTDEC |
50616 | //RCC_DWNP_DEV2_PCIE_ERR_CNTL |
50617 | #define RCC_DWNP_DEV2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
50618 | #define RCC_DWNP_DEV2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
50619 | #define RCC_DWNP_DEV2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 |
50620 | #define RCC_DWNP_DEV2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 |
50621 | #define RCC_DWNP_DEV2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 |
50622 | #define RCC_DWNP_DEV2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
50623 | #define RCC_DWNP_DEV2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
50624 | #define RCC_DWNP_DEV2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L |
50625 | #define RCC_DWNP_DEV2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L |
50626 | #define RCC_DWNP_DEV2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L |
50627 | //RCC_DWNP_DEV2_PCIE_RX_CNTL |
50628 | #define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
50629 | #define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 |
50630 | #define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
50631 | #define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 |
50632 | #define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
50633 | #define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
50634 | #define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L |
50635 | #define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
50636 | #define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L |
50637 | #define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
50638 | //RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL |
50639 | //RCC_DWNP_DEV2_PCIE_LC_CNTL2 |
50640 | #define RCC_DWNP_DEV2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 |
50641 | #define RCC_DWNP_DEV2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
50642 | #define RCC_DWNP_DEV2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L |
50643 | #define RCC_DWNP_DEV2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
50644 | //RCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP |
50645 | #define RCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 |
50646 | #define RCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL |
50647 | |
50648 | |
50649 | // addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal |
50650 | //RCC_STRAP0_RCC_DEV0_EPF0_STRAP0 |
50651 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 |
50652 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 |
50653 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 |
50654 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 |
50655 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c |
50656 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d |
50657 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e |
50658 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f |
50659 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL |
50660 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L |
50661 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L |
50662 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L |
50663 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L |
50664 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L |
50665 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L |
50666 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L |
50667 | |
50668 | |
50669 | // addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk |
50670 | //HARD_RST_CTRL |
50671 | #define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 |
50672 | #define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 |
50673 | #define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 |
50674 | #define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 |
50675 | #define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 |
50676 | #define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 |
50677 | #define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 |
50678 | #define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 |
50679 | #define HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x9 |
50680 | #define HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0xa |
50681 | #define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d |
50682 | #define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f |
50683 | #define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L |
50684 | #define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L |
50685 | #define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L |
50686 | #define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L |
50687 | #define HARD_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L |
50688 | #define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L |
50689 | #define HARD_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L |
50690 | #define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L |
50691 | #define HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000200L |
50692 | #define HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000400L |
50693 | #define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L |
50694 | #define HARD_RST_CTRL__CORE_RST_EN_MASK 0x80000000L |
50695 | //SELF_SOFT_RST |
50696 | #define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0 |
50697 | #define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1 |
50698 | #define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2 |
50699 | #define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3 |
50700 | #define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4 |
50701 | #define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5 |
50702 | #define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6 |
50703 | #define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7 |
50704 | #define SELF_SOFT_RST__DSPT1_CFG_RST__SHIFT 0x8 |
50705 | #define SELF_SOFT_RST__DSPT1_CFG_STICKY_RST__SHIFT 0x9 |
50706 | #define SELF_SOFT_RST__DSPT1_PRV_RST__SHIFT 0xa |
50707 | #define SELF_SOFT_RST__DSPT1_PRV_STICKY_RST__SHIFT 0xb |
50708 | #define SELF_SOFT_RST__EP1_CFG_RST__SHIFT 0xc |
50709 | #define SELF_SOFT_RST__EP1_CFG_STICKY_RST__SHIFT 0xd |
50710 | #define SELF_SOFT_RST__EP1_PRV_RST__SHIFT 0xe |
50711 | #define SELF_SOFT_RST__EP1_PRV_STICKY_RST__SHIFT 0xf |
50712 | #define SELF_SOFT_RST__DSPT2_CFG_RST__SHIFT 0x10 |
50713 | #define SELF_SOFT_RST__DSPT2_CFG_STICKY_RST__SHIFT 0x11 |
50714 | #define SELF_SOFT_RST__DSPT2_PRV_RST__SHIFT 0x12 |
50715 | #define SELF_SOFT_RST__DSPT2_PRV_STICKY_RST__SHIFT 0x13 |
50716 | #define SELF_SOFT_RST__EP2_CFG_RST__SHIFT 0x14 |
50717 | #define SELF_SOFT_RST__EP2_CFG_STICKY_RST__SHIFT 0x15 |
50718 | #define SELF_SOFT_RST__EP2_PRV_RST__SHIFT 0x16 |
50719 | #define SELF_SOFT_RST__EP2_PRV_STICKY_RST__SHIFT 0x17 |
50720 | #define SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT 0x18 |
50721 | #define SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT 0x19 |
50722 | #define SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT 0x1a |
50723 | #define SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT 0x1b |
50724 | #define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d |
50725 | #define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f |
50726 | #define SELF_SOFT_RST__DSPT0_CFG_RST_MASK 0x00000001L |
50727 | #define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK 0x00000002L |
50728 | #define SELF_SOFT_RST__DSPT0_PRV_RST_MASK 0x00000004L |
50729 | #define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK 0x00000008L |
50730 | #define SELF_SOFT_RST__EP0_CFG_RST_MASK 0x00000010L |
50731 | #define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK 0x00000020L |
50732 | #define SELF_SOFT_RST__EP0_PRV_RST_MASK 0x00000040L |
50733 | #define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK 0x00000080L |
50734 | #define SELF_SOFT_RST__DSPT1_CFG_RST_MASK 0x00000100L |
50735 | #define SELF_SOFT_RST__DSPT1_CFG_STICKY_RST_MASK 0x00000200L |
50736 | #define SELF_SOFT_RST__DSPT1_PRV_RST_MASK 0x00000400L |
50737 | #define SELF_SOFT_RST__DSPT1_PRV_STICKY_RST_MASK 0x00000800L |
50738 | #define SELF_SOFT_RST__EP1_CFG_RST_MASK 0x00001000L |
50739 | #define SELF_SOFT_RST__EP1_CFG_STICKY_RST_MASK 0x00002000L |
50740 | #define SELF_SOFT_RST__EP1_PRV_RST_MASK 0x00004000L |
50741 | #define SELF_SOFT_RST__EP1_PRV_STICKY_RST_MASK 0x00008000L |
50742 | #define SELF_SOFT_RST__DSPT2_CFG_RST_MASK 0x00010000L |
50743 | #define SELF_SOFT_RST__DSPT2_CFG_STICKY_RST_MASK 0x00020000L |
50744 | #define SELF_SOFT_RST__DSPT2_PRV_RST_MASK 0x00040000L |
50745 | #define SELF_SOFT_RST__DSPT2_PRV_STICKY_RST_MASK 0x00080000L |
50746 | #define SELF_SOFT_RST__EP2_CFG_RST_MASK 0x00100000L |
50747 | #define SELF_SOFT_RST__EP2_CFG_STICKY_RST_MASK 0x00200000L |
50748 | #define SELF_SOFT_RST__EP2_PRV_RST_MASK 0x00400000L |
50749 | #define SELF_SOFT_RST__EP2_PRV_STICKY_RST_MASK 0x00800000L |
50750 | #define SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK 0x01000000L |
50751 | #define SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK 0x02000000L |
50752 | #define SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK 0x04000000L |
50753 | #define SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK 0x08000000L |
50754 | #define SELF_SOFT_RST__CORE_STICKY_RST_MASK 0x20000000L |
50755 | #define SELF_SOFT_RST__CORE_RST_MASK 0x80000000L |
50756 | //BIF_GFX_DRV_VPU_RST |
50757 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT 0x0 |
50758 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1 |
50759 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2 |
50760 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT 0x3 |
50761 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4 |
50762 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT 0x5 |
50763 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6 |
50764 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT 0x7 |
50765 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK 0x00000001L |
50766 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK 0x00000002L |
50767 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK 0x00000004L |
50768 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK 0x00000008L |
50769 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK 0x00000010L |
50770 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK 0x00000020L |
50771 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK 0x00000040L |
50772 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK 0x00000080L |
50773 | //BIF_RST_MISC_CTRL |
50774 | #define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0 |
50775 | #define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2 |
50776 | #define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4 |
50777 | #define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5 |
50778 | #define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6 |
50779 | #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9 |
50780 | #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa |
50781 | #define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd |
50782 | #define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf |
50783 | #define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11 |
50784 | #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17 |
50785 | #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18 |
50786 | #define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK 0x00000001L |
50787 | #define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK 0x0000000CL |
50788 | #define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK 0x00000010L |
50789 | #define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK 0x00000020L |
50790 | #define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK 0x00000040L |
50791 | #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK 0x00000200L |
50792 | #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK 0x00001C00L |
50793 | #define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK 0x00006000L |
50794 | #define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK 0x00018000L |
50795 | #define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x000E0000L |
50796 | #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK 0x00800000L |
50797 | #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK 0x03000000L |
50798 | //BIF_RST_MISC_CTRL2 |
50799 | #define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10 |
50800 | #define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11 |
50801 | #define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12 |
50802 | #define BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE__SHIFT 0x13 |
50803 | #define BIF_RST_MISC_CTRL2__ENDP2_LNK_RST_TRANS_IDLE__SHIFT 0x14 |
50804 | #define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f |
50805 | #define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK 0x00010000L |
50806 | #define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK 0x00020000L |
50807 | #define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK 0x00040000L |
50808 | #define BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE_MASK 0x00080000L |
50809 | #define BIF_RST_MISC_CTRL2__ENDP2_LNK_RST_TRANS_IDLE_MASK 0x00100000L |
50810 | #define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK 0x80000000L |
50811 | //BIF_RST_MISC_CTRL3 |
50812 | #define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0 |
50813 | #define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4 |
50814 | #define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6 |
50815 | #define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK 0x0000000FL |
50816 | #define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK 0x00000030L |
50817 | #define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK 0x00000040L |
50818 | //DEV0_PF0_FLR_RST_CTRL |
50819 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
50820 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
50821 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
50822 | #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
50823 | #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
50824 | #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
50825 | #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
50826 | #define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
50827 | #define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
50828 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
50829 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
50830 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
50831 | #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
50832 | #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
50833 | #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
50834 | #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
50835 | #define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
50836 | #define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
50837 | //DEV0_PF1_FLR_RST_CTRL |
50838 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
50839 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
50840 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
50841 | #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
50842 | #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
50843 | #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
50844 | #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
50845 | #define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
50846 | #define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
50847 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
50848 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
50849 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
50850 | #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
50851 | #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
50852 | #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
50853 | #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
50854 | #define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
50855 | #define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
50856 | //DEV0_PF2_FLR_RST_CTRL |
50857 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
50858 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
50859 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
50860 | #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
50861 | #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
50862 | #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
50863 | #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
50864 | #define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
50865 | #define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
50866 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
50867 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
50868 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
50869 | #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
50870 | #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
50871 | #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
50872 | #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
50873 | #define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
50874 | #define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
50875 | //DEV0_PF3_FLR_RST_CTRL |
50876 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
50877 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
50878 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
50879 | #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
50880 | #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
50881 | #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
50882 | #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
50883 | #define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
50884 | #define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
50885 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
50886 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
50887 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
50888 | #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
50889 | #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
50890 | #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
50891 | #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
50892 | #define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
50893 | #define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
50894 | //DEV0_PF4_FLR_RST_CTRL |
50895 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
50896 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
50897 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
50898 | #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
50899 | #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
50900 | #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
50901 | #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
50902 | #define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
50903 | #define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
50904 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
50905 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
50906 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
50907 | #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
50908 | #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
50909 | #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
50910 | #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
50911 | #define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
50912 | #define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
50913 | //DEV0_PF5_FLR_RST_CTRL |
50914 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
50915 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
50916 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
50917 | #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
50918 | #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
50919 | #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
50920 | #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
50921 | #define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
50922 | #define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
50923 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
50924 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
50925 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
50926 | #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
50927 | #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
50928 | #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
50929 | #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
50930 | #define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
50931 | #define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
50932 | //DEV0_PF6_FLR_RST_CTRL |
50933 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
50934 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
50935 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
50936 | #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
50937 | #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
50938 | #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
50939 | #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
50940 | #define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
50941 | #define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
50942 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
50943 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
50944 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
50945 | #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
50946 | #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
50947 | #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
50948 | #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
50949 | #define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
50950 | #define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
50951 | //DEV0_PF7_FLR_RST_CTRL |
50952 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
50953 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
50954 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
50955 | #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
50956 | #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
50957 | #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
50958 | #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
50959 | #define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
50960 | #define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
50961 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
50962 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
50963 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
50964 | #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
50965 | #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
50966 | #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
50967 | #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
50968 | #define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
50969 | #define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
50970 | //BIF_INST_RESET_INTR_STS |
50971 | #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0 |
50972 | #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1 |
50973 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2 |
50974 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3 |
50975 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4 |
50976 | #define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS__SHIFT 0x8 |
50977 | #define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x9 |
50978 | #define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_INTR_STS__SHIFT 0xa |
50979 | #define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0xb |
50980 | #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK 0x00000001L |
50981 | #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000002L |
50982 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK 0x00000004L |
50983 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK 0x00000008L |
50984 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK 0x00000010L |
50985 | #define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS_MASK 0x00000100L |
50986 | #define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000200L |
50987 | #define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_INTR_STS_MASK 0x00000400L |
50988 | #define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000800L |
50989 | //BIF_PF_FLR_INTR_STS |
50990 | #define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0 |
50991 | #define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1 |
50992 | #define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2 |
50993 | #define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3 |
50994 | #define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x4 |
50995 | #define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x5 |
50996 | #define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x6 |
50997 | #define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT 0x7 |
50998 | #define BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS__SHIFT 0x8 |
50999 | #define BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS__SHIFT 0x9 |
51000 | #define BIF_PF_FLR_INTR_STS__DEV2_PF0_FLR_INTR_STS__SHIFT 0x10 |
51001 | #define BIF_PF_FLR_INTR_STS__DEV2_PF1_FLR_INTR_STS__SHIFT 0x11 |
51002 | #define BIF_PF_FLR_INTR_STS__DEV2_PF2_FLR_INTR_STS__SHIFT 0x12 |
51003 | #define BIF_PF_FLR_INTR_STS__DEV2_PF3_FLR_INTR_STS__SHIFT 0x13 |
51004 | #define BIF_PF_FLR_INTR_STS__DEV2_PF4_FLR_INTR_STS__SHIFT 0x14 |
51005 | #define BIF_PF_FLR_INTR_STS__DEV2_PF5_FLR_INTR_STS__SHIFT 0x15 |
51006 | #define BIF_PF_FLR_INTR_STS__DEV2_PF6_FLR_INTR_STS__SHIFT 0x16 |
51007 | #define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK 0x00000001L |
51008 | #define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK 0x00000002L |
51009 | #define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK 0x00000004L |
51010 | #define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK 0x00000008L |
51011 | #define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS_MASK 0x00000010L |
51012 | #define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS_MASK 0x00000020L |
51013 | #define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS_MASK 0x00000040L |
51014 | #define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS_MASK 0x00000080L |
51015 | #define BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS_MASK 0x00000100L |
51016 | #define BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS_MASK 0x00000200L |
51017 | #define BIF_PF_FLR_INTR_STS__DEV2_PF0_FLR_INTR_STS_MASK 0x00010000L |
51018 | #define BIF_PF_FLR_INTR_STS__DEV2_PF1_FLR_INTR_STS_MASK 0x00020000L |
51019 | #define BIF_PF_FLR_INTR_STS__DEV2_PF2_FLR_INTR_STS_MASK 0x00040000L |
51020 | #define BIF_PF_FLR_INTR_STS__DEV2_PF3_FLR_INTR_STS_MASK 0x00080000L |
51021 | #define BIF_PF_FLR_INTR_STS__DEV2_PF4_FLR_INTR_STS_MASK 0x00100000L |
51022 | #define BIF_PF_FLR_INTR_STS__DEV2_PF5_FLR_INTR_STS_MASK 0x00200000L |
51023 | #define BIF_PF_FLR_INTR_STS__DEV2_PF6_FLR_INTR_STS_MASK 0x00400000L |
51024 | //BIF_D3HOTD0_INTR_STS |
51025 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0 |
51026 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1 |
51027 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2 |
51028 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3 |
51029 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x4 |
51030 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x5 |
51031 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x6 |
51032 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT 0x7 |
51033 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS__SHIFT 0x8 |
51034 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS__SHIFT 0x9 |
51035 | #define BIF_D3HOTD0_INTR_STS__DEV2_PF0_D3HOTD0_INTR_STS__SHIFT 0x10 |
51036 | #define BIF_D3HOTD0_INTR_STS__DEV2_PF1_D3HOTD0_INTR_STS__SHIFT 0x11 |
51037 | #define BIF_D3HOTD0_INTR_STS__DEV2_PF2_D3HOTD0_INTR_STS__SHIFT 0x12 |
51038 | #define BIF_D3HOTD0_INTR_STS__DEV2_PF3_D3HOTD0_INTR_STS__SHIFT 0x13 |
51039 | #define BIF_D3HOTD0_INTR_STS__DEV2_PF4_D3HOTD0_INTR_STS__SHIFT 0x14 |
51040 | #define BIF_D3HOTD0_INTR_STS__DEV2_PF5_D3HOTD0_INTR_STS__SHIFT 0x15 |
51041 | #define BIF_D3HOTD0_INTR_STS__DEV2_PF6_D3HOTD0_INTR_STS__SHIFT 0x16 |
51042 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK 0x00000001L |
51043 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK 0x00000002L |
51044 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK 0x00000004L |
51045 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK 0x00000008L |
51046 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS_MASK 0x00000010L |
51047 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS_MASK 0x00000020L |
51048 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS_MASK 0x00000040L |
51049 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS_MASK 0x00000080L |
51050 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS_MASK 0x00000100L |
51051 | #define BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS_MASK 0x00000200L |
51052 | #define BIF_D3HOTD0_INTR_STS__DEV2_PF0_D3HOTD0_INTR_STS_MASK 0x00010000L |
51053 | #define BIF_D3HOTD0_INTR_STS__DEV2_PF1_D3HOTD0_INTR_STS_MASK 0x00020000L |
51054 | #define BIF_D3HOTD0_INTR_STS__DEV2_PF2_D3HOTD0_INTR_STS_MASK 0x00040000L |
51055 | #define BIF_D3HOTD0_INTR_STS__DEV2_PF3_D3HOTD0_INTR_STS_MASK 0x00080000L |
51056 | #define BIF_D3HOTD0_INTR_STS__DEV2_PF4_D3HOTD0_INTR_STS_MASK 0x00100000L |
51057 | #define BIF_D3HOTD0_INTR_STS__DEV2_PF5_D3HOTD0_INTR_STS_MASK 0x00200000L |
51058 | #define BIF_D3HOTD0_INTR_STS__DEV2_PF6_D3HOTD0_INTR_STS_MASK 0x00400000L |
51059 | //BIF_POWER_INTR_STS |
51060 | #define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0 |
51061 | #define BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS__SHIFT 0x1 |
51062 | #define BIF_POWER_INTR_STS__DEV2_PME_TURN_OFF_INTR_STS__SHIFT 0x2 |
51063 | #define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10 |
51064 | #define BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS__SHIFT 0x11 |
51065 | #define BIF_POWER_INTR_STS__PORT2_DSTATE_INTR_STS__SHIFT 0x12 |
51066 | #define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK 0x00000001L |
51067 | #define BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS_MASK 0x00000002L |
51068 | #define BIF_POWER_INTR_STS__DEV2_PME_TURN_OFF_INTR_STS_MASK 0x00000004L |
51069 | #define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK 0x00010000L |
51070 | #define BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS_MASK 0x00020000L |
51071 | #define BIF_POWER_INTR_STS__PORT2_DSTATE_INTR_STS_MASK 0x00040000L |
51072 | //BIF_PF_DSTATE_INTR_STS |
51073 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0 |
51074 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1 |
51075 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2 |
51076 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3 |
51077 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4 |
51078 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5 |
51079 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6 |
51080 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7 |
51081 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS__SHIFT 0x8 |
51082 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS__SHIFT 0x9 |
51083 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS__SHIFT 0xa |
51084 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS__SHIFT 0xb |
51085 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS__SHIFT 0xc |
51086 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS__SHIFT 0xd |
51087 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS__SHIFT 0xe |
51088 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS__SHIFT 0xf |
51089 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF0_DSTATE_INTR_STS__SHIFT 0x10 |
51090 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF1_DSTATE_INTR_STS__SHIFT 0x11 |
51091 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF2_DSTATE_INTR_STS__SHIFT 0x12 |
51092 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF3_DSTATE_INTR_STS__SHIFT 0x13 |
51093 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF4_DSTATE_INTR_STS__SHIFT 0x14 |
51094 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF5_DSTATE_INTR_STS__SHIFT 0x15 |
51095 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF6_DSTATE_INTR_STS__SHIFT 0x16 |
51096 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF7_DSTATE_INTR_STS__SHIFT 0x17 |
51097 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK 0x00000001L |
51098 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK 0x00000002L |
51099 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK 0x00000004L |
51100 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK 0x00000008L |
51101 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK 0x00000010L |
51102 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK 0x00000020L |
51103 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK 0x00000040L |
51104 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK 0x00000080L |
51105 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS_MASK 0x00000100L |
51106 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS_MASK 0x00000200L |
51107 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS_MASK 0x00000400L |
51108 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS_MASK 0x00000800L |
51109 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS_MASK 0x00001000L |
51110 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS_MASK 0x00002000L |
51111 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS_MASK 0x00004000L |
51112 | #define BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS_MASK 0x00008000L |
51113 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF0_DSTATE_INTR_STS_MASK 0x00010000L |
51114 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF1_DSTATE_INTR_STS_MASK 0x00020000L |
51115 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF2_DSTATE_INTR_STS_MASK 0x00040000L |
51116 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF3_DSTATE_INTR_STS_MASK 0x00080000L |
51117 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF4_DSTATE_INTR_STS_MASK 0x00100000L |
51118 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF5_DSTATE_INTR_STS_MASK 0x00200000L |
51119 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF6_DSTATE_INTR_STS_MASK 0x00400000L |
51120 | #define BIF_PF_DSTATE_INTR_STS__DEV2_PF7_DSTATE_INTR_STS_MASK 0x00800000L |
51121 | //SELF_SOFT_RST_2 |
51122 | #define SELF_SOFT_RST_2__DSPT3_CFG_RST__SHIFT 0x0 |
51123 | #define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST__SHIFT 0x1 |
51124 | #define SELF_SOFT_RST_2__DSPT3_PRV_RST__SHIFT 0x2 |
51125 | #define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST__SHIFT 0x3 |
51126 | #define SELF_SOFT_RST_2__EP3_CFG_RST__SHIFT 0x4 |
51127 | #define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST__SHIFT 0x5 |
51128 | #define SELF_SOFT_RST_2__EP3_PRV_RST__SHIFT 0x6 |
51129 | #define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST__SHIFT 0x7 |
51130 | #define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT 0x18 |
51131 | #define SELF_SOFT_RST_2__DSPT3_CFG_RST_MASK 0x00000001L |
51132 | #define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST_MASK 0x00000002L |
51133 | #define SELF_SOFT_RST_2__DSPT3_PRV_RST_MASK 0x00000004L |
51134 | #define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST_MASK 0x00000008L |
51135 | #define SELF_SOFT_RST_2__EP3_CFG_RST_MASK 0x00000010L |
51136 | #define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST_MASK 0x00000020L |
51137 | #define SELF_SOFT_RST_2__EP3_PRV_RST_MASK 0x00000040L |
51138 | #define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST_MASK 0x00000080L |
51139 | #define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK 0x01000000L |
51140 | //BIF_INST_RESET_INTR_MASK |
51141 | #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0 |
51142 | #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1 |
51143 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2 |
51144 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3 |
51145 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4 |
51146 | #define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK__SHIFT 0x8 |
51147 | #define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x9 |
51148 | #define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_INTR_MASK__SHIFT 0xa |
51149 | #define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0xb |
51150 | #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK 0x00000001L |
51151 | #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000002L |
51152 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK 0x00000004L |
51153 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK 0x00000008L |
51154 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK 0x00000010L |
51155 | #define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK_MASK 0x00000100L |
51156 | #define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000200L |
51157 | #define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_INTR_MASK_MASK 0x00000400L |
51158 | #define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000800L |
51159 | //BIF_PF_FLR_INTR_MASK |
51160 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0 |
51161 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1 |
51162 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2 |
51163 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3 |
51164 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x4 |
51165 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x5 |
51166 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x6 |
51167 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT 0x7 |
51168 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK__SHIFT 0x8 |
51169 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK__SHIFT 0x9 |
51170 | #define BIF_PF_FLR_INTR_MASK__DEV2_PF0_FLR_INTR_MASK__SHIFT 0x10 |
51171 | #define BIF_PF_FLR_INTR_MASK__DEV2_PF1_FLR_INTR_MASK__SHIFT 0x11 |
51172 | #define BIF_PF_FLR_INTR_MASK__DEV2_PF2_FLR_INTR_MASK__SHIFT 0x12 |
51173 | #define BIF_PF_FLR_INTR_MASK__DEV2_PF3_FLR_INTR_MASK__SHIFT 0x13 |
51174 | #define BIF_PF_FLR_INTR_MASK__DEV2_PF4_FLR_INTR_MASK__SHIFT 0x14 |
51175 | #define BIF_PF_FLR_INTR_MASK__DEV2_PF5_FLR_INTR_MASK__SHIFT 0x15 |
51176 | #define BIF_PF_FLR_INTR_MASK__DEV2_PF6_FLR_INTR_MASK__SHIFT 0x16 |
51177 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK 0x00000001L |
51178 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK 0x00000002L |
51179 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK 0x00000004L |
51180 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK 0x00000008L |
51181 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK_MASK 0x00000010L |
51182 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK_MASK 0x00000020L |
51183 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK_MASK 0x00000040L |
51184 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK_MASK 0x00000080L |
51185 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK_MASK 0x00000100L |
51186 | #define BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK_MASK 0x00000200L |
51187 | #define BIF_PF_FLR_INTR_MASK__DEV2_PF0_FLR_INTR_MASK_MASK 0x00010000L |
51188 | #define BIF_PF_FLR_INTR_MASK__DEV2_PF1_FLR_INTR_MASK_MASK 0x00020000L |
51189 | #define BIF_PF_FLR_INTR_MASK__DEV2_PF2_FLR_INTR_MASK_MASK 0x00040000L |
51190 | #define BIF_PF_FLR_INTR_MASK__DEV2_PF3_FLR_INTR_MASK_MASK 0x00080000L |
51191 | #define BIF_PF_FLR_INTR_MASK__DEV2_PF4_FLR_INTR_MASK_MASK 0x00100000L |
51192 | #define BIF_PF_FLR_INTR_MASK__DEV2_PF5_FLR_INTR_MASK_MASK 0x00200000L |
51193 | #define BIF_PF_FLR_INTR_MASK__DEV2_PF6_FLR_INTR_MASK_MASK 0x00400000L |
51194 | //BIF_D3HOTD0_INTR_MASK |
51195 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0 |
51196 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1 |
51197 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2 |
51198 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3 |
51199 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x4 |
51200 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x5 |
51201 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x6 |
51202 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT 0x7 |
51203 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK__SHIFT 0x8 |
51204 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK__SHIFT 0x9 |
51205 | #define BIF_D3HOTD0_INTR_MASK__DEV2_PF0_D3HOTD0_INTR_MASK__SHIFT 0x10 |
51206 | #define BIF_D3HOTD0_INTR_MASK__DEV2_PF1_D3HOTD0_INTR_MASK__SHIFT 0x11 |
51207 | #define BIF_D3HOTD0_INTR_MASK__DEV2_PF2_D3HOTD0_INTR_MASK__SHIFT 0x12 |
51208 | #define BIF_D3HOTD0_INTR_MASK__DEV2_PF3_D3HOTD0_INTR_MASK__SHIFT 0x13 |
51209 | #define BIF_D3HOTD0_INTR_MASK__DEV2_PF4_D3HOTD0_INTR_MASK__SHIFT 0x14 |
51210 | #define BIF_D3HOTD0_INTR_MASK__DEV2_PF5_D3HOTD0_INTR_MASK__SHIFT 0x15 |
51211 | #define BIF_D3HOTD0_INTR_MASK__DEV2_PF6_D3HOTD0_INTR_MASK__SHIFT 0x16 |
51212 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK 0x00000001L |
51213 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK 0x00000002L |
51214 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK 0x00000004L |
51215 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK 0x00000008L |
51216 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK_MASK 0x00000010L |
51217 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK_MASK 0x00000020L |
51218 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK_MASK 0x00000040L |
51219 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK_MASK 0x00000080L |
51220 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK_MASK 0x00000100L |
51221 | #define BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK_MASK 0x00000200L |
51222 | #define BIF_D3HOTD0_INTR_MASK__DEV2_PF0_D3HOTD0_INTR_MASK_MASK 0x00010000L |
51223 | #define BIF_D3HOTD0_INTR_MASK__DEV2_PF1_D3HOTD0_INTR_MASK_MASK 0x00020000L |
51224 | #define BIF_D3HOTD0_INTR_MASK__DEV2_PF2_D3HOTD0_INTR_MASK_MASK 0x00040000L |
51225 | #define BIF_D3HOTD0_INTR_MASK__DEV2_PF3_D3HOTD0_INTR_MASK_MASK 0x00080000L |
51226 | #define BIF_D3HOTD0_INTR_MASK__DEV2_PF4_D3HOTD0_INTR_MASK_MASK 0x00100000L |
51227 | #define BIF_D3HOTD0_INTR_MASK__DEV2_PF5_D3HOTD0_INTR_MASK_MASK 0x00200000L |
51228 | #define BIF_D3HOTD0_INTR_MASK__DEV2_PF6_D3HOTD0_INTR_MASK_MASK 0x00400000L |
51229 | //BIF_POWER_INTR_MASK |
51230 | #define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0 |
51231 | #define BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK__SHIFT 0x1 |
51232 | #define BIF_POWER_INTR_MASK__DEV2_PME_TURN_OFF_INTR_MASK__SHIFT 0x2 |
51233 | #define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10 |
51234 | #define BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK__SHIFT 0x11 |
51235 | #define BIF_POWER_INTR_MASK__PORT2_DSTATE_INTR_MASK__SHIFT 0x12 |
51236 | #define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK 0x00000001L |
51237 | #define BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK_MASK 0x00000002L |
51238 | #define BIF_POWER_INTR_MASK__DEV2_PME_TURN_OFF_INTR_MASK_MASK 0x00000004L |
51239 | #define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK 0x00010000L |
51240 | #define BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK_MASK 0x00020000L |
51241 | #define BIF_POWER_INTR_MASK__PORT2_DSTATE_INTR_MASK_MASK 0x00040000L |
51242 | //BIF_PF_DSTATE_INTR_MASK |
51243 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0 |
51244 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1 |
51245 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2 |
51246 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3 |
51247 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4 |
51248 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5 |
51249 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6 |
51250 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7 |
51251 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK__SHIFT 0x8 |
51252 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK__SHIFT 0x9 |
51253 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK__SHIFT 0xa |
51254 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK__SHIFT 0xb |
51255 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK__SHIFT 0xc |
51256 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK__SHIFT 0xd |
51257 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK__SHIFT 0xe |
51258 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK__SHIFT 0xf |
51259 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF0_DSTATE_INTR_MASK__SHIFT 0x10 |
51260 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF1_DSTATE_INTR_MASK__SHIFT 0x11 |
51261 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF2_DSTATE_INTR_MASK__SHIFT 0x12 |
51262 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF3_DSTATE_INTR_MASK__SHIFT 0x13 |
51263 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF4_DSTATE_INTR_MASK__SHIFT 0x14 |
51264 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF5_DSTATE_INTR_MASK__SHIFT 0x15 |
51265 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF6_DSTATE_INTR_MASK__SHIFT 0x16 |
51266 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF7_DSTATE_INTR_MASK__SHIFT 0x17 |
51267 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK 0x00000001L |
51268 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK 0x00000002L |
51269 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK 0x00000004L |
51270 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK 0x00000008L |
51271 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK 0x00000010L |
51272 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK 0x00000020L |
51273 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK 0x00000040L |
51274 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK 0x00000080L |
51275 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK_MASK 0x00000100L |
51276 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK_MASK 0x00000200L |
51277 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK_MASK 0x00000400L |
51278 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK_MASK 0x00000800L |
51279 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK_MASK 0x00001000L |
51280 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK_MASK 0x00002000L |
51281 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK_MASK 0x00004000L |
51282 | #define BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK_MASK 0x00008000L |
51283 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF0_DSTATE_INTR_MASK_MASK 0x00010000L |
51284 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF1_DSTATE_INTR_MASK_MASK 0x00020000L |
51285 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF2_DSTATE_INTR_MASK_MASK 0x00040000L |
51286 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF3_DSTATE_INTR_MASK_MASK 0x00080000L |
51287 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF4_DSTATE_INTR_MASK_MASK 0x00100000L |
51288 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF5_DSTATE_INTR_MASK_MASK 0x00200000L |
51289 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF6_DSTATE_INTR_MASK_MASK 0x00400000L |
51290 | #define BIF_PF_DSTATE_INTR_MASK__DEV2_PF7_DSTATE_INTR_MASK_MASK 0x00800000L |
51291 | //BIF_PF_FLR_RST |
51292 | #define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 |
51293 | #define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 |
51294 | #define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2 |
51295 | #define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3 |
51296 | #define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4 |
51297 | #define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5 |
51298 | #define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6 |
51299 | #define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7 |
51300 | #define BIF_PF_FLR_RST__DEV1_PF0_FLR_RST__SHIFT 0x8 |
51301 | #define BIF_PF_FLR_RST__DEV1_PF1_FLR_RST__SHIFT 0x9 |
51302 | #define BIF_PF_FLR_RST__DEV2_PF0_FLR_RST__SHIFT 0x10 |
51303 | #define BIF_PF_FLR_RST__DEV2_PF1_FLR_RST__SHIFT 0x11 |
51304 | #define BIF_PF_FLR_RST__DEV2_PF2_FLR_RST__SHIFT 0x12 |
51305 | #define BIF_PF_FLR_RST__DEV2_PF3_FLR_RST__SHIFT 0x13 |
51306 | #define BIF_PF_FLR_RST__DEV2_PF4_FLR_RST__SHIFT 0x14 |
51307 | #define BIF_PF_FLR_RST__DEV2_PF5_FLR_RST__SHIFT 0x15 |
51308 | #define BIF_PF_FLR_RST__DEV2_PF6_FLR_RST__SHIFT 0x16 |
51309 | #define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L |
51310 | #define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L |
51311 | #define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L |
51312 | #define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L |
51313 | #define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L |
51314 | #define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L |
51315 | #define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L |
51316 | #define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK 0x00000080L |
51317 | #define BIF_PF_FLR_RST__DEV1_PF0_FLR_RST_MASK 0x00000100L |
51318 | #define BIF_PF_FLR_RST__DEV1_PF1_FLR_RST_MASK 0x00000200L |
51319 | #define BIF_PF_FLR_RST__DEV2_PF0_FLR_RST_MASK 0x00010000L |
51320 | #define BIF_PF_FLR_RST__DEV2_PF1_FLR_RST_MASK 0x00020000L |
51321 | #define BIF_PF_FLR_RST__DEV2_PF2_FLR_RST_MASK 0x00040000L |
51322 | #define BIF_PF_FLR_RST__DEV2_PF3_FLR_RST_MASK 0x00080000L |
51323 | #define BIF_PF_FLR_RST__DEV2_PF4_FLR_RST_MASK 0x00100000L |
51324 | #define BIF_PF_FLR_RST__DEV2_PF5_FLR_RST_MASK 0x00200000L |
51325 | #define BIF_PF_FLR_RST__DEV2_PF6_FLR_RST_MASK 0x00400000L |
51326 | //BIF_DEV0_PF0_DSTATE_VALUE |
51327 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 |
51328 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51329 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 |
51330 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L |
51331 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51332 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L |
51333 | //BIF_DEV0_PF1_DSTATE_VALUE |
51334 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 |
51335 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51336 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 |
51337 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L |
51338 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51339 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L |
51340 | //BIF_DEV0_PF2_DSTATE_VALUE |
51341 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0 |
51342 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51343 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10 |
51344 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L |
51345 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51346 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L |
51347 | //BIF_DEV0_PF3_DSTATE_VALUE |
51348 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0 |
51349 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51350 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10 |
51351 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L |
51352 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51353 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L |
51354 | //BIF_DEV0_PF4_DSTATE_VALUE |
51355 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x0 |
51356 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51357 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x10 |
51358 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L |
51359 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51360 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L |
51361 | //BIF_DEV0_PF5_DSTATE_VALUE |
51362 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x0 |
51363 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51364 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x10 |
51365 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L |
51366 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51367 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L |
51368 | //BIF_DEV0_PF6_DSTATE_VALUE |
51369 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x0 |
51370 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51371 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x10 |
51372 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L |
51373 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51374 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L |
51375 | //BIF_DEV0_PF7_DSTATE_VALUE |
51376 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT 0x0 |
51377 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51378 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT 0x10 |
51379 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE_MASK 0x00000003L |
51380 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51381 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE_MASK 0x00030000L |
51382 | //DEV0_PF0_D3HOTD0_RST_CTRL |
51383 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51384 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51385 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51386 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51387 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51388 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51389 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51390 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51391 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51392 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51393 | //DEV0_PF1_D3HOTD0_RST_CTRL |
51394 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51395 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51396 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51397 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51398 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51399 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51400 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51401 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51402 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51403 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51404 | //DEV0_PF2_D3HOTD0_RST_CTRL |
51405 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51406 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51407 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51408 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51409 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51410 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51411 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51412 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51413 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51414 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51415 | //DEV0_PF3_D3HOTD0_RST_CTRL |
51416 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51417 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51418 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51419 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51420 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51421 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51422 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51423 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51424 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51425 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51426 | //DEV0_PF4_D3HOTD0_RST_CTRL |
51427 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51428 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51429 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51430 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51431 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51432 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51433 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51434 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51435 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51436 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51437 | //DEV0_PF5_D3HOTD0_RST_CTRL |
51438 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51439 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51440 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51441 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51442 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51443 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51444 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51445 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51446 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51447 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51448 | //DEV0_PF6_D3HOTD0_RST_CTRL |
51449 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51450 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51451 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51452 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51453 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51454 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51455 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51456 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51457 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51458 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51459 | //DEV0_PF7_D3HOTD0_RST_CTRL |
51460 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51461 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51462 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51463 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51464 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51465 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51466 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51467 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51468 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51469 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51470 | //DEV1_PF0_FLR_RST_CTRL |
51471 | #define DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51472 | #define DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51473 | #define DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51474 | #define DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51475 | #define DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51476 | #define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
51477 | #define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
51478 | #define DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
51479 | #define DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
51480 | #define DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51481 | #define DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51482 | #define DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51483 | #define DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51484 | #define DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51485 | #define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
51486 | #define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
51487 | #define DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
51488 | #define DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
51489 | //DEV1_PF1_FLR_RST_CTRL |
51490 | #define DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51491 | #define DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51492 | #define DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51493 | #define DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51494 | #define DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51495 | #define DEV1_PF1_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5 |
51496 | #define DEV1_PF1_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6 |
51497 | #define DEV1_PF1_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7 |
51498 | #define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8 |
51499 | #define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9 |
51500 | #define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa |
51501 | #define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb |
51502 | #define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc |
51503 | #define DEV1_PF1_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd |
51504 | #define DEV1_PF1_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe |
51505 | #define DEV1_PF1_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf |
51506 | #define DEV1_PF1_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10 |
51507 | #define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
51508 | #define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
51509 | #define DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
51510 | #define DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
51511 | #define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT 0x1f |
51512 | #define DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51513 | #define DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51514 | #define DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51515 | #define DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51516 | #define DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51517 | #define DEV1_PF1_FLR_RST_CTRL__VF_CFG_EN_MASK 0x00000020L |
51518 | #define DEV1_PF1_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK 0x00000040L |
51519 | #define DEV1_PF1_FLR_RST_CTRL__VF_PRV_EN_MASK 0x00000080L |
51520 | #define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK 0x00000100L |
51521 | #define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK 0x00000200L |
51522 | #define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK 0x00000400L |
51523 | #define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK 0x00000800L |
51524 | #define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK 0x00001000L |
51525 | #define DEV1_PF1_FLR_RST_CTRL__VF_VF_CFG_EN_MASK 0x00002000L |
51526 | #define DEV1_PF1_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK 0x00004000L |
51527 | #define DEV1_PF1_FLR_RST_CTRL__VF_VF_PRV_EN_MASK 0x00008000L |
51528 | #define DEV1_PF1_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L |
51529 | #define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
51530 | #define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
51531 | #define DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
51532 | #define DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
51533 | #define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK 0x80000000L |
51534 | //BIF_DEV1_PF0_DSTATE_VALUE |
51535 | #define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 |
51536 | #define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51537 | #define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 |
51538 | #define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L |
51539 | #define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51540 | #define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L |
51541 | //BIF_DEV1_PF1_DSTATE_VALUE |
51542 | #define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 |
51543 | #define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51544 | #define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 |
51545 | #define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L |
51546 | #define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51547 | #define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L |
51548 | //DEV1_PF0_D3HOTD0_RST_CTRL |
51549 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51550 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51551 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51552 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51553 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51554 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51555 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51556 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51557 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51558 | #define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51559 | //DEV1_PF1_D3HOTD0_RST_CTRL |
51560 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51561 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51562 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51563 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51564 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51565 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51566 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51567 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51568 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51569 | #define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51570 | //DEV2_PF0_FLR_RST_CTRL |
51571 | #define DEV2_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51572 | #define DEV2_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51573 | #define DEV2_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51574 | #define DEV2_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51575 | #define DEV2_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51576 | #define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
51577 | #define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
51578 | #define DEV2_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
51579 | #define DEV2_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
51580 | #define DEV2_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51581 | #define DEV2_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51582 | #define DEV2_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51583 | #define DEV2_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51584 | #define DEV2_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51585 | #define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
51586 | #define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
51587 | #define DEV2_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
51588 | #define DEV2_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
51589 | //DEV2_PF1_FLR_RST_CTRL |
51590 | #define DEV2_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51591 | #define DEV2_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51592 | #define DEV2_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51593 | #define DEV2_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51594 | #define DEV2_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51595 | #define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
51596 | #define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
51597 | #define DEV2_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
51598 | #define DEV2_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
51599 | #define DEV2_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51600 | #define DEV2_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51601 | #define DEV2_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51602 | #define DEV2_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51603 | #define DEV2_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51604 | #define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
51605 | #define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
51606 | #define DEV2_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
51607 | #define DEV2_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
51608 | //DEV2_PF2_FLR_RST_CTRL |
51609 | #define DEV2_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51610 | #define DEV2_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51611 | #define DEV2_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51612 | #define DEV2_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51613 | #define DEV2_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51614 | #define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
51615 | #define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
51616 | #define DEV2_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
51617 | #define DEV2_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
51618 | #define DEV2_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51619 | #define DEV2_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51620 | #define DEV2_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51621 | #define DEV2_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51622 | #define DEV2_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51623 | #define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
51624 | #define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
51625 | #define DEV2_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
51626 | #define DEV2_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
51627 | //DEV2_PF3_FLR_RST_CTRL |
51628 | #define DEV2_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51629 | #define DEV2_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51630 | #define DEV2_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51631 | #define DEV2_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51632 | #define DEV2_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51633 | #define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
51634 | #define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
51635 | #define DEV2_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
51636 | #define DEV2_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
51637 | #define DEV2_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51638 | #define DEV2_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51639 | #define DEV2_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51640 | #define DEV2_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51641 | #define DEV2_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51642 | #define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
51643 | #define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
51644 | #define DEV2_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
51645 | #define DEV2_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
51646 | //DEV2_PF4_FLR_RST_CTRL |
51647 | #define DEV2_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51648 | #define DEV2_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51649 | #define DEV2_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51650 | #define DEV2_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51651 | #define DEV2_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51652 | #define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
51653 | #define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
51654 | #define DEV2_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
51655 | #define DEV2_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
51656 | #define DEV2_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51657 | #define DEV2_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51658 | #define DEV2_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51659 | #define DEV2_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51660 | #define DEV2_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51661 | #define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
51662 | #define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
51663 | #define DEV2_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
51664 | #define DEV2_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
51665 | //DEV2_PF5_FLR_RST_CTRL |
51666 | #define DEV2_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51667 | #define DEV2_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51668 | #define DEV2_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51669 | #define DEV2_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51670 | #define DEV2_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51671 | #define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
51672 | #define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
51673 | #define DEV2_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
51674 | #define DEV2_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
51675 | #define DEV2_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51676 | #define DEV2_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51677 | #define DEV2_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51678 | #define DEV2_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51679 | #define DEV2_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51680 | #define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
51681 | #define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
51682 | #define DEV2_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
51683 | #define DEV2_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
51684 | //DEV2_PF6_FLR_RST_CTRL |
51685 | #define DEV2_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51686 | #define DEV2_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51687 | #define DEV2_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51688 | #define DEV2_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51689 | #define DEV2_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51690 | #define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
51691 | #define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
51692 | #define DEV2_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
51693 | #define DEV2_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
51694 | #define DEV2_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51695 | #define DEV2_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51696 | #define DEV2_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51697 | #define DEV2_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51698 | #define DEV2_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51699 | #define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
51700 | #define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
51701 | #define DEV2_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
51702 | #define DEV2_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
51703 | //BIF_DEV2_PF0_DSTATE_VALUE |
51704 | #define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 |
51705 | #define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51706 | #define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 |
51707 | #define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L |
51708 | #define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51709 | #define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L |
51710 | //BIF_DEV2_PF1_DSTATE_VALUE |
51711 | #define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 |
51712 | #define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51713 | #define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 |
51714 | #define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L |
51715 | #define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51716 | #define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L |
51717 | //BIF_DEV2_PF2_DSTATE_VALUE |
51718 | #define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_TGT_VALUE__SHIFT 0x0 |
51719 | #define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51720 | #define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_ACK_VALUE__SHIFT 0x10 |
51721 | #define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L |
51722 | #define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51723 | #define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L |
51724 | //BIF_DEV2_PF3_DSTATE_VALUE |
51725 | #define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_TGT_VALUE__SHIFT 0x0 |
51726 | #define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51727 | #define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_ACK_VALUE__SHIFT 0x10 |
51728 | #define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L |
51729 | #define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51730 | #define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L |
51731 | //BIF_DEV2_PF4_DSTATE_VALUE |
51732 | #define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_TGT_VALUE__SHIFT 0x0 |
51733 | #define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51734 | #define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_ACK_VALUE__SHIFT 0x10 |
51735 | #define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L |
51736 | #define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51737 | #define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L |
51738 | //BIF_DEV2_PF5_DSTATE_VALUE |
51739 | #define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_TGT_VALUE__SHIFT 0x0 |
51740 | #define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51741 | #define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_ACK_VALUE__SHIFT 0x10 |
51742 | #define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L |
51743 | #define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51744 | #define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L |
51745 | //BIF_DEV2_PF6_DSTATE_VALUE |
51746 | #define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_TGT_VALUE__SHIFT 0x0 |
51747 | #define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
51748 | #define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_ACK_VALUE__SHIFT 0x10 |
51749 | #define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L |
51750 | #define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
51751 | #define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L |
51752 | //DEV2_PF0_D3HOTD0_RST_CTRL |
51753 | #define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51754 | #define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51755 | #define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51756 | #define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51757 | #define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51758 | #define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51759 | #define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51760 | #define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51761 | #define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51762 | #define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51763 | //DEV2_PF1_D3HOTD0_RST_CTRL |
51764 | #define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51765 | #define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51766 | #define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51767 | #define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51768 | #define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51769 | #define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51770 | #define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51771 | #define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51772 | #define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51773 | #define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51774 | //DEV2_PF2_D3HOTD0_RST_CTRL |
51775 | #define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51776 | #define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51777 | #define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51778 | #define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51779 | #define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51780 | #define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51781 | #define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51782 | #define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51783 | #define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51784 | #define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51785 | //DEV2_PF3_D3HOTD0_RST_CTRL |
51786 | #define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51787 | #define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51788 | #define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51789 | #define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51790 | #define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51791 | #define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51792 | #define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51793 | #define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51794 | #define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51795 | #define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51796 | //DEV2_PF4_D3HOTD0_RST_CTRL |
51797 | #define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51798 | #define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51799 | #define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51800 | #define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51801 | #define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51802 | #define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51803 | #define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51804 | #define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51805 | #define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51806 | #define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51807 | //DEV2_PF5_D3HOTD0_RST_CTRL |
51808 | #define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51809 | #define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51810 | #define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51811 | #define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51812 | #define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51813 | #define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51814 | #define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51815 | #define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51816 | #define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51817 | #define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51818 | //DEV2_PF6_D3HOTD0_RST_CTRL |
51819 | #define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
51820 | #define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
51821 | #define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
51822 | #define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
51823 | #define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
51824 | #define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
51825 | #define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
51826 | #define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
51827 | #define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
51828 | #define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
51829 | //BIF_PORT0_DSTATE_VALUE |
51830 | #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0 |
51831 | #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10 |
51832 | #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK 0x00000003L |
51833 | #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK 0x00030000L |
51834 | //BIF_PORT1_DSTATE_VALUE |
51835 | #define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE__SHIFT 0x0 |
51836 | #define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE__SHIFT 0x10 |
51837 | #define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE_MASK 0x00000003L |
51838 | #define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE_MASK 0x00030000L |
51839 | //BIF_PORT2_DSTATE_VALUE |
51840 | #define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_TGT_VALUE__SHIFT 0x0 |
51841 | #define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_ACK_VALUE__SHIFT 0x10 |
51842 | #define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_TGT_VALUE_MASK 0x00000003L |
51843 | #define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_ACK_VALUE_MASK 0x00030000L |
51844 | |
51845 | |
51846 | // addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk |
51847 | //MISC_SCRATCH |
51848 | #define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0 |
51849 | #define MISC_SCRATCH__MISC_SCRATCH0_MASK 0xFFFFFFFFL |
51850 | //INTR_LINE_POLARITY |
51851 | #define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0 |
51852 | #define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1__SHIFT 0x8 |
51853 | #define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV2__SHIFT 0x10 |
51854 | #define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK 0x000000FFL |
51855 | #define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1_MASK 0x0000FF00L |
51856 | #define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV2_MASK 0x00FF0000L |
51857 | //INTR_LINE_ENABLE |
51858 | #define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0 |
51859 | #define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1__SHIFT 0x8 |
51860 | #define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV2__SHIFT 0x10 |
51861 | #define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK 0x000000FFL |
51862 | #define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1_MASK 0x0000FF00L |
51863 | #define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV2_MASK 0x00FF0000L |
51864 | //OUTSTANDING_VC_ALLOC |
51865 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0 |
51866 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2 |
51867 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4 |
51868 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6 |
51869 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8 |
51870 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa |
51871 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc |
51872 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe |
51873 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10 |
51874 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18 |
51875 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a |
51876 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c |
51877 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK 0x00000003L |
51878 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK 0x0000000CL |
51879 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK 0x00000030L |
51880 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK 0x000000C0L |
51881 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK 0x00000300L |
51882 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK 0x00000C00L |
51883 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK 0x00003000L |
51884 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK 0x0000C000L |
51885 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK 0x000F0000L |
51886 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK 0x03000000L |
51887 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK 0x0C000000L |
51888 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK 0xF0000000L |
51889 | //BIFC_MISC_CTRL0 |
51890 | #define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0 |
51891 | #define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1 |
51892 | #define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT 0x4 |
51893 | #define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8 |
51894 | #define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT 0x9 |
51895 | #define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa |
51896 | #define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0xb |
51897 | #define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0xc |
51898 | #define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10 |
51899 | #define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11 |
51900 | #define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT 0x12 |
51901 | #define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT 0x13 |
51902 | #define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT 0x14 |
51903 | #define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN__SHIFT 0x15 |
51904 | #define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN__SHIFT 0x16 |
51905 | #define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18 |
51906 | #define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a |
51907 | #define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b |
51908 | #define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c |
51909 | #define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST__SHIFT 0x1e |
51910 | #define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f |
51911 | #define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK 0x00000001L |
51912 | #define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK 0x00000006L |
51913 | #define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK 0x000000F0L |
51914 | #define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK 0x00000100L |
51915 | #define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_MASK 0x00000200L |
51916 | #define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK 0x00000400L |
51917 | #define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x00000800L |
51918 | #define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x00001000L |
51919 | #define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK 0x00010000L |
51920 | #define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK 0x00020000L |
51921 | #define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK 0x00040000L |
51922 | #define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK 0x00080000L |
51923 | #define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK 0x00100000L |
51924 | #define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN_MASK 0x00200000L |
51925 | #define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN_MASK 0x00400000L |
51926 | #define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK 0x01000000L |
51927 | #define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK 0x04000000L |
51928 | #define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK 0x08000000L |
51929 | #define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK 0x10000000L |
51930 | #define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST_MASK 0x40000000L |
51931 | #define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK 0x80000000L |
51932 | //BIFC_MISC_CTRL1 |
51933 | #define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0 |
51934 | #define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1 |
51935 | #define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2 |
51936 | #define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3 |
51937 | #define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4 |
51938 | #define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5 |
51939 | #define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6 |
51940 | #define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT 0x7 |
51941 | #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8 |
51942 | #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa |
51943 | #define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc |
51944 | #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd |
51945 | #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe |
51946 | #define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf |
51947 | #define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10 |
51948 | #define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11 |
51949 | #define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12 |
51950 | #define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13 |
51951 | #define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT 0x14 |
51952 | #define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG__SHIFT 0x17 |
51953 | #define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT 0x18 |
51954 | #define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT 0x19 |
51955 | #define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT 0x1a |
51956 | #define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT 0x1b |
51957 | #define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT 0x1c |
51958 | #define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT 0x1d |
51959 | #define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x1e |
51960 | #define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK 0x00000001L |
51961 | #define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK 0x00000002L |
51962 | #define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK 0x00000004L |
51963 | #define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK 0x00000008L |
51964 | #define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK 0x00000010L |
51965 | #define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK 0x00000020L |
51966 | #define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK 0x00000040L |
51967 | #define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK 0x00000080L |
51968 | #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK 0x00000300L |
51969 | #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK 0x00000C00L |
51970 | #define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK 0x00001000L |
51971 | #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK 0x00002000L |
51972 | #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK 0x00004000L |
51973 | #define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK 0x00008000L |
51974 | #define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK 0x00010000L |
51975 | #define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK 0x00020000L |
51976 | #define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK 0x00040000L |
51977 | #define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK 0x00080000L |
51978 | #define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK 0x00100000L |
51979 | #define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG_MASK 0x00800000L |
51980 | #define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK 0x01000000L |
51981 | #define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK 0x02000000L |
51982 | #define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK 0x04000000L |
51983 | #define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK 0x08000000L |
51984 | #define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK 0x10000000L |
51985 | #define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK 0x20000000L |
51986 | #define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK 0xC0000000L |
51987 | //BIFC_LC_TIMER_CTRL |
51988 | #define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE__SHIFT 0x0 |
51989 | #define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE__SHIFT 0x10 |
51990 | #define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE_MASK 0x0000FFFFL |
51991 | #define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE_MASK 0xFFFF0000L |
51992 | //BIFC_RCCBIH_BME_ERR_LOG0 |
51993 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0 |
51994 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1 |
51995 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2 |
51996 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3 |
51997 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x4 |
51998 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x5 |
51999 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x6 |
52000 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x7 |
52001 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT 0x8 |
52002 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT 0x9 |
52003 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10 |
52004 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11 |
52005 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12 |
52006 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13 |
52007 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x14 |
52008 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x15 |
52009 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x16 |
52010 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x17 |
52011 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT 0x18 |
52012 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT 0x19 |
52013 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00000001L |
52014 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00000002L |
52015 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00000004L |
52016 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00000008L |
52017 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00000010L |
52018 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00000020L |
52019 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00000040L |
52020 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00000080L |
52021 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F0_MASK 0x00000100L |
52022 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F1_MASK 0x00000200L |
52023 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00010000L |
52024 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00020000L |
52025 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00040000L |
52026 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00080000L |
52027 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00100000L |
52028 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00200000L |
52029 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00400000L |
52030 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00800000L |
52031 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0_MASK 0x01000000L |
52032 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1_MASK 0x02000000L |
52033 | //BIFC_RCCBIH_BME_ERR_LOG1 |
52034 | #define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F0__SHIFT 0x0 |
52035 | #define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F1__SHIFT 0x1 |
52036 | #define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F2__SHIFT 0x2 |
52037 | #define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F3__SHIFT 0x3 |
52038 | #define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F4__SHIFT 0x4 |
52039 | #define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F5__SHIFT 0x5 |
52040 | #define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F6__SHIFT 0x6 |
52041 | #define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F0__SHIFT 0x10 |
52042 | #define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F1__SHIFT 0x11 |
52043 | #define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F2__SHIFT 0x12 |
52044 | #define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F3__SHIFT 0x13 |
52045 | #define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F4__SHIFT 0x14 |
52046 | #define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F5__SHIFT 0x15 |
52047 | #define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F6__SHIFT 0x16 |
52048 | #define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F0_MASK 0x00000001L |
52049 | #define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F1_MASK 0x00000002L |
52050 | #define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F2_MASK 0x00000004L |
52051 | #define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F3_MASK 0x00000008L |
52052 | #define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F4_MASK 0x00000010L |
52053 | #define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F5_MASK 0x00000020L |
52054 | #define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F6_MASK 0x00000040L |
52055 | #define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F0_MASK 0x00010000L |
52056 | #define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F1_MASK 0x00020000L |
52057 | #define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F2_MASK 0x00040000L |
52058 | #define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F3_MASK 0x00080000L |
52059 | #define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F4_MASK 0x00100000L |
52060 | #define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F5_MASK 0x00200000L |
52061 | #define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F6_MASK 0x00400000L |
52062 | //BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 |
52063 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0 |
52064 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2 |
52065 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT 0x4 |
52066 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6 |
52067 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8 |
52068 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa |
52069 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc |
52070 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT 0xe |
52071 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10 |
52072 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12 |
52073 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT 0x14 |
52074 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16 |
52075 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18 |
52076 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a |
52077 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c |
52078 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT 0x1e |
52079 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK 0x00000003L |
52080 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK 0x0000000CL |
52081 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK 0x00000030L |
52082 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK 0x000000C0L |
52083 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK 0x00000300L |
52084 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK 0x00000C00L |
52085 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK 0x00003000L |
52086 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK 0x0000C000L |
52087 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK 0x00030000L |
52088 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK 0x000C0000L |
52089 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK 0x00300000L |
52090 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK 0x00C00000L |
52091 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK 0x03000000L |
52092 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK 0x0C000000L |
52093 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK 0x30000000L |
52094 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK 0xC0000000L |
52095 | //BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 |
52096 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0 |
52097 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2 |
52098 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT 0x4 |
52099 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6 |
52100 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8 |
52101 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa |
52102 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc |
52103 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT 0xe |
52104 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10 |
52105 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12 |
52106 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT 0x14 |
52107 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16 |
52108 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18 |
52109 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a |
52110 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c |
52111 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT 0x1e |
52112 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK 0x00000003L |
52113 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK 0x0000000CL |
52114 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK 0x00000030L |
52115 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK 0x000000C0L |
52116 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK 0x00000300L |
52117 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK 0x00000C00L |
52118 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK 0x00003000L |
52119 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK 0x0000C000L |
52120 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK 0x00030000L |
52121 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK 0x000C0000L |
52122 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK 0x00300000L |
52123 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK 0x00C00000L |
52124 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK 0x03000000L |
52125 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK 0x0C000000L |
52126 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK 0x30000000L |
52127 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK 0xC0000000L |
52128 | //BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 |
52129 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0 |
52130 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2 |
52131 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT 0x4 |
52132 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6 |
52133 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8 |
52134 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa |
52135 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc |
52136 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT 0xe |
52137 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10 |
52138 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12 |
52139 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT 0x14 |
52140 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16 |
52141 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18 |
52142 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a |
52143 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c |
52144 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT 0x1e |
52145 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK 0x00000003L |
52146 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK 0x0000000CL |
52147 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK 0x00000030L |
52148 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK 0x000000C0L |
52149 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK 0x00000300L |
52150 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK 0x00000C00L |
52151 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK 0x00003000L |
52152 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK 0x0000C000L |
52153 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK 0x00030000L |
52154 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK 0x000C0000L |
52155 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK 0x00300000L |
52156 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK 0x00C00000L |
52157 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK 0x03000000L |
52158 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK 0x0C000000L |
52159 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK 0x30000000L |
52160 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK 0xC0000000L |
52161 | //BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 |
52162 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0 |
52163 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2 |
52164 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT 0x4 |
52165 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6 |
52166 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8 |
52167 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa |
52168 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc |
52169 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT 0xe |
52170 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10 |
52171 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12 |
52172 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT 0x14 |
52173 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16 |
52174 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18 |
52175 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a |
52176 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c |
52177 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT 0x1e |
52178 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK 0x00000003L |
52179 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK 0x0000000CL |
52180 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK 0x00000030L |
52181 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK 0x000000C0L |
52182 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK 0x00000300L |
52183 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK 0x00000C00L |
52184 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK 0x00003000L |
52185 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK 0x0000C000L |
52186 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK 0x00030000L |
52187 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK 0x000C0000L |
52188 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK 0x00300000L |
52189 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK 0x00C00000L |
52190 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK 0x03000000L |
52191 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK 0x0C000000L |
52192 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK 0x30000000L |
52193 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK 0xC0000000L |
52194 | //BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1 |
52195 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0__SHIFT 0x0 |
52196 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0__SHIFT 0x2 |
52197 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F0__SHIFT 0x4 |
52198 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0__SHIFT 0x6 |
52199 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0__SHIFT 0x8 |
52200 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0__SHIFT 0xa |
52201 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0__SHIFT 0xc |
52202 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F0__SHIFT 0xe |
52203 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1__SHIFT 0x10 |
52204 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1__SHIFT 0x12 |
52205 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F1__SHIFT 0x14 |
52206 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1__SHIFT 0x16 |
52207 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1__SHIFT 0x18 |
52208 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1__SHIFT 0x1a |
52209 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1__SHIFT 0x1c |
52210 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F1__SHIFT 0x1e |
52211 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0_MASK 0x00000003L |
52212 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0_MASK 0x0000000CL |
52213 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F0_MASK 0x00000030L |
52214 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0_MASK 0x000000C0L |
52215 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0_MASK 0x00000300L |
52216 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0_MASK 0x00000C00L |
52217 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0_MASK 0x00003000L |
52218 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F0_MASK 0x0000C000L |
52219 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1_MASK 0x00030000L |
52220 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1_MASK 0x000C0000L |
52221 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F1_MASK 0x00300000L |
52222 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1_MASK 0x00C00000L |
52223 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1_MASK 0x03000000L |
52224 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1_MASK 0x0C000000L |
52225 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1_MASK 0x30000000L |
52226 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F1_MASK 0xC0000000L |
52227 | //BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3 |
52228 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2__SHIFT 0x0 |
52229 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2__SHIFT 0x2 |
52230 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F2__SHIFT 0x4 |
52231 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2__SHIFT 0x6 |
52232 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2__SHIFT 0x8 |
52233 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2__SHIFT 0xa |
52234 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2__SHIFT 0xc |
52235 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F2__SHIFT 0xe |
52236 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3__SHIFT 0x10 |
52237 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3__SHIFT 0x12 |
52238 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F3__SHIFT 0x14 |
52239 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3__SHIFT 0x16 |
52240 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3__SHIFT 0x18 |
52241 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3__SHIFT 0x1a |
52242 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3__SHIFT 0x1c |
52243 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F3__SHIFT 0x1e |
52244 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2_MASK 0x00000003L |
52245 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2_MASK 0x0000000CL |
52246 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F2_MASK 0x00000030L |
52247 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2_MASK 0x000000C0L |
52248 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2_MASK 0x00000300L |
52249 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2_MASK 0x00000C00L |
52250 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2_MASK 0x00003000L |
52251 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F2_MASK 0x0000C000L |
52252 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3_MASK 0x00030000L |
52253 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3_MASK 0x000C0000L |
52254 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F3_MASK 0x00300000L |
52255 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3_MASK 0x00C00000L |
52256 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3_MASK 0x03000000L |
52257 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3_MASK 0x0C000000L |
52258 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3_MASK 0x30000000L |
52259 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F3_MASK 0xC0000000L |
52260 | //BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5 |
52261 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4__SHIFT 0x0 |
52262 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4__SHIFT 0x2 |
52263 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F4__SHIFT 0x4 |
52264 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4__SHIFT 0x6 |
52265 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4__SHIFT 0x8 |
52266 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4__SHIFT 0xa |
52267 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4__SHIFT 0xc |
52268 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F4__SHIFT 0xe |
52269 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5__SHIFT 0x10 |
52270 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5__SHIFT 0x12 |
52271 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F5__SHIFT 0x14 |
52272 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5__SHIFT 0x16 |
52273 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5__SHIFT 0x18 |
52274 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5__SHIFT 0x1a |
52275 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5__SHIFT 0x1c |
52276 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F5__SHIFT 0x1e |
52277 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4_MASK 0x00000003L |
52278 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4_MASK 0x0000000CL |
52279 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F4_MASK 0x00000030L |
52280 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4_MASK 0x000000C0L |
52281 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4_MASK 0x00000300L |
52282 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4_MASK 0x00000C00L |
52283 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4_MASK 0x00003000L |
52284 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F4_MASK 0x0000C000L |
52285 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5_MASK 0x00030000L |
52286 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5_MASK 0x000C0000L |
52287 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F5_MASK 0x00300000L |
52288 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5_MASK 0x00C00000L |
52289 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5_MASK 0x03000000L |
52290 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5_MASK 0x0C000000L |
52291 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5_MASK 0x30000000L |
52292 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F5_MASK 0xC0000000L |
52293 | //BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7 |
52294 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6__SHIFT 0x0 |
52295 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6__SHIFT 0x2 |
52296 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F6__SHIFT 0x4 |
52297 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6__SHIFT 0x6 |
52298 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6__SHIFT 0x8 |
52299 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6__SHIFT 0xa |
52300 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6__SHIFT 0xc |
52301 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F6__SHIFT 0xe |
52302 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7__SHIFT 0x10 |
52303 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7__SHIFT 0x12 |
52304 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F7__SHIFT 0x14 |
52305 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7__SHIFT 0x16 |
52306 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7__SHIFT 0x18 |
52307 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7__SHIFT 0x1a |
52308 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7__SHIFT 0x1c |
52309 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F7__SHIFT 0x1e |
52310 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6_MASK 0x00000003L |
52311 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6_MASK 0x0000000CL |
52312 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F6_MASK 0x00000030L |
52313 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6_MASK 0x000000C0L |
52314 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6_MASK 0x00000300L |
52315 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6_MASK 0x00000C00L |
52316 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6_MASK 0x00003000L |
52317 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F6_MASK 0x0000C000L |
52318 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7_MASK 0x00030000L |
52319 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7_MASK 0x000C0000L |
52320 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F7_MASK 0x00300000L |
52321 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7_MASK 0x00C00000L |
52322 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7_MASK 0x03000000L |
52323 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7_MASK 0x0C000000L |
52324 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7_MASK 0x30000000L |
52325 | #define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F7_MASK 0xC0000000L |
52326 | //BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1 |
52327 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F0__SHIFT 0x0 |
52328 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F0__SHIFT 0x2 |
52329 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F0__SHIFT 0x4 |
52330 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F0__SHIFT 0x6 |
52331 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F0__SHIFT 0x8 |
52332 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F0__SHIFT 0xa |
52333 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F0__SHIFT 0xc |
52334 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F0__SHIFT 0xe |
52335 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F1__SHIFT 0x10 |
52336 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F1__SHIFT 0x12 |
52337 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F1__SHIFT 0x14 |
52338 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F1__SHIFT 0x16 |
52339 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F1__SHIFT 0x18 |
52340 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F1__SHIFT 0x1a |
52341 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F1__SHIFT 0x1c |
52342 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F1__SHIFT 0x1e |
52343 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F0_MASK 0x00000003L |
52344 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F0_MASK 0x0000000CL |
52345 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F0_MASK 0x00000030L |
52346 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F0_MASK 0x000000C0L |
52347 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F0_MASK 0x00000300L |
52348 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F0_MASK 0x00000C00L |
52349 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F0_MASK 0x00003000L |
52350 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F0_MASK 0x0000C000L |
52351 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F1_MASK 0x00030000L |
52352 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F1_MASK 0x000C0000L |
52353 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F1_MASK 0x00300000L |
52354 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F1_MASK 0x00C00000L |
52355 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F1_MASK 0x03000000L |
52356 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F1_MASK 0x0C000000L |
52357 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F1_MASK 0x30000000L |
52358 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F1_MASK 0xC0000000L |
52359 | //BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3 |
52360 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F2__SHIFT 0x0 |
52361 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F2__SHIFT 0x2 |
52362 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F2__SHIFT 0x4 |
52363 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F2__SHIFT 0x6 |
52364 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F2__SHIFT 0x8 |
52365 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F2__SHIFT 0xa |
52366 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F2__SHIFT 0xc |
52367 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F2__SHIFT 0xe |
52368 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F3__SHIFT 0x10 |
52369 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F3__SHIFT 0x12 |
52370 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F3__SHIFT 0x14 |
52371 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F3__SHIFT 0x16 |
52372 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F3__SHIFT 0x18 |
52373 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F3__SHIFT 0x1a |
52374 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F3__SHIFT 0x1c |
52375 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F3__SHIFT 0x1e |
52376 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F2_MASK 0x00000003L |
52377 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F2_MASK 0x0000000CL |
52378 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F2_MASK 0x00000030L |
52379 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F2_MASK 0x000000C0L |
52380 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F2_MASK 0x00000300L |
52381 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F2_MASK 0x00000C00L |
52382 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F2_MASK 0x00003000L |
52383 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F2_MASK 0x0000C000L |
52384 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F3_MASK 0x00030000L |
52385 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F3_MASK 0x000C0000L |
52386 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F3_MASK 0x00300000L |
52387 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F3_MASK 0x00C00000L |
52388 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F3_MASK 0x03000000L |
52389 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F3_MASK 0x0C000000L |
52390 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F3_MASK 0x30000000L |
52391 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F3_MASK 0xC0000000L |
52392 | //BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5 |
52393 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F4__SHIFT 0x0 |
52394 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F4__SHIFT 0x2 |
52395 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F4__SHIFT 0x4 |
52396 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F4__SHIFT 0x6 |
52397 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F4__SHIFT 0x8 |
52398 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F4__SHIFT 0xa |
52399 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F4__SHIFT 0xc |
52400 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F4__SHIFT 0xe |
52401 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F5__SHIFT 0x10 |
52402 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F5__SHIFT 0x12 |
52403 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F5__SHIFT 0x14 |
52404 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F5__SHIFT 0x16 |
52405 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F5__SHIFT 0x18 |
52406 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F5__SHIFT 0x1a |
52407 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F5__SHIFT 0x1c |
52408 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F5__SHIFT 0x1e |
52409 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F4_MASK 0x00000003L |
52410 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F4_MASK 0x0000000CL |
52411 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F4_MASK 0x00000030L |
52412 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F4_MASK 0x000000C0L |
52413 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F4_MASK 0x00000300L |
52414 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F4_MASK 0x00000C00L |
52415 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F4_MASK 0x00003000L |
52416 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F4_MASK 0x0000C000L |
52417 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F5_MASK 0x00030000L |
52418 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F5_MASK 0x000C0000L |
52419 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F5_MASK 0x00300000L |
52420 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F5_MASK 0x00C00000L |
52421 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F5_MASK 0x03000000L |
52422 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F5_MASK 0x0C000000L |
52423 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F5_MASK 0x30000000L |
52424 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F5_MASK 0xC0000000L |
52425 | //BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7 |
52426 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F6__SHIFT 0x0 |
52427 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F6__SHIFT 0x2 |
52428 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F6__SHIFT 0x4 |
52429 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F6__SHIFT 0x6 |
52430 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F6__SHIFT 0x8 |
52431 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F6__SHIFT 0xa |
52432 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F6__SHIFT 0xc |
52433 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F6__SHIFT 0xe |
52434 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F7__SHIFT 0x10 |
52435 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F7__SHIFT 0x12 |
52436 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F7__SHIFT 0x14 |
52437 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F7__SHIFT 0x16 |
52438 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F7__SHIFT 0x18 |
52439 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F7__SHIFT 0x1a |
52440 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F7__SHIFT 0x1c |
52441 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F7__SHIFT 0x1e |
52442 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F6_MASK 0x00000003L |
52443 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F6_MASK 0x0000000CL |
52444 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F6_MASK 0x00000030L |
52445 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F6_MASK 0x000000C0L |
52446 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F6_MASK 0x00000300L |
52447 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F6_MASK 0x00000C00L |
52448 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F6_MASK 0x00003000L |
52449 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F6_MASK 0x0000C000L |
52450 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F7_MASK 0x00030000L |
52451 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F7_MASK 0x000C0000L |
52452 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F7_MASK 0x00300000L |
52453 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F7_MASK 0x00C00000L |
52454 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F7_MASK 0x03000000L |
52455 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F7_MASK 0x0C000000L |
52456 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F7_MASK 0x30000000L |
52457 | #define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F7_MASK 0xC0000000L |
52458 | //BIFC_DMA_ATTR_CNTL2_DEV0 |
52459 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT 0x0 |
52460 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT 0x4 |
52461 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT 0x8 |
52462 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT 0xc |
52463 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT 0x10 |
52464 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT 0x14 |
52465 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT 0x18 |
52466 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT 0x1c |
52467 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK 0x00000001L |
52468 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK 0x00000010L |
52469 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK 0x00000100L |
52470 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK 0x00001000L |
52471 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK 0x00010000L |
52472 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK 0x00100000L |
52473 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK 0x01000000L |
52474 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK 0x10000000L |
52475 | //BIFC_DMA_ATTR_CNTL2_DEV1 |
52476 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F0__SHIFT 0x0 |
52477 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F1__SHIFT 0x4 |
52478 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F2__SHIFT 0x8 |
52479 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F3__SHIFT 0xc |
52480 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F4__SHIFT 0x10 |
52481 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F5__SHIFT 0x14 |
52482 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F6__SHIFT 0x18 |
52483 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F7__SHIFT 0x1c |
52484 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F0_MASK 0x00000001L |
52485 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F1_MASK 0x00000010L |
52486 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F2_MASK 0x00000100L |
52487 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F3_MASK 0x00001000L |
52488 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F4_MASK 0x00010000L |
52489 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F5_MASK 0x00100000L |
52490 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F6_MASK 0x01000000L |
52491 | #define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F7_MASK 0x10000000L |
52492 | //BIFC_DMA_ATTR_CNTL2_DEV2 |
52493 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F0__SHIFT 0x0 |
52494 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F1__SHIFT 0x4 |
52495 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F2__SHIFT 0x8 |
52496 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F3__SHIFT 0xc |
52497 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F4__SHIFT 0x10 |
52498 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F5__SHIFT 0x14 |
52499 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F6__SHIFT 0x18 |
52500 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F7__SHIFT 0x1c |
52501 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F0_MASK 0x00000001L |
52502 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F1_MASK 0x00000010L |
52503 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F2_MASK 0x00000100L |
52504 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F3_MASK 0x00001000L |
52505 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F4_MASK 0x00010000L |
52506 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F5_MASK 0x00100000L |
52507 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F6_MASK 0x01000000L |
52508 | #define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F7_MASK 0x10000000L |
52509 | //BIFC_MISC_CTRL2 |
52510 | #define BIFC_MISC_CTRL2__SLFR_IGNORE_DATAERR_EN__SHIFT 0x10 |
52511 | #define BIFC_MISC_CTRL2__DATAERR_OVERRIDE_SLFR_BYTEEN_EN__SHIFT 0x11 |
52512 | #define BIFC_MISC_CTRL2__SLFR_IGNORE_DATAERR_EN_MASK 0x00010000L |
52513 | #define BIFC_MISC_CTRL2__DATAERR_OVERRIDE_SLFR_BYTEEN_EN_MASK 0x00020000L |
52514 | //BME_DUMMY_CNTL_0 |
52515 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0 |
52516 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2 |
52517 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4 |
52518 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6 |
52519 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8 |
52520 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa |
52521 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc |
52522 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe |
52523 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0__SHIFT 0x10 |
52524 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1__SHIFT 0x12 |
52525 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2__SHIFT 0x14 |
52526 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3__SHIFT 0x16 |
52527 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4__SHIFT 0x18 |
52528 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5__SHIFT 0x1a |
52529 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6__SHIFT 0x1c |
52530 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7__SHIFT 0x1e |
52531 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK 0x00000003L |
52532 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK 0x0000000CL |
52533 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK 0x00000030L |
52534 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK 0x000000C0L |
52535 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK 0x00000300L |
52536 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK 0x00000C00L |
52537 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK 0x00003000L |
52538 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK 0x0000C000L |
52539 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0_MASK 0x00030000L |
52540 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1_MASK 0x000C0000L |
52541 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2_MASK 0x00300000L |
52542 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3_MASK 0x00C00000L |
52543 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4_MASK 0x03000000L |
52544 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5_MASK 0x0C000000L |
52545 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6_MASK 0x30000000L |
52546 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7_MASK 0xC0000000L |
52547 | //BME_DUMMY_CNTL_1 |
52548 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F0__SHIFT 0x0 |
52549 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F1__SHIFT 0x2 |
52550 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F2__SHIFT 0x4 |
52551 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F3__SHIFT 0x6 |
52552 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F4__SHIFT 0x8 |
52553 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F5__SHIFT 0xa |
52554 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F6__SHIFT 0xc |
52555 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F7__SHIFT 0xe |
52556 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F0_MASK 0x00000003L |
52557 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F1_MASK 0x0000000CL |
52558 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F2_MASK 0x00000030L |
52559 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F3_MASK 0x000000C0L |
52560 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F4_MASK 0x00000300L |
52561 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F5_MASK 0x00000C00L |
52562 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F6_MASK 0x00003000L |
52563 | #define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F7_MASK 0x0000C000L |
52564 | //BIFC_THT_CNTL |
52565 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0 |
52566 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4 |
52567 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8 |
52568 | #define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x10 |
52569 | #define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS__SHIFT 0x18 |
52570 | #define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS__SHIFT 0x19 |
52571 | #define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS__SHIFT 0x1a |
52572 | #define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS__SHIFT 0x1b |
52573 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK 0x0000000FL |
52574 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK 0x000000F0L |
52575 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK 0x00000F00L |
52576 | #define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x00010000L |
52577 | #define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS_MASK 0x01000000L |
52578 | #define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS_MASK 0x02000000L |
52579 | #define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS_MASK 0x04000000L |
52580 | #define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS_MASK 0x08000000L |
52581 | //BIFC_HSTARB_CNTL |
52582 | #define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0 |
52583 | #define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN__SHIFT 0x8 |
52584 | #define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK 0x00000003L |
52585 | #define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN_MASK 0x00000100L |
52586 | //BIFC_GSI_CNTL |
52587 | #define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0 |
52588 | #define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2 |
52589 | #define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5 |
52590 | #define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6 |
52591 | #define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7 |
52592 | #define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8 |
52593 | #define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x9 |
52594 | #define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa |
52595 | #define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc |
52596 | #define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN__SHIFT 0xe |
52597 | #define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK__SHIFT 0xf |
52598 | #define BIFC_GSI_CNTL__GSI_SMN_BURST_EN__SHIFT 0x10 |
52599 | #define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN__SHIFT 0x11 |
52600 | #define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE__SHIFT 0x1b |
52601 | #define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH__SHIFT 0x1c |
52602 | #define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH__SHIFT 0x1d |
52603 | #define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD__SHIFT 0x1e |
52604 | #define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL__SHIFT 0x1f |
52605 | #define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK 0x00000003L |
52606 | #define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK 0x0000001CL |
52607 | #define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK 0x00000020L |
52608 | #define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK 0x00000040L |
52609 | #define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK 0x00000080L |
52610 | #define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK 0x00000100L |
52611 | #define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK 0x00000200L |
52612 | #define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK 0x00000C00L |
52613 | #define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK 0x00003000L |
52614 | #define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN_MASK 0x00004000L |
52615 | #define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK_MASK 0x00008000L |
52616 | #define BIFC_GSI_CNTL__GSI_SMN_BURST_EN_MASK 0x00010000L |
52617 | #define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN_MASK 0x00020000L |
52618 | #define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE_MASK 0x08000000L |
52619 | #define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH_MASK 0x10000000L |
52620 | #define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH_MASK 0x20000000L |
52621 | #define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD_MASK 0x40000000L |
52622 | #define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL_MASK 0x80000000L |
52623 | //BIFC_PCIEFUNC_CNTL |
52624 | #define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0 |
52625 | #define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10 |
52626 | #define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK 0x0000FFFFL |
52627 | #define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK 0x00010000L |
52628 | //BIFC_PASID_CHECK_DIS |
52629 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT 0x0 |
52630 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT 0x1 |
52631 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2__SHIFT 0x2 |
52632 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3__SHIFT 0x3 |
52633 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F4__SHIFT 0x4 |
52634 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F5__SHIFT 0x5 |
52635 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F6__SHIFT 0x6 |
52636 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F7__SHIFT 0x7 |
52637 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F0__SHIFT 0x8 |
52638 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F1__SHIFT 0x9 |
52639 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F0__SHIFT 0x10 |
52640 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F1__SHIFT 0x11 |
52641 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F2__SHIFT 0x12 |
52642 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F3__SHIFT 0x13 |
52643 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F4__SHIFT 0x14 |
52644 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F5__SHIFT 0x15 |
52645 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F6__SHIFT 0x16 |
52646 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK 0x00000001L |
52647 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK 0x00000002L |
52648 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2_MASK 0x00000004L |
52649 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3_MASK 0x00000008L |
52650 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F4_MASK 0x00000010L |
52651 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F5_MASK 0x00000020L |
52652 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F6_MASK 0x00000040L |
52653 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F7_MASK 0x00000080L |
52654 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F0_MASK 0x00000100L |
52655 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F1_MASK 0x00000200L |
52656 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F0_MASK 0x00010000L |
52657 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F1_MASK 0x00020000L |
52658 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F2_MASK 0x00040000L |
52659 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F3_MASK 0x00080000L |
52660 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F4_MASK 0x00100000L |
52661 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F5_MASK 0x00200000L |
52662 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F6_MASK 0x00400000L |
52663 | //BIFC_SDP_CNTL_0 |
52664 | #define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0 |
52665 | #define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x8 |
52666 | #define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0x10 |
52667 | #define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x18 |
52668 | #define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK 0x000000FFL |
52669 | #define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK 0x0000FF00L |
52670 | #define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK 0x00FF0000L |
52671 | #define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK 0xFF000000L |
52672 | //BIFC_SDP_CNTL_1 |
52673 | #define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT 0x0 |
52674 | #define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT 0x1 |
52675 | #define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT 0x2 |
52676 | #define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT 0x3 |
52677 | #define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x4 |
52678 | #define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P__SHIFT 0x5 |
52679 | #define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x7 |
52680 | #define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN__SHIFT 0x8 |
52681 | #define BIFC_SDP_CNTL_1__NBIF_OBFF_HW_URGENT_EARLY_WAKEUP_EN__SHIFT 0x1e |
52682 | #define BIFC_SDP_CNTL_1__GMI_UPS_SDP_WAKEUP_BY_USB_EARLY_WAKEUP_EN__SHIFT 0x1f |
52683 | #define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK 0x00000001L |
52684 | #define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK 0x00000002L |
52685 | #define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK 0x00000004L |
52686 | #define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK 0x00000008L |
52687 | #define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000010L |
52688 | #define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P_MASK 0x00000020L |
52689 | #define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000080L |
52690 | #define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN_MASK 0x00000100L |
52691 | #define BIFC_SDP_CNTL_1__NBIF_OBFF_HW_URGENT_EARLY_WAKEUP_EN_MASK 0x40000000L |
52692 | #define BIFC_SDP_CNTL_1__GMI_UPS_SDP_WAKEUP_BY_USB_EARLY_WAKEUP_EN_MASK 0x80000000L |
52693 | //BIFC_PASID_STS |
52694 | #define BIFC_PASID_STS__PASID_STS__SHIFT 0x0 |
52695 | #define BIFC_PASID_STS__PASID_STS_MASK 0x0000000FL |
52696 | //BIFC_ATHUB_ACT_CNTL |
52697 | #define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT 0x0 |
52698 | #define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE__SHIFT 0x3 |
52699 | #define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT 0x8 |
52700 | #define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_DIS__SHIFT 0x9 |
52701 | #define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_DIS__SHIFT 0xa |
52702 | #define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN__SHIFT 0xb |
52703 | #define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK 0x00000007L |
52704 | #define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE_MASK 0x00000038L |
52705 | #define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK 0x00000100L |
52706 | #define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_DIS_MASK 0x00000200L |
52707 | #define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_DIS_MASK 0x00000400L |
52708 | #define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN_MASK 0x00000800L |
52709 | //BIFC_PERF_CNTL_0 |
52710 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0 |
52711 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1 |
52712 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8 |
52713 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9 |
52714 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10 |
52715 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18 |
52716 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK 0x00000001L |
52717 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK 0x00000002L |
52718 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK 0x00000100L |
52719 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK 0x00000200L |
52720 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK 0x007F0000L |
52721 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK 0x7F000000L |
52722 | //BIFC_PERF_CNTL_1 |
52723 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0 |
52724 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1 |
52725 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x4 |
52726 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x5 |
52727 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x8 |
52728 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x10 |
52729 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK 0x00000001L |
52730 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK 0x00000002L |
52731 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK 0x00000010L |
52732 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK 0x00000020L |
52733 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK 0x0000FF00L |
52734 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK 0x01FF0000L |
52735 | //BIFC_PERF_CNT_MMIO_RD_L32BIT |
52736 | #define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT__SHIFT 0x0 |
52737 | #define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT_MASK 0xFFFFFFFFL |
52738 | //BIFC_PERF_CNT_MMIO_WR_L32BIT |
52739 | #define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT__SHIFT 0x0 |
52740 | #define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT_MASK 0xFFFFFFFFL |
52741 | //BIFC_PERF_CNT_DMA_RD_L32BIT |
52742 | #define BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT__SHIFT 0x0 |
52743 | #define BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT_MASK 0xFFFFFFFFL |
52744 | //BIFC_PERF_CNT_DMA_WR_L32BIT |
52745 | #define BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT__SHIFT 0x0 |
52746 | #define BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT_MASK 0xFFFFFFFFL |
52747 | //NBIF_REGIF_ERRSET_CTRL |
52748 | #define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 |
52749 | #define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L |
52750 | //BIFC_SDP_CNTL_2 |
52751 | #define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS__SHIFT 0x0 |
52752 | #define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H__SHIFT 0x8 |
52753 | #define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H__SHIFT 0x10 |
52754 | #define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H__SHIFT 0x18 |
52755 | #define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_MASK 0x000000FFL |
52756 | #define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H_MASK 0x00000F00L |
52757 | #define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H_MASK 0x000F0000L |
52758 | #define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H_MASK 0x0F000000L |
52759 | //NBIF_PGMST_CTRL |
52760 | #define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT 0x0 |
52761 | #define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT 0x8 |
52762 | #define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT 0xa |
52763 | #define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT 0xe |
52764 | #define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK 0x000000FFL |
52765 | #define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK 0x00000100L |
52766 | #define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L |
52767 | #define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L |
52768 | //NBIF_PGSLV_CTRL |
52769 | #define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT 0x0 |
52770 | #define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK 0x0000001FL |
52771 | //NBIF_PG_MISC_CTRL |
52772 | #define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT 0xa |
52773 | #define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1__SHIFT 0xd |
52774 | #define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT 0xe |
52775 | #define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2__SHIFT 0x10 |
52776 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 |
52777 | #define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK__SHIFT 0x1e |
52778 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f |
52779 | #define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK 0x00000400L |
52780 | #define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1_MASK 0x00002000L |
52781 | #define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK 0x00004000L |
52782 | #define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2_MASK 0x00010000L |
52783 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L |
52784 | #define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK_MASK 0x40000000L |
52785 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L |
52786 | //NBIF_HST_MISC_CTRL |
52787 | #define NBIF_HST_MISC_CTRL__ACP_NP_OSTD_LIMIT__SHIFT 0x0 |
52788 | #define NBIF_HST_MISC_CTRL__ACP_NP_OSTD_LIMIT_MASK 0x000000FFL |
52789 | //SMN_MST_EP_CNTL3 |
52790 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0 |
52791 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1 |
52792 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2 |
52793 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3 |
52794 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4 |
52795 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5 |
52796 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6 |
52797 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7 |
52798 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF0__SHIFT 0x8 |
52799 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF1__SHIFT 0x9 |
52800 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF2__SHIFT 0xa |
52801 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF3__SHIFT 0xb |
52802 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF4__SHIFT 0xc |
52803 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF5__SHIFT 0xd |
52804 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF6__SHIFT 0xe |
52805 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF7__SHIFT 0xf |
52806 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF0__SHIFT 0x10 |
52807 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF1__SHIFT 0x11 |
52808 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF2__SHIFT 0x12 |
52809 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF3__SHIFT 0x13 |
52810 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF4__SHIFT 0x14 |
52811 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF5__SHIFT 0x15 |
52812 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF6__SHIFT 0x16 |
52813 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF7__SHIFT 0x17 |
52814 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK 0x00000001L |
52815 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK 0x00000002L |
52816 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK 0x00000004L |
52817 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK 0x00000008L |
52818 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK 0x00000010L |
52819 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK 0x00000020L |
52820 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK 0x00000040L |
52821 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK 0x00000080L |
52822 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF0_MASK 0x00000100L |
52823 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF1_MASK 0x00000200L |
52824 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF2_MASK 0x00000400L |
52825 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF3_MASK 0x00000800L |
52826 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF4_MASK 0x00001000L |
52827 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF5_MASK 0x00002000L |
52828 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF6_MASK 0x00004000L |
52829 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF7_MASK 0x00008000L |
52830 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF0_MASK 0x00010000L |
52831 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF1_MASK 0x00020000L |
52832 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF2_MASK 0x00040000L |
52833 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF3_MASK 0x00080000L |
52834 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF4_MASK 0x00100000L |
52835 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF5_MASK 0x00200000L |
52836 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF6_MASK 0x00400000L |
52837 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF7_MASK 0x00800000L |
52838 | //SMN_MST_EP_CNTL4 |
52839 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0 |
52840 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1 |
52841 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2 |
52842 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3 |
52843 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4 |
52844 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5 |
52845 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6 |
52846 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7 |
52847 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF0__SHIFT 0x8 |
52848 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF1__SHIFT 0x9 |
52849 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF2__SHIFT 0xa |
52850 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF3__SHIFT 0xb |
52851 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF4__SHIFT 0xc |
52852 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF5__SHIFT 0xd |
52853 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF6__SHIFT 0xe |
52854 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF7__SHIFT 0xf |
52855 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF0__SHIFT 0x10 |
52856 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF1__SHIFT 0x11 |
52857 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF2__SHIFT 0x12 |
52858 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF3__SHIFT 0x13 |
52859 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF4__SHIFT 0x14 |
52860 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF5__SHIFT 0x15 |
52861 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF6__SHIFT 0x16 |
52862 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF7__SHIFT 0x17 |
52863 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK 0x00000001L |
52864 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK 0x00000002L |
52865 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK 0x00000004L |
52866 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK 0x00000008L |
52867 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK 0x00000010L |
52868 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK 0x00000020L |
52869 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK 0x00000040L |
52870 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK 0x00000080L |
52871 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF0_MASK 0x00000100L |
52872 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF1_MASK 0x00000200L |
52873 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF2_MASK 0x00000400L |
52874 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF3_MASK 0x00000800L |
52875 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF4_MASK 0x00001000L |
52876 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF5_MASK 0x00002000L |
52877 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF6_MASK 0x00004000L |
52878 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF7_MASK 0x00008000L |
52879 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF0_MASK 0x00010000L |
52880 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF1_MASK 0x00020000L |
52881 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF2_MASK 0x00040000L |
52882 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF3_MASK 0x00080000L |
52883 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF4_MASK 0x00100000L |
52884 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF5_MASK 0x00200000L |
52885 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF6_MASK 0x00400000L |
52886 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF7_MASK 0x00800000L |
52887 | //SMN_MST_CNTL1 |
52888 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT 0x0 |
52889 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT 0x10 |
52890 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV1__SHIFT 0x11 |
52891 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV2__SHIFT 0x12 |
52892 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK 0x00000001L |
52893 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK 0x00010000L |
52894 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV1_MASK 0x00020000L |
52895 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV2_MASK 0x00040000L |
52896 | //SMN_MST_EP_CNTL5 |
52897 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT 0x0 |
52898 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT 0x1 |
52899 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT 0x2 |
52900 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT 0x3 |
52901 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT 0x4 |
52902 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT 0x5 |
52903 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT 0x6 |
52904 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT 0x7 |
52905 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF0__SHIFT 0x8 |
52906 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF1__SHIFT 0x9 |
52907 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF2__SHIFT 0xa |
52908 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF3__SHIFT 0xb |
52909 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF4__SHIFT 0xc |
52910 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF5__SHIFT 0xd |
52911 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF6__SHIFT 0xe |
52912 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF7__SHIFT 0xf |
52913 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF0__SHIFT 0x10 |
52914 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF1__SHIFT 0x11 |
52915 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF2__SHIFT 0x12 |
52916 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF3__SHIFT 0x13 |
52917 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF4__SHIFT 0x14 |
52918 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF5__SHIFT 0x15 |
52919 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF6__SHIFT 0x16 |
52920 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF7__SHIFT 0x17 |
52921 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK 0x00000001L |
52922 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK 0x00000002L |
52923 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK 0x00000004L |
52924 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK 0x00000008L |
52925 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK 0x00000010L |
52926 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK 0x00000020L |
52927 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK 0x00000040L |
52928 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK 0x00000080L |
52929 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF0_MASK 0x00000100L |
52930 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF1_MASK 0x00000200L |
52931 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF2_MASK 0x00000400L |
52932 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF3_MASK 0x00000800L |
52933 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF4_MASK 0x00001000L |
52934 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF5_MASK 0x00002000L |
52935 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF6_MASK 0x00004000L |
52936 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF7_MASK 0x00008000L |
52937 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF0_MASK 0x00010000L |
52938 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF1_MASK 0x00020000L |
52939 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF2_MASK 0x00040000L |
52940 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF3_MASK 0x00080000L |
52941 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF4_MASK 0x00100000L |
52942 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF5_MASK 0x00200000L |
52943 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF6_MASK 0x00400000L |
52944 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF7_MASK 0x00800000L |
52945 | //BIF_SELFRING_BUFFER_VID |
52946 | #define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0 |
52947 | #define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT 0x8 |
52948 | #define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT 0x10 |
52949 | #define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK 0x000000FFL |
52950 | #define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK 0x0000FF00L |
52951 | #define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK 0x00FF0000L |
52952 | //BIF_SELFRING_VECTOR_CNTL |
52953 | #define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0 |
52954 | #define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT 0x1 |
52955 | #define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK 0x00000001L |
52956 | #define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK 0x00000002L |
52957 | //NBIF_INTX_DSTATE_MISC_CNTL |
52958 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x0 |
52959 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x1 |
52960 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x2 |
52961 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x3 |
52962 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x4 |
52963 | #define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT 0x5 |
52964 | #define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT 0x6 |
52965 | #define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x7 |
52966 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00000001L |
52967 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00000002L |
52968 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00000004L |
52969 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00000008L |
52970 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00000010L |
52971 | #define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK 0x00000020L |
52972 | #define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK 0x00000040L |
52973 | #define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000080L |
52974 | //NBIF_PENDING_MISC_CNTL |
52975 | #define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT 0x0 |
52976 | #define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT 0x1 |
52977 | #define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK 0x00000001L |
52978 | #define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK 0x00000002L |
52979 | //BIF_GMI_WRR_WEIGHT |
52980 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE__SHIFT 0x1d |
52981 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE__SHIFT 0x1e |
52982 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE__SHIFT 0x1f |
52983 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE_MASK 0x20000000L |
52984 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE_MASK 0x40000000L |
52985 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE_MASK 0x80000000L |
52986 | //BIF_GMI_WRR_WEIGHT2 |
52987 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT 0x0 |
52988 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT 0x8 |
52989 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT 0x10 |
52990 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT 0x18 |
52991 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK 0x000000FFL |
52992 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK 0x0000FF00L |
52993 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK 0x00FF0000L |
52994 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK 0xFF000000L |
52995 | //BIF_GMI_WRR_WEIGHT3 |
52996 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT 0x0 |
52997 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT 0x8 |
52998 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT 0x10 |
52999 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT 0x18 |
53000 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK 0x000000FFL |
53001 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK 0x0000FF00L |
53002 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK 0x00FF0000L |
53003 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK 0xFF000000L |
53004 | //NBIF_PWRBRK_REQUEST |
53005 | #define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT 0x0 |
53006 | #define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK 0x00000001L |
53007 | //BIF_DMA_MP4_ERR_LOG |
53008 | //BIF_PASID_ERR_LOG |
53009 | //BIF_PASID_ERR_CLR |
53010 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT 0x0 |
53011 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT 0x1 |
53012 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2__SHIFT 0x2 |
53013 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3__SHIFT 0x3 |
53014 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F4__SHIFT 0x4 |
53015 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F5__SHIFT 0x5 |
53016 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F6__SHIFT 0x6 |
53017 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F7__SHIFT 0x7 |
53018 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F0__SHIFT 0x8 |
53019 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F1__SHIFT 0x9 |
53020 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F0__SHIFT 0x10 |
53021 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F1__SHIFT 0x11 |
53022 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F2__SHIFT 0x12 |
53023 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F3__SHIFT 0x13 |
53024 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F4__SHIFT 0x14 |
53025 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F5__SHIFT 0x15 |
53026 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F6__SHIFT 0x16 |
53027 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK 0x00000001L |
53028 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK 0x00000002L |
53029 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2_MASK 0x00000004L |
53030 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3_MASK 0x00000008L |
53031 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F4_MASK 0x00000010L |
53032 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F5_MASK 0x00000020L |
53033 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F6_MASK 0x00000040L |
53034 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F7_MASK 0x00000080L |
53035 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F0_MASK 0x00000100L |
53036 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F1_MASK 0x00000200L |
53037 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F0_MASK 0x00010000L |
53038 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F1_MASK 0x00020000L |
53039 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F2_MASK 0x00040000L |
53040 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F3_MASK 0x00080000L |
53041 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F4_MASK 0x00100000L |
53042 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F5_MASK 0x00200000L |
53043 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F6_MASK 0x00400000L |
53044 | //OBFF_EMU_CFG |
53045 | #define OBFF_EMU_CFG__OBFF_EMU_INTR_EN__SHIFT 0x0 |
53046 | #define OBFF_EMU_CFG__OBFF_EMU_INTR_EN_MASK 0x00000001L |
53047 | //EP0_INTR_URGENT_CAP |
53048 | #define EP0_INTR_URGENT_CAP__EP0_F0_INTR_URGENT_MODE__SHIFT 0x0 |
53049 | #define EP0_INTR_URGENT_CAP__EP0_F1_INTR_URGENT_MODE__SHIFT 0x2 |
53050 | #define EP0_INTR_URGENT_CAP__EP0_F2_INTR_URGENT_MODE__SHIFT 0x4 |
53051 | #define EP0_INTR_URGENT_CAP__EP0_F3_INTR_URGENT_MODE__SHIFT 0x6 |
53052 | #define EP0_INTR_URGENT_CAP__EP0_F4_INTR_URGENT_MODE__SHIFT 0x8 |
53053 | #define EP0_INTR_URGENT_CAP__EP0_F5_INTR_URGENT_MODE__SHIFT 0xa |
53054 | #define EP0_INTR_URGENT_CAP__EP0_F6_INTR_URGENT_MODE__SHIFT 0xc |
53055 | #define EP0_INTR_URGENT_CAP__EP0_F7_INTR_URGENT_MODE__SHIFT 0xe |
53056 | #define EP0_INTR_URGENT_CAP__EP0_F0_INTR_URGENT_MODE_MASK 0x00000003L |
53057 | #define EP0_INTR_URGENT_CAP__EP0_F1_INTR_URGENT_MODE_MASK 0x0000000CL |
53058 | #define EP0_INTR_URGENT_CAP__EP0_F2_INTR_URGENT_MODE_MASK 0x00000030L |
53059 | #define EP0_INTR_URGENT_CAP__EP0_F3_INTR_URGENT_MODE_MASK 0x000000C0L |
53060 | #define EP0_INTR_URGENT_CAP__EP0_F4_INTR_URGENT_MODE_MASK 0x00000300L |
53061 | #define EP0_INTR_URGENT_CAP__EP0_F5_INTR_URGENT_MODE_MASK 0x00000C00L |
53062 | #define EP0_INTR_URGENT_CAP__EP0_F6_INTR_URGENT_MODE_MASK 0x00003000L |
53063 | #define EP0_INTR_URGENT_CAP__EP0_F7_INTR_URGENT_MODE_MASK 0x0000C000L |
53064 | //EP1_INTR_URGENT_CAP |
53065 | #define EP1_INTR_URGENT_CAP__EP1_F0_INTR_URGENT_MODE__SHIFT 0x0 |
53066 | #define EP1_INTR_URGENT_CAP__EP1_F1_INTR_URGENT_MODE__SHIFT 0x2 |
53067 | #define EP1_INTR_URGENT_CAP__EP1_F0_INTR_URGENT_MODE_MASK 0x00000003L |
53068 | #define EP1_INTR_URGENT_CAP__EP1_F1_INTR_URGENT_MODE_MASK 0x0000000CL |
53069 | //EP2_INTR_URGENT_CAP |
53070 | #define EP2_INTR_URGENT_CAP__EP2_F0_INTR_URGENT_MODE__SHIFT 0x0 |
53071 | #define EP2_INTR_URGENT_CAP__EP2_F1_INTR_URGENT_MODE__SHIFT 0x2 |
53072 | #define EP2_INTR_URGENT_CAP__EP2_F2_INTR_URGENT_MODE__SHIFT 0x4 |
53073 | #define EP2_INTR_URGENT_CAP__EP2_F3_INTR_URGENT_MODE__SHIFT 0x6 |
53074 | #define EP2_INTR_URGENT_CAP__EP2_F4_INTR_URGENT_MODE__SHIFT 0x8 |
53075 | #define EP2_INTR_URGENT_CAP__EP2_F5_INTR_URGENT_MODE__SHIFT 0xa |
53076 | #define EP2_INTR_URGENT_CAP__EP2_F6_INTR_URGENT_MODE__SHIFT 0xc |
53077 | #define EP2_INTR_URGENT_CAP__EP2_F0_INTR_URGENT_MODE_MASK 0x00000003L |
53078 | #define EP2_INTR_URGENT_CAP__EP2_F1_INTR_URGENT_MODE_MASK 0x0000000CL |
53079 | #define EP2_INTR_URGENT_CAP__EP2_F2_INTR_URGENT_MODE_MASK 0x00000030L |
53080 | #define EP2_INTR_URGENT_CAP__EP2_F3_INTR_URGENT_MODE_MASK 0x000000C0L |
53081 | #define EP2_INTR_URGENT_CAP__EP2_F4_INTR_URGENT_MODE_MASK 0x00000300L |
53082 | #define EP2_INTR_URGENT_CAP__EP2_F5_INTR_URGENT_MODE_MASK 0x00000C00L |
53083 | #define EP2_INTR_URGENT_CAP__EP2_F6_INTR_URGENT_MODE_MASK 0x00003000L |
53084 | //EP_PEND_BLOCK_MSK |
53085 | #define EP_PEND_BLOCK_MSK__EP0_F0_PEND_BLOCK_MSK__SHIFT 0x0 |
53086 | #define EP_PEND_BLOCK_MSK__EP0_F1_PEND_BLOCK_MSK__SHIFT 0x1 |
53087 | #define EP_PEND_BLOCK_MSK__EP0_F2_PEND_BLOCK_MSK__SHIFT 0x2 |
53088 | #define EP_PEND_BLOCK_MSK__EP0_F3_PEND_BLOCK_MSK__SHIFT 0x3 |
53089 | #define EP_PEND_BLOCK_MSK__EP0_F4_PEND_BLOCK_MSK__SHIFT 0x4 |
53090 | #define EP_PEND_BLOCK_MSK__EP0_F5_PEND_BLOCK_MSK__SHIFT 0x5 |
53091 | #define EP_PEND_BLOCK_MSK__EP0_F6_PEND_BLOCK_MSK__SHIFT 0x6 |
53092 | #define EP_PEND_BLOCK_MSK__EP0_F7_PEND_BLOCK_MSK__SHIFT 0x7 |
53093 | #define EP_PEND_BLOCK_MSK__EP1_F0_PEND_BLOCK_MSK__SHIFT 0x8 |
53094 | #define EP_PEND_BLOCK_MSK__EP1_F1_PEND_BLOCK_MSK__SHIFT 0x9 |
53095 | #define EP_PEND_BLOCK_MSK__EP2_F0_PEND_BLOCK_MSK__SHIFT 0x10 |
53096 | #define EP_PEND_BLOCK_MSK__EP2_F1_PEND_BLOCK_MSK__SHIFT 0x11 |
53097 | #define EP_PEND_BLOCK_MSK__EP2_F2_PEND_BLOCK_MSK__SHIFT 0x12 |
53098 | #define EP_PEND_BLOCK_MSK__EP2_F3_PEND_BLOCK_MSK__SHIFT 0x13 |
53099 | #define EP_PEND_BLOCK_MSK__EP2_F4_PEND_BLOCK_MSK__SHIFT 0x14 |
53100 | #define EP_PEND_BLOCK_MSK__EP2_F5_PEND_BLOCK_MSK__SHIFT 0x15 |
53101 | #define EP_PEND_BLOCK_MSK__EP2_F6_PEND_BLOCK_MSK__SHIFT 0x16 |
53102 | #define EP_PEND_BLOCK_MSK__EP0_F0_PEND_BLOCK_MSK_MASK 0x00000001L |
53103 | #define EP_PEND_BLOCK_MSK__EP0_F1_PEND_BLOCK_MSK_MASK 0x00000002L |
53104 | #define EP_PEND_BLOCK_MSK__EP0_F2_PEND_BLOCK_MSK_MASK 0x00000004L |
53105 | #define EP_PEND_BLOCK_MSK__EP0_F3_PEND_BLOCK_MSK_MASK 0x00000008L |
53106 | #define EP_PEND_BLOCK_MSK__EP0_F4_PEND_BLOCK_MSK_MASK 0x00000010L |
53107 | #define EP_PEND_BLOCK_MSK__EP0_F5_PEND_BLOCK_MSK_MASK 0x00000020L |
53108 | #define EP_PEND_BLOCK_MSK__EP0_F6_PEND_BLOCK_MSK_MASK 0x00000040L |
53109 | #define EP_PEND_BLOCK_MSK__EP0_F7_PEND_BLOCK_MSK_MASK 0x00000080L |
53110 | #define EP_PEND_BLOCK_MSK__EP1_F0_PEND_BLOCK_MSK_MASK 0x00000100L |
53111 | #define EP_PEND_BLOCK_MSK__EP1_F1_PEND_BLOCK_MSK_MASK 0x00000200L |
53112 | #define EP_PEND_BLOCK_MSK__EP2_F0_PEND_BLOCK_MSK_MASK 0x00010000L |
53113 | #define EP_PEND_BLOCK_MSK__EP2_F1_PEND_BLOCK_MSK_MASK 0x00020000L |
53114 | #define EP_PEND_BLOCK_MSK__EP2_F2_PEND_BLOCK_MSK_MASK 0x00040000L |
53115 | #define EP_PEND_BLOCK_MSK__EP2_F3_PEND_BLOCK_MSK_MASK 0x00080000L |
53116 | #define EP_PEND_BLOCK_MSK__EP2_F4_PEND_BLOCK_MSK_MASK 0x00100000L |
53117 | #define EP_PEND_BLOCK_MSK__EP2_F5_PEND_BLOCK_MSK_MASK 0x00200000L |
53118 | #define EP_PEND_BLOCK_MSK__EP2_F6_PEND_BLOCK_MSK_MASK 0x00400000L |
53119 | //NBIF_VWIRE_CTRL |
53120 | #define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4 |
53121 | #define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8 |
53122 | #define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14 |
53123 | #define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a |
53124 | #define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK 0x000000F0L |
53125 | #define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK 0x00000100L |
53126 | #define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK 0x00F00000L |
53127 | #define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK 0x0C000000L |
53128 | //NBIF_MGCG_CTRL_LCLK |
53129 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT 0x0 |
53130 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT 0x1 |
53131 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT 0x2 |
53132 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT 0xa |
53133 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT 0xb |
53134 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT 0xc |
53135 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT 0xd |
53136 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK 0x00000001L |
53137 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK 0x00000002L |
53138 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK 0x000003FCL |
53139 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK 0x00000400L |
53140 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK 0x00000800L |
53141 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L |
53142 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK 0x00002000L |
53143 | //NBIF_DS_CTRL_LCLK |
53144 | #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0 |
53145 | #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10 |
53146 | #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK 0x00000001L |
53147 | #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK 0xFFFF0000L |
53148 | //SMN_MST_CNTL0 |
53149 | #define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0 |
53150 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8 |
53151 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9 |
53152 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa |
53153 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb |
53154 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10 |
53155 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV1__SHIFT 0x11 |
53156 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV2__SHIFT 0x12 |
53157 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14 |
53158 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV1__SHIFT 0x15 |
53159 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV2__SHIFT 0x16 |
53160 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18 |
53161 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV1__SHIFT 0x19 |
53162 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV2__SHIFT 0x1a |
53163 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c |
53164 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV1__SHIFT 0x1d |
53165 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV2__SHIFT 0x1e |
53166 | #define SMN_MST_CNTL0__SMN_ARB_MODE_MASK 0x00000003L |
53167 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK 0x00000100L |
53168 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK 0x00000200L |
53169 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK 0x00000400L |
53170 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK 0x00000800L |
53171 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK 0x00010000L |
53172 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV1_MASK 0x00020000L |
53173 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV2_MASK 0x00040000L |
53174 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK 0x00100000L |
53175 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV1_MASK 0x00200000L |
53176 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV2_MASK 0x00400000L |
53177 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK 0x01000000L |
53178 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV1_MASK 0x02000000L |
53179 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV2_MASK 0x04000000L |
53180 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK 0x10000000L |
53181 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV1_MASK 0x20000000L |
53182 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV2_MASK 0x40000000L |
53183 | //SMN_MST_EP_CNTL1 |
53184 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0 |
53185 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1 |
53186 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2 |
53187 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3 |
53188 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4 |
53189 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5 |
53190 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6 |
53191 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7 |
53192 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF0__SHIFT 0x8 |
53193 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF1__SHIFT 0x9 |
53194 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF2__SHIFT 0xa |
53195 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF3__SHIFT 0xb |
53196 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF4__SHIFT 0xc |
53197 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF5__SHIFT 0xd |
53198 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF6__SHIFT 0xe |
53199 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF7__SHIFT 0xf |
53200 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF0__SHIFT 0x10 |
53201 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF1__SHIFT 0x11 |
53202 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF2__SHIFT 0x12 |
53203 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF3__SHIFT 0x13 |
53204 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF4__SHIFT 0x14 |
53205 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF5__SHIFT 0x15 |
53206 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF6__SHIFT 0x16 |
53207 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF7__SHIFT 0x17 |
53208 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK 0x00000001L |
53209 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK 0x00000002L |
53210 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK 0x00000004L |
53211 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK 0x00000008L |
53212 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK 0x00000010L |
53213 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK 0x00000020L |
53214 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK 0x00000040L |
53215 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK 0x00000080L |
53216 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF0_MASK 0x00000100L |
53217 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF1_MASK 0x00000200L |
53218 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF2_MASK 0x00000400L |
53219 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF3_MASK 0x00000800L |
53220 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF4_MASK 0x00001000L |
53221 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF5_MASK 0x00002000L |
53222 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF6_MASK 0x00004000L |
53223 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF7_MASK 0x00008000L |
53224 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF0_MASK 0x00010000L |
53225 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF1_MASK 0x00020000L |
53226 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF2_MASK 0x00040000L |
53227 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF3_MASK 0x00080000L |
53228 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF4_MASK 0x00100000L |
53229 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF5_MASK 0x00200000L |
53230 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF6_MASK 0x00400000L |
53231 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF7_MASK 0x00800000L |
53232 | //SMN_MST_EP_CNTL2 |
53233 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0 |
53234 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1 |
53235 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2 |
53236 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3 |
53237 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4 |
53238 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5 |
53239 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6 |
53240 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7 |
53241 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF0__SHIFT 0x8 |
53242 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF1__SHIFT 0x9 |
53243 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF2__SHIFT 0xa |
53244 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF3__SHIFT 0xb |
53245 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF4__SHIFT 0xc |
53246 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF5__SHIFT 0xd |
53247 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF6__SHIFT 0xe |
53248 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF7__SHIFT 0xf |
53249 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF0__SHIFT 0x10 |
53250 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF1__SHIFT 0x11 |
53251 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF2__SHIFT 0x12 |
53252 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF3__SHIFT 0x13 |
53253 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF4__SHIFT 0x14 |
53254 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF5__SHIFT 0x15 |
53255 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF6__SHIFT 0x16 |
53256 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF7__SHIFT 0x17 |
53257 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK 0x00000001L |
53258 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK 0x00000002L |
53259 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK 0x00000004L |
53260 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK 0x00000008L |
53261 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK 0x00000010L |
53262 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK 0x00000020L |
53263 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK 0x00000040L |
53264 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK 0x00000080L |
53265 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF0_MASK 0x00000100L |
53266 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF1_MASK 0x00000200L |
53267 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF2_MASK 0x00000400L |
53268 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF3_MASK 0x00000800L |
53269 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF4_MASK 0x00001000L |
53270 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF5_MASK 0x00002000L |
53271 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF6_MASK 0x00004000L |
53272 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF7_MASK 0x00008000L |
53273 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF0_MASK 0x00010000L |
53274 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF1_MASK 0x00020000L |
53275 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF2_MASK 0x00040000L |
53276 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF3_MASK 0x00080000L |
53277 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF4_MASK 0x00100000L |
53278 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF5_MASK 0x00200000L |
53279 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF6_MASK 0x00400000L |
53280 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF7_MASK 0x00800000L |
53281 | //NBIF_SDP_VWR_VCHG_DIS_CTRL |
53282 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0 |
53283 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1 |
53284 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2 |
53285 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3 |
53286 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4 |
53287 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5 |
53288 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6 |
53289 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7 |
53290 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18 |
53291 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK 0x00000001L |
53292 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK 0x00000002L |
53293 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK 0x00000004L |
53294 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK 0x00000008L |
53295 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK 0x00000010L |
53296 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK 0x00000020L |
53297 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK 0x00000040L |
53298 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK 0x00000080L |
53299 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK 0x01000000L |
53300 | //NBIF_SDP_VWR_VCHG_RST_CTRL0 |
53301 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0 |
53302 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1 |
53303 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2 |
53304 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3 |
53305 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4 |
53306 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5 |
53307 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6 |
53308 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7 |
53309 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18 |
53310 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK 0x00000001L |
53311 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK 0x00000002L |
53312 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK 0x00000004L |
53313 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK 0x00000008L |
53314 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK 0x00000010L |
53315 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK 0x00000020L |
53316 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK 0x00000040L |
53317 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK 0x00000080L |
53318 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK 0x01000000L |
53319 | //NBIF_SDP_VWR_VCHG_RST_CTRL1 |
53320 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0 |
53321 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1 |
53322 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2 |
53323 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3 |
53324 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4 |
53325 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5 |
53326 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6 |
53327 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7 |
53328 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18 |
53329 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK 0x00000001L |
53330 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK 0x00000002L |
53331 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK 0x00000004L |
53332 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK 0x00000008L |
53333 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK 0x00000010L |
53334 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK 0x00000020L |
53335 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK 0x00000040L |
53336 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK 0x00000080L |
53337 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK 0x01000000L |
53338 | //NBIF_SDP_VWR_VCHG_TRIG |
53339 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0 |
53340 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1 |
53341 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2 |
53342 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3 |
53343 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4 |
53344 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5 |
53345 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6 |
53346 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7 |
53347 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18 |
53348 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK 0x00000001L |
53349 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK 0x00000002L |
53350 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK 0x00000004L |
53351 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK 0x00000008L |
53352 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK 0x00000010L |
53353 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK 0x00000020L |
53354 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK 0x00000040L |
53355 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK 0x00000080L |
53356 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK 0x01000000L |
53357 | //NBIF_SHUB_TODET_CTRL |
53358 | #define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN__SHIFT 0x0 |
53359 | #define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT__SHIFT 0x8 |
53360 | #define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT__SHIFT 0x10 |
53361 | #define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN_MASK 0x00000001L |
53362 | #define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT_MASK 0x00000700L |
53363 | #define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT_MASK 0xFFFF0000L |
53364 | //NBIF_SHUB_TODET_CLIENT_CTRL |
53365 | #define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN__SHIFT 0x0 |
53366 | #define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN_MASK 0xFFFFFFFFL |
53367 | //NBIF_SHUB_TODET_CLIENT_STATUS |
53368 | #define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS__SHIFT 0x0 |
53369 | #define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS_MASK 0xFFFFFFFFL |
53370 | //NBIF_SHUB_TODET_SYNCFLOOD_CTRL |
53371 | #define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN__SHIFT 0x0 |
53372 | #define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN_MASK 0xFFFFFFFFL |
53373 | //NBIF_SHUB_TODET_CLIENT_CTRL2 |
53374 | #define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2__SHIFT 0x0 |
53375 | #define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2_MASK 0xFFFFFFFFL |
53376 | //NBIF_SHUB_TODET_CLIENT_STATUS2 |
53377 | #define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2__SHIFT 0x0 |
53378 | #define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2_MASK 0xFFFFFFFFL |
53379 | //NBIF_SHUB_TODET_SYNCFLOOD_CTRL2 |
53380 | #define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2__SHIFT 0x0 |
53381 | #define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2_MASK 0xFFFFFFFFL |
53382 | //BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC |
53383 | #define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 |
53384 | #define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 |
53385 | #define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL |
53386 | #define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L |
53387 | //BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC |
53388 | #define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 |
53389 | #define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 |
53390 | #define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL |
53391 | #define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L |
53392 | //BIFC_GMI_SDP_REQ_POOLCRED_ALLOC |
53393 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 |
53394 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 |
53395 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 |
53396 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc |
53397 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 |
53398 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 |
53399 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 |
53400 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c |
53401 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL |
53402 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L |
53403 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L |
53404 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L |
53405 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L |
53406 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L |
53407 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L |
53408 | #define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L |
53409 | //BIFC_GMI_SDP_DAT_POOLCRED_ALLOC |
53410 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 |
53411 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 |
53412 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 |
53413 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc |
53414 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 |
53415 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 |
53416 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 |
53417 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c |
53418 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL |
53419 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L |
53420 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L |
53421 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L |
53422 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L |
53423 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L |
53424 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L |
53425 | #define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L |
53426 | //BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC |
53427 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 |
53428 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 |
53429 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 |
53430 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc |
53431 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 |
53432 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 |
53433 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 |
53434 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c |
53435 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL |
53436 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L |
53437 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L |
53438 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L |
53439 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L |
53440 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L |
53441 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L |
53442 | #define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L |
53443 | //BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC |
53444 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 |
53445 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 |
53446 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 |
53447 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc |
53448 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 |
53449 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 |
53450 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 |
53451 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c |
53452 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL |
53453 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L |
53454 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L |
53455 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L |
53456 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L |
53457 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L |
53458 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L |
53459 | #define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L |
53460 | //DISCON_HYSTERESIS_HEAD_CTRL |
53461 | #define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x0 |
53462 | #define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x8 |
53463 | #define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H_MASK 0x0000000FL |
53464 | #define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H_MASK 0x00000F00L |
53465 | //BIFC_Z10_CTRL0 |
53466 | #define BIFC_Z10_CTRL0__BIFC_Z10_IDLE_MASK__SHIFT 0x0 |
53467 | #define BIFC_Z10_CTRL0__REGS_Z10_IDLE_ASSERT__SHIFT 0x10 |
53468 | #define BIFC_Z10_CTRL0__REGS_Z10_FENCE_INTF_ACK_EN__SHIFT 0x11 |
53469 | #define BIFC_Z10_CTRL0__REGS_Z10_FENCE_ACK_TIMEOUT_EN__SHIFT 0x12 |
53470 | #define BIFC_Z10_CTRL0__REGS_Z10_FENCE_ACK_ASSERT__SHIFT 0x13 |
53471 | #define BIFC_Z10_CTRL0__Z10_DS_ALLOW_EN_IN_PG__SHIFT 0x1e |
53472 | #define BIFC_Z10_CTRL0__BIFC_Z10_IDLE_MASK_MASK 0x0000FFFFL |
53473 | #define BIFC_Z10_CTRL0__REGS_Z10_IDLE_ASSERT_MASK 0x00010000L |
53474 | #define BIFC_Z10_CTRL0__REGS_Z10_FENCE_INTF_ACK_EN_MASK 0x00020000L |
53475 | #define BIFC_Z10_CTRL0__REGS_Z10_FENCE_ACK_TIMEOUT_EN_MASK 0x00040000L |
53476 | #define BIFC_Z10_CTRL0__REGS_Z10_FENCE_ACK_ASSERT_MASK 0x00080000L |
53477 | #define BIFC_Z10_CTRL0__Z10_DS_ALLOW_EN_IN_PG_MASK 0x40000000L |
53478 | //BIFC_Z10_CTRL1 |
53479 | #define BIFC_Z10_CTRL1__REGS_Z10_FENCE_ACK_TIMEOUT__SHIFT 0x0 |
53480 | #define BIFC_Z10_CTRL1__REGS_Z10_FENCE_ACK_TIMEOUT_MASK 0xFFFFFFFFL |
53481 | //BIFC_Z10_STATUS |
53482 | #define BIFC_Z10_STATUS__REGS_BIFC_Z10_STATUS__SHIFT 0x0 |
53483 | #define BIFC_Z10_STATUS__REGS_BIFC_Z10_STATUS_MASK 0xFFFFFFFFL |
53484 | //BIFC_PCIE_BDF_CNTL0 |
53485 | #define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL0__SHIFT 0x0 |
53486 | #define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL1__SHIFT 0x10 |
53487 | #define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL0_MASK 0x0000FFFFL |
53488 | #define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL1_MASK 0xFFFF0000L |
53489 | //BIFC_PCIE_BDF_CNTL1 |
53490 | #define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL2__SHIFT 0x0 |
53491 | #define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL3__SHIFT 0x10 |
53492 | #define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL2_MASK 0x0000FFFFL |
53493 | #define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL3_MASK 0xFFFF0000L |
53494 | //BIFC_EARLY_WAKEUP_CNTL |
53495 | #define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0 |
53496 | #define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1 |
53497 | #define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2 |
53498 | #define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L |
53499 | #define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L |
53500 | #define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L |
53501 | //BIFC_PERF_CNT_MMIO_RD_H16BIT |
53502 | #define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT__SHIFT 0x0 |
53503 | #define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT_MASK 0x0000FFFFL |
53504 | //BIFC_PERF_CNT_MMIO_WR_H16BIT |
53505 | #define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT__SHIFT 0x0 |
53506 | #define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT_MASK 0x0000FFFFL |
53507 | //BIFC_PERF_CNT_DMA_RD_H16BIT |
53508 | #define BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT__SHIFT 0x0 |
53509 | #define BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT_MASK 0x0000FFFFL |
53510 | //BIFC_PERF_CNT_DMA_WR_H16BIT |
53511 | #define BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT__SHIFT 0x0 |
53512 | #define BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT_MASK 0x0000FFFFL |
53513 | //NBIF_PERF_COM_COUNT_ENABLE |
53514 | #define NBIF_PERF_COM_COUNT_ENABLE__NBIF_COM_COUNT_ENABLE__SHIFT 0x0 |
53515 | #define NBIF_PERF_COM_COUNT_ENABLE__START_COUNT_NOPULS__SHIFT 0x3 |
53516 | #define NBIF_PERF_COM_COUNT_ENABLE__LEGACY_OUT_REALTIME_SEL__SHIFT 0x4 |
53517 | #define NBIF_PERF_COM_COUNT_ENABLE__NBIF_COM_COUNT_ENABLE_MASK 0x00000001L |
53518 | #define NBIF_PERF_COM_COUNT_ENABLE__START_COUNT_NOPULS_MASK 0x00000008L |
53519 | #define NBIF_PERF_COM_COUNT_ENABLE__LEGACY_OUT_REALTIME_SEL_MASK 0x00000010L |
53520 | //NBIF_BX_PERF_CNT_FSM |
53521 | #define NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_COUNT__SHIFT 0x4 |
53522 | #define NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_EN__SHIFT 0x8 |
53523 | #define NBIF_BX_PERF_CNT_FSM__BX_PERF_CNT_DONE__SHIFT 0xa |
53524 | #define NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_COUNT_MASK 0x000000F0L |
53525 | #define NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_EN_MASK 0x00000100L |
53526 | #define NBIF_BX_PERF_CNT_FSM__BX_PERF_CNT_DONE_MASK 0x00000400L |
53527 | //NBIF_COM_COUNT_VALUE |
53528 | #define NBIF_COM_COUNT_VALUE__NBIF_COM_COUNT_VALUE__SHIFT 0x0 |
53529 | #define NBIF_COM_COUNT_VALUE__NBIF_COM_COUNT_VALUE_MASK 0xFFFFFFFFL |
53530 | |
53531 | |
53532 | // addressBlock: nbio_nbif0_nbif_sion_SIONDEC |
53533 | //SION_CL0_RdRsp_BurstTarget_REG0 |
53534 | #define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 |
53535 | #define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
53536 | //SION_CL0_RdRsp_BurstTarget_REG1 |
53537 | #define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 |
53538 | #define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
53539 | //SION_CL0_RdRsp_TimeSlot_REG0 |
53540 | #define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 |
53541 | #define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
53542 | //SION_CL0_RdRsp_TimeSlot_REG1 |
53543 | #define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 |
53544 | #define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
53545 | //SION_CL0_WrRsp_BurstTarget_REG0 |
53546 | #define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 |
53547 | #define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
53548 | //SION_CL0_WrRsp_BurstTarget_REG1 |
53549 | #define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 |
53550 | #define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
53551 | //SION_CL0_WrRsp_TimeSlot_REG0 |
53552 | #define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 |
53553 | #define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
53554 | //SION_CL0_WrRsp_TimeSlot_REG1 |
53555 | #define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 |
53556 | #define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
53557 | //SION_CL0_Req_BurstTarget_REG0 |
53558 | #define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 |
53559 | #define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL |
53560 | //SION_CL0_Req_BurstTarget_REG1 |
53561 | #define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 |
53562 | #define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL |
53563 | //SION_CL0_Req_TimeSlot_REG0 |
53564 | #define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 |
53565 | #define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL |
53566 | //SION_CL0_Req_TimeSlot_REG1 |
53567 | #define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 |
53568 | #define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL |
53569 | //SION_CL0_ReqPoolCredit_Alloc_REG0 |
53570 | #define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 |
53571 | #define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
53572 | //SION_CL0_ReqPoolCredit_Alloc_REG1 |
53573 | #define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 |
53574 | #define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
53575 | //SION_CL0_DataPoolCredit_Alloc_REG0 |
53576 | #define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 |
53577 | #define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
53578 | //SION_CL0_DataPoolCredit_Alloc_REG1 |
53579 | #define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 |
53580 | #define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
53581 | //SION_CL0_RdRspPoolCredit_Alloc_REG0 |
53582 | #define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
53583 | #define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
53584 | //SION_CL0_RdRspPoolCredit_Alloc_REG1 |
53585 | #define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
53586 | #define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
53587 | //SION_CL0_WrRspPoolCredit_Alloc_REG0 |
53588 | #define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
53589 | #define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
53590 | //SION_CL0_WrRspPoolCredit_Alloc_REG1 |
53591 | #define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
53592 | #define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
53593 | //SION_CL1_RdRsp_BurstTarget_REG0 |
53594 | #define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 |
53595 | #define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
53596 | //SION_CL1_RdRsp_BurstTarget_REG1 |
53597 | #define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 |
53598 | #define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
53599 | //SION_CL1_RdRsp_TimeSlot_REG0 |
53600 | #define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 |
53601 | #define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
53602 | //SION_CL1_RdRsp_TimeSlot_REG1 |
53603 | #define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 |
53604 | #define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
53605 | //SION_CL1_WrRsp_BurstTarget_REG0 |
53606 | #define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 |
53607 | #define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
53608 | //SION_CL1_WrRsp_BurstTarget_REG1 |
53609 | #define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 |
53610 | #define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
53611 | //SION_CL1_WrRsp_TimeSlot_REG0 |
53612 | #define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 |
53613 | #define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
53614 | //SION_CL1_WrRsp_TimeSlot_REG1 |
53615 | #define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 |
53616 | #define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
53617 | //SION_CL1_Req_BurstTarget_REG0 |
53618 | #define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 |
53619 | #define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL |
53620 | //SION_CL1_Req_BurstTarget_REG1 |
53621 | #define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 |
53622 | #define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL |
53623 | //SION_CL1_Req_TimeSlot_REG0 |
53624 | #define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 |
53625 | #define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL |
53626 | //SION_CL1_Req_TimeSlot_REG1 |
53627 | #define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 |
53628 | #define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL |
53629 | //SION_CL1_ReqPoolCredit_Alloc_REG0 |
53630 | #define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 |
53631 | #define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
53632 | //SION_CL1_ReqPoolCredit_Alloc_REG1 |
53633 | #define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 |
53634 | #define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
53635 | //SION_CL1_DataPoolCredit_Alloc_REG0 |
53636 | #define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 |
53637 | #define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
53638 | //SION_CL1_DataPoolCredit_Alloc_REG1 |
53639 | #define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 |
53640 | #define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
53641 | //SION_CL1_RdRspPoolCredit_Alloc_REG0 |
53642 | #define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
53643 | #define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
53644 | //SION_CL1_RdRspPoolCredit_Alloc_REG1 |
53645 | #define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
53646 | #define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
53647 | //SION_CL1_WrRspPoolCredit_Alloc_REG0 |
53648 | #define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
53649 | #define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
53650 | //SION_CL1_WrRspPoolCredit_Alloc_REG1 |
53651 | #define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
53652 | #define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
53653 | //SION_CL2_RdRsp_BurstTarget_REG0 |
53654 | #define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 |
53655 | #define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
53656 | //SION_CL2_RdRsp_BurstTarget_REG1 |
53657 | #define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 |
53658 | #define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
53659 | //SION_CL2_RdRsp_TimeSlot_REG0 |
53660 | #define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 |
53661 | #define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
53662 | //SION_CL2_RdRsp_TimeSlot_REG1 |
53663 | #define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 |
53664 | #define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
53665 | //SION_CL2_WrRsp_BurstTarget_REG0 |
53666 | #define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 |
53667 | #define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
53668 | //SION_CL2_WrRsp_BurstTarget_REG1 |
53669 | #define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 |
53670 | #define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
53671 | //SION_CL2_WrRsp_TimeSlot_REG0 |
53672 | #define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 |
53673 | #define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
53674 | //SION_CL2_WrRsp_TimeSlot_REG1 |
53675 | #define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 |
53676 | #define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
53677 | //SION_CL2_Req_BurstTarget_REG0 |
53678 | #define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 |
53679 | #define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL |
53680 | //SION_CL2_Req_BurstTarget_REG1 |
53681 | #define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 |
53682 | #define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL |
53683 | //SION_CL2_Req_TimeSlot_REG0 |
53684 | #define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 |
53685 | #define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL |
53686 | //SION_CL2_Req_TimeSlot_REG1 |
53687 | #define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 |
53688 | #define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL |
53689 | //SION_CL2_ReqPoolCredit_Alloc_REG0 |
53690 | #define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 |
53691 | #define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
53692 | //SION_CL2_ReqPoolCredit_Alloc_REG1 |
53693 | #define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 |
53694 | #define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
53695 | //SION_CL2_DataPoolCredit_Alloc_REG0 |
53696 | #define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 |
53697 | #define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
53698 | //SION_CL2_DataPoolCredit_Alloc_REG1 |
53699 | #define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 |
53700 | #define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
53701 | //SION_CL2_RdRspPoolCredit_Alloc_REG0 |
53702 | #define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
53703 | #define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
53704 | //SION_CL2_RdRspPoolCredit_Alloc_REG1 |
53705 | #define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
53706 | #define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
53707 | //SION_CL2_WrRspPoolCredit_Alloc_REG0 |
53708 | #define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
53709 | #define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
53710 | //SION_CL2_WrRspPoolCredit_Alloc_REG1 |
53711 | #define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
53712 | #define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
53713 | //SION_CNTL_REG0 |
53714 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 |
53715 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 |
53716 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 |
53717 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 |
53718 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 |
53719 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 |
53720 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 |
53721 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 |
53722 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 |
53723 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 |
53724 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa |
53725 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb |
53726 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc |
53727 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd |
53728 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe |
53729 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf |
53730 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10 |
53731 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11 |
53732 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12 |
53733 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13 |
53734 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L |
53735 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L |
53736 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L |
53737 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L |
53738 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L |
53739 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L |
53740 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L |
53741 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L |
53742 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L |
53743 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L |
53744 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L |
53745 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L |
53746 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L |
53747 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L |
53748 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L |
53749 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L |
53750 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L |
53751 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L |
53752 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L |
53753 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L |
53754 | //SION_CNTL_REG1 |
53755 | #define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0 |
53756 | #define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT 0x8 |
53757 | #define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL |
53758 | #define SION_CNTL_REG1__CG_OFF_HYSTERESIS_MASK 0x0000FF00L |
53759 | |
53760 | |
53761 | // addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk |
53762 | //BIFL_RAS_CENTRAL_CNTL |
53763 | #define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS__SHIFT 0x1d |
53764 | #define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS__SHIFT 0x1e |
53765 | #define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS__SHIFT 0x1f |
53766 | #define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS_MASK 0x20000000L |
53767 | #define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS_MASK 0x40000000L |
53768 | #define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS_MASK 0x80000000L |
53769 | //BIFL_RAS_CENTRAL_STATUS |
53770 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det__SHIFT 0x0 |
53771 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det__SHIFT 0x1 |
53772 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det__SHIFT 0x2 |
53773 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det__SHIFT 0x3 |
53774 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv__SHIFT 0x1d |
53775 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv__SHIFT 0x1e |
53776 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv__SHIFT 0x1f |
53777 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det_MASK 0x00000001L |
53778 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det_MASK 0x00000002L |
53779 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det_MASK 0x00000004L |
53780 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det_MASK 0x00000008L |
53781 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv_MASK 0x20000000L |
53782 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv_MASK 0x40000000L |
53783 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv_MASK 0x80000000L |
53784 | //BIFL_RAS_LEAF0_CTRL |
53785 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 |
53786 | #define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
53787 | #define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 |
53788 | #define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 |
53789 | #define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x4 |
53790 | #define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 |
53791 | #define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 |
53792 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 |
53793 | #define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 |
53794 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa |
53795 | #define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb |
53796 | #define BIFL_RAS_LEAF0_CTRL__POISON_DBUG_EN__SHIFT 0xc |
53797 | #define BIFL_RAS_LEAF0_CTRL__PARITY_DBUG_EN__SHIFT 0xd |
53798 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 |
53799 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L |
53800 | #define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
53801 | #define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L |
53802 | #define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L |
53803 | #define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000010L |
53804 | #define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L |
53805 | #define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L |
53806 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L |
53807 | #define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L |
53808 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L |
53809 | #define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L |
53810 | #define BIFL_RAS_LEAF0_CTRL__POISON_DBUG_EN_MASK 0x00001000L |
53811 | #define BIFL_RAS_LEAF0_CTRL__PARITY_DBUG_EN_MASK 0x00002000L |
53812 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L |
53813 | //BIFL_RAS_LEAF1_CTRL |
53814 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 |
53815 | #define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
53816 | #define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 |
53817 | #define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 |
53818 | #define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x4 |
53819 | #define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 |
53820 | #define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 |
53821 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 |
53822 | #define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 |
53823 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa |
53824 | #define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb |
53825 | #define BIFL_RAS_LEAF1_CTRL__POISON_DBUG_EN__SHIFT 0xc |
53826 | #define BIFL_RAS_LEAF1_CTRL__PARITY_DBUG_EN__SHIFT 0xd |
53827 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 |
53828 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L |
53829 | #define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
53830 | #define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L |
53831 | #define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L |
53832 | #define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000010L |
53833 | #define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L |
53834 | #define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L |
53835 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L |
53836 | #define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L |
53837 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L |
53838 | #define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L |
53839 | #define BIFL_RAS_LEAF1_CTRL__POISON_DBUG_EN_MASK 0x00001000L |
53840 | #define BIFL_RAS_LEAF1_CTRL__PARITY_DBUG_EN_MASK 0x00002000L |
53841 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L |
53842 | //BIFL_RAS_LEAF2_CTRL |
53843 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 |
53844 | #define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
53845 | #define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 |
53846 | #define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 |
53847 | #define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x4 |
53848 | #define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 |
53849 | #define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 |
53850 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 |
53851 | #define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 |
53852 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa |
53853 | #define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb |
53854 | #define BIFL_RAS_LEAF2_CTRL__POISON_DBUG_EN__SHIFT 0xc |
53855 | #define BIFL_RAS_LEAF2_CTRL__PARITY_DBUG_EN__SHIFT 0xd |
53856 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 |
53857 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L |
53858 | #define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
53859 | #define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L |
53860 | #define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L |
53861 | #define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000010L |
53862 | #define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L |
53863 | #define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L |
53864 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L |
53865 | #define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L |
53866 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L |
53867 | #define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L |
53868 | #define BIFL_RAS_LEAF2_CTRL__POISON_DBUG_EN_MASK 0x00001000L |
53869 | #define BIFL_RAS_LEAF2_CTRL__PARITY_DBUG_EN_MASK 0x00002000L |
53870 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L |
53871 | //BIFL_RAS_LEAF0_STATUS |
53872 | #define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV__SHIFT 0x0 |
53873 | #define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET__SHIFT 0x1 |
53874 | #define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET__SHIFT 0x2 |
53875 | #define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 |
53876 | #define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 |
53877 | #define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa |
53878 | #define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb |
53879 | #define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV_MASK 0x00000001L |
53880 | #define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET_MASK 0x00000002L |
53881 | #define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET_MASK 0x00000004L |
53882 | #define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L |
53883 | #define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L |
53884 | #define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L |
53885 | #define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L |
53886 | //BIFL_RAS_LEAF1_STATUS |
53887 | #define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV__SHIFT 0x0 |
53888 | #define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET__SHIFT 0x1 |
53889 | #define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET__SHIFT 0x2 |
53890 | #define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 |
53891 | #define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 |
53892 | #define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa |
53893 | #define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb |
53894 | #define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV_MASK 0x00000001L |
53895 | #define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET_MASK 0x00000002L |
53896 | #define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET_MASK 0x00000004L |
53897 | #define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L |
53898 | #define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L |
53899 | #define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L |
53900 | #define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L |
53901 | //BIFL_RAS_LEAF2_STATUS |
53902 | #define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV__SHIFT 0x0 |
53903 | #define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET__SHIFT 0x1 |
53904 | #define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET__SHIFT 0x2 |
53905 | #define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 |
53906 | #define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 |
53907 | #define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa |
53908 | #define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb |
53909 | #define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV_MASK 0x00000001L |
53910 | #define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET_MASK 0x00000002L |
53911 | #define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET_MASK 0x00000004L |
53912 | #define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L |
53913 | #define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L |
53914 | #define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L |
53915 | #define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L |
53916 | //BIFL_IOHUB_RAS_IH_CNTL |
53917 | #define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN__SHIFT 0x0 |
53918 | #define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN_MASK 0x00000001L |
53919 | //BIFL_RAS_VWR_FROM_IOHUB |
53920 | #define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG__SHIFT 0x0 |
53921 | #define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG_MASK 0x00000001L |
53922 | |
53923 | |
53924 | // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 |
53925 | //RCC_DWN_DEV0_1_DN_PCIE_RESERVED |
53926 | #define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
53927 | #define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL |
53928 | //RCC_DWN_DEV0_1_DN_PCIE_SCRATCH |
53929 | #define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
53930 | #define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
53931 | //RCC_DWN_DEV0_1_DN_PCIE_CNTL |
53932 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
53933 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 |
53934 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
53935 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
53936 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L |
53937 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
53938 | //RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL |
53939 | #define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
53940 | #define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
53941 | //RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 |
53942 | #define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
53943 | #define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
53944 | //RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL |
53945 | #define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
53946 | #define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 |
53947 | #define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
53948 | #define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L |
53949 | //RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL |
53950 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
53951 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
53952 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
53953 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
53954 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 |
53955 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
53956 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
53957 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
53958 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
53959 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L |
53960 | |
53961 | |
53962 | // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 |
53963 | //RCC_DWNP_DEV0_1_PCIE_ERR_CNTL |
53964 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
53965 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
53966 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 |
53967 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 |
53968 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 |
53969 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
53970 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
53971 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L |
53972 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L |
53973 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L |
53974 | //RCC_DWNP_DEV0_1_PCIE_RX_CNTL |
53975 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
53976 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 |
53977 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
53978 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 |
53979 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
53980 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
53981 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L |
53982 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
53983 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L |
53984 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
53985 | //RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL |
53986 | //RCC_DWNP_DEV0_1_PCIE_LC_CNTL2 |
53987 | #define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 |
53988 | #define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
53989 | #define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L |
53990 | #define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
53991 | //RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP |
53992 | #define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 |
53993 | #define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL |
53994 | |
53995 | |
53996 | // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 |
53997 | //RCC_EP_DEV0_1_EP_PCIE_SCRATCH |
53998 | #define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
53999 | #define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
54000 | //RCC_EP_DEV0_1_EP_PCIE_CNTL |
54001 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
54002 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
54003 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
54004 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
54005 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
54006 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
54007 | //RCC_EP_DEV0_1_EP_PCIE_INT_CNTL |
54008 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 |
54009 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 |
54010 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 |
54011 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 |
54012 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 |
54013 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 |
54014 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L |
54015 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L |
54016 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L |
54017 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L |
54018 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L |
54019 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L |
54020 | //RCC_EP_DEV0_1_EP_PCIE_INT_STATUS |
54021 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 |
54022 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 |
54023 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 |
54024 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 |
54025 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 |
54026 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 |
54027 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 |
54028 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L |
54029 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L |
54030 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L |
54031 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L |
54032 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L |
54033 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L |
54034 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L |
54035 | //RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 |
54036 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
54037 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
54038 | //RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL |
54039 | #define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
54040 | #define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
54041 | //RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL |
54042 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
54043 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
54044 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
54045 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
54046 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 |
54047 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
54048 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
54049 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
54050 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
54051 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L |
54052 | //RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL |
54053 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 |
54054 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 |
54055 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 |
54056 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 |
54057 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa |
54058 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd |
54059 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe |
54060 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf |
54061 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 |
54062 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 |
54063 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L |
54064 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L |
54065 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L |
54066 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L |
54067 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L |
54068 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L |
54069 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L |
54070 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L |
54071 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L |
54072 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L |
54073 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 |
54074 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54075 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54076 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 |
54077 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54078 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54079 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 |
54080 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54081 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54082 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 |
54083 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54084 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54085 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 |
54086 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54087 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54088 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 |
54089 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54090 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54091 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 |
54092 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54093 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54094 | //RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 |
54095 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54096 | #define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54097 | //RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP |
54098 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
54099 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
54100 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
54101 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
54102 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
54103 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
54104 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
54105 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
54106 | //RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR |
54107 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
54108 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
54109 | //RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL |
54110 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 |
54111 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 |
54112 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL |
54113 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L |
54114 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 |
54115 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54116 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54117 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 |
54118 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54119 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54120 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 |
54121 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54122 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54123 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 |
54124 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54125 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54126 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 |
54127 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54128 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54129 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 |
54130 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54131 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54132 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 |
54133 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54134 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54135 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 |
54136 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
54137 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
54138 | //RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL |
54139 | #define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 |
54140 | #define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL |
54141 | //RCC_EP_DEV0_1_EP_PCIEP_RESERVED |
54142 | #define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
54143 | #define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
54144 | //RCC_EP_DEV0_1_EP_PCIE_TX_CNTL |
54145 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
54146 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
54147 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 |
54148 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 |
54149 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a |
54150 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
54151 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
54152 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L |
54153 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L |
54154 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L |
54155 | //RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID |
54156 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
54157 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
54158 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
54159 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
54160 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
54161 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
54162 | //RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL |
54163 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
54164 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
54165 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
54166 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
54167 | //RCC_EP_DEV0_1_EP_PCIE_RX_CNTL |
54168 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
54169 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
54170 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
54171 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
54172 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
54173 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
54174 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
54175 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
54176 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
54177 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
54178 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
54179 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
54180 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
54181 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
54182 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
54183 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
54184 | //RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL |
54185 | |
54186 | |
54187 | // addressBlock: nbio_nbif0_bif_bx_SYSDEC |
54188 | //BIF_BX0_PCIE_INDEX |
54189 | #define BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 |
54190 | #define BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL |
54191 | //BIF_BX0_PCIE_DATA |
54192 | #define BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT 0x0 |
54193 | #define BIF_BX0_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL |
54194 | //BIF_BX0_PCIE_INDEX2 |
54195 | #define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 |
54196 | #define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL |
54197 | //BIF_BX0_PCIE_DATA2 |
54198 | #define BIF_BX0_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 |
54199 | #define BIF_BX0_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL |
54200 | //BIF_BX0_SBIOS_SCRATCH_0 |
54201 | #define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0 |
54202 | #define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
54203 | //BIF_BX0_SBIOS_SCRATCH_1 |
54204 | #define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0 |
54205 | #define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
54206 | //BIF_BX0_SBIOS_SCRATCH_2 |
54207 | #define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0 |
54208 | #define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
54209 | //BIF_BX0_SBIOS_SCRATCH_3 |
54210 | #define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0 |
54211 | #define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
54212 | //BIF_BX0_BIOS_SCRATCH_0 |
54213 | #define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 |
54214 | #define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL |
54215 | //BIF_BX0_BIOS_SCRATCH_1 |
54216 | #define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 |
54217 | #define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL |
54218 | //BIF_BX0_BIOS_SCRATCH_2 |
54219 | #define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 |
54220 | #define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL |
54221 | //BIF_BX0_BIOS_SCRATCH_3 |
54222 | #define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 |
54223 | #define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL |
54224 | //BIF_BX0_BIOS_SCRATCH_4 |
54225 | #define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 |
54226 | #define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL |
54227 | //BIF_BX0_BIOS_SCRATCH_5 |
54228 | #define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 |
54229 | #define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL |
54230 | //BIF_BX0_BIOS_SCRATCH_6 |
54231 | #define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 |
54232 | #define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL |
54233 | //BIF_BX0_BIOS_SCRATCH_7 |
54234 | #define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 |
54235 | #define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL |
54236 | //BIF_BX0_BIOS_SCRATCH_8 |
54237 | #define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 |
54238 | #define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL |
54239 | //BIF_BX0_BIOS_SCRATCH_9 |
54240 | #define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 |
54241 | #define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL |
54242 | //BIF_BX0_BIOS_SCRATCH_10 |
54243 | #define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 |
54244 | #define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL |
54245 | //BIF_BX0_BIOS_SCRATCH_11 |
54246 | #define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 |
54247 | #define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL |
54248 | //BIF_BX0_BIOS_SCRATCH_12 |
54249 | #define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 |
54250 | #define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL |
54251 | //BIF_BX0_BIOS_SCRATCH_13 |
54252 | #define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 |
54253 | #define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL |
54254 | //BIF_BX0_BIOS_SCRATCH_14 |
54255 | #define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 |
54256 | #define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL |
54257 | //BIF_BX0_BIOS_SCRATCH_15 |
54258 | #define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 |
54259 | #define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL |
54260 | //BIF_BX0_BIF_RLC_INTR_CNTL |
54261 | #define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0 |
54262 | #define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1 |
54263 | #define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2 |
54264 | #define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3 |
54265 | #define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L |
54266 | #define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L |
54267 | #define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L |
54268 | #define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L |
54269 | //BIF_BX0_BIF_VCE_INTR_CNTL |
54270 | #define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0 |
54271 | #define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1 |
54272 | #define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2 |
54273 | #define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3 |
54274 | #define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L |
54275 | #define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L |
54276 | #define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L |
54277 | #define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L |
54278 | //BIF_BX0_BIF_UVD_INTR_CNTL |
54279 | #define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0 |
54280 | #define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1 |
54281 | #define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2 |
54282 | #define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3 |
54283 | #define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_INST_SEL__SHIFT 0x1c |
54284 | #define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L |
54285 | #define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L |
54286 | #define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L |
54287 | #define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L |
54288 | #define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_INST_SEL_MASK 0xF0000000L |
54289 | //BIF_BX0_GFX_MMIOREG_CAM_ADDR0 |
54290 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 |
54291 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL |
54292 | //BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 |
54293 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 |
54294 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL |
54295 | //BIF_BX0_GFX_MMIOREG_CAM_ADDR1 |
54296 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 |
54297 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL |
54298 | //BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 |
54299 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 |
54300 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL |
54301 | //BIF_BX0_GFX_MMIOREG_CAM_ADDR2 |
54302 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 |
54303 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL |
54304 | //BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 |
54305 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 |
54306 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL |
54307 | //BIF_BX0_GFX_MMIOREG_CAM_ADDR3 |
54308 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 |
54309 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL |
54310 | //BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 |
54311 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 |
54312 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL |
54313 | //BIF_BX0_GFX_MMIOREG_CAM_ADDR4 |
54314 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 |
54315 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL |
54316 | //BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 |
54317 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 |
54318 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL |
54319 | //BIF_BX0_GFX_MMIOREG_CAM_ADDR5 |
54320 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 |
54321 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL |
54322 | //BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 |
54323 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 |
54324 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL |
54325 | //BIF_BX0_GFX_MMIOREG_CAM_ADDR6 |
54326 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 |
54327 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL |
54328 | //BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 |
54329 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 |
54330 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL |
54331 | //BIF_BX0_GFX_MMIOREG_CAM_ADDR7 |
54332 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 |
54333 | #define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL |
54334 | //BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 |
54335 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 |
54336 | #define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL |
54337 | //BIF_BX0_GFX_MMIOREG_CAM_CNTL |
54338 | #define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 |
54339 | #define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL |
54340 | //BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL |
54341 | #define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 |
54342 | #define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL |
54343 | //BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL |
54344 | #define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 |
54345 | #define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL |
54346 | //BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL |
54347 | #define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 |
54348 | #define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL |
54349 | |
54350 | |
54351 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC |
54352 | //BIF_BX_PF0_MM_INDEX |
54353 | #define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
54354 | #define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT 0x1f |
54355 | #define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
54356 | #define BIF_BX_PF0_MM_INDEX__MM_APER_MASK 0x80000000L |
54357 | //BIF_BX_PF0_MM_DATA |
54358 | #define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT 0x0 |
54359 | #define BIF_BX_PF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
54360 | //BIF_BX_PF0_MM_INDEX_HI |
54361 | #define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
54362 | #define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
54363 | //BIF_BX_PF0_RSMU_INDEX |
54364 | #define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX__SHIFT 0x0 |
54365 | #define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX_MASK 0xFFFFFFFFL |
54366 | //BIF_BX_PF0_RSMU_DATA |
54367 | #define BIF_BX_PF0_RSMU_DATA__RSMU_DATA__SHIFT 0x0 |
54368 | #define BIF_BX_PF0_RSMU_DATA__RSMU_DATA_MASK 0xFFFFFFFFL |
54369 | |
54370 | |
54371 | // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 |
54372 | //BIF_BX0_BIF_MM_INDACCESS_CNTL |
54373 | #define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 |
54374 | #define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L |
54375 | //BIF_BX0_BUS_CNTL |
54376 | #define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 |
54377 | #define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 |
54378 | #define BIF_BX0_BUS_CNTL__SET_AZ_TC__SHIFT 0xa |
54379 | #define BIF_BX0_BUS_CNTL__SET_MC_TC__SHIFT 0xd |
54380 | #define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 |
54381 | #define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 |
54382 | #define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 |
54383 | #define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18 |
54384 | #define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 |
54385 | #define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a |
54386 | #define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b |
54387 | #define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c |
54388 | #define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d |
54389 | #define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e |
54390 | #define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f |
54391 | #define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L |
54392 | #define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L |
54393 | #define BIF_BX0_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L |
54394 | #define BIF_BX0_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L |
54395 | #define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L |
54396 | #define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L |
54397 | #define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L |
54398 | #define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L |
54399 | #define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L |
54400 | #define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L |
54401 | #define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L |
54402 | #define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L |
54403 | #define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L |
54404 | #define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L |
54405 | #define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L |
54406 | //BIF_BX0_BIF_SCRATCH0 |
54407 | #define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 |
54408 | #define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL |
54409 | //BIF_BX0_BIF_SCRATCH1 |
54410 | #define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 |
54411 | #define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL |
54412 | //BIF_BX0_BX_RESET_EN |
54413 | #define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 |
54414 | #define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L |
54415 | //BIF_BX0_MM_CFGREGS_CNTL |
54416 | #define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 |
54417 | #define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 |
54418 | #define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f |
54419 | #define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L |
54420 | #define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L |
54421 | #define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L |
54422 | //BIF_BX0_BX_RESET_CNTL |
54423 | #define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 |
54424 | #define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L |
54425 | //BIF_BX0_INTERRUPT_CNTL |
54426 | #define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 |
54427 | #define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 |
54428 | #define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 |
54429 | #define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 |
54430 | #define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 |
54431 | #define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf |
54432 | #define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 |
54433 | #define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 |
54434 | #define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12 |
54435 | #define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L |
54436 | #define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L |
54437 | #define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L |
54438 | #define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L |
54439 | #define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L |
54440 | #define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L |
54441 | #define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L |
54442 | #define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L |
54443 | #define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L |
54444 | //BIF_BX0_INTERRUPT_CNTL2 |
54445 | #define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 |
54446 | #define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL |
54447 | //BIF_BX0_CLKREQB_PAD_CNTL |
54448 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 |
54449 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 |
54450 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 |
54451 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 |
54452 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 |
54453 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 |
54454 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 |
54455 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 |
54456 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 |
54457 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa |
54458 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb |
54459 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc |
54460 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd |
54461 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L |
54462 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L |
54463 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L |
54464 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L |
54465 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L |
54466 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L |
54467 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L |
54468 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L |
54469 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L |
54470 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L |
54471 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L |
54472 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L |
54473 | #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L |
54474 | //BIF_BX0_BIF_FEATURES_CONTROL_MISC |
54475 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 |
54476 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 |
54477 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 |
54478 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 |
54479 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb |
54480 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc |
54481 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd |
54482 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf |
54483 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10 |
54484 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18 |
54485 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L |
54486 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L |
54487 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L |
54488 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L |
54489 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L |
54490 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L |
54491 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L |
54492 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L |
54493 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x00FF0000L |
54494 | #define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L |
54495 | //BIF_BX0_HDP_ATOMIC_CONTROL_MISC |
54496 | #define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0 |
54497 | #define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL |
54498 | //BIF_BX0_BIF_DOORBELL_CNTL |
54499 | #define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 |
54500 | #define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 |
54501 | #define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 |
54502 | #define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 |
54503 | #define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 |
54504 | #define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 |
54505 | #define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 |
54506 | #define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a |
54507 | #define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b |
54508 | #define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L |
54509 | #define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L |
54510 | #define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L |
54511 | #define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L |
54512 | #define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L |
54513 | #define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L |
54514 | #define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L |
54515 | #define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L |
54516 | #define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L |
54517 | //BIF_BX0_BIF_DOORBELL_INT_CNTL |
54518 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 |
54519 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 |
54520 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 |
54521 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 |
54522 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 |
54523 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 |
54524 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 |
54525 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19 |
54526 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a |
54527 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c |
54528 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d |
54529 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e |
54530 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f |
54531 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L |
54532 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L |
54533 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L |
54534 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L |
54535 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L |
54536 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L |
54537 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L |
54538 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L |
54539 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L |
54540 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L |
54541 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L |
54542 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L |
54543 | #define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L |
54544 | //BIF_BX0_BIF_FB_EN |
54545 | #define BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 |
54546 | #define BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 |
54547 | #define BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L |
54548 | #define BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L |
54549 | //BIF_BX0_BIF_INTR_CNTL |
54550 | #define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 |
54551 | #define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L |
54552 | //BIF_BX0_BIF_MST_TRANS_PENDING_VF |
54553 | #define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
54554 | #define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL |
54555 | //BIF_BX0_BIF_SLV_TRANS_PENDING_VF |
54556 | #define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 |
54557 | #define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL |
54558 | //BIF_BX0_BACO_CNTL |
54559 | #define BIF_BX0_BACO_CNTL__BACO_EN__SHIFT 0x0 |
54560 | #define BIF_BX0_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1 |
54561 | #define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 |
54562 | #define BIF_BX0_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 |
54563 | #define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 |
54564 | #define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 |
54565 | #define BIF_BX0_BACO_CNTL__BACO_MODE__SHIFT 0x8 |
54566 | #define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 |
54567 | #define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f |
54568 | #define BIF_BX0_BACO_CNTL__BACO_EN_MASK 0x00000001L |
54569 | #define BIF_BX0_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L |
54570 | #define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L |
54571 | #define BIF_BX0_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L |
54572 | #define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L |
54573 | #define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L |
54574 | #define BIF_BX0_BACO_CNTL__BACO_MODE_MASK 0x00000100L |
54575 | #define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L |
54576 | #define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L |
54577 | //BIF_BX0_BIF_BACO_EXIT_TIME0 |
54578 | #define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 |
54579 | #define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL |
54580 | //BIF_BX0_BIF_BACO_EXIT_TIMER1 |
54581 | #define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 |
54582 | #define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 |
54583 | #define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a |
54584 | #define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b |
54585 | #define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c |
54586 | #define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d |
54587 | #define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f |
54588 | #define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL |
54589 | #define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L |
54590 | #define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L |
54591 | #define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L |
54592 | #define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L |
54593 | #define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L |
54594 | #define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L |
54595 | //BIF_BX0_BIF_BACO_EXIT_TIMER2 |
54596 | #define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 |
54597 | #define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL |
54598 | //BIF_BX0_BIF_BACO_EXIT_TIMER3 |
54599 | #define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 |
54600 | #define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL |
54601 | //BIF_BX0_BIF_BACO_EXIT_TIMER4 |
54602 | #define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 |
54603 | #define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL |
54604 | //BIF_BX0_MEM_TYPE_CNTL |
54605 | #define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 |
54606 | #define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L |
54607 | //BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL |
54608 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0 |
54609 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1 |
54610 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8 |
54611 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L |
54612 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L |
54613 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L |
54614 | //BIF_BX0_NBIF_GFX_ADDR_LUT_0 |
54615 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0 |
54616 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL |
54617 | //BIF_BX0_NBIF_GFX_ADDR_LUT_1 |
54618 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0 |
54619 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL |
54620 | //BIF_BX0_NBIF_GFX_ADDR_LUT_2 |
54621 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0 |
54622 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL |
54623 | //BIF_BX0_NBIF_GFX_ADDR_LUT_3 |
54624 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0 |
54625 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL |
54626 | //BIF_BX0_NBIF_GFX_ADDR_LUT_4 |
54627 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0 |
54628 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL |
54629 | //BIF_BX0_NBIF_GFX_ADDR_LUT_5 |
54630 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0 |
54631 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL |
54632 | //BIF_BX0_NBIF_GFX_ADDR_LUT_6 |
54633 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0 |
54634 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL |
54635 | //BIF_BX0_NBIF_GFX_ADDR_LUT_7 |
54636 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0 |
54637 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL |
54638 | //BIF_BX0_NBIF_GFX_ADDR_LUT_8 |
54639 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0 |
54640 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL |
54641 | //BIF_BX0_NBIF_GFX_ADDR_LUT_9 |
54642 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0 |
54643 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL |
54644 | //BIF_BX0_NBIF_GFX_ADDR_LUT_10 |
54645 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0 |
54646 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL |
54647 | //BIF_BX0_NBIF_GFX_ADDR_LUT_11 |
54648 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0 |
54649 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL |
54650 | //BIF_BX0_NBIF_GFX_ADDR_LUT_12 |
54651 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0 |
54652 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL |
54653 | //BIF_BX0_NBIF_GFX_ADDR_LUT_13 |
54654 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0 |
54655 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL |
54656 | //BIF_BX0_NBIF_GFX_ADDR_LUT_14 |
54657 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0 |
54658 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL |
54659 | //BIF_BX0_NBIF_GFX_ADDR_LUT_15 |
54660 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0 |
54661 | #define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL |
54662 | //BIF_BX0_GFX_RST_CNTL |
54663 | #define BIF_BX0_GFX_RST_CNTL__GFX_RST_FINISH_INDICATION__SHIFT 0x0 |
54664 | #define BIF_BX0_GFX_RST_CNTL__GFX_RST_FINISH_INDICATION_MASK 0x00000001L |
54665 | //BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL |
54666 | #define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
54667 | #define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL |
54668 | //BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL |
54669 | #define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
54670 | #define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL |
54671 | //BIF_BX0_BIF_RB_CNTL |
54672 | #define BIF_BX0_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
54673 | #define BIF_BX0_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 |
54674 | #define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 |
54675 | #define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 |
54676 | #define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 |
54677 | #define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a |
54678 | #define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d |
54679 | #define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e |
54680 | #define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f |
54681 | #define BIF_BX0_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
54682 | #define BIF_BX0_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
54683 | #define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L |
54684 | #define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L |
54685 | #define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L |
54686 | #define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L |
54687 | #define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L |
54688 | #define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L |
54689 | #define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L |
54690 | //BIF_BX0_BIF_RB_BASE |
54691 | #define BIF_BX0_BIF_RB_BASE__ADDR__SHIFT 0x0 |
54692 | #define BIF_BX0_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
54693 | //BIF_BX0_BIF_RB_RPTR |
54694 | #define BIF_BX0_BIF_RB_RPTR__OFFSET__SHIFT 0x2 |
54695 | #define BIF_BX0_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL |
54696 | //BIF_BX0_BIF_RB_WPTR |
54697 | #define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 |
54698 | #define BIF_BX0_BIF_RB_WPTR__OFFSET__SHIFT 0x2 |
54699 | #define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L |
54700 | #define BIF_BX0_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL |
54701 | //BIF_BX0_BIF_RB_WPTR_ADDR_HI |
54702 | #define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 |
54703 | #define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL |
54704 | //BIF_BX0_BIF_RB_WPTR_ADDR_LO |
54705 | #define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 |
54706 | #define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
54707 | //BIF_BX0_MAILBOX_INDEX |
54708 | #define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 |
54709 | #define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL |
54710 | //BIF_BX0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE |
54711 | #define BIF_BX0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 |
54712 | #define BIF_BX0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL |
54713 | //BIF_BX0_BIF_PERSTB_PAD_CNTL |
54714 | #define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 |
54715 | #define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL |
54716 | //BIF_BX0_BIF_PX_EN_PAD_CNTL |
54717 | #define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 |
54718 | #define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL |
54719 | //BIF_BX0_BIF_REFPADKIN_PAD_CNTL |
54720 | #define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 |
54721 | #define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL |
54722 | //BIF_BX0_BIF_CLKREQB_PAD_CNTL |
54723 | #define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 |
54724 | #define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL |
54725 | //BIF_BX0_BIF_PWRBRK_PAD_CNTL |
54726 | #define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0 |
54727 | #define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL |
54728 | |
54729 | |
54730 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 |
54731 | //BIF_BX_PF0_BIF_BME_STATUS |
54732 | #define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
54733 | #define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
54734 | #define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
54735 | #define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
54736 | //BIF_BX_PF0_BIF_ATOMIC_ERR_LOG |
54737 | //BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
54738 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
54739 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
54740 | //BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
54741 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
54742 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
54743 | //BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL |
54744 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
54745 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
54746 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
54747 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
54748 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
54749 | #define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
54750 | //BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL |
54751 | #define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
54752 | #define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
54753 | //BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL |
54754 | #define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
54755 | #define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
54756 | //BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL |
54757 | #define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 |
54758 | #define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L |
54759 | //BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL |
54760 | #define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 |
54761 | #define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L |
54762 | //BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ |
54763 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP0__SHIFT 0x0 |
54764 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP1__SHIFT 0x1 |
54765 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP2__SHIFT 0x2 |
54766 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP3__SHIFT 0x3 |
54767 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP4__SHIFT 0x4 |
54768 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP5__SHIFT 0x5 |
54769 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP6__SHIFT 0x6 |
54770 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP7__SHIFT 0x7 |
54771 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP8__SHIFT 0x8 |
54772 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP9__SHIFT 0x9 |
54773 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA0__SHIFT 0xa |
54774 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA1__SHIFT 0xb |
54775 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0__SHIFT 0xc |
54776 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1__SHIFT 0xd |
54777 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2__SHIFT 0xe |
54778 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3__SHIFT 0xf |
54779 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4__SHIFT 0x10 |
54780 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5__SHIFT 0x11 |
54781 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6__SHIFT 0x12 |
54782 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7__SHIFT 0x13 |
54783 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8__SHIFT 0x14 |
54784 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9__SHIFT 0x15 |
54785 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10__SHIFT 0x16 |
54786 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11__SHIFT 0x17 |
54787 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12__SHIFT 0x18 |
54788 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13__SHIFT 0x19 |
54789 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14__SHIFT 0x1a |
54790 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15__SHIFT 0x1b |
54791 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16__SHIFT 0x1c |
54792 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17__SHIFT 0x1d |
54793 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18__SHIFT 0x1e |
54794 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19__SHIFT 0x1f |
54795 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP0_MASK 0x00000001L |
54796 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP1_MASK 0x00000002L |
54797 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP2_MASK 0x00000004L |
54798 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP3_MASK 0x00000008L |
54799 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP4_MASK 0x00000010L |
54800 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP5_MASK 0x00000020L |
54801 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP6_MASK 0x00000040L |
54802 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP7_MASK 0x00000080L |
54803 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP8_MASK 0x00000100L |
54804 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP9_MASK 0x00000200L |
54805 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA0_MASK 0x00000400L |
54806 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA1_MASK 0x00000800L |
54807 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0_MASK 0x00001000L |
54808 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1_MASK 0x00002000L |
54809 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2_MASK 0x00004000L |
54810 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3_MASK 0x00008000L |
54811 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4_MASK 0x00010000L |
54812 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5_MASK 0x00020000L |
54813 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6_MASK 0x00040000L |
54814 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7_MASK 0x00080000L |
54815 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8_MASK 0x00100000L |
54816 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9_MASK 0x00200000L |
54817 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10_MASK 0x00400000L |
54818 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11_MASK 0x00800000L |
54819 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12_MASK 0x01000000L |
54820 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13_MASK 0x02000000L |
54821 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14_MASK 0x04000000L |
54822 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15_MASK 0x08000000L |
54823 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16_MASK 0x10000000L |
54824 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17_MASK 0x20000000L |
54825 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18_MASK 0x40000000L |
54826 | #define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19_MASK 0x80000000L |
54827 | //BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ |
54828 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP0__SHIFT 0x0 |
54829 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP1__SHIFT 0x1 |
54830 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP2__SHIFT 0x2 |
54831 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP3__SHIFT 0x3 |
54832 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP4__SHIFT 0x4 |
54833 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP5__SHIFT 0x5 |
54834 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP6__SHIFT 0x6 |
54835 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP7__SHIFT 0x7 |
54836 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP8__SHIFT 0x8 |
54837 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP9__SHIFT 0x9 |
54838 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0__SHIFT 0xa |
54839 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1__SHIFT 0xb |
54840 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0__SHIFT 0xc |
54841 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1__SHIFT 0xd |
54842 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2__SHIFT 0xe |
54843 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3__SHIFT 0xf |
54844 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4__SHIFT 0x10 |
54845 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5__SHIFT 0x11 |
54846 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6__SHIFT 0x12 |
54847 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7__SHIFT 0x13 |
54848 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8__SHIFT 0x14 |
54849 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9__SHIFT 0x15 |
54850 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10__SHIFT 0x16 |
54851 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11__SHIFT 0x17 |
54852 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12__SHIFT 0x18 |
54853 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13__SHIFT 0x19 |
54854 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14__SHIFT 0x1a |
54855 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15__SHIFT 0x1b |
54856 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16__SHIFT 0x1c |
54857 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17__SHIFT 0x1d |
54858 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18__SHIFT 0x1e |
54859 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19__SHIFT 0x1f |
54860 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP0_MASK 0x00000001L |
54861 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP1_MASK 0x00000002L |
54862 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP2_MASK 0x00000004L |
54863 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP3_MASK 0x00000008L |
54864 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP4_MASK 0x00000010L |
54865 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP5_MASK 0x00000020L |
54866 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP6_MASK 0x00000040L |
54867 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP7_MASK 0x00000080L |
54868 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP8_MASK 0x00000100L |
54869 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP9_MASK 0x00000200L |
54870 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0_MASK 0x00000400L |
54871 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1_MASK 0x00000800L |
54872 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0_MASK 0x00001000L |
54873 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1_MASK 0x00002000L |
54874 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2_MASK 0x00004000L |
54875 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3_MASK 0x00008000L |
54876 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4_MASK 0x00010000L |
54877 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5_MASK 0x00020000L |
54878 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6_MASK 0x00040000L |
54879 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7_MASK 0x00080000L |
54880 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8_MASK 0x00100000L |
54881 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9_MASK 0x00200000L |
54882 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10_MASK 0x00400000L |
54883 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11_MASK 0x00800000L |
54884 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12_MASK 0x01000000L |
54885 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13_MASK 0x02000000L |
54886 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14_MASK 0x04000000L |
54887 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15_MASK 0x08000000L |
54888 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16_MASK 0x10000000L |
54889 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17_MASK 0x20000000L |
54890 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18_MASK 0x40000000L |
54891 | #define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19_MASK 0x80000000L |
54892 | //BIF_BX_PF0_GPU_HDP_FLUSH_REQ |
54893 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
54894 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
54895 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
54896 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
54897 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
54898 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
54899 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
54900 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
54901 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
54902 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
54903 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
54904 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
54905 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc |
54906 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd |
54907 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe |
54908 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf |
54909 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 |
54910 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 |
54911 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 |
54912 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 |
54913 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 |
54914 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 |
54915 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 |
54916 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 |
54917 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 |
54918 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 |
54919 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a |
54920 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b |
54921 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c |
54922 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d |
54923 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e |
54924 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f |
54925 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
54926 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
54927 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
54928 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
54929 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
54930 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
54931 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
54932 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
54933 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
54934 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
54935 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
54936 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
54937 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L |
54938 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L |
54939 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L |
54940 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L |
54941 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L |
54942 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L |
54943 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L |
54944 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L |
54945 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L |
54946 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L |
54947 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L |
54948 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L |
54949 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L |
54950 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L |
54951 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L |
54952 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L |
54953 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L |
54954 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L |
54955 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L |
54956 | #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L |
54957 | //BIF_BX_PF0_GPU_HDP_FLUSH_DONE |
54958 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
54959 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
54960 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
54961 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
54962 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
54963 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
54964 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
54965 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
54966 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
54967 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
54968 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
54969 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
54970 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc |
54971 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd |
54972 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe |
54973 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf |
54974 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 |
54975 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 |
54976 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 |
54977 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 |
54978 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 |
54979 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 |
54980 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 |
54981 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 |
54982 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 |
54983 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 |
54984 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a |
54985 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b |
54986 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c |
54987 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d |
54988 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e |
54989 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f |
54990 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
54991 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
54992 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
54993 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
54994 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
54995 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
54996 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
54997 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
54998 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
54999 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
55000 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
55001 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
55002 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L |
55003 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L |
55004 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L |
55005 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L |
55006 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L |
55007 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L |
55008 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L |
55009 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L |
55010 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L |
55011 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L |
55012 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L |
55013 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L |
55014 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L |
55015 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L |
55016 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L |
55017 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L |
55018 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L |
55019 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L |
55020 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L |
55021 | #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L |
55022 | //BIF_BX_PF0_BIF_TRANS_PENDING |
55023 | #define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
55024 | #define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
55025 | #define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
55026 | #define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
55027 | //BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS |
55028 | #define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
55029 | #define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
55030 | //BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 |
55031 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
55032 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
55033 | //BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 |
55034 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
55035 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
55036 | //BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 |
55037 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
55038 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
55039 | //BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 |
55040 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
55041 | #define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
55042 | //BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 |
55043 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
55044 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
55045 | //BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 |
55046 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
55047 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
55048 | //BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 |
55049 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
55050 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
55051 | //BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 |
55052 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
55053 | #define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
55054 | //BIF_BX_PF0_MAILBOX_CONTROL |
55055 | #define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
55056 | #define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
55057 | #define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
55058 | #define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
55059 | #define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
55060 | #define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
55061 | #define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
55062 | #define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
55063 | //BIF_BX_PF0_MAILBOX_INT_CNTL |
55064 | #define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
55065 | #define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
55066 | #define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
55067 | #define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
55068 | //BIF_BX_PF0_BIF_VMHV_MAILBOX |
55069 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
55070 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
55071 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
55072 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
55073 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
55074 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
55075 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
55076 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
55077 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
55078 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
55079 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
55080 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
55081 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
55082 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
55083 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
55084 | #define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
55085 | |
55086 | |
55087 | // addressBlock: nbio_nbif0_bif_bx_SYSDEC:1 |
55088 | //BIF_BX1_PCIE_INDEX |
55089 | #define BIF_BX1_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 |
55090 | #define BIF_BX1_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL |
55091 | //BIF_BX1_PCIE_DATA |
55092 | #define BIF_BX1_PCIE_DATA__PCIE_DATA__SHIFT 0x0 |
55093 | #define BIF_BX1_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL |
55094 | //BIF_BX1_PCIE_INDEX2 |
55095 | #define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 |
55096 | #define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL |
55097 | //BIF_BX1_PCIE_DATA2 |
55098 | #define BIF_BX1_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 |
55099 | #define BIF_BX1_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL |
55100 | //BIF_BX1_SBIOS_SCRATCH_0 |
55101 | #define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0 |
55102 | #define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
55103 | //BIF_BX1_SBIOS_SCRATCH_1 |
55104 | #define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0 |
55105 | #define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
55106 | //BIF_BX1_SBIOS_SCRATCH_2 |
55107 | #define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0 |
55108 | #define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
55109 | //BIF_BX1_SBIOS_SCRATCH_3 |
55110 | #define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0 |
55111 | #define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
55112 | //BIF_BX1_BIOS_SCRATCH_0 |
55113 | #define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 |
55114 | #define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL |
55115 | //BIF_BX1_BIOS_SCRATCH_1 |
55116 | #define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 |
55117 | #define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL |
55118 | //BIF_BX1_BIOS_SCRATCH_2 |
55119 | #define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 |
55120 | #define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL |
55121 | //BIF_BX1_BIOS_SCRATCH_3 |
55122 | #define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 |
55123 | #define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL |
55124 | //BIF_BX1_BIOS_SCRATCH_4 |
55125 | #define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 |
55126 | #define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL |
55127 | //BIF_BX1_BIOS_SCRATCH_5 |
55128 | #define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 |
55129 | #define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL |
55130 | //BIF_BX1_BIOS_SCRATCH_6 |
55131 | #define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 |
55132 | #define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL |
55133 | //BIF_BX1_BIOS_SCRATCH_7 |
55134 | #define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 |
55135 | #define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL |
55136 | //BIF_BX1_BIOS_SCRATCH_8 |
55137 | #define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 |
55138 | #define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL |
55139 | //BIF_BX1_BIOS_SCRATCH_9 |
55140 | #define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 |
55141 | #define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL |
55142 | //BIF_BX1_BIOS_SCRATCH_10 |
55143 | #define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 |
55144 | #define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL |
55145 | //BIF_BX1_BIOS_SCRATCH_11 |
55146 | #define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 |
55147 | #define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL |
55148 | //BIF_BX1_BIOS_SCRATCH_12 |
55149 | #define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 |
55150 | #define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL |
55151 | //BIF_BX1_BIOS_SCRATCH_13 |
55152 | #define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 |
55153 | #define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL |
55154 | //BIF_BX1_BIOS_SCRATCH_14 |
55155 | #define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 |
55156 | #define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL |
55157 | //BIF_BX1_BIOS_SCRATCH_15 |
55158 | #define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 |
55159 | #define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL |
55160 | //BIF_BX1_BIF_RLC_INTR_CNTL |
55161 | #define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0 |
55162 | #define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1 |
55163 | #define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2 |
55164 | #define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3 |
55165 | #define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L |
55166 | #define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L |
55167 | #define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L |
55168 | #define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L |
55169 | //BIF_BX1_BIF_VCE_INTR_CNTL |
55170 | #define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0 |
55171 | #define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1 |
55172 | #define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2 |
55173 | #define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3 |
55174 | #define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L |
55175 | #define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L |
55176 | #define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L |
55177 | #define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L |
55178 | //BIF_BX1_BIF_UVD_INTR_CNTL |
55179 | #define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0 |
55180 | #define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1 |
55181 | #define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2 |
55182 | #define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3 |
55183 | #define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_INST_SEL__SHIFT 0x1c |
55184 | #define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L |
55185 | #define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L |
55186 | #define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L |
55187 | #define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L |
55188 | #define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_INST_SEL_MASK 0xF0000000L |
55189 | //BIF_BX1_GFX_MMIOREG_CAM_ADDR0 |
55190 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 |
55191 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL |
55192 | //BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 |
55193 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 |
55194 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL |
55195 | //BIF_BX1_GFX_MMIOREG_CAM_ADDR1 |
55196 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 |
55197 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL |
55198 | //BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 |
55199 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 |
55200 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL |
55201 | //BIF_BX1_GFX_MMIOREG_CAM_ADDR2 |
55202 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 |
55203 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL |
55204 | //BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 |
55205 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 |
55206 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL |
55207 | //BIF_BX1_GFX_MMIOREG_CAM_ADDR3 |
55208 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 |
55209 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL |
55210 | //BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 |
55211 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 |
55212 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL |
55213 | //BIF_BX1_GFX_MMIOREG_CAM_ADDR4 |
55214 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 |
55215 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL |
55216 | //BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 |
55217 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 |
55218 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL |
55219 | //BIF_BX1_GFX_MMIOREG_CAM_ADDR5 |
55220 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 |
55221 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL |
55222 | //BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 |
55223 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 |
55224 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL |
55225 | //BIF_BX1_GFX_MMIOREG_CAM_ADDR6 |
55226 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 |
55227 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL |
55228 | //BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 |
55229 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 |
55230 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL |
55231 | //BIF_BX1_GFX_MMIOREG_CAM_ADDR7 |
55232 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 |
55233 | #define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL |
55234 | //BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 |
55235 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 |
55236 | #define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL |
55237 | //BIF_BX1_GFX_MMIOREG_CAM_CNTL |
55238 | #define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 |
55239 | #define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL |
55240 | //BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL |
55241 | #define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 |
55242 | #define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL |
55243 | //BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL |
55244 | #define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 |
55245 | #define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL |
55246 | //BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL |
55247 | #define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 |
55248 | #define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL |
55249 | |
55250 | |
55251 | // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1:1 |
55252 | //RCC_DWN_DEV0_2_DN_PCIE_RESERVED |
55253 | #define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
55254 | #define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL |
55255 | //RCC_DWN_DEV0_2_DN_PCIE_SCRATCH |
55256 | #define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
55257 | #define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
55258 | //RCC_DWN_DEV0_2_DN_PCIE_CNTL |
55259 | #define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
55260 | #define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 |
55261 | #define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
55262 | #define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
55263 | #define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L |
55264 | #define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
55265 | //RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL |
55266 | #define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
55267 | #define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
55268 | //RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 |
55269 | #define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
55270 | #define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
55271 | //RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL |
55272 | #define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
55273 | #define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 |
55274 | #define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
55275 | #define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L |
55276 | //RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL |
55277 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
55278 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
55279 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
55280 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
55281 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 |
55282 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
55283 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
55284 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
55285 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
55286 | #define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L |
55287 | |
55288 | |
55289 | // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1:1 |
55290 | //RCC_DWNP_DEV0_2_PCIE_ERR_CNTL |
55291 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
55292 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
55293 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 |
55294 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 |
55295 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 |
55296 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
55297 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
55298 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L |
55299 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L |
55300 | #define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L |
55301 | //RCC_DWNP_DEV0_2_PCIE_RX_CNTL |
55302 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
55303 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 |
55304 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
55305 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 |
55306 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
55307 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
55308 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L |
55309 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
55310 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L |
55311 | #define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
55312 | //RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL |
55313 | //RCC_DWNP_DEV0_2_PCIE_LC_CNTL2 |
55314 | #define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 |
55315 | #define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
55316 | #define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L |
55317 | #define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
55318 | //RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP |
55319 | #define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 |
55320 | #define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL |
55321 | |
55322 | |
55323 | // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1:1 |
55324 | //RCC_EP_DEV0_2_EP_PCIE_SCRATCH |
55325 | #define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
55326 | #define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
55327 | //RCC_EP_DEV0_2_EP_PCIE_CNTL |
55328 | #define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
55329 | #define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
55330 | #define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
55331 | #define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
55332 | #define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
55333 | #define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
55334 | //RCC_EP_DEV0_2_EP_PCIE_INT_CNTL |
55335 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 |
55336 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 |
55337 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 |
55338 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 |
55339 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 |
55340 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 |
55341 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L |
55342 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L |
55343 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L |
55344 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L |
55345 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L |
55346 | #define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L |
55347 | //RCC_EP_DEV0_2_EP_PCIE_INT_STATUS |
55348 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 |
55349 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 |
55350 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 |
55351 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 |
55352 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 |
55353 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 |
55354 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 |
55355 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L |
55356 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L |
55357 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L |
55358 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L |
55359 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L |
55360 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L |
55361 | #define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L |
55362 | //RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 |
55363 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
55364 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
55365 | //RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL |
55366 | #define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
55367 | #define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
55368 | //RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL |
55369 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
55370 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
55371 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
55372 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
55373 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 |
55374 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
55375 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
55376 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
55377 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
55378 | #define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L |
55379 | //RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL |
55380 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 |
55381 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 |
55382 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 |
55383 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 |
55384 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa |
55385 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd |
55386 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe |
55387 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf |
55388 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 |
55389 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 |
55390 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L |
55391 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L |
55392 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L |
55393 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L |
55394 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L |
55395 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L |
55396 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L |
55397 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L |
55398 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L |
55399 | #define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L |
55400 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 |
55401 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55402 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55403 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 |
55404 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55405 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55406 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 |
55407 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55408 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55409 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 |
55410 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55411 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55412 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 |
55413 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55414 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55415 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 |
55416 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55417 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55418 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 |
55419 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55420 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55421 | //RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 |
55422 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55423 | #define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55424 | //RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP |
55425 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
55426 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
55427 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
55428 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
55429 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
55430 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
55431 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
55432 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
55433 | //RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR |
55434 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
55435 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
55436 | //RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL |
55437 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 |
55438 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 |
55439 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL |
55440 | #define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L |
55441 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 |
55442 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55443 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55444 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 |
55445 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55446 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55447 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 |
55448 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55449 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55450 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 |
55451 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55452 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55453 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 |
55454 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55455 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55456 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 |
55457 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55458 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55459 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 |
55460 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55461 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55462 | //RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 |
55463 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
55464 | #define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
55465 | //RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL |
55466 | #define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 |
55467 | #define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL |
55468 | //RCC_EP_DEV0_2_EP_PCIEP_RESERVED |
55469 | #define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
55470 | #define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
55471 | //RCC_EP_DEV0_2_EP_PCIE_TX_CNTL |
55472 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
55473 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
55474 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 |
55475 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 |
55476 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a |
55477 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
55478 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
55479 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L |
55480 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L |
55481 | #define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L |
55482 | //RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID |
55483 | #define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
55484 | #define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
55485 | #define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
55486 | #define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
55487 | #define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
55488 | #define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
55489 | //RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL |
55490 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
55491 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
55492 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
55493 | #define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
55494 | //RCC_EP_DEV0_2_EP_PCIE_RX_CNTL |
55495 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
55496 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
55497 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
55498 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
55499 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
55500 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
55501 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
55502 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
55503 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
55504 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
55505 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
55506 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
55507 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
55508 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
55509 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
55510 | #define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
55511 | //RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL |
55512 | |
55513 | |
55514 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1 |
55515 | //BIF_BX_PF1_MM_INDEX |
55516 | #define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
55517 | #define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT 0x1f |
55518 | #define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
55519 | #define BIF_BX_PF1_MM_INDEX__MM_APER_MASK 0x80000000L |
55520 | //BIF_BX_PF1_MM_DATA |
55521 | #define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT 0x0 |
55522 | #define BIF_BX_PF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
55523 | //BIF_BX_PF1_MM_INDEX_HI |
55524 | #define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
55525 | #define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
55526 | |
55527 | |
55528 | // addressBlock: nbio_nbif0_bif_bx_BIFDEC1:1 |
55529 | //BIF_BX1_BIF_MM_INDACCESS_CNTL |
55530 | #define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 |
55531 | #define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L |
55532 | //BIF_BX1_BUS_CNTL |
55533 | #define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 |
55534 | #define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 |
55535 | #define BIF_BX1_BUS_CNTL__SET_AZ_TC__SHIFT 0xa |
55536 | #define BIF_BX1_BUS_CNTL__SET_MC_TC__SHIFT 0xd |
55537 | #define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 |
55538 | #define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 |
55539 | #define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 |
55540 | #define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18 |
55541 | #define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 |
55542 | #define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a |
55543 | #define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b |
55544 | #define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c |
55545 | #define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d |
55546 | #define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e |
55547 | #define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f |
55548 | #define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L |
55549 | #define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L |
55550 | #define BIF_BX1_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L |
55551 | #define BIF_BX1_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L |
55552 | #define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L |
55553 | #define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L |
55554 | #define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L |
55555 | #define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L |
55556 | #define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L |
55557 | #define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L |
55558 | #define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L |
55559 | #define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L |
55560 | #define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L |
55561 | #define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L |
55562 | #define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L |
55563 | //BIF_BX1_BIF_SCRATCH0 |
55564 | #define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 |
55565 | #define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL |
55566 | //BIF_BX1_BIF_SCRATCH1 |
55567 | #define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 |
55568 | #define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL |
55569 | //BIF_BX1_BX_RESET_EN |
55570 | #define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 |
55571 | #define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L |
55572 | //BIF_BX1_MM_CFGREGS_CNTL |
55573 | #define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 |
55574 | #define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 |
55575 | #define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f |
55576 | #define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L |
55577 | #define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L |
55578 | #define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L |
55579 | //BIF_BX1_BX_RESET_CNTL |
55580 | #define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 |
55581 | #define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L |
55582 | //BIF_BX1_INTERRUPT_CNTL |
55583 | #define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 |
55584 | #define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 |
55585 | #define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 |
55586 | #define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 |
55587 | #define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 |
55588 | #define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf |
55589 | #define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 |
55590 | #define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 |
55591 | #define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12 |
55592 | #define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L |
55593 | #define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L |
55594 | #define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L |
55595 | #define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L |
55596 | #define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L |
55597 | #define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L |
55598 | #define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L |
55599 | #define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L |
55600 | #define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L |
55601 | //BIF_BX1_INTERRUPT_CNTL2 |
55602 | #define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 |
55603 | #define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL |
55604 | //BIF_BX1_CLKREQB_PAD_CNTL |
55605 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 |
55606 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 |
55607 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 |
55608 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 |
55609 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 |
55610 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 |
55611 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 |
55612 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 |
55613 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 |
55614 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa |
55615 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb |
55616 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc |
55617 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd |
55618 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L |
55619 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L |
55620 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L |
55621 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L |
55622 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L |
55623 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L |
55624 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L |
55625 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L |
55626 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L |
55627 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L |
55628 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L |
55629 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L |
55630 | #define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L |
55631 | //BIF_BX1_BIF_FEATURES_CONTROL_MISC |
55632 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 |
55633 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 |
55634 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 |
55635 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 |
55636 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb |
55637 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc |
55638 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd |
55639 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf |
55640 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10 |
55641 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18 |
55642 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L |
55643 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L |
55644 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L |
55645 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L |
55646 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L |
55647 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L |
55648 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L |
55649 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L |
55650 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x00FF0000L |
55651 | #define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L |
55652 | //BIF_BX1_HDP_ATOMIC_CONTROL_MISC |
55653 | #define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0 |
55654 | #define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL |
55655 | //BIF_BX1_BIF_DOORBELL_CNTL |
55656 | #define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 |
55657 | #define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 |
55658 | #define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 |
55659 | #define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 |
55660 | #define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 |
55661 | #define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 |
55662 | #define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 |
55663 | #define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a |
55664 | #define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b |
55665 | #define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L |
55666 | #define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L |
55667 | #define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L |
55668 | #define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L |
55669 | #define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L |
55670 | #define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L |
55671 | #define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L |
55672 | #define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L |
55673 | #define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L |
55674 | //BIF_BX1_BIF_DOORBELL_INT_CNTL |
55675 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 |
55676 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 |
55677 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 |
55678 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 |
55679 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 |
55680 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 |
55681 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 |
55682 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19 |
55683 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a |
55684 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c |
55685 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d |
55686 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e |
55687 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f |
55688 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L |
55689 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L |
55690 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L |
55691 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L |
55692 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L |
55693 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L |
55694 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L |
55695 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L |
55696 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L |
55697 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L |
55698 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L |
55699 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L |
55700 | #define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L |
55701 | //BIF_BX1_BIF_FB_EN |
55702 | #define BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 |
55703 | #define BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 |
55704 | #define BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L |
55705 | #define BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L |
55706 | //BIF_BX1_BIF_INTR_CNTL |
55707 | #define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 |
55708 | #define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L |
55709 | //BIF_BX1_BIF_MST_TRANS_PENDING_VF |
55710 | #define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
55711 | #define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL |
55712 | //BIF_BX1_BIF_SLV_TRANS_PENDING_VF |
55713 | #define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 |
55714 | #define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL |
55715 | //BIF_BX1_BACO_CNTL |
55716 | #define BIF_BX1_BACO_CNTL__BACO_EN__SHIFT 0x0 |
55717 | #define BIF_BX1_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1 |
55718 | #define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 |
55719 | #define BIF_BX1_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 |
55720 | #define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 |
55721 | #define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 |
55722 | #define BIF_BX1_BACO_CNTL__BACO_MODE__SHIFT 0x8 |
55723 | #define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 |
55724 | #define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f |
55725 | #define BIF_BX1_BACO_CNTL__BACO_EN_MASK 0x00000001L |
55726 | #define BIF_BX1_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L |
55727 | #define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L |
55728 | #define BIF_BX1_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L |
55729 | #define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L |
55730 | #define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L |
55731 | #define BIF_BX1_BACO_CNTL__BACO_MODE_MASK 0x00000100L |
55732 | #define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L |
55733 | #define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L |
55734 | //BIF_BX1_BIF_BACO_EXIT_TIME0 |
55735 | #define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 |
55736 | #define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL |
55737 | //BIF_BX1_BIF_BACO_EXIT_TIMER1 |
55738 | #define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 |
55739 | #define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 |
55740 | #define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a |
55741 | #define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b |
55742 | #define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c |
55743 | #define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d |
55744 | #define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f |
55745 | #define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL |
55746 | #define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L |
55747 | #define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L |
55748 | #define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L |
55749 | #define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L |
55750 | #define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L |
55751 | #define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L |
55752 | //BIF_BX1_BIF_BACO_EXIT_TIMER2 |
55753 | #define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 |
55754 | #define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL |
55755 | //BIF_BX1_BIF_BACO_EXIT_TIMER3 |
55756 | #define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 |
55757 | #define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL |
55758 | //BIF_BX1_BIF_BACO_EXIT_TIMER4 |
55759 | #define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 |
55760 | #define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL |
55761 | //BIF_BX1_MEM_TYPE_CNTL |
55762 | #define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 |
55763 | #define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L |
55764 | //BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL |
55765 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0 |
55766 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1 |
55767 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8 |
55768 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L |
55769 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L |
55770 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L |
55771 | //BIF_BX1_NBIF_GFX_ADDR_LUT_0 |
55772 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0 |
55773 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL |
55774 | //BIF_BX1_NBIF_GFX_ADDR_LUT_1 |
55775 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0 |
55776 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL |
55777 | //BIF_BX1_NBIF_GFX_ADDR_LUT_2 |
55778 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0 |
55779 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL |
55780 | //BIF_BX1_NBIF_GFX_ADDR_LUT_3 |
55781 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0 |
55782 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL |
55783 | //BIF_BX1_NBIF_GFX_ADDR_LUT_4 |
55784 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0 |
55785 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL |
55786 | //BIF_BX1_NBIF_GFX_ADDR_LUT_5 |
55787 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0 |
55788 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL |
55789 | //BIF_BX1_NBIF_GFX_ADDR_LUT_6 |
55790 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0 |
55791 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL |
55792 | //BIF_BX1_NBIF_GFX_ADDR_LUT_7 |
55793 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0 |
55794 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL |
55795 | //BIF_BX1_NBIF_GFX_ADDR_LUT_8 |
55796 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0 |
55797 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL |
55798 | //BIF_BX1_NBIF_GFX_ADDR_LUT_9 |
55799 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0 |
55800 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL |
55801 | //BIF_BX1_NBIF_GFX_ADDR_LUT_10 |
55802 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0 |
55803 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL |
55804 | //BIF_BX1_NBIF_GFX_ADDR_LUT_11 |
55805 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0 |
55806 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL |
55807 | //BIF_BX1_NBIF_GFX_ADDR_LUT_12 |
55808 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0 |
55809 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL |
55810 | //BIF_BX1_NBIF_GFX_ADDR_LUT_13 |
55811 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0 |
55812 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL |
55813 | //BIF_BX1_NBIF_GFX_ADDR_LUT_14 |
55814 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0 |
55815 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL |
55816 | //BIF_BX1_NBIF_GFX_ADDR_LUT_15 |
55817 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0 |
55818 | #define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL |
55819 | //BIF_BX1_GFX_RST_CNTL |
55820 | #define BIF_BX1_GFX_RST_CNTL__GFX_RST_FINISH_INDICATION__SHIFT 0x0 |
55821 | #define BIF_BX1_GFX_RST_CNTL__GFX_RST_FINISH_INDICATION_MASK 0x00000001L |
55822 | //BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL |
55823 | #define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
55824 | #define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL |
55825 | //BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL |
55826 | #define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
55827 | #define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL |
55828 | //BIF_BX1_BIF_RB_CNTL |
55829 | #define BIF_BX1_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
55830 | #define BIF_BX1_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 |
55831 | #define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 |
55832 | #define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 |
55833 | #define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 |
55834 | #define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a |
55835 | #define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d |
55836 | #define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e |
55837 | #define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f |
55838 | #define BIF_BX1_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
55839 | #define BIF_BX1_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
55840 | #define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L |
55841 | #define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L |
55842 | #define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L |
55843 | #define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L |
55844 | #define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L |
55845 | #define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L |
55846 | #define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L |
55847 | //BIF_BX1_BIF_RB_BASE |
55848 | #define BIF_BX1_BIF_RB_BASE__ADDR__SHIFT 0x0 |
55849 | #define BIF_BX1_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
55850 | //BIF_BX1_BIF_RB_RPTR |
55851 | #define BIF_BX1_BIF_RB_RPTR__OFFSET__SHIFT 0x2 |
55852 | #define BIF_BX1_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL |
55853 | //BIF_BX1_BIF_RB_WPTR |
55854 | #define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 |
55855 | #define BIF_BX1_BIF_RB_WPTR__OFFSET__SHIFT 0x2 |
55856 | #define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L |
55857 | #define BIF_BX1_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL |
55858 | //BIF_BX1_BIF_RB_WPTR_ADDR_HI |
55859 | #define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 |
55860 | #define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL |
55861 | //BIF_BX1_BIF_RB_WPTR_ADDR_LO |
55862 | #define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 |
55863 | #define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
55864 | //BIF_BX1_MAILBOX_INDEX |
55865 | #define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 |
55866 | #define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL |
55867 | //BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE |
55868 | #define BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 |
55869 | #define BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL |
55870 | //BIF_BX1_BIF_PERSTB_PAD_CNTL |
55871 | #define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 |
55872 | #define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL |
55873 | //BIF_BX1_BIF_PX_EN_PAD_CNTL |
55874 | #define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 |
55875 | #define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL |
55876 | //BIF_BX1_BIF_REFPADKIN_PAD_CNTL |
55877 | #define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 |
55878 | #define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL |
55879 | //BIF_BX1_BIF_CLKREQB_PAD_CNTL |
55880 | #define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 |
55881 | #define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL |
55882 | //BIF_BX1_BIF_PWRBRK_PAD_CNTL |
55883 | #define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0 |
55884 | #define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL |
55885 | |
55886 | |
55887 | // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 |
55888 | //RCC_STRAP1_RCC_DEV0_EPF0_STRAP0 |
55889 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 |
55890 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 |
55891 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 |
55892 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 |
55893 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c |
55894 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d |
55895 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e |
55896 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f |
55897 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL |
55898 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L |
55899 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L |
55900 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L |
55901 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L |
55902 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L |
55903 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L |
55904 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L |
55905 | |
55906 | |
55907 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1:1 |
55908 | //BIF_BX_PF1_BIF_BME_STATUS |
55909 | #define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
55910 | #define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
55911 | #define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
55912 | #define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
55913 | //BIF_BX_PF1_BIF_ATOMIC_ERR_LOG |
55914 | //BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
55915 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
55916 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
55917 | //BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
55918 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
55919 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
55920 | //BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL |
55921 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
55922 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
55923 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
55924 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
55925 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
55926 | #define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
55927 | //BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL |
55928 | #define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
55929 | #define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
55930 | //BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL |
55931 | #define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
55932 | #define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
55933 | //BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL |
55934 | #define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 |
55935 | #define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L |
55936 | //BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL |
55937 | #define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 |
55938 | #define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L |
55939 | //BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ |
55940 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP0__SHIFT 0x0 |
55941 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP1__SHIFT 0x1 |
55942 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP2__SHIFT 0x2 |
55943 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP3__SHIFT 0x3 |
55944 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP4__SHIFT 0x4 |
55945 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP5__SHIFT 0x5 |
55946 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP6__SHIFT 0x6 |
55947 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP7__SHIFT 0x7 |
55948 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP8__SHIFT 0x8 |
55949 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP9__SHIFT 0x9 |
55950 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA0__SHIFT 0xa |
55951 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA1__SHIFT 0xb |
55952 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0__SHIFT 0xc |
55953 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1__SHIFT 0xd |
55954 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2__SHIFT 0xe |
55955 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3__SHIFT 0xf |
55956 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4__SHIFT 0x10 |
55957 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5__SHIFT 0x11 |
55958 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6__SHIFT 0x12 |
55959 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7__SHIFT 0x13 |
55960 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8__SHIFT 0x14 |
55961 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9__SHIFT 0x15 |
55962 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10__SHIFT 0x16 |
55963 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11__SHIFT 0x17 |
55964 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12__SHIFT 0x18 |
55965 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13__SHIFT 0x19 |
55966 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14__SHIFT 0x1a |
55967 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15__SHIFT 0x1b |
55968 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16__SHIFT 0x1c |
55969 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17__SHIFT 0x1d |
55970 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18__SHIFT 0x1e |
55971 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19__SHIFT 0x1f |
55972 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP0_MASK 0x00000001L |
55973 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP1_MASK 0x00000002L |
55974 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP2_MASK 0x00000004L |
55975 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP3_MASK 0x00000008L |
55976 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP4_MASK 0x00000010L |
55977 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP5_MASK 0x00000020L |
55978 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP6_MASK 0x00000040L |
55979 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP7_MASK 0x00000080L |
55980 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP8_MASK 0x00000100L |
55981 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP9_MASK 0x00000200L |
55982 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA0_MASK 0x00000400L |
55983 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA1_MASK 0x00000800L |
55984 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0_MASK 0x00001000L |
55985 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1_MASK 0x00002000L |
55986 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2_MASK 0x00004000L |
55987 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3_MASK 0x00008000L |
55988 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4_MASK 0x00010000L |
55989 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5_MASK 0x00020000L |
55990 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6_MASK 0x00040000L |
55991 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7_MASK 0x00080000L |
55992 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8_MASK 0x00100000L |
55993 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9_MASK 0x00200000L |
55994 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10_MASK 0x00400000L |
55995 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11_MASK 0x00800000L |
55996 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12_MASK 0x01000000L |
55997 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13_MASK 0x02000000L |
55998 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14_MASK 0x04000000L |
55999 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15_MASK 0x08000000L |
56000 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16_MASK 0x10000000L |
56001 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17_MASK 0x20000000L |
56002 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18_MASK 0x40000000L |
56003 | #define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19_MASK 0x80000000L |
56004 | //BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ |
56005 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP0__SHIFT 0x0 |
56006 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP1__SHIFT 0x1 |
56007 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP2__SHIFT 0x2 |
56008 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP3__SHIFT 0x3 |
56009 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP4__SHIFT 0x4 |
56010 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP5__SHIFT 0x5 |
56011 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP6__SHIFT 0x6 |
56012 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP7__SHIFT 0x7 |
56013 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP8__SHIFT 0x8 |
56014 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP9__SHIFT 0x9 |
56015 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0__SHIFT 0xa |
56016 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1__SHIFT 0xb |
56017 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0__SHIFT 0xc |
56018 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1__SHIFT 0xd |
56019 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2__SHIFT 0xe |
56020 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3__SHIFT 0xf |
56021 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4__SHIFT 0x10 |
56022 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5__SHIFT 0x11 |
56023 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6__SHIFT 0x12 |
56024 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7__SHIFT 0x13 |
56025 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8__SHIFT 0x14 |
56026 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9__SHIFT 0x15 |
56027 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10__SHIFT 0x16 |
56028 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11__SHIFT 0x17 |
56029 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12__SHIFT 0x18 |
56030 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13__SHIFT 0x19 |
56031 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14__SHIFT 0x1a |
56032 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15__SHIFT 0x1b |
56033 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16__SHIFT 0x1c |
56034 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17__SHIFT 0x1d |
56035 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18__SHIFT 0x1e |
56036 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19__SHIFT 0x1f |
56037 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP0_MASK 0x00000001L |
56038 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP1_MASK 0x00000002L |
56039 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP2_MASK 0x00000004L |
56040 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP3_MASK 0x00000008L |
56041 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP4_MASK 0x00000010L |
56042 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP5_MASK 0x00000020L |
56043 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP6_MASK 0x00000040L |
56044 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP7_MASK 0x00000080L |
56045 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP8_MASK 0x00000100L |
56046 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP9_MASK 0x00000200L |
56047 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0_MASK 0x00000400L |
56048 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1_MASK 0x00000800L |
56049 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0_MASK 0x00001000L |
56050 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1_MASK 0x00002000L |
56051 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2_MASK 0x00004000L |
56052 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3_MASK 0x00008000L |
56053 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4_MASK 0x00010000L |
56054 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5_MASK 0x00020000L |
56055 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6_MASK 0x00040000L |
56056 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7_MASK 0x00080000L |
56057 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8_MASK 0x00100000L |
56058 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9_MASK 0x00200000L |
56059 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10_MASK 0x00400000L |
56060 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11_MASK 0x00800000L |
56061 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12_MASK 0x01000000L |
56062 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13_MASK 0x02000000L |
56063 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14_MASK 0x04000000L |
56064 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15_MASK 0x08000000L |
56065 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16_MASK 0x10000000L |
56066 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17_MASK 0x20000000L |
56067 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18_MASK 0x40000000L |
56068 | #define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19_MASK 0x80000000L |
56069 | //BIF_BX_PF1_GPU_HDP_FLUSH_REQ |
56070 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
56071 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
56072 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
56073 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
56074 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
56075 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
56076 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
56077 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
56078 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
56079 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
56080 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
56081 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
56082 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc |
56083 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd |
56084 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe |
56085 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf |
56086 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 |
56087 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 |
56088 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 |
56089 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 |
56090 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 |
56091 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 |
56092 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 |
56093 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 |
56094 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 |
56095 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 |
56096 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a |
56097 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b |
56098 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c |
56099 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d |
56100 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e |
56101 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f |
56102 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
56103 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
56104 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
56105 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
56106 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
56107 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
56108 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
56109 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
56110 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
56111 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
56112 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
56113 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
56114 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L |
56115 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L |
56116 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L |
56117 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L |
56118 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L |
56119 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L |
56120 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L |
56121 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L |
56122 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L |
56123 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L |
56124 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L |
56125 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L |
56126 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L |
56127 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L |
56128 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L |
56129 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L |
56130 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L |
56131 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L |
56132 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L |
56133 | #define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L |
56134 | //BIF_BX_PF1_GPU_HDP_FLUSH_DONE |
56135 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
56136 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
56137 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
56138 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
56139 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
56140 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
56141 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
56142 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
56143 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
56144 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
56145 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
56146 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
56147 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc |
56148 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd |
56149 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe |
56150 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf |
56151 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 |
56152 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 |
56153 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 |
56154 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 |
56155 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 |
56156 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 |
56157 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 |
56158 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 |
56159 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 |
56160 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 |
56161 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a |
56162 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b |
56163 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c |
56164 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d |
56165 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e |
56166 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f |
56167 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
56168 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
56169 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
56170 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
56171 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
56172 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
56173 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
56174 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
56175 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
56176 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
56177 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
56178 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
56179 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L |
56180 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L |
56181 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L |
56182 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L |
56183 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L |
56184 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L |
56185 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L |
56186 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L |
56187 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L |
56188 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L |
56189 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L |
56190 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L |
56191 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L |
56192 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L |
56193 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L |
56194 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L |
56195 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L |
56196 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L |
56197 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L |
56198 | #define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L |
56199 | //BIF_BX_PF1_BIF_TRANS_PENDING |
56200 | #define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
56201 | #define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
56202 | #define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
56203 | #define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
56204 | //BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS |
56205 | #define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
56206 | #define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
56207 | //BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 |
56208 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
56209 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
56210 | //BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 |
56211 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
56212 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
56213 | //BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 |
56214 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
56215 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
56216 | //BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 |
56217 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
56218 | #define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
56219 | //BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 |
56220 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
56221 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
56222 | //BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 |
56223 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
56224 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
56225 | //BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 |
56226 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
56227 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
56228 | //BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 |
56229 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
56230 | #define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
56231 | //BIF_BX_PF1_MAILBOX_CONTROL |
56232 | #define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
56233 | #define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
56234 | #define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
56235 | #define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
56236 | #define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
56237 | #define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
56238 | #define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
56239 | #define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
56240 | //BIF_BX_PF1_MAILBOX_INT_CNTL |
56241 | #define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
56242 | #define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
56243 | #define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
56244 | #define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
56245 | //BIF_BX_PF1_BIF_VMHV_MAILBOX |
56246 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
56247 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
56248 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
56249 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
56250 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
56251 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
56252 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
56253 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
56254 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
56255 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
56256 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
56257 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
56258 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
56259 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
56260 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
56261 | #define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
56262 | |
56263 | |
56264 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1 |
56265 | //RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN |
56266 | #define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
56267 | #define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
56268 | //RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE |
56269 | #define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
56270 | #define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
56271 | |
56272 | |
56273 | // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1:1 |
56274 | //RCC_STRAP2_RCC_DEV0_EPF0_STRAP0 |
56275 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 |
56276 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 |
56277 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 |
56278 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 |
56279 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c |
56280 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d |
56281 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e |
56282 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f |
56283 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL |
56284 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L |
56285 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L |
56286 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L |
56287 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L |
56288 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L |
56289 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L |
56290 | #define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L |
56291 | |
56292 | |
56293 | // addressBlock: nbio_nbif0_gdc_GDCDEC |
56294 | //GDC0_A2S_QUEUE_FIFO_ARB_CNTL |
56295 | #define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT 0x0 |
56296 | #define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT 0x8 |
56297 | #define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE__SHIFT 0x10 |
56298 | #define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE__SHIFT 0x11 |
56299 | #define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY_MASK 0x000000FFL |
56300 | #define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY_MASK 0x0000FF00L |
56301 | #define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE_MASK 0x00010000L |
56302 | #define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE_MASK 0x00020000L |
56303 | //GDC0_NBIF_GFX_DOORBELL_STATUS |
56304 | #define GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0 |
56305 | #define GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x00000001L |
56306 | //GDC0_BIF_SDMA0_DOORBELL_RANGE |
56307 | #define GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56308 | #define GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56309 | #define GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56310 | #define GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56311 | //GDC0_BIF_SDMA1_DOORBELL_RANGE |
56312 | #define GDC0_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56313 | #define GDC0_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56314 | #define GDC0_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56315 | #define GDC0_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56316 | //GDC0_BIF_IH_DOORBELL_RANGE |
56317 | #define GDC0_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56318 | #define GDC0_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56319 | #define GDC0_BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56320 | #define GDC0_BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56321 | //GDC0_BIF_VCN0_DOORBELL_RANGE |
56322 | #define GDC0_BIF_VCN0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56323 | #define GDC0_BIF_VCN0_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56324 | #define GDC0_BIF_VCN0_DOORBELL_RANGE__NEED_DEDUCT__SHIFT 0x15 |
56325 | #define GDC0_BIF_VCN0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56326 | #define GDC0_BIF_VCN0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56327 | #define GDC0_BIF_VCN0_DOORBELL_RANGE__NEED_DEDUCT_MASK 0x00200000L |
56328 | //GDC0_BIF_RLC_DOORBELL_RANGE |
56329 | #define GDC0_BIF_RLC_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56330 | #define GDC0_BIF_RLC_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56331 | #define GDC0_BIF_RLC_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56332 | #define GDC0_BIF_RLC_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56333 | //GDC0_BIF_SDMA2_DOORBELL_RANGE |
56334 | #define GDC0_BIF_SDMA2_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56335 | #define GDC0_BIF_SDMA2_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56336 | #define GDC0_BIF_SDMA2_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56337 | #define GDC0_BIF_SDMA2_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56338 | //GDC0_BIF_SDMA3_DOORBELL_RANGE |
56339 | #define GDC0_BIF_SDMA3_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56340 | #define GDC0_BIF_SDMA3_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56341 | #define GDC0_BIF_SDMA3_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56342 | #define GDC0_BIF_SDMA3_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56343 | //GDC0_BIF_VCN1_DOORBELL_RANGE |
56344 | #define GDC0_BIF_VCN1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56345 | #define GDC0_BIF_VCN1_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56346 | #define GDC0_BIF_VCN1_DOORBELL_RANGE__NEED_DEDUCT__SHIFT 0x15 |
56347 | #define GDC0_BIF_VCN1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56348 | #define GDC0_BIF_VCN1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56349 | #define GDC0_BIF_VCN1_DOORBELL_RANGE__NEED_DEDUCT_MASK 0x00200000L |
56350 | //GDC0_BIF_SDMA4_DOORBELL_RANGE |
56351 | #define GDC0_BIF_SDMA4_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56352 | #define GDC0_BIF_SDMA4_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56353 | #define GDC0_BIF_SDMA4_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56354 | #define GDC0_BIF_SDMA4_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56355 | //GDC0_BIF_SDMA5_DOORBELL_RANGE |
56356 | #define GDC0_BIF_SDMA5_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56357 | #define GDC0_BIF_SDMA5_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56358 | #define GDC0_BIF_SDMA5_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56359 | #define GDC0_BIF_SDMA5_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56360 | //GDC0_BIF_CSDMA_DOORBELL_RANGE |
56361 | #define GDC0_BIF_CSDMA_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56362 | #define GDC0_BIF_CSDMA_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56363 | #define GDC0_BIF_CSDMA_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56364 | #define GDC0_BIF_CSDMA_DOORBELL_RANGE__SIZE_MASK 0x00FF0000L |
56365 | //GDC0_BIF_VPE_DOORBELL_RANGE |
56366 | #define GDC0_BIF_VPE_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56367 | #define GDC0_BIF_VPE_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56368 | #define GDC0_BIF_VPE_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56369 | #define GDC0_BIF_VPE_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56370 | //GDC0_ATDMA_MISC_CNTL |
56371 | #define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 |
56372 | #define GDC0_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 |
56373 | #define GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT 0x2 |
56374 | #define GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT 0x8 |
56375 | #define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 |
56376 | #define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 |
56377 | #define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L |
56378 | #define GDC0_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L |
56379 | #define GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK 0x0000000CL |
56380 | #define GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK 0x0000FF00L |
56381 | #define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L |
56382 | #define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L |
56383 | //GDC0_BIF_DOORBELL_FENCE_CNTL |
56384 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE__SHIFT 0x0 |
56385 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE__SHIFT 0x1 |
56386 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE__SHIFT 0x2 |
56387 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE__SHIFT 0x4 |
56388 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE__SHIFT 0x5 |
56389 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE__SHIFT 0x6 |
56390 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE__SHIFT 0x7 |
56391 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE__SHIFT 0x8 |
56392 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CSDMA_ENABLE__SHIFT 0x9 |
56393 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_VPE_ENABLE__SHIFT 0xa |
56394 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x10 |
56395 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE_MASK 0x00000001L |
56396 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE_MASK 0x00000002L |
56397 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE_MASK 0x00000004L |
56398 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE_MASK 0x00000010L |
56399 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE_MASK 0x00000020L |
56400 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE_MASK 0x00000040L |
56401 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE_MASK 0x00000080L |
56402 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE_MASK 0x00000100L |
56403 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CSDMA_ENABLE_MASK 0x00000200L |
56404 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_VPE_ENABLE_MASK 0x00000400L |
56405 | #define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00010000L |
56406 | //GDC0_S2A_MISC_CNTL |
56407 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0 |
56408 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1 |
56409 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2 |
56410 | #define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 |
56411 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS__SHIFT 0x5 |
56412 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_VPE_DIS__SHIFT 0x6 |
56413 | #define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8 |
56414 | #define GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa |
56415 | #define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc |
56416 | #define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10 |
56417 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS__SHIFT 0x18 |
56418 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS__SHIFT 0x19 |
56419 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS__SHIFT 0x1a |
56420 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS__SHIFT 0x1b |
56421 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CSDMA_DIS__SHIFT 0x1c |
56422 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L |
56423 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L |
56424 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L |
56425 | #define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L |
56426 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS_MASK 0x00000020L |
56427 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_VPE_DIS_MASK 0x00000040L |
56428 | #define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L |
56429 | #define GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L |
56430 | #define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L |
56431 | #define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L |
56432 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS_MASK 0x01000000L |
56433 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS_MASK 0x02000000L |
56434 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS_MASK 0x04000000L |
56435 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS_MASK 0x08000000L |
56436 | #define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CSDMA_DIS_MASK 0x10000000L |
56437 | |
56438 | |
56439 | // addressBlock: nbio_nbif0_gdc_GDC_LINEAR_REGION |
56440 | //GDC1_A2S_QUEUE_FIFO_ARB_CNTL |
56441 | #define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT 0x0 |
56442 | #define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT 0x8 |
56443 | #define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE__SHIFT 0x10 |
56444 | #define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE__SHIFT 0x11 |
56445 | #define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY_MASK 0x000000FFL |
56446 | #define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY_MASK 0x0000FF00L |
56447 | #define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE_MASK 0x00010000L |
56448 | #define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE_MASK 0x00020000L |
56449 | //GDC1_NBIF_GFX_DOORBELL_STATUS |
56450 | #define GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0 |
56451 | #define GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x00000001L |
56452 | //GDC1_BIF_SDMA0_DOORBELL_RANGE |
56453 | #define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56454 | #define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56455 | #define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56456 | #define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56457 | //GDC1_BIF_SDMA1_DOORBELL_RANGE |
56458 | #define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56459 | #define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56460 | #define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56461 | #define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56462 | //GDC1_BIF_IH_DOORBELL_RANGE |
56463 | #define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56464 | #define GDC1_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56465 | #define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56466 | #define GDC1_BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56467 | //GDC1_BIF_VCN0_DOORBELL_RANGE |
56468 | #define GDC1_BIF_VCN0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56469 | #define GDC1_BIF_VCN0_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56470 | #define GDC1_BIF_VCN0_DOORBELL_RANGE__NEED_DEDUCT__SHIFT 0x15 |
56471 | #define GDC1_BIF_VCN0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56472 | #define GDC1_BIF_VCN0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56473 | #define GDC1_BIF_VCN0_DOORBELL_RANGE__NEED_DEDUCT_MASK 0x00200000L |
56474 | //GDC1_BIF_RLC_DOORBELL_RANGE |
56475 | #define GDC1_BIF_RLC_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56476 | #define GDC1_BIF_RLC_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56477 | #define GDC1_BIF_RLC_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56478 | #define GDC1_BIF_RLC_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56479 | //GDC1_BIF_SDMA2_DOORBELL_RANGE |
56480 | #define GDC1_BIF_SDMA2_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56481 | #define GDC1_BIF_SDMA2_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56482 | #define GDC1_BIF_SDMA2_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56483 | #define GDC1_BIF_SDMA2_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56484 | //GDC1_BIF_SDMA3_DOORBELL_RANGE |
56485 | #define GDC1_BIF_SDMA3_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56486 | #define GDC1_BIF_SDMA3_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56487 | #define GDC1_BIF_SDMA3_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56488 | #define GDC1_BIF_SDMA3_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56489 | //GDC1_BIF_VCN1_DOORBELL_RANGE |
56490 | #define GDC1_BIF_VCN1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56491 | #define GDC1_BIF_VCN1_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56492 | #define GDC1_BIF_VCN1_DOORBELL_RANGE__NEED_DEDUCT__SHIFT 0x15 |
56493 | #define GDC1_BIF_VCN1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56494 | #define GDC1_BIF_VCN1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56495 | #define GDC1_BIF_VCN1_DOORBELL_RANGE__NEED_DEDUCT_MASK 0x00200000L |
56496 | //GDC1_BIF_SDMA4_DOORBELL_RANGE |
56497 | #define GDC1_BIF_SDMA4_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56498 | #define GDC1_BIF_SDMA4_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56499 | #define GDC1_BIF_SDMA4_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56500 | #define GDC1_BIF_SDMA4_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56501 | //GDC1_BIF_SDMA5_DOORBELL_RANGE |
56502 | #define GDC1_BIF_SDMA5_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56503 | #define GDC1_BIF_SDMA5_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56504 | #define GDC1_BIF_SDMA5_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56505 | #define GDC1_BIF_SDMA5_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56506 | //GDC1_BIF_CSDMA_DOORBELL_RANGE |
56507 | #define GDC1_BIF_CSDMA_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56508 | #define GDC1_BIF_CSDMA_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56509 | #define GDC1_BIF_CSDMA_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56510 | #define GDC1_BIF_CSDMA_DOORBELL_RANGE__SIZE_MASK 0x00FF0000L |
56511 | //GDC1_BIF_VPE_DOORBELL_RANGE |
56512 | #define GDC1_BIF_VPE_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
56513 | #define GDC1_BIF_VPE_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
56514 | #define GDC1_BIF_VPE_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
56515 | #define GDC1_BIF_VPE_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
56516 | //GDC1_ATDMA_MISC_CNTL |
56517 | #define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 |
56518 | #define GDC1_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 |
56519 | #define GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT 0x2 |
56520 | #define GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT 0x8 |
56521 | #define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 |
56522 | #define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 |
56523 | #define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L |
56524 | #define GDC1_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L |
56525 | #define GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK 0x0000000CL |
56526 | #define GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK 0x0000FF00L |
56527 | #define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L |
56528 | #define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L |
56529 | //GDC1_BIF_DOORBELL_FENCE_CNTL |
56530 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE__SHIFT 0x0 |
56531 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE__SHIFT 0x1 |
56532 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE__SHIFT 0x2 |
56533 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE__SHIFT 0x4 |
56534 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE__SHIFT 0x5 |
56535 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE__SHIFT 0x6 |
56536 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE__SHIFT 0x7 |
56537 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE__SHIFT 0x8 |
56538 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CSDMA_ENABLE__SHIFT 0x9 |
56539 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_VPE_ENABLE__SHIFT 0xa |
56540 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x10 |
56541 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE_MASK 0x00000001L |
56542 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE_MASK 0x00000002L |
56543 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE_MASK 0x00000004L |
56544 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE_MASK 0x00000010L |
56545 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE_MASK 0x00000020L |
56546 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE_MASK 0x00000040L |
56547 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE_MASK 0x00000080L |
56548 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE_MASK 0x00000100L |
56549 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CSDMA_ENABLE_MASK 0x00000200L |
56550 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_VPE_ENABLE_MASK 0x00000400L |
56551 | #define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00010000L |
56552 | //GDC1_S2A_MISC_CNTL |
56553 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0 |
56554 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1 |
56555 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2 |
56556 | #define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 |
56557 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS__SHIFT 0x5 |
56558 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_VPE_DIS__SHIFT 0x6 |
56559 | #define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8 |
56560 | #define GDC1_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa |
56561 | #define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc |
56562 | #define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10 |
56563 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS__SHIFT 0x18 |
56564 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS__SHIFT 0x19 |
56565 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS__SHIFT 0x1a |
56566 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS__SHIFT 0x1b |
56567 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CSDMA_DIS__SHIFT 0x1c |
56568 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L |
56569 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L |
56570 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L |
56571 | #define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L |
56572 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS_MASK 0x00000020L |
56573 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_VPE_DIS_MASK 0x00000040L |
56574 | #define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L |
56575 | #define GDC1_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L |
56576 | #define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L |
56577 | #define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L |
56578 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS_MASK 0x01000000L |
56579 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS_MASK 0x02000000L |
56580 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS_MASK 0x04000000L |
56581 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS_MASK 0x08000000L |
56582 | #define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CSDMA_DIS_MASK 0x10000000L |
56583 | |
56584 | |
56585 | // addressBlock: nbio_nbif0_bif_bx_SYSDEC |
56586 | //BIF_BX2_PCIE_INDEX |
56587 | #define BIF_BX2_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 |
56588 | #define BIF_BX2_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL |
56589 | //BIF_BX2_PCIE_DATA |
56590 | #define BIF_BX2_PCIE_DATA__PCIE_DATA__SHIFT 0x0 |
56591 | #define BIF_BX2_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL |
56592 | //BIF_BX2_PCIE_INDEX2 |
56593 | #define BIF_BX2_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 |
56594 | #define BIF_BX2_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL |
56595 | //BIF_BX2_PCIE_DATA2 |
56596 | #define BIF_BX2_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 |
56597 | #define BIF_BX2_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL |
56598 | //BIF_BX2_SBIOS_SCRATCH_0 |
56599 | #define BIF_BX2_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0 |
56600 | #define BIF_BX2_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
56601 | //BIF_BX2_SBIOS_SCRATCH_1 |
56602 | #define BIF_BX2_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0 |
56603 | #define BIF_BX2_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
56604 | //BIF_BX2_SBIOS_SCRATCH_2 |
56605 | #define BIF_BX2_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0 |
56606 | #define BIF_BX2_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
56607 | //BIF_BX2_SBIOS_SCRATCH_3 |
56608 | #define BIF_BX2_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0 |
56609 | #define BIF_BX2_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
56610 | //BIF_BX2_BIOS_SCRATCH_0 |
56611 | #define BIF_BX2_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 |
56612 | #define BIF_BX2_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL |
56613 | //BIF_BX2_BIOS_SCRATCH_1 |
56614 | #define BIF_BX2_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 |
56615 | #define BIF_BX2_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL |
56616 | //BIF_BX2_BIOS_SCRATCH_2 |
56617 | #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 |
56618 | #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL |
56619 | //BIF_BX2_BIOS_SCRATCH_3 |
56620 | #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 |
56621 | #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL |
56622 | //BIF_BX2_BIOS_SCRATCH_4 |
56623 | #define BIF_BX2_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 |
56624 | #define BIF_BX2_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL |
56625 | //BIF_BX2_BIOS_SCRATCH_5 |
56626 | #define BIF_BX2_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 |
56627 | #define BIF_BX2_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL |
56628 | //BIF_BX2_BIOS_SCRATCH_6 |
56629 | #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 |
56630 | #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL |
56631 | //BIF_BX2_BIOS_SCRATCH_7 |
56632 | #define BIF_BX2_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 |
56633 | #define BIF_BX2_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL |
56634 | //BIF_BX2_BIOS_SCRATCH_8 |
56635 | #define BIF_BX2_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 |
56636 | #define BIF_BX2_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL |
56637 | //BIF_BX2_BIOS_SCRATCH_9 |
56638 | #define BIF_BX2_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 |
56639 | #define BIF_BX2_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL |
56640 | //BIF_BX2_BIOS_SCRATCH_10 |
56641 | #define BIF_BX2_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 |
56642 | #define BIF_BX2_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL |
56643 | //BIF_BX2_BIOS_SCRATCH_11 |
56644 | #define BIF_BX2_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 |
56645 | #define BIF_BX2_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL |
56646 | //BIF_BX2_BIOS_SCRATCH_12 |
56647 | #define BIF_BX2_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 |
56648 | #define BIF_BX2_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL |
56649 | //BIF_BX2_BIOS_SCRATCH_13 |
56650 | #define BIF_BX2_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 |
56651 | #define BIF_BX2_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL |
56652 | //BIF_BX2_BIOS_SCRATCH_14 |
56653 | #define BIF_BX2_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 |
56654 | #define BIF_BX2_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL |
56655 | //BIF_BX2_BIOS_SCRATCH_15 |
56656 | #define BIF_BX2_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 |
56657 | #define BIF_BX2_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL |
56658 | //BIF_BX2_BIF_RLC_INTR_CNTL |
56659 | #define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0 |
56660 | #define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1 |
56661 | #define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2 |
56662 | #define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3 |
56663 | #define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L |
56664 | #define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L |
56665 | #define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L |
56666 | #define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L |
56667 | //BIF_BX2_BIF_VCE_INTR_CNTL |
56668 | #define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0 |
56669 | #define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1 |
56670 | #define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2 |
56671 | #define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3 |
56672 | #define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L |
56673 | #define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L |
56674 | #define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L |
56675 | #define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L |
56676 | //BIF_BX2_BIF_UVD_INTR_CNTL |
56677 | #define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0 |
56678 | #define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1 |
56679 | #define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2 |
56680 | #define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3 |
56681 | #define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_INST_SEL__SHIFT 0x1c |
56682 | #define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L |
56683 | #define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L |
56684 | #define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L |
56685 | #define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L |
56686 | #define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_INST_SEL_MASK 0xF0000000L |
56687 | //BIF_BX2_GFX_MMIOREG_CAM_ADDR0 |
56688 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 |
56689 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL |
56690 | //BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0 |
56691 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 |
56692 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL |
56693 | //BIF_BX2_GFX_MMIOREG_CAM_ADDR1 |
56694 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 |
56695 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL |
56696 | //BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1 |
56697 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 |
56698 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL |
56699 | //BIF_BX2_GFX_MMIOREG_CAM_ADDR2 |
56700 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 |
56701 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL |
56702 | //BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2 |
56703 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 |
56704 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL |
56705 | //BIF_BX2_GFX_MMIOREG_CAM_ADDR3 |
56706 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 |
56707 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL |
56708 | //BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3 |
56709 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 |
56710 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL |
56711 | //BIF_BX2_GFX_MMIOREG_CAM_ADDR4 |
56712 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 |
56713 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL |
56714 | //BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4 |
56715 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 |
56716 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL |
56717 | //BIF_BX2_GFX_MMIOREG_CAM_ADDR5 |
56718 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 |
56719 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL |
56720 | //BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5 |
56721 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 |
56722 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL |
56723 | //BIF_BX2_GFX_MMIOREG_CAM_ADDR6 |
56724 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 |
56725 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL |
56726 | //BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6 |
56727 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 |
56728 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL |
56729 | //BIF_BX2_GFX_MMIOREG_CAM_ADDR7 |
56730 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 |
56731 | #define BIF_BX2_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL |
56732 | //BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7 |
56733 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 |
56734 | #define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL |
56735 | //BIF_BX2_GFX_MMIOREG_CAM_CNTL |
56736 | #define BIF_BX2_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 |
56737 | #define BIF_BX2_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL |
56738 | //BIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL |
56739 | #define BIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 |
56740 | #define BIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL |
56741 | //BIF_BX2_GFX_MMIOREG_CAM_ONE_CPL |
56742 | #define BIF_BX2_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 |
56743 | #define BIF_BX2_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL |
56744 | //BIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL |
56745 | #define BIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 |
56746 | #define BIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL |
56747 | |
56748 | |
56749 | // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 |
56750 | //RCC_DWN_DEV0_3_DN_PCIE_RESERVED |
56751 | #define RCC_DWN_DEV0_3_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
56752 | #define RCC_DWN_DEV0_3_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL |
56753 | //RCC_DWN_DEV0_3_DN_PCIE_SCRATCH |
56754 | #define RCC_DWN_DEV0_3_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
56755 | #define RCC_DWN_DEV0_3_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
56756 | //RCC_DWN_DEV0_3_DN_PCIE_CNTL |
56757 | #define RCC_DWN_DEV0_3_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
56758 | #define RCC_DWN_DEV0_3_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 |
56759 | #define RCC_DWN_DEV0_3_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
56760 | #define RCC_DWN_DEV0_3_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
56761 | #define RCC_DWN_DEV0_3_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L |
56762 | #define RCC_DWN_DEV0_3_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
56763 | //RCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL |
56764 | #define RCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
56765 | #define RCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
56766 | //RCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2 |
56767 | #define RCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
56768 | #define RCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
56769 | //RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL |
56770 | #define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
56771 | #define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 |
56772 | #define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
56773 | #define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L |
56774 | //RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL |
56775 | #define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
56776 | #define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
56777 | #define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
56778 | #define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
56779 | #define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 |
56780 | #define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
56781 | #define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
56782 | #define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
56783 | #define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
56784 | #define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L |
56785 | |
56786 | |
56787 | // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 |
56788 | //RCC_DWNP_DEV0_3_PCIE_ERR_CNTL |
56789 | #define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
56790 | #define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
56791 | #define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 |
56792 | #define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 |
56793 | #define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 |
56794 | #define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
56795 | #define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
56796 | #define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L |
56797 | #define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L |
56798 | #define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L |
56799 | //RCC_DWNP_DEV0_3_PCIE_RX_CNTL |
56800 | #define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
56801 | #define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 |
56802 | #define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
56803 | #define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 |
56804 | #define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
56805 | #define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
56806 | #define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L |
56807 | #define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
56808 | #define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L |
56809 | #define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
56810 | //RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL |
56811 | //RCC_DWNP_DEV0_3_PCIE_LC_CNTL2 |
56812 | #define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 |
56813 | #define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
56814 | #define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L |
56815 | #define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
56816 | //RCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP |
56817 | #define RCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 |
56818 | #define RCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL |
56819 | |
56820 | |
56821 | // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 |
56822 | //RCC_EP_DEV0_3_EP_PCIE_SCRATCH |
56823 | #define RCC_EP_DEV0_3_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
56824 | #define RCC_EP_DEV0_3_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
56825 | //RCC_EP_DEV0_3_EP_PCIE_CNTL |
56826 | #define RCC_EP_DEV0_3_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
56827 | #define RCC_EP_DEV0_3_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
56828 | #define RCC_EP_DEV0_3_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
56829 | #define RCC_EP_DEV0_3_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
56830 | #define RCC_EP_DEV0_3_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
56831 | #define RCC_EP_DEV0_3_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
56832 | //RCC_EP_DEV0_3_EP_PCIE_INT_CNTL |
56833 | #define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 |
56834 | #define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 |
56835 | #define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 |
56836 | #define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 |
56837 | #define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 |
56838 | #define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 |
56839 | #define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L |
56840 | #define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L |
56841 | #define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L |
56842 | #define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L |
56843 | #define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L |
56844 | #define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L |
56845 | //RCC_EP_DEV0_3_EP_PCIE_INT_STATUS |
56846 | #define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 |
56847 | #define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 |
56848 | #define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 |
56849 | #define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 |
56850 | #define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 |
56851 | #define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 |
56852 | #define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 |
56853 | #define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L |
56854 | #define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L |
56855 | #define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L |
56856 | #define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L |
56857 | #define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L |
56858 | #define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L |
56859 | #define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L |
56860 | //RCC_EP_DEV0_3_EP_PCIE_RX_CNTL2 |
56861 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
56862 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
56863 | //RCC_EP_DEV0_3_EP_PCIE_BUS_CNTL |
56864 | #define RCC_EP_DEV0_3_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
56865 | #define RCC_EP_DEV0_3_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
56866 | //RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL |
56867 | #define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
56868 | #define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
56869 | #define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
56870 | #define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
56871 | #define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 |
56872 | #define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
56873 | #define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
56874 | #define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
56875 | #define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
56876 | #define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L |
56877 | //RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL |
56878 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 |
56879 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 |
56880 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 |
56881 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 |
56882 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa |
56883 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd |
56884 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe |
56885 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf |
56886 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 |
56887 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 |
56888 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L |
56889 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L |
56890 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L |
56891 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L |
56892 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L |
56893 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L |
56894 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L |
56895 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L |
56896 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L |
56897 | #define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L |
56898 | //RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 |
56899 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56900 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56901 | //RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 |
56902 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56903 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56904 | //RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 |
56905 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56906 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56907 | //RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 |
56908 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56909 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56910 | //RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 |
56911 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56912 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56913 | //RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 |
56914 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56915 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56916 | //RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 |
56917 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56918 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56919 | //RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 |
56920 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56921 | #define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56922 | //RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP |
56923 | #define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
56924 | #define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
56925 | #define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
56926 | #define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
56927 | #define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
56928 | #define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
56929 | #define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
56930 | #define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
56931 | //RCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR |
56932 | #define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
56933 | #define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
56934 | //RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL |
56935 | #define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 |
56936 | #define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 |
56937 | #define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL |
56938 | #define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L |
56939 | //RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 |
56940 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56941 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56942 | //RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 |
56943 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56944 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56945 | //RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 |
56946 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56947 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56948 | //RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 |
56949 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56950 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56951 | //RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 |
56952 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56953 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56954 | //RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 |
56955 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56956 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56957 | //RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 |
56958 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56959 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56960 | //RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 |
56961 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
56962 | #define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
56963 | //RCC_EP_DEV0_3_EP_PCIE_PME_CONTROL |
56964 | #define RCC_EP_DEV0_3_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 |
56965 | #define RCC_EP_DEV0_3_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL |
56966 | //RCC_EP_DEV0_3_EP_PCIEP_RESERVED |
56967 | #define RCC_EP_DEV0_3_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
56968 | #define RCC_EP_DEV0_3_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
56969 | //RCC_EP_DEV0_3_EP_PCIE_TX_CNTL |
56970 | #define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
56971 | #define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
56972 | #define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 |
56973 | #define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 |
56974 | #define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a |
56975 | #define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
56976 | #define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
56977 | #define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L |
56978 | #define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L |
56979 | #define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L |
56980 | //RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID |
56981 | #define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
56982 | #define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
56983 | #define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
56984 | #define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
56985 | #define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
56986 | #define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
56987 | //RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL |
56988 | #define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
56989 | #define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
56990 | #define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
56991 | #define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
56992 | //RCC_EP_DEV0_3_EP_PCIE_RX_CNTL |
56993 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
56994 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
56995 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
56996 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
56997 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
56998 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
56999 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
57000 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
57001 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
57002 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
57003 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
57004 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
57005 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
57006 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
57007 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
57008 | #define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
57009 | //RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL |
57010 | |
57011 | |
57012 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC |
57013 | //BIF_BX_PF2_MM_INDEX |
57014 | #define BIF_BX_PF2_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
57015 | #define BIF_BX_PF2_MM_INDEX__MM_APER__SHIFT 0x1f |
57016 | #define BIF_BX_PF2_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
57017 | #define BIF_BX_PF2_MM_INDEX__MM_APER_MASK 0x80000000L |
57018 | //BIF_BX_PF2_MM_DATA |
57019 | #define BIF_BX_PF2_MM_DATA__MM_DATA__SHIFT 0x0 |
57020 | #define BIF_BX_PF2_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
57021 | //BIF_BX_PF2_MM_INDEX_HI |
57022 | #define BIF_BX_PF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
57023 | #define BIF_BX_PF2_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
57024 | |
57025 | |
57026 | // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 |
57027 | //BIF_BX2_BIF_MM_INDACCESS_CNTL |
57028 | #define BIF_BX2_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 |
57029 | #define BIF_BX2_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L |
57030 | //BIF_BX2_BUS_CNTL |
57031 | #define BIF_BX2_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 |
57032 | #define BIF_BX2_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 |
57033 | #define BIF_BX2_BUS_CNTL__SET_AZ_TC__SHIFT 0xa |
57034 | #define BIF_BX2_BUS_CNTL__SET_MC_TC__SHIFT 0xd |
57035 | #define BIF_BX2_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 |
57036 | #define BIF_BX2_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 |
57037 | #define BIF_BX2_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 |
57038 | #define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18 |
57039 | #define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 |
57040 | #define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a |
57041 | #define BIF_BX2_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b |
57042 | #define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c |
57043 | #define BIF_BX2_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d |
57044 | #define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e |
57045 | #define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f |
57046 | #define BIF_BX2_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L |
57047 | #define BIF_BX2_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L |
57048 | #define BIF_BX2_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L |
57049 | #define BIF_BX2_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L |
57050 | #define BIF_BX2_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L |
57051 | #define BIF_BX2_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L |
57052 | #define BIF_BX2_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L |
57053 | #define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L |
57054 | #define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L |
57055 | #define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L |
57056 | #define BIF_BX2_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L |
57057 | #define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L |
57058 | #define BIF_BX2_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L |
57059 | #define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L |
57060 | #define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L |
57061 | //BIF_BX2_BIF_SCRATCH0 |
57062 | #define BIF_BX2_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 |
57063 | #define BIF_BX2_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL |
57064 | //BIF_BX2_BIF_SCRATCH1 |
57065 | #define BIF_BX2_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 |
57066 | #define BIF_BX2_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL |
57067 | //BIF_BX2_BX_RESET_EN |
57068 | #define BIF_BX2_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 |
57069 | #define BIF_BX2_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L |
57070 | //BIF_BX2_MM_CFGREGS_CNTL |
57071 | #define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 |
57072 | #define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 |
57073 | #define BIF_BX2_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f |
57074 | #define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L |
57075 | #define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L |
57076 | #define BIF_BX2_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L |
57077 | //BIF_BX2_BX_RESET_CNTL |
57078 | #define BIF_BX2_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 |
57079 | #define BIF_BX2_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L |
57080 | //BIF_BX2_INTERRUPT_CNTL |
57081 | #define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 |
57082 | #define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 |
57083 | #define BIF_BX2_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 |
57084 | #define BIF_BX2_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 |
57085 | #define BIF_BX2_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 |
57086 | #define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf |
57087 | #define BIF_BX2_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 |
57088 | #define BIF_BX2_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 |
57089 | #define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12 |
57090 | #define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L |
57091 | #define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L |
57092 | #define BIF_BX2_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L |
57093 | #define BIF_BX2_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L |
57094 | #define BIF_BX2_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L |
57095 | #define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L |
57096 | #define BIF_BX2_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L |
57097 | #define BIF_BX2_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L |
57098 | #define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L |
57099 | //BIF_BX2_INTERRUPT_CNTL2 |
57100 | #define BIF_BX2_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 |
57101 | #define BIF_BX2_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL |
57102 | //BIF_BX2_CLKREQB_PAD_CNTL |
57103 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 |
57104 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 |
57105 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 |
57106 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 |
57107 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 |
57108 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 |
57109 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 |
57110 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 |
57111 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 |
57112 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa |
57113 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb |
57114 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc |
57115 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd |
57116 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L |
57117 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L |
57118 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L |
57119 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L |
57120 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L |
57121 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L |
57122 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L |
57123 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L |
57124 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L |
57125 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L |
57126 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L |
57127 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L |
57128 | #define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L |
57129 | //BIF_BX2_BIF_FEATURES_CONTROL_MISC |
57130 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 |
57131 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 |
57132 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 |
57133 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 |
57134 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb |
57135 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc |
57136 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd |
57137 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf |
57138 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10 |
57139 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18 |
57140 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L |
57141 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L |
57142 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L |
57143 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L |
57144 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L |
57145 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L |
57146 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L |
57147 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L |
57148 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x00FF0000L |
57149 | #define BIF_BX2_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L |
57150 | //BIF_BX2_HDP_ATOMIC_CONTROL_MISC |
57151 | #define BIF_BX2_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0 |
57152 | #define BIF_BX2_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL |
57153 | //BIF_BX2_BIF_DOORBELL_CNTL |
57154 | #define BIF_BX2_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 |
57155 | #define BIF_BX2_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 |
57156 | #define BIF_BX2_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 |
57157 | #define BIF_BX2_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 |
57158 | #define BIF_BX2_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 |
57159 | #define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 |
57160 | #define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 |
57161 | #define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a |
57162 | #define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b |
57163 | #define BIF_BX2_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L |
57164 | #define BIF_BX2_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L |
57165 | #define BIF_BX2_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L |
57166 | #define BIF_BX2_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L |
57167 | #define BIF_BX2_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L |
57168 | #define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L |
57169 | #define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L |
57170 | #define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L |
57171 | #define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L |
57172 | //BIF_BX2_BIF_DOORBELL_INT_CNTL |
57173 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 |
57174 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 |
57175 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 |
57176 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 |
57177 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 |
57178 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 |
57179 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 |
57180 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19 |
57181 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a |
57182 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c |
57183 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d |
57184 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e |
57185 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f |
57186 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L |
57187 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L |
57188 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L |
57189 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L |
57190 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L |
57191 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L |
57192 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L |
57193 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L |
57194 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L |
57195 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L |
57196 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L |
57197 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L |
57198 | #define BIF_BX2_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L |
57199 | //BIF_BX2_BIF_FB_EN |
57200 | #define BIF_BX2_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 |
57201 | #define BIF_BX2_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 |
57202 | #define BIF_BX2_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L |
57203 | #define BIF_BX2_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L |
57204 | //BIF_BX2_BIF_INTR_CNTL |
57205 | #define BIF_BX2_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 |
57206 | #define BIF_BX2_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L |
57207 | //BIF_BX2_BIF_MST_TRANS_PENDING_VF |
57208 | #define BIF_BX2_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
57209 | #define BIF_BX2_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL |
57210 | //BIF_BX2_BIF_SLV_TRANS_PENDING_VF |
57211 | #define BIF_BX2_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 |
57212 | #define BIF_BX2_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL |
57213 | //BIF_BX2_BACO_CNTL |
57214 | #define BIF_BX2_BACO_CNTL__BACO_EN__SHIFT 0x0 |
57215 | #define BIF_BX2_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1 |
57216 | #define BIF_BX2_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 |
57217 | #define BIF_BX2_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 |
57218 | #define BIF_BX2_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 |
57219 | #define BIF_BX2_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 |
57220 | #define BIF_BX2_BACO_CNTL__BACO_MODE__SHIFT 0x8 |
57221 | #define BIF_BX2_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 |
57222 | #define BIF_BX2_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f |
57223 | #define BIF_BX2_BACO_CNTL__BACO_EN_MASK 0x00000001L |
57224 | #define BIF_BX2_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L |
57225 | #define BIF_BX2_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L |
57226 | #define BIF_BX2_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L |
57227 | #define BIF_BX2_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L |
57228 | #define BIF_BX2_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L |
57229 | #define BIF_BX2_BACO_CNTL__BACO_MODE_MASK 0x00000100L |
57230 | #define BIF_BX2_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L |
57231 | #define BIF_BX2_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L |
57232 | //BIF_BX2_BIF_BACO_EXIT_TIME0 |
57233 | #define BIF_BX2_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 |
57234 | #define BIF_BX2_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL |
57235 | //BIF_BX2_BIF_BACO_EXIT_TIMER1 |
57236 | #define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 |
57237 | #define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 |
57238 | #define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a |
57239 | #define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b |
57240 | #define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c |
57241 | #define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d |
57242 | #define BIF_BX2_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f |
57243 | #define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL |
57244 | #define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L |
57245 | #define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L |
57246 | #define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L |
57247 | #define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L |
57248 | #define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L |
57249 | #define BIF_BX2_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L |
57250 | //BIF_BX2_BIF_BACO_EXIT_TIMER2 |
57251 | #define BIF_BX2_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 |
57252 | #define BIF_BX2_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL |
57253 | //BIF_BX2_BIF_BACO_EXIT_TIMER3 |
57254 | #define BIF_BX2_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 |
57255 | #define BIF_BX2_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL |
57256 | //BIF_BX2_BIF_BACO_EXIT_TIMER4 |
57257 | #define BIF_BX2_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 |
57258 | #define BIF_BX2_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL |
57259 | //BIF_BX2_MEM_TYPE_CNTL |
57260 | #define BIF_BX2_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 |
57261 | #define BIF_BX2_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L |
57262 | //BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL |
57263 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0 |
57264 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1 |
57265 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8 |
57266 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L |
57267 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L |
57268 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L |
57269 | //BIF_BX2_NBIF_GFX_ADDR_LUT_0 |
57270 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0 |
57271 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL |
57272 | //BIF_BX2_NBIF_GFX_ADDR_LUT_1 |
57273 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0 |
57274 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL |
57275 | //BIF_BX2_NBIF_GFX_ADDR_LUT_2 |
57276 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0 |
57277 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL |
57278 | //BIF_BX2_NBIF_GFX_ADDR_LUT_3 |
57279 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0 |
57280 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL |
57281 | //BIF_BX2_NBIF_GFX_ADDR_LUT_4 |
57282 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0 |
57283 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL |
57284 | //BIF_BX2_NBIF_GFX_ADDR_LUT_5 |
57285 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0 |
57286 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL |
57287 | //BIF_BX2_NBIF_GFX_ADDR_LUT_6 |
57288 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0 |
57289 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL |
57290 | //BIF_BX2_NBIF_GFX_ADDR_LUT_7 |
57291 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0 |
57292 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL |
57293 | //BIF_BX2_NBIF_GFX_ADDR_LUT_8 |
57294 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0 |
57295 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL |
57296 | //BIF_BX2_NBIF_GFX_ADDR_LUT_9 |
57297 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0 |
57298 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL |
57299 | //BIF_BX2_NBIF_GFX_ADDR_LUT_10 |
57300 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0 |
57301 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL |
57302 | //BIF_BX2_NBIF_GFX_ADDR_LUT_11 |
57303 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0 |
57304 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL |
57305 | //BIF_BX2_NBIF_GFX_ADDR_LUT_12 |
57306 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0 |
57307 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL |
57308 | //BIF_BX2_NBIF_GFX_ADDR_LUT_13 |
57309 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0 |
57310 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL |
57311 | //BIF_BX2_NBIF_GFX_ADDR_LUT_14 |
57312 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0 |
57313 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL |
57314 | //BIF_BX2_NBIF_GFX_ADDR_LUT_15 |
57315 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0 |
57316 | #define BIF_BX2_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL |
57317 | //BIF_BX2_GFX_RST_CNTL |
57318 | #define BIF_BX2_GFX_RST_CNTL__GFX_RST_FINISH_INDICATION__SHIFT 0x0 |
57319 | #define BIF_BX2_GFX_RST_CNTL__GFX_RST_FINISH_INDICATION_MASK 0x00000001L |
57320 | //BIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL |
57321 | #define BIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
57322 | #define BIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL |
57323 | //BIF_BX2_REMAP_HDP_REG_FLUSH_CNTL |
57324 | #define BIF_BX2_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
57325 | #define BIF_BX2_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL |
57326 | //BIF_BX2_BIF_RB_CNTL |
57327 | #define BIF_BX2_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
57328 | #define BIF_BX2_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 |
57329 | #define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 |
57330 | #define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 |
57331 | #define BIF_BX2_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 |
57332 | #define BIF_BX2_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a |
57333 | #define BIF_BX2_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d |
57334 | #define BIF_BX2_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e |
57335 | #define BIF_BX2_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f |
57336 | #define BIF_BX2_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
57337 | #define BIF_BX2_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
57338 | #define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L |
57339 | #define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L |
57340 | #define BIF_BX2_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L |
57341 | #define BIF_BX2_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L |
57342 | #define BIF_BX2_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L |
57343 | #define BIF_BX2_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L |
57344 | #define BIF_BX2_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L |
57345 | //BIF_BX2_BIF_RB_BASE |
57346 | #define BIF_BX2_BIF_RB_BASE__ADDR__SHIFT 0x0 |
57347 | #define BIF_BX2_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
57348 | //BIF_BX2_BIF_RB_RPTR |
57349 | #define BIF_BX2_BIF_RB_RPTR__OFFSET__SHIFT 0x2 |
57350 | #define BIF_BX2_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL |
57351 | //BIF_BX2_BIF_RB_WPTR |
57352 | #define BIF_BX2_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 |
57353 | #define BIF_BX2_BIF_RB_WPTR__OFFSET__SHIFT 0x2 |
57354 | #define BIF_BX2_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L |
57355 | #define BIF_BX2_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL |
57356 | //BIF_BX2_BIF_RB_WPTR_ADDR_HI |
57357 | #define BIF_BX2_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 |
57358 | #define BIF_BX2_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL |
57359 | //BIF_BX2_BIF_RB_WPTR_ADDR_LO |
57360 | #define BIF_BX2_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 |
57361 | #define BIF_BX2_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
57362 | //BIF_BX2_MAILBOX_INDEX |
57363 | #define BIF_BX2_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 |
57364 | #define BIF_BX2_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL |
57365 | //BIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE |
57366 | #define BIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 |
57367 | #define BIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL |
57368 | //BIF_BX2_BIF_PERSTB_PAD_CNTL |
57369 | #define BIF_BX2_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 |
57370 | #define BIF_BX2_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL |
57371 | //BIF_BX2_BIF_PX_EN_PAD_CNTL |
57372 | #define BIF_BX2_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 |
57373 | #define BIF_BX2_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL |
57374 | //BIF_BX2_BIF_REFPADKIN_PAD_CNTL |
57375 | #define BIF_BX2_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 |
57376 | #define BIF_BX2_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL |
57377 | //BIF_BX2_BIF_CLKREQB_PAD_CNTL |
57378 | #define BIF_BX2_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 |
57379 | #define BIF_BX2_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL |
57380 | //BIF_BX2_BIF_PWRBRK_PAD_CNTL |
57381 | #define BIF_BX2_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0 |
57382 | #define BIF_BX2_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL |
57383 | |
57384 | |
57385 | // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 |
57386 | //RCC_STRAP3_RCC_DEV0_EPF0_STRAP0 |
57387 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 |
57388 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 |
57389 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 |
57390 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 |
57391 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c |
57392 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d |
57393 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e |
57394 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f |
57395 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL |
57396 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L |
57397 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L |
57398 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L |
57399 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L |
57400 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L |
57401 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L |
57402 | #define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L |
57403 | |
57404 | |
57405 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 |
57406 | //BIF_BX_PF2_BIF_BME_STATUS |
57407 | #define BIF_BX_PF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
57408 | #define BIF_BX_PF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
57409 | #define BIF_BX_PF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
57410 | #define BIF_BX_PF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
57411 | //BIF_BX_PF2_BIF_ATOMIC_ERR_LOG |
57412 | //BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
57413 | #define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
57414 | #define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
57415 | //BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
57416 | #define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
57417 | #define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
57418 | //BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL |
57419 | #define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
57420 | #define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
57421 | #define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
57422 | #define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
57423 | #define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
57424 | #define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
57425 | //BIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL |
57426 | #define BIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
57427 | #define BIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
57428 | //BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL |
57429 | #define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
57430 | #define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
57431 | //BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL |
57432 | #define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 |
57433 | #define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L |
57434 | //BIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL |
57435 | #define BIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 |
57436 | #define BIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L |
57437 | //BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ |
57438 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP0__SHIFT 0x0 |
57439 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP1__SHIFT 0x1 |
57440 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP2__SHIFT 0x2 |
57441 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP3__SHIFT 0x3 |
57442 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP4__SHIFT 0x4 |
57443 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP5__SHIFT 0x5 |
57444 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP6__SHIFT 0x6 |
57445 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP7__SHIFT 0x7 |
57446 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP8__SHIFT 0x8 |
57447 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP9__SHIFT 0x9 |
57448 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA0__SHIFT 0xa |
57449 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA1__SHIFT 0xb |
57450 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0__SHIFT 0xc |
57451 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1__SHIFT 0xd |
57452 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2__SHIFT 0xe |
57453 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3__SHIFT 0xf |
57454 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4__SHIFT 0x10 |
57455 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5__SHIFT 0x11 |
57456 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6__SHIFT 0x12 |
57457 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7__SHIFT 0x13 |
57458 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8__SHIFT 0x14 |
57459 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9__SHIFT 0x15 |
57460 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10__SHIFT 0x16 |
57461 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11__SHIFT 0x17 |
57462 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12__SHIFT 0x18 |
57463 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13__SHIFT 0x19 |
57464 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14__SHIFT 0x1a |
57465 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15__SHIFT 0x1b |
57466 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16__SHIFT 0x1c |
57467 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17__SHIFT 0x1d |
57468 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18__SHIFT 0x1e |
57469 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19__SHIFT 0x1f |
57470 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP0_MASK 0x00000001L |
57471 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP1_MASK 0x00000002L |
57472 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP2_MASK 0x00000004L |
57473 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP3_MASK 0x00000008L |
57474 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP4_MASK 0x00000010L |
57475 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP5_MASK 0x00000020L |
57476 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP6_MASK 0x00000040L |
57477 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP7_MASK 0x00000080L |
57478 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP8_MASK 0x00000100L |
57479 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP9_MASK 0x00000200L |
57480 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA0_MASK 0x00000400L |
57481 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA1_MASK 0x00000800L |
57482 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0_MASK 0x00001000L |
57483 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1_MASK 0x00002000L |
57484 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2_MASK 0x00004000L |
57485 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3_MASK 0x00008000L |
57486 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4_MASK 0x00010000L |
57487 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5_MASK 0x00020000L |
57488 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6_MASK 0x00040000L |
57489 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7_MASK 0x00080000L |
57490 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8_MASK 0x00100000L |
57491 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9_MASK 0x00200000L |
57492 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10_MASK 0x00400000L |
57493 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11_MASK 0x00800000L |
57494 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12_MASK 0x01000000L |
57495 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13_MASK 0x02000000L |
57496 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14_MASK 0x04000000L |
57497 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15_MASK 0x08000000L |
57498 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16_MASK 0x10000000L |
57499 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17_MASK 0x20000000L |
57500 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18_MASK 0x40000000L |
57501 | #define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19_MASK 0x80000000L |
57502 | //BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ |
57503 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP0__SHIFT 0x0 |
57504 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP1__SHIFT 0x1 |
57505 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP2__SHIFT 0x2 |
57506 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP3__SHIFT 0x3 |
57507 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP4__SHIFT 0x4 |
57508 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP5__SHIFT 0x5 |
57509 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP6__SHIFT 0x6 |
57510 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP7__SHIFT 0x7 |
57511 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP8__SHIFT 0x8 |
57512 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP9__SHIFT 0x9 |
57513 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0__SHIFT 0xa |
57514 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1__SHIFT 0xb |
57515 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0__SHIFT 0xc |
57516 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1__SHIFT 0xd |
57517 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2__SHIFT 0xe |
57518 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3__SHIFT 0xf |
57519 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4__SHIFT 0x10 |
57520 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5__SHIFT 0x11 |
57521 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6__SHIFT 0x12 |
57522 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7__SHIFT 0x13 |
57523 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8__SHIFT 0x14 |
57524 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9__SHIFT 0x15 |
57525 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10__SHIFT 0x16 |
57526 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11__SHIFT 0x17 |
57527 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12__SHIFT 0x18 |
57528 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13__SHIFT 0x19 |
57529 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14__SHIFT 0x1a |
57530 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15__SHIFT 0x1b |
57531 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16__SHIFT 0x1c |
57532 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17__SHIFT 0x1d |
57533 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18__SHIFT 0x1e |
57534 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19__SHIFT 0x1f |
57535 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP0_MASK 0x00000001L |
57536 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP1_MASK 0x00000002L |
57537 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP2_MASK 0x00000004L |
57538 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP3_MASK 0x00000008L |
57539 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP4_MASK 0x00000010L |
57540 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP5_MASK 0x00000020L |
57541 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP6_MASK 0x00000040L |
57542 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP7_MASK 0x00000080L |
57543 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP8_MASK 0x00000100L |
57544 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP9_MASK 0x00000200L |
57545 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0_MASK 0x00000400L |
57546 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1_MASK 0x00000800L |
57547 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0_MASK 0x00001000L |
57548 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1_MASK 0x00002000L |
57549 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2_MASK 0x00004000L |
57550 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3_MASK 0x00008000L |
57551 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4_MASK 0x00010000L |
57552 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5_MASK 0x00020000L |
57553 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6_MASK 0x00040000L |
57554 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7_MASK 0x00080000L |
57555 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8_MASK 0x00100000L |
57556 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9_MASK 0x00200000L |
57557 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10_MASK 0x00400000L |
57558 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11_MASK 0x00800000L |
57559 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12_MASK 0x01000000L |
57560 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13_MASK 0x02000000L |
57561 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14_MASK 0x04000000L |
57562 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15_MASK 0x08000000L |
57563 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16_MASK 0x10000000L |
57564 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17_MASK 0x20000000L |
57565 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18_MASK 0x40000000L |
57566 | #define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19_MASK 0x80000000L |
57567 | //BIF_BX_PF2_GPU_HDP_FLUSH_REQ |
57568 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
57569 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
57570 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
57571 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
57572 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
57573 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
57574 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
57575 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
57576 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
57577 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
57578 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
57579 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
57580 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc |
57581 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd |
57582 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe |
57583 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf |
57584 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 |
57585 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 |
57586 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 |
57587 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 |
57588 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 |
57589 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 |
57590 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 |
57591 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 |
57592 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 |
57593 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 |
57594 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a |
57595 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b |
57596 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c |
57597 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d |
57598 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e |
57599 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f |
57600 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
57601 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
57602 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
57603 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
57604 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
57605 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
57606 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
57607 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
57608 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
57609 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
57610 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
57611 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
57612 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L |
57613 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L |
57614 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L |
57615 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L |
57616 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L |
57617 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L |
57618 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L |
57619 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L |
57620 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L |
57621 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L |
57622 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L |
57623 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L |
57624 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L |
57625 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L |
57626 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L |
57627 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L |
57628 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L |
57629 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L |
57630 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L |
57631 | #define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L |
57632 | //BIF_BX_PF2_GPU_HDP_FLUSH_DONE |
57633 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
57634 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
57635 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
57636 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
57637 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
57638 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
57639 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
57640 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
57641 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
57642 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
57643 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
57644 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
57645 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc |
57646 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd |
57647 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe |
57648 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf |
57649 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 |
57650 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 |
57651 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 |
57652 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 |
57653 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 |
57654 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 |
57655 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 |
57656 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 |
57657 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 |
57658 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 |
57659 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a |
57660 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b |
57661 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c |
57662 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d |
57663 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e |
57664 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f |
57665 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
57666 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
57667 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
57668 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
57669 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
57670 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
57671 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
57672 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
57673 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
57674 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
57675 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
57676 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
57677 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L |
57678 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L |
57679 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L |
57680 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L |
57681 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L |
57682 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L |
57683 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L |
57684 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L |
57685 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L |
57686 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L |
57687 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L |
57688 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L |
57689 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L |
57690 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L |
57691 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L |
57692 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L |
57693 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L |
57694 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L |
57695 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L |
57696 | #define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L |
57697 | //BIF_BX_PF2_BIF_TRANS_PENDING |
57698 | #define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
57699 | #define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
57700 | #define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
57701 | #define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
57702 | //BIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS |
57703 | #define BIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
57704 | #define BIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
57705 | //BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0 |
57706 | #define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
57707 | #define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
57708 | //BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1 |
57709 | #define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
57710 | #define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
57711 | //BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2 |
57712 | #define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
57713 | #define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
57714 | //BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3 |
57715 | #define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
57716 | #define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
57717 | //BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0 |
57718 | #define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
57719 | #define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
57720 | //BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1 |
57721 | #define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
57722 | #define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
57723 | //BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2 |
57724 | #define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
57725 | #define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
57726 | //BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3 |
57727 | #define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
57728 | #define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
57729 | //BIF_BX_PF2_MAILBOX_CONTROL |
57730 | #define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
57731 | #define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
57732 | #define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
57733 | #define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
57734 | #define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
57735 | #define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
57736 | #define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
57737 | #define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
57738 | //BIF_BX_PF2_MAILBOX_INT_CNTL |
57739 | #define BIF_BX_PF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
57740 | #define BIF_BX_PF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
57741 | #define BIF_BX_PF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
57742 | #define BIF_BX_PF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
57743 | //BIF_BX_PF2_BIF_VMHV_MAILBOX |
57744 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
57745 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
57746 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
57747 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
57748 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
57749 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
57750 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
57751 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
57752 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
57753 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
57754 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
57755 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
57756 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
57757 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
57758 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
57759 | #define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
57760 | |
57761 | |
57762 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] |
57763 | //RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN |
57764 | #define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
57765 | #define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
57766 | //RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE |
57767 | #define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
57768 | #define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
57769 | |
57770 | |
57771 | // addressBlock: nbio_nbif0_gdc_GDCDEC |
57772 | //GDC2_A2S_QUEUE_FIFO_ARB_CNTL |
57773 | #define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT 0x0 |
57774 | #define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT 0x8 |
57775 | #define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE__SHIFT 0x10 |
57776 | #define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE__SHIFT 0x11 |
57777 | #define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY_MASK 0x000000FFL |
57778 | #define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY_MASK 0x0000FF00L |
57779 | #define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE_MASK 0x00010000L |
57780 | #define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE_MASK 0x00020000L |
57781 | //GDC2_NBIF_GFX_DOORBELL_STATUS |
57782 | #define GDC2_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0 |
57783 | #define GDC2_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x00000001L |
57784 | //GDC2_BIF_SDMA0_DOORBELL_RANGE |
57785 | #define GDC2_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
57786 | #define GDC2_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
57787 | #define GDC2_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
57788 | #define GDC2_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
57789 | //GDC2_BIF_SDMA1_DOORBELL_RANGE |
57790 | #define GDC2_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
57791 | #define GDC2_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
57792 | #define GDC2_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
57793 | #define GDC2_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
57794 | //GDC2_BIF_IH_DOORBELL_RANGE |
57795 | #define GDC2_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
57796 | #define GDC2_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
57797 | #define GDC2_BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
57798 | #define GDC2_BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
57799 | //GDC2_BIF_VCN0_DOORBELL_RANGE |
57800 | #define GDC2_BIF_VCN0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
57801 | #define GDC2_BIF_VCN0_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
57802 | #define GDC2_BIF_VCN0_DOORBELL_RANGE__NEED_DEDUCT__SHIFT 0x15 |
57803 | #define GDC2_BIF_VCN0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
57804 | #define GDC2_BIF_VCN0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
57805 | #define GDC2_BIF_VCN0_DOORBELL_RANGE__NEED_DEDUCT_MASK 0x00200000L |
57806 | //GDC2_BIF_RLC_DOORBELL_RANGE |
57807 | #define GDC2_BIF_RLC_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
57808 | #define GDC2_BIF_RLC_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
57809 | #define GDC2_BIF_RLC_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
57810 | #define GDC2_BIF_RLC_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
57811 | //GDC2_BIF_SDMA2_DOORBELL_RANGE |
57812 | #define GDC2_BIF_SDMA2_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
57813 | #define GDC2_BIF_SDMA2_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
57814 | #define GDC2_BIF_SDMA2_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
57815 | #define GDC2_BIF_SDMA2_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
57816 | //GDC2_BIF_SDMA3_DOORBELL_RANGE |
57817 | #define GDC2_BIF_SDMA3_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
57818 | #define GDC2_BIF_SDMA3_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
57819 | #define GDC2_BIF_SDMA3_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
57820 | #define GDC2_BIF_SDMA3_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
57821 | //GDC2_BIF_VCN1_DOORBELL_RANGE |
57822 | #define GDC2_BIF_VCN1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
57823 | #define GDC2_BIF_VCN1_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
57824 | #define GDC2_BIF_VCN1_DOORBELL_RANGE__NEED_DEDUCT__SHIFT 0x15 |
57825 | #define GDC2_BIF_VCN1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
57826 | #define GDC2_BIF_VCN1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
57827 | #define GDC2_BIF_VCN1_DOORBELL_RANGE__NEED_DEDUCT_MASK 0x00200000L |
57828 | //GDC2_BIF_SDMA4_DOORBELL_RANGE |
57829 | #define GDC2_BIF_SDMA4_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
57830 | #define GDC2_BIF_SDMA4_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
57831 | #define GDC2_BIF_SDMA4_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
57832 | #define GDC2_BIF_SDMA4_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
57833 | //GDC2_BIF_SDMA5_DOORBELL_RANGE |
57834 | #define GDC2_BIF_SDMA5_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
57835 | #define GDC2_BIF_SDMA5_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
57836 | #define GDC2_BIF_SDMA5_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
57837 | #define GDC2_BIF_SDMA5_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
57838 | //GDC2_BIF_CSDMA_DOORBELL_RANGE |
57839 | #define GDC2_BIF_CSDMA_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
57840 | #define GDC2_BIF_CSDMA_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
57841 | #define GDC2_BIF_CSDMA_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
57842 | #define GDC2_BIF_CSDMA_DOORBELL_RANGE__SIZE_MASK 0x00FF0000L |
57843 | //GDC2_BIF_VPE_DOORBELL_RANGE |
57844 | #define GDC2_BIF_VPE_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
57845 | #define GDC2_BIF_VPE_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
57846 | #define GDC2_BIF_VPE_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
57847 | #define GDC2_BIF_VPE_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
57848 | //GDC2_ATDMA_MISC_CNTL |
57849 | #define GDC2_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 |
57850 | #define GDC2_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 |
57851 | #define GDC2_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT 0x2 |
57852 | #define GDC2_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT 0x8 |
57853 | #define GDC2_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 |
57854 | #define GDC2_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 |
57855 | #define GDC2_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L |
57856 | #define GDC2_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L |
57857 | #define GDC2_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK 0x0000000CL |
57858 | #define GDC2_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK 0x0000FF00L |
57859 | #define GDC2_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L |
57860 | #define GDC2_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L |
57861 | //GDC2_BIF_DOORBELL_FENCE_CNTL |
57862 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE__SHIFT 0x0 |
57863 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE__SHIFT 0x1 |
57864 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE__SHIFT 0x2 |
57865 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE__SHIFT 0x4 |
57866 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE__SHIFT 0x5 |
57867 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE__SHIFT 0x6 |
57868 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE__SHIFT 0x7 |
57869 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE__SHIFT 0x8 |
57870 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CSDMA_ENABLE__SHIFT 0x9 |
57871 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_VPE_ENABLE__SHIFT 0xa |
57872 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x10 |
57873 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE_MASK 0x00000001L |
57874 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE_MASK 0x00000002L |
57875 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE_MASK 0x00000004L |
57876 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE_MASK 0x00000010L |
57877 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE_MASK 0x00000020L |
57878 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE_MASK 0x00000040L |
57879 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE_MASK 0x00000080L |
57880 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE_MASK 0x00000100L |
57881 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CSDMA_ENABLE_MASK 0x00000200L |
57882 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_VPE_ENABLE_MASK 0x00000400L |
57883 | #define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00010000L |
57884 | |
57885 | |
57886 | #endif |
57887 | |