1 | /* |
2 | * Copyright 2021 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #include "amdgpu.h" |
24 | #include "nbio_v7_11.h" |
25 | |
26 | #include "nbio/nbio_7_11_0_offset.h" |
27 | #include "nbio/nbio_7_11_0_sh_mask.h" |
28 | #include <uapi/linux/kfd_ioctl.h> |
29 | |
30 | static void nbio_v7_11_remap_hdp_registers(struct amdgpu_device *adev) |
31 | { |
32 | WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, |
33 | adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); |
34 | WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, |
35 | adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); |
36 | } |
37 | |
38 | static u32 nbio_v7_11_get_rev_id(struct amdgpu_device *adev) |
39 | { |
40 | u32 tmp; |
41 | |
42 | tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0); |
43 | tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; |
44 | tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; |
45 | |
46 | return tmp; |
47 | } |
48 | |
49 | static void nbio_v7_11_mc_access_enable(struct amdgpu_device *adev, bool enable) |
50 | { |
51 | if (enable) |
52 | WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, |
53 | BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK | |
54 | BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK); |
55 | else |
56 | WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 0); |
57 | } |
58 | |
59 | static u32 nbio_v7_11_get_memsize(struct amdgpu_device *adev) |
60 | { |
61 | return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE); |
62 | } |
63 | |
64 | static void nbio_v7_11_sdma_doorbell_range(struct amdgpu_device *adev, int instance, |
65 | bool use_doorbell, int doorbell_index, |
66 | int doorbell_size) |
67 | { |
68 | u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE); |
69 | u32 doorbell_range = RREG32_PCIE_PORT(reg); |
70 | |
71 | if (use_doorbell) { |
72 | doorbell_range = REG_SET_FIELD(doorbell_range, |
73 | GDC0_BIF_CSDMA_DOORBELL_RANGE, |
74 | OFFSET, doorbell_index); |
75 | doorbell_range = REG_SET_FIELD(doorbell_range, |
76 | GDC0_BIF_CSDMA_DOORBELL_RANGE, |
77 | SIZE, doorbell_size); |
78 | } else { |
79 | doorbell_range = REG_SET_FIELD(doorbell_range, |
80 | GDC0_BIF_CSDMA_DOORBELL_RANGE, |
81 | SIZE, 0); |
82 | } |
83 | |
84 | WREG32_PCIE_PORT(reg, doorbell_range); |
85 | } |
86 | |
87 | static void nbio_v7_11_vpe_doorbell_range(struct amdgpu_device *adev, int instance, |
88 | bool use_doorbell, int doorbell_index, |
89 | int doorbell_size) |
90 | { |
91 | u32 reg = instance == 0 ? |
92 | SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VPE_DOORBELL_RANGE) : |
93 | SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VPE1_DOORBELL_RANGE); |
94 | u32 doorbell_range = RREG32_PCIE_PORT(reg); |
95 | |
96 | if (use_doorbell) { |
97 | doorbell_range = REG_SET_FIELD(doorbell_range, |
98 | GDC0_BIF_VPE_DOORBELL_RANGE, |
99 | OFFSET, doorbell_index); |
100 | doorbell_range = REG_SET_FIELD(doorbell_range, |
101 | GDC0_BIF_VPE_DOORBELL_RANGE, |
102 | SIZE, doorbell_size); |
103 | } else { |
104 | doorbell_range = REG_SET_FIELD(doorbell_range, |
105 | GDC0_BIF_VPE_DOORBELL_RANGE, |
106 | SIZE, 0); |
107 | } |
108 | |
109 | WREG32_PCIE_PORT(reg, doorbell_range); |
110 | } |
111 | |
112 | static void nbio_v7_11_vcn_doorbell_range(struct amdgpu_device *adev, |
113 | bool use_doorbell, |
114 | int doorbell_index, int instance) |
115 | { |
116 | u32 reg = instance == 0 ? |
117 | SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE): |
118 | SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN1_DOORBELL_RANGE); |
119 | |
120 | u32 doorbell_range = RREG32_PCIE_PORT(reg); |
121 | |
122 | if (use_doorbell) { |
123 | doorbell_range = REG_SET_FIELD(doorbell_range, |
124 | GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET, |
125 | doorbell_index); |
126 | doorbell_range = REG_SET_FIELD(doorbell_range, |
127 | GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8); |
128 | } else { |
129 | doorbell_range = REG_SET_FIELD(doorbell_range, |
130 | GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0); |
131 | } |
132 | |
133 | WREG32_PCIE_PORT(reg, doorbell_range); |
134 | } |
135 | |
136 | static void nbio_v7_11_enable_doorbell_aperture(struct amdgpu_device *adev, |
137 | bool enable) |
138 | { |
139 | u32 reg; |
140 | |
141 | |
142 | reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN); |
143 | reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, |
144 | BIF_DOORBELL_APER_EN, enable ? 1 : 0); |
145 | |
146 | WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg); |
147 | } |
148 | |
149 | static void nbio_v7_11_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, |
150 | bool enable) |
151 | { |
152 | u32 tmp = 0; |
153 | |
154 | if (enable) { |
155 | tmp = REG_SET_FIELD(tmp, BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL, |
156 | DOORBELL_SELFRING_GPA_APER_EN, 1) | |
157 | REG_SET_FIELD(tmp, BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL, |
158 | DOORBELL_SELFRING_GPA_APER_MODE, 1) | |
159 | REG_SET_FIELD(tmp, BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL, |
160 | DOORBELL_SELFRING_GPA_APER_SIZE, 0); |
161 | |
162 | WREG32_SOC15(NBIO, 0, |
163 | regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW, |
164 | lower_32_bits(adev->doorbell.base)); |
165 | WREG32_SOC15(NBIO, 0, |
166 | regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, |
167 | upper_32_bits(adev->doorbell.base)); |
168 | } |
169 | |
170 | WREG32_SOC15(NBIO, 0, regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); |
171 | } |
172 | |
173 | |
174 | static void nbio_v7_11_ih_doorbell_range(struct amdgpu_device *adev, |
175 | bool use_doorbell, int doorbell_index) |
176 | { |
177 | u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,regGDC0_BIF_IH_DOORBELL_RANGE); |
178 | |
179 | if (use_doorbell) { |
180 | ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, |
181 | GDC0_BIF_IH_DOORBELL_RANGE, OFFSET, |
182 | doorbell_index); |
183 | ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, |
184 | GDC0_BIF_IH_DOORBELL_RANGE, SIZE, |
185 | 2); |
186 | } else { |
187 | ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, |
188 | GDC0_BIF_IH_DOORBELL_RANGE, SIZE, |
189 | 0); |
190 | } |
191 | |
192 | WREG32_SOC15(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE, |
193 | ih_doorbell_range); |
194 | } |
195 | |
196 | static void nbio_v7_11_ih_control(struct amdgpu_device *adev) |
197 | { |
198 | u32 interrupt_cntl; |
199 | |
200 | /* setup interrupt control */ |
201 | WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL2, |
202 | adev->dummy_page_addr >> 8); |
203 | |
204 | interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL); |
205 | /* |
206 | * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi |
207 | * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN |
208 | */ |
209 | interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL, |
210 | IH_DUMMY_RD_OVERRIDE, 0); |
211 | |
212 | /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ |
213 | interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL, |
214 | IH_REQ_NONSNOOP_EN, 0); |
215 | |
216 | WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL, interrupt_cntl); |
217 | } |
218 | |
219 | static u32 nbio_v7_11_get_hdp_flush_req_offset(struct amdgpu_device *adev) |
220 | { |
221 | return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_GPU_HDP_FLUSH_REQ); |
222 | } |
223 | |
224 | static u32 nbio_v7_11_get_hdp_flush_done_offset(struct amdgpu_device *adev) |
225 | { |
226 | return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_GPU_HDP_FLUSH_DONE); |
227 | } |
228 | |
229 | static u32 nbio_v7_11_get_pcie_index_offset(struct amdgpu_device *adev) |
230 | { |
231 | return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX1_PCIE_INDEX2); |
232 | } |
233 | |
234 | static u32 nbio_v7_11_get_pcie_data_offset(struct amdgpu_device *adev) |
235 | { |
236 | return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX1_PCIE_DATA2); |
237 | } |
238 | |
239 | static u32 nbio_v7_11_get_pcie_port_index_offset(struct amdgpu_device *adev) |
240 | { |
241 | return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_RSMU_INDEX); |
242 | } |
243 | |
244 | static u32 nbio_v7_11_get_pcie_port_data_offset(struct amdgpu_device *adev) |
245 | { |
246 | return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_RSMU_DATA); |
247 | } |
248 | |
249 | const struct nbio_hdp_flush_reg nbio_v7_11_hdp_flush_reg = { |
250 | .ref_and_mask_cp0 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK, |
251 | .ref_and_mask_cp1 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK, |
252 | .ref_and_mask_cp2 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK, |
253 | .ref_and_mask_cp3 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK, |
254 | .ref_and_mask_cp4 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK, |
255 | .ref_and_mask_cp5 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK, |
256 | .ref_and_mask_cp6 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK, |
257 | .ref_and_mask_cp7 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK, |
258 | .ref_and_mask_cp8 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK, |
259 | .ref_and_mask_cp9 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK, |
260 | .ref_and_mask_sdma0 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK, |
261 | .ref_and_mask_sdma1 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK, |
262 | }; |
263 | |
264 | static void nbio_v7_11_init_registers(struct amdgpu_device *adev) |
265 | { |
266 | uint32_t def, data; |
267 | |
268 | def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3); |
269 | data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, |
270 | CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); |
271 | data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, |
272 | CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); |
273 | |
274 | if (def != data) |
275 | WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, data); |
276 | |
277 | switch (amdgpu_ip_version(adev, ip: NBIO_HWIP, inst: 0)) { |
278 | case IP_VERSION(7, 11, 0): |
279 | case IP_VERSION(7, 11, 1): |
280 | case IP_VERSION(7, 11, 2): |
281 | case IP_VERSION(7, 11, 3): |
282 | data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23); |
283 | WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4, data); |
284 | break; |
285 | } |
286 | } |
287 | |
288 | static void nbio_v7_11_update_medium_grain_clock_gating(struct amdgpu_device *adev, |
289 | bool enable) |
290 | { |
291 | uint32_t def, data; |
292 | |
293 | if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) |
294 | return; |
295 | |
296 | def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL); |
297 | if (enable) { |
298 | data |= (BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | |
299 | BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | |
300 | BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | |
301 | BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | |
302 | BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | |
303 | BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); |
304 | } else { |
305 | data &= ~(BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | |
306 | BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | |
307 | BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | |
308 | BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | |
309 | BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | |
310 | BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); |
311 | } |
312 | |
313 | if (def != data) |
314 | WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL, data); |
315 | } |
316 | |
317 | static void nbio_v7_11_update_medium_grain_light_sleep(struct amdgpu_device *adev, |
318 | bool enable) |
319 | { |
320 | uint32_t def, data; |
321 | |
322 | if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) |
323 | return; |
324 | |
325 | def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2); |
326 | if (enable) |
327 | data |= BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK; |
328 | else |
329 | data &= ~BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK; |
330 | |
331 | if (def != data) |
332 | WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2, data); |
333 | |
334 | def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1); |
335 | if (enable) { |
336 | data |= (BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK | |
337 | BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK); |
338 | } else { |
339 | data &= ~(BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK | |
340 | BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK); |
341 | } |
342 | |
343 | if (def != data) |
344 | WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1, data); |
345 | } |
346 | |
347 | static void nbio_v7_11_get_clockgating_state(struct amdgpu_device *adev, |
348 | u64 *flags) |
349 | { |
350 | uint32_t data; |
351 | |
352 | /* AMD_CG_SUPPORT_BIF_MGCG */ |
353 | data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL); |
354 | if (data & BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) |
355 | *flags |= AMD_CG_SUPPORT_BIF_MGCG; |
356 | |
357 | /* AMD_CG_SUPPORT_BIF_LS */ |
358 | data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2); |
359 | if (data & BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK) |
360 | *flags |= AMD_CG_SUPPORT_BIF_LS; |
361 | } |
362 | |
363 | #define MMIO_REG_HOLE_OFFSET 0x44000 |
364 | |
365 | static void nbio_v7_11_set_reg_remap(struct amdgpu_device *adev) |
366 | { |
367 | if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) { |
368 | adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; |
369 | adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; |
370 | } else { |
371 | adev->rmmio_remap.reg_offset = |
372 | SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; |
373 | adev->rmmio_remap.bus_addr = 0; |
374 | } |
375 | } |
376 | |
377 | const struct amdgpu_nbio_funcs nbio_v7_11_funcs = { |
378 | .get_hdp_flush_req_offset = nbio_v7_11_get_hdp_flush_req_offset, |
379 | .get_hdp_flush_done_offset = nbio_v7_11_get_hdp_flush_done_offset, |
380 | .get_pcie_index_offset = nbio_v7_11_get_pcie_index_offset, |
381 | .get_pcie_data_offset = nbio_v7_11_get_pcie_data_offset, |
382 | .get_pcie_port_index_offset = nbio_v7_11_get_pcie_port_index_offset, |
383 | .get_pcie_port_data_offset = nbio_v7_11_get_pcie_port_data_offset, |
384 | .get_rev_id = nbio_v7_11_get_rev_id, |
385 | .mc_access_enable = nbio_v7_11_mc_access_enable, |
386 | .get_memsize = nbio_v7_11_get_memsize, |
387 | .sdma_doorbell_range = nbio_v7_11_sdma_doorbell_range, |
388 | .vcn_doorbell_range = nbio_v7_11_vcn_doorbell_range, |
389 | .vpe_doorbell_range = nbio_v7_11_vpe_doorbell_range, |
390 | .enable_doorbell_aperture = nbio_v7_11_enable_doorbell_aperture, |
391 | .enable_doorbell_selfring_aperture = nbio_v7_11_enable_doorbell_selfring_aperture, |
392 | .ih_doorbell_range = nbio_v7_11_ih_doorbell_range, |
393 | .update_medium_grain_clock_gating = nbio_v7_11_update_medium_grain_clock_gating, |
394 | .update_medium_grain_light_sleep = nbio_v7_11_update_medium_grain_light_sleep, |
395 | .get_clockgating_state = nbio_v7_11_get_clockgating_state, |
396 | .ih_control = nbio_v7_11_ih_control, |
397 | .init_registers = nbio_v7_11_init_registers, |
398 | .remap_hdp_registers = nbio_v7_11_remap_hdp_registers, |
399 | .set_reg_remap = nbio_v7_11_set_reg_remap, |
400 | }; |
401 | |