1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #ifndef PP_SISLANDS_SMC_H |
24 | #define PP_SISLANDS_SMC_H |
25 | |
26 | #include "ppsmc.h" |
27 | |
28 | #pragma pack(push, 1) |
29 | |
30 | #define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 |
31 | |
32 | struct PP_SIslands_Dpm2PerfLevel { |
33 | uint8_t MaxPS; |
34 | uint8_t TgtAct; |
35 | uint8_t MaxPS_StepInc; |
36 | uint8_t MaxPS_StepDec; |
37 | uint8_t PSSamplingTime; |
38 | uint8_t NearTDPDec; |
39 | uint8_t AboveSafeInc; |
40 | uint8_t BelowSafeInc; |
41 | uint8_t PSDeltaLimit; |
42 | uint8_t PSDeltaWin; |
43 | uint16_t PwrEfficiencyRatio; |
44 | uint8_t Reserved[4]; |
45 | }; |
46 | |
47 | typedef struct PP_SIslands_Dpm2PerfLevel PP_SIslands_Dpm2PerfLevel; |
48 | |
49 | struct PP_SIslands_DPM2Status { |
50 | uint32_t dpm2Flags; |
51 | uint8_t CurrPSkip; |
52 | uint8_t CurrPSkipPowerShift; |
53 | uint8_t CurrPSkipTDP; |
54 | uint8_t CurrPSkipOCP; |
55 | uint8_t MaxSPLLIndex; |
56 | uint8_t MinSPLLIndex; |
57 | uint8_t CurrSPLLIndex; |
58 | uint8_t InfSweepMode; |
59 | uint8_t InfSweepDir; |
60 | uint8_t TDPexceeded; |
61 | uint8_t reserved; |
62 | uint8_t SwitchDownThreshold; |
63 | uint32_t SwitchDownCounter; |
64 | uint32_t SysScalingFactor; |
65 | }; |
66 | |
67 | typedef struct PP_SIslands_DPM2Status PP_SIslands_DPM2Status; |
68 | |
69 | struct PP_SIslands_DPM2Parameters { |
70 | uint32_t TDPLimit; |
71 | uint32_t NearTDPLimit; |
72 | uint32_t SafePowerLimit; |
73 | uint32_t PowerBoostLimit; |
74 | uint32_t MinLimitDelta; |
75 | }; |
76 | typedef struct PP_SIslands_DPM2Parameters PP_SIslands_DPM2Parameters; |
77 | |
78 | struct PP_SIslands_PAPMStatus { |
79 | uint32_t EstimatedDGPU_T; |
80 | uint32_t EstimatedDGPU_P; |
81 | uint32_t EstimatedAPU_T; |
82 | uint32_t EstimatedAPU_P; |
83 | uint8_t dGPU_T_Limit_Exceeded; |
84 | uint8_t reserved[3]; |
85 | }; |
86 | typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus; |
87 | |
88 | struct PP_SIslands_PAPMParameters { |
89 | uint32_t NearTDPLimitTherm; |
90 | uint32_t NearTDPLimitPAPM; |
91 | uint32_t PlatformPowerLimit; |
92 | uint32_t dGPU_T_Limit; |
93 | uint32_t dGPU_T_Warning; |
94 | uint32_t dGPU_T_Hysteresis; |
95 | }; |
96 | typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters; |
97 | |
98 | struct SISLANDS_SMC_SCLK_VALUE { |
99 | uint32_t vCG_SPLL_FUNC_CNTL; |
100 | uint32_t vCG_SPLL_FUNC_CNTL_2; |
101 | uint32_t vCG_SPLL_FUNC_CNTL_3; |
102 | uint32_t vCG_SPLL_FUNC_CNTL_4; |
103 | uint32_t vCG_SPLL_SPREAD_SPECTRUM; |
104 | uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; |
105 | uint32_t sclk_value; |
106 | }; |
107 | |
108 | typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE; |
109 | |
110 | struct SISLANDS_SMC_MCLK_VALUE { |
111 | uint32_t vMPLL_FUNC_CNTL; |
112 | uint32_t vMPLL_FUNC_CNTL_1; |
113 | uint32_t vMPLL_FUNC_CNTL_2; |
114 | uint32_t vMPLL_AD_FUNC_CNTL; |
115 | uint32_t vMPLL_DQ_FUNC_CNTL; |
116 | uint32_t vMCLK_PWRMGT_CNTL; |
117 | uint32_t vDLL_CNTL; |
118 | uint32_t vMPLL_SS; |
119 | uint32_t vMPLL_SS2; |
120 | uint32_t mclk_value; |
121 | }; |
122 | |
123 | typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE; |
124 | |
125 | struct SISLANDS_SMC_VOLTAGE_VALUE { |
126 | uint16_t value; |
127 | uint8_t index; |
128 | uint8_t phase_settings; |
129 | }; |
130 | |
131 | typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE; |
132 | |
133 | struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL { |
134 | uint8_t ACIndex; |
135 | uint8_t displayWatermark; |
136 | uint8_t gen2PCIE; |
137 | uint8_t UVDWatermark; |
138 | uint8_t VCEWatermark; |
139 | uint8_t strobeMode; |
140 | uint8_t mcFlags; |
141 | uint8_t padding; |
142 | uint32_t aT; |
143 | uint32_t bSP; |
144 | SISLANDS_SMC_SCLK_VALUE sclk; |
145 | SISLANDS_SMC_MCLK_VALUE mclk; |
146 | SISLANDS_SMC_VOLTAGE_VALUE vddc; |
147 | SISLANDS_SMC_VOLTAGE_VALUE mvdd; |
148 | SISLANDS_SMC_VOLTAGE_VALUE vddci; |
149 | SISLANDS_SMC_VOLTAGE_VALUE std_vddc; |
150 | uint8_t hysteresisUp; |
151 | uint8_t hysteresisDown; |
152 | uint8_t stateFlags; |
153 | uint8_t arbRefreshState; |
154 | uint32_t SQPowerThrottle; |
155 | uint32_t SQPowerThrottle_2; |
156 | uint32_t MaxPoweredUpCU; |
157 | SISLANDS_SMC_VOLTAGE_VALUE high_temp_vddc; |
158 | SISLANDS_SMC_VOLTAGE_VALUE low_temp_vddc; |
159 | uint32_t reserved[2]; |
160 | PP_SIslands_Dpm2PerfLevel dpm2; |
161 | }; |
162 | |
163 | #define SISLANDS_SMC_STROBE_RATIO 0x0F |
164 | #define SISLANDS_SMC_STROBE_ENABLE 0x10 |
165 | |
166 | #define SISLANDS_SMC_MC_EDC_RD_FLAG 0x01 |
167 | #define SISLANDS_SMC_MC_EDC_WR_FLAG 0x02 |
168 | #define SISLANDS_SMC_MC_RTT_ENABLE 0x04 |
169 | #define SISLANDS_SMC_MC_STUTTER_EN 0x08 |
170 | #define SISLANDS_SMC_MC_PG_EN 0x10 |
171 | |
172 | typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL; |
173 | |
174 | struct SISLANDS_SMC_SWSTATE { |
175 | uint8_t flags; |
176 | uint8_t levelCount; |
177 | uint8_t padding2; |
178 | uint8_t padding3; |
179 | SISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[]; |
180 | }; |
181 | |
182 | typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE; |
183 | |
184 | struct SISLANDS_SMC_SWSTATE_SINGLE { |
185 | uint8_t flags; |
186 | uint8_t levelCount; |
187 | uint8_t padding2; |
188 | uint8_t padding3; |
189 | SISLANDS_SMC_HW_PERFORMANCE_LEVEL level; |
190 | }; |
191 | |
192 | #define SISLANDS_SMC_VOLTAGEMASK_VDDC 0 |
193 | #define SISLANDS_SMC_VOLTAGEMASK_MVDD 1 |
194 | #define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2 |
195 | #define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3 |
196 | #define SISLANDS_SMC_VOLTAGEMASK_MAX 4 |
197 | |
198 | struct SISLANDS_SMC_VOLTAGEMASKTABLE { |
199 | uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX]; |
200 | }; |
201 | |
202 | typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE; |
203 | |
204 | #define SISLANDS_MAX_NO_VREG_STEPS 32 |
205 | |
206 | struct SISLANDS_SMC_STATETABLE { |
207 | uint8_t thermalProtectType; |
208 | uint8_t systemFlags; |
209 | uint8_t maxVDDCIndexInPPTable; |
210 | uint8_t extraFlags; |
211 | uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS]; |
212 | SISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable; |
213 | SISLANDS_SMC_VOLTAGEMASKTABLE phaseMaskTable; |
214 | PP_SIslands_DPM2Parameters dpm2Params; |
215 | struct SISLANDS_SMC_SWSTATE_SINGLE initialState; |
216 | struct SISLANDS_SMC_SWSTATE_SINGLE ACPIState; |
217 | struct SISLANDS_SMC_SWSTATE_SINGLE ULVState; |
218 | SISLANDS_SMC_SWSTATE driverState; |
219 | SISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; |
220 | }; |
221 | |
222 | typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE; |
223 | |
224 | #define SI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0 |
225 | #define SI_SMC_SOFT_REGISTER_delay_vreg 0xC |
226 | #define SI_SMC_SOFT_REGISTER_delay_acpi 0x28 |
227 | #define SI_SMC_SOFT_REGISTER_seq_index 0x5C |
228 | #define SI_SMC_SOFT_REGISTER_mvdd_chg_time 0x60 |
229 | #define SI_SMC_SOFT_REGISTER_mclk_switch_lim 0x70 |
230 | #define SI_SMC_SOFT_REGISTER_watermark_threshold 0x78 |
231 | #define SI_SMC_SOFT_REGISTER_phase_shedding_delay 0x88 |
232 | #define SI_SMC_SOFT_REGISTER_ulv_volt_change_delay 0x8C |
233 | #define SI_SMC_SOFT_REGISTER_mc_block_delay 0x98 |
234 | #define SI_SMC_SOFT_REGISTER_ticks_per_us 0xA8 |
235 | #define SI_SMC_SOFT_REGISTER_crtc_index 0xC4 |
236 | #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min 0xC8 |
237 | #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max 0xCC |
238 | #define SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width 0xF4 |
239 | #define SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen 0xFC |
240 | #define SI_SMC_SOFT_REGISTER_vr_hot_gpio 0x100 |
241 | #define SI_SMC_SOFT_REGISTER_svi_rework_plat_type 0x118 |
242 | #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd 0x11c |
243 | #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc 0x120 |
244 | |
245 | struct PP_SIslands_FanTable { |
246 | uint8_t fdo_mode; |
247 | uint8_t padding; |
248 | int16_t temp_min; |
249 | int16_t temp_med; |
250 | int16_t temp_max; |
251 | int16_t slope1; |
252 | int16_t slope2; |
253 | int16_t fdo_min; |
254 | int16_t hys_up; |
255 | int16_t hys_down; |
256 | int16_t hys_slope; |
257 | int16_t temp_resp_lim; |
258 | int16_t temp_curr; |
259 | int16_t slope_curr; |
260 | int16_t pwm_curr; |
261 | uint32_t refresh_period; |
262 | int16_t fdo_max; |
263 | uint8_t temp_src; |
264 | int8_t padding2; |
265 | }; |
266 | |
267 | typedef struct PP_SIslands_FanTable PP_SIslands_FanTable; |
268 | |
269 | #define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 |
270 | #define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 32 |
271 | |
272 | #define SMC_SISLANDS_SCALE_I 7 |
273 | #define SMC_SISLANDS_SCALE_R 12 |
274 | |
275 | struct PP_SIslands_CacConfig { |
276 | uint16_t cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES]; |
277 | uint32_t lkge_lut_V0; |
278 | uint32_t lkge_lut_Vstep; |
279 | uint32_t WinTime; |
280 | uint32_t R_LL; |
281 | uint32_t calculation_repeats; |
282 | uint32_t l2numWin_TDP; |
283 | uint32_t dc_cac; |
284 | uint8_t lts_truncate_n; |
285 | uint8_t SHIFT_N; |
286 | uint8_t log2_PG_LKG_SCALE; |
287 | uint8_t cac_temp; |
288 | uint32_t lkge_lut_T0; |
289 | uint32_t lkge_lut_Tstep; |
290 | }; |
291 | |
292 | typedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig; |
293 | |
294 | #define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16 |
295 | #define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 |
296 | |
297 | struct SMC_SIslands_MCRegisterAddress { |
298 | uint16_t s0; |
299 | uint16_t s1; |
300 | }; |
301 | |
302 | typedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress; |
303 | |
304 | struct SMC_SIslands_MCRegisterSet { |
305 | uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; |
306 | }; |
307 | |
308 | typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet; |
309 | |
310 | struct SMC_SIslands_MCRegisters { |
311 | uint8_t last; |
312 | uint8_t reserved[3]; |
313 | SMC_SIslands_MCRegisterAddress address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; |
314 | SMC_SIslands_MCRegisterSet data[SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT]; |
315 | }; |
316 | |
317 | typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters; |
318 | |
319 | struct SMC_SIslands_MCArbDramTimingRegisterSet { |
320 | uint32_t mc_arb_dram_timing; |
321 | uint32_t mc_arb_dram_timing2; |
322 | uint8_t mc_arb_rfsh_rate; |
323 | uint8_t mc_arb_burst_time; |
324 | uint8_t padding[2]; |
325 | }; |
326 | |
327 | typedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet; |
328 | |
329 | struct SMC_SIslands_MCArbDramTimingRegisters { |
330 | uint8_t arb_current; |
331 | uint8_t reserved[3]; |
332 | SMC_SIslands_MCArbDramTimingRegisterSet data[16]; |
333 | }; |
334 | |
335 | typedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters; |
336 | |
337 | struct SMC_SISLANDS_SPLL_DIV_TABLE { |
338 | uint32_t freq[256]; |
339 | uint32_t ss[256]; |
340 | }; |
341 | |
342 | #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff |
343 | #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0 |
344 | #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000 |
345 | #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25 |
346 | #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff |
347 | #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0 |
348 | #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000 |
349 | #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20 |
350 | |
351 | typedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE; |
352 | |
353 | #define SMC_SISLANDS_DTE_MAX_FILTER_STAGES 5 |
354 | |
355 | #define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16 |
356 | |
357 | struct Smc_SIslands_DTE_Configuration { |
358 | uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; |
359 | uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; |
360 | uint32_t K; |
361 | uint32_t T0; |
362 | uint32_t MaxT; |
363 | uint8_t WindowSize; |
364 | uint8_t Tdep_count; |
365 | uint8_t temp_select; |
366 | uint8_t DTE_mode; |
367 | uint8_t T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; |
368 | uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; |
369 | uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; |
370 | uint32_t Tthreshold; |
371 | }; |
372 | |
373 | typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration; |
374 | |
375 | #define SMC_SISLANDS_DTE_STATUS_FLAG_DTE_ON 1 |
376 | |
377 | #define SISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x10000 |
378 | |
379 | #define SISLANDS_SMC_FIRMWARE_HEADER_version 0x0 |
380 | #define SISLANDS_SMC_FIRMWARE_HEADER_flags 0x4 |
381 | #define SISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0xC |
382 | #define SISLANDS_SMC_FIRMWARE_HEADER_stateTable 0x10 |
383 | #define SISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x14 |
384 | #define SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable 0x18 |
385 | #define SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x24 |
386 | #define SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x30 |
387 | #define SISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x38 |
388 | #define SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration 0x40 |
389 | #define SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters 0x48 |
390 | |
391 | #pragma pack(pop) |
392 | |
393 | int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev, |
394 | u32 smc_start_address, |
395 | const u8 *src, u32 byte_count, u32 limit); |
396 | void amdgpu_si_start_smc(struct amdgpu_device *adev); |
397 | void amdgpu_si_reset_smc(struct amdgpu_device *adev); |
398 | int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev); |
399 | void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable); |
400 | bool amdgpu_si_is_smc_running(struct amdgpu_device *adev); |
401 | PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg); |
402 | PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev); |
403 | int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit); |
404 | int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, |
405 | u32 *value, u32 limit); |
406 | int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, |
407 | u32 value, u32 limit); |
408 | |
409 | #endif |
410 | |
411 | |