1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * DesignWare High-Definition Multimedia Interface (HDMI) driver |
4 | * |
5 | * Copyright (C) 2013-2015 Mentor Graphics Inc. |
6 | * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. |
7 | * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
8 | */ |
9 | #include <linux/clk.h> |
10 | #include <linux/delay.h> |
11 | #include <linux/err.h> |
12 | #include <linux/hdmi.h> |
13 | #include <linux/i2c.h> |
14 | #include <linux/irq.h> |
15 | #include <linux/module.h> |
16 | #include <linux/mutex.h> |
17 | #include <linux/of.h> |
18 | #include <linux/pinctrl/consumer.h> |
19 | #include <linux/regmap.h> |
20 | #include <linux/dma-mapping.h> |
21 | #include <linux/spinlock.h> |
22 | |
23 | #include <media/cec-notifier.h> |
24 | |
25 | #include <uapi/linux/media-bus-format.h> |
26 | #include <uapi/linux/videodev2.h> |
27 | |
28 | #include <drm/bridge/dw_hdmi.h> |
29 | #include <drm/display/drm_hdmi_helper.h> |
30 | #include <drm/display/drm_scdc_helper.h> |
31 | #include <drm/drm_atomic.h> |
32 | #include <drm/drm_atomic_helper.h> |
33 | #include <drm/drm_bridge.h> |
34 | #include <drm/drm_edid.h> |
35 | #include <drm/drm_of.h> |
36 | #include <drm/drm_print.h> |
37 | #include <drm/drm_probe_helper.h> |
38 | |
39 | #include "dw-hdmi-audio.h" |
40 | #include "dw-hdmi-cec.h" |
41 | #include "dw-hdmi.h" |
42 | |
43 | #define DDC_CI_ADDR 0x37 |
44 | #define DDC_SEGMENT_ADDR 0x30 |
45 | |
46 | #define HDMI_EDID_LEN 512 |
47 | |
48 | /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ |
49 | #define SCDC_MIN_SOURCE_VERSION 0x1 |
50 | |
51 | #define HDMI14_MAX_TMDSCLK 340000000 |
52 | |
53 | static const u16 csc_coeff_default[3][4] = { |
54 | { 0x2000, 0x0000, 0x0000, 0x0000 }, |
55 | { 0x0000, 0x2000, 0x0000, 0x0000 }, |
56 | { 0x0000, 0x0000, 0x2000, 0x0000 } |
57 | }; |
58 | |
59 | static const u16 csc_coeff_rgb_out_eitu601[3][4] = { |
60 | { 0x2000, 0x6926, 0x74fd, 0x010e }, |
61 | { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, |
62 | { 0x2000, 0x0000, 0x38b4, 0x7e3b } |
63 | }; |
64 | |
65 | static const u16 csc_coeff_rgb_out_eitu709[3][4] = { |
66 | { 0x2000, 0x7106, 0x7a02, 0x00a7 }, |
67 | { 0x2000, 0x3264, 0x0000, 0x7e6d }, |
68 | { 0x2000, 0x0000, 0x3b61, 0x7e25 } |
69 | }; |
70 | |
71 | static const u16 csc_coeff_rgb_in_eitu601[3][4] = { |
72 | { 0x2591, 0x1322, 0x074b, 0x0000 }, |
73 | { 0x6535, 0x2000, 0x7acc, 0x0200 }, |
74 | { 0x6acd, 0x7534, 0x2000, 0x0200 } |
75 | }; |
76 | |
77 | static const u16 csc_coeff_rgb_in_eitu709[3][4] = { |
78 | { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, |
79 | { 0x62f0, 0x2000, 0x7d11, 0x0200 }, |
80 | { 0x6756, 0x78ab, 0x2000, 0x0200 } |
81 | }; |
82 | |
83 | static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = { |
84 | { 0x1b7c, 0x0000, 0x0000, 0x0020 }, |
85 | { 0x0000, 0x1b7c, 0x0000, 0x0020 }, |
86 | { 0x0000, 0x0000, 0x1b7c, 0x0020 } |
87 | }; |
88 | |
89 | struct hdmi_vmode { |
90 | bool mdataenablepolarity; |
91 | |
92 | unsigned int mpixelclock; |
93 | unsigned int mpixelrepetitioninput; |
94 | unsigned int mpixelrepetitionoutput; |
95 | unsigned int mtmdsclock; |
96 | }; |
97 | |
98 | struct hdmi_data_info { |
99 | unsigned int enc_in_bus_format; |
100 | unsigned int enc_out_bus_format; |
101 | unsigned int enc_in_encoding; |
102 | unsigned int enc_out_encoding; |
103 | unsigned int pix_repet_factor; |
104 | unsigned int hdcp_enable; |
105 | struct hdmi_vmode video_mode; |
106 | bool rgb_limited_range; |
107 | }; |
108 | |
109 | struct dw_hdmi_i2c { |
110 | struct i2c_adapter adap; |
111 | |
112 | struct mutex lock; /* used to serialize data transfers */ |
113 | struct completion cmp; |
114 | u8 stat; |
115 | |
116 | u8 slave_reg; |
117 | bool is_regaddr; |
118 | bool is_segment; |
119 | }; |
120 | |
121 | struct dw_hdmi_phy_data { |
122 | enum dw_hdmi_phy_type type; |
123 | const char *name; |
124 | unsigned int gen; |
125 | bool has_svsret; |
126 | int (*configure)(struct dw_hdmi *hdmi, |
127 | const struct dw_hdmi_plat_data *pdata, |
128 | unsigned long mpixelclock); |
129 | }; |
130 | |
131 | struct dw_hdmi { |
132 | struct drm_connector connector; |
133 | struct drm_bridge bridge; |
134 | struct drm_bridge *next_bridge; |
135 | |
136 | unsigned int version; |
137 | |
138 | struct platform_device *audio; |
139 | struct platform_device *cec; |
140 | struct device *dev; |
141 | struct clk *isfr_clk; |
142 | struct clk *iahb_clk; |
143 | struct clk *cec_clk; |
144 | struct dw_hdmi_i2c *i2c; |
145 | |
146 | struct hdmi_data_info hdmi_data; |
147 | const struct dw_hdmi_plat_data *plat_data; |
148 | |
149 | int vic; |
150 | |
151 | u8 edid[HDMI_EDID_LEN]; |
152 | |
153 | struct { |
154 | const struct dw_hdmi_phy_ops *ops; |
155 | const char *name; |
156 | void *data; |
157 | bool enabled; |
158 | } phy; |
159 | |
160 | struct drm_display_mode previous_mode; |
161 | |
162 | struct i2c_adapter *ddc; |
163 | void __iomem *regs; |
164 | bool sink_is_hdmi; |
165 | bool sink_has_audio; |
166 | |
167 | struct pinctrl *pinctrl; |
168 | struct pinctrl_state *default_state; |
169 | struct pinctrl_state *unwedge_state; |
170 | |
171 | struct mutex mutex; /* for state below and previous_mode */ |
172 | enum drm_connector_force force; /* mutex-protected force state */ |
173 | struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */ |
174 | bool disabled; /* DRM has disabled our bridge */ |
175 | bool bridge_is_on; /* indicates the bridge is on */ |
176 | bool rxsense; /* rxsense state */ |
177 | u8 phy_mask; /* desired phy int mask settings */ |
178 | u8 mc_clkdis; /* clock disable register */ |
179 | |
180 | spinlock_t audio_lock; |
181 | struct mutex audio_mutex; |
182 | unsigned int sample_non_pcm; |
183 | unsigned int sample_width; |
184 | unsigned int sample_rate; |
185 | unsigned int channels; |
186 | unsigned int audio_cts; |
187 | unsigned int audio_n; |
188 | bool audio_enable; |
189 | |
190 | unsigned int reg_shift; |
191 | struct regmap *regm; |
192 | void (*enable_audio)(struct dw_hdmi *hdmi); |
193 | void (*disable_audio)(struct dw_hdmi *hdmi); |
194 | |
195 | struct mutex cec_notifier_mutex; |
196 | struct cec_notifier *cec_notifier; |
197 | |
198 | hdmi_codec_plugged_cb plugged_cb; |
199 | struct device *codec_dev; |
200 | enum drm_connector_status last_connector_result; |
201 | }; |
202 | |
203 | #define HDMI_IH_PHY_STAT0_RX_SENSE \ |
204 | (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ |
205 | HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) |
206 | |
207 | #define HDMI_PHY_RX_SENSE \ |
208 | (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ |
209 | HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) |
210 | |
211 | static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) |
212 | { |
213 | regmap_write(map: hdmi->regm, reg: offset << hdmi->reg_shift, val); |
214 | } |
215 | |
216 | static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) |
217 | { |
218 | unsigned int val = 0; |
219 | |
220 | regmap_read(map: hdmi->regm, reg: offset << hdmi->reg_shift, val: &val); |
221 | |
222 | return val; |
223 | } |
224 | |
225 | static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged) |
226 | { |
227 | if (hdmi->plugged_cb && hdmi->codec_dev) |
228 | hdmi->plugged_cb(hdmi->codec_dev, plugged); |
229 | } |
230 | |
231 | int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn, |
232 | struct device *codec_dev) |
233 | { |
234 | bool plugged; |
235 | |
236 | mutex_lock(&hdmi->mutex); |
237 | hdmi->plugged_cb = fn; |
238 | hdmi->codec_dev = codec_dev; |
239 | plugged = hdmi->last_connector_result == connector_status_connected; |
240 | handle_plugged_change(hdmi, plugged); |
241 | mutex_unlock(lock: &hdmi->mutex); |
242 | |
243 | return 0; |
244 | } |
245 | EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb); |
246 | |
247 | static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) |
248 | { |
249 | regmap_update_bits(map: hdmi->regm, reg: reg << hdmi->reg_shift, mask, val: data); |
250 | } |
251 | |
252 | static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, |
253 | u8 shift, u8 mask) |
254 | { |
255 | hdmi_modb(hdmi, data: data << shift, mask, reg); |
256 | } |
257 | |
258 | static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) |
259 | { |
260 | hdmi_writeb(hdmi, val: HDMI_PHY_I2CM_INT_ADDR_DONE_POL, |
261 | HDMI_PHY_I2CM_INT_ADDR); |
262 | |
263 | hdmi_writeb(hdmi, val: HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | |
264 | HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, |
265 | HDMI_PHY_I2CM_CTLINT_ADDR); |
266 | |
267 | /* Software reset */ |
268 | hdmi_writeb(hdmi, val: 0x00, HDMI_I2CM_SOFTRSTZ); |
269 | |
270 | /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ |
271 | hdmi_writeb(hdmi, val: 0x00, HDMI_I2CM_DIV); |
272 | |
273 | /* Set done, not acknowledged and arbitration interrupt polarities */ |
274 | hdmi_writeb(hdmi, val: HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); |
275 | hdmi_writeb(hdmi, val: HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, |
276 | HDMI_I2CM_CTLINT); |
277 | |
278 | /* Clear DONE and ERROR interrupts */ |
279 | hdmi_writeb(hdmi, val: HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, |
280 | HDMI_IH_I2CM_STAT0); |
281 | |
282 | /* Mute DONE and ERROR interrupts */ |
283 | hdmi_writeb(hdmi, val: HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, |
284 | HDMI_IH_MUTE_I2CM_STAT0); |
285 | } |
286 | |
287 | static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi) |
288 | { |
289 | /* If no unwedge state then give up */ |
290 | if (!hdmi->unwedge_state) |
291 | return false; |
292 | |
293 | dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n" ); |
294 | |
295 | /* |
296 | * This is a huge hack to workaround a problem where the dw_hdmi i2c |
297 | * bus could sometimes get wedged. Once wedged there doesn't appear |
298 | * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ) |
299 | * other than pulsing the SDA line. |
300 | * |
301 | * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi) |
302 | * by: |
303 | * 1. Remux the pin as a GPIO output, driven low. |
304 | * 2. Wait a little while. 1 ms seems to work, but we'll do 10. |
305 | * 3. Immediately jump to remux the pin as dw_hdmi i2c again. |
306 | * |
307 | * At the moment of remuxing, the line will still be low due to its |
308 | * recent stint as an output, but then it will be pulled high by the |
309 | * (presumed) external pullup. dw_hdmi seems to see this as a rising |
310 | * edge and that seems to get it out of its jam. |
311 | * |
312 | * This wedging was only ever seen on one TV, and only on one of |
313 | * its HDMI ports. It happened when the TV was powered on while the |
314 | * device was plugged in. A scope trace shows the TV bringing both SDA |
315 | * and SCL low, then bringing them both back up at roughly the same |
316 | * time. Presumably this confuses dw_hdmi because it saw activity but |
317 | * no real STOP (maybe it thinks there's another master on the bus?). |
318 | * Giving it a clean rising edge of SDA while SCL is already high |
319 | * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out |
320 | * of its stupor. |
321 | * |
322 | * Note that after coming back alive, transfers seem to immediately |
323 | * resume, so if we unwedge due to a timeout we should wait a little |
324 | * longer for our transfer to finish, since it might have just started |
325 | * now. |
326 | */ |
327 | pinctrl_select_state(p: hdmi->pinctrl, s: hdmi->unwedge_state); |
328 | msleep(msecs: 10); |
329 | pinctrl_select_state(p: hdmi->pinctrl, s: hdmi->default_state); |
330 | |
331 | return true; |
332 | } |
333 | |
334 | static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi) |
335 | { |
336 | struct dw_hdmi_i2c *i2c = hdmi->i2c; |
337 | int stat; |
338 | |
339 | stat = wait_for_completion_timeout(x: &i2c->cmp, HZ / 10); |
340 | if (!stat) { |
341 | /* If we can't unwedge, return timeout */ |
342 | if (!dw_hdmi_i2c_unwedge(hdmi)) |
343 | return -EAGAIN; |
344 | |
345 | /* We tried to unwedge; give it another chance */ |
346 | stat = wait_for_completion_timeout(x: &i2c->cmp, HZ / 10); |
347 | if (!stat) |
348 | return -EAGAIN; |
349 | } |
350 | |
351 | /* Check for error condition on the bus */ |
352 | if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) |
353 | return -EIO; |
354 | |
355 | return 0; |
356 | } |
357 | |
358 | static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, |
359 | unsigned char *buf, unsigned int length) |
360 | { |
361 | struct dw_hdmi_i2c *i2c = hdmi->i2c; |
362 | int ret; |
363 | |
364 | if (!i2c->is_regaddr) { |
365 | dev_dbg(hdmi->dev, "set read register address to 0\n" ); |
366 | i2c->slave_reg = 0x00; |
367 | i2c->is_regaddr = true; |
368 | } |
369 | |
370 | while (length--) { |
371 | reinit_completion(x: &i2c->cmp); |
372 | |
373 | hdmi_writeb(hdmi, val: i2c->slave_reg++, HDMI_I2CM_ADDRESS); |
374 | if (i2c->is_segment) |
375 | hdmi_writeb(hdmi, val: HDMI_I2CM_OPERATION_READ_EXT, |
376 | HDMI_I2CM_OPERATION); |
377 | else |
378 | hdmi_writeb(hdmi, val: HDMI_I2CM_OPERATION_READ, |
379 | HDMI_I2CM_OPERATION); |
380 | |
381 | ret = dw_hdmi_i2c_wait(hdmi); |
382 | if (ret) |
383 | return ret; |
384 | |
385 | *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); |
386 | } |
387 | i2c->is_segment = false; |
388 | |
389 | return 0; |
390 | } |
391 | |
392 | static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, |
393 | unsigned char *buf, unsigned int length) |
394 | { |
395 | struct dw_hdmi_i2c *i2c = hdmi->i2c; |
396 | int ret; |
397 | |
398 | if (!i2c->is_regaddr) { |
399 | /* Use the first write byte as register address */ |
400 | i2c->slave_reg = buf[0]; |
401 | length--; |
402 | buf++; |
403 | i2c->is_regaddr = true; |
404 | } |
405 | |
406 | while (length--) { |
407 | reinit_completion(x: &i2c->cmp); |
408 | |
409 | hdmi_writeb(hdmi, val: *buf++, HDMI_I2CM_DATAO); |
410 | hdmi_writeb(hdmi, val: i2c->slave_reg++, HDMI_I2CM_ADDRESS); |
411 | hdmi_writeb(hdmi, val: HDMI_I2CM_OPERATION_WRITE, |
412 | HDMI_I2CM_OPERATION); |
413 | |
414 | ret = dw_hdmi_i2c_wait(hdmi); |
415 | if (ret) |
416 | return ret; |
417 | } |
418 | |
419 | return 0; |
420 | } |
421 | |
422 | static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, |
423 | struct i2c_msg *msgs, int num) |
424 | { |
425 | struct dw_hdmi *hdmi = i2c_get_adapdata(adap); |
426 | struct dw_hdmi_i2c *i2c = hdmi->i2c; |
427 | u8 addr = msgs[0].addr; |
428 | int i, ret = 0; |
429 | |
430 | if (addr == DDC_CI_ADDR) |
431 | /* |
432 | * The internal I2C controller does not support the multi-byte |
433 | * read and write operations needed for DDC/CI. |
434 | * TOFIX: Blacklist the DDC/CI address until we filter out |
435 | * unsupported I2C operations. |
436 | */ |
437 | return -EOPNOTSUPP; |
438 | |
439 | dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n" , num, addr); |
440 | |
441 | for (i = 0; i < num; i++) { |
442 | if (msgs[i].len == 0) { |
443 | dev_dbg(hdmi->dev, |
444 | "unsupported transfer %d/%d, no data\n" , |
445 | i + 1, num); |
446 | return -EOPNOTSUPP; |
447 | } |
448 | } |
449 | |
450 | mutex_lock(&i2c->lock); |
451 | |
452 | /* Unmute DONE and ERROR interrupts */ |
453 | hdmi_writeb(hdmi, val: 0x00, HDMI_IH_MUTE_I2CM_STAT0); |
454 | |
455 | /* Set slave device address taken from the first I2C message */ |
456 | hdmi_writeb(hdmi, val: addr, HDMI_I2CM_SLAVE); |
457 | |
458 | /* Set slave device register address on transfer */ |
459 | i2c->is_regaddr = false; |
460 | |
461 | /* Set segment pointer for I2C extended read mode operation */ |
462 | i2c->is_segment = false; |
463 | |
464 | for (i = 0; i < num; i++) { |
465 | dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n" , |
466 | i + 1, num, msgs[i].len, msgs[i].flags); |
467 | if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { |
468 | i2c->is_segment = true; |
469 | hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); |
470 | hdmi_writeb(hdmi, val: *msgs[i].buf, HDMI_I2CM_SEGPTR); |
471 | } else { |
472 | if (msgs[i].flags & I2C_M_RD) |
473 | ret = dw_hdmi_i2c_read(hdmi, buf: msgs[i].buf, |
474 | length: msgs[i].len); |
475 | else |
476 | ret = dw_hdmi_i2c_write(hdmi, buf: msgs[i].buf, |
477 | length: msgs[i].len); |
478 | } |
479 | if (ret < 0) |
480 | break; |
481 | } |
482 | |
483 | if (!ret) |
484 | ret = num; |
485 | |
486 | /* Mute DONE and ERROR interrupts */ |
487 | hdmi_writeb(hdmi, val: HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, |
488 | HDMI_IH_MUTE_I2CM_STAT0); |
489 | |
490 | mutex_unlock(lock: &i2c->lock); |
491 | |
492 | return ret; |
493 | } |
494 | |
495 | static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) |
496 | { |
497 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
498 | } |
499 | |
500 | static const struct i2c_algorithm dw_hdmi_algorithm = { |
501 | .master_xfer = dw_hdmi_i2c_xfer, |
502 | .functionality = dw_hdmi_i2c_func, |
503 | }; |
504 | |
505 | static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) |
506 | { |
507 | struct i2c_adapter *adap; |
508 | struct dw_hdmi_i2c *i2c; |
509 | int ret; |
510 | |
511 | i2c = devm_kzalloc(dev: hdmi->dev, size: sizeof(*i2c), GFP_KERNEL); |
512 | if (!i2c) |
513 | return ERR_PTR(error: -ENOMEM); |
514 | |
515 | mutex_init(&i2c->lock); |
516 | init_completion(x: &i2c->cmp); |
517 | |
518 | adap = &i2c->adap; |
519 | adap->owner = THIS_MODULE; |
520 | adap->dev.parent = hdmi->dev; |
521 | adap->algo = &dw_hdmi_algorithm; |
522 | strscpy(adap->name, "DesignWare HDMI" , sizeof(adap->name)); |
523 | i2c_set_adapdata(adap, data: hdmi); |
524 | |
525 | ret = i2c_add_adapter(adap); |
526 | if (ret) { |
527 | dev_warn(hdmi->dev, "cannot add %s I2C adapter\n" , adap->name); |
528 | devm_kfree(dev: hdmi->dev, p: i2c); |
529 | return ERR_PTR(error: ret); |
530 | } |
531 | |
532 | hdmi->i2c = i2c; |
533 | |
534 | dev_info(hdmi->dev, "registered %s I2C bus driver\n" , adap->name); |
535 | |
536 | return adap; |
537 | } |
538 | |
539 | static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, |
540 | unsigned int n) |
541 | { |
542 | /* Must be set/cleared first */ |
543 | hdmi_modb(hdmi, data: 0, mask: HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); |
544 | |
545 | /* nshift factor = 0 */ |
546 | hdmi_modb(hdmi, data: 0, mask: HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); |
547 | |
548 | /* Use automatic CTS generation mode when CTS is not set */ |
549 | if (cts) |
550 | hdmi_writeb(hdmi, val: ((cts >> 16) & |
551 | HDMI_AUD_CTS3_AUDCTS19_16_MASK) | |
552 | HDMI_AUD_CTS3_CTS_MANUAL, |
553 | HDMI_AUD_CTS3); |
554 | else |
555 | hdmi_writeb(hdmi, val: 0, HDMI_AUD_CTS3); |
556 | hdmi_writeb(hdmi, val: (cts >> 8) & 0xff, HDMI_AUD_CTS2); |
557 | hdmi_writeb(hdmi, val: cts & 0xff, HDMI_AUD_CTS1); |
558 | |
559 | hdmi_writeb(hdmi, val: (n >> 16) & 0x0f, HDMI_AUD_N3); |
560 | hdmi_writeb(hdmi, val: (n >> 8) & 0xff, HDMI_AUD_N2); |
561 | hdmi_writeb(hdmi, val: n & 0xff, HDMI_AUD_N1); |
562 | } |
563 | |
564 | static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) |
565 | { |
566 | unsigned int n = (128 * freq) / 1000; |
567 | unsigned int mult = 1; |
568 | |
569 | while (freq > 48000) { |
570 | mult *= 2; |
571 | freq /= 2; |
572 | } |
573 | |
574 | switch (freq) { |
575 | case 32000: |
576 | if (pixel_clk == 25175000) |
577 | n = 4576; |
578 | else if (pixel_clk == 27027000) |
579 | n = 4096; |
580 | else if (pixel_clk == 74176000 || pixel_clk == 148352000) |
581 | n = 11648; |
582 | else if (pixel_clk == 297000000) |
583 | n = 3072; |
584 | else |
585 | n = 4096; |
586 | n *= mult; |
587 | break; |
588 | |
589 | case 44100: |
590 | if (pixel_clk == 25175000) |
591 | n = 7007; |
592 | else if (pixel_clk == 74176000) |
593 | n = 17836; |
594 | else if (pixel_clk == 148352000) |
595 | n = 8918; |
596 | else if (pixel_clk == 297000000) |
597 | n = 4704; |
598 | else |
599 | n = 6272; |
600 | n *= mult; |
601 | break; |
602 | |
603 | case 48000: |
604 | if (pixel_clk == 25175000) |
605 | n = 6864; |
606 | else if (pixel_clk == 27027000) |
607 | n = 6144; |
608 | else if (pixel_clk == 74176000) |
609 | n = 11648; |
610 | else if (pixel_clk == 148352000) |
611 | n = 5824; |
612 | else if (pixel_clk == 297000000) |
613 | n = 5120; |
614 | else |
615 | n = 6144; |
616 | n *= mult; |
617 | break; |
618 | |
619 | default: |
620 | break; |
621 | } |
622 | |
623 | return n; |
624 | } |
625 | |
626 | /* |
627 | * When transmitting IEC60958 linear PCM audio, these registers allow to |
628 | * configure the channel status information of all the channel status |
629 | * bits in the IEC60958 frame. For the moment this configuration is only |
630 | * used when the I2S audio interface, General Purpose Audio (GPA), |
631 | * or AHB audio DMA (AHBAUDDMA) interface is active |
632 | * (for S/PDIF interface this information comes from the stream). |
633 | */ |
634 | void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, |
635 | u8 *channel_status) |
636 | { |
637 | /* |
638 | * Set channel status register for frequency and word length. |
639 | * Use default values for other registers. |
640 | */ |
641 | hdmi_writeb(hdmi, val: channel_status[3], HDMI_FC_AUDSCHNLS7); |
642 | hdmi_writeb(hdmi, val: channel_status[4], HDMI_FC_AUDSCHNLS8); |
643 | } |
644 | EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status); |
645 | |
646 | static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, |
647 | unsigned long pixel_clk, unsigned int sample_rate) |
648 | { |
649 | unsigned long ftdms = pixel_clk; |
650 | unsigned int n, cts; |
651 | u8 config3; |
652 | u64 tmp; |
653 | |
654 | n = hdmi_compute_n(freq: sample_rate, pixel_clk); |
655 | |
656 | config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); |
657 | |
658 | /* Compute CTS when using internal AHB audio or General Parallel audio*/ |
659 | if ((config3 & HDMI_CONFIG3_AHBAUDDMA) || (config3 & HDMI_CONFIG3_GPAUD)) { |
660 | /* |
661 | * Compute the CTS value from the N value. Note that CTS and N |
662 | * can be up to 20 bits in total, so we need 64-bit math. Also |
663 | * note that our TDMS clock is not fully accurate; it is |
664 | * accurate to kHz. This can introduce an unnecessary remainder |
665 | * in the calculation below, so we don't try to warn about that. |
666 | */ |
667 | tmp = (u64)ftdms * n; |
668 | do_div(tmp, 128 * sample_rate); |
669 | cts = tmp; |
670 | |
671 | dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n" , |
672 | __func__, sample_rate, |
673 | ftdms / 1000000, (ftdms / 1000) % 1000, |
674 | n, cts); |
675 | } else { |
676 | cts = 0; |
677 | } |
678 | |
679 | spin_lock_irq(lock: &hdmi->audio_lock); |
680 | hdmi->audio_n = n; |
681 | hdmi->audio_cts = cts; |
682 | hdmi_set_cts_n(hdmi, cts, n: hdmi->audio_enable ? n : 0); |
683 | spin_unlock_irq(lock: &hdmi->audio_lock); |
684 | } |
685 | |
686 | static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) |
687 | { |
688 | mutex_lock(&hdmi->audio_mutex); |
689 | hdmi_set_clk_regenerator(hdmi, pixel_clk: 74250000, sample_rate: hdmi->sample_rate); |
690 | mutex_unlock(lock: &hdmi->audio_mutex); |
691 | } |
692 | |
693 | static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) |
694 | { |
695 | mutex_lock(&hdmi->audio_mutex); |
696 | hdmi_set_clk_regenerator(hdmi, pixel_clk: hdmi->hdmi_data.video_mode.mtmdsclock, |
697 | sample_rate: hdmi->sample_rate); |
698 | mutex_unlock(lock: &hdmi->audio_mutex); |
699 | } |
700 | |
701 | void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width) |
702 | { |
703 | mutex_lock(&hdmi->audio_mutex); |
704 | hdmi->sample_width = width; |
705 | mutex_unlock(lock: &hdmi->audio_mutex); |
706 | } |
707 | EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_width); |
708 | |
709 | void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm) |
710 | { |
711 | mutex_lock(&hdmi->audio_mutex); |
712 | hdmi->sample_non_pcm = non_pcm; |
713 | mutex_unlock(lock: &hdmi->audio_mutex); |
714 | } |
715 | EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_non_pcm); |
716 | |
717 | void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) |
718 | { |
719 | mutex_lock(&hdmi->audio_mutex); |
720 | hdmi->sample_rate = rate; |
721 | hdmi_set_clk_regenerator(hdmi, pixel_clk: hdmi->hdmi_data.video_mode.mtmdsclock, |
722 | sample_rate: hdmi->sample_rate); |
723 | mutex_unlock(lock: &hdmi->audio_mutex); |
724 | } |
725 | EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); |
726 | |
727 | void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt) |
728 | { |
729 | u8 layout; |
730 | |
731 | mutex_lock(&hdmi->audio_mutex); |
732 | hdmi->channels = cnt; |
733 | |
734 | /* |
735 | * For >2 channel PCM audio, we need to select layout 1 |
736 | * and set an appropriate channel map. |
737 | */ |
738 | if (cnt > 2) |
739 | layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1; |
740 | else |
741 | layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0; |
742 | |
743 | hdmi_modb(hdmi, data: layout, mask: HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, |
744 | HDMI_FC_AUDSCONF); |
745 | |
746 | /* Set the audio infoframes channel count */ |
747 | hdmi_modb(hdmi, data: (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, |
748 | mask: HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0); |
749 | |
750 | mutex_unlock(lock: &hdmi->audio_mutex); |
751 | } |
752 | EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count); |
753 | |
754 | void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca) |
755 | { |
756 | mutex_lock(&hdmi->audio_mutex); |
757 | |
758 | hdmi_writeb(hdmi, val: ca, HDMI_FC_AUDICONF2); |
759 | |
760 | mutex_unlock(lock: &hdmi->audio_mutex); |
761 | } |
762 | EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation); |
763 | |
764 | static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) |
765 | { |
766 | if (enable) |
767 | hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; |
768 | else |
769 | hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; |
770 | hdmi_writeb(hdmi, val: hdmi->mc_clkdis, HDMI_MC_CLKDIS); |
771 | } |
772 | |
773 | static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi) |
774 | { |
775 | if (!hdmi->curr_conn) |
776 | return NULL; |
777 | |
778 | return hdmi->curr_conn->eld; |
779 | } |
780 | |
781 | static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi) |
782 | { |
783 | const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; |
784 | int sample_freq = 0x2, org_sample_freq = 0xD; |
785 | int ch_mask = BIT(hdmi->channels) - 1; |
786 | |
787 | switch (hdmi->sample_rate) { |
788 | case 32000: |
789 | sample_freq = 0x03; |
790 | org_sample_freq = 0x0C; |
791 | break; |
792 | case 44100: |
793 | sample_freq = 0x00; |
794 | org_sample_freq = 0x0F; |
795 | break; |
796 | case 48000: |
797 | sample_freq = 0x02; |
798 | org_sample_freq = 0x0D; |
799 | break; |
800 | case 88200: |
801 | sample_freq = 0x08; |
802 | org_sample_freq = 0x07; |
803 | break; |
804 | case 96000: |
805 | sample_freq = 0x0A; |
806 | org_sample_freq = 0x05; |
807 | break; |
808 | case 176400: |
809 | sample_freq = 0x0C; |
810 | org_sample_freq = 0x03; |
811 | break; |
812 | case 192000: |
813 | sample_freq = 0x0E; |
814 | org_sample_freq = 0x01; |
815 | break; |
816 | default: |
817 | break; |
818 | } |
819 | |
820 | hdmi_set_cts_n(hdmi, cts: hdmi->audio_cts, n: hdmi->audio_n); |
821 | hdmi_enable_audio_clk(hdmi, enable: true); |
822 | |
823 | hdmi_writeb(hdmi, val: 0x1, HDMI_FC_AUDSCHNLS0); |
824 | hdmi_writeb(hdmi, val: hdmi->channels, HDMI_FC_AUDSCHNLS2); |
825 | hdmi_writeb(hdmi, val: 0x22, HDMI_FC_AUDSCHNLS3); |
826 | hdmi_writeb(hdmi, val: 0x22, HDMI_FC_AUDSCHNLS4); |
827 | hdmi_writeb(hdmi, val: 0x11, HDMI_FC_AUDSCHNLS5); |
828 | hdmi_writeb(hdmi, val: 0x11, HDMI_FC_AUDSCHNLS6); |
829 | hdmi_writeb(hdmi, val: (0x3 << 4) | sample_freq, HDMI_FC_AUDSCHNLS7); |
830 | hdmi_writeb(hdmi, val: (org_sample_freq << 4) | 0xb, HDMI_FC_AUDSCHNLS8); |
831 | |
832 | hdmi_writeb(hdmi, val: ch_mask, HDMI_GP_CONF1); |
833 | hdmi_writeb(hdmi, val: 0x02, HDMI_GP_CONF2); |
834 | hdmi_writeb(hdmi, val: 0x01, HDMI_GP_CONF0); |
835 | |
836 | hdmi_modb(hdmi, data: 0x3, mask: 0x3, HDMI_FC_DATAUTO3); |
837 | |
838 | /* hbr */ |
839 | if (hdmi->sample_rate == 192000 && hdmi->channels == 8 && |
840 | hdmi->sample_width == 32 && hdmi->sample_non_pcm) |
841 | hdmi_modb(hdmi, data: 0x01, mask: 0x01, HDMI_GP_CONF2); |
842 | |
843 | if (pdata->enable_audio) |
844 | pdata->enable_audio(hdmi, |
845 | hdmi->channels, |
846 | hdmi->sample_width, |
847 | hdmi->sample_rate, |
848 | hdmi->sample_non_pcm); |
849 | } |
850 | |
851 | static void dw_hdmi_gp_audio_disable(struct dw_hdmi *hdmi) |
852 | { |
853 | const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; |
854 | |
855 | hdmi_set_cts_n(hdmi, cts: hdmi->audio_cts, n: 0); |
856 | |
857 | hdmi_modb(hdmi, data: 0, mask: 0x3, HDMI_FC_DATAUTO3); |
858 | if (pdata->disable_audio) |
859 | pdata->disable_audio(hdmi); |
860 | |
861 | hdmi_enable_audio_clk(hdmi, enable: false); |
862 | } |
863 | |
864 | static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) |
865 | { |
866 | hdmi_set_cts_n(hdmi, cts: hdmi->audio_cts, n: hdmi->audio_n); |
867 | } |
868 | |
869 | static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) |
870 | { |
871 | hdmi_set_cts_n(hdmi, cts: hdmi->audio_cts, n: 0); |
872 | } |
873 | |
874 | static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) |
875 | { |
876 | hdmi_set_cts_n(hdmi, cts: hdmi->audio_cts, n: hdmi->audio_n); |
877 | hdmi_enable_audio_clk(hdmi, enable: true); |
878 | } |
879 | |
880 | static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) |
881 | { |
882 | hdmi_enable_audio_clk(hdmi, enable: false); |
883 | } |
884 | |
885 | void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) |
886 | { |
887 | unsigned long flags; |
888 | |
889 | spin_lock_irqsave(&hdmi->audio_lock, flags); |
890 | hdmi->audio_enable = true; |
891 | if (hdmi->enable_audio) |
892 | hdmi->enable_audio(hdmi); |
893 | spin_unlock_irqrestore(lock: &hdmi->audio_lock, flags); |
894 | } |
895 | EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); |
896 | |
897 | void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) |
898 | { |
899 | unsigned long flags; |
900 | |
901 | spin_lock_irqsave(&hdmi->audio_lock, flags); |
902 | hdmi->audio_enable = false; |
903 | if (hdmi->disable_audio) |
904 | hdmi->disable_audio(hdmi); |
905 | spin_unlock_irqrestore(lock: &hdmi->audio_lock, flags); |
906 | } |
907 | EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); |
908 | |
909 | static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) |
910 | { |
911 | switch (bus_format) { |
912 | case MEDIA_BUS_FMT_RGB888_1X24: |
913 | case MEDIA_BUS_FMT_RGB101010_1X30: |
914 | case MEDIA_BUS_FMT_RGB121212_1X36: |
915 | case MEDIA_BUS_FMT_RGB161616_1X48: |
916 | return true; |
917 | |
918 | default: |
919 | return false; |
920 | } |
921 | } |
922 | |
923 | static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) |
924 | { |
925 | switch (bus_format) { |
926 | case MEDIA_BUS_FMT_YUV8_1X24: |
927 | case MEDIA_BUS_FMT_YUV10_1X30: |
928 | case MEDIA_BUS_FMT_YUV12_1X36: |
929 | case MEDIA_BUS_FMT_YUV16_1X48: |
930 | return true; |
931 | |
932 | default: |
933 | return false; |
934 | } |
935 | } |
936 | |
937 | static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) |
938 | { |
939 | switch (bus_format) { |
940 | case MEDIA_BUS_FMT_UYVY8_1X16: |
941 | case MEDIA_BUS_FMT_UYVY10_1X20: |
942 | case MEDIA_BUS_FMT_UYVY12_1X24: |
943 | return true; |
944 | |
945 | default: |
946 | return false; |
947 | } |
948 | } |
949 | |
950 | static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) |
951 | { |
952 | switch (bus_format) { |
953 | case MEDIA_BUS_FMT_UYYVYY8_0_5X24: |
954 | case MEDIA_BUS_FMT_UYYVYY10_0_5X30: |
955 | case MEDIA_BUS_FMT_UYYVYY12_0_5X36: |
956 | case MEDIA_BUS_FMT_UYYVYY16_0_5X48: |
957 | return true; |
958 | |
959 | default: |
960 | return false; |
961 | } |
962 | } |
963 | |
964 | static int hdmi_bus_fmt_color_depth(unsigned int bus_format) |
965 | { |
966 | switch (bus_format) { |
967 | case MEDIA_BUS_FMT_RGB888_1X24: |
968 | case MEDIA_BUS_FMT_YUV8_1X24: |
969 | case MEDIA_BUS_FMT_UYVY8_1X16: |
970 | case MEDIA_BUS_FMT_UYYVYY8_0_5X24: |
971 | return 8; |
972 | |
973 | case MEDIA_BUS_FMT_RGB101010_1X30: |
974 | case MEDIA_BUS_FMT_YUV10_1X30: |
975 | case MEDIA_BUS_FMT_UYVY10_1X20: |
976 | case MEDIA_BUS_FMT_UYYVYY10_0_5X30: |
977 | return 10; |
978 | |
979 | case MEDIA_BUS_FMT_RGB121212_1X36: |
980 | case MEDIA_BUS_FMT_YUV12_1X36: |
981 | case MEDIA_BUS_FMT_UYVY12_1X24: |
982 | case MEDIA_BUS_FMT_UYYVYY12_0_5X36: |
983 | return 12; |
984 | |
985 | case MEDIA_BUS_FMT_RGB161616_1X48: |
986 | case MEDIA_BUS_FMT_YUV16_1X48: |
987 | case MEDIA_BUS_FMT_UYYVYY16_0_5X48: |
988 | return 16; |
989 | |
990 | default: |
991 | return 0; |
992 | } |
993 | } |
994 | |
995 | /* |
996 | * this submodule is responsible for the video data synchronization. |
997 | * for example, for RGB 4:4:4 input, the data map is defined as |
998 | * pin{47~40} <==> R[7:0] |
999 | * pin{31~24} <==> G[7:0] |
1000 | * pin{15~8} <==> B[7:0] |
1001 | */ |
1002 | static void hdmi_video_sample(struct dw_hdmi *hdmi) |
1003 | { |
1004 | int color_format = 0; |
1005 | u8 val; |
1006 | |
1007 | switch (hdmi->hdmi_data.enc_in_bus_format) { |
1008 | case MEDIA_BUS_FMT_RGB888_1X24: |
1009 | color_format = 0x01; |
1010 | break; |
1011 | case MEDIA_BUS_FMT_RGB101010_1X30: |
1012 | color_format = 0x03; |
1013 | break; |
1014 | case MEDIA_BUS_FMT_RGB121212_1X36: |
1015 | color_format = 0x05; |
1016 | break; |
1017 | case MEDIA_BUS_FMT_RGB161616_1X48: |
1018 | color_format = 0x07; |
1019 | break; |
1020 | |
1021 | case MEDIA_BUS_FMT_YUV8_1X24: |
1022 | case MEDIA_BUS_FMT_UYYVYY8_0_5X24: |
1023 | color_format = 0x09; |
1024 | break; |
1025 | case MEDIA_BUS_FMT_YUV10_1X30: |
1026 | case MEDIA_BUS_FMT_UYYVYY10_0_5X30: |
1027 | color_format = 0x0B; |
1028 | break; |
1029 | case MEDIA_BUS_FMT_YUV12_1X36: |
1030 | case MEDIA_BUS_FMT_UYYVYY12_0_5X36: |
1031 | color_format = 0x0D; |
1032 | break; |
1033 | case MEDIA_BUS_FMT_YUV16_1X48: |
1034 | case MEDIA_BUS_FMT_UYYVYY16_0_5X48: |
1035 | color_format = 0x0F; |
1036 | break; |
1037 | |
1038 | case MEDIA_BUS_FMT_UYVY8_1X16: |
1039 | color_format = 0x16; |
1040 | break; |
1041 | case MEDIA_BUS_FMT_UYVY10_1X20: |
1042 | color_format = 0x14; |
1043 | break; |
1044 | case MEDIA_BUS_FMT_UYVY12_1X24: |
1045 | color_format = 0x12; |
1046 | break; |
1047 | |
1048 | default: |
1049 | return; |
1050 | } |
1051 | |
1052 | val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | |
1053 | ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & |
1054 | HDMI_TX_INVID0_VIDEO_MAPPING_MASK); |
1055 | hdmi_writeb(hdmi, val, HDMI_TX_INVID0); |
1056 | |
1057 | /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ |
1058 | val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | |
1059 | HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | |
1060 | HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; |
1061 | hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); |
1062 | hdmi_writeb(hdmi, val: 0x0, HDMI_TX_GYDATA0); |
1063 | hdmi_writeb(hdmi, val: 0x0, HDMI_TX_GYDATA1); |
1064 | hdmi_writeb(hdmi, val: 0x0, HDMI_TX_RCRDATA0); |
1065 | hdmi_writeb(hdmi, val: 0x0, HDMI_TX_RCRDATA1); |
1066 | hdmi_writeb(hdmi, val: 0x0, HDMI_TX_BCBDATA0); |
1067 | hdmi_writeb(hdmi, val: 0x0, HDMI_TX_BCBDATA1); |
1068 | } |
1069 | |
1070 | static int is_color_space_conversion(struct dw_hdmi *hdmi) |
1071 | { |
1072 | struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; |
1073 | bool is_input_rgb, is_output_rgb; |
1074 | |
1075 | is_input_rgb = hdmi_bus_fmt_is_rgb(bus_format: hdmi_data->enc_in_bus_format); |
1076 | is_output_rgb = hdmi_bus_fmt_is_rgb(bus_format: hdmi_data->enc_out_bus_format); |
1077 | |
1078 | return (is_input_rgb != is_output_rgb) || |
1079 | (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range); |
1080 | } |
1081 | |
1082 | static int is_color_space_decimation(struct dw_hdmi *hdmi) |
1083 | { |
1084 | if (!hdmi_bus_fmt_is_yuv422(bus_format: hdmi->hdmi_data.enc_out_bus_format)) |
1085 | return 0; |
1086 | |
1087 | if (hdmi_bus_fmt_is_rgb(bus_format: hdmi->hdmi_data.enc_in_bus_format) || |
1088 | hdmi_bus_fmt_is_yuv444(bus_format: hdmi->hdmi_data.enc_in_bus_format)) |
1089 | return 1; |
1090 | |
1091 | return 0; |
1092 | } |
1093 | |
1094 | static int is_color_space_interpolation(struct dw_hdmi *hdmi) |
1095 | { |
1096 | if (!hdmi_bus_fmt_is_yuv422(bus_format: hdmi->hdmi_data.enc_in_bus_format)) |
1097 | return 0; |
1098 | |
1099 | if (hdmi_bus_fmt_is_rgb(bus_format: hdmi->hdmi_data.enc_out_bus_format) || |
1100 | hdmi_bus_fmt_is_yuv444(bus_format: hdmi->hdmi_data.enc_out_bus_format)) |
1101 | return 1; |
1102 | |
1103 | return 0; |
1104 | } |
1105 | |
1106 | static bool is_csc_needed(struct dw_hdmi *hdmi) |
1107 | { |
1108 | return is_color_space_conversion(hdmi) || |
1109 | is_color_space_decimation(hdmi) || |
1110 | is_color_space_interpolation(hdmi); |
1111 | } |
1112 | |
1113 | static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) |
1114 | { |
1115 | const u16 (*csc_coeff)[3][4] = &csc_coeff_default; |
1116 | bool is_input_rgb, is_output_rgb; |
1117 | unsigned i; |
1118 | u32 csc_scale = 1; |
1119 | |
1120 | is_input_rgb = hdmi_bus_fmt_is_rgb(bus_format: hdmi->hdmi_data.enc_in_bus_format); |
1121 | is_output_rgb = hdmi_bus_fmt_is_rgb(bus_format: hdmi->hdmi_data.enc_out_bus_format); |
1122 | |
1123 | if (!is_input_rgb && is_output_rgb) { |
1124 | if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) |
1125 | csc_coeff = &csc_coeff_rgb_out_eitu601; |
1126 | else |
1127 | csc_coeff = &csc_coeff_rgb_out_eitu709; |
1128 | } else if (is_input_rgb && !is_output_rgb) { |
1129 | if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) |
1130 | csc_coeff = &csc_coeff_rgb_in_eitu601; |
1131 | else |
1132 | csc_coeff = &csc_coeff_rgb_in_eitu709; |
1133 | csc_scale = 0; |
1134 | } else if (is_input_rgb && is_output_rgb && |
1135 | hdmi->hdmi_data.rgb_limited_range) { |
1136 | csc_coeff = &csc_coeff_rgb_full_to_rgb_limited; |
1137 | } |
1138 | |
1139 | /* The CSC registers are sequential, alternating MSB then LSB */ |
1140 | for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { |
1141 | u16 coeff_a = (*csc_coeff)[0][i]; |
1142 | u16 coeff_b = (*csc_coeff)[1][i]; |
1143 | u16 coeff_c = (*csc_coeff)[2][i]; |
1144 | |
1145 | hdmi_writeb(hdmi, val: coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); |
1146 | hdmi_writeb(hdmi, val: coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); |
1147 | hdmi_writeb(hdmi, val: coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); |
1148 | hdmi_writeb(hdmi, val: coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); |
1149 | hdmi_writeb(hdmi, val: coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); |
1150 | hdmi_writeb(hdmi, val: coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); |
1151 | } |
1152 | |
1153 | hdmi_modb(hdmi, data: csc_scale, mask: HDMI_CSC_SCALE_CSCSCALE_MASK, |
1154 | HDMI_CSC_SCALE); |
1155 | } |
1156 | |
1157 | static void hdmi_video_csc(struct dw_hdmi *hdmi) |
1158 | { |
1159 | int color_depth = 0; |
1160 | int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; |
1161 | int decimation = 0; |
1162 | |
1163 | /* YCC422 interpolation to 444 mode */ |
1164 | if (is_color_space_interpolation(hdmi)) |
1165 | interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; |
1166 | else if (is_color_space_decimation(hdmi)) |
1167 | decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; |
1168 | |
1169 | switch (hdmi_bus_fmt_color_depth(bus_format: hdmi->hdmi_data.enc_out_bus_format)) { |
1170 | case 8: |
1171 | color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; |
1172 | break; |
1173 | case 10: |
1174 | color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; |
1175 | break; |
1176 | case 12: |
1177 | color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; |
1178 | break; |
1179 | case 16: |
1180 | color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; |
1181 | break; |
1182 | |
1183 | default: |
1184 | return; |
1185 | } |
1186 | |
1187 | /* Configure the CSC registers */ |
1188 | hdmi_writeb(hdmi, val: interpolation | decimation, HDMI_CSC_CFG); |
1189 | hdmi_modb(hdmi, data: color_depth, mask: HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, |
1190 | HDMI_CSC_SCALE); |
1191 | |
1192 | dw_hdmi_update_csc_coeffs(hdmi); |
1193 | } |
1194 | |
1195 | /* |
1196 | * HDMI video packetizer is used to packetize the data. |
1197 | * for example, if input is YCC422 mode or repeater is used, |
1198 | * data should be repacked this module can be bypassed. |
1199 | */ |
1200 | static void hdmi_video_packetize(struct dw_hdmi *hdmi) |
1201 | { |
1202 | unsigned int color_depth = 0; |
1203 | unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; |
1204 | unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; |
1205 | struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; |
1206 | u8 val, vp_conf; |
1207 | u8 clear_gcp_auto = 0; |
1208 | |
1209 | |
1210 | if (hdmi_bus_fmt_is_rgb(bus_format: hdmi->hdmi_data.enc_out_bus_format) || |
1211 | hdmi_bus_fmt_is_yuv444(bus_format: hdmi->hdmi_data.enc_out_bus_format) || |
1212 | hdmi_bus_fmt_is_yuv420(bus_format: hdmi->hdmi_data.enc_out_bus_format)) { |
1213 | switch (hdmi_bus_fmt_color_depth( |
1214 | bus_format: hdmi->hdmi_data.enc_out_bus_format)) { |
1215 | case 8: |
1216 | color_depth = 4; |
1217 | output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; |
1218 | clear_gcp_auto = 1; |
1219 | break; |
1220 | case 10: |
1221 | color_depth = 5; |
1222 | break; |
1223 | case 12: |
1224 | color_depth = 6; |
1225 | break; |
1226 | case 16: |
1227 | color_depth = 7; |
1228 | break; |
1229 | default: |
1230 | output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; |
1231 | } |
1232 | } else if (hdmi_bus_fmt_is_yuv422(bus_format: hdmi->hdmi_data.enc_out_bus_format)) { |
1233 | switch (hdmi_bus_fmt_color_depth( |
1234 | bus_format: hdmi->hdmi_data.enc_out_bus_format)) { |
1235 | case 0: |
1236 | case 8: |
1237 | remap_size = HDMI_VP_REMAP_YCC422_16bit; |
1238 | clear_gcp_auto = 1; |
1239 | break; |
1240 | case 10: |
1241 | remap_size = HDMI_VP_REMAP_YCC422_20bit; |
1242 | break; |
1243 | case 12: |
1244 | remap_size = HDMI_VP_REMAP_YCC422_24bit; |
1245 | break; |
1246 | |
1247 | default: |
1248 | return; |
1249 | } |
1250 | output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; |
1251 | } else { |
1252 | return; |
1253 | } |
1254 | |
1255 | /* set the packetizer registers */ |
1256 | val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & |
1257 | HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | |
1258 | ((hdmi_data->pix_repet_factor << |
1259 | HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & |
1260 | HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); |
1261 | hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); |
1262 | |
1263 | /* HDMI1.4b specification section 6.5.3: |
1264 | * Source shall only send GCPs with non-zero CD to sinks |
1265 | * that indicate support for Deep Color. |
1266 | * GCP only transmit CD and do not handle AVMUTE, PP norDefault_Phase (yet). |
1267 | * Disable Auto GCP when 24-bit color for sinks that not support Deep Color. |
1268 | */ |
1269 | val = hdmi_readb(hdmi, HDMI_FC_DATAUTO3); |
1270 | if (clear_gcp_auto == 1) |
1271 | val &= ~HDMI_FC_DATAUTO3_GCP_AUTO; |
1272 | else |
1273 | val |= HDMI_FC_DATAUTO3_GCP_AUTO; |
1274 | hdmi_writeb(hdmi, val, HDMI_FC_DATAUTO3); |
1275 | |
1276 | hdmi_modb(hdmi, data: HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, |
1277 | mask: HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); |
1278 | |
1279 | /* Data from pixel repeater block */ |
1280 | if (hdmi_data->pix_repet_factor > 1) { |
1281 | vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | |
1282 | HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; |
1283 | } else { /* data from packetizer block */ |
1284 | vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | |
1285 | HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; |
1286 | } |
1287 | |
1288 | hdmi_modb(hdmi, data: vp_conf, |
1289 | mask: HDMI_VP_CONF_PR_EN_MASK | |
1290 | HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); |
1291 | |
1292 | hdmi_modb(hdmi, data: 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, |
1293 | mask: HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); |
1294 | |
1295 | hdmi_writeb(hdmi, val: remap_size, HDMI_VP_REMAP); |
1296 | |
1297 | if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { |
1298 | vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | |
1299 | HDMI_VP_CONF_PP_EN_ENABLE | |
1300 | HDMI_VP_CONF_YCC422_EN_DISABLE; |
1301 | } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { |
1302 | vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | |
1303 | HDMI_VP_CONF_PP_EN_DISABLE | |
1304 | HDMI_VP_CONF_YCC422_EN_ENABLE; |
1305 | } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { |
1306 | vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | |
1307 | HDMI_VP_CONF_PP_EN_DISABLE | |
1308 | HDMI_VP_CONF_YCC422_EN_DISABLE; |
1309 | } else { |
1310 | return; |
1311 | } |
1312 | |
1313 | hdmi_modb(hdmi, data: vp_conf, |
1314 | mask: HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | |
1315 | HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); |
1316 | |
1317 | hdmi_modb(hdmi, data: HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | |
1318 | HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, |
1319 | mask: HDMI_VP_STUFF_PP_STUFFING_MASK | |
1320 | HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); |
1321 | |
1322 | hdmi_modb(hdmi, data: output_select, mask: HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, |
1323 | HDMI_VP_CONF); |
1324 | } |
1325 | |
1326 | /* ----------------------------------------------------------------------------- |
1327 | * Synopsys PHY Handling |
1328 | */ |
1329 | |
1330 | static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, |
1331 | unsigned char bit) |
1332 | { |
1333 | hdmi_modb(hdmi, data: bit << HDMI_PHY_TST0_TSTCLR_OFFSET, |
1334 | mask: HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); |
1335 | } |
1336 | |
1337 | static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) |
1338 | { |
1339 | u32 val; |
1340 | |
1341 | while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { |
1342 | if (msec-- == 0) |
1343 | return false; |
1344 | udelay(1000); |
1345 | } |
1346 | hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); |
1347 | |
1348 | return true; |
1349 | } |
1350 | |
1351 | void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, |
1352 | unsigned char addr) |
1353 | { |
1354 | hdmi_writeb(hdmi, val: 0xFF, HDMI_IH_I2CMPHY_STAT0); |
1355 | hdmi_writeb(hdmi, val: addr, HDMI_PHY_I2CM_ADDRESS_ADDR); |
1356 | hdmi_writeb(hdmi, val: (unsigned char)(data >> 8), |
1357 | HDMI_PHY_I2CM_DATAO_1_ADDR); |
1358 | hdmi_writeb(hdmi, val: (unsigned char)(data >> 0), |
1359 | HDMI_PHY_I2CM_DATAO_0_ADDR); |
1360 | hdmi_writeb(hdmi, val: HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, |
1361 | HDMI_PHY_I2CM_OPERATION_ADDR); |
1362 | hdmi_phy_wait_i2c_done(hdmi, msec: 1000); |
1363 | } |
1364 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); |
1365 | |
1366 | /* Filter out invalid setups to avoid configuring SCDC and scrambling */ |
1367 | static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi, |
1368 | const struct drm_display_info *display) |
1369 | { |
1370 | /* Completely disable SCDC support for older controllers */ |
1371 | if (hdmi->version < 0x200a) |
1372 | return false; |
1373 | |
1374 | /* Disable if no DDC bus */ |
1375 | if (!hdmi->ddc) |
1376 | return false; |
1377 | |
1378 | /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ |
1379 | if (!display->hdmi.scdc.supported || |
1380 | !display->hdmi.scdc.scrambling.supported) |
1381 | return false; |
1382 | |
1383 | /* |
1384 | * Disable if display only support low TMDS rates and scrambling |
1385 | * for low rates is not supported either |
1386 | */ |
1387 | if (!display->hdmi.scdc.scrambling.low_rates && |
1388 | display->max_tmds_clock <= 340000) |
1389 | return false; |
1390 | |
1391 | return true; |
1392 | } |
1393 | |
1394 | /* |
1395 | * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: |
1396 | * - The Source shall suspend transmission of the TMDS clock and data |
1397 | * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it |
1398 | * from a 0 to a 1 or from a 1 to a 0 |
1399 | * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from |
1400 | * the time the TMDS_Bit_Clock_Ratio bit is written until resuming |
1401 | * transmission of TMDS clock and data |
1402 | * |
1403 | * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() |
1404 | * helper should called right before enabling the TMDS Clock and Data in |
1405 | * the PHY configuration callback. |
1406 | */ |
1407 | void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi, |
1408 | const struct drm_display_info *display) |
1409 | { |
1410 | unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; |
1411 | |
1412 | /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ |
1413 | if (dw_hdmi_support_scdc(hdmi, display)) { |
1414 | if (mtmdsclock > HDMI14_MAX_TMDSCLK) |
1415 | drm_scdc_set_high_tmds_clock_ratio(connector: hdmi->curr_conn, set: 1); |
1416 | else |
1417 | drm_scdc_set_high_tmds_clock_ratio(connector: hdmi->curr_conn, set: 0); |
1418 | } |
1419 | } |
1420 | EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); |
1421 | |
1422 | static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) |
1423 | { |
1424 | hdmi_mask_writeb(hdmi, data: !enable, HDMI_PHY_CONF0, |
1425 | shift: HDMI_PHY_CONF0_PDZ_OFFSET, |
1426 | mask: HDMI_PHY_CONF0_PDZ_MASK); |
1427 | } |
1428 | |
1429 | static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) |
1430 | { |
1431 | hdmi_mask_writeb(hdmi, data: enable, HDMI_PHY_CONF0, |
1432 | shift: HDMI_PHY_CONF0_ENTMDS_OFFSET, |
1433 | mask: HDMI_PHY_CONF0_ENTMDS_MASK); |
1434 | } |
1435 | |
1436 | static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) |
1437 | { |
1438 | hdmi_mask_writeb(hdmi, data: enable, HDMI_PHY_CONF0, |
1439 | shift: HDMI_PHY_CONF0_SVSRET_OFFSET, |
1440 | mask: HDMI_PHY_CONF0_SVSRET_MASK); |
1441 | } |
1442 | |
1443 | void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) |
1444 | { |
1445 | hdmi_mask_writeb(hdmi, data: enable, HDMI_PHY_CONF0, |
1446 | shift: HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, |
1447 | mask: HDMI_PHY_CONF0_GEN2_PDDQ_MASK); |
1448 | } |
1449 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); |
1450 | |
1451 | void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) |
1452 | { |
1453 | hdmi_mask_writeb(hdmi, data: enable, HDMI_PHY_CONF0, |
1454 | shift: HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, |
1455 | mask: HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); |
1456 | } |
1457 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); |
1458 | |
1459 | static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) |
1460 | { |
1461 | hdmi_mask_writeb(hdmi, data: enable, HDMI_PHY_CONF0, |
1462 | shift: HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, |
1463 | mask: HDMI_PHY_CONF0_SELDATAENPOL_MASK); |
1464 | } |
1465 | |
1466 | static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) |
1467 | { |
1468 | hdmi_mask_writeb(hdmi, data: enable, HDMI_PHY_CONF0, |
1469 | shift: HDMI_PHY_CONF0_SELDIPIF_OFFSET, |
1470 | mask: HDMI_PHY_CONF0_SELDIPIF_MASK); |
1471 | } |
1472 | |
1473 | void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi) |
1474 | { |
1475 | /* PHY reset. The reset signal is active low on Gen1 PHYs. */ |
1476 | hdmi_writeb(hdmi, val: 0, HDMI_MC_PHYRSTZ); |
1477 | hdmi_writeb(hdmi, val: HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); |
1478 | } |
1479 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset); |
1480 | |
1481 | void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi) |
1482 | { |
1483 | /* PHY reset. The reset signal is active high on Gen2 PHYs. */ |
1484 | hdmi_writeb(hdmi, val: HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); |
1485 | hdmi_writeb(hdmi, val: 0, HDMI_MC_PHYRSTZ); |
1486 | } |
1487 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset); |
1488 | |
1489 | void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) |
1490 | { |
1491 | hdmi_phy_test_clear(hdmi, bit: 1); |
1492 | hdmi_writeb(hdmi, val: address, HDMI_PHY_I2CM_SLAVE_ADDR); |
1493 | hdmi_phy_test_clear(hdmi, bit: 0); |
1494 | } |
1495 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); |
1496 | |
1497 | static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) |
1498 | { |
1499 | const struct dw_hdmi_phy_data *phy = hdmi->phy.data; |
1500 | unsigned int i; |
1501 | u16 val; |
1502 | |
1503 | if (phy->gen == 1) { |
1504 | dw_hdmi_phy_enable_tmds(hdmi, enable: 0); |
1505 | dw_hdmi_phy_enable_powerdown(hdmi, enable: true); |
1506 | return; |
1507 | } |
1508 | |
1509 | dw_hdmi_phy_gen2_txpwron(hdmi, 0); |
1510 | |
1511 | /* |
1512 | * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went |
1513 | * to low power mode. |
1514 | */ |
1515 | for (i = 0; i < 5; ++i) { |
1516 | val = hdmi_readb(hdmi, HDMI_PHY_STAT0); |
1517 | if (!(val & HDMI_PHY_TX_PHY_LOCK)) |
1518 | break; |
1519 | |
1520 | usleep_range(min: 1000, max: 2000); |
1521 | } |
1522 | |
1523 | if (val & HDMI_PHY_TX_PHY_LOCK) |
1524 | dev_warn(hdmi->dev, "PHY failed to power down\n" ); |
1525 | else |
1526 | dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n" , i); |
1527 | |
1528 | dw_hdmi_phy_gen2_pddq(hdmi, 1); |
1529 | } |
1530 | |
1531 | static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) |
1532 | { |
1533 | const struct dw_hdmi_phy_data *phy = hdmi->phy.data; |
1534 | unsigned int i; |
1535 | u8 val; |
1536 | |
1537 | if (phy->gen == 1) { |
1538 | dw_hdmi_phy_enable_powerdown(hdmi, enable: false); |
1539 | |
1540 | /* Toggle TMDS enable. */ |
1541 | dw_hdmi_phy_enable_tmds(hdmi, enable: 0); |
1542 | dw_hdmi_phy_enable_tmds(hdmi, enable: 1); |
1543 | return 0; |
1544 | } |
1545 | |
1546 | dw_hdmi_phy_gen2_txpwron(hdmi, 1); |
1547 | dw_hdmi_phy_gen2_pddq(hdmi, 0); |
1548 | |
1549 | /* Wait for PHY PLL lock */ |
1550 | for (i = 0; i < 5; ++i) { |
1551 | val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; |
1552 | if (val) |
1553 | break; |
1554 | |
1555 | usleep_range(min: 1000, max: 2000); |
1556 | } |
1557 | |
1558 | if (!val) { |
1559 | dev_err(hdmi->dev, "PHY PLL failed to lock\n" ); |
1560 | return -ETIMEDOUT; |
1561 | } |
1562 | |
1563 | dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n" , i); |
1564 | return 0; |
1565 | } |
1566 | |
1567 | /* |
1568 | * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available |
1569 | * information the DWC MHL PHY has the same register layout and is thus also |
1570 | * supported by this function. |
1571 | */ |
1572 | static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, |
1573 | const struct dw_hdmi_plat_data *pdata, |
1574 | unsigned long mpixelclock) |
1575 | { |
1576 | const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; |
1577 | const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; |
1578 | const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; |
1579 | |
1580 | /* TOFIX Will need 420 specific PHY configuration tables */ |
1581 | |
1582 | /* PLL/MPLL Cfg - always match on final entry */ |
1583 | for (; mpll_config->mpixelclock != ~0UL; mpll_config++) |
1584 | if (mpixelclock <= mpll_config->mpixelclock) |
1585 | break; |
1586 | |
1587 | for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) |
1588 | if (mpixelclock <= curr_ctrl->mpixelclock) |
1589 | break; |
1590 | |
1591 | for (; phy_config->mpixelclock != ~0UL; phy_config++) |
1592 | if (mpixelclock <= phy_config->mpixelclock) |
1593 | break; |
1594 | |
1595 | if (mpll_config->mpixelclock == ~0UL || |
1596 | curr_ctrl->mpixelclock == ~0UL || |
1597 | phy_config->mpixelclock == ~0UL) |
1598 | return -EINVAL; |
1599 | |
1600 | dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, |
1601 | HDMI_3D_TX_PHY_CPCE_CTRL); |
1602 | dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, |
1603 | HDMI_3D_TX_PHY_GMPCTRL); |
1604 | dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], |
1605 | HDMI_3D_TX_PHY_CURRCTRL); |
1606 | |
1607 | dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); |
1608 | dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, |
1609 | HDMI_3D_TX_PHY_MSM_CTRL); |
1610 | |
1611 | dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); |
1612 | dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, |
1613 | HDMI_3D_TX_PHY_CKSYMTXCTRL); |
1614 | dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, |
1615 | HDMI_3D_TX_PHY_VLEVCTRL); |
1616 | |
1617 | /* Override and disable clock termination. */ |
1618 | dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, |
1619 | HDMI_3D_TX_PHY_CKCALCTRL); |
1620 | |
1621 | return 0; |
1622 | } |
1623 | |
1624 | static int hdmi_phy_configure(struct dw_hdmi *hdmi, |
1625 | const struct drm_display_info *display) |
1626 | { |
1627 | const struct dw_hdmi_phy_data *phy = hdmi->phy.data; |
1628 | const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; |
1629 | unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; |
1630 | unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; |
1631 | int ret; |
1632 | |
1633 | dw_hdmi_phy_power_off(hdmi); |
1634 | |
1635 | dw_hdmi_set_high_tmds_clock_ratio(hdmi, display); |
1636 | |
1637 | /* Leave low power consumption mode by asserting SVSRET. */ |
1638 | if (phy->has_svsret) |
1639 | dw_hdmi_phy_enable_svsret(hdmi, enable: 1); |
1640 | |
1641 | dw_hdmi_phy_gen2_reset(hdmi); |
1642 | |
1643 | hdmi_writeb(hdmi, val: HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); |
1644 | |
1645 | dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); |
1646 | |
1647 | /* Write to the PHY as configured by the platform */ |
1648 | if (pdata->configure_phy) |
1649 | ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock); |
1650 | else |
1651 | ret = phy->configure(hdmi, pdata, mpixelclock); |
1652 | if (ret) { |
1653 | dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n" , |
1654 | mpixelclock); |
1655 | return ret; |
1656 | } |
1657 | |
1658 | /* Wait for resuming transmission of TMDS clock and data */ |
1659 | if (mtmdsclock > HDMI14_MAX_TMDSCLK) |
1660 | msleep(msecs: 100); |
1661 | |
1662 | return dw_hdmi_phy_power_on(hdmi); |
1663 | } |
1664 | |
1665 | static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, |
1666 | const struct drm_display_info *display, |
1667 | const struct drm_display_mode *mode) |
1668 | { |
1669 | int i, ret; |
1670 | |
1671 | /* HDMI Phy spec says to do the phy initialization sequence twice */ |
1672 | for (i = 0; i < 2; i++) { |
1673 | dw_hdmi_phy_sel_data_en_pol(hdmi, enable: 1); |
1674 | dw_hdmi_phy_sel_interface_control(hdmi, enable: 0); |
1675 | |
1676 | ret = hdmi_phy_configure(hdmi, display); |
1677 | if (ret) |
1678 | return ret; |
1679 | } |
1680 | |
1681 | return 0; |
1682 | } |
1683 | |
1684 | static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) |
1685 | { |
1686 | dw_hdmi_phy_power_off(hdmi); |
1687 | } |
1688 | |
1689 | enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, |
1690 | void *data) |
1691 | { |
1692 | return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? |
1693 | connector_status_connected : connector_status_disconnected; |
1694 | } |
1695 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); |
1696 | |
1697 | void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, |
1698 | bool force, bool disabled, bool rxsense) |
1699 | { |
1700 | u8 old_mask = hdmi->phy_mask; |
1701 | |
1702 | if (force || disabled || !rxsense) |
1703 | hdmi->phy_mask |= HDMI_PHY_RX_SENSE; |
1704 | else |
1705 | hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; |
1706 | |
1707 | if (old_mask != hdmi->phy_mask) |
1708 | hdmi_writeb(hdmi, val: hdmi->phy_mask, HDMI_PHY_MASK0); |
1709 | } |
1710 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); |
1711 | |
1712 | void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) |
1713 | { |
1714 | /* |
1715 | * Configure the PHY RX SENSE and HPD interrupts polarities and clear |
1716 | * any pending interrupt. |
1717 | */ |
1718 | hdmi_writeb(hdmi, val: HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); |
1719 | hdmi_writeb(hdmi, val: HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, |
1720 | HDMI_IH_PHY_STAT0); |
1721 | |
1722 | /* Enable cable hot plug irq. */ |
1723 | hdmi_writeb(hdmi, val: hdmi->phy_mask, HDMI_PHY_MASK0); |
1724 | |
1725 | /* Clear and unmute interrupts. */ |
1726 | hdmi_writeb(hdmi, val: HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, |
1727 | HDMI_IH_PHY_STAT0); |
1728 | hdmi_writeb(hdmi, val: ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), |
1729 | HDMI_IH_MUTE_PHY_STAT0); |
1730 | } |
1731 | EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); |
1732 | |
1733 | static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { |
1734 | .init = dw_hdmi_phy_init, |
1735 | .disable = dw_hdmi_phy_disable, |
1736 | .read_hpd = dw_hdmi_phy_read_hpd, |
1737 | .update_hpd = dw_hdmi_phy_update_hpd, |
1738 | .setup_hpd = dw_hdmi_phy_setup_hpd, |
1739 | }; |
1740 | |
1741 | /* ----------------------------------------------------------------------------- |
1742 | * HDMI TX Setup |
1743 | */ |
1744 | |
1745 | static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) |
1746 | { |
1747 | u8 de; |
1748 | |
1749 | if (hdmi->hdmi_data.video_mode.mdataenablepolarity) |
1750 | de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; |
1751 | else |
1752 | de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; |
1753 | |
1754 | /* disable rx detect */ |
1755 | hdmi_modb(hdmi, data: HDMI_A_HDCPCFG0_RXDETECT_DISABLE, |
1756 | mask: HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); |
1757 | |
1758 | hdmi_modb(hdmi, data: de, mask: HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); |
1759 | |
1760 | hdmi_modb(hdmi, data: HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, |
1761 | mask: HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); |
1762 | } |
1763 | |
1764 | static void hdmi_config_AVI(struct dw_hdmi *hdmi, |
1765 | const struct drm_connector *connector, |
1766 | const struct drm_display_mode *mode) |
1767 | { |
1768 | struct hdmi_avi_infoframe frame; |
1769 | u8 val; |
1770 | |
1771 | /* Initialise info frame from DRM mode */ |
1772 | drm_hdmi_avi_infoframe_from_display_mode(frame: &frame, connector, mode); |
1773 | |
1774 | if (hdmi_bus_fmt_is_rgb(bus_format: hdmi->hdmi_data.enc_out_bus_format)) { |
1775 | drm_hdmi_avi_infoframe_quant_range(frame: &frame, connector, mode, |
1776 | rgb_quant_range: hdmi->hdmi_data.rgb_limited_range ? |
1777 | HDMI_QUANTIZATION_RANGE_LIMITED : |
1778 | HDMI_QUANTIZATION_RANGE_FULL); |
1779 | } else { |
1780 | frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; |
1781 | frame.ycc_quantization_range = |
1782 | HDMI_YCC_QUANTIZATION_RANGE_LIMITED; |
1783 | } |
1784 | |
1785 | if (hdmi_bus_fmt_is_yuv444(bus_format: hdmi->hdmi_data.enc_out_bus_format)) |
1786 | frame.colorspace = HDMI_COLORSPACE_YUV444; |
1787 | else if (hdmi_bus_fmt_is_yuv422(bus_format: hdmi->hdmi_data.enc_out_bus_format)) |
1788 | frame.colorspace = HDMI_COLORSPACE_YUV422; |
1789 | else if (hdmi_bus_fmt_is_yuv420(bus_format: hdmi->hdmi_data.enc_out_bus_format)) |
1790 | frame.colorspace = HDMI_COLORSPACE_YUV420; |
1791 | else |
1792 | frame.colorspace = HDMI_COLORSPACE_RGB; |
1793 | |
1794 | /* Set up colorimetry */ |
1795 | if (!hdmi_bus_fmt_is_rgb(bus_format: hdmi->hdmi_data.enc_out_bus_format)) { |
1796 | switch (hdmi->hdmi_data.enc_out_encoding) { |
1797 | case V4L2_YCBCR_ENC_601: |
1798 | if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) |
1799 | frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; |
1800 | else |
1801 | frame.colorimetry = HDMI_COLORIMETRY_ITU_601; |
1802 | frame.extended_colorimetry = |
1803 | HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; |
1804 | break; |
1805 | case V4L2_YCBCR_ENC_709: |
1806 | if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) |
1807 | frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; |
1808 | else |
1809 | frame.colorimetry = HDMI_COLORIMETRY_ITU_709; |
1810 | frame.extended_colorimetry = |
1811 | HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; |
1812 | break; |
1813 | default: /* Carries no data */ |
1814 | frame.colorimetry = HDMI_COLORIMETRY_ITU_601; |
1815 | frame.extended_colorimetry = |
1816 | HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; |
1817 | break; |
1818 | } |
1819 | } else { |
1820 | frame.colorimetry = HDMI_COLORIMETRY_NONE; |
1821 | frame.extended_colorimetry = |
1822 | HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; |
1823 | } |
1824 | |
1825 | /* |
1826 | * The Designware IP uses a different byte format from standard |
1827 | * AVI info frames, though generally the bits are in the correct |
1828 | * bytes. |
1829 | */ |
1830 | |
1831 | /* |
1832 | * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, |
1833 | * scan info in bits 4,5 rather than 0,1 and active aspect present in |
1834 | * bit 6 rather than 4. |
1835 | */ |
1836 | val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); |
1837 | if (frame.active_aspect & 15) |
1838 | val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; |
1839 | if (frame.top_bar || frame.bottom_bar) |
1840 | val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; |
1841 | if (frame.left_bar || frame.right_bar) |
1842 | val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; |
1843 | hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); |
1844 | |
1845 | /* AVI data byte 2 differences: none */ |
1846 | val = ((frame.colorimetry & 0x3) << 6) | |
1847 | ((frame.picture_aspect & 0x3) << 4) | |
1848 | (frame.active_aspect & 0xf); |
1849 | hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); |
1850 | |
1851 | /* AVI data byte 3 differences: none */ |
1852 | val = ((frame.extended_colorimetry & 0x7) << 4) | |
1853 | ((frame.quantization_range & 0x3) << 2) | |
1854 | (frame.nups & 0x3); |
1855 | if (frame.itc) |
1856 | val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; |
1857 | hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); |
1858 | |
1859 | /* AVI data byte 4 differences: none */ |
1860 | val = frame.video_code & 0x7f; |
1861 | hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); |
1862 | |
1863 | /* AVI Data Byte 5- set up input and output pixel repetition */ |
1864 | val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << |
1865 | HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & |
1866 | HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | |
1867 | ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << |
1868 | HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & |
1869 | HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); |
1870 | hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); |
1871 | |
1872 | /* |
1873 | * AVI data byte 5 differences: content type in 0,1 rather than 4,5, |
1874 | * ycc range in bits 2,3 rather than 6,7 |
1875 | */ |
1876 | val = ((frame.ycc_quantization_range & 0x3) << 2) | |
1877 | (frame.content_type & 0x3); |
1878 | hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); |
1879 | |
1880 | /* AVI Data Bytes 6-13 */ |
1881 | hdmi_writeb(hdmi, val: frame.top_bar & 0xff, HDMI_FC_AVIETB0); |
1882 | hdmi_writeb(hdmi, val: (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); |
1883 | hdmi_writeb(hdmi, val: frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); |
1884 | hdmi_writeb(hdmi, val: (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); |
1885 | hdmi_writeb(hdmi, val: frame.left_bar & 0xff, HDMI_FC_AVIELB0); |
1886 | hdmi_writeb(hdmi, val: (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); |
1887 | hdmi_writeb(hdmi, val: frame.right_bar & 0xff, HDMI_FC_AVISRB0); |
1888 | hdmi_writeb(hdmi, val: (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); |
1889 | } |
1890 | |
1891 | static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, |
1892 | const struct drm_connector *connector, |
1893 | const struct drm_display_mode *mode) |
1894 | { |
1895 | struct hdmi_vendor_infoframe frame; |
1896 | u8 buffer[10]; |
1897 | ssize_t err; |
1898 | |
1899 | err = drm_hdmi_vendor_infoframe_from_display_mode(frame: &frame, connector, |
1900 | mode); |
1901 | if (err < 0) |
1902 | /* |
1903 | * Going into that statement does not means vendor infoframe |
1904 | * fails. It just informed us that vendor infoframe is not |
1905 | * needed for the selected mode. Only 4k or stereoscopic 3D |
1906 | * mode requires vendor infoframe. So just simply return. |
1907 | */ |
1908 | return; |
1909 | |
1910 | err = hdmi_vendor_infoframe_pack(frame: &frame, buffer, size: sizeof(buffer)); |
1911 | if (err < 0) { |
1912 | dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n" , |
1913 | err); |
1914 | return; |
1915 | } |
1916 | hdmi_mask_writeb(hdmi, data: 0, HDMI_FC_DATAUTO0, shift: HDMI_FC_DATAUTO0_VSD_OFFSET, |
1917 | mask: HDMI_FC_DATAUTO0_VSD_MASK); |
1918 | |
1919 | /* Set the length of HDMI vendor specific InfoFrame payload */ |
1920 | hdmi_writeb(hdmi, val: buffer[2], HDMI_FC_VSDSIZE); |
1921 | |
1922 | /* Set 24bit IEEE Registration Identifier */ |
1923 | hdmi_writeb(hdmi, val: buffer[4], HDMI_FC_VSDIEEEID0); |
1924 | hdmi_writeb(hdmi, val: buffer[5], HDMI_FC_VSDIEEEID1); |
1925 | hdmi_writeb(hdmi, val: buffer[6], HDMI_FC_VSDIEEEID2); |
1926 | |
1927 | /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ |
1928 | hdmi_writeb(hdmi, val: buffer[7], HDMI_FC_VSDPAYLOAD0); |
1929 | hdmi_writeb(hdmi, val: buffer[8], HDMI_FC_VSDPAYLOAD1); |
1930 | |
1931 | if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) |
1932 | hdmi_writeb(hdmi, val: buffer[9], HDMI_FC_VSDPAYLOAD2); |
1933 | |
1934 | /* Packet frame interpolation */ |
1935 | hdmi_writeb(hdmi, val: 1, HDMI_FC_DATAUTO1); |
1936 | |
1937 | /* Auto packets per frame and line spacing */ |
1938 | hdmi_writeb(hdmi, val: 0x11, HDMI_FC_DATAUTO2); |
1939 | |
1940 | /* Configures the Frame Composer On RDRB mode */ |
1941 | hdmi_mask_writeb(hdmi, data: 1, HDMI_FC_DATAUTO0, shift: HDMI_FC_DATAUTO0_VSD_OFFSET, |
1942 | mask: HDMI_FC_DATAUTO0_VSD_MASK); |
1943 | } |
1944 | |
1945 | static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, |
1946 | const struct drm_connector *connector) |
1947 | { |
1948 | const struct drm_connector_state *conn_state = connector->state; |
1949 | struct hdmi_drm_infoframe frame; |
1950 | u8 buffer[30]; |
1951 | ssize_t err; |
1952 | int i; |
1953 | |
1954 | if (!hdmi->plat_data->use_drm_infoframe) |
1955 | return; |
1956 | |
1957 | hdmi_modb(hdmi, data: HDMI_FC_PACKET_TX_EN_DRM_DISABLE, |
1958 | mask: HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); |
1959 | |
1960 | err = drm_hdmi_infoframe_set_hdr_metadata(frame: &frame, conn_state); |
1961 | if (err < 0) |
1962 | return; |
1963 | |
1964 | err = hdmi_drm_infoframe_pack(frame: &frame, buffer, size: sizeof(buffer)); |
1965 | if (err < 0) { |
1966 | dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n" , err); |
1967 | return; |
1968 | } |
1969 | |
1970 | hdmi_writeb(hdmi, val: frame.version, HDMI_FC_DRM_HB0); |
1971 | hdmi_writeb(hdmi, val: frame.length, HDMI_FC_DRM_HB1); |
1972 | |
1973 | for (i = 0; i < frame.length; i++) |
1974 | hdmi_writeb(hdmi, val: buffer[4 + i], HDMI_FC_DRM_PB0 + i); |
1975 | |
1976 | hdmi_writeb(hdmi, val: 1, HDMI_FC_DRM_UP); |
1977 | hdmi_modb(hdmi, data: HDMI_FC_PACKET_TX_EN_DRM_ENABLE, |
1978 | mask: HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); |
1979 | } |
1980 | |
1981 | static void hdmi_av_composer(struct dw_hdmi *hdmi, |
1982 | const struct drm_display_info *display, |
1983 | const struct drm_display_mode *mode) |
1984 | { |
1985 | u8 inv_val, bytes; |
1986 | const struct drm_hdmi_info *hdmi_info = &display->hdmi; |
1987 | struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; |
1988 | int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; |
1989 | unsigned int vdisplay, hdisplay; |
1990 | |
1991 | vmode->mpixelclock = mode->clock * 1000; |
1992 | |
1993 | dev_dbg(hdmi->dev, "final pixclk = %d\n" , vmode->mpixelclock); |
1994 | |
1995 | vmode->mtmdsclock = vmode->mpixelclock; |
1996 | |
1997 | if (!hdmi_bus_fmt_is_yuv422(bus_format: hdmi->hdmi_data.enc_out_bus_format)) { |
1998 | switch (hdmi_bus_fmt_color_depth( |
1999 | bus_format: hdmi->hdmi_data.enc_out_bus_format)) { |
2000 | case 16: |
2001 | vmode->mtmdsclock = vmode->mpixelclock * 2; |
2002 | break; |
2003 | case 12: |
2004 | vmode->mtmdsclock = vmode->mpixelclock * 3 / 2; |
2005 | break; |
2006 | case 10: |
2007 | vmode->mtmdsclock = vmode->mpixelclock * 5 / 4; |
2008 | break; |
2009 | } |
2010 | } |
2011 | |
2012 | if (hdmi_bus_fmt_is_yuv420(bus_format: hdmi->hdmi_data.enc_out_bus_format)) |
2013 | vmode->mtmdsclock /= 2; |
2014 | |
2015 | dev_dbg(hdmi->dev, "final tmdsclock = %d\n" , vmode->mtmdsclock); |
2016 | |
2017 | /* Set up HDMI_FC_INVIDCONF */ |
2018 | inv_val = (hdmi->hdmi_data.hdcp_enable || |
2019 | (dw_hdmi_support_scdc(hdmi, display) && |
2020 | (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || |
2021 | hdmi_info->scdc.scrambling.low_rates)) ? |
2022 | HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : |
2023 | HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); |
2024 | |
2025 | inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? |
2026 | HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : |
2027 | HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; |
2028 | |
2029 | inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? |
2030 | HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : |
2031 | HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; |
2032 | |
2033 | inv_val |= (vmode->mdataenablepolarity ? |
2034 | HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : |
2035 | HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); |
2036 | |
2037 | if (hdmi->vic == 39) |
2038 | inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; |
2039 | else |
2040 | inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? |
2041 | HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : |
2042 | HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; |
2043 | |
2044 | inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? |
2045 | HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : |
2046 | HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; |
2047 | |
2048 | inv_val |= hdmi->sink_is_hdmi ? |
2049 | HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : |
2050 | HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; |
2051 | |
2052 | hdmi_writeb(hdmi, val: inv_val, HDMI_FC_INVIDCONF); |
2053 | |
2054 | hdisplay = mode->hdisplay; |
2055 | hblank = mode->htotal - mode->hdisplay; |
2056 | h_de_hs = mode->hsync_start - mode->hdisplay; |
2057 | hsync_len = mode->hsync_end - mode->hsync_start; |
2058 | |
2059 | /* |
2060 | * When we're setting a YCbCr420 mode, we need |
2061 | * to adjust the horizontal timing to suit. |
2062 | */ |
2063 | if (hdmi_bus_fmt_is_yuv420(bus_format: hdmi->hdmi_data.enc_out_bus_format)) { |
2064 | hdisplay /= 2; |
2065 | hblank /= 2; |
2066 | h_de_hs /= 2; |
2067 | hsync_len /= 2; |
2068 | } |
2069 | |
2070 | vdisplay = mode->vdisplay; |
2071 | vblank = mode->vtotal - mode->vdisplay; |
2072 | v_de_vs = mode->vsync_start - mode->vdisplay; |
2073 | vsync_len = mode->vsync_end - mode->vsync_start; |
2074 | |
2075 | /* |
2076 | * When we're setting an interlaced mode, we need |
2077 | * to adjust the vertical timing to suit. |
2078 | */ |
2079 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
2080 | vdisplay /= 2; |
2081 | vblank /= 2; |
2082 | v_de_vs /= 2; |
2083 | vsync_len /= 2; |
2084 | } |
2085 | |
2086 | /* Scrambling Control */ |
2087 | if (dw_hdmi_support_scdc(hdmi, display)) { |
2088 | if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || |
2089 | hdmi_info->scdc.scrambling.low_rates) { |
2090 | /* |
2091 | * HDMI2.0 Specifies the following procedure: |
2092 | * After the Source Device has determined that |
2093 | * SCDC_Present is set (=1), the Source Device should |
2094 | * write the accurate Version of the Source Device |
2095 | * to the Source Version field in the SCDCS. |
2096 | * Source Devices compliant shall set the |
2097 | * Source Version = 1. |
2098 | */ |
2099 | drm_scdc_readb(adapter: hdmi->ddc, SCDC_SINK_VERSION, |
2100 | value: &bytes); |
2101 | drm_scdc_writeb(adapter: hdmi->ddc, SCDC_SOURCE_VERSION, |
2102 | min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); |
2103 | |
2104 | /* Enabled Scrambling in the Sink */ |
2105 | drm_scdc_set_scrambling(connector: hdmi->curr_conn, enable: 1); |
2106 | |
2107 | /* |
2108 | * To activate the scrambler feature, you must ensure |
2109 | * that the quasi-static configuration bit |
2110 | * fc_invidconf.HDCP_keepout is set at configuration |
2111 | * time, before the required mc_swrstzreq.tmdsswrst_req |
2112 | * reset request is issued. |
2113 | */ |
2114 | hdmi_writeb(hdmi, val: (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, |
2115 | HDMI_MC_SWRSTZ); |
2116 | hdmi_writeb(hdmi, val: 1, HDMI_FC_SCRAMBLER_CTRL); |
2117 | } else { |
2118 | hdmi_writeb(hdmi, val: 0, HDMI_FC_SCRAMBLER_CTRL); |
2119 | hdmi_writeb(hdmi, val: (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, |
2120 | HDMI_MC_SWRSTZ); |
2121 | drm_scdc_set_scrambling(connector: hdmi->curr_conn, enable: 0); |
2122 | } |
2123 | } |
2124 | |
2125 | /* Set up horizontal active pixel width */ |
2126 | hdmi_writeb(hdmi, val: hdisplay >> 8, HDMI_FC_INHACTV1); |
2127 | hdmi_writeb(hdmi, val: hdisplay, HDMI_FC_INHACTV0); |
2128 | |
2129 | /* Set up vertical active lines */ |
2130 | hdmi_writeb(hdmi, val: vdisplay >> 8, HDMI_FC_INVACTV1); |
2131 | hdmi_writeb(hdmi, val: vdisplay, HDMI_FC_INVACTV0); |
2132 | |
2133 | /* Set up horizontal blanking pixel region width */ |
2134 | hdmi_writeb(hdmi, val: hblank >> 8, HDMI_FC_INHBLANK1); |
2135 | hdmi_writeb(hdmi, val: hblank, HDMI_FC_INHBLANK0); |
2136 | |
2137 | /* Set up vertical blanking pixel region width */ |
2138 | hdmi_writeb(hdmi, val: vblank, HDMI_FC_INVBLANK); |
2139 | |
2140 | /* Set up HSYNC active edge delay width (in pixel clks) */ |
2141 | hdmi_writeb(hdmi, val: h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); |
2142 | hdmi_writeb(hdmi, val: h_de_hs, HDMI_FC_HSYNCINDELAY0); |
2143 | |
2144 | /* Set up VSYNC active edge delay (in lines) */ |
2145 | hdmi_writeb(hdmi, val: v_de_vs, HDMI_FC_VSYNCINDELAY); |
2146 | |
2147 | /* Set up HSYNC active pulse width (in pixel clks) */ |
2148 | hdmi_writeb(hdmi, val: hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); |
2149 | hdmi_writeb(hdmi, val: hsync_len, HDMI_FC_HSYNCINWIDTH0); |
2150 | |
2151 | /* Set up VSYNC active edge delay (in lines) */ |
2152 | hdmi_writeb(hdmi, val: vsync_len, HDMI_FC_VSYNCINWIDTH); |
2153 | } |
2154 | |
2155 | /* HDMI Initialization Step B.4 */ |
2156 | static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) |
2157 | { |
2158 | /* control period minimum duration */ |
2159 | hdmi_writeb(hdmi, val: 12, HDMI_FC_CTRLDUR); |
2160 | hdmi_writeb(hdmi, val: 32, HDMI_FC_EXCTRLDUR); |
2161 | hdmi_writeb(hdmi, val: 1, HDMI_FC_EXCTRLSPAC); |
2162 | |
2163 | /* Set to fill TMDS data channels */ |
2164 | hdmi_writeb(hdmi, val: 0x0B, HDMI_FC_CH0PREAM); |
2165 | hdmi_writeb(hdmi, val: 0x16, HDMI_FC_CH1PREAM); |
2166 | hdmi_writeb(hdmi, val: 0x21, HDMI_FC_CH2PREAM); |
2167 | |
2168 | /* Enable pixel clock and tmds data path */ |
2169 | hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | |
2170 | HDMI_MC_CLKDIS_CSCCLK_DISABLE | |
2171 | HDMI_MC_CLKDIS_AUDCLK_DISABLE | |
2172 | HDMI_MC_CLKDIS_PREPCLK_DISABLE | |
2173 | HDMI_MC_CLKDIS_TMDSCLK_DISABLE; |
2174 | hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; |
2175 | hdmi_writeb(hdmi, val: hdmi->mc_clkdis, HDMI_MC_CLKDIS); |
2176 | |
2177 | hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; |
2178 | hdmi_writeb(hdmi, val: hdmi->mc_clkdis, HDMI_MC_CLKDIS); |
2179 | |
2180 | /* Enable csc path */ |
2181 | if (is_csc_needed(hdmi)) { |
2182 | hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; |
2183 | hdmi_writeb(hdmi, val: hdmi->mc_clkdis, HDMI_MC_CLKDIS); |
2184 | |
2185 | hdmi_writeb(hdmi, val: HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, |
2186 | HDMI_MC_FLOWCTRL); |
2187 | } else { |
2188 | hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE; |
2189 | hdmi_writeb(hdmi, val: hdmi->mc_clkdis, HDMI_MC_CLKDIS); |
2190 | |
2191 | hdmi_writeb(hdmi, val: HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, |
2192 | HDMI_MC_FLOWCTRL); |
2193 | } |
2194 | } |
2195 | |
2196 | /* Workaround to clear the overflow condition */ |
2197 | static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) |
2198 | { |
2199 | unsigned int count; |
2200 | unsigned int i; |
2201 | u8 val; |
2202 | |
2203 | /* |
2204 | * Under some circumstances the Frame Composer arithmetic unit can miss |
2205 | * an FC register write due to being busy processing the previous one. |
2206 | * The issue can be worked around by issuing a TMDS software reset and |
2207 | * then write one of the FC registers several times. |
2208 | * |
2209 | * The number of iterations matters and depends on the HDMI TX revision |
2210 | * (and possibly on the platform). |
2211 | * 4 iterations for i.MX6Q(v1.30a) and 1 iteration for others. |
2212 | * i.MX6DL (v1.31a), Allwinner SoCs (v1.32a), Rockchip RK3288 SoC (v2.00a), |
2213 | * Amlogic Meson GX SoCs (v2.01a), RK3328/RK3399 SoCs (v2.11a) |
2214 | * and i.MX8MPlus (v2.13a) have been identified as needing the workaround |
2215 | * with a single iteration. |
2216 | */ |
2217 | |
2218 | switch (hdmi->version) { |
2219 | case 0x130a: |
2220 | count = 4; |
2221 | break; |
2222 | default: |
2223 | count = 1; |
2224 | break; |
2225 | } |
2226 | |
2227 | /* TMDS software reset */ |
2228 | hdmi_writeb(hdmi, val: (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); |
2229 | |
2230 | val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); |
2231 | for (i = 0; i < count; i++) |
2232 | hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); |
2233 | } |
2234 | |
2235 | static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) |
2236 | { |
2237 | hdmi_writeb(hdmi, val: HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, |
2238 | HDMI_IH_MUTE_FC_STAT2); |
2239 | } |
2240 | |
2241 | static int dw_hdmi_setup(struct dw_hdmi *hdmi, |
2242 | const struct drm_connector *connector, |
2243 | const struct drm_display_mode *mode) |
2244 | { |
2245 | int ret; |
2246 | |
2247 | hdmi_disable_overflow_interrupts(hdmi); |
2248 | |
2249 | hdmi->vic = drm_match_cea_mode(to_match: mode); |
2250 | |
2251 | if (!hdmi->vic) { |
2252 | dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n" ); |
2253 | } else { |
2254 | dev_dbg(hdmi->dev, "CEA mode used vic=%d\n" , hdmi->vic); |
2255 | } |
2256 | |
2257 | if ((hdmi->vic == 6) || (hdmi->vic == 7) || |
2258 | (hdmi->vic == 21) || (hdmi->vic == 22) || |
2259 | (hdmi->vic == 2) || (hdmi->vic == 3) || |
2260 | (hdmi->vic == 17) || (hdmi->vic == 18)) |
2261 | hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; |
2262 | else |
2263 | hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; |
2264 | |
2265 | hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; |
2266 | hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; |
2267 | |
2268 | if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED) |
2269 | hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; |
2270 | |
2271 | /* TOFIX: Get input encoding from plat data or fallback to none */ |
2272 | if (hdmi->plat_data->input_bus_encoding) |
2273 | hdmi->hdmi_data.enc_in_encoding = |
2274 | hdmi->plat_data->input_bus_encoding; |
2275 | else |
2276 | hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; |
2277 | |
2278 | if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED) |
2279 | hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; |
2280 | |
2281 | hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi && |
2282 | drm_default_rgb_quant_range(mode) == |
2283 | HDMI_QUANTIZATION_RANGE_LIMITED; |
2284 | |
2285 | hdmi->hdmi_data.pix_repet_factor = 0; |
2286 | hdmi->hdmi_data.hdcp_enable = 0; |
2287 | hdmi->hdmi_data.video_mode.mdataenablepolarity = true; |
2288 | |
2289 | /* HDMI Initialization Step B.1 */ |
2290 | hdmi_av_composer(hdmi, display: &connector->display_info, mode); |
2291 | |
2292 | /* HDMI Initializateion Step B.2 */ |
2293 | ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, |
2294 | &connector->display_info, |
2295 | &hdmi->previous_mode); |
2296 | if (ret) |
2297 | return ret; |
2298 | hdmi->phy.enabled = true; |
2299 | |
2300 | /* HDMI Initialization Step B.3 */ |
2301 | dw_hdmi_enable_video_path(hdmi); |
2302 | |
2303 | if (hdmi->sink_has_audio) { |
2304 | dev_dbg(hdmi->dev, "sink has audio support\n" ); |
2305 | |
2306 | /* HDMI Initialization Step E - Configure audio */ |
2307 | hdmi_clk_regenerator_update_pixel_clock(hdmi); |
2308 | hdmi_enable_audio_clk(hdmi, enable: hdmi->audio_enable); |
2309 | } |
2310 | |
2311 | /* not for DVI mode */ |
2312 | if (hdmi->sink_is_hdmi) { |
2313 | dev_dbg(hdmi->dev, "%s HDMI mode\n" , __func__); |
2314 | |
2315 | /* HDMI Initialization Step F - Configure AVI InfoFrame */ |
2316 | hdmi_config_AVI(hdmi, connector, mode); |
2317 | hdmi_config_vendor_specific_infoframe(hdmi, connector, mode); |
2318 | hdmi_config_drm_infoframe(hdmi, connector); |
2319 | } else { |
2320 | dev_dbg(hdmi->dev, "%s DVI mode\n" , __func__); |
2321 | } |
2322 | |
2323 | hdmi_video_packetize(hdmi); |
2324 | hdmi_video_csc(hdmi); |
2325 | hdmi_video_sample(hdmi); |
2326 | hdmi_tx_hdcp_config(hdmi); |
2327 | |
2328 | dw_hdmi_clear_overflow(hdmi); |
2329 | |
2330 | return 0; |
2331 | } |
2332 | |
2333 | static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) |
2334 | { |
2335 | u8 ih_mute; |
2336 | |
2337 | /* |
2338 | * Boot up defaults are: |
2339 | * HDMI_IH_MUTE = 0x03 (disabled) |
2340 | * HDMI_IH_MUTE_* = 0x00 (enabled) |
2341 | * |
2342 | * Disable top level interrupt bits in HDMI block |
2343 | */ |
2344 | ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | |
2345 | HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | |
2346 | HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; |
2347 | |
2348 | hdmi_writeb(hdmi, val: ih_mute, HDMI_IH_MUTE); |
2349 | |
2350 | /* by default mask all interrupts */ |
2351 | hdmi_writeb(hdmi, val: 0xff, HDMI_VP_MASK); |
2352 | hdmi_writeb(hdmi, val: 0xff, HDMI_FC_MASK0); |
2353 | hdmi_writeb(hdmi, val: 0xff, HDMI_FC_MASK1); |
2354 | hdmi_writeb(hdmi, val: 0xff, HDMI_FC_MASK2); |
2355 | hdmi_writeb(hdmi, val: 0xff, HDMI_PHY_MASK0); |
2356 | hdmi_writeb(hdmi, val: 0xff, HDMI_PHY_I2CM_INT_ADDR); |
2357 | hdmi_writeb(hdmi, val: 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); |
2358 | hdmi_writeb(hdmi, val: 0xff, HDMI_AUD_INT); |
2359 | hdmi_writeb(hdmi, val: 0xff, HDMI_AUD_SPDIFINT); |
2360 | hdmi_writeb(hdmi, val: 0xff, HDMI_AUD_HBR_MASK); |
2361 | hdmi_writeb(hdmi, val: 0xff, HDMI_GP_MASK); |
2362 | hdmi_writeb(hdmi, val: 0xff, HDMI_A_APIINTMSK); |
2363 | hdmi_writeb(hdmi, val: 0xff, HDMI_I2CM_INT); |
2364 | hdmi_writeb(hdmi, val: 0xff, HDMI_I2CM_CTLINT); |
2365 | |
2366 | /* Disable interrupts in the IH_MUTE_* registers */ |
2367 | hdmi_writeb(hdmi, val: 0xff, HDMI_IH_MUTE_FC_STAT0); |
2368 | hdmi_writeb(hdmi, val: 0xff, HDMI_IH_MUTE_FC_STAT1); |
2369 | hdmi_writeb(hdmi, val: 0xff, HDMI_IH_MUTE_FC_STAT2); |
2370 | hdmi_writeb(hdmi, val: 0xff, HDMI_IH_MUTE_AS_STAT0); |
2371 | hdmi_writeb(hdmi, val: 0xff, HDMI_IH_MUTE_PHY_STAT0); |
2372 | hdmi_writeb(hdmi, val: 0xff, HDMI_IH_MUTE_I2CM_STAT0); |
2373 | hdmi_writeb(hdmi, val: 0xff, HDMI_IH_MUTE_CEC_STAT0); |
2374 | hdmi_writeb(hdmi, val: 0xff, HDMI_IH_MUTE_VP_STAT0); |
2375 | hdmi_writeb(hdmi, val: 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); |
2376 | hdmi_writeb(hdmi, val: 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); |
2377 | |
2378 | /* Enable top level interrupt bits in HDMI block */ |
2379 | ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | |
2380 | HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); |
2381 | hdmi_writeb(hdmi, val: ih_mute, HDMI_IH_MUTE); |
2382 | } |
2383 | |
2384 | static void dw_hdmi_poweron(struct dw_hdmi *hdmi) |
2385 | { |
2386 | hdmi->bridge_is_on = true; |
2387 | |
2388 | /* |
2389 | * The curr_conn field is guaranteed to be valid here, as this function |
2390 | * is only be called when !hdmi->disabled. |
2391 | */ |
2392 | dw_hdmi_setup(hdmi, connector: hdmi->curr_conn, mode: &hdmi->previous_mode); |
2393 | } |
2394 | |
2395 | static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) |
2396 | { |
2397 | if (hdmi->phy.enabled) { |
2398 | hdmi->phy.ops->disable(hdmi, hdmi->phy.data); |
2399 | hdmi->phy.enabled = false; |
2400 | } |
2401 | |
2402 | hdmi->bridge_is_on = false; |
2403 | } |
2404 | |
2405 | static void dw_hdmi_update_power(struct dw_hdmi *hdmi) |
2406 | { |
2407 | int force = hdmi->force; |
2408 | |
2409 | if (hdmi->disabled) { |
2410 | force = DRM_FORCE_OFF; |
2411 | } else if (force == DRM_FORCE_UNSPECIFIED) { |
2412 | if (hdmi->rxsense) |
2413 | force = DRM_FORCE_ON; |
2414 | else |
2415 | force = DRM_FORCE_OFF; |
2416 | } |
2417 | |
2418 | if (force == DRM_FORCE_OFF) { |
2419 | if (hdmi->bridge_is_on) |
2420 | dw_hdmi_poweroff(hdmi); |
2421 | } else { |
2422 | if (!hdmi->bridge_is_on) |
2423 | dw_hdmi_poweron(hdmi); |
2424 | } |
2425 | } |
2426 | |
2427 | /* |
2428 | * Adjust the detection of RXSENSE according to whether we have a forced |
2429 | * connection mode enabled, or whether we have been disabled. There is |
2430 | * no point processing RXSENSE interrupts if we have a forced connection |
2431 | * state, or DRM has us disabled. |
2432 | * |
2433 | * We also disable rxsense interrupts when we think we're disconnected |
2434 | * to avoid floating TDMS signals giving false rxsense interrupts. |
2435 | * |
2436 | * Note: we still need to listen for HPD interrupts even when DRM has us |
2437 | * disabled so that we can detect a connect event. |
2438 | */ |
2439 | static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) |
2440 | { |
2441 | if (hdmi->phy.ops->update_hpd) |
2442 | hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, |
2443 | hdmi->force, hdmi->disabled, |
2444 | hdmi->rxsense); |
2445 | } |
2446 | |
2447 | static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi) |
2448 | { |
2449 | enum drm_connector_status result; |
2450 | |
2451 | result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); |
2452 | hdmi->last_connector_result = result; |
2453 | |
2454 | return result; |
2455 | } |
2456 | |
2457 | static const struct drm_edid *dw_hdmi_edid_read(struct dw_hdmi *hdmi, |
2458 | struct drm_connector *connector) |
2459 | { |
2460 | const struct drm_edid *drm_edid; |
2461 | const struct edid *edid; |
2462 | |
2463 | if (!hdmi->ddc) |
2464 | return NULL; |
2465 | |
2466 | drm_edid = drm_edid_read_ddc(connector, adapter: hdmi->ddc); |
2467 | if (!drm_edid) { |
2468 | dev_dbg(hdmi->dev, "failed to get edid\n" ); |
2469 | return NULL; |
2470 | } |
2471 | |
2472 | /* |
2473 | * FIXME: This should use connector->display_info.is_hdmi and |
2474 | * connector->display_info.has_audio from a path that has read the EDID |
2475 | * and called drm_edid_connector_update(). |
2476 | */ |
2477 | edid = drm_edid_raw(drm_edid); |
2478 | |
2479 | dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n" , |
2480 | edid->width_cm, edid->height_cm); |
2481 | |
2482 | hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); |
2483 | hdmi->sink_has_audio = drm_detect_monitor_audio(edid); |
2484 | |
2485 | return drm_edid; |
2486 | } |
2487 | |
2488 | /* ----------------------------------------------------------------------------- |
2489 | * DRM Connector Operations |
2490 | */ |
2491 | |
2492 | static enum drm_connector_status |
2493 | dw_hdmi_connector_detect(struct drm_connector *connector, bool force) |
2494 | { |
2495 | struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, |
2496 | connector); |
2497 | return dw_hdmi_detect(hdmi); |
2498 | } |
2499 | |
2500 | static int dw_hdmi_connector_get_modes(struct drm_connector *connector) |
2501 | { |
2502 | struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, |
2503 | connector); |
2504 | const struct drm_edid *drm_edid; |
2505 | int ret; |
2506 | |
2507 | drm_edid = dw_hdmi_edid_read(hdmi, connector); |
2508 | |
2509 | drm_edid_connector_update(connector, edid: drm_edid); |
2510 | cec_notifier_set_phys_addr(n: hdmi->cec_notifier, |
2511 | pa: connector->display_info.source_physical_address); |
2512 | ret = drm_edid_connector_add_modes(connector); |
2513 | drm_edid_free(drm_edid); |
2514 | |
2515 | return ret; |
2516 | } |
2517 | |
2518 | static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, |
2519 | struct drm_atomic_state *state) |
2520 | { |
2521 | struct drm_connector_state *old_state = |
2522 | drm_atomic_get_old_connector_state(state, connector); |
2523 | struct drm_connector_state *new_state = |
2524 | drm_atomic_get_new_connector_state(state, connector); |
2525 | struct drm_crtc *crtc = new_state->crtc; |
2526 | struct drm_crtc_state *crtc_state; |
2527 | |
2528 | if (!crtc) |
2529 | return 0; |
2530 | |
2531 | if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { |
2532 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
2533 | if (IS_ERR(ptr: crtc_state)) |
2534 | return PTR_ERR(ptr: crtc_state); |
2535 | |
2536 | crtc_state->mode_changed = true; |
2537 | } |
2538 | |
2539 | return 0; |
2540 | } |
2541 | |
2542 | static void dw_hdmi_connector_force(struct drm_connector *connector) |
2543 | { |
2544 | struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, |
2545 | connector); |
2546 | |
2547 | mutex_lock(&hdmi->mutex); |
2548 | hdmi->force = connector->force; |
2549 | dw_hdmi_update_power(hdmi); |
2550 | dw_hdmi_update_phy_mask(hdmi); |
2551 | mutex_unlock(lock: &hdmi->mutex); |
2552 | } |
2553 | |
2554 | static const struct drm_connector_funcs dw_hdmi_connector_funcs = { |
2555 | .fill_modes = drm_helper_probe_single_connector_modes, |
2556 | .detect = dw_hdmi_connector_detect, |
2557 | .destroy = drm_connector_cleanup, |
2558 | .force = dw_hdmi_connector_force, |
2559 | .reset = drm_atomic_helper_connector_reset, |
2560 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
2561 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
2562 | }; |
2563 | |
2564 | static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { |
2565 | .get_modes = dw_hdmi_connector_get_modes, |
2566 | .atomic_check = dw_hdmi_connector_atomic_check, |
2567 | }; |
2568 | |
2569 | static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) |
2570 | { |
2571 | struct drm_connector *connector = &hdmi->connector; |
2572 | struct cec_connector_info conn_info; |
2573 | struct cec_notifier *notifier; |
2574 | |
2575 | if (hdmi->version >= 0x200a) |
2576 | connector->ycbcr_420_allowed = |
2577 | hdmi->plat_data->ycbcr_420_allowed; |
2578 | else |
2579 | connector->ycbcr_420_allowed = false; |
2580 | |
2581 | connector->interlace_allowed = 1; |
2582 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
2583 | |
2584 | drm_connector_helper_add(connector, funcs: &dw_hdmi_connector_helper_funcs); |
2585 | |
2586 | drm_connector_init_with_ddc(dev: hdmi->bridge.dev, connector, |
2587 | funcs: &dw_hdmi_connector_funcs, |
2588 | DRM_MODE_CONNECTOR_HDMIA, |
2589 | ddc: hdmi->ddc); |
2590 | |
2591 | /* |
2592 | * drm_connector_attach_max_bpc_property() requires the |
2593 | * connector to have a state. |
2594 | */ |
2595 | drm_atomic_helper_connector_reset(connector); |
2596 | |
2597 | drm_connector_attach_max_bpc_property(connector, min: 8, max: 16); |
2598 | |
2599 | if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) |
2600 | drm_connector_attach_hdr_output_metadata_property(connector); |
2601 | |
2602 | drm_connector_attach_encoder(connector, encoder: hdmi->bridge.encoder); |
2603 | |
2604 | cec_fill_conn_info_from_drm(conn_info: &conn_info, connector); |
2605 | |
2606 | notifier = cec_notifier_conn_register(hdmi_dev: hdmi->dev, NULL, conn_info: &conn_info); |
2607 | if (!notifier) |
2608 | return -ENOMEM; |
2609 | |
2610 | mutex_lock(&hdmi->cec_notifier_mutex); |
2611 | hdmi->cec_notifier = notifier; |
2612 | mutex_unlock(lock: &hdmi->cec_notifier_mutex); |
2613 | |
2614 | return 0; |
2615 | } |
2616 | |
2617 | /* ----------------------------------------------------------------------------- |
2618 | * DRM Bridge Operations |
2619 | */ |
2620 | |
2621 | /* |
2622 | * Possible output formats : |
2623 | * - MEDIA_BUS_FMT_UYYVYY16_0_5X48, |
2624 | * - MEDIA_BUS_FMT_UYYVYY12_0_5X36, |
2625 | * - MEDIA_BUS_FMT_UYYVYY10_0_5X30, |
2626 | * - MEDIA_BUS_FMT_UYYVYY8_0_5X24, |
2627 | * - MEDIA_BUS_FMT_YUV16_1X48, |
2628 | * - MEDIA_BUS_FMT_RGB161616_1X48, |
2629 | * - MEDIA_BUS_FMT_UYVY12_1X24, |
2630 | * - MEDIA_BUS_FMT_YUV12_1X36, |
2631 | * - MEDIA_BUS_FMT_RGB121212_1X36, |
2632 | * - MEDIA_BUS_FMT_UYVY10_1X20, |
2633 | * - MEDIA_BUS_FMT_YUV10_1X30, |
2634 | * - MEDIA_BUS_FMT_RGB101010_1X30, |
2635 | * - MEDIA_BUS_FMT_UYVY8_1X16, |
2636 | * - MEDIA_BUS_FMT_YUV8_1X24, |
2637 | * - MEDIA_BUS_FMT_RGB888_1X24, |
2638 | */ |
2639 | |
2640 | /* Can return a maximum of 11 possible output formats for a mode/connector */ |
2641 | #define MAX_OUTPUT_SEL_FORMATS 11 |
2642 | |
2643 | static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, |
2644 | struct drm_bridge_state *bridge_state, |
2645 | struct drm_crtc_state *crtc_state, |
2646 | struct drm_connector_state *conn_state, |
2647 | unsigned int *num_output_fmts) |
2648 | { |
2649 | struct drm_connector *conn = conn_state->connector; |
2650 | struct drm_display_info *info = &conn->display_info; |
2651 | struct drm_display_mode *mode = &crtc_state->mode; |
2652 | u8 max_bpc = conn_state->max_requested_bpc; |
2653 | bool is_hdmi2_sink = info->hdmi.scdc.supported || |
2654 | (info->color_formats & DRM_COLOR_FORMAT_YCBCR420); |
2655 | u32 *output_fmts; |
2656 | unsigned int i = 0; |
2657 | |
2658 | *num_output_fmts = 0; |
2659 | |
2660 | output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, size: sizeof(*output_fmts), |
2661 | GFP_KERNEL); |
2662 | if (!output_fmts) |
2663 | return NULL; |
2664 | |
2665 | /* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */ |
2666 | if (list_is_singular(head: &bridge->encoder->bridge_chain) || |
2667 | list_is_first(list: &bridge->chain_node, head: &bridge->encoder->bridge_chain)) { |
2668 | *num_output_fmts = 1; |
2669 | output_fmts[0] = MEDIA_BUS_FMT_FIXED; |
2670 | |
2671 | return output_fmts; |
2672 | } |
2673 | |
2674 | /* |
2675 | * If the current mode enforces 4:2:0, force the output but format |
2676 | * to 4:2:0 and do not add the YUV422/444/RGB formats |
2677 | */ |
2678 | if (conn->ycbcr_420_allowed && |
2679 | (drm_mode_is_420_only(display: info, mode) || |
2680 | (is_hdmi2_sink && drm_mode_is_420_also(display: info, mode)))) { |
2681 | |
2682 | /* Order bus formats from 16bit to 8bit if supported */ |
2683 | if (max_bpc >= 16 && info->bpc == 16 && |
2684 | (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)) |
2685 | output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48; |
2686 | |
2687 | if (max_bpc >= 12 && info->bpc >= 12 && |
2688 | (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) |
2689 | output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36; |
2690 | |
2691 | if (max_bpc >= 10 && info->bpc >= 10 && |
2692 | (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)) |
2693 | output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30; |
2694 | |
2695 | /* Default 8bit fallback */ |
2696 | output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; |
2697 | |
2698 | if (drm_mode_is_420_only(display: info, mode)) { |
2699 | *num_output_fmts = i; |
2700 | return output_fmts; |
2701 | } |
2702 | } |
2703 | |
2704 | /* |
2705 | * Order bus formats from 16bit to 8bit and from YUV422 to RGB |
2706 | * if supported. In any case the default RGB888 format is added |
2707 | */ |
2708 | |
2709 | /* Default 8bit RGB fallback */ |
2710 | output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; |
2711 | |
2712 | if (max_bpc >= 16 && info->bpc == 16) { |
2713 | if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) |
2714 | output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; |
2715 | |
2716 | output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; |
2717 | } |
2718 | |
2719 | if (max_bpc >= 12 && info->bpc >= 12) { |
2720 | if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) |
2721 | output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; |
2722 | |
2723 | if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) |
2724 | output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; |
2725 | |
2726 | output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; |
2727 | } |
2728 | |
2729 | if (max_bpc >= 10 && info->bpc >= 10) { |
2730 | if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) |
2731 | output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; |
2732 | |
2733 | if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) |
2734 | output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; |
2735 | |
2736 | output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; |
2737 | } |
2738 | |
2739 | if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) |
2740 | output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; |
2741 | |
2742 | if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) |
2743 | output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; |
2744 | |
2745 | *num_output_fmts = i; |
2746 | |
2747 | return output_fmts; |
2748 | } |
2749 | |
2750 | /* |
2751 | * Possible input formats : |
2752 | * - MEDIA_BUS_FMT_RGB888_1X24 |
2753 | * - MEDIA_BUS_FMT_YUV8_1X24 |
2754 | * - MEDIA_BUS_FMT_UYVY8_1X16 |
2755 | * - MEDIA_BUS_FMT_UYYVYY8_0_5X24 |
2756 | * - MEDIA_BUS_FMT_RGB101010_1X30 |
2757 | * - MEDIA_BUS_FMT_YUV10_1X30 |
2758 | * - MEDIA_BUS_FMT_UYVY10_1X20 |
2759 | * - MEDIA_BUS_FMT_UYYVYY10_0_5X30 |
2760 | * - MEDIA_BUS_FMT_RGB121212_1X36 |
2761 | * - MEDIA_BUS_FMT_YUV12_1X36 |
2762 | * - MEDIA_BUS_FMT_UYVY12_1X24 |
2763 | * - MEDIA_BUS_FMT_UYYVYY12_0_5X36 |
2764 | * - MEDIA_BUS_FMT_RGB161616_1X48 |
2765 | * - MEDIA_BUS_FMT_YUV16_1X48 |
2766 | * - MEDIA_BUS_FMT_UYYVYY16_0_5X48 |
2767 | */ |
2768 | |
2769 | /* Can return a maximum of 3 possible input formats for an output format */ |
2770 | #define MAX_INPUT_SEL_FORMATS 3 |
2771 | |
2772 | static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, |
2773 | struct drm_bridge_state *bridge_state, |
2774 | struct drm_crtc_state *crtc_state, |
2775 | struct drm_connector_state *conn_state, |
2776 | u32 output_fmt, |
2777 | unsigned int *num_input_fmts) |
2778 | { |
2779 | u32 *input_fmts; |
2780 | unsigned int i = 0; |
2781 | |
2782 | *num_input_fmts = 0; |
2783 | |
2784 | input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, size: sizeof(*input_fmts), |
2785 | GFP_KERNEL); |
2786 | if (!input_fmts) |
2787 | return NULL; |
2788 | |
2789 | switch (output_fmt) { |
2790 | /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */ |
2791 | case MEDIA_BUS_FMT_FIXED: |
2792 | input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; |
2793 | break; |
2794 | /* 8bit */ |
2795 | case MEDIA_BUS_FMT_RGB888_1X24: |
2796 | input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; |
2797 | input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; |
2798 | input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; |
2799 | break; |
2800 | case MEDIA_BUS_FMT_YUV8_1X24: |
2801 | input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; |
2802 | input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; |
2803 | input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; |
2804 | break; |
2805 | case MEDIA_BUS_FMT_UYVY8_1X16: |
2806 | input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; |
2807 | input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; |
2808 | input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; |
2809 | break; |
2810 | |
2811 | /* 10bit */ |
2812 | case MEDIA_BUS_FMT_RGB101010_1X30: |
2813 | input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; |
2814 | input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; |
2815 | input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; |
2816 | break; |
2817 | case MEDIA_BUS_FMT_YUV10_1X30: |
2818 | input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; |
2819 | input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; |
2820 | input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; |
2821 | break; |
2822 | case MEDIA_BUS_FMT_UYVY10_1X20: |
2823 | input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; |
2824 | input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; |
2825 | input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; |
2826 | break; |
2827 | |
2828 | /* 12bit */ |
2829 | case MEDIA_BUS_FMT_RGB121212_1X36: |
2830 | input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; |
2831 | input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; |
2832 | input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; |
2833 | break; |
2834 | case MEDIA_BUS_FMT_YUV12_1X36: |
2835 | input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; |
2836 | input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; |
2837 | input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; |
2838 | break; |
2839 | case MEDIA_BUS_FMT_UYVY12_1X24: |
2840 | input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; |
2841 | input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; |
2842 | input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; |
2843 | break; |
2844 | |
2845 | /* 16bit */ |
2846 | case MEDIA_BUS_FMT_RGB161616_1X48: |
2847 | input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; |
2848 | input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; |
2849 | break; |
2850 | case MEDIA_BUS_FMT_YUV16_1X48: |
2851 | input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; |
2852 | input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; |
2853 | break; |
2854 | |
2855 | /*YUV 4:2:0 */ |
2856 | case MEDIA_BUS_FMT_UYYVYY8_0_5X24: |
2857 | case MEDIA_BUS_FMT_UYYVYY10_0_5X30: |
2858 | case MEDIA_BUS_FMT_UYYVYY12_0_5X36: |
2859 | case MEDIA_BUS_FMT_UYYVYY16_0_5X48: |
2860 | input_fmts[i++] = output_fmt; |
2861 | break; |
2862 | } |
2863 | |
2864 | *num_input_fmts = i; |
2865 | |
2866 | if (*num_input_fmts == 0) { |
2867 | kfree(objp: input_fmts); |
2868 | input_fmts = NULL; |
2869 | } |
2870 | |
2871 | return input_fmts; |
2872 | } |
2873 | |
2874 | static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge, |
2875 | struct drm_bridge_state *bridge_state, |
2876 | struct drm_crtc_state *crtc_state, |
2877 | struct drm_connector_state *conn_state) |
2878 | { |
2879 | struct dw_hdmi *hdmi = bridge->driver_private; |
2880 | |
2881 | hdmi->hdmi_data.enc_out_bus_format = |
2882 | bridge_state->output_bus_cfg.format; |
2883 | |
2884 | hdmi->hdmi_data.enc_in_bus_format = |
2885 | bridge_state->input_bus_cfg.format; |
2886 | |
2887 | dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n" , |
2888 | bridge_state->input_bus_cfg.format, |
2889 | bridge_state->output_bus_cfg.format); |
2890 | |
2891 | return 0; |
2892 | } |
2893 | |
2894 | static int dw_hdmi_bridge_attach(struct drm_bridge *bridge, |
2895 | enum drm_bridge_attach_flags flags) |
2896 | { |
2897 | struct dw_hdmi *hdmi = bridge->driver_private; |
2898 | |
2899 | if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) |
2900 | return drm_bridge_attach(encoder: bridge->encoder, bridge: hdmi->next_bridge, |
2901 | previous: bridge, flags); |
2902 | |
2903 | return dw_hdmi_connector_create(hdmi); |
2904 | } |
2905 | |
2906 | static void dw_hdmi_bridge_detach(struct drm_bridge *bridge) |
2907 | { |
2908 | struct dw_hdmi *hdmi = bridge->driver_private; |
2909 | |
2910 | mutex_lock(&hdmi->cec_notifier_mutex); |
2911 | cec_notifier_conn_unregister(n: hdmi->cec_notifier); |
2912 | hdmi->cec_notifier = NULL; |
2913 | mutex_unlock(lock: &hdmi->cec_notifier_mutex); |
2914 | } |
2915 | |
2916 | static enum drm_mode_status |
2917 | dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, |
2918 | const struct drm_display_info *info, |
2919 | const struct drm_display_mode *mode) |
2920 | { |
2921 | struct dw_hdmi *hdmi = bridge->driver_private; |
2922 | const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; |
2923 | enum drm_mode_status mode_status = MODE_OK; |
2924 | |
2925 | /* We don't support double-clocked modes */ |
2926 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
2927 | return MODE_BAD; |
2928 | |
2929 | if (pdata->mode_valid) |
2930 | mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info, |
2931 | mode); |
2932 | |
2933 | return mode_status; |
2934 | } |
2935 | |
2936 | static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, |
2937 | const struct drm_display_mode *orig_mode, |
2938 | const struct drm_display_mode *mode) |
2939 | { |
2940 | struct dw_hdmi *hdmi = bridge->driver_private; |
2941 | |
2942 | mutex_lock(&hdmi->mutex); |
2943 | |
2944 | /* Store the display mode for plugin/DKMS poweron events */ |
2945 | drm_mode_copy(dst: &hdmi->previous_mode, src: mode); |
2946 | |
2947 | mutex_unlock(lock: &hdmi->mutex); |
2948 | } |
2949 | |
2950 | static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, |
2951 | struct drm_bridge_state *old_state) |
2952 | { |
2953 | struct dw_hdmi *hdmi = bridge->driver_private; |
2954 | |
2955 | mutex_lock(&hdmi->mutex); |
2956 | hdmi->disabled = true; |
2957 | hdmi->curr_conn = NULL; |
2958 | dw_hdmi_update_power(hdmi); |
2959 | dw_hdmi_update_phy_mask(hdmi); |
2960 | handle_plugged_change(hdmi, plugged: false); |
2961 | mutex_unlock(lock: &hdmi->mutex); |
2962 | } |
2963 | |
2964 | static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, |
2965 | struct drm_bridge_state *old_state) |
2966 | { |
2967 | struct dw_hdmi *hdmi = bridge->driver_private; |
2968 | struct drm_atomic_state *state = old_state->base.state; |
2969 | struct drm_connector *connector; |
2970 | |
2971 | connector = drm_atomic_get_new_connector_for_encoder(state, |
2972 | encoder: bridge->encoder); |
2973 | |
2974 | mutex_lock(&hdmi->mutex); |
2975 | hdmi->disabled = false; |
2976 | hdmi->curr_conn = connector; |
2977 | dw_hdmi_update_power(hdmi); |
2978 | dw_hdmi_update_phy_mask(hdmi); |
2979 | handle_plugged_change(hdmi, plugged: true); |
2980 | mutex_unlock(lock: &hdmi->mutex); |
2981 | } |
2982 | |
2983 | static enum drm_connector_status dw_hdmi_bridge_detect(struct drm_bridge *bridge) |
2984 | { |
2985 | struct dw_hdmi *hdmi = bridge->driver_private; |
2986 | |
2987 | return dw_hdmi_detect(hdmi); |
2988 | } |
2989 | |
2990 | static const struct drm_edid *dw_hdmi_bridge_edid_read(struct drm_bridge *bridge, |
2991 | struct drm_connector *connector) |
2992 | { |
2993 | struct dw_hdmi *hdmi = bridge->driver_private; |
2994 | |
2995 | return dw_hdmi_edid_read(hdmi, connector); |
2996 | } |
2997 | |
2998 | static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { |
2999 | .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, |
3000 | .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, |
3001 | .atomic_reset = drm_atomic_helper_bridge_reset, |
3002 | .attach = dw_hdmi_bridge_attach, |
3003 | .detach = dw_hdmi_bridge_detach, |
3004 | .atomic_check = dw_hdmi_bridge_atomic_check, |
3005 | .atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts, |
3006 | .atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts, |
3007 | .atomic_enable = dw_hdmi_bridge_atomic_enable, |
3008 | .atomic_disable = dw_hdmi_bridge_atomic_disable, |
3009 | .mode_set = dw_hdmi_bridge_mode_set, |
3010 | .mode_valid = dw_hdmi_bridge_mode_valid, |
3011 | .detect = dw_hdmi_bridge_detect, |
3012 | .edid_read = dw_hdmi_bridge_edid_read, |
3013 | }; |
3014 | |
3015 | /* ----------------------------------------------------------------------------- |
3016 | * IRQ Handling |
3017 | */ |
3018 | |
3019 | static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) |
3020 | { |
3021 | struct dw_hdmi_i2c *i2c = hdmi->i2c; |
3022 | unsigned int stat; |
3023 | |
3024 | stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); |
3025 | if (!stat) |
3026 | return IRQ_NONE; |
3027 | |
3028 | hdmi_writeb(hdmi, val: stat, HDMI_IH_I2CM_STAT0); |
3029 | |
3030 | i2c->stat = stat; |
3031 | |
3032 | complete(&i2c->cmp); |
3033 | |
3034 | return IRQ_HANDLED; |
3035 | } |
3036 | |
3037 | static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) |
3038 | { |
3039 | struct dw_hdmi *hdmi = dev_id; |
3040 | u8 intr_stat; |
3041 | irqreturn_t ret = IRQ_NONE; |
3042 | |
3043 | if (hdmi->i2c) |
3044 | ret = dw_hdmi_i2c_irq(hdmi); |
3045 | |
3046 | intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); |
3047 | if (intr_stat) { |
3048 | hdmi_writeb(hdmi, val: ~0, HDMI_IH_MUTE_PHY_STAT0); |
3049 | return IRQ_WAKE_THREAD; |
3050 | } |
3051 | |
3052 | return ret; |
3053 | } |
3054 | |
3055 | void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) |
3056 | { |
3057 | mutex_lock(&hdmi->mutex); |
3058 | |
3059 | if (!hdmi->force) { |
3060 | /* |
3061 | * If the RX sense status indicates we're disconnected, |
3062 | * clear the software rxsense status. |
3063 | */ |
3064 | if (!rx_sense) |
3065 | hdmi->rxsense = false; |
3066 | |
3067 | /* |
3068 | * Only set the software rxsense status when both |
3069 | * rxsense and hpd indicates we're connected. |
3070 | * This avoids what seems to be bad behaviour in |
3071 | * at least iMX6S versions of the phy. |
3072 | */ |
3073 | if (hpd) |
3074 | hdmi->rxsense = true; |
3075 | |
3076 | dw_hdmi_update_power(hdmi); |
3077 | dw_hdmi_update_phy_mask(hdmi); |
3078 | } |
3079 | mutex_unlock(lock: &hdmi->mutex); |
3080 | } |
3081 | EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); |
3082 | |
3083 | static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) |
3084 | { |
3085 | struct dw_hdmi *hdmi = dev_id; |
3086 | u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; |
3087 | enum drm_connector_status status = connector_status_unknown; |
3088 | |
3089 | intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); |
3090 | phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); |
3091 | phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); |
3092 | |
3093 | phy_pol_mask = 0; |
3094 | if (intr_stat & HDMI_IH_PHY_STAT0_HPD) |
3095 | phy_pol_mask |= HDMI_PHY_HPD; |
3096 | if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) |
3097 | phy_pol_mask |= HDMI_PHY_RX_SENSE0; |
3098 | if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) |
3099 | phy_pol_mask |= HDMI_PHY_RX_SENSE1; |
3100 | if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) |
3101 | phy_pol_mask |= HDMI_PHY_RX_SENSE2; |
3102 | if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) |
3103 | phy_pol_mask |= HDMI_PHY_RX_SENSE3; |
3104 | |
3105 | if (phy_pol_mask) |
3106 | hdmi_modb(hdmi, data: ~phy_int_pol, mask: phy_pol_mask, HDMI_PHY_POL0); |
3107 | |
3108 | /* |
3109 | * RX sense tells us whether the TDMS transmitters are detecting |
3110 | * load - in other words, there's something listening on the |
3111 | * other end of the link. Use this to decide whether we should |
3112 | * power on the phy as HPD may be toggled by the sink to merely |
3113 | * ask the source to re-read the EDID. |
3114 | */ |
3115 | if (intr_stat & |
3116 | (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { |
3117 | dw_hdmi_setup_rx_sense(hdmi, |
3118 | phy_stat & HDMI_PHY_HPD, |
3119 | phy_stat & HDMI_PHY_RX_SENSE); |
3120 | |
3121 | if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { |
3122 | mutex_lock(&hdmi->cec_notifier_mutex); |
3123 | cec_notifier_phys_addr_invalidate(n: hdmi->cec_notifier); |
3124 | mutex_unlock(lock: &hdmi->cec_notifier_mutex); |
3125 | } |
3126 | |
3127 | if (phy_stat & HDMI_PHY_HPD) |
3128 | status = connector_status_connected; |
3129 | |
3130 | if (!(phy_stat & (HDMI_PHY_HPD | HDMI_PHY_RX_SENSE))) |
3131 | status = connector_status_disconnected; |
3132 | } |
3133 | |
3134 | if (status != connector_status_unknown) { |
3135 | dev_dbg(hdmi->dev, "EVENT=%s\n" , |
3136 | status == connector_status_connected ? |
3137 | "plugin" : "plugout" ); |
3138 | |
3139 | if (hdmi->bridge.dev) { |
3140 | drm_helper_hpd_irq_event(dev: hdmi->bridge.dev); |
3141 | drm_bridge_hpd_notify(bridge: &hdmi->bridge, status); |
3142 | } |
3143 | } |
3144 | |
3145 | hdmi_writeb(hdmi, val: intr_stat, HDMI_IH_PHY_STAT0); |
3146 | hdmi_writeb(hdmi, val: ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), |
3147 | HDMI_IH_MUTE_PHY_STAT0); |
3148 | |
3149 | return IRQ_HANDLED; |
3150 | } |
3151 | |
3152 | static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { |
3153 | { |
3154 | .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, |
3155 | .name = "DWC HDMI TX PHY" , |
3156 | .gen = 1, |
3157 | }, { |
3158 | .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, |
3159 | .name = "DWC MHL PHY + HEAC PHY" , |
3160 | .gen = 2, |
3161 | .has_svsret = true, |
3162 | .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, |
3163 | }, { |
3164 | .type = DW_HDMI_PHY_DWC_MHL_PHY, |
3165 | .name = "DWC MHL PHY" , |
3166 | .gen = 2, |
3167 | .has_svsret = true, |
3168 | .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, |
3169 | }, { |
3170 | .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, |
3171 | .name = "DWC HDMI 3D TX PHY + HEAC PHY" , |
3172 | .gen = 2, |
3173 | .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, |
3174 | }, { |
3175 | .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, |
3176 | .name = "DWC HDMI 3D TX PHY" , |
3177 | .gen = 2, |
3178 | .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, |
3179 | }, { |
3180 | .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, |
3181 | .name = "DWC HDMI 2.0 TX PHY" , |
3182 | .gen = 2, |
3183 | .has_svsret = true, |
3184 | .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, |
3185 | }, { |
3186 | .type = DW_HDMI_PHY_VENDOR_PHY, |
3187 | .name = "Vendor PHY" , |
3188 | } |
3189 | }; |
3190 | |
3191 | static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) |
3192 | { |
3193 | unsigned int i; |
3194 | u8 phy_type; |
3195 | |
3196 | phy_type = hdmi->plat_data->phy_force_vendor ? |
3197 | DW_HDMI_PHY_VENDOR_PHY : |
3198 | hdmi_readb(hdmi, HDMI_CONFIG2_ID); |
3199 | |
3200 | if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { |
3201 | /* Vendor PHYs require support from the glue layer. */ |
3202 | if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { |
3203 | dev_err(hdmi->dev, |
3204 | "Vendor HDMI PHY not supported by glue layer\n" ); |
3205 | return -ENODEV; |
3206 | } |
3207 | |
3208 | hdmi->phy.ops = hdmi->plat_data->phy_ops; |
3209 | hdmi->phy.data = hdmi->plat_data->phy_data; |
3210 | hdmi->phy.name = hdmi->plat_data->phy_name; |
3211 | return 0; |
3212 | } |
3213 | |
3214 | /* Synopsys PHYs are handled internally. */ |
3215 | for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { |
3216 | if (dw_hdmi_phys[i].type == phy_type) { |
3217 | hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; |
3218 | hdmi->phy.name = dw_hdmi_phys[i].name; |
3219 | hdmi->phy.data = (void *)&dw_hdmi_phys[i]; |
3220 | |
3221 | if (!dw_hdmi_phys[i].configure && |
3222 | !hdmi->plat_data->configure_phy) { |
3223 | dev_err(hdmi->dev, "%s requires platform support\n" , |
3224 | hdmi->phy.name); |
3225 | return -ENODEV; |
3226 | } |
3227 | |
3228 | return 0; |
3229 | } |
3230 | } |
3231 | |
3232 | dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n" , phy_type); |
3233 | return -ENODEV; |
3234 | } |
3235 | |
3236 | static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) |
3237 | { |
3238 | mutex_lock(&hdmi->mutex); |
3239 | hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; |
3240 | hdmi_writeb(hdmi, val: hdmi->mc_clkdis, HDMI_MC_CLKDIS); |
3241 | mutex_unlock(lock: &hdmi->mutex); |
3242 | } |
3243 | |
3244 | static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) |
3245 | { |
3246 | mutex_lock(&hdmi->mutex); |
3247 | hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; |
3248 | hdmi_writeb(hdmi, val: hdmi->mc_clkdis, HDMI_MC_CLKDIS); |
3249 | mutex_unlock(lock: &hdmi->mutex); |
3250 | } |
3251 | |
3252 | static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { |
3253 | .write = hdmi_writeb, |
3254 | .read = hdmi_readb, |
3255 | .enable = dw_hdmi_cec_enable, |
3256 | .disable = dw_hdmi_cec_disable, |
3257 | }; |
3258 | |
3259 | static const struct regmap_config hdmi_regmap_8bit_config = { |
3260 | .reg_bits = 32, |
3261 | .val_bits = 8, |
3262 | .reg_stride = 1, |
3263 | .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, |
3264 | }; |
3265 | |
3266 | static const struct regmap_config hdmi_regmap_32bit_config = { |
3267 | .reg_bits = 32, |
3268 | .val_bits = 32, |
3269 | .reg_stride = 4, |
3270 | .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, |
3271 | }; |
3272 | |
3273 | static void dw_hdmi_init_hw(struct dw_hdmi *hdmi) |
3274 | { |
3275 | initialize_hdmi_ih_mutes(hdmi); |
3276 | |
3277 | /* |
3278 | * Reset HDMI DDC I2C master controller and mute I2CM interrupts. |
3279 | * Even if we are using a separate i2c adapter doing this doesn't |
3280 | * hurt. |
3281 | */ |
3282 | dw_hdmi_i2c_init(hdmi); |
3283 | |
3284 | if (hdmi->phy.ops->setup_hpd) |
3285 | hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); |
3286 | } |
3287 | |
3288 | /* ----------------------------------------------------------------------------- |
3289 | * Probe/remove API, used from platforms based on the DRM bridge API. |
3290 | */ |
3291 | |
3292 | static int dw_hdmi_parse_dt(struct dw_hdmi *hdmi) |
3293 | { |
3294 | struct device_node *endpoint; |
3295 | struct device_node *remote; |
3296 | |
3297 | if (!hdmi->plat_data->output_port) |
3298 | return 0; |
3299 | |
3300 | endpoint = of_graph_get_endpoint_by_regs(parent: hdmi->dev->of_node, |
3301 | port_reg: hdmi->plat_data->output_port, |
3302 | reg: -1); |
3303 | if (!endpoint) { |
3304 | /* |
3305 | * On platforms whose bindings don't make the output port |
3306 | * mandatory (such as Rockchip) the plat_data->output_port |
3307 | * field isn't set, so it's safe to make this a fatal error. |
3308 | */ |
3309 | dev_err(hdmi->dev, "Missing endpoint in port@%u\n" , |
3310 | hdmi->plat_data->output_port); |
3311 | return -ENODEV; |
3312 | } |
3313 | |
3314 | remote = of_graph_get_remote_port_parent(node: endpoint); |
3315 | of_node_put(node: endpoint); |
3316 | if (!remote) { |
3317 | dev_err(hdmi->dev, "Endpoint in port@%u unconnected\n" , |
3318 | hdmi->plat_data->output_port); |
3319 | return -ENODEV; |
3320 | } |
3321 | |
3322 | if (!of_device_is_available(device: remote)) { |
3323 | dev_err(hdmi->dev, "port@%u remote device is disabled\n" , |
3324 | hdmi->plat_data->output_port); |
3325 | of_node_put(node: remote); |
3326 | return -ENODEV; |
3327 | } |
3328 | |
3329 | hdmi->next_bridge = of_drm_find_bridge(np: remote); |
3330 | of_node_put(node: remote); |
3331 | if (!hdmi->next_bridge) |
3332 | return -EPROBE_DEFER; |
3333 | |
3334 | return 0; |
3335 | } |
3336 | |
3337 | bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi) |
3338 | { |
3339 | return hdmi_bus_fmt_is_yuv420(bus_format: hdmi->hdmi_data.enc_out_bus_format); |
3340 | } |
3341 | EXPORT_SYMBOL_GPL(dw_hdmi_bus_fmt_is_420); |
3342 | |
3343 | struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, |
3344 | const struct dw_hdmi_plat_data *plat_data) |
3345 | { |
3346 | struct device *dev = &pdev->dev; |
3347 | struct device_node *np = dev->of_node; |
3348 | struct platform_device_info pdevinfo; |
3349 | struct device_node *ddc_node; |
3350 | struct dw_hdmi_cec_data cec; |
3351 | struct dw_hdmi *hdmi; |
3352 | struct resource *iores = NULL; |
3353 | int irq; |
3354 | int ret; |
3355 | u32 val = 1; |
3356 | u8 prod_id0; |
3357 | u8 prod_id1; |
3358 | u8 config0; |
3359 | u8 config3; |
3360 | |
3361 | hdmi = devm_kzalloc(dev, size: sizeof(*hdmi), GFP_KERNEL); |
3362 | if (!hdmi) |
3363 | return ERR_PTR(error: -ENOMEM); |
3364 | |
3365 | hdmi->plat_data = plat_data; |
3366 | hdmi->dev = dev; |
3367 | hdmi->sample_rate = 48000; |
3368 | hdmi->channels = 2; |
3369 | hdmi->disabled = true; |
3370 | hdmi->rxsense = true; |
3371 | hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); |
3372 | hdmi->mc_clkdis = 0x7f; |
3373 | hdmi->last_connector_result = connector_status_disconnected; |
3374 | |
3375 | mutex_init(&hdmi->mutex); |
3376 | mutex_init(&hdmi->audio_mutex); |
3377 | mutex_init(&hdmi->cec_notifier_mutex); |
3378 | spin_lock_init(&hdmi->audio_lock); |
3379 | |
3380 | ret = dw_hdmi_parse_dt(hdmi); |
3381 | if (ret < 0) |
3382 | return ERR_PTR(error: ret); |
3383 | |
3384 | ddc_node = of_parse_phandle(np, phandle_name: "ddc-i2c-bus" , index: 0); |
3385 | if (ddc_node) { |
3386 | hdmi->ddc = of_get_i2c_adapter_by_node(node: ddc_node); |
3387 | of_node_put(node: ddc_node); |
3388 | if (!hdmi->ddc) { |
3389 | dev_dbg(hdmi->dev, "failed to read ddc node\n" ); |
3390 | return ERR_PTR(error: -EPROBE_DEFER); |
3391 | } |
3392 | |
3393 | } else { |
3394 | dev_dbg(hdmi->dev, "no ddc property found\n" ); |
3395 | } |
3396 | |
3397 | if (!plat_data->regm) { |
3398 | const struct regmap_config *reg_config; |
3399 | |
3400 | of_property_read_u32(np, propname: "reg-io-width" , out_value: &val); |
3401 | switch (val) { |
3402 | case 4: |
3403 | reg_config = &hdmi_regmap_32bit_config; |
3404 | hdmi->reg_shift = 2; |
3405 | break; |
3406 | case 1: |
3407 | reg_config = &hdmi_regmap_8bit_config; |
3408 | break; |
3409 | default: |
3410 | dev_err(dev, "reg-io-width must be 1 or 4\n" ); |
3411 | return ERR_PTR(error: -EINVAL); |
3412 | } |
3413 | |
3414 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
3415 | hdmi->regs = devm_ioremap_resource(dev, res: iores); |
3416 | if (IS_ERR(ptr: hdmi->regs)) { |
3417 | ret = PTR_ERR(ptr: hdmi->regs); |
3418 | goto err_res; |
3419 | } |
3420 | |
3421 | hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); |
3422 | if (IS_ERR(ptr: hdmi->regm)) { |
3423 | dev_err(dev, "Failed to configure regmap\n" ); |
3424 | ret = PTR_ERR(ptr: hdmi->regm); |
3425 | goto err_res; |
3426 | } |
3427 | } else { |
3428 | hdmi->regm = plat_data->regm; |
3429 | } |
3430 | |
3431 | hdmi->isfr_clk = devm_clk_get(dev: hdmi->dev, id: "isfr" ); |
3432 | if (IS_ERR(ptr: hdmi->isfr_clk)) { |
3433 | ret = PTR_ERR(ptr: hdmi->isfr_clk); |
3434 | dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n" , ret); |
3435 | goto err_res; |
3436 | } |
3437 | |
3438 | ret = clk_prepare_enable(clk: hdmi->isfr_clk); |
3439 | if (ret) { |
3440 | dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n" , ret); |
3441 | goto err_res; |
3442 | } |
3443 | |
3444 | hdmi->iahb_clk = devm_clk_get(dev: hdmi->dev, id: "iahb" ); |
3445 | if (IS_ERR(ptr: hdmi->iahb_clk)) { |
3446 | ret = PTR_ERR(ptr: hdmi->iahb_clk); |
3447 | dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n" , ret); |
3448 | goto err_isfr; |
3449 | } |
3450 | |
3451 | ret = clk_prepare_enable(clk: hdmi->iahb_clk); |
3452 | if (ret) { |
3453 | dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n" , ret); |
3454 | goto err_isfr; |
3455 | } |
3456 | |
3457 | hdmi->cec_clk = devm_clk_get(dev: hdmi->dev, id: "cec" ); |
3458 | if (PTR_ERR(ptr: hdmi->cec_clk) == -ENOENT) { |
3459 | hdmi->cec_clk = NULL; |
3460 | } else if (IS_ERR(ptr: hdmi->cec_clk)) { |
3461 | ret = PTR_ERR(ptr: hdmi->cec_clk); |
3462 | if (ret != -EPROBE_DEFER) |
3463 | dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n" , |
3464 | ret); |
3465 | |
3466 | hdmi->cec_clk = NULL; |
3467 | goto err_iahb; |
3468 | } else { |
3469 | ret = clk_prepare_enable(clk: hdmi->cec_clk); |
3470 | if (ret) { |
3471 | dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n" , |
3472 | ret); |
3473 | goto err_iahb; |
3474 | } |
3475 | } |
3476 | |
3477 | /* Product and revision IDs */ |
3478 | hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) |
3479 | | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); |
3480 | prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); |
3481 | prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); |
3482 | |
3483 | if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || |
3484 | (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { |
3485 | dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n" , |
3486 | hdmi->version, prod_id0, prod_id1); |
3487 | ret = -ENODEV; |
3488 | goto err_iahb; |
3489 | } |
3490 | |
3491 | ret = dw_hdmi_detect_phy(hdmi); |
3492 | if (ret < 0) |
3493 | goto err_iahb; |
3494 | |
3495 | dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n" , |
3496 | hdmi->version >> 12, hdmi->version & 0xfff, |
3497 | prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without" , |
3498 | hdmi->phy.name); |
3499 | |
3500 | dw_hdmi_init_hw(hdmi); |
3501 | |
3502 | irq = platform_get_irq(pdev, 0); |
3503 | if (irq < 0) { |
3504 | ret = irq; |
3505 | goto err_iahb; |
3506 | } |
3507 | |
3508 | ret = devm_request_threaded_irq(dev, irq, handler: dw_hdmi_hardirq, |
3509 | thread_fn: dw_hdmi_irq, IRQF_SHARED, |
3510 | devname: dev_name(dev), dev_id: hdmi); |
3511 | if (ret) |
3512 | goto err_iahb; |
3513 | |
3514 | /* |
3515 | * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator |
3516 | * N and cts values before enabling phy |
3517 | */ |
3518 | hdmi_init_clk_regenerator(hdmi); |
3519 | |
3520 | /* If DDC bus is not specified, try to register HDMI I2C bus */ |
3521 | if (!hdmi->ddc) { |
3522 | /* Look for (optional) stuff related to unwedging */ |
3523 | hdmi->pinctrl = devm_pinctrl_get(dev); |
3524 | if (!IS_ERR(ptr: hdmi->pinctrl)) { |
3525 | hdmi->unwedge_state = |
3526 | pinctrl_lookup_state(p: hdmi->pinctrl, name: "unwedge" ); |
3527 | hdmi->default_state = |
3528 | pinctrl_lookup_state(p: hdmi->pinctrl, name: "default" ); |
3529 | |
3530 | if (IS_ERR(ptr: hdmi->default_state) || |
3531 | IS_ERR(ptr: hdmi->unwedge_state)) { |
3532 | if (!IS_ERR(ptr: hdmi->unwedge_state)) |
3533 | dev_warn(dev, |
3534 | "Unwedge requires default pinctrl\n" ); |
3535 | hdmi->default_state = NULL; |
3536 | hdmi->unwedge_state = NULL; |
3537 | } |
3538 | } |
3539 | |
3540 | hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); |
3541 | if (IS_ERR(ptr: hdmi->ddc)) |
3542 | hdmi->ddc = NULL; |
3543 | } |
3544 | |
3545 | hdmi->bridge.driver_private = hdmi; |
3546 | hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; |
3547 | hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
3548 | | DRM_BRIDGE_OP_HPD; |
3549 | hdmi->bridge.interlace_allowed = true; |
3550 | hdmi->bridge.ddc = hdmi->ddc; |
3551 | hdmi->bridge.of_node = pdev->dev.of_node; |
3552 | hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; |
3553 | |
3554 | memset(&pdevinfo, 0, sizeof(pdevinfo)); |
3555 | pdevinfo.parent = dev; |
3556 | pdevinfo.id = PLATFORM_DEVID_AUTO; |
3557 | |
3558 | config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); |
3559 | config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); |
3560 | |
3561 | if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { |
3562 | struct dw_hdmi_audio_data audio; |
3563 | |
3564 | audio.phys = iores->start; |
3565 | audio.base = hdmi->regs; |
3566 | audio.irq = irq; |
3567 | audio.hdmi = hdmi; |
3568 | audio.get_eld = hdmi_audio_get_eld; |
3569 | hdmi->enable_audio = dw_hdmi_ahb_audio_enable; |
3570 | hdmi->disable_audio = dw_hdmi_ahb_audio_disable; |
3571 | |
3572 | pdevinfo.name = "dw-hdmi-ahb-audio" ; |
3573 | pdevinfo.data = &audio; |
3574 | pdevinfo.size_data = sizeof(audio); |
3575 | pdevinfo.dma_mask = DMA_BIT_MASK(32); |
3576 | hdmi->audio = platform_device_register_full(pdevinfo: &pdevinfo); |
3577 | } else if (config0 & HDMI_CONFIG0_I2S) { |
3578 | struct dw_hdmi_i2s_audio_data audio; |
3579 | |
3580 | audio.hdmi = hdmi; |
3581 | audio.get_eld = hdmi_audio_get_eld; |
3582 | audio.write = hdmi_writeb; |
3583 | audio.read = hdmi_readb; |
3584 | hdmi->enable_audio = dw_hdmi_i2s_audio_enable; |
3585 | hdmi->disable_audio = dw_hdmi_i2s_audio_disable; |
3586 | |
3587 | pdevinfo.name = "dw-hdmi-i2s-audio" ; |
3588 | pdevinfo.data = &audio; |
3589 | pdevinfo.size_data = sizeof(audio); |
3590 | pdevinfo.dma_mask = DMA_BIT_MASK(32); |
3591 | hdmi->audio = platform_device_register_full(pdevinfo: &pdevinfo); |
3592 | } else if (iores && config3 & HDMI_CONFIG3_GPAUD) { |
3593 | struct dw_hdmi_audio_data audio; |
3594 | |
3595 | audio.phys = iores->start; |
3596 | audio.base = hdmi->regs; |
3597 | audio.irq = irq; |
3598 | audio.hdmi = hdmi; |
3599 | audio.get_eld = hdmi_audio_get_eld; |
3600 | |
3601 | hdmi->enable_audio = dw_hdmi_gp_audio_enable; |
3602 | hdmi->disable_audio = dw_hdmi_gp_audio_disable; |
3603 | |
3604 | pdevinfo.name = "dw-hdmi-gp-audio" ; |
3605 | pdevinfo.id = PLATFORM_DEVID_NONE; |
3606 | pdevinfo.data = &audio; |
3607 | pdevinfo.size_data = sizeof(audio); |
3608 | pdevinfo.dma_mask = DMA_BIT_MASK(32); |
3609 | hdmi->audio = platform_device_register_full(pdevinfo: &pdevinfo); |
3610 | } |
3611 | |
3612 | if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) { |
3613 | cec.hdmi = hdmi; |
3614 | cec.ops = &dw_hdmi_cec_ops; |
3615 | cec.irq = irq; |
3616 | |
3617 | pdevinfo.name = "dw-hdmi-cec" ; |
3618 | pdevinfo.data = &cec; |
3619 | pdevinfo.size_data = sizeof(cec); |
3620 | pdevinfo.dma_mask = 0; |
3621 | |
3622 | hdmi->cec = platform_device_register_full(pdevinfo: &pdevinfo); |
3623 | } |
3624 | |
3625 | drm_bridge_add(bridge: &hdmi->bridge); |
3626 | |
3627 | return hdmi; |
3628 | |
3629 | err_iahb: |
3630 | clk_disable_unprepare(clk: hdmi->iahb_clk); |
3631 | clk_disable_unprepare(clk: hdmi->cec_clk); |
3632 | err_isfr: |
3633 | clk_disable_unprepare(clk: hdmi->isfr_clk); |
3634 | err_res: |
3635 | i2c_put_adapter(adap: hdmi->ddc); |
3636 | |
3637 | return ERR_PTR(error: ret); |
3638 | } |
3639 | EXPORT_SYMBOL_GPL(dw_hdmi_probe); |
3640 | |
3641 | void dw_hdmi_remove(struct dw_hdmi *hdmi) |
3642 | { |
3643 | drm_bridge_remove(bridge: &hdmi->bridge); |
3644 | |
3645 | if (hdmi->audio && !IS_ERR(ptr: hdmi->audio)) |
3646 | platform_device_unregister(hdmi->audio); |
3647 | if (!IS_ERR(ptr: hdmi->cec)) |
3648 | platform_device_unregister(hdmi->cec); |
3649 | |
3650 | /* Disable all interrupts */ |
3651 | hdmi_writeb(hdmi, val: ~0, HDMI_IH_MUTE_PHY_STAT0); |
3652 | |
3653 | clk_disable_unprepare(clk: hdmi->iahb_clk); |
3654 | clk_disable_unprepare(clk: hdmi->isfr_clk); |
3655 | clk_disable_unprepare(clk: hdmi->cec_clk); |
3656 | |
3657 | if (hdmi->i2c) |
3658 | i2c_del_adapter(adap: &hdmi->i2c->adap); |
3659 | else |
3660 | i2c_put_adapter(adap: hdmi->ddc); |
3661 | } |
3662 | EXPORT_SYMBOL_GPL(dw_hdmi_remove); |
3663 | |
3664 | /* ----------------------------------------------------------------------------- |
3665 | * Bind/unbind API, used from platforms based on the component framework. |
3666 | */ |
3667 | struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, |
3668 | struct drm_encoder *encoder, |
3669 | const struct dw_hdmi_plat_data *plat_data) |
3670 | { |
3671 | struct dw_hdmi *hdmi; |
3672 | int ret; |
3673 | |
3674 | hdmi = dw_hdmi_probe(pdev, plat_data); |
3675 | if (IS_ERR(ptr: hdmi)) |
3676 | return hdmi; |
3677 | |
3678 | ret = drm_bridge_attach(encoder, bridge: &hdmi->bridge, NULL, flags: 0); |
3679 | if (ret) { |
3680 | dw_hdmi_remove(hdmi); |
3681 | return ERR_PTR(error: ret); |
3682 | } |
3683 | |
3684 | return hdmi; |
3685 | } |
3686 | EXPORT_SYMBOL_GPL(dw_hdmi_bind); |
3687 | |
3688 | void dw_hdmi_unbind(struct dw_hdmi *hdmi) |
3689 | { |
3690 | dw_hdmi_remove(hdmi); |
3691 | } |
3692 | EXPORT_SYMBOL_GPL(dw_hdmi_unbind); |
3693 | |
3694 | void dw_hdmi_resume(struct dw_hdmi *hdmi) |
3695 | { |
3696 | dw_hdmi_init_hw(hdmi); |
3697 | } |
3698 | EXPORT_SYMBOL_GPL(dw_hdmi_resume); |
3699 | |
3700 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>" ); |
3701 | MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>" ); |
3702 | MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>" ); |
3703 | MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>" ); |
3704 | MODULE_DESCRIPTION("DW HDMI transmitter driver" ); |
3705 | MODULE_LICENSE("GPL" ); |
3706 | MODULE_ALIAS("platform:dw-hdmi" ); |
3707 | |