1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
5 */
6
7#include <linux/atomic.h>
8#include <linux/auxiliary_bus.h>
9#include <linux/bitfield.h>
10#include <linux/bits.h>
11#include <linux/clk.h>
12#include <linux/debugfs.h>
13#include <linux/gpio/consumer.h>
14#include <linux/gpio/driver.h>
15#include <linux/i2c.h>
16#include <linux/iopoll.h>
17#include <linux/module.h>
18#include <linux/of_graph.h>
19#include <linux/pm_runtime.h>
20#include <linux/pwm.h>
21#include <linux/regmap.h>
22#include <linux/regulator/consumer.h>
23
24#include <linux/unaligned.h>
25
26#include <drm/display/drm_dp_aux_bus.h>
27#include <drm/display/drm_dp_helper.h>
28#include <drm/drm_atomic.h>
29#include <drm/drm_atomic_helper.h>
30#include <drm/drm_bridge.h>
31#include <drm/drm_bridge_connector.h>
32#include <drm/drm_edid.h>
33#include <drm/drm_mipi_dsi.h>
34#include <drm/drm_of.h>
35#include <drm/drm_print.h>
36#include <drm/drm_probe_helper.h>
37
38#define SN_DEVICE_ID_REGS 0x00 /* up to 0x07 */
39#define SN_DEVICE_REV_REG 0x08
40#define SN_DPPLL_SRC_REG 0x0A
41#define DPPLL_CLK_SRC_DSICLK BIT(0)
42#define REFCLK_FREQ_MASK GENMASK(3, 1)
43#define REFCLK_FREQ(x) ((x) << 1)
44#define DPPLL_SRC_DP_PLL_LOCK BIT(7)
45#define SN_PLL_ENABLE_REG 0x0D
46#define SN_DSI_LANES_REG 0x10
47#define CHA_DSI_LANES_MASK GENMASK(4, 3)
48#define CHA_DSI_LANES(x) ((x) << 3)
49#define SN_DSIA_CLK_FREQ_REG 0x12
50#define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
51#define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
52#define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
53#define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
54#define CHA_HSYNC_POLARITY BIT(7)
55#define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
56#define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
57#define CHA_VSYNC_POLARITY BIT(7)
58#define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
59#define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
60#define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
61#define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
62#define SN_LN_ASSIGN_REG 0x59
63#define LN_ASSIGN_WIDTH 2
64#define SN_ENH_FRAME_REG 0x5A
65#define VSTREAM_ENABLE BIT(3)
66#define LN_POLRS_OFFSET 4
67#define LN_POLRS_MASK 0xf0
68#define SN_DATA_FORMAT_REG 0x5B
69#define BPP_18_RGB BIT(0)
70#define SN_HPD_DISABLE_REG 0x5C
71#define HPD_DISABLE BIT(0)
72#define HPD_DEBOUNCED_STATE BIT(4)
73#define SN_GPIO_IO_REG 0x5E
74#define SN_GPIO_INPUT_SHIFT 4
75#define SN_GPIO_OUTPUT_SHIFT 0
76#define SN_GPIO_CTRL_REG 0x5F
77#define SN_GPIO_MUX_INPUT 0
78#define SN_GPIO_MUX_OUTPUT 1
79#define SN_GPIO_MUX_SPECIAL 2
80#define SN_GPIO_MUX_MASK 0x3
81#define SN_AUX_WDATA_REG(x) (0x64 + (x))
82#define SN_AUX_ADDR_19_16_REG 0x74
83#define SN_AUX_ADDR_15_8_REG 0x75
84#define SN_AUX_ADDR_7_0_REG 0x76
85#define SN_AUX_ADDR_MASK GENMASK(19, 0)
86#define SN_AUX_LENGTH_REG 0x77
87#define SN_AUX_CMD_REG 0x78
88#define AUX_CMD_SEND BIT(0)
89#define AUX_CMD_REQ(x) ((x) << 4)
90#define SN_AUX_RDATA_REG(x) (0x79 + (x))
91#define SN_SSC_CONFIG_REG 0x93
92#define DP_NUM_LANES_MASK GENMASK(5, 4)
93#define DP_NUM_LANES(x) ((x) << 4)
94#define SN_DATARATE_CONFIG_REG 0x94
95#define DP_DATARATE_MASK GENMASK(7, 5)
96#define DP_DATARATE(x) ((x) << 5)
97#define SN_TRAINING_SETTING_REG 0x95
98#define SCRAMBLE_DISABLE BIT(4)
99#define SN_ML_TX_MODE_REG 0x96
100#define ML_TX_MAIN_LINK_OFF 0
101#define ML_TX_NORMAL_MODE BIT(0)
102#define SN_PWM_PRE_DIV_REG 0xA0
103#define SN_BACKLIGHT_SCALE_REG 0xA1
104#define BACKLIGHT_SCALE_MAX 0xFFFF
105#define SN_BACKLIGHT_REG 0xA3
106#define SN_PWM_EN_INV_REG 0xA5
107#define SN_PWM_INV_MASK BIT(0)
108#define SN_PWM_EN_MASK BIT(1)
109
110#define SN_IRQ_EN_REG 0xE0
111#define IRQ_EN BIT(0)
112
113#define SN_IRQ_EVENTS_EN_REG 0xE6
114#define HPD_INSERTION_EN BIT(1)
115#define HPD_REMOVAL_EN BIT(2)
116
117#define SN_AUX_CMD_STATUS_REG 0xF4
118#define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
119#define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
120#define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
121#define SN_IRQ_STATUS_REG 0xF5
122#define HPD_REMOVAL_STATUS BIT(2)
123#define HPD_INSERTION_STATUS BIT(1)
124
125#define MIN_DSI_CLK_FREQ_MHZ 40
126
127/* fudge factor required to account for 8b/10b encoding */
128#define DP_CLK_FUDGE_NUM 10
129#define DP_CLK_FUDGE_DEN 8
130
131/* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
132#define SN_AUX_MAX_PAYLOAD_BYTES 16
133
134#define SN_REGULATOR_SUPPLY_NUM 4
135
136#define SN_MAX_DP_LANES 4
137#define SN_NUM_GPIOS 4
138#define SN_GPIO_PHYSICAL_OFFSET 1
139
140#define SN_LINK_TRAINING_TRIES 10
141
142#define SN_PWM_GPIO_IDX 3 /* 4th GPIO */
143
144/**
145 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
146 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
147 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
148 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
149 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
150 *
151 * @dev: Pointer to the top level (i2c) device.
152 * @regmap: Regmap for accessing i2c.
153 * @aux: Our aux channel.
154 * @bridge: Our bridge.
155 * @connector: Our connector.
156 * @host_node: Remote DSI node.
157 * @dsi: Our MIPI DSI source.
158 * @refclk: Our reference clock.
159 * @next_bridge: The bridge on the eDP side.
160 * @enable_gpio: The GPIO we toggle to enable the bridge.
161 * @supplies: Data for bulk enabling/disabling our regulators.
162 * @dp_lanes: Count of dp_lanes we're using.
163 * @ln_assign: Value to program to the LN_ASSIGN register.
164 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
165 * @comms_enabled: If true then communication over the aux channel is enabled.
166 * @hpd_enabled: If true then HPD events are enabled.
167 * @comms_mutex: Protects modification of comms_enabled.
168 * @hpd_mutex: Protects modification of hpd_enabled.
169 *
170 * @gchip: If we expose our GPIOs, this is used.
171 * @gchip_output: A cache of whether we've set GPIOs to output. This
172 * serves double-duty of keeping track of the direction and
173 * also keeping track of whether we've incremented the
174 * pm_runtime reference count for this pin, which we do
175 * whenever a pin is configured as an output. This is a
176 * bitmap so we can do atomic ops on it without an extra
177 * lock so concurrent users of our 4 GPIOs don't stomp on
178 * each other's read-modify-write.
179 *
180 * @pchip: pwm_chip if the PWM is exposed.
181 * @pwm_enabled: Used to track if the PWM signal is currently enabled.
182 * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM.
183 * @pwm_refclk_freq: Cache for the reference clock input to the PWM.
184 */
185struct ti_sn65dsi86 {
186 struct auxiliary_device *bridge_aux;
187 struct auxiliary_device *gpio_aux;
188 struct auxiliary_device *aux_aux;
189 struct auxiliary_device *pwm_aux;
190
191 struct device *dev;
192 struct regmap *regmap;
193 struct drm_dp_aux aux;
194 struct drm_bridge bridge;
195 struct drm_connector *connector;
196 struct device_node *host_node;
197 struct mipi_dsi_device *dsi;
198 struct clk *refclk;
199 struct drm_bridge *next_bridge;
200 struct gpio_desc *enable_gpio;
201 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM];
202 int dp_lanes;
203 u8 ln_assign;
204 u8 ln_polrs;
205 bool comms_enabled;
206 bool hpd_enabled;
207 struct mutex comms_mutex;
208 struct mutex hpd_mutex;
209
210#if defined(CONFIG_OF_GPIO)
211 struct gpio_chip gchip;
212 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
213#endif
214#if IS_REACHABLE(CONFIG_PWM)
215 struct pwm_chip *pchip;
216 bool pwm_enabled;
217 atomic_t pwm_pin_busy;
218#endif
219 unsigned int pwm_refclk_freq;
220};
221
222static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = {
223 { .range_min = 0, .range_max = 0xFF },
224};
225
226static const struct regmap_access_table ti_sn_bridge_volatile_table = {
227 .yes_ranges = ti_sn65dsi86_volatile_ranges,
228 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges),
229};
230
231static const struct regmap_config ti_sn65dsi86_regmap_config = {
232 .reg_bits = 8,
233 .val_bits = 8,
234 .volatile_table = &ti_sn_bridge_volatile_table,
235 .cache_type = REGCACHE_NONE,
236 .max_register = 0xFF,
237};
238
239static int ti_sn65dsi86_read_u8(struct ti_sn65dsi86 *pdata, unsigned int reg,
240 u8 *val)
241{
242 int ret;
243 unsigned int reg_val;
244
245 ret = regmap_read(map: pdata->regmap, reg, val: &reg_val);
246 if (ret) {
247 dev_err(pdata->dev, "fail to read raw reg %#x: %d\n",
248 reg, ret);
249 return ret;
250 }
251 *val = (u8)reg_val;
252
253 return 0;
254}
255
256static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata,
257 unsigned int reg, u16 *val)
258{
259 u8 buf[2];
260 int ret;
261
262 ret = regmap_bulk_read(map: pdata->regmap, reg, val: buf, ARRAY_SIZE(buf));
263 if (ret)
264 return ret;
265
266 *val = buf[0] | (buf[1] << 8);
267
268 return 0;
269}
270
271static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata,
272 unsigned int reg, u16 val)
273{
274 u8 buf[2] = { val & 0xff, val >> 8 };
275
276 regmap_bulk_write(map: pdata->regmap, reg, val: buf, ARRAY_SIZE(buf));
277}
278
279static struct drm_display_mode *
280get_new_adjusted_display_mode(struct drm_bridge *bridge,
281 struct drm_atomic_state *state)
282{
283 struct drm_connector *connector =
284 drm_atomic_get_new_connector_for_encoder(state, encoder: bridge->encoder);
285 struct drm_connector_state *conn_state =
286 drm_atomic_get_new_connector_state(state, connector);
287 struct drm_crtc_state *crtc_state =
288 drm_atomic_get_new_crtc_state(state, crtc: conn_state->crtc);
289
290 return &crtc_state->adjusted_mode;
291}
292
293static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata,
294 struct drm_atomic_state *state)
295{
296 u32 bit_rate_khz, clk_freq_khz;
297 struct drm_display_mode *mode =
298 get_new_adjusted_display_mode(bridge: &pdata->bridge, state);
299
300 bit_rate_khz = mode->clock *
301 mipi_dsi_pixel_format_to_bpp(fmt: pdata->dsi->format);
302 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
303
304 return clk_freq_khz;
305}
306
307/* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
308static const u32 ti_sn_bridge_refclk_lut[] = {
309 12000000,
310 19200000,
311 26000000,
312 27000000,
313 38400000,
314};
315
316/* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
317static const u32 ti_sn_bridge_dsiclk_lut[] = {
318 468000000,
319 384000000,
320 416000000,
321 486000000,
322 460800000,
323};
324
325static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata,
326 struct drm_atomic_state *state)
327{
328 int i;
329 u32 refclk_rate;
330 const u32 *refclk_lut;
331 size_t refclk_lut_size;
332
333 if (pdata->refclk) {
334 refclk_rate = clk_get_rate(clk: pdata->refclk);
335 refclk_lut = ti_sn_bridge_refclk_lut;
336 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
337 clk_prepare_enable(clk: pdata->refclk);
338 } else {
339 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata, state) * 1000;
340 refclk_lut = ti_sn_bridge_dsiclk_lut;
341 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
342 }
343
344 /* for i equals to refclk_lut_size means default frequency */
345 for (i = 0; i < refclk_lut_size; i++)
346 if (refclk_lut[i] == refclk_rate)
347 break;
348
349 /* avoid buffer overflow and "1" is the default rate in the datasheet. */
350 if (i >= refclk_lut_size)
351 i = 1;
352
353 regmap_update_bits(map: pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
354 REFCLK_FREQ(i));
355
356 /*
357 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG,
358 * regardless of its actual sourcing.
359 */
360 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i];
361}
362
363static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata,
364 struct drm_atomic_state *state)
365{
366 mutex_lock(&pdata->comms_mutex);
367
368 /* configure bridge ref_clk */
369 ti_sn_bridge_set_refclk_freq(pdata, state);
370
371 /*
372 * HPD on this bridge chip is a bit useless. This is an eDP bridge
373 * so the HPD is an internal signal that's only there to signal that
374 * the panel is done powering up. ...but the bridge chip debounces
375 * this signal by between 100 ms and 400 ms (depending on process,
376 * voltage, and temperate--I measured it at about 200 ms). One
377 * particular panel asserted HPD 84 ms after it was powered on meaning
378 * that we saw HPD 284 ms after power on. ...but the same panel said
379 * that instead of looking at HPD you could just hardcode a delay of
380 * 200 ms. We'll assume that the panel driver will have the hardcoded
381 * delay in its prepare and always disable HPD.
382 *
383 * For DisplayPort bridge type, we need HPD. So we use the bridge type
384 * to conditionally disable HPD.
385 * NOTE: The bridge type is set in ti_sn_bridge_probe() but enable_comms()
386 * can be called before. So for DisplayPort, HPD will be enabled once
387 * bridge type is set. We are using bridge type instead of "no-hpd"
388 * property because it is not used properly in devicetree description
389 * and hence is unreliable.
390 */
391
392 if (pdata->bridge.type != DRM_MODE_CONNECTOR_DisplayPort)
393 regmap_update_bits(map: pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
394 HPD_DISABLE);
395
396 pdata->comms_enabled = true;
397
398 mutex_unlock(lock: &pdata->comms_mutex);
399}
400
401static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata)
402{
403 mutex_lock(&pdata->comms_mutex);
404
405 pdata->comms_enabled = false;
406 clk_disable_unprepare(clk: pdata->refclk);
407
408 mutex_unlock(lock: &pdata->comms_mutex);
409}
410
411static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
412{
413 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
414 const struct i2c_client *client = to_i2c_client(pdata->dev);
415 int ret;
416
417 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, consumers: pdata->supplies);
418 if (ret) {
419 DRM_ERROR("failed to enable supplies %d\n", ret);
420 return ret;
421 }
422
423 /* td2: min 100 us after regulators before enabling the GPIO */
424 usleep_range(min: 100, max: 110);
425
426 gpiod_set_value_cansleep(desc: pdata->enable_gpio, value: 1);
427
428 /*
429 * After EN is deasserted and an external clock is detected, the bridge
430 * will sample GPIO3:1 to determine its frequency. The driver will
431 * overwrite this setting in ti_sn_bridge_set_refclk_freq(). But this is
432 * racy. Thus we have to wait a couple of us. According to the datasheet
433 * the GPIO lines has to be stable at least 5 us (td5) but it seems that
434 * is not enough and the refclk frequency value is still lost or
435 * overwritten by the bridge itself. Waiting for 20us seems to work.
436 */
437 usleep_range(min: 20, max: 30);
438
439 /*
440 * If we have a reference clock we can enable communication w/ the
441 * panel (including the aux channel) w/out any need for an input clock
442 * so we can do it in resume which lets us read the EDID before
443 * pre_enable(). Without a reference clock we need the MIPI reference
444 * clock so reading early doesn't work.
445 */
446 if (pdata->refclk)
447 ti_sn65dsi86_enable_comms(pdata, NULL);
448
449 if (client->irq) {
450 ret = regmap_update_bits(map: pdata->regmap, SN_IRQ_EN_REG, IRQ_EN,
451 IRQ_EN);
452 if (ret)
453 dev_err(pdata->dev, "Failed to enable IRQ events: %d\n", ret);
454 }
455
456 return ret;
457}
458
459static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev)
460{
461 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
462 int ret;
463
464 if (pdata->refclk)
465 ti_sn65dsi86_disable_comms(pdata);
466
467 gpiod_set_value_cansleep(desc: pdata->enable_gpio, value: 0);
468
469 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, consumers: pdata->supplies);
470 if (ret)
471 DRM_ERROR("failed to disable supplies %d\n", ret);
472
473 return ret;
474}
475
476static const struct dev_pm_ops ti_sn65dsi86_pm_ops = {
477 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL)
478 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
479 pm_runtime_force_resume)
480};
481
482static int status_show(struct seq_file *s, void *data)
483{
484 struct ti_sn65dsi86 *pdata = s->private;
485 unsigned int reg, val;
486
487 seq_puts(m: s, s: "STATUS REGISTERS:\n");
488
489 pm_runtime_get_sync(dev: pdata->dev);
490
491 /* IRQ Status Registers, see Table 31 in datasheet */
492 for (reg = 0xf0; reg <= 0xf8; reg++) {
493 regmap_read(map: pdata->regmap, reg, val: &val);
494 seq_printf(m: s, fmt: "[0x%02x] = 0x%08x\n", reg, val);
495 }
496
497 pm_runtime_put_autosuspend(dev: pdata->dev);
498
499 return 0;
500}
501DEFINE_SHOW_ATTRIBUTE(status);
502
503/* -----------------------------------------------------------------------------
504 * Auxiliary Devices (*not* AUX)
505 */
506
507static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata,
508 struct auxiliary_device **aux_out,
509 const char *name)
510{
511 struct device *dev = pdata->dev;
512 const struct i2c_client *client = to_i2c_client(dev);
513 struct auxiliary_device *aux;
514 int id;
515
516 id = (client->adapter->nr << 10) | client->addr;
517 aux = __devm_auxiliary_device_create(dev, KBUILD_MODNAME, devname: name,
518 NULL, id);
519 if (!aux)
520 return -ENODEV;
521
522 *aux_out = aux;
523 return 0;
524}
525
526/* -----------------------------------------------------------------------------
527 * AUX Adapter
528 */
529
530static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux)
531{
532 return container_of(aux, struct ti_sn65dsi86, aux);
533}
534
535static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
536 struct drm_dp_aux_msg *msg)
537{
538 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux);
539 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
540 u32 request_val = AUX_CMD_REQ(msg->request);
541 u8 *buf = msg->buffer;
542 unsigned int len = msg->size;
543 unsigned int short_len;
544 unsigned int val;
545 int ret;
546 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
547
548 if (len > SN_AUX_MAX_PAYLOAD_BYTES)
549 return -EINVAL;
550
551 pm_runtime_get_sync(dev: pdata->dev);
552 mutex_lock(&pdata->comms_mutex);
553
554 /*
555 * If someone tries to do a DDC over AUX transaction before pre_enable()
556 * on a device without a dedicated reference clock then we just can't
557 * do it. Fail right away. This prevents non-refclk users from reading
558 * the EDID before enabling the panel but such is life.
559 */
560 if (!pdata->comms_enabled) {
561 ret = -EIO;
562 goto exit;
563 }
564
565 switch (request) {
566 case DP_AUX_NATIVE_WRITE:
567 case DP_AUX_I2C_WRITE:
568 case DP_AUX_NATIVE_READ:
569 case DP_AUX_I2C_READ:
570 regmap_write(map: pdata->regmap, SN_AUX_CMD_REG, val: request_val);
571 /* Assume it's good */
572 msg->reply = 0;
573 break;
574 default:
575 ret = -EINVAL;
576 goto exit;
577 }
578
579 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32));
580 put_unaligned_be32(val: (msg->address & SN_AUX_ADDR_MASK) << 8 | len,
581 p: addr_len);
582 regmap_bulk_write(map: pdata->regmap, SN_AUX_ADDR_19_16_REG, val: addr_len,
583 ARRAY_SIZE(addr_len));
584
585 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
586 regmap_bulk_write(map: pdata->regmap, SN_AUX_WDATA_REG(0), val: buf, val_count: len);
587
588 /* Clear old status bits before start so we don't get confused */
589 regmap_write(map: pdata->regmap, SN_AUX_CMD_STATUS_REG,
590 AUX_IRQ_STATUS_NAT_I2C_FAIL |
591 AUX_IRQ_STATUS_AUX_RPLY_TOUT |
592 AUX_IRQ_STATUS_AUX_SHORT);
593
594 regmap_write(map: pdata->regmap, SN_AUX_CMD_REG, val: request_val | AUX_CMD_SEND);
595
596 /* Zero delay loop because i2c transactions are slow already */
597 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
598 !(val & AUX_CMD_SEND), 0, 50 * 1000);
599 if (ret)
600 goto exit;
601
602 ret = regmap_read(map: pdata->regmap, SN_AUX_CMD_STATUS_REG, val: &val);
603 if (ret)
604 goto exit;
605
606 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) {
607 /*
608 * The hardware tried the message seven times per the DP spec
609 * but it hit a timeout. We ignore defers here because they're
610 * handled in hardware.
611 */
612 ret = -ETIMEDOUT;
613 goto exit;
614 }
615
616 if (val & AUX_IRQ_STATUS_AUX_SHORT) {
617 ret = regmap_read(map: pdata->regmap, SN_AUX_LENGTH_REG, val: &short_len);
618 len = min(len, short_len);
619 if (ret)
620 goto exit;
621 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) {
622 switch (request) {
623 case DP_AUX_I2C_WRITE:
624 case DP_AUX_I2C_READ:
625 msg->reply |= DP_AUX_I2C_REPLY_NACK;
626 break;
627 case DP_AUX_NATIVE_READ:
628 case DP_AUX_NATIVE_WRITE:
629 msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
630 break;
631 }
632 len = 0;
633 goto exit;
634 }
635
636 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0)
637 ret = regmap_bulk_read(map: pdata->regmap, SN_AUX_RDATA_REG(0), val: buf, val_count: len);
638
639exit:
640 mutex_unlock(lock: &pdata->comms_mutex);
641 pm_runtime_mark_last_busy(dev: pdata->dev);
642 pm_runtime_put_autosuspend(dev: pdata->dev);
643
644 if (ret)
645 return ret;
646 return len;
647}
648
649static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
650{
651 /*
652 * The HPD in this chip is a bit useless (See comment in
653 * ti_sn65dsi86_enable_comms) so if our driver is expected to wait
654 * for HPD, we just assume it's asserted after the wait_us delay.
655 *
656 * In case we are asked to wait forever (wait_us=0) take conservative
657 * 500ms delay.
658 */
659 if (wait_us == 0)
660 wait_us = 500000;
661
662 usleep_range(min: wait_us, max: wait_us + 1000);
663
664 return 0;
665}
666
667static int ti_sn_aux_probe(struct auxiliary_device *adev,
668 const struct auxiliary_device_id *id)
669{
670 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev: adev->dev.parent);
671 int ret;
672
673 pdata->aux.name = "ti-sn65dsi86-aux";
674 pdata->aux.dev = &adev->dev;
675 pdata->aux.transfer = ti_sn_aux_transfer;
676 pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted;
677 drm_dp_aux_init(aux: &pdata->aux);
678
679 ret = devm_of_dp_aux_populate_ep_devices(aux: &pdata->aux);
680 if (ret)
681 return ret;
682
683 /*
684 * The eDP to MIPI bridge parts don't work until the AUX channel is
685 * setup so we don't add it in the main driver probe, we add it now.
686 */
687 return ti_sn65dsi86_add_aux_device(pdata, aux_out: &pdata->bridge_aux, name: "bridge");
688}
689
690static const struct auxiliary_device_id ti_sn_aux_id_table[] = {
691 { .name = "ti_sn65dsi86.aux", },
692 {},
693};
694
695static struct auxiliary_driver ti_sn_aux_driver = {
696 .name = "aux",
697 .probe = ti_sn_aux_probe,
698 .id_table = ti_sn_aux_id_table,
699};
700
701/*------------------------------------------------------------------------------
702 * DRM Bridge
703 */
704
705static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge)
706{
707 return container_of(bridge, struct ti_sn65dsi86, bridge);
708}
709
710static int ti_sn_attach_host(struct auxiliary_device *adev, struct ti_sn65dsi86 *pdata)
711{
712 int val;
713 struct mipi_dsi_host *host;
714 struct mipi_dsi_device *dsi;
715 struct device *dev = pdata->dev;
716 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
717 .channel = 0,
718 .node = NULL,
719 };
720
721 host = of_find_mipi_dsi_host_by_node(node: pdata->host_node);
722 if (!host)
723 return -EPROBE_DEFER;
724
725 dsi = devm_mipi_dsi_device_register_full(dev: &adev->dev, host, info: &info);
726 if (IS_ERR(ptr: dsi))
727 return PTR_ERR(ptr: dsi);
728
729 /* TODO: setting to 4 MIPI lanes always for now */
730 dsi->lanes = 4;
731 dsi->format = MIPI_DSI_FMT_RGB888;
732 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
733
734 /* check if continuous dsi clock is required or not */
735 pm_runtime_get_sync(dev);
736 regmap_read(map: pdata->regmap, SN_DPPLL_SRC_REG, val: &val);
737 pm_runtime_put_autosuspend(dev);
738 if (!(val & DPPLL_CLK_SRC_DSICLK))
739 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
740
741 pdata->dsi = dsi;
742
743 return devm_mipi_dsi_attach(dev: &adev->dev, dsi);
744}
745
746static int ti_sn_bridge_attach(struct drm_bridge *bridge,
747 struct drm_encoder *encoder,
748 enum drm_bridge_attach_flags flags)
749{
750 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
751 int ret;
752
753 pdata->aux.drm_dev = bridge->dev;
754 ret = drm_dp_aux_register(aux: &pdata->aux);
755 if (ret < 0) {
756 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret);
757 return ret;
758 }
759
760 /*
761 * Attach the next bridge.
762 * We never want the next bridge to *also* create a connector.
763 */
764 ret = drm_bridge_attach(encoder, bridge: pdata->next_bridge,
765 previous: &pdata->bridge, flags: flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
766 if (ret < 0)
767 goto err_initted_aux;
768
769 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
770 return 0;
771
772 pdata->connector = drm_bridge_connector_init(drm: pdata->bridge.dev,
773 encoder: pdata->bridge.encoder);
774 if (IS_ERR(ptr: pdata->connector)) {
775 ret = PTR_ERR(ptr: pdata->connector);
776 goto err_initted_aux;
777 }
778
779 drm_connector_attach_encoder(connector: pdata->connector, encoder: pdata->bridge.encoder);
780
781 return 0;
782
783err_initted_aux:
784 drm_dp_aux_unregister(aux: &pdata->aux);
785 return ret;
786}
787
788static void ti_sn_bridge_detach(struct drm_bridge *bridge)
789{
790 drm_dp_aux_unregister(aux: &bridge_to_ti_sn65dsi86(bridge)->aux);
791}
792
793static enum drm_mode_status
794ti_sn_bridge_mode_valid(struct drm_bridge *bridge,
795 const struct drm_display_info *info,
796 const struct drm_display_mode *mode)
797{
798 /* maximum supported resolution is 4K at 60 fps */
799 if (mode->clock > 594000)
800 return MODE_CLOCK_HIGH;
801
802 /*
803 * The front and back porch registers are 8 bits, and pulse width
804 * registers are 15 bits, so reject any modes with larger periods.
805 */
806
807 if ((mode->hsync_start - mode->hdisplay) > 0xff)
808 return MODE_HBLANK_WIDE;
809
810 if ((mode->vsync_start - mode->vdisplay) > 0xff)
811 return MODE_VBLANK_WIDE;
812
813 if ((mode->hsync_end - mode->hsync_start) > 0x7fff)
814 return MODE_HSYNC_WIDE;
815
816 if ((mode->vsync_end - mode->vsync_start) > 0x7fff)
817 return MODE_VSYNC_WIDE;
818
819 if ((mode->htotal - mode->hsync_end) > 0xff)
820 return MODE_HBLANK_WIDE;
821
822 if ((mode->vtotal - mode->vsync_end) > 0xff)
823 return MODE_VBLANK_WIDE;
824
825 return MODE_OK;
826}
827
828static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge,
829 struct drm_atomic_state *state)
830{
831 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
832
833 /* disable video stream */
834 regmap_update_bits(map: pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, val: 0);
835}
836
837static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata,
838 struct drm_atomic_state *state)
839{
840 unsigned int bit_rate_mhz, clk_freq_mhz;
841 unsigned int val;
842 struct drm_display_mode *mode =
843 get_new_adjusted_display_mode(bridge: &pdata->bridge, state);
844
845 /* set DSIA clk frequency */
846 bit_rate_mhz = (mode->clock / 1000) *
847 mipi_dsi_pixel_format_to_bpp(fmt: pdata->dsi->format);
848 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
849
850 /* for each increment in val, frequency increases by 5MHz */
851 val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
852 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
853 regmap_write(map: pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
854}
855
856static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector)
857{
858 if (connector->display_info.bpc <= 6)
859 return 18;
860 else
861 return 24;
862}
863
864/*
865 * LUT index corresponds to register value and
866 * LUT values corresponds to dp data rate supported
867 * by the bridge in Mbps unit.
868 */
869static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
870 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
871};
872
873static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata,
874 struct drm_atomic_state *state,
875 unsigned int bpp)
876{
877 unsigned int bit_rate_khz, dp_rate_mhz;
878 unsigned int i;
879 struct drm_display_mode *mode =
880 get_new_adjusted_display_mode(bridge: &pdata->bridge, state);
881
882 /* Calculate minimum bit rate based on our pixel clock. */
883 bit_rate_khz = mode->clock * bpp;
884
885 /* Calculate minimum DP data rate, taking 80% as per DP spec */
886 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
887 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
888
889 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
890 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
891 break;
892
893 return i;
894}
895
896static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata)
897{
898 unsigned int valid_rates = 0;
899 unsigned int rate_per_200khz;
900 unsigned int rate_mhz;
901 u8 dpcd_val;
902 int ret;
903 int i, j;
904
905 ret = drm_dp_dpcd_readb(aux: &pdata->aux, DP_EDP_DPCD_REV, valuep: &dpcd_val);
906 if (ret != 1) {
907 DRM_DEV_ERROR(pdata->dev,
908 "Can't read eDP rev (%d), assuming 1.1\n", ret);
909 dpcd_val = DP_EDP_11;
910 }
911
912 if (dpcd_val >= DP_EDP_14) {
913 /* eDP 1.4 devices must provide a custom table */
914 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
915
916 ret = drm_dp_dpcd_read(aux: &pdata->aux, DP_SUPPORTED_LINK_RATES,
917 buffer: sink_rates, size: sizeof(sink_rates));
918
919 if (ret != sizeof(sink_rates)) {
920 DRM_DEV_ERROR(pdata->dev,
921 "Can't read supported rate table (%d)\n", ret);
922
923 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
924 memset(sink_rates, 0, sizeof(sink_rates));
925 }
926
927 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
928 rate_per_200khz = le16_to_cpu(sink_rates[i]);
929
930 if (!rate_per_200khz)
931 break;
932
933 rate_mhz = rate_per_200khz * 200 / 1000;
934 for (j = 0;
935 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
936 j++) {
937 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
938 valid_rates |= BIT(j);
939 }
940 }
941
942 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
943 if (valid_rates & BIT(i))
944 return valid_rates;
945 }
946 DRM_DEV_ERROR(pdata->dev,
947 "No matching eDP rates in table; falling back\n");
948 }
949
950 /* On older versions best we can do is use DP_MAX_LINK_RATE */
951 ret = drm_dp_dpcd_readb(aux: &pdata->aux, DP_MAX_LINK_RATE, valuep: &dpcd_val);
952 if (ret != 1) {
953 DRM_DEV_ERROR(pdata->dev,
954 "Can't read max rate (%d); assuming 5.4 GHz\n",
955 ret);
956 dpcd_val = DP_LINK_BW_5_4;
957 }
958
959 switch (dpcd_val) {
960 default:
961 DRM_DEV_ERROR(pdata->dev,
962 "Unexpected max rate (%#x); assuming 5.4 GHz\n",
963 (int)dpcd_val);
964 fallthrough;
965 case DP_LINK_BW_5_4:
966 valid_rates |= BIT(7);
967 fallthrough;
968 case DP_LINK_BW_2_7:
969 valid_rates |= BIT(4);
970 fallthrough;
971 case DP_LINK_BW_1_62:
972 valid_rates |= BIT(1);
973 break;
974 }
975
976 return valid_rates;
977}
978
979static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata,
980 struct drm_atomic_state *state)
981{
982 struct drm_display_mode *mode =
983 get_new_adjusted_display_mode(bridge: &pdata->bridge, state);
984 u8 hsync_polarity = 0, vsync_polarity = 0;
985
986 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
987 hsync_polarity = CHA_HSYNC_POLARITY;
988 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
989 vsync_polarity = CHA_VSYNC_POLARITY;
990
991 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
992 val: mode->hdisplay);
993 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
994 val: mode->vdisplay);
995 regmap_write(map: pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
996 val: (mode->hsync_end - mode->hsync_start) & 0xFF);
997 regmap_write(map: pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
998 val: (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
999 hsync_polarity);
1000 regmap_write(map: pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
1001 val: (mode->vsync_end - mode->vsync_start) & 0xFF);
1002 regmap_write(map: pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
1003 val: (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
1004 vsync_polarity);
1005
1006 regmap_write(map: pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
1007 val: (mode->htotal - mode->hsync_end) & 0xFF);
1008 regmap_write(map: pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
1009 val: (mode->vtotal - mode->vsync_end) & 0xFF);
1010
1011 regmap_write(map: pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
1012 val: (mode->hsync_start - mode->hdisplay) & 0xFF);
1013 regmap_write(map: pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
1014 val: (mode->vsync_start - mode->vdisplay) & 0xFF);
1015
1016 usleep_range(min: 10000, max: 10500); /* 10ms delay recommended by spec */
1017}
1018
1019static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata)
1020{
1021 u8 data;
1022 int ret;
1023
1024 ret = drm_dp_dpcd_readb(aux: &pdata->aux, DP_MAX_LANE_COUNT, valuep: &data);
1025 if (ret != 1) {
1026 DRM_DEV_ERROR(pdata->dev,
1027 "Can't read lane count (%d); assuming 4\n", ret);
1028 return 4;
1029 }
1030
1031 return data & DP_LANE_COUNT_MASK;
1032}
1033
1034static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx,
1035 const char **last_err_str)
1036{
1037 unsigned int val;
1038 int ret;
1039 int i;
1040
1041 /* set dp clk frequency value */
1042 regmap_update_bits(map: pdata->regmap, SN_DATARATE_CONFIG_REG,
1043 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
1044
1045 /* enable DP PLL */
1046 regmap_write(map: pdata->regmap, SN_PLL_ENABLE_REG, val: 1);
1047
1048 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
1049 val & DPPLL_SRC_DP_PLL_LOCK, 1000,
1050 50 * 1000);
1051 if (ret) {
1052 *last_err_str = "DP_PLL_LOCK polling failed";
1053 goto exit;
1054 }
1055
1056 /*
1057 * We'll try to link train several times. As part of link training
1058 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If
1059 * the panel isn't ready quite it might respond NAK here which means
1060 * we need to try again.
1061 */
1062 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) {
1063 /* Semi auto link training mode */
1064 regmap_write(map: pdata->regmap, SN_ML_TX_MODE_REG, val: 0x0A);
1065 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
1066 val == ML_TX_MAIN_LINK_OFF ||
1067 val == ML_TX_NORMAL_MODE, 1000,
1068 500 * 1000);
1069 if (ret) {
1070 *last_err_str = "Training complete polling failed";
1071 } else if (val == ML_TX_MAIN_LINK_OFF) {
1072 *last_err_str = "Link training failed, link is off";
1073 ret = -EIO;
1074 continue;
1075 }
1076
1077 break;
1078 }
1079
1080 /* If we saw quite a few retries, add a note about it */
1081 if (!ret && i > SN_LINK_TRAINING_TRIES / 2)
1082 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i);
1083
1084exit:
1085 /* Disable the PLL if we failed */
1086 if (ret)
1087 regmap_write(map: pdata->regmap, SN_PLL_ENABLE_REG, val: 0);
1088
1089 return ret;
1090}
1091
1092static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge,
1093 struct drm_atomic_state *state)
1094{
1095 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1096 struct drm_connector *connector;
1097 const char *last_err_str = "No supported DP rate";
1098 unsigned int valid_rates;
1099 int dp_rate_idx;
1100 unsigned int val;
1101 int ret = -EINVAL;
1102 int max_dp_lanes;
1103 unsigned int bpp;
1104
1105 connector = drm_atomic_get_new_connector_for_encoder(state,
1106 encoder: bridge->encoder);
1107 if (!connector) {
1108 dev_err_ratelimited(pdata->dev, "Could not get the connector\n");
1109 return;
1110 }
1111
1112 max_dp_lanes = ti_sn_get_max_lanes(pdata);
1113 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
1114
1115 /* DSI_A lane config */
1116 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
1117 regmap_update_bits(map: pdata->regmap, SN_DSI_LANES_REG,
1118 CHA_DSI_LANES_MASK, val);
1119
1120 regmap_write(map: pdata->regmap, SN_LN_ASSIGN_REG, val: pdata->ln_assign);
1121 regmap_update_bits(map: pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
1122 val: pdata->ln_polrs << LN_POLRS_OFFSET);
1123
1124 /* set dsi clk frequency value */
1125 ti_sn_bridge_set_dsi_rate(pdata, state);
1126
1127 /*
1128 * The SN65DSI86 only supports ASSR Display Authentication method and
1129 * this method is enabled for eDP panels. An eDP panel must support this
1130 * authentication method. We need to enable this method in the eDP panel
1131 * at DisplayPort address 0x0010A prior to link training.
1132 *
1133 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays
1134 * we need to disable the scrambler.
1135 */
1136 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) {
1137 drm_dp_dpcd_writeb(aux: &pdata->aux, DP_EDP_CONFIGURATION_SET,
1138 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
1139
1140 regmap_update_bits(map: pdata->regmap, SN_TRAINING_SETTING_REG,
1141 SCRAMBLE_DISABLE, val: 0);
1142 } else {
1143 regmap_update_bits(map: pdata->regmap, SN_TRAINING_SETTING_REG,
1144 SCRAMBLE_DISABLE, SCRAMBLE_DISABLE);
1145 }
1146
1147 bpp = ti_sn_bridge_get_bpp(connector);
1148 /* Set the DP output format (18 bpp or 24 bpp) */
1149 val = bpp == 18 ? BPP_18_RGB : 0;
1150 regmap_update_bits(map: pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
1151
1152 /* DP lane config */
1153 val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
1154 regmap_update_bits(map: pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
1155 val);
1156
1157 valid_rates = ti_sn_bridge_read_valid_rates(pdata);
1158
1159 /* Train until we run out of rates */
1160 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, state, bpp);
1161 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
1162 dp_rate_idx++) {
1163 if (!(valid_rates & BIT(dp_rate_idx)))
1164 continue;
1165
1166 ret = ti_sn_link_training(pdata, dp_rate_idx, last_err_str: &last_err_str);
1167 if (!ret)
1168 break;
1169 }
1170 if (ret) {
1171 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
1172 return;
1173 }
1174
1175 /* config video parameters */
1176 ti_sn_bridge_set_video_timings(pdata, state);
1177
1178 /* enable video stream */
1179 regmap_update_bits(map: pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
1180 VSTREAM_ENABLE);
1181}
1182
1183static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1184 struct drm_atomic_state *state)
1185{
1186 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1187
1188 pm_runtime_get_sync(dev: pdata->dev);
1189
1190 if (!pdata->refclk)
1191 ti_sn65dsi86_enable_comms(pdata, state);
1192
1193 /* td7: min 100 us after enable before DSI data */
1194 usleep_range(min: 100, max: 110);
1195}
1196
1197static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge,
1198 struct drm_atomic_state *state)
1199{
1200 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1201
1202 /* semi auto link training mode OFF */
1203 regmap_write(map: pdata->regmap, SN_ML_TX_MODE_REG, val: 0);
1204 /* Num lanes to 0 as per power sequencing in data sheet */
1205 regmap_update_bits(map: pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, val: 0);
1206 /* disable DP PLL */
1207 regmap_write(map: pdata->regmap, SN_PLL_ENABLE_REG, val: 0);
1208
1209 if (!pdata->refclk)
1210 ti_sn65dsi86_disable_comms(pdata);
1211
1212 pm_runtime_put_sync(dev: pdata->dev);
1213}
1214
1215static enum drm_connector_status
1216ti_sn_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector)
1217{
1218 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1219 int val = 0;
1220
1221 /*
1222 * Runtime reference is grabbed in ti_sn_bridge_hpd_enable()
1223 * as the chip won't report HPD just after being powered on.
1224 * HPD_DEBOUNCED_STATE reflects correct state only after the
1225 * debounce time (~100-400 ms).
1226 */
1227
1228 regmap_read(map: pdata->regmap, SN_HPD_DISABLE_REG, val: &val);
1229
1230 return val & HPD_DEBOUNCED_STATE ? connector_status_connected
1231 : connector_status_disconnected;
1232}
1233
1234static const struct drm_edid *ti_sn_bridge_edid_read(struct drm_bridge *bridge,
1235 struct drm_connector *connector)
1236{
1237 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1238
1239 return drm_edid_read_ddc(connector, adapter: &pdata->aux.ddc);
1240}
1241
1242static void ti_sn65dsi86_debugfs_init(struct drm_bridge *bridge, struct dentry *root)
1243{
1244 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1245 struct dentry *debugfs;
1246
1247 debugfs = debugfs_create_dir(name: dev_name(dev: pdata->dev), parent: root);
1248 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops);
1249}
1250
1251static void ti_sn_bridge_hpd_enable(struct drm_bridge *bridge)
1252{
1253 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1254 const struct i2c_client *client = to_i2c_client(pdata->dev);
1255 int ret;
1256
1257 /*
1258 * Device needs to be powered on before reading the HPD state
1259 * for reliable hpd detection in ti_sn_bridge_detect() due to
1260 * the high debounce time.
1261 */
1262
1263 pm_runtime_get_sync(dev: pdata->dev);
1264
1265 mutex_lock(&pdata->hpd_mutex);
1266 pdata->hpd_enabled = true;
1267 mutex_unlock(lock: &pdata->hpd_mutex);
1268
1269 if (client->irq) {
1270 ret = regmap_set_bits(map: pdata->regmap, SN_IRQ_EVENTS_EN_REG,
1271 HPD_REMOVAL_EN | HPD_INSERTION_EN);
1272 if (ret)
1273 dev_err(pdata->dev, "Failed to enable HPD events: %d\n", ret);
1274 }
1275}
1276
1277static void ti_sn_bridge_hpd_disable(struct drm_bridge *bridge)
1278{
1279 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1280 const struct i2c_client *client = to_i2c_client(pdata->dev);
1281 int ret;
1282
1283 if (client->irq) {
1284 ret = regmap_clear_bits(map: pdata->regmap, SN_IRQ_EVENTS_EN_REG,
1285 HPD_REMOVAL_EN | HPD_INSERTION_EN);
1286 if (ret)
1287 dev_err(pdata->dev, "Failed to disable HPD events: %d\n", ret);
1288 }
1289
1290 mutex_lock(&pdata->hpd_mutex);
1291 pdata->hpd_enabled = false;
1292 mutex_unlock(lock: &pdata->hpd_mutex);
1293
1294 pm_runtime_put_autosuspend(dev: pdata->dev);
1295}
1296
1297static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
1298 .attach = ti_sn_bridge_attach,
1299 .detach = ti_sn_bridge_detach,
1300 .mode_valid = ti_sn_bridge_mode_valid,
1301 .edid_read = ti_sn_bridge_edid_read,
1302 .detect = ti_sn_bridge_detect,
1303 .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable,
1304 .atomic_enable = ti_sn_bridge_atomic_enable,
1305 .atomic_disable = ti_sn_bridge_atomic_disable,
1306 .atomic_post_disable = ti_sn_bridge_atomic_post_disable,
1307 .atomic_reset = drm_atomic_helper_bridge_reset,
1308 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1309 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1310 .debugfs_init = ti_sn65dsi86_debugfs_init,
1311 .hpd_enable = ti_sn_bridge_hpd_enable,
1312 .hpd_disable = ti_sn_bridge_hpd_disable,
1313};
1314
1315static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
1316 struct device_node *np)
1317{
1318 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1319 u32 lane_polarities[SN_MAX_DP_LANES] = { };
1320 struct device_node *endpoint;
1321 u8 ln_assign = 0;
1322 u8 ln_polrs = 0;
1323 int dp_lanes;
1324 int i;
1325
1326 /*
1327 * Read config from the device tree about lane remapping and lane
1328 * polarities. These are optional and we assume identity map and
1329 * normal polarity if nothing is specified. It's OK to specify just
1330 * data-lanes but not lane-polarities but not vice versa.
1331 *
1332 * Error checking is light (we just make sure we don't crash or
1333 * buffer overrun) and we assume dts is well formed and specifying
1334 * mappings that the hardware supports.
1335 */
1336 endpoint = of_graph_get_endpoint_by_regs(parent: np, port_reg: 1, reg: -1);
1337 dp_lanes = drm_of_get_data_lanes_count(endpoint, min: 1, SN_MAX_DP_LANES);
1338 if (dp_lanes > 0) {
1339 of_property_read_u32_array(np: endpoint, propname: "data-lanes",
1340 out_values: lane_assignments, sz: dp_lanes);
1341 of_property_read_u32_array(np: endpoint, propname: "lane-polarities",
1342 out_values: lane_polarities, sz: dp_lanes);
1343 } else {
1344 dp_lanes = SN_MAX_DP_LANES;
1345 }
1346 of_node_put(node: endpoint);
1347
1348 /*
1349 * Convert into register format. Loop over all lanes even if
1350 * data-lanes had fewer elements so that we nicely initialize
1351 * the LN_ASSIGN register.
1352 */
1353 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1354 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1355 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1356 }
1357
1358 /* Stash in our struct for when we power on */
1359 pdata->dp_lanes = dp_lanes;
1360 pdata->ln_assign = ln_assign;
1361 pdata->ln_polrs = ln_polrs;
1362}
1363
1364static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata)
1365{
1366 struct device_node *np = pdata->dev->of_node;
1367
1368 pdata->host_node = of_graph_get_remote_node(node: np, port: 0, endpoint: 0);
1369
1370 if (!pdata->host_node) {
1371 DRM_ERROR("remote dsi host node not found\n");
1372 return -ENODEV;
1373 }
1374
1375 return 0;
1376}
1377
1378static irqreturn_t ti_sn_bridge_interrupt(int irq, void *private)
1379{
1380 struct ti_sn65dsi86 *pdata = private;
1381 struct drm_device *dev = pdata->bridge.dev;
1382 u8 status;
1383 int ret;
1384 bool hpd_event;
1385
1386 ret = ti_sn65dsi86_read_u8(pdata, SN_IRQ_STATUS_REG, val: &status);
1387 if (ret) {
1388 dev_err(pdata->dev, "Failed to read IRQ status: %d\n", ret);
1389 return IRQ_NONE;
1390 }
1391
1392 hpd_event = status & (HPD_REMOVAL_STATUS | HPD_INSERTION_STATUS);
1393
1394 dev_dbg(pdata->dev, "(SN_IRQ_STATUS_REG = %#x)\n", status);
1395 if (!status)
1396 return IRQ_NONE;
1397
1398 ret = regmap_write(map: pdata->regmap, SN_IRQ_STATUS_REG, val: status);
1399 if (ret) {
1400 dev_err(pdata->dev, "Failed to clear IRQ status: %d\n", ret);
1401 return IRQ_NONE;
1402 }
1403
1404 /* Only send the HPD event if we are bound with a device. */
1405 mutex_lock(&pdata->hpd_mutex);
1406 if (pdata->hpd_enabled && hpd_event)
1407 drm_kms_helper_hotplug_event(dev);
1408 mutex_unlock(lock: &pdata->hpd_mutex);
1409
1410 return IRQ_HANDLED;
1411}
1412
1413static int ti_sn_bridge_probe(struct auxiliary_device *adev,
1414 const struct auxiliary_device_id *id)
1415{
1416 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev: adev->dev.parent);
1417 struct device_node *np = pdata->dev->of_node;
1418 int ret;
1419
1420 pdata->next_bridge = devm_drm_of_get_bridge(dev: &adev->dev, node: np, port: 1, endpoint: 0);
1421 if (IS_ERR(ptr: pdata->next_bridge))
1422 return dev_err_probe(dev: &adev->dev, err: PTR_ERR(ptr: pdata->next_bridge),
1423 fmt: "failed to create panel bridge\n");
1424
1425 ti_sn_bridge_parse_lanes(pdata, np);
1426
1427 ret = ti_sn_bridge_parse_dsi_host(pdata);
1428 if (ret)
1429 return ret;
1430
1431 pdata->bridge.of_node = np;
1432 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort
1433 ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP;
1434
1435 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) {
1436 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT |
1437 DRM_BRIDGE_OP_HPD;
1438 /*
1439 * If comms were already enabled they would have been enabled
1440 * with the wrong value of HPD_DISABLE. Update it now. Comms
1441 * could be enabled if anyone is holding a pm_runtime reference
1442 * (like if a GPIO is in use). Note that in most cases nobody
1443 * is doing AUX channel xfers before the bridge is added so
1444 * HPD doesn't _really_ matter then. The only exception is in
1445 * the eDP case where the panel wants to read the EDID before
1446 * the bridge is added. We always consistently have HPD disabled
1447 * for eDP.
1448 */
1449 mutex_lock(&pdata->comms_mutex);
1450 if (pdata->comms_enabled)
1451 regmap_update_bits(map: pdata->regmap, SN_HPD_DISABLE_REG,
1452 HPD_DISABLE, val: 0);
1453 mutex_unlock(lock: &pdata->comms_mutex);
1454 }
1455
1456 drm_bridge_add(bridge: &pdata->bridge);
1457
1458 ret = ti_sn_attach_host(adev, pdata);
1459 if (ret) {
1460 dev_err_probe(dev: &adev->dev, err: ret, fmt: "failed to attach dsi host\n");
1461 goto err_remove_bridge;
1462 }
1463
1464 return 0;
1465
1466err_remove_bridge:
1467 drm_bridge_remove(bridge: &pdata->bridge);
1468 return ret;
1469}
1470
1471static void ti_sn_bridge_remove(struct auxiliary_device *adev)
1472{
1473 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev: adev->dev.parent);
1474
1475 if (!pdata)
1476 return;
1477
1478 drm_bridge_remove(bridge: &pdata->bridge);
1479
1480 of_node_put(node: pdata->host_node);
1481}
1482
1483static const struct auxiliary_device_id ti_sn_bridge_id_table[] = {
1484 { .name = "ti_sn65dsi86.bridge", },
1485 {},
1486};
1487
1488static struct auxiliary_driver ti_sn_bridge_driver = {
1489 .name = "bridge",
1490 .probe = ti_sn_bridge_probe,
1491 .remove = ti_sn_bridge_remove,
1492 .id_table = ti_sn_bridge_id_table,
1493};
1494
1495/* -----------------------------------------------------------------------------
1496 * PWM Controller
1497 */
1498#if IS_REACHABLE(CONFIG_PWM)
1499static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata)
1500{
1501 return atomic_xchg(v: &pdata->pwm_pin_busy, new: 1) ? -EBUSY : 0;
1502}
1503
1504static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata)
1505{
1506 atomic_set(v: &pdata->pwm_pin_busy, i: 0);
1507}
1508
1509static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip)
1510{
1511 return pwmchip_get_drvdata(chip);
1512}
1513
1514static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
1515{
1516 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1517
1518 return ti_sn_pwm_pin_request(pdata);
1519}
1520
1521static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
1522{
1523 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1524
1525 ti_sn_pwm_pin_release(pdata);
1526}
1527
1528/*
1529 * Limitations:
1530 * - The PWM signal is not driven when the chip is powered down, or in its
1531 * reset state and the driver does not implement the "suspend state"
1532 * described in the documentation. In order to save power, state->enabled is
1533 * interpreted as denoting if the signal is expected to be valid, and is used
1534 * to determine if the chip needs to be kept powered.
1535 * - Changing both period and duty_cycle is not done atomically, neither is the
1536 * multi-byte register updates, so the output might briefly be undefined
1537 * during update.
1538 */
1539static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
1540 const struct pwm_state *state)
1541{
1542 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1543 unsigned int pwm_en_inv;
1544 unsigned int backlight;
1545 unsigned int pre_div;
1546 unsigned int scale;
1547 u64 period_max;
1548 u64 period;
1549 int ret;
1550
1551 if (!pdata->pwm_enabled) {
1552 ret = pm_runtime_resume_and_get(dev: pwmchip_parent(chip));
1553 if (ret < 0)
1554 return ret;
1555 }
1556
1557 if (state->enabled) {
1558 if (!pdata->pwm_enabled) {
1559 /*
1560 * The chip might have been powered down while we
1561 * didn't hold a PM runtime reference, so mux in the
1562 * PWM function on the GPIO pin again.
1563 */
1564 ret = regmap_update_bits(map: pdata->regmap, SN_GPIO_CTRL_REG,
1565 SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX),
1566 SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX));
1567 if (ret) {
1568 dev_err(pwmchip_parent(chip), "failed to mux in PWM function\n");
1569 goto out;
1570 }
1571 }
1572
1573 /*
1574 * Per the datasheet the PWM frequency is given by:
1575 *
1576 * REFCLK_FREQ
1577 * PWM_FREQ = -----------------------------------
1578 * PWM_PRE_DIV * BACKLIGHT_SCALE + 1
1579 *
1580 * However, after careful review the author is convinced that
1581 * the documentation has lost some parenthesis around
1582 * "BACKLIGHT_SCALE + 1".
1583 *
1584 * With the period T_pwm = 1/PWM_FREQ this can be written:
1585 *
1586 * T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1)
1587 *
1588 * In order to keep BACKLIGHT_SCALE within its 16 bits,
1589 * PWM_PRE_DIV must be:
1590 *
1591 * T_pwm * REFCLK_FREQ
1592 * PWM_PRE_DIV >= -------------------------
1593 * BACKLIGHT_SCALE_MAX + 1
1594 *
1595 * To simplify the search and to favour higher resolution of
1596 * the duty cycle over accuracy of the period, the lowest
1597 * possible PWM_PRE_DIV is used. Finally the scale is
1598 * calculated as:
1599 *
1600 * T_pwm * REFCLK_FREQ
1601 * BACKLIGHT_SCALE = ---------------------- - 1
1602 * PWM_PRE_DIV
1603 *
1604 * Here T_pwm is represented in seconds, so appropriate scaling
1605 * to nanoseconds is necessary.
1606 */
1607
1608 /* Minimum T_pwm is 1 / REFCLK_FREQ */
1609 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) {
1610 ret = -EINVAL;
1611 goto out;
1612 }
1613
1614 /*
1615 * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ
1616 * Limit period to this to avoid overflows
1617 */
1618 period_max = div_u64(dividend: (u64)NSEC_PER_SEC * 255 * (65535 + 1),
1619 divisor: pdata->pwm_refclk_freq);
1620 period = min(state->period, period_max);
1621
1622 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq,
1623 (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1));
1624 scale = div64_u64(dividend: period * pdata->pwm_refclk_freq, divisor: (u64)NSEC_PER_SEC * pre_div) - 1;
1625
1626 /*
1627 * The documentation has the duty ratio given as:
1628 *
1629 * duty BACKLIGHT
1630 * ------- = ---------------------
1631 * period BACKLIGHT_SCALE + 1
1632 *
1633 * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according
1634 * to definition above and adjusting for nanosecond
1635 * representation of duty cycle gives us:
1636 */
1637 backlight = div64_u64(dividend: state->duty_cycle * pdata->pwm_refclk_freq,
1638 divisor: (u64)NSEC_PER_SEC * pre_div);
1639 if (backlight > scale)
1640 backlight = scale;
1641
1642 ret = regmap_write(map: pdata->regmap, SN_PWM_PRE_DIV_REG, val: pre_div);
1643 if (ret) {
1644 dev_err(pwmchip_parent(chip), "failed to update PWM_PRE_DIV\n");
1645 goto out;
1646 }
1647
1648 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, val: scale);
1649 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, val: backlight);
1650 }
1651
1652 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) |
1653 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED);
1654 ret = regmap_write(map: pdata->regmap, SN_PWM_EN_INV_REG, val: pwm_en_inv);
1655 if (ret) {
1656 dev_err(pwmchip_parent(chip), "failed to update PWM_EN/PWM_INV\n");
1657 goto out;
1658 }
1659
1660 pdata->pwm_enabled = state->enabled;
1661out:
1662
1663 if (!pdata->pwm_enabled)
1664 pm_runtime_put_sync(dev: pwmchip_parent(chip));
1665
1666 return ret;
1667}
1668
1669static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
1670 struct pwm_state *state)
1671{
1672 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1673 unsigned int pwm_en_inv;
1674 unsigned int pre_div;
1675 u16 backlight;
1676 u16 scale;
1677 int ret;
1678
1679 ret = regmap_read(map: pdata->regmap, SN_PWM_EN_INV_REG, val: &pwm_en_inv);
1680 if (ret)
1681 return ret;
1682
1683 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, val: &scale);
1684 if (ret)
1685 return ret;
1686
1687 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, val: &backlight);
1688 if (ret)
1689 return ret;
1690
1691 ret = regmap_read(map: pdata->regmap, SN_PWM_PRE_DIV_REG, val: &pre_div);
1692 if (ret)
1693 return ret;
1694
1695 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv);
1696 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv))
1697 state->polarity = PWM_POLARITY_INVERSED;
1698 else
1699 state->polarity = PWM_POLARITY_NORMAL;
1700
1701 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1),
1702 pdata->pwm_refclk_freq);
1703 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight,
1704 pdata->pwm_refclk_freq);
1705
1706 if (state->duty_cycle > state->period)
1707 state->duty_cycle = state->period;
1708
1709 return 0;
1710}
1711
1712static const struct pwm_ops ti_sn_pwm_ops = {
1713 .request = ti_sn_pwm_request,
1714 .free = ti_sn_pwm_free,
1715 .apply = ti_sn_pwm_apply,
1716 .get_state = ti_sn_pwm_get_state,
1717};
1718
1719static int ti_sn_pwm_probe(struct auxiliary_device *adev,
1720 const struct auxiliary_device_id *id)
1721{
1722 struct pwm_chip *chip;
1723 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev: adev->dev.parent);
1724
1725 pdata->pchip = chip = devm_pwmchip_alloc(parent: &adev->dev, npwm: 1, sizeof_priv: 0);
1726 if (IS_ERR(ptr: chip))
1727 return PTR_ERR(ptr: chip);
1728
1729 pwmchip_set_drvdata(chip, data: pdata);
1730
1731 chip->ops = &ti_sn_pwm_ops;
1732 chip->of_xlate = of_pwm_single_xlate;
1733
1734 devm_pm_runtime_enable(dev: &adev->dev);
1735
1736 return pwmchip_add(chip);
1737}
1738
1739static void ti_sn_pwm_remove(struct auxiliary_device *adev)
1740{
1741 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev: adev->dev.parent);
1742
1743 pwmchip_remove(chip: pdata->pchip);
1744
1745 if (pdata->pwm_enabled)
1746 pm_runtime_put_sync(dev: &adev->dev);
1747}
1748
1749static const struct auxiliary_device_id ti_sn_pwm_id_table[] = {
1750 { .name = "ti_sn65dsi86.pwm", },
1751 {},
1752};
1753
1754static struct auxiliary_driver ti_sn_pwm_driver = {
1755 .name = "pwm",
1756 .probe = ti_sn_pwm_probe,
1757 .remove = ti_sn_pwm_remove,
1758 .id_table = ti_sn_pwm_id_table,
1759};
1760
1761static int __init ti_sn_pwm_register(void)
1762{
1763 return auxiliary_driver_register(&ti_sn_pwm_driver);
1764}
1765
1766static void ti_sn_pwm_unregister(void)
1767{
1768 auxiliary_driver_unregister(auxdrv: &ti_sn_pwm_driver);
1769}
1770
1771#else
1772static inline int __maybe_unused ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; }
1773static inline void __maybe_unused ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {}
1774
1775static inline int ti_sn_pwm_register(void) { return 0; }
1776static inline void ti_sn_pwm_unregister(void) {}
1777#endif
1778
1779/* -----------------------------------------------------------------------------
1780 * GPIO Controller
1781 */
1782#if defined(CONFIG_OF_GPIO)
1783
1784static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
1785 const struct of_phandle_args *gpiospec,
1786 u32 *flags)
1787{
1788 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
1789 return -EINVAL;
1790
1791 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
1792 return -EINVAL;
1793
1794 if (flags)
1795 *flags = gpiospec->args[1];
1796
1797 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
1798}
1799
1800static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
1801 unsigned int offset)
1802{
1803 struct ti_sn65dsi86 *pdata = gpiochip_get_data(gc: chip);
1804
1805 /*
1806 * We already have to keep track of the direction because we use
1807 * that to figure out whether we've powered the device. We can
1808 * just return that rather than (maybe) powering up the device
1809 * to ask its direction.
1810 */
1811 return test_bit(offset, pdata->gchip_output) ?
1812 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1813}
1814
1815static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
1816{
1817 struct ti_sn65dsi86 *pdata = gpiochip_get_data(gc: chip);
1818 unsigned int val;
1819 int ret;
1820
1821 /*
1822 * When the pin is an input we don't forcibly keep the bridge
1823 * powered--we just power it on to read the pin. NOTE: part of
1824 * the reason this works is that the bridge defaults (when
1825 * powered back on) to all 4 GPIOs being configured as GPIO input.
1826 * Also note that if something else is keeping the chip powered the
1827 * pm_runtime functions are lightweight increments of a refcount.
1828 */
1829 pm_runtime_get_sync(dev: pdata->dev);
1830 ret = regmap_read(map: pdata->regmap, SN_GPIO_IO_REG, val: &val);
1831 pm_runtime_put_autosuspend(dev: pdata->dev);
1832
1833 if (ret)
1834 return ret;
1835
1836 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
1837}
1838
1839static int ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
1840 int val)
1841{
1842 struct ti_sn65dsi86 *pdata = gpiochip_get_data(gc: chip);
1843
1844 val &= 1;
1845 return regmap_update_bits(map: pdata->regmap, SN_GPIO_IO_REG,
1846 BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1847 val: val << (SN_GPIO_OUTPUT_SHIFT + offset));
1848}
1849
1850static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1851 unsigned int offset)
1852{
1853 struct ti_sn65dsi86 *pdata = gpiochip_get_data(gc: chip);
1854 int shift = offset * 2;
1855 int ret;
1856
1857 if (!test_and_clear_bit(nr: offset, addr: pdata->gchip_output))
1858 return 0;
1859
1860 ret = regmap_update_bits(map: pdata->regmap, SN_GPIO_CTRL_REG,
1861 SN_GPIO_MUX_MASK << shift,
1862 SN_GPIO_MUX_INPUT << shift);
1863 if (ret) {
1864 set_bit(nr: offset, addr: pdata->gchip_output);
1865 return ret;
1866 }
1867
1868 /*
1869 * NOTE: if nobody else is powering the device this may fully power
1870 * it off and when it comes back it will have lost all state, but
1871 * that's OK because the default is input and we're now an input.
1872 */
1873 pm_runtime_put_autosuspend(dev: pdata->dev);
1874
1875 return 0;
1876}
1877
1878static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1879 unsigned int offset, int val)
1880{
1881 struct ti_sn65dsi86 *pdata = gpiochip_get_data(gc: chip);
1882 int shift = offset * 2;
1883 int ret;
1884
1885 if (test_and_set_bit(nr: offset, addr: pdata->gchip_output))
1886 return 0;
1887
1888 pm_runtime_get_sync(dev: pdata->dev);
1889
1890 /* Set value first to avoid glitching */
1891 ti_sn_bridge_gpio_set(chip, offset, val);
1892
1893 /* Set direction */
1894 ret = regmap_update_bits(map: pdata->regmap, SN_GPIO_CTRL_REG,
1895 SN_GPIO_MUX_MASK << shift,
1896 SN_GPIO_MUX_OUTPUT << shift);
1897 if (ret) {
1898 clear_bit(nr: offset, addr: pdata->gchip_output);
1899 pm_runtime_put_autosuspend(dev: pdata->dev);
1900 }
1901
1902 return ret;
1903}
1904
1905static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset)
1906{
1907 struct ti_sn65dsi86 *pdata = gpiochip_get_data(gc: chip);
1908
1909 if (offset == SN_PWM_GPIO_IDX)
1910 return ti_sn_pwm_pin_request(pdata);
1911
1912 return 0;
1913}
1914
1915static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1916{
1917 struct ti_sn65dsi86 *pdata = gpiochip_get_data(gc: chip);
1918
1919 /* We won't keep pm_runtime if we're input, so switch there on free */
1920 ti_sn_bridge_gpio_direction_input(chip, offset);
1921
1922 if (offset == SN_PWM_GPIO_IDX)
1923 ti_sn_pwm_pin_release(pdata);
1924}
1925
1926static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1927 "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1928};
1929
1930static int ti_sn_gpio_probe(struct auxiliary_device *adev,
1931 const struct auxiliary_device_id *id)
1932{
1933 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev: adev->dev.parent);
1934 int ret;
1935
1936 /* Only init if someone is going to use us as a GPIO controller */
1937 if (!of_property_read_bool(np: pdata->dev->of_node, propname: "gpio-controller"))
1938 return 0;
1939
1940 pdata->gchip.label = dev_name(dev: pdata->dev);
1941 pdata->gchip.parent = pdata->dev;
1942 pdata->gchip.owner = THIS_MODULE;
1943 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1944 pdata->gchip.of_gpio_n_cells = 2;
1945 pdata->gchip.request = ti_sn_bridge_gpio_request;
1946 pdata->gchip.free = ti_sn_bridge_gpio_free;
1947 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1948 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1949 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1950 pdata->gchip.get = ti_sn_bridge_gpio_get;
1951 pdata->gchip.set = ti_sn_bridge_gpio_set;
1952 pdata->gchip.can_sleep = true;
1953 pdata->gchip.names = ti_sn_bridge_gpio_names;
1954 pdata->gchip.ngpio = SN_NUM_GPIOS;
1955 pdata->gchip.base = -1;
1956 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata);
1957 if (ret)
1958 dev_err(pdata->dev, "can't add gpio chip\n");
1959
1960 return ret;
1961}
1962
1963static const struct auxiliary_device_id ti_sn_gpio_id_table[] = {
1964 { .name = "ti_sn65dsi86.gpio", },
1965 {},
1966};
1967
1968MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table);
1969
1970static struct auxiliary_driver ti_sn_gpio_driver = {
1971 .name = "gpio",
1972 .probe = ti_sn_gpio_probe,
1973 .id_table = ti_sn_gpio_id_table,
1974};
1975
1976static int __init ti_sn_gpio_register(void)
1977{
1978 return auxiliary_driver_register(&ti_sn_gpio_driver);
1979}
1980
1981static void ti_sn_gpio_unregister(void)
1982{
1983 auxiliary_driver_unregister(auxdrv: &ti_sn_gpio_driver);
1984}
1985
1986#else
1987
1988static inline int ti_sn_gpio_register(void) { return 0; }
1989static inline void ti_sn_gpio_unregister(void) {}
1990
1991#endif
1992
1993/* -----------------------------------------------------------------------------
1994 * Probe & Remove
1995 */
1996
1997static void ti_sn65dsi86_runtime_disable(void *data)
1998{
1999 pm_runtime_dont_use_autosuspend(dev: data);
2000 pm_runtime_disable(dev: data);
2001}
2002
2003static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata)
2004{
2005 unsigned int i;
2006 const char * const ti_sn_bridge_supply_names[] = {
2007 "vcca", "vcc", "vccio", "vpll",
2008 };
2009
2010 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
2011 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
2012
2013 return devm_regulator_bulk_get(dev: pdata->dev, SN_REGULATOR_SUPPLY_NUM,
2014 consumers: pdata->supplies);
2015}
2016
2017static int ti_sn65dsi86_probe(struct i2c_client *client)
2018{
2019 struct device *dev = &client->dev;
2020 struct ti_sn65dsi86 *pdata;
2021 u8 id_buf[8];
2022 int ret;
2023
2024 if (!i2c_check_functionality(adap: client->adapter, I2C_FUNC_I2C)) {
2025 DRM_ERROR("device doesn't support I2C\n");
2026 return -ENODEV;
2027 }
2028
2029 pdata = devm_drm_bridge_alloc(dev, struct ti_sn65dsi86, bridge, &ti_sn_bridge_funcs);
2030 if (IS_ERR(ptr: pdata))
2031 return PTR_ERR(ptr: pdata);
2032 dev_set_drvdata(dev, data: pdata);
2033 pdata->dev = dev;
2034
2035 mutex_init(&pdata->hpd_mutex);
2036 mutex_init(&pdata->comms_mutex);
2037
2038 pdata->regmap = devm_regmap_init_i2c(client,
2039 &ti_sn65dsi86_regmap_config);
2040 if (IS_ERR(ptr: pdata->regmap))
2041 return dev_err_probe(dev, err: PTR_ERR(ptr: pdata->regmap),
2042 fmt: "regmap i2c init failed\n");
2043
2044 pdata->enable_gpio = devm_gpiod_get_optional(dev, con_id: "enable",
2045 flags: GPIOD_OUT_LOW);
2046 if (IS_ERR(ptr: pdata->enable_gpio))
2047 return dev_err_probe(dev, err: PTR_ERR(ptr: pdata->enable_gpio),
2048 fmt: "failed to get enable gpio from DT\n");
2049
2050 ret = ti_sn65dsi86_parse_regulators(pdata);
2051 if (ret)
2052 return dev_err_probe(dev, err: ret, fmt: "failed to parse regulators\n");
2053
2054 pdata->refclk = devm_clk_get_optional(dev, id: "refclk");
2055 if (IS_ERR(ptr: pdata->refclk))
2056 return dev_err_probe(dev, err: PTR_ERR(ptr: pdata->refclk),
2057 fmt: "failed to get reference clock\n");
2058
2059 pm_runtime_enable(dev);
2060 pm_runtime_set_autosuspend_delay(dev: pdata->dev, delay: 500);
2061 pm_runtime_use_autosuspend(dev: pdata->dev);
2062 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev);
2063 if (ret)
2064 return ret;
2065
2066 pm_runtime_get_sync(dev);
2067 ret = regmap_bulk_read(map: pdata->regmap, SN_DEVICE_ID_REGS, val: id_buf, ARRAY_SIZE(id_buf));
2068 pm_runtime_put_autosuspend(dev);
2069 if (ret)
2070 return dev_err_probe(dev, err: ret, fmt: "failed to read device id\n");
2071
2072 /* The ID string is stored backwards */
2073 if (strncmp(id_buf, "68ISD ", ARRAY_SIZE(id_buf)))
2074 return dev_err_probe(dev, err: -EOPNOTSUPP, fmt: "unsupported device id\n");
2075
2076 if (client->irq) {
2077 ret = devm_request_threaded_irq(dev: pdata->dev, irq: client->irq, NULL,
2078 thread_fn: ti_sn_bridge_interrupt,
2079 IRQF_ONESHOT,
2080 devname: dev_name(dev: pdata->dev), dev_id: pdata);
2081
2082 if (ret)
2083 return dev_err_probe(dev, err: ret, fmt: "failed to request interrupt\n");
2084 }
2085
2086 /*
2087 * Break ourselves up into a collection of aux devices. The only real
2088 * motiviation here is to solve the chicken-and-egg problem of probe
2089 * ordering. The bridge wants the panel to be there when it probes.
2090 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards)
2091 * when it probes. The panel and maybe backlight might want the DDC
2092 * bus or the pwm_chip. Having sub-devices allows the some sub devices
2093 * to finish probing even if others return -EPROBE_DEFER and gets us
2094 * around the problems.
2095 */
2096
2097 if (IS_ENABLED(CONFIG_OF_GPIO)) {
2098 ret = ti_sn65dsi86_add_aux_device(pdata, aux_out: &pdata->gpio_aux, name: "gpio");
2099 if (ret)
2100 return ret;
2101 }
2102
2103 if (IS_REACHABLE(CONFIG_PWM)) {
2104 ret = ti_sn65dsi86_add_aux_device(pdata, aux_out: &pdata->pwm_aux, name: "pwm");
2105 if (ret)
2106 return ret;
2107 }
2108
2109 /*
2110 * NOTE: At the end of the AUX channel probe we'll add the aux device
2111 * for the bridge. This is because the bridge can't be used until the
2112 * AUX channel is there and this is a very simple solution to the
2113 * dependency problem.
2114 */
2115 return ti_sn65dsi86_add_aux_device(pdata, aux_out: &pdata->aux_aux, name: "aux");
2116}
2117
2118static const struct i2c_device_id ti_sn65dsi86_id[] = {
2119 { "ti,sn65dsi86" },
2120 {}
2121};
2122MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id);
2123
2124static const struct of_device_id ti_sn65dsi86_match_table[] = {
2125 {.compatible = "ti,sn65dsi86"},
2126 {},
2127};
2128MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table);
2129
2130static struct i2c_driver ti_sn65dsi86_driver = {
2131 .driver = {
2132 .name = "ti_sn65dsi86",
2133 .of_match_table = ti_sn65dsi86_match_table,
2134 .pm = &ti_sn65dsi86_pm_ops,
2135 },
2136 .probe = ti_sn65dsi86_probe,
2137 .id_table = ti_sn65dsi86_id,
2138};
2139
2140static int __init ti_sn65dsi86_init(void)
2141{
2142 int ret;
2143
2144 ret = i2c_add_driver(&ti_sn65dsi86_driver);
2145 if (ret)
2146 return ret;
2147
2148 ret = ti_sn_gpio_register();
2149 if (ret)
2150 goto err_main_was_registered;
2151
2152 ret = ti_sn_pwm_register();
2153 if (ret)
2154 goto err_gpio_was_registered;
2155
2156 ret = auxiliary_driver_register(&ti_sn_aux_driver);
2157 if (ret)
2158 goto err_pwm_was_registered;
2159
2160 ret = auxiliary_driver_register(&ti_sn_bridge_driver);
2161 if (ret)
2162 goto err_aux_was_registered;
2163
2164 return 0;
2165
2166err_aux_was_registered:
2167 auxiliary_driver_unregister(auxdrv: &ti_sn_aux_driver);
2168err_pwm_was_registered:
2169 ti_sn_pwm_unregister();
2170err_gpio_was_registered:
2171 ti_sn_gpio_unregister();
2172err_main_was_registered:
2173 i2c_del_driver(driver: &ti_sn65dsi86_driver);
2174
2175 return ret;
2176}
2177module_init(ti_sn65dsi86_init);
2178
2179static void __exit ti_sn65dsi86_exit(void)
2180{
2181 auxiliary_driver_unregister(auxdrv: &ti_sn_bridge_driver);
2182 auxiliary_driver_unregister(auxdrv: &ti_sn_aux_driver);
2183 ti_sn_pwm_unregister();
2184 ti_sn_gpio_unregister();
2185 i2c_del_driver(driver: &ti_sn65dsi86_driver);
2186}
2187module_exit(ti_sn65dsi86_exit);
2188
2189MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
2190MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
2191MODULE_LICENSE("GPL v2");
2192

source code of linux/drivers/gpu/drm/bridge/ti-sn65dsi86.c