1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (c) 2016 Linaro Limited. |
4 | * Copyright (c) 2014-2016 HiSilicon Limited. |
5 | */ |
6 | |
7 | #ifndef __KIRIN_DRM_DRV_H__ |
8 | #define __KIRIN_DRM_DRV_H__ |
9 | |
10 | #define to_kirin_crtc(crtc) \ |
11 | container_of(crtc, struct kirin_crtc, base) |
12 | |
13 | #define to_kirin_plane(plane) \ |
14 | container_of(plane, struct kirin_plane, base) |
15 | |
16 | /* kirin-format translate table */ |
17 | struct kirin_format { |
18 | u32 pixel_format; |
19 | u32 hw_format; |
20 | }; |
21 | |
22 | struct kirin_crtc { |
23 | struct drm_crtc base; |
24 | void *hw_ctx; |
25 | bool enable; |
26 | }; |
27 | |
28 | struct kirin_plane { |
29 | struct drm_plane base; |
30 | void *hw_ctx; |
31 | u32 ch; |
32 | }; |
33 | |
34 | /* display controller init/cleanup ops */ |
35 | struct kirin_drm_data { |
36 | const u32 *channel_formats; |
37 | u32 channel_formats_cnt; |
38 | int config_max_width; |
39 | int config_max_height; |
40 | u32 num_planes; |
41 | u32 prim_plane; |
42 | |
43 | const struct drm_driver *driver; |
44 | const struct drm_crtc_helper_funcs *crtc_helper_funcs; |
45 | const struct drm_crtc_funcs *crtc_funcs; |
46 | const struct drm_plane_helper_funcs *plane_helper_funcs; |
47 | const struct drm_plane_funcs *plane_funcs; |
48 | const struct drm_mode_config_funcs *mode_config_funcs; |
49 | |
50 | void *(*alloc_hw_ctx)(struct platform_device *pdev, |
51 | struct drm_crtc *crtc); |
52 | void (*cleanup_hw_ctx)(void *hw_ctx); |
53 | }; |
54 | |
55 | extern struct kirin_drm_data ade_driver_data; |
56 | |
57 | #endif /* __KIRIN_DRM_DRV_H__ */ |
58 | |