| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2022 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_AUDIO_REGS_H__ |
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| 7 | #define __INTEL_AUDIO_REGS_H__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | |
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| 11 | #define G4X_AUD_CNTL_ST _MMIO(0x620B4) |
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| 12 | #define G4X_ELD_VALID REG_BIT(14) |
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| 13 | #define G4X_ELD_BUFFER_SIZE_MASK REG_GENMASK(13, 9) |
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| 14 | #define G4X_ELD_ADDRESS_MASK REG_GENMASK(8, 5) |
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| 15 | #define G4X_ELD_ACK REG_BIT(4) |
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| 16 | #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) |
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| 17 | |
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| 18 | #define _IBX_HDMIW_HDMIEDID_A 0xE2050 |
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| 19 | #define _IBX_HDMIW_HDMIEDID_B 0xE2150 |
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| 20 | #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ |
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| 21 | _IBX_HDMIW_HDMIEDID_B) |
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| 22 | #define _IBX_AUD_CNTL_ST_A 0xE20B4 |
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| 23 | #define _IBX_AUD_CNTL_ST_B 0xE21B4 |
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| 24 | #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ |
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| 25 | _IBX_AUD_CNTL_ST_B) |
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| 26 | #define IBX_ELD_BUFFER_SIZE_MASK REG_GENMASK(14, 10) |
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| 27 | #define IBX_ELD_ADDRESS_MASK REG_GENMASK(9, 5) |
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| 28 | #define IBX_ELD_ACK REG_BIT(4) |
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| 29 | #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) |
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| 30 | #define IBX_CP_READY(port) REG_BIT(((port) - 1) * 4 + 1) |
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| 31 | #define IBX_ELD_VALID(port) REG_BIT(((port) - 1) * 4 + 0) |
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| 32 | |
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| 33 | #define _CPT_HDMIW_HDMIEDID_A 0xE5050 |
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| 34 | #define _CPT_HDMIW_HDMIEDID_B 0xE5150 |
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| 35 | #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) |
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| 36 | #define _CPT_AUD_CNTL_ST_A 0xE50B4 |
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| 37 | #define _CPT_AUD_CNTL_ST_B 0xE51B4 |
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| 38 | #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) |
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| 39 | #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) |
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| 40 | |
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| 41 | #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) |
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| 42 | #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) |
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| 43 | #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) |
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| 44 | #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) |
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| 45 | #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) |
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| 46 | #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) |
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| 47 | #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) |
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| 48 | |
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| 49 | #define _IBX_AUD_CONFIG_A 0xe2000 |
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| 50 | #define _IBX_AUD_CONFIG_B 0xe2100 |
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| 51 | #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) |
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| 52 | #define _CPT_AUD_CONFIG_A 0xe5000 |
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| 53 | #define _CPT_AUD_CONFIG_B 0xe5100 |
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| 54 | #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) |
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| 55 | #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) |
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| 56 | #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) |
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| 57 | #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) |
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| 58 | #define AUD_CONFIG_N_VALUE_INDEX REG_BIT(29) |
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| 59 | #define AUD_CONFIG_N_PROG_ENABLE REG_BIT(28) |
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| 60 | #define AUD_CONFIG_UPPER_N_MASK REG_GENMASK(27, 20) |
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| 61 | #define AUD_CONFIG_LOWER_N_MASK REG_GENMASK(15, 4) |
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| 62 | #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | \ |
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| 63 | AUD_CONFIG_LOWER_N_MASK) |
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| 64 | #define AUD_CONFIG_N(n) (REG_FIELD_PREP(AUD_CONFIG_UPPER_N_MASK, (n) >> 12) | \ |
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| 65 | REG_FIELD_PREP(AUD_CONFIG_LOWER_N_MASK, (n) & 0xfff)) |
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| 66 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK REG_GENMASK(19, 16) |
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| 67 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 0) |
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| 68 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 1) |
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| 69 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 2) |
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| 70 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 3) |
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| 71 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 4) |
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| 72 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 5) |
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| 73 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 6) |
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| 74 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 7) |
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| 75 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 8) |
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| 76 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 9) |
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| 77 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 10) |
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| 78 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 11) |
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| 79 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 12) |
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| 80 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 13) |
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| 81 | #define AUD_CONFIG_DISABLE_NCTS REG_BIT(3) |
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| 82 | |
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| 83 | #define _HSW_AUD_CONFIG_A 0x65000 |
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| 84 | #define _HSW_AUD_CONFIG_B 0x65100 |
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| 85 | #define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) |
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| 86 | |
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| 87 | #define _HSW_AUD_MISC_CTRL_A 0x65010 |
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| 88 | #define _HSW_AUD_MISC_CTRL_B 0x65110 |
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| 89 | #define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) |
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| 90 | |
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| 91 | #define _HSW_AUD_M_CTS_ENABLE_A 0x65028 |
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| 92 | #define _HSW_AUD_M_CTS_ENABLE_B 0x65128 |
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| 93 | #define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) |
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| 94 | #define AUD_M_CTS_M_VALUE_INDEX REG_BIT(21) |
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| 95 | #define AUD_M_CTS_M_PROG_ENABLE REG_BIT(20) |
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| 96 | #define AUD_CONFIG_M_MASK REG_GENMASK(19, 0) |
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| 97 | |
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| 98 | #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 |
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| 99 | #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 |
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| 100 | #define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) |
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| 101 | |
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| 102 | /* Audio Digital Converter */ |
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| 103 | #define _HSW_AUD_DIG_CNVT_1 0x65080 |
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| 104 | #define _HSW_AUD_DIG_CNVT_2 0x65180 |
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| 105 | #define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) |
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| 106 | #define DIP_PORT_SEL_MASK 0x3 |
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| 107 | |
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| 108 | #define _HSW_AUD_EDID_DATA_A 0x65050 |
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| 109 | #define _HSW_AUD_EDID_DATA_B 0x65150 |
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| 110 | #define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) |
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| 111 | |
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| 112 | #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) |
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| 113 | #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) |
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| 114 | #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) |
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| 115 | #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) |
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| 116 | #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) |
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| 117 | #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) |
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| 118 | |
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| 119 | #define _AUD_TCA_DP_2DOT0_CTRL 0x650bc |
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| 120 | #define _AUD_TCB_DP_2DOT0_CTRL 0x651bc |
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| 121 | #define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL) |
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| 122 | #define AUD_ENABLE_SDP_SPLIT REG_BIT(31) |
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| 123 | |
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| 124 | #define HSW_AUD_CHICKENBIT _MMIO(0x65f10) |
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| 125 | #define SKL_AUD_CODEC_WAKE_SIGNAL REG_BIT(15) |
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| 126 | |
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| 127 | #define AUD_FREQ_CNTRL _MMIO(0x65900) |
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| 128 | #define AUD_PIN_BUF_CTL _MMIO(0x48414) |
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| 129 | #define AUD_PIN_BUF_ENABLE REG_BIT(31) |
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| 130 | |
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| 131 | #define AUD_TS_CDCLK_M _MMIO(0x65ea0) |
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| 132 | #define AUD_TS_CDCLK_M_EN REG_BIT(31) |
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| 133 | #define AUD_TS_CDCLK_N _MMIO(0x65ea4) |
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| 134 | |
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| 135 | /* Display Audio Config Reg */ |
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| 136 | #define AUD_CONFIG_BE _MMIO(0x65ef0) |
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| 137 | #define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe))) |
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| 138 | #define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe))) |
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| 139 | #define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6))) |
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| 140 | #define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6)) |
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| 141 | #define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6)) |
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| 142 | #define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6)) |
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| 143 | |
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| 144 | #define HBLANK_START_COUNT_8 0 |
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| 145 | #define HBLANK_START_COUNT_16 1 |
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| 146 | #define HBLANK_START_COUNT_32 2 |
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| 147 | #define HBLANK_START_COUNT_64 3 |
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| 148 | #define HBLANK_START_COUNT_96 4 |
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| 149 | #define HBLANK_START_COUNT_128 5 |
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| 150 | |
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| 151 | /* LPE Audio */ |
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| 152 | #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) |
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| 153 | #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 |
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| 154 | |
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| 155 | #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) |
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| 156 | #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) |
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| 157 | |
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| 158 | #define _VLV_AUD_PORT_EN_B_DBG 0x62F20 |
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| 159 | #define _VLV_AUD_PORT_EN_C_DBG 0x62F30 |
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| 160 | #define _VLV_AUD_PORT_EN_D_DBG 0x62F34 |
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| 161 | #define VLV_AUD_PORT_EN_DBG(port) _MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (port) - PORT_B, \ |
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| 162 | _VLV_AUD_PORT_EN_B_DBG, \ |
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| 163 | _VLV_AUD_PORT_EN_C_DBG, \ |
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| 164 | _VLV_AUD_PORT_EN_D_DBG) |
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| 165 | #define VLV_AMP_MUTE (1 << 1) |
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| 166 | |
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| 167 | #define AUD_CHICKENBIT_REG3 _MMIO(0x65F1C) |
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| 168 | #define DACBE_DISABLE_MIN_HBLANK_FIX REG_BIT(18) |
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| 169 | |
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| 170 | #endif /* __INTEL_AUDIO_REGS_H__ */ |
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| 171 | |
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