| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2025 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_CMTG_REGS_H__ |
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| 7 | #define __INTEL_CMTG_REGS_H__ |
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| 8 | |
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| 9 | #include "i915_reg_defs.h" |
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| 10 | |
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| 11 | #define CMTG_CLK_SEL _MMIO(0x46160) |
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| 12 | #define CMTG_CLK_SEL_A_MASK REG_GENMASK(31, 29) |
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| 13 | #define CMTG_CLK_SEL_A_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0) |
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| 14 | #define CMTG_CLK_SEL_B_MASK REG_GENMASK(15, 13) |
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| 15 | #define CMTG_CLK_SEL_B_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0) |
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| 16 | |
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| 17 | #define TRANS_CMTG_CTL_A _MMIO(0x6fa88) |
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| 18 | #define TRANS_CMTG_CTL_B _MMIO(0x6fb88) |
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| 19 | #define CMTG_ENABLE REG_BIT(31) |
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| 20 | |
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| 21 | #endif /* __INTEL_CMTG_REGS_H__ */ |
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| 22 | |
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