| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2023 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_DP_AUX_REGS_H__ |
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| 7 | #define __INTEL_DP_AUX_REGS_H__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | |
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| 11 | /* |
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| 12 | * The aux channel provides a way to talk to the signal sink for DDC etc. Max |
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| 13 | * packet size supported is 20 bytes in each direction, hence the 5 fixed data |
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| 14 | * registers |
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| 15 | */ |
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| 16 | |
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| 17 | /* |
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| 18 | * Wrapper macro to convert from aux_ch to the index used in some of the |
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| 19 | * registers. |
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| 20 | */ |
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| 21 | #define __xe2lpd_aux_ch_idx(aux_ch) \ |
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| 22 | (aux_ch >= AUX_CH_USBC1 ? aux_ch : AUX_CH_USBC4 + 1 + (aux_ch) - AUX_CH_A) |
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| 23 | |
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| 24 | #define _DPA_AUX_CH_CTL 0x64010 |
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| 25 | #define _DPB_AUX_CH_CTL 0x64110 |
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| 26 | #define _XELPDP_USBC1_AUX_CH_CTL 0x16f210 |
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| 27 | #define _XELPDP_USBC2_AUX_CH_CTL 0x16f410 |
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| 28 | #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, \ |
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| 29 | _DPB_AUX_CH_CTL) |
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| 30 | #define VLV_DP_AUX_CH_CTL(aux_ch) _MMIO(VLV_DISPLAY_BASE + \ |
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| 31 | _PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)) |
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| 32 | #define _XELPDP_DP_AUX_CH_CTL(aux_ch) \ |
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| 33 | _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \ |
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| 34 | _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL, \ |
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| 35 | _XELPDP_USBC1_AUX_CH_CTL, \ |
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| 36 | _XELPDP_USBC2_AUX_CH_CTL)) |
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| 37 | #define XELPDP_DP_AUX_CH_CTL(i915__, aux_ch) \ |
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| 38 | (DISPLAY_VER(i915__) >= 20 ? \ |
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| 39 | _XELPDP_DP_AUX_CH_CTL(__xe2lpd_aux_ch_idx(aux_ch)) : \ |
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| 40 | _XELPDP_DP_AUX_CH_CTL(aux_ch)) |
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| 41 | #define DP_AUX_CH_CTL_SEND_BUSY REG_BIT(31) |
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| 42 | #define DP_AUX_CH_CTL_DONE REG_BIT(30) |
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| 43 | #define DP_AUX_CH_CTL_INTERRUPT REG_BIT(29) |
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| 44 | #define DP_AUX_CH_CTL_TIME_OUT_ERROR REG_BIT(28) |
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| 45 | #define DP_AUX_CH_CTL_TIME_OUT_MASK REG_GENMASK(27, 26) |
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| 46 | #define DP_AUX_CH_CTL_TIME_OUT_400us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 0) |
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| 47 | #define DP_AUX_CH_CTL_TIME_OUT_600us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 1) |
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| 48 | #define DP_AUX_CH_CTL_TIME_OUT_800us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 2) |
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| 49 | #define DP_AUX_CH_CTL_TIME_OUT_MAX REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 3) /* Varies per platform */ |
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| 50 | #define DP_AUX_CH_CTL_RECEIVE_ERROR REG_BIT(25) |
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| 51 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK REG_GENMASK(24, 20) |
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| 52 | #define DP_AUX_CH_CTL_MESSAGE_SIZE(x) REG_FIELD_PREP(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, (x)) |
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| 53 | #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK REG_GENMASK(19, 16) /* pre-skl */ |
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| 54 | #define DP_AUX_CH_CTL_PRECHARGE_2US(x) REG_FIELD_PREP(DP_AUX_CH_CTL_PRECHARGE_2US_MASK, (x)) |
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| 55 | #define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19) /* mtl+ */ |
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| 56 | #define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18) /* mtl+ */ |
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| 57 | #define DP_AUX_CH_CTL_AUX_AKSV_SELECT REG_BIT(15) |
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| 58 | #define DP_AUX_CH_CTL_MANCHESTER_TEST REG_BIT(14) /* pre-hsw */ |
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| 59 | #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL REG_BIT(14) /* skl+ */ |
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| 60 | #define DP_AUX_CH_CTL_SYNC_TEST REG_BIT(13) /* pre-hsw */ |
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| 61 | #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL REG_BIT(13) /* skl+ */ |
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| 62 | #define DP_AUX_CH_CTL_DEGLITCH_TEST REG_BIT(12) /* pre-hsw */ |
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| 63 | #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL REG_BIT(12) /* skl+ */ |
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| 64 | #define DP_AUX_CH_CTL_PRECHARGE_TEST REG_BIT(11) /* pre-hsw */ |
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| 65 | #define DP_AUX_CH_CTL_TBT_IO REG_BIT(11) /* icl+ */ |
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| 66 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK REG_GENMASK(10, 0) /* pre-skl */ |
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| 67 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X(x) REG_FIELD_PREP(DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK, (x)) |
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| 68 | #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK REG_GENMASK(9, 5) /* skl+ */ |
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| 69 | #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK, (c) - 1) |
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| 70 | #define DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK REG_GENMASK(4, 0) /* skl+ */ |
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| 71 | #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1) |
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| 72 | |
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| 73 | #define _DPA_AUX_CH_DATA1 0x64014 |
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| 74 | #define _DPB_AUX_CH_DATA1 0x64114 |
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| 75 | #define _XELPDP_USBC1_AUX_CH_DATA1 0x16f214 |
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| 76 | #define _XELPDP_USBC2_AUX_CH_DATA1 0x16f414 |
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| 77 | #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, \ |
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| 78 | _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ |
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| 79 | #define VLV_DP_AUX_CH_DATA(aux_ch, i) _MMIO(VLV_DISPLAY_BASE + _PORT(aux_ch, _DPA_AUX_CH_DATA1, \ |
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| 80 | _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ |
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| 81 | #define _XELPDP_DP_AUX_CH_DATA(aux_ch, i) \ |
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| 82 | _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \ |
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| 83 | _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1, \ |
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| 84 | _XELPDP_USBC1_AUX_CH_DATA1, \ |
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| 85 | _XELPDP_USBC2_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ |
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| 86 | #define XELPDP_DP_AUX_CH_DATA(i915__, aux_ch, i) \ |
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| 87 | (DISPLAY_VER(i915__) >= 20 ? \ |
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| 88 | _XELPDP_DP_AUX_CH_DATA(__xe2lpd_aux_ch_idx(aux_ch), i) : \ |
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| 89 | _XELPDP_DP_AUX_CH_DATA(aux_ch, i)) |
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| 90 | |
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| 91 | /* PICA Power Well Control */ |
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| 92 | #define XE2LPD_PICA_PW_CTL _MMIO(0x16fe04) |
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| 93 | #define XE2LPD_PICA_CTL_POWER_REQUEST REG_BIT(31) |
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| 94 | #define XE2LPD_PICA_CTL_POWER_STATUS REG_BIT(30) |
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| 95 | |
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| 96 | #endif /* __INTEL_DP_AUX_REGS_H__ */ |
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| 97 | |
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