1/*
2 * Copyright © 2012-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DPLL_MGR_H_
26#define _INTEL_DPLL_MGR_H_
27
28#include <linux/types.h>
29
30#include "intel_display_power.h"
31#include "intel_wakeref.h"
32
33#define for_each_shared_dpll(__i915, __pll, __i) \
34 for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \
35 ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++)
36
37enum tc_port;
38struct drm_i915_private;
39struct intel_atomic_state;
40struct intel_crtc;
41struct intel_crtc_state;
42struct intel_encoder;
43struct intel_shared_dpll;
44struct intel_shared_dpll_funcs;
45
46/**
47 * enum intel_dpll_id - possible DPLL ids
48 *
49 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
50 */
51enum intel_dpll_id {
52 /**
53 * @DPLL_ID_PRIVATE: non-shared dpll in use
54 */
55 DPLL_ID_PRIVATE = -1,
56
57 /**
58 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
59 */
60 DPLL_ID_PCH_PLL_A = 0,
61 /**
62 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
63 */
64 DPLL_ID_PCH_PLL_B = 1,
65
66
67 /**
68 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1
69 */
70 DPLL_ID_WRPLL1 = 0,
71 /**
72 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2
73 */
74 DPLL_ID_WRPLL2 = 1,
75 /**
76 * @DPLL_ID_SPLL: HSW and BDW SPLL
77 */
78 DPLL_ID_SPLL = 2,
79 /**
80 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL
81 */
82 DPLL_ID_LCPLL_810 = 3,
83 /**
84 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL
85 */
86 DPLL_ID_LCPLL_1350 = 4,
87 /**
88 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL
89 */
90 DPLL_ID_LCPLL_2700 = 5,
91
92
93 /**
94 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0
95 */
96 DPLL_ID_SKL_DPLL0 = 0,
97 /**
98 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1
99 */
100 DPLL_ID_SKL_DPLL1 = 1,
101 /**
102 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2
103 */
104 DPLL_ID_SKL_DPLL2 = 2,
105 /**
106 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3
107 */
108 DPLL_ID_SKL_DPLL3 = 3,
109
110
111 /**
112 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
113 */
114 DPLL_ID_ICL_DPLL0 = 0,
115 /**
116 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
117 */
118 DPLL_ID_ICL_DPLL1 = 1,
119 /**
120 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
121 */
122 DPLL_ID_EHL_DPLL4 = 2,
123 /**
124 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
125 */
126 DPLL_ID_ICL_TBTPLL = 2,
127 /**
128 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
129 * TGL TC PLL 1 port 1 (TC1)
130 */
131 DPLL_ID_ICL_MGPLL1 = 3,
132 /**
133 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
134 * TGL TC PLL 1 port 2 (TC2)
135 */
136 DPLL_ID_ICL_MGPLL2 = 4,
137 /**
138 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
139 * TGL TC PLL 1 port 3 (TC3)
140 */
141 DPLL_ID_ICL_MGPLL3 = 5,
142 /**
143 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
144 * TGL TC PLL 1 port 4 (TC4)
145 */
146 DPLL_ID_ICL_MGPLL4 = 6,
147 /**
148 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
149 */
150 DPLL_ID_TGL_MGPLL5 = 7,
151 /**
152 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
153 */
154 DPLL_ID_TGL_MGPLL6 = 8,
155
156 /**
157 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
158 */
159 DPLL_ID_DG1_DPLL0 = 0,
160 /**
161 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
162 */
163 DPLL_ID_DG1_DPLL1 = 1,
164 /**
165 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
166 */
167 DPLL_ID_DG1_DPLL2 = 2,
168 /**
169 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
170 */
171 DPLL_ID_DG1_DPLL3 = 3,
172};
173
174#define I915_NUM_PLLS 9
175
176enum icl_port_dpll_id {
177 ICL_PORT_DPLL_DEFAULT,
178 ICL_PORT_DPLL_MG_PHY,
179
180 ICL_PORT_DPLL_COUNT,
181};
182
183struct intel_dpll_hw_state {
184 /* i9xx, pch plls */
185 u32 dpll;
186 u32 dpll_md;
187 u32 fp0;
188 u32 fp1;
189
190 /* hsw, bdw */
191 u32 wrpll;
192 u32 spll;
193
194 /* skl */
195 /*
196 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
197 * lower part of ctrl1 and they get shifted into position when writing
198 * the register. This allows us to easily compare the state to share
199 * the DPLL.
200 */
201 u32 ctrl1;
202 /* HDMI only, 0 when used for DP */
203 u32 cfgcr1, cfgcr2;
204
205 /* icl */
206 u32 cfgcr0;
207
208 /* tgl */
209 u32 div0;
210
211 /* bxt */
212 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
213
214 /*
215 * ICL uses the following, already defined:
216 * u32 cfgcr0, cfgcr1;
217 */
218 u32 mg_refclkin_ctl;
219 u32 mg_clktop2_coreclkctl1;
220 u32 mg_clktop2_hsclkctl;
221 u32 mg_pll_div0;
222 u32 mg_pll_div1;
223 u32 mg_pll_lf;
224 u32 mg_pll_frac_lock;
225 u32 mg_pll_ssc;
226 u32 mg_pll_bias;
227 u32 mg_pll_tdc_coldst_bias;
228 u32 mg_pll_bias_mask;
229 u32 mg_pll_tdc_coldst_bias_mask;
230};
231
232/**
233 * struct intel_shared_dpll_state - hold the DPLL atomic state
234 *
235 * This structure holds an atomic state for the DPLL, that can represent
236 * either its current state (in struct &intel_shared_dpll) or a desired
237 * future state which would be applied by an atomic mode set (stored in
238 * a struct &intel_atomic_state).
239 *
240 * See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
241 */
242struct intel_shared_dpll_state {
243 /**
244 * @pipe_mask: mask of pipes using this DPLL, active or not
245 */
246 u8 pipe_mask;
247
248 /**
249 * @hw_state: hardware configuration for the DPLL stored in
250 * struct &intel_dpll_hw_state.
251 */
252 struct intel_dpll_hw_state hw_state;
253};
254
255/**
256 * struct dpll_info - display PLL platform specific info
257 */
258struct dpll_info {
259 /**
260 * @name: DPLL name; used for logging
261 */
262 const char *name;
263
264 /**
265 * @funcs: platform specific hooks
266 */
267 const struct intel_shared_dpll_funcs *funcs;
268
269 /**
270 * @id: unique indentifier for this DPLL
271 */
272 enum intel_dpll_id id;
273
274 /**
275 * @power_domain: extra power domain required by the DPLL
276 */
277 enum intel_display_power_domain power_domain;
278
279 /**
280 * @always_on:
281 *
282 * Inform the state checker that the DPLL is kept enabled even if
283 * not in use by any CRTC.
284 */
285 bool always_on;
286
287 /**
288 * @is_alt_port_dpll:
289 *
290 * Inform the state checker that the DPLL can be used as a fallback
291 * (for TC->TBT fallback).
292 */
293 bool is_alt_port_dpll;
294};
295
296/**
297 * struct intel_shared_dpll - display PLL with tracked state and users
298 */
299struct intel_shared_dpll {
300 /**
301 * @state:
302 *
303 * Store the state for the pll, including its hw state
304 * and CRTCs using it.
305 */
306 struct intel_shared_dpll_state state;
307
308 /**
309 * @index: index for atomic state
310 */
311 u8 index;
312
313 /**
314 * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL
315 */
316 u8 active_mask;
317
318 /**
319 * @on: is the PLL actually active? Disabled during modeset
320 */
321 bool on;
322
323 /**
324 * @info: platform specific info
325 */
326 const struct dpll_info *info;
327
328 /**
329 * @wakeref: In some platforms a device-level runtime pm reference may
330 * need to be grabbed to disable DC states while this DPLL is enabled
331 */
332 intel_wakeref_t wakeref;
333};
334
335#define SKL_DPLL0 0
336#define SKL_DPLL1 1
337#define SKL_DPLL2 2
338#define SKL_DPLL3 3
339
340/* shared dpll functions */
341struct intel_shared_dpll *
342intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
343 enum intel_dpll_id id);
344void assert_shared_dpll(struct drm_i915_private *i915,
345 struct intel_shared_dpll *pll,
346 bool state);
347#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
348#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
349int intel_compute_shared_dplls(struct intel_atomic_state *state,
350 struct intel_crtc *crtc,
351 struct intel_encoder *encoder);
352int intel_reserve_shared_dplls(struct intel_atomic_state *state,
353 struct intel_crtc *crtc,
354 struct intel_encoder *encoder);
355void intel_release_shared_dplls(struct intel_atomic_state *state,
356 struct intel_crtc *crtc);
357void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
358 const struct intel_shared_dpll *pll,
359 struct intel_shared_dpll_state *shared_dpll_state);
360void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
361 enum icl_port_dpll_id port_dpll_id);
362void intel_update_active_dpll(struct intel_atomic_state *state,
363 struct intel_crtc *crtc,
364 struct intel_encoder *encoder);
365int intel_dpll_get_freq(struct drm_i915_private *i915,
366 const struct intel_shared_dpll *pll,
367 const struct intel_dpll_hw_state *pll_state);
368bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
369 struct intel_shared_dpll *pll,
370 struct intel_dpll_hw_state *hw_state);
371void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
372void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
373void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
374void intel_shared_dpll_init(struct drm_i915_private *i915);
375void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
376void intel_dpll_readout_hw_state(struct drm_i915_private *i915);
377void intel_dpll_sanitize_state(struct drm_i915_private *i915);
378
379void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
380 const struct intel_dpll_hw_state *hw_state);
381bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
382 const struct intel_dpll_hw_state *a,
383 const struct intel_dpll_hw_state *b);
384enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
385bool intel_dpll_is_combophy(enum intel_dpll_id id);
386
387void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
388 struct intel_crtc *crtc);
389void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state);
390
391#endif /* _INTEL_DPLL_MGR_H_ */
392

source code of linux/drivers/gpu/drm/i915/display/intel_dpll_mgr.h