1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> |
3 | * Copyright (c) 2007-2008 Intel Corporation |
4 | * Jesse Barnes <jesse.barnes@intel.com> |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice (including the next |
14 | * paragraph) shall be included in all copies or substantial portions of the |
15 | * Software. |
16 | * |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
23 | * IN THE SOFTWARE. |
24 | */ |
25 | |
26 | #ifndef __INTEL_DISPLAY_TYPES_H__ |
27 | #define __INTEL_DISPLAY_TYPES_H__ |
28 | |
29 | #include <linux/i2c.h> |
30 | #include <linux/pm_qos.h> |
31 | #include <linux/pwm.h> |
32 | #include <linux/sched/clock.h> |
33 | |
34 | #include <drm/display/drm_dp_dual_mode_helper.h> |
35 | #include <drm/display/drm_dp_mst_helper.h> |
36 | #include <drm/display/drm_dp_tunnel.h> |
37 | #include <drm/display/drm_dsc.h> |
38 | #include <drm/drm_atomic.h> |
39 | #include <drm/drm_crtc.h> |
40 | #include <drm/drm_encoder.h> |
41 | #include <drm/drm_fourcc.h> |
42 | #include <drm/drm_framebuffer.h> |
43 | #include <drm/drm_probe_helper.h> |
44 | #include <drm/drm_rect.h> |
45 | #include <drm/drm_vblank.h> |
46 | #include <drm/drm_vblank_work.h> |
47 | #include <drm/i915_hdcp_interface.h> |
48 | #include <media/cec-notifier.h> |
49 | |
50 | #include "i915_vma.h" |
51 | #include "i915_vma_types.h" |
52 | #include "intel_bios.h" |
53 | #include "intel_display.h" |
54 | #include "intel_display_limits.h" |
55 | #include "intel_display_power.h" |
56 | #include "intel_dpll_mgr.h" |
57 | #include "intel_wm_types.h" |
58 | |
59 | struct drm_printer; |
60 | struct __intel_global_objs_state; |
61 | struct intel_ddi_buf_trans; |
62 | struct intel_fbc; |
63 | struct intel_connector; |
64 | struct intel_tc_port; |
65 | |
66 | /* |
67 | * Display related stuff |
68 | */ |
69 | |
70 | /* these are outputs from the chip - integrated only |
71 | external chips are via DVO or SDVO output */ |
72 | enum intel_output_type { |
73 | INTEL_OUTPUT_UNUSED = 0, |
74 | INTEL_OUTPUT_ANALOG = 1, |
75 | INTEL_OUTPUT_DVO = 2, |
76 | INTEL_OUTPUT_SDVO = 3, |
77 | INTEL_OUTPUT_LVDS = 4, |
78 | INTEL_OUTPUT_TVOUT = 5, |
79 | INTEL_OUTPUT_HDMI = 6, |
80 | INTEL_OUTPUT_DP = 7, |
81 | INTEL_OUTPUT_EDP = 8, |
82 | INTEL_OUTPUT_DSI = 9, |
83 | INTEL_OUTPUT_DDI = 10, |
84 | INTEL_OUTPUT_DP_MST = 11, |
85 | }; |
86 | |
87 | enum hdmi_force_audio { |
88 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ |
89 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ |
90 | HDMI_AUDIO_AUTO, /* trust EDID */ |
91 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ |
92 | }; |
93 | |
94 | /* "Broadcast RGB" property */ |
95 | enum intel_broadcast_rgb { |
96 | INTEL_BROADCAST_RGB_AUTO, |
97 | INTEL_BROADCAST_RGB_FULL, |
98 | INTEL_BROADCAST_RGB_LIMITED, |
99 | }; |
100 | |
101 | struct intel_fb_view { |
102 | /* |
103 | * The remap information used in the remapped and rotated views to |
104 | * create the DMA scatter-gather list for each FB color plane. This sg |
105 | * list is created along with the view type (gtt.type) specific |
106 | * i915_vma object and contains the list of FB object pages (reordered |
107 | * in the rotated view) that are visible in the view. |
108 | * In the normal view the FB object's backing store sg list is used |
109 | * directly and hence the remap information here is not used. |
110 | */ |
111 | struct i915_gtt_view gtt; |
112 | |
113 | /* |
114 | * The GTT view (gtt.type) specific information for each FB color |
115 | * plane. In the normal GTT view all formats (up to 4 color planes), |
116 | * in the rotated and remapped GTT view all no-CCS formats (up to 2 |
117 | * color planes) are supported. |
118 | * |
119 | * The view information shared by all FB color planes in the FB, |
120 | * like dst x/y and src/dst width, is stored separately in |
121 | * intel_plane_state. |
122 | */ |
123 | struct i915_color_plane_view { |
124 | u32 offset; |
125 | unsigned int x, y; |
126 | /* |
127 | * Plane stride in: |
128 | * bytes for 0/180 degree rotation |
129 | * pixels for 90/270 degree rotation |
130 | */ |
131 | unsigned int mapping_stride; |
132 | unsigned int scanout_stride; |
133 | } color_plane[4]; |
134 | }; |
135 | |
136 | struct intel_framebuffer { |
137 | struct drm_framebuffer base; |
138 | struct intel_frontbuffer *frontbuffer; |
139 | |
140 | /* Params to remap the FB pages and program the plane registers in each view. */ |
141 | struct intel_fb_view normal_view; |
142 | union { |
143 | struct intel_fb_view rotated_view; |
144 | struct intel_fb_view remapped_view; |
145 | }; |
146 | |
147 | struct i915_address_space *dpt_vm; |
148 | }; |
149 | |
150 | enum intel_hotplug_state { |
151 | INTEL_HOTPLUG_UNCHANGED, |
152 | INTEL_HOTPLUG_CHANGED, |
153 | INTEL_HOTPLUG_RETRY, |
154 | }; |
155 | |
156 | struct intel_encoder { |
157 | struct drm_encoder base; |
158 | |
159 | enum intel_output_type type; |
160 | enum port port; |
161 | u16 cloneable; |
162 | u8 pipe_mask; |
163 | enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder, |
164 | struct intel_connector *connector); |
165 | enum intel_output_type (*compute_output_type)(struct intel_encoder *, |
166 | struct intel_crtc_state *, |
167 | struct drm_connector_state *); |
168 | int (*compute_config)(struct intel_encoder *, |
169 | struct intel_crtc_state *, |
170 | struct drm_connector_state *); |
171 | int (*compute_config_late)(struct intel_encoder *, |
172 | struct intel_crtc_state *, |
173 | struct drm_connector_state *); |
174 | void (*pre_pll_enable)(struct intel_atomic_state *, |
175 | struct intel_encoder *, |
176 | const struct intel_crtc_state *, |
177 | const struct drm_connector_state *); |
178 | void (*pre_enable)(struct intel_atomic_state *, |
179 | struct intel_encoder *, |
180 | const struct intel_crtc_state *, |
181 | const struct drm_connector_state *); |
182 | void (*enable)(struct intel_atomic_state *, |
183 | struct intel_encoder *, |
184 | const struct intel_crtc_state *, |
185 | const struct drm_connector_state *); |
186 | void (*disable)(struct intel_atomic_state *, |
187 | struct intel_encoder *, |
188 | const struct intel_crtc_state *, |
189 | const struct drm_connector_state *); |
190 | void (*post_disable)(struct intel_atomic_state *, |
191 | struct intel_encoder *, |
192 | const struct intel_crtc_state *, |
193 | const struct drm_connector_state *); |
194 | void (*post_pll_disable)(struct intel_atomic_state *, |
195 | struct intel_encoder *, |
196 | const struct intel_crtc_state *, |
197 | const struct drm_connector_state *); |
198 | void (*update_pipe)(struct intel_atomic_state *, |
199 | struct intel_encoder *, |
200 | const struct intel_crtc_state *, |
201 | const struct drm_connector_state *); |
202 | void (*audio_enable)(struct intel_encoder *encoder, |
203 | const struct intel_crtc_state *crtc_state, |
204 | const struct drm_connector_state *conn_state); |
205 | void (*audio_disable)(struct intel_encoder *encoder, |
206 | const struct intel_crtc_state *old_crtc_state, |
207 | const struct drm_connector_state *old_conn_state); |
208 | /* Read out the current hw state of this connector, returning true if |
209 | * the encoder is active. If the encoder is enabled it also set the pipe |
210 | * it is connected to in the pipe parameter. */ |
211 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
212 | /* Reconstructs the equivalent mode flags for the current hardware |
213 | * state. This must be called _after_ display->get_pipe_config has |
214 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
215 | * be set correctly before calling this function. */ |
216 | void (*get_config)(struct intel_encoder *, |
217 | struct intel_crtc_state *pipe_config); |
218 | |
219 | /* |
220 | * Optional hook called during init/resume to sync any state |
221 | * stored in the encoder (eg. DP link parameters) wrt. the HW state. |
222 | */ |
223 | void (*sync_state)(struct intel_encoder *encoder, |
224 | const struct intel_crtc_state *crtc_state); |
225 | |
226 | /* |
227 | * Optional hook, returning true if this encoder allows a fastset |
228 | * during the initial commit, false otherwise. |
229 | */ |
230 | bool (*initial_fastset_check)(struct intel_encoder *encoder, |
231 | struct intel_crtc_state *crtc_state); |
232 | |
233 | /* |
234 | * Acquires the power domains needed for an active encoder during |
235 | * hardware state readout. |
236 | */ |
237 | void (*get_power_domains)(struct intel_encoder *encoder, |
238 | struct intel_crtc_state *crtc_state); |
239 | /* |
240 | * Called during system suspend after all pending requests for the |
241 | * encoder are flushed (for example for DP AUX transactions) and |
242 | * device interrupts are disabled. |
243 | * All modeset locks are held while the hook is called. |
244 | */ |
245 | void (*suspend)(struct intel_encoder *); |
246 | /* |
247 | * Called without the modeset locks held after the suspend() hook for |
248 | * all encoders have been called. |
249 | */ |
250 | void (*suspend_complete)(struct intel_encoder *encoder); |
251 | /* |
252 | * Called during system reboot/shutdown after all the |
253 | * encoders have been disabled and suspended. |
254 | * All modeset locks are held while the hook is called. |
255 | */ |
256 | void (*shutdown)(struct intel_encoder *encoder); |
257 | /* |
258 | * Called without the modeset locks held after the shutdown() hook for |
259 | * all encoders have been called. |
260 | */ |
261 | void (*shutdown_complete)(struct intel_encoder *encoder); |
262 | /* |
263 | * Enable/disable the clock to the port. |
264 | */ |
265 | void (*enable_clock)(struct intel_encoder *encoder, |
266 | const struct intel_crtc_state *crtc_state); |
267 | void (*disable_clock)(struct intel_encoder *encoder); |
268 | /* |
269 | * Returns whether the port clock is enabled or not. |
270 | */ |
271 | bool (*is_clock_enabled)(struct intel_encoder *encoder); |
272 | /* |
273 | * Returns the PLL type the port uses. |
274 | */ |
275 | enum icl_port_dpll_id (*port_pll_type)(struct intel_encoder *encoder, |
276 | const struct intel_crtc_state *crtc_state); |
277 | const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder, |
278 | const struct intel_crtc_state *crtc_state, |
279 | int *n_entries); |
280 | void (*set_signal_levels)(struct intel_encoder *encoder, |
281 | const struct intel_crtc_state *crtc_state); |
282 | |
283 | enum hpd_pin hpd_pin; |
284 | enum intel_display_power_domain power_domain; |
285 | |
286 | /* VBT information for this encoder (may be NULL for older platforms) */ |
287 | const struct intel_bios_encoder_data *devdata; |
288 | }; |
289 | |
290 | struct intel_panel_bl_funcs { |
291 | /* Connector and platform specific backlight functions */ |
292 | int (*setup)(struct intel_connector *connector, enum pipe pipe); |
293 | u32 (*get)(struct intel_connector *connector, enum pipe pipe); |
294 | void (*set)(const struct drm_connector_state *conn_state, u32 level); |
295 | void (*disable)(const struct drm_connector_state *conn_state, u32 level); |
296 | void (*enable)(const struct intel_crtc_state *crtc_state, |
297 | const struct drm_connector_state *conn_state, u32 level); |
298 | u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz); |
299 | }; |
300 | |
301 | enum drrs_type { |
302 | DRRS_TYPE_NONE, |
303 | DRRS_TYPE_STATIC, |
304 | DRRS_TYPE_SEAMLESS, |
305 | }; |
306 | |
307 | struct intel_vbt_panel_data { |
308 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
309 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
310 | |
311 | /* Feature bits */ |
312 | int panel_type; |
313 | unsigned int lvds_dither:1; |
314 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
315 | |
316 | bool vrr; |
317 | |
318 | u8 seamless_drrs_min_refresh_rate; |
319 | enum drrs_type drrs_type; |
320 | |
321 | struct { |
322 | int max_link_rate; |
323 | int rate; |
324 | int lanes; |
325 | int preemphasis; |
326 | int vswing; |
327 | int bpp; |
328 | struct edp_power_seq pps; |
329 | u8 drrs_msa_timing_delay; |
330 | bool low_vswing; |
331 | bool hobl; |
332 | } edp; |
333 | |
334 | struct { |
335 | bool enable; |
336 | bool full_link; |
337 | bool require_aux_wakeup; |
338 | int idle_frames; |
339 | int tp1_wakeup_time_us; |
340 | int tp2_tp3_wakeup_time_us; |
341 | int psr2_tp2_tp3_wakeup_time_us; |
342 | } psr; |
343 | |
344 | struct { |
345 | u16 pwm_freq_hz; |
346 | u16 brightness_precision_bits; |
347 | u16 hdr_dpcd_refresh_timeout; |
348 | bool present; |
349 | bool active_low_pwm; |
350 | u8 min_brightness; /* min_brightness/255 of max */ |
351 | s8 controller; /* brightness controller number */ |
352 | enum intel_backlight_type type; |
353 | } backlight; |
354 | |
355 | /* MIPI DSI */ |
356 | struct { |
357 | u16 panel_id; |
358 | struct mipi_config *config; |
359 | struct mipi_pps_data *pps; |
360 | u16 bl_ports; |
361 | u16 cabc_ports; |
362 | u8 seq_version; |
363 | u32 size; |
364 | u8 *data; |
365 | const u8 *sequence[MIPI_SEQ_MAX]; |
366 | u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ |
367 | enum drm_panel_orientation orientation; |
368 | } dsi; |
369 | }; |
370 | |
371 | struct intel_panel { |
372 | /* Fixed EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
373 | const struct drm_edid *fixed_edid; |
374 | |
375 | struct list_head fixed_modes; |
376 | |
377 | /* backlight */ |
378 | struct { |
379 | bool present; |
380 | u32 level; |
381 | u32 min; |
382 | u32 max; |
383 | bool enabled; |
384 | bool combination_mode; /* gen 2/4 only */ |
385 | bool active_low_pwm; |
386 | bool alternate_pwm_increment; /* lpt+ */ |
387 | |
388 | /* PWM chip */ |
389 | u32 pwm_level_min; |
390 | u32 pwm_level_max; |
391 | bool pwm_enabled; |
392 | bool util_pin_active_low; /* bxt+ */ |
393 | u8 controller; /* bxt+ only */ |
394 | struct pwm_device *pwm; |
395 | struct pwm_state pwm_state; |
396 | |
397 | /* DPCD backlight */ |
398 | union { |
399 | struct { |
400 | struct drm_edp_backlight_info info; |
401 | } vesa; |
402 | struct { |
403 | bool sdr_uses_aux; |
404 | } intel; |
405 | } edp; |
406 | |
407 | struct backlight_device *device; |
408 | |
409 | const struct intel_panel_bl_funcs *funcs; |
410 | const struct intel_panel_bl_funcs *pwm_funcs; |
411 | void (*power)(struct intel_connector *, bool enable); |
412 | } backlight; |
413 | |
414 | struct intel_vbt_panel_data vbt; |
415 | }; |
416 | |
417 | struct intel_digital_port; |
418 | |
419 | enum check_link_response { |
420 | HDCP_LINK_PROTECTED = 0, |
421 | HDCP_TOPOLOGY_CHANGE, |
422 | HDCP_LINK_INTEGRITY_FAILURE, |
423 | HDCP_REAUTH_REQUEST |
424 | }; |
425 | |
426 | /* |
427 | * This structure serves as a translation layer between the generic HDCP code |
428 | * and the bus-specific code. What that means is that HDCP over HDMI differs |
429 | * from HDCP over DP, so to account for these differences, we need to |
430 | * communicate with the receiver through this shim. |
431 | * |
432 | * For completeness, the 2 buses differ in the following ways: |
433 | * - DP AUX vs. DDC |
434 | * HDCP registers on the receiver are set via DP AUX for DP, and |
435 | * they are set via DDC for HDMI. |
436 | * - Receiver register offsets |
437 | * The offsets of the registers are different for DP vs. HDMI |
438 | * - Receiver register masks/offsets |
439 | * For instance, the ready bit for the KSV fifo is in a different |
440 | * place on DP vs HDMI |
441 | * - Receiver register names |
442 | * Seriously. In the DP spec, the 16-bit register containing |
443 | * downstream information is called BINFO, on HDMI it's called |
444 | * BSTATUS. To confuse matters further, DP has a BSTATUS register |
445 | * with a completely different definition. |
446 | * - KSV FIFO |
447 | * On HDMI, the ksv fifo is read all at once, whereas on DP it must |
448 | * be read 3 keys at a time |
449 | * - Aksv output |
450 | * Since Aksv is hidden in hardware, there's different procedures |
451 | * to send it over DP AUX vs DDC |
452 | */ |
453 | struct intel_hdcp_shim { |
454 | /* Outputs the transmitter's An and Aksv values to the receiver. */ |
455 | int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an); |
456 | |
457 | /* Reads the receiver's key selection vector */ |
458 | int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv); |
459 | |
460 | /* |
461 | * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The |
462 | * definitions are the same in the respective specs, but the names are |
463 | * different. Call it BSTATUS since that's the name the HDMI spec |
464 | * uses and it was there first. |
465 | */ |
466 | int (*read_bstatus)(struct intel_digital_port *dig_port, |
467 | u8 *bstatus); |
468 | |
469 | /* Determines whether a repeater is present downstream */ |
470 | int (*repeater_present)(struct intel_digital_port *dig_port, |
471 | bool *repeater_present); |
472 | |
473 | /* Reads the receiver's Ri' value */ |
474 | int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri); |
475 | |
476 | /* Determines if the receiver's KSV FIFO is ready for consumption */ |
477 | int (*read_ksv_ready)(struct intel_digital_port *dig_port, |
478 | bool *ksv_ready); |
479 | |
480 | /* Reads the ksv fifo for num_downstream devices */ |
481 | int (*read_ksv_fifo)(struct intel_digital_port *dig_port, |
482 | int num_downstream, u8 *ksv_fifo); |
483 | |
484 | /* Reads a 32-bit part of V' from the receiver */ |
485 | int (*read_v_prime_part)(struct intel_digital_port *dig_port, |
486 | int i, u32 *part); |
487 | |
488 | /* Enables HDCP signalling on the port */ |
489 | int (*toggle_signalling)(struct intel_digital_port *dig_port, |
490 | enum transcoder cpu_transcoder, |
491 | bool enable); |
492 | |
493 | /* Enable/Disable stream encryption on DP MST Transport Link */ |
494 | int (*stream_encryption)(struct intel_connector *connector, |
495 | bool enable); |
496 | |
497 | /* Ensures the link is still protected */ |
498 | bool (*check_link)(struct intel_digital_port *dig_port, |
499 | struct intel_connector *connector); |
500 | |
501 | /* Detects panel's hdcp capability. This is optional for HDMI. */ |
502 | int (*hdcp_get_capability)(struct intel_digital_port *dig_port, |
503 | bool *hdcp_capable); |
504 | |
505 | /* HDCP adaptation(DP/HDMI) required on the port */ |
506 | enum hdcp_wired_protocol protocol; |
507 | |
508 | /* Detects whether sink is HDCP2.2 capable */ |
509 | int (*hdcp_2_2_get_capability)(struct intel_connector *connector, |
510 | bool *capable); |
511 | |
512 | /* Write HDCP2.2 messages */ |
513 | int (*write_2_2_msg)(struct intel_connector *connector, |
514 | void *buf, size_t size); |
515 | |
516 | /* Read HDCP2.2 messages */ |
517 | int (*read_2_2_msg)(struct intel_connector *connector, |
518 | u8 msg_id, void *buf, size_t size); |
519 | |
520 | /* |
521 | * Implementation of DP HDCP2.2 Errata for the communication of stream |
522 | * type to Receivers. In DP HDCP2.2 Stream type is one of the input to |
523 | * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI. |
524 | */ |
525 | int (*config_stream_type)(struct intel_connector *connector, |
526 | bool is_repeater, u8 type); |
527 | |
528 | /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */ |
529 | int (*stream_2_2_encryption)(struct intel_connector *connector, |
530 | bool enable); |
531 | |
532 | /* HDCP2.2 Link Integrity Check */ |
533 | int (*check_2_2_link)(struct intel_digital_port *dig_port, |
534 | struct intel_connector *connector); |
535 | |
536 | /* HDCP remote sink cap */ |
537 | int (*get_remote_hdcp_capability)(struct intel_connector *connector, |
538 | bool *hdcp_capable, bool *hdcp2_capable); |
539 | }; |
540 | |
541 | struct intel_hdcp { |
542 | const struct intel_hdcp_shim *shim; |
543 | /* Mutex for hdcp state of the connector */ |
544 | struct mutex mutex; |
545 | u64 value; |
546 | struct delayed_work check_work; |
547 | struct work_struct prop_work; |
548 | |
549 | /* HDCP1.4 Encryption status */ |
550 | bool hdcp_encrypted; |
551 | |
552 | /* HDCP2.2 related definitions */ |
553 | /* Flag indicates whether this connector supports HDCP2.2 or not. */ |
554 | bool hdcp2_supported; |
555 | |
556 | /* HDCP2.2 Encryption status */ |
557 | bool hdcp2_encrypted; |
558 | |
559 | /* |
560 | * Content Stream Type defined by content owner. TYPE0(0x0) content can |
561 | * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1) |
562 | * content can flow only through a link protected by HDCP2.2. |
563 | */ |
564 | u8 content_type; |
565 | |
566 | bool is_paired; |
567 | bool is_repeater; |
568 | |
569 | /* |
570 | * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT. |
571 | * Incremented after processing the RepeaterAuth_Send_ReceiverID_List. |
572 | * When it rolls over re-auth has to be triggered. |
573 | */ |
574 | u32 seq_num_v; |
575 | |
576 | /* |
577 | * Count of RepeaterAuth_Stream_Manage msg propagated. |
578 | * Initialized to 0 on AKE_INIT. Incremented after every successful |
579 | * transmission of RepeaterAuth_Stream_Manage message. When it rolls |
580 | * over re-Auth has to be triggered. |
581 | */ |
582 | u32 seq_num_m; |
583 | |
584 | /* |
585 | * Work queue to signal the CP_IRQ. Used for the waiters to read the |
586 | * available information from HDCP DP sink. |
587 | */ |
588 | wait_queue_head_t cp_irq_queue; |
589 | atomic_t cp_irq_count; |
590 | int cp_irq_count_cached; |
591 | |
592 | /* |
593 | * HDCP register access for gen12+ need the transcoder associated. |
594 | * Transcoder attached to the connector could be changed at modeset. |
595 | * Hence caching the transcoder here. |
596 | */ |
597 | enum transcoder cpu_transcoder; |
598 | /* Only used for DP MST stream encryption */ |
599 | enum transcoder stream_transcoder; |
600 | }; |
601 | |
602 | struct intel_connector { |
603 | struct drm_connector base; |
604 | /* |
605 | * The fixed encoder this connector is connected to. |
606 | */ |
607 | struct intel_encoder *encoder; |
608 | |
609 | /* ACPI device id for ACPI and driver cooperation */ |
610 | u32 acpi_device_id; |
611 | |
612 | /* Reads out the current hw, returning true if the connector is enabled |
613 | * and active (i.e. dpms ON state). */ |
614 | bool (*get_hw_state)(struct intel_connector *); |
615 | |
616 | /* |
617 | * Optional hook called during init/resume to sync any state |
618 | * stored in the connector (eg. DSC state) wrt. the HW state. |
619 | */ |
620 | void (*sync_state)(struct intel_connector *connector, |
621 | const struct intel_crtc_state *crtc_state); |
622 | |
623 | /* Panel info for eDP and LVDS */ |
624 | struct intel_panel panel; |
625 | |
626 | /* Cached EDID for detect. */ |
627 | const struct drm_edid *detect_edid; |
628 | |
629 | /* Number of times hotplug detection was tried after an HPD interrupt */ |
630 | int hotplug_retries; |
631 | |
632 | /* since POLL and HPD connectors may use the same HPD line keep the native |
633 | state of connector->polled in case hotplug storm detection changes it */ |
634 | u8 polled; |
635 | |
636 | struct drm_dp_mst_port *port; |
637 | |
638 | struct intel_dp *mst_port; |
639 | |
640 | bool force_bigjoiner_enable; |
641 | |
642 | struct { |
643 | struct drm_dp_aux *dsc_decompression_aux; |
644 | u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; |
645 | u8 fec_capability; |
646 | |
647 | u8 dsc_hblank_expansion_quirk:1; |
648 | u8 dsc_decompression_enabled:1; |
649 | } dp; |
650 | |
651 | /* Work struct to schedule a uevent on link train failure */ |
652 | struct work_struct modeset_retry_work; |
653 | |
654 | struct intel_hdcp hdcp; |
655 | }; |
656 | |
657 | struct intel_digital_connector_state { |
658 | struct drm_connector_state base; |
659 | |
660 | enum hdmi_force_audio force_audio; |
661 | int broadcast_rgb; |
662 | }; |
663 | |
664 | #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base) |
665 | |
666 | struct dpll { |
667 | /* given values */ |
668 | int n; |
669 | int m1, m2; |
670 | int p1, p2; |
671 | /* derived values */ |
672 | int dot; |
673 | int vco; |
674 | int m; |
675 | int p; |
676 | }; |
677 | |
678 | struct intel_atomic_state { |
679 | struct drm_atomic_state base; |
680 | |
681 | intel_wakeref_t wakeref; |
682 | |
683 | struct __intel_global_objs_state *global_objs; |
684 | int num_global_objs; |
685 | |
686 | /* Internal commit, as opposed to userspace/client initiated one */ |
687 | bool internal; |
688 | |
689 | bool dpll_set, modeset; |
690 | |
691 | struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; |
692 | |
693 | struct intel_dp_tunnel_inherited_state *inherited_dp_tunnels; |
694 | |
695 | /* |
696 | * Current watermarks can't be trusted during hardware readout, so |
697 | * don't bother calculating intermediate watermarks. |
698 | */ |
699 | bool skip_intermediate_wm; |
700 | |
701 | bool rps_interactive; |
702 | }; |
703 | |
704 | struct intel_plane_state { |
705 | struct drm_plane_state uapi; |
706 | |
707 | /* |
708 | * actual hardware state, the state we program to the hardware. |
709 | * The following members are used to verify the hardware state: |
710 | * During initial hw readout, they need to be copied from uapi. |
711 | */ |
712 | struct { |
713 | struct drm_crtc *crtc; |
714 | struct drm_framebuffer *fb; |
715 | |
716 | u16 alpha; |
717 | u16 pixel_blend_mode; |
718 | unsigned int rotation; |
719 | enum drm_color_encoding color_encoding; |
720 | enum drm_color_range color_range; |
721 | enum drm_scaling_filter scaling_filter; |
722 | } hw; |
723 | |
724 | struct i915_vma *ggtt_vma; |
725 | struct i915_vma *dpt_vma; |
726 | unsigned long flags; |
727 | #define PLANE_HAS_FENCE BIT(0) |
728 | |
729 | struct intel_fb_view view; |
730 | u32 phys_dma_addr; /* for cursor_needs_physical */ |
731 | |
732 | /* Plane pxp decryption state */ |
733 | bool decrypt; |
734 | |
735 | /* Plane state to display black pixels when pxp is borked */ |
736 | bool force_black; |
737 | |
738 | /* plane control register */ |
739 | u32 ctl; |
740 | |
741 | /* plane color control register */ |
742 | u32 color_ctl; |
743 | |
744 | /* chroma upsampler control register */ |
745 | u32 cus_ctl; |
746 | |
747 | /* |
748 | * scaler_id |
749 | * = -1 : not using a scaler |
750 | * >= 0 : using a scalers |
751 | * |
752 | * plane requiring a scaler: |
753 | * - During check_plane, its bit is set in |
754 | * crtc_state->scaler_state.scaler_users by calling helper function |
755 | * update_scaler_plane. |
756 | * - scaler_id indicates the scaler it got assigned. |
757 | * |
758 | * plane doesn't require a scaler: |
759 | * - this can happen when scaling is no more required or plane simply |
760 | * got disabled. |
761 | * - During check_plane, corresponding bit is reset in |
762 | * crtc_state->scaler_state.scaler_users by calling helper function |
763 | * update_scaler_plane. |
764 | */ |
765 | int scaler_id; |
766 | |
767 | /* |
768 | * planar_linked_plane: |
769 | * |
770 | * ICL planar formats require 2 planes that are updated as pairs. |
771 | * This member is used to make sure the other plane is also updated |
772 | * when required, and for update_slave() to find the correct |
773 | * plane_state to pass as argument. |
774 | */ |
775 | struct intel_plane *planar_linked_plane; |
776 | |
777 | /* |
778 | * planar_slave: |
779 | * If set don't update use the linked plane's state for updating |
780 | * this plane during atomic commit with the update_slave() callback. |
781 | * |
782 | * It's also used by the watermark code to ignore wm calculations on |
783 | * this plane. They're calculated by the linked plane's wm code. |
784 | */ |
785 | u32 planar_slave; |
786 | |
787 | struct drm_intel_sprite_colorkey ckey; |
788 | |
789 | struct drm_rect psr2_sel_fetch_area; |
790 | |
791 | /* Clear Color Value */ |
792 | u64 ccval; |
793 | |
794 | const char *no_fbc_reason; |
795 | }; |
796 | |
797 | struct intel_initial_plane_config { |
798 | struct intel_framebuffer *fb; |
799 | struct intel_memory_region *mem; |
800 | resource_size_t phys_base; |
801 | struct i915_vma *vma; |
802 | unsigned int tiling; |
803 | int size; |
804 | u32 base; |
805 | u8 rotation; |
806 | }; |
807 | |
808 | struct intel_scaler { |
809 | int in_use; |
810 | u32 mode; |
811 | }; |
812 | |
813 | struct intel_crtc_scaler_state { |
814 | #define SKL_NUM_SCALERS 2 |
815 | struct intel_scaler scalers[SKL_NUM_SCALERS]; |
816 | |
817 | /* |
818 | * scaler_users: keeps track of users requesting scalers on this crtc. |
819 | * |
820 | * If a bit is set, a user is using a scaler. |
821 | * Here user can be a plane or crtc as defined below: |
822 | * bits 0-30 - plane (bit position is index from drm_plane_index) |
823 | * bit 31 - crtc |
824 | * |
825 | * Instead of creating a new index to cover planes and crtc, using |
826 | * existing drm_plane_index for planes which is well less than 31 |
827 | * planes and bit 31 for crtc. This should be fine to cover all |
828 | * our platforms. |
829 | * |
830 | * intel_atomic_setup_scalers will setup available scalers to users |
831 | * requesting scalers. It will gracefully fail if request exceeds |
832 | * avilability. |
833 | */ |
834 | #define SKL_CRTC_INDEX 31 |
835 | unsigned scaler_users; |
836 | |
837 | /* scaler used by crtc for panel fitting purpose */ |
838 | int scaler_id; |
839 | }; |
840 | |
841 | /* {crtc,crtc_state}->mode_flags */ |
842 | /* Flag to get scanline using frame time stamps */ |
843 | #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1) |
844 | /* Flag to use the scanline counter instead of the pixel counter */ |
845 | #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2) |
846 | /* |
847 | * TE0 or TE1 flag is set if the crtc has a DSI encoder which |
848 | * is operating in command mode. |
849 | * Flag to use TE from DSI0 instead of VBI in command mode |
850 | */ |
851 | #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3) |
852 | /* Flag to use TE from DSI1 instead of VBI in command mode */ |
853 | #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4) |
854 | /* Flag to indicate mipi dsi periodic command mode where we do not get TE */ |
855 | #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5) |
856 | /* Do tricks to make vblank timestamps sane with VRR? */ |
857 | #define I915_MODE_FLAG_VRR (1<<6) |
858 | |
859 | struct intel_wm_level { |
860 | bool enable; |
861 | u32 pri_val; |
862 | u32 spr_val; |
863 | u32 cur_val; |
864 | u32 fbc_val; |
865 | }; |
866 | |
867 | struct intel_pipe_wm { |
868 | struct intel_wm_level wm[5]; |
869 | bool fbc_wm_enabled; |
870 | bool pipe_enabled; |
871 | bool sprites_enabled; |
872 | bool sprites_scaled; |
873 | }; |
874 | |
875 | struct skl_wm_level { |
876 | u16 min_ddb_alloc; |
877 | u16 blocks; |
878 | u8 lines; |
879 | bool enable; |
880 | bool ignore_lines; |
881 | bool can_sagv; |
882 | }; |
883 | |
884 | struct skl_plane_wm { |
885 | struct skl_wm_level wm[8]; |
886 | struct skl_wm_level uv_wm[8]; |
887 | struct skl_wm_level trans_wm; |
888 | struct { |
889 | struct skl_wm_level wm0; |
890 | struct skl_wm_level trans_wm; |
891 | } sagv; |
892 | bool is_planar; |
893 | }; |
894 | |
895 | struct skl_pipe_wm { |
896 | struct skl_plane_wm planes[I915_MAX_PLANES]; |
897 | bool use_sagv_wm; |
898 | }; |
899 | |
900 | enum vlv_wm_level { |
901 | VLV_WM_LEVEL_PM2, |
902 | VLV_WM_LEVEL_PM5, |
903 | VLV_WM_LEVEL_DDR_DVFS, |
904 | NUM_VLV_WM_LEVELS, |
905 | }; |
906 | |
907 | struct vlv_wm_state { |
908 | struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS]; |
909 | struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS]; |
910 | u8 num_levels; |
911 | bool cxsr; |
912 | }; |
913 | |
914 | struct vlv_fifo_state { |
915 | u16 plane[I915_MAX_PLANES]; |
916 | }; |
917 | |
918 | enum g4x_wm_level { |
919 | G4X_WM_LEVEL_NORMAL, |
920 | G4X_WM_LEVEL_SR, |
921 | G4X_WM_LEVEL_HPLL, |
922 | NUM_G4X_WM_LEVELS, |
923 | }; |
924 | |
925 | struct g4x_wm_state { |
926 | struct g4x_pipe_wm wm; |
927 | struct g4x_sr_wm sr; |
928 | struct g4x_sr_wm hpll; |
929 | bool cxsr; |
930 | bool hpll_en; |
931 | bool fbc_en; |
932 | }; |
933 | |
934 | struct intel_crtc_wm_state { |
935 | union { |
936 | /* |
937 | * raw: |
938 | * The "raw" watermark values produced by the formula |
939 | * given the plane's current state. They do not consider |
940 | * how much FIFO is actually allocated for each plane. |
941 | * |
942 | * optimal: |
943 | * The "optimal" watermark values given the current |
944 | * state of the planes and the amount of FIFO |
945 | * allocated to each, ignoring any previous state |
946 | * of the planes. |
947 | * |
948 | * intermediate: |
949 | * The "intermediate" watermark values when transitioning |
950 | * between the old and new "optimal" values. Used when |
951 | * the watermark registers are single buffered and hence |
952 | * their state changes asynchronously with regards to the |
953 | * actual plane registers. These are essentially the |
954 | * worst case combination of the old and new "optimal" |
955 | * watermarks, which are therefore safe to use when the |
956 | * plane is in either its old or new state. |
957 | */ |
958 | struct { |
959 | struct intel_pipe_wm intermediate; |
960 | struct intel_pipe_wm optimal; |
961 | } ilk; |
962 | |
963 | struct { |
964 | struct skl_pipe_wm raw; |
965 | /* gen9+ only needs 1-step wm programming */ |
966 | struct skl_pipe_wm optimal; |
967 | struct skl_ddb_entry ddb; |
968 | /* |
969 | * pre-icl: for packed/planar CbCr |
970 | * icl+: for everything |
971 | */ |
972 | struct skl_ddb_entry plane_ddb[I915_MAX_PLANES]; |
973 | /* pre-icl: for planar Y */ |
974 | struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES]; |
975 | } skl; |
976 | |
977 | struct { |
978 | struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */ |
979 | struct vlv_wm_state intermediate; /* inverted */ |
980 | struct vlv_wm_state optimal; /* inverted */ |
981 | struct vlv_fifo_state fifo_state; |
982 | } vlv; |
983 | |
984 | struct { |
985 | struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS]; |
986 | struct g4x_wm_state intermediate; |
987 | struct g4x_wm_state optimal; |
988 | } g4x; |
989 | }; |
990 | |
991 | /* |
992 | * Platforms with two-step watermark programming will need to |
993 | * update watermark programming post-vblank to switch from the |
994 | * safe intermediate watermarks to the optimal final |
995 | * watermarks. |
996 | */ |
997 | bool need_postvbl_update; |
998 | }; |
999 | |
1000 | enum intel_output_format { |
1001 | INTEL_OUTPUT_FORMAT_RGB, |
1002 | INTEL_OUTPUT_FORMAT_YCBCR420, |
1003 | INTEL_OUTPUT_FORMAT_YCBCR444, |
1004 | }; |
1005 | |
1006 | struct intel_mpllb_state { |
1007 | u32 clock; /* in KHz */ |
1008 | u32 ref_control; |
1009 | u32 mpllb_cp; |
1010 | u32 mpllb_div; |
1011 | u32 mpllb_div2; |
1012 | u32 mpllb_fracn1; |
1013 | u32 mpllb_fracn2; |
1014 | u32 mpllb_sscen; |
1015 | u32 mpllb_sscstep; |
1016 | }; |
1017 | |
1018 | /* Used by dp and fdi links */ |
1019 | struct intel_link_m_n { |
1020 | u32 tu; |
1021 | u32 data_m; |
1022 | u32 data_n; |
1023 | u32 link_m; |
1024 | u32 link_n; |
1025 | }; |
1026 | |
1027 | struct intel_csc_matrix { |
1028 | u16 coeff[9]; |
1029 | u16 preoff[3]; |
1030 | u16 postoff[3]; |
1031 | }; |
1032 | |
1033 | struct intel_c10pll_state { |
1034 | u32 clock; /* in KHz */ |
1035 | u8 tx; |
1036 | u8 cmn; |
1037 | u8 pll[20]; |
1038 | }; |
1039 | |
1040 | struct intel_c20pll_state { |
1041 | u32 clock; /* in kHz */ |
1042 | u16 tx[3]; |
1043 | u16 cmn[4]; |
1044 | union { |
1045 | u16 mplla[10]; |
1046 | u16 mpllb[11]; |
1047 | }; |
1048 | }; |
1049 | |
1050 | struct intel_cx0pll_state { |
1051 | union { |
1052 | struct intel_c10pll_state c10; |
1053 | struct intel_c20pll_state c20; |
1054 | }; |
1055 | bool ssc_enabled; |
1056 | }; |
1057 | |
1058 | struct intel_crtc_state { |
1059 | /* |
1060 | * uapi (drm) state. This is the software state shown to userspace. |
1061 | * In particular, the following members are used for bookkeeping: |
1062 | * - crtc |
1063 | * - state |
1064 | * - *_changed |
1065 | * - event |
1066 | * - commit |
1067 | * - mode_blob |
1068 | */ |
1069 | struct drm_crtc_state uapi; |
1070 | |
1071 | /* |
1072 | * actual hardware state, the state we program to the hardware. |
1073 | * The following members are used to verify the hardware state: |
1074 | * - enable |
1075 | * - active |
1076 | * - mode / pipe_mode / adjusted_mode |
1077 | * - color property blobs. |
1078 | * |
1079 | * During initial hw readout, they need to be copied to uapi. |
1080 | * |
1081 | * Bigjoiner will allow a transcoder mode that spans 2 pipes; |
1082 | * Use the pipe_mode for calculations like watermarks, pipe |
1083 | * scaler, and bandwidth. |
1084 | * |
1085 | * Use adjusted_mode for things that need to know the full |
1086 | * mode on the transcoder, which spans all pipes. |
1087 | */ |
1088 | struct { |
1089 | bool active, enable; |
1090 | /* logical state of LUTs */ |
1091 | struct drm_property_blob *degamma_lut, *gamma_lut, *ctm; |
1092 | struct drm_display_mode mode, pipe_mode, adjusted_mode; |
1093 | enum drm_scaling_filter scaling_filter; |
1094 | } hw; |
1095 | |
1096 | /* actual state of LUTs */ |
1097 | struct drm_property_blob *pre_csc_lut, *post_csc_lut; |
1098 | |
1099 | struct intel_csc_matrix csc, output_csc; |
1100 | |
1101 | /** |
1102 | * quirks - bitfield with hw state readout quirks |
1103 | * |
1104 | * For various reasons the hw state readout code might not be able to |
1105 | * completely faithfully read out the current state. These cases are |
1106 | * tracked with quirk flags so that fastboot and state checker can act |
1107 | * accordingly. |
1108 | */ |
1109 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
1110 | unsigned long quirks; |
1111 | |
1112 | unsigned fb_bits; /* framebuffers to flip */ |
1113 | bool update_pipe; /* can a fast modeset be performed? */ |
1114 | bool update_m_n; /* update M/N seamlessly during fastset? */ |
1115 | bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */ |
1116 | bool disable_cxsr; |
1117 | bool update_wm_pre, update_wm_post; /* watermarks are updated */ |
1118 | bool fifo_changed; /* FIFO split is changed */ |
1119 | bool preload_luts; |
1120 | bool inherited; /* state inherited from BIOS? */ |
1121 | |
1122 | /* Ask the hardware to actually async flip? */ |
1123 | bool do_async_flip; |
1124 | |
1125 | /* Pipe source size (ie. panel fitter input size) |
1126 | * All planes will be positioned inside this space, |
1127 | * and get clipped at the edges. */ |
1128 | struct drm_rect pipe_src; |
1129 | |
1130 | /* |
1131 | * Pipe pixel rate, adjusted for |
1132 | * panel fitter/pipe scaler downscaling. |
1133 | */ |
1134 | unsigned int pixel_rate; |
1135 | |
1136 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
1137 | * between pch encoders and cpu encoders. */ |
1138 | bool has_pch_encoder; |
1139 | |
1140 | /* Are we sending infoframes on the attached port */ |
1141 | bool has_infoframe; |
1142 | |
1143 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
1144 | * pipe on Haswell and later (where we have a special eDP transcoder) |
1145 | * and Broxton (where we have special DSI transcoders). */ |
1146 | enum transcoder cpu_transcoder; |
1147 | |
1148 | /* |
1149 | * Use reduced/limited/broadcast rbg range, compressing from the full |
1150 | * range fed into the crtcs. |
1151 | */ |
1152 | bool limited_color_range; |
1153 | |
1154 | /* Bitmask of encoder types (enum intel_output_type) |
1155 | * driven by the pipe. |
1156 | */ |
1157 | unsigned int output_types; |
1158 | |
1159 | /* Whether we should send NULL infoframes. Required for audio. */ |
1160 | bool has_hdmi_sink; |
1161 | |
1162 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
1163 | * has_dp_encoder is set. */ |
1164 | bool has_audio; |
1165 | |
1166 | /* |
1167 | * Enable dithering, used when the selected pipe bpp doesn't match the |
1168 | * plane bpp. |
1169 | */ |
1170 | bool dither; |
1171 | |
1172 | /* |
1173 | * Dither gets enabled for 18bpp which causes CRC mismatch errors for |
1174 | * compliance video pattern tests. |
1175 | * Disable dither only if it is a compliance test request for |
1176 | * 18bpp. |
1177 | */ |
1178 | bool dither_force_disable; |
1179 | |
1180 | /* Controls for the clock computation, to override various stages. */ |
1181 | bool clock_set; |
1182 | |
1183 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
1184 | * work correctly, we need to track this at runtime.*/ |
1185 | bool sdvo_tv_clock; |
1186 | |
1187 | /* |
1188 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really |
1189 | * required. This is set in the 2nd loop of calling encoder's |
1190 | * ->compute_config if the first pick doesn't work out. |
1191 | */ |
1192 | bool bw_constrained; |
1193 | |
1194 | /* Settings for the intel dpll used on pretty much everything but |
1195 | * haswell. */ |
1196 | struct dpll dpll; |
1197 | |
1198 | /* Selected dpll when shared or NULL. */ |
1199 | struct intel_shared_dpll *shared_dpll; |
1200 | |
1201 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
1202 | union { |
1203 | struct intel_dpll_hw_state dpll_hw_state; |
1204 | struct intel_mpllb_state mpllb_state; |
1205 | struct intel_cx0pll_state cx0pll_state; |
1206 | }; |
1207 | |
1208 | /* |
1209 | * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by |
1210 | * setting shared_dpll and dpll_hw_state to one of these reserved ones. |
1211 | */ |
1212 | struct icl_port_dpll { |
1213 | struct intel_shared_dpll *pll; |
1214 | struct intel_dpll_hw_state hw_state; |
1215 | } icl_port_dplls[ICL_PORT_DPLL_COUNT]; |
1216 | |
1217 | /* DSI PLL registers */ |
1218 | struct { |
1219 | u32 ctrl, div; |
1220 | } dsi_pll; |
1221 | |
1222 | int max_link_bpp_x16; /* in 1/16 bpp units */ |
1223 | int pipe_bpp; /* in 1 bpp units */ |
1224 | struct intel_link_m_n dp_m_n; |
1225 | |
1226 | /* m2_n2 for eDP downclock */ |
1227 | struct intel_link_m_n dp_m2_n2; |
1228 | bool has_drrs; |
1229 | |
1230 | /* PSR is supported but might not be enabled due the lack of enabled planes */ |
1231 | bool has_psr; |
1232 | bool has_psr2; |
1233 | bool enable_psr2_sel_fetch; |
1234 | bool enable_psr2_su_region_et; |
1235 | bool req_psr2_sdp_prior_scanline; |
1236 | bool has_panel_replay; |
1237 | bool wm_level_disabled; |
1238 | u32 dc3co_exitline; |
1239 | u16 su_y_granularity; |
1240 | |
1241 | /* |
1242 | * Frequence the dpll for the port should run at. Differs from the |
1243 | * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also |
1244 | * already multiplied by pixel_multiplier. |
1245 | */ |
1246 | int port_clock; |
1247 | |
1248 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
1249 | unsigned pixel_multiplier; |
1250 | |
1251 | /* I915_MODE_FLAG_* */ |
1252 | u8 mode_flags; |
1253 | |
1254 | u8 lane_count; |
1255 | |
1256 | /* |
1257 | * Used by platforms having DP/HDMI PHY with programmable lane |
1258 | * latency optimization. |
1259 | */ |
1260 | u8 lane_lat_optim_mask; |
1261 | |
1262 | /* minimum acceptable voltage level */ |
1263 | u8 min_voltage_level; |
1264 | |
1265 | /* Panel fitter controls for gen2-gen4 + VLV */ |
1266 | struct { |
1267 | u32 control; |
1268 | u32 pgm_ratios; |
1269 | u32 lvds_border_bits; |
1270 | } gmch_pfit; |
1271 | |
1272 | /* Panel fitter placement and size for Ironlake+ */ |
1273 | struct { |
1274 | struct drm_rect dst; |
1275 | bool enabled; |
1276 | bool force_thru; |
1277 | } pch_pfit; |
1278 | |
1279 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
1280 | int fdi_lanes; |
1281 | struct intel_link_m_n fdi_m_n; |
1282 | |
1283 | bool ips_enabled; |
1284 | |
1285 | bool crc_enabled; |
1286 | |
1287 | bool double_wide; |
1288 | |
1289 | int pbn; |
1290 | |
1291 | struct intel_crtc_scaler_state scaler_state; |
1292 | |
1293 | /* w/a for waiting 2 vblanks during crtc enable */ |
1294 | enum pipe hsw_workaround_pipe; |
1295 | |
1296 | /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ |
1297 | bool disable_lp_wm; |
1298 | |
1299 | struct intel_crtc_wm_state wm; |
1300 | |
1301 | int min_cdclk[I915_MAX_PLANES]; |
1302 | |
1303 | /* for packed/planar CbCr */ |
1304 | u32 data_rate[I915_MAX_PLANES]; |
1305 | /* for planar Y */ |
1306 | u32 data_rate_y[I915_MAX_PLANES]; |
1307 | |
1308 | /* FIXME unify with data_rate[]? */ |
1309 | u64 rel_data_rate[I915_MAX_PLANES]; |
1310 | u64 rel_data_rate_y[I915_MAX_PLANES]; |
1311 | |
1312 | /* Gamma mode programmed on the pipe */ |
1313 | u32 gamma_mode; |
1314 | |
1315 | union { |
1316 | /* CSC mode programmed on the pipe */ |
1317 | u32 csc_mode; |
1318 | |
1319 | /* CHV CGM mode */ |
1320 | u32 cgm_mode; |
1321 | }; |
1322 | |
1323 | /* bitmask of logically enabled planes (enum plane_id) */ |
1324 | u8 enabled_planes; |
1325 | |
1326 | /* bitmask of actually visible planes (enum plane_id) */ |
1327 | u8 active_planes; |
1328 | u8 scaled_planes; |
1329 | u8 nv12_planes; |
1330 | u8 c8_planes; |
1331 | |
1332 | /* bitmask of planes that will be updated during the commit */ |
1333 | u8 update_planes; |
1334 | |
1335 | /* bitmask of planes with async flip active */ |
1336 | u8 async_flip_planes; |
1337 | |
1338 | u8 framestart_delay; /* 1-4 */ |
1339 | u8 msa_timing_delay; /* 0-3 */ |
1340 | |
1341 | struct { |
1342 | u32 enable; |
1343 | u32 gcp; |
1344 | union hdmi_infoframe avi; |
1345 | union hdmi_infoframe spd; |
1346 | union hdmi_infoframe hdmi; |
1347 | union hdmi_infoframe drm; |
1348 | struct drm_dp_vsc_sdp vsc; |
1349 | } infoframes; |
1350 | |
1351 | u8 eld[MAX_ELD_BYTES]; |
1352 | |
1353 | /* HDMI scrambling status */ |
1354 | bool hdmi_scrambling; |
1355 | |
1356 | /* HDMI High TMDS char rate ratio */ |
1357 | bool hdmi_high_tmds_clock_ratio; |
1358 | |
1359 | /* |
1360 | * Output format RGB/YCBCR etc., that is coming out |
1361 | * at the end of the pipe. |
1362 | */ |
1363 | enum intel_output_format output_format; |
1364 | |
1365 | /* |
1366 | * Sink output format RGB/YCBCR etc., that is going |
1367 | * into the sink. |
1368 | */ |
1369 | enum intel_output_format sink_format; |
1370 | |
1371 | /* enable pipe gamma? */ |
1372 | bool gamma_enable; |
1373 | |
1374 | /* enable pipe csc? */ |
1375 | bool csc_enable; |
1376 | |
1377 | /* enable vlv/chv wgc csc? */ |
1378 | bool wgc_enable; |
1379 | |
1380 | /* big joiner pipe bitmask */ |
1381 | u8 bigjoiner_pipes; |
1382 | |
1383 | /* Display Stream compression state */ |
1384 | struct { |
1385 | bool compression_enable; |
1386 | bool dsc_split; |
1387 | /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */ |
1388 | u16 compressed_bpp_x16; |
1389 | u8 slice_count; |
1390 | struct drm_dsc_config config; |
1391 | } dsc; |
1392 | |
1393 | /* DP tunnel used for BW allocation. */ |
1394 | struct drm_dp_tunnel_ref dp_tunnel_ref; |
1395 | |
1396 | /* HSW+ linetime watermarks */ |
1397 | u16 linetime; |
1398 | u16 ips_linetime; |
1399 | |
1400 | bool enhanced_framing; |
1401 | |
1402 | /* |
1403 | * Forward Error Correction. |
1404 | * |
1405 | * Note: This will be false for 128b/132b, which will always have FEC |
1406 | * enabled automatically. |
1407 | */ |
1408 | bool fec_enable; |
1409 | |
1410 | bool sdp_split_enable; |
1411 | |
1412 | /* Pointer to master transcoder in case of tiled displays */ |
1413 | enum transcoder master_transcoder; |
1414 | |
1415 | /* Bitmask to indicate slaves attached */ |
1416 | u8 sync_mode_slaves_mask; |
1417 | |
1418 | /* Only valid on TGL+ */ |
1419 | enum transcoder mst_master_transcoder; |
1420 | |
1421 | /* For DSB related info */ |
1422 | struct intel_dsb *dsb; |
1423 | |
1424 | u32 psr2_man_track_ctl; |
1425 | |
1426 | u32 pipe_srcsz_early_tpt; |
1427 | |
1428 | struct drm_rect psr2_su_area; |
1429 | |
1430 | /* Variable Refresh Rate state */ |
1431 | struct { |
1432 | bool enable, in_range; |
1433 | u8 pipeline_full; |
1434 | u16 flipline, vmin, vmax, guardband; |
1435 | } vrr; |
1436 | |
1437 | /* Stream Splitter for eDP MSO */ |
1438 | struct { |
1439 | bool enable; |
1440 | u8 link_count; |
1441 | u8 pixel_overlap; |
1442 | } splitter; |
1443 | |
1444 | /* for loading single buffered registers during vblank */ |
1445 | struct drm_vblank_work vblank_work; |
1446 | }; |
1447 | |
1448 | enum intel_pipe_crc_source { |
1449 | INTEL_PIPE_CRC_SOURCE_NONE, |
1450 | INTEL_PIPE_CRC_SOURCE_PLANE1, |
1451 | INTEL_PIPE_CRC_SOURCE_PLANE2, |
1452 | INTEL_PIPE_CRC_SOURCE_PLANE3, |
1453 | INTEL_PIPE_CRC_SOURCE_PLANE4, |
1454 | INTEL_PIPE_CRC_SOURCE_PLANE5, |
1455 | INTEL_PIPE_CRC_SOURCE_PLANE6, |
1456 | INTEL_PIPE_CRC_SOURCE_PLANE7, |
1457 | INTEL_PIPE_CRC_SOURCE_PIPE, |
1458 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1459 | INTEL_PIPE_CRC_SOURCE_TV, |
1460 | INTEL_PIPE_CRC_SOURCE_DP_B, |
1461 | INTEL_PIPE_CRC_SOURCE_DP_C, |
1462 | INTEL_PIPE_CRC_SOURCE_DP_D, |
1463 | INTEL_PIPE_CRC_SOURCE_AUTO, |
1464 | INTEL_PIPE_CRC_SOURCE_MAX, |
1465 | }; |
1466 | |
1467 | enum drrs_refresh_rate { |
1468 | DRRS_REFRESH_RATE_HIGH, |
1469 | DRRS_REFRESH_RATE_LOW, |
1470 | }; |
1471 | |
1472 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
1473 | struct intel_pipe_crc { |
1474 | spinlock_t lock; |
1475 | int skipped; |
1476 | enum intel_pipe_crc_source source; |
1477 | }; |
1478 | |
1479 | struct intel_crtc { |
1480 | struct drm_crtc base; |
1481 | enum pipe pipe; |
1482 | /* |
1483 | * Whether the crtc and the connected output pipeline is active. Implies |
1484 | * that crtc->enabled is set, i.e. the current mode configuration has |
1485 | * some outputs connected to this crtc. |
1486 | */ |
1487 | bool active; |
1488 | u8 plane_ids_mask; |
1489 | |
1490 | /* I915_MODE_FLAG_* */ |
1491 | u8 mode_flags; |
1492 | |
1493 | u16 vmax_vblank_start; |
1494 | |
1495 | struct intel_display_power_domain_set enabled_power_domains; |
1496 | struct intel_display_power_domain_set hw_readout_power_domains; |
1497 | struct intel_overlay *overlay; |
1498 | |
1499 | struct intel_crtc_state *config; |
1500 | |
1501 | /* armed event for async flip */ |
1502 | struct drm_pending_vblank_event *flip_done_event; |
1503 | |
1504 | /* Access to these should be protected by dev_priv->irq_lock. */ |
1505 | bool cpu_fifo_underrun_disabled; |
1506 | bool pch_fifo_underrun_disabled; |
1507 | |
1508 | /* per-pipe watermark state */ |
1509 | struct { |
1510 | /* watermarks currently being used */ |
1511 | union { |
1512 | struct intel_pipe_wm ilk; |
1513 | struct vlv_wm_state vlv; |
1514 | struct g4x_wm_state g4x; |
1515 | } active; |
1516 | } wm; |
1517 | |
1518 | struct { |
1519 | struct mutex mutex; |
1520 | struct delayed_work work; |
1521 | enum drrs_refresh_rate refresh_rate; |
1522 | unsigned int frontbuffer_bits; |
1523 | unsigned int busy_frontbuffer_bits; |
1524 | enum transcoder cpu_transcoder; |
1525 | struct intel_link_m_n m_n, m2_n2; |
1526 | } drrs; |
1527 | |
1528 | int scanline_offset; |
1529 | |
1530 | struct { |
1531 | unsigned start_vbl_count; |
1532 | ktime_t start_vbl_time; |
1533 | int min_vbl, max_vbl; |
1534 | int scanline_start; |
1535 | #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE |
1536 | struct { |
1537 | u64 min; |
1538 | u64 max; |
1539 | u64 sum; |
1540 | unsigned int over; |
1541 | unsigned int times[17]; /* [1us, 16ms] */ |
1542 | } vbl; |
1543 | #endif |
1544 | } debug; |
1545 | |
1546 | /* scalers available on this crtc */ |
1547 | int num_scalers; |
1548 | |
1549 | /* for loading single buffered registers during vblank */ |
1550 | struct pm_qos_request vblank_pm_qos; |
1551 | |
1552 | #ifdef CONFIG_DEBUG_FS |
1553 | struct intel_pipe_crc pipe_crc; |
1554 | #endif |
1555 | }; |
1556 | |
1557 | struct intel_plane { |
1558 | struct drm_plane base; |
1559 | enum i9xx_plane_id i9xx_plane; |
1560 | enum plane_id id; |
1561 | enum pipe pipe; |
1562 | bool need_async_flip_disable_wa; |
1563 | u32 frontbuffer_bit; |
1564 | |
1565 | struct { |
1566 | u32 base, cntl, size; |
1567 | } cursor; |
1568 | |
1569 | struct intel_fbc *fbc; |
1570 | |
1571 | /* |
1572 | * NOTE: Do not place new plane state fields here (e.g., when adding |
1573 | * new plane properties). New runtime state should now be placed in |
1574 | * the intel_plane_state structure and accessed via plane_state. |
1575 | */ |
1576 | |
1577 | int (*min_width)(const struct drm_framebuffer *fb, |
1578 | int color_plane, |
1579 | unsigned int rotation); |
1580 | int (*max_width)(const struct drm_framebuffer *fb, |
1581 | int color_plane, |
1582 | unsigned int rotation); |
1583 | int (*max_height)(const struct drm_framebuffer *fb, |
1584 | int color_plane, |
1585 | unsigned int rotation); |
1586 | unsigned int (*max_stride)(struct intel_plane *plane, |
1587 | u32 pixel_format, u64 modifier, |
1588 | unsigned int rotation); |
1589 | /* Write all non-self arming plane registers */ |
1590 | void (*update_noarm)(struct intel_plane *plane, |
1591 | const struct intel_crtc_state *crtc_state, |
1592 | const struct intel_plane_state *plane_state); |
1593 | /* Write all self-arming plane registers */ |
1594 | void (*update_arm)(struct intel_plane *plane, |
1595 | const struct intel_crtc_state *crtc_state, |
1596 | const struct intel_plane_state *plane_state); |
1597 | /* Disable the plane, must arm */ |
1598 | void (*disable_arm)(struct intel_plane *plane, |
1599 | const struct intel_crtc_state *crtc_state); |
1600 | bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe); |
1601 | int (*check_plane)(struct intel_crtc_state *crtc_state, |
1602 | struct intel_plane_state *plane_state); |
1603 | int (*min_cdclk)(const struct intel_crtc_state *crtc_state, |
1604 | const struct intel_plane_state *plane_state); |
1605 | void (*async_flip)(struct intel_plane *plane, |
1606 | const struct intel_crtc_state *crtc_state, |
1607 | const struct intel_plane_state *plane_state, |
1608 | bool async_flip); |
1609 | void (*enable_flip_done)(struct intel_plane *plane); |
1610 | void (*disable_flip_done)(struct intel_plane *plane); |
1611 | }; |
1612 | |
1613 | struct intel_watermark_params { |
1614 | u16 fifo_size; |
1615 | u16 max_wm; |
1616 | u8 default_wm; |
1617 | u8 guard_size; |
1618 | u8 cacheline_size; |
1619 | }; |
1620 | |
1621 | #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) |
1622 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
1623 | #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi) |
1624 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
1625 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
1626 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
1627 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
1628 | #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi) |
1629 | #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL) |
1630 | |
1631 | struct intel_hdmi { |
1632 | i915_reg_t hdmi_reg; |
1633 | struct { |
1634 | enum drm_dp_dual_mode_type type; |
1635 | int max_tmds_clock; |
1636 | } dp_dual_mode; |
1637 | struct intel_connector *attached_connector; |
1638 | struct cec_notifier *cec_notifier; |
1639 | }; |
1640 | |
1641 | struct intel_dp_mst_encoder; |
1642 | |
1643 | struct intel_dp_compliance_data { |
1644 | unsigned long edid; |
1645 | u8 video_pattern; |
1646 | u16 hdisplay, vdisplay; |
1647 | u8 bpc; |
1648 | struct drm_dp_phy_test_params phytest; |
1649 | }; |
1650 | |
1651 | struct intel_dp_compliance { |
1652 | unsigned long test_type; |
1653 | struct intel_dp_compliance_data test_data; |
1654 | bool test_active; |
1655 | int test_link_rate; |
1656 | u8 test_lane_count; |
1657 | }; |
1658 | |
1659 | struct intel_dp_pcon_frl { |
1660 | bool is_trained; |
1661 | int trained_rate_gbps; |
1662 | }; |
1663 | |
1664 | struct intel_pps { |
1665 | int panel_power_up_delay; |
1666 | int panel_power_down_delay; |
1667 | int panel_power_cycle_delay; |
1668 | int backlight_on_delay; |
1669 | int backlight_off_delay; |
1670 | struct delayed_work panel_vdd_work; |
1671 | bool want_panel_vdd; |
1672 | bool initializing; |
1673 | unsigned long last_power_on; |
1674 | unsigned long last_backlight_off; |
1675 | ktime_t panel_power_off_time; |
1676 | intel_wakeref_t vdd_wakeref; |
1677 | |
1678 | union { |
1679 | /* |
1680 | * Pipe whose power sequencer is currently locked into |
1681 | * this port. Only relevant on VLV/CHV. |
1682 | */ |
1683 | enum pipe pps_pipe; |
1684 | |
1685 | /* |
1686 | * Power sequencer index. Only relevant on BXT+. |
1687 | */ |
1688 | int pps_idx; |
1689 | }; |
1690 | |
1691 | /* |
1692 | * Pipe currently driving the port. Used for preventing |
1693 | * the use of the PPS for any pipe currentrly driving |
1694 | * external DP as that will mess things up on VLV. |
1695 | */ |
1696 | enum pipe active_pipe; |
1697 | /* |
1698 | * Set if the sequencer may be reset due to a power transition, |
1699 | * requiring a reinitialization. Only relevant on BXT+. |
1700 | */ |
1701 | bool pps_reset; |
1702 | struct edp_power_seq pps_delays; |
1703 | struct edp_power_seq bios_pps_delays; |
1704 | }; |
1705 | |
1706 | struct intel_psr { |
1707 | /* Mutex for PSR state of the transcoder */ |
1708 | struct mutex lock; |
1709 | |
1710 | #define I915_PSR_DEBUG_MODE_MASK 0x0f |
1711 | #define I915_PSR_DEBUG_DEFAULT 0x00 |
1712 | #define I915_PSR_DEBUG_DISABLE 0x01 |
1713 | #define I915_PSR_DEBUG_ENABLE 0x02 |
1714 | #define I915_PSR_DEBUG_FORCE_PSR1 0x03 |
1715 | #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4 |
1716 | #define I915_PSR_DEBUG_IRQ 0x10 |
1717 | #define I915_PSR_DEBUG_SU_REGION_ET_DISABLE 0x20 |
1718 | |
1719 | u32 debug; |
1720 | bool sink_support; |
1721 | bool source_support; |
1722 | bool enabled; |
1723 | bool paused; |
1724 | enum pipe pipe; |
1725 | enum transcoder transcoder; |
1726 | bool active; |
1727 | struct work_struct work; |
1728 | unsigned int busy_frontbuffer_bits; |
1729 | bool sink_psr2_support; |
1730 | bool link_standby; |
1731 | bool psr2_enabled; |
1732 | bool psr2_sel_fetch_enabled; |
1733 | bool psr2_sel_fetch_cff_enabled; |
1734 | bool req_psr2_sdp_prior_scanline; |
1735 | u8 sink_sync_latency; |
1736 | |
1737 | struct { |
1738 | u8 io_wake_lines; |
1739 | u8 fast_wake_lines; |
1740 | |
1741 | /* LNL and beyond */ |
1742 | u8 check_entry_lines; |
1743 | } alpm_parameters; |
1744 | |
1745 | ktime_t last_entry_attempt; |
1746 | ktime_t last_exit; |
1747 | bool sink_not_reliable; |
1748 | bool irq_aux_error; |
1749 | u16 su_w_granularity; |
1750 | u16 su_y_granularity; |
1751 | bool source_panel_replay_support; |
1752 | bool sink_panel_replay_support; |
1753 | bool panel_replay_enabled; |
1754 | u32 dc3co_exitline; |
1755 | u32 dc3co_exit_delay; |
1756 | struct delayed_work dc3co_work; |
1757 | u8 entry_setup_frames; |
1758 | }; |
1759 | |
1760 | struct intel_dp { |
1761 | i915_reg_t output_reg; |
1762 | u32 DP; |
1763 | int link_rate; |
1764 | u8 lane_count; |
1765 | u8 sink_count; |
1766 | bool link_trained; |
1767 | bool reset_link_params; |
1768 | bool use_max_params; |
1769 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
1770 | u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
1771 | u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
1772 | u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; |
1773 | u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE]; |
1774 | u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE]; |
1775 | u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]; |
1776 | /* source rates */ |
1777 | int num_source_rates; |
1778 | const int *source_rates; |
1779 | /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */ |
1780 | int num_sink_rates; |
1781 | int sink_rates[DP_MAX_SUPPORTED_RATES]; |
1782 | bool use_rate_select; |
1783 | /* Max sink lane count as reported by DP_MAX_LANE_COUNT */ |
1784 | int max_sink_lane_count; |
1785 | /* intersection of source and sink rates */ |
1786 | int num_common_rates; |
1787 | int common_rates[DP_MAX_SUPPORTED_RATES]; |
1788 | /* Max lane count for the current link */ |
1789 | int max_link_lane_count; |
1790 | /* Max rate for the current link */ |
1791 | int max_link_rate; |
1792 | int mso_link_count; |
1793 | int mso_pixel_overlap; |
1794 | /* sink or branch descriptor */ |
1795 | struct drm_dp_desc desc; |
1796 | struct drm_dp_aux aux; |
1797 | u32 aux_busy_last_status; |
1798 | u8 train_set[4]; |
1799 | |
1800 | struct intel_pps pps; |
1801 | |
1802 | bool is_mst; |
1803 | int active_mst_links; |
1804 | |
1805 | /* connector directly attached - won't be use for modeset in mst world */ |
1806 | struct intel_connector *attached_connector; |
1807 | |
1808 | struct drm_dp_tunnel *tunnel; |
1809 | bool tunnel_suspended:1; |
1810 | |
1811 | /* mst connector list */ |
1812 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; |
1813 | struct drm_dp_mst_topology_mgr mst_mgr; |
1814 | |
1815 | u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
1816 | /* |
1817 | * This function returns the value we have to program the AUX_CTL |
1818 | * register with to kick off an AUX transaction. |
1819 | */ |
1820 | u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes, |
1821 | u32 aux_clock_divider); |
1822 | |
1823 | i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); |
1824 | i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); |
1825 | |
1826 | /* This is called before a link training is starterd */ |
1827 | void (*prepare_link_retrain)(struct intel_dp *intel_dp, |
1828 | const struct intel_crtc_state *crtc_state); |
1829 | void (*set_link_train)(struct intel_dp *intel_dp, |
1830 | const struct intel_crtc_state *crtc_state, |
1831 | u8 dp_train_pat); |
1832 | void (*set_idle_link_train)(struct intel_dp *intel_dp, |
1833 | const struct intel_crtc_state *crtc_state); |
1834 | |
1835 | u8 (*preemph_max)(struct intel_dp *intel_dp); |
1836 | u8 (*voltage_max)(struct intel_dp *intel_dp, |
1837 | const struct intel_crtc_state *crtc_state); |
1838 | |
1839 | /* Displayport compliance testing */ |
1840 | struct intel_dp_compliance compliance; |
1841 | |
1842 | /* Downstream facing port caps */ |
1843 | struct { |
1844 | int min_tmds_clock, max_tmds_clock; |
1845 | int max_dotclock; |
1846 | int pcon_max_frl_bw; |
1847 | u8 max_bpc; |
1848 | bool ycbcr_444_to_420; |
1849 | bool ycbcr420_passthrough; |
1850 | bool rgb_to_ycbcr; |
1851 | } dfp; |
1852 | |
1853 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1854 | struct pm_qos_request pm_qos; |
1855 | |
1856 | /* Display stream compression testing */ |
1857 | bool force_dsc_en; |
1858 | int force_dsc_output_format; |
1859 | bool force_dsc_fractional_bpp_en; |
1860 | int force_dsc_bpc; |
1861 | |
1862 | bool hobl_failed; |
1863 | bool hobl_active; |
1864 | |
1865 | struct intel_dp_pcon_frl frl; |
1866 | |
1867 | struct intel_psr psr; |
1868 | |
1869 | /* When we last wrote the OUI for eDP */ |
1870 | unsigned long last_oui_write; |
1871 | |
1872 | bool colorimetry_support; |
1873 | }; |
1874 | |
1875 | enum lspcon_vendor { |
1876 | LSPCON_VENDOR_MCA, |
1877 | LSPCON_VENDOR_PARADE |
1878 | }; |
1879 | |
1880 | struct intel_lspcon { |
1881 | bool active; |
1882 | bool hdr_supported; |
1883 | enum drm_lspcon_mode mode; |
1884 | enum lspcon_vendor vendor; |
1885 | }; |
1886 | |
1887 | struct intel_digital_port { |
1888 | struct intel_encoder base; |
1889 | u32 saved_port_bits; |
1890 | struct intel_dp dp; |
1891 | struct intel_hdmi hdmi; |
1892 | struct intel_lspcon lspcon; |
1893 | enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); |
1894 | bool release_cl2_override; |
1895 | u8 max_lanes; |
1896 | /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */ |
1897 | enum aux_ch aux_ch; |
1898 | enum intel_display_power_domain ddi_io_power_domain; |
1899 | intel_wakeref_t ddi_io_wakeref; |
1900 | intel_wakeref_t aux_wakeref; |
1901 | |
1902 | struct intel_tc_port *tc; |
1903 | |
1904 | /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */ |
1905 | struct mutex hdcp_mutex; |
1906 | /* the number of pipes using HDCP signalling out of this port */ |
1907 | unsigned int num_hdcp_streams; |
1908 | /* port HDCP auth status */ |
1909 | bool hdcp_auth_status; |
1910 | /* HDCP port data need to pass to security f/w */ |
1911 | struct hdcp_port_data hdcp_port_data; |
1912 | /* Whether the MST topology supports HDCP Type 1 Content */ |
1913 | bool hdcp_mst_type1_capable; |
1914 | |
1915 | void (*write_infoframe)(struct intel_encoder *encoder, |
1916 | const struct intel_crtc_state *crtc_state, |
1917 | unsigned int type, |
1918 | const void *frame, ssize_t len); |
1919 | void (*read_infoframe)(struct intel_encoder *encoder, |
1920 | const struct intel_crtc_state *crtc_state, |
1921 | unsigned int type, |
1922 | void *frame, ssize_t len); |
1923 | void (*set_infoframes)(struct intel_encoder *encoder, |
1924 | bool enable, |
1925 | const struct intel_crtc_state *crtc_state, |
1926 | const struct drm_connector_state *conn_state); |
1927 | u32 (*infoframes_enabled)(struct intel_encoder *encoder, |
1928 | const struct intel_crtc_state *pipe_config); |
1929 | bool (*connected)(struct intel_encoder *encoder); |
1930 | |
1931 | void (*lock)(struct intel_digital_port *dig_port); |
1932 | void (*unlock)(struct intel_digital_port *dig_port); |
1933 | }; |
1934 | |
1935 | struct intel_dp_mst_encoder { |
1936 | struct intel_encoder base; |
1937 | enum pipe pipe; |
1938 | struct intel_digital_port *primary; |
1939 | struct intel_connector *connector; |
1940 | }; |
1941 | |
1942 | static inline struct intel_encoder * |
1943 | intel_attached_encoder(struct intel_connector *connector) |
1944 | { |
1945 | return connector->encoder; |
1946 | } |
1947 | |
1948 | static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder) |
1949 | { |
1950 | switch (encoder->type) { |
1951 | case INTEL_OUTPUT_DDI: |
1952 | case INTEL_OUTPUT_DP: |
1953 | case INTEL_OUTPUT_EDP: |
1954 | case INTEL_OUTPUT_HDMI: |
1955 | return true; |
1956 | default: |
1957 | return false; |
1958 | } |
1959 | } |
1960 | |
1961 | static inline bool intel_encoder_is_mst(struct intel_encoder *encoder) |
1962 | { |
1963 | return encoder->type == INTEL_OUTPUT_DP_MST; |
1964 | } |
1965 | |
1966 | static inline struct intel_dp_mst_encoder * |
1967 | enc_to_mst(struct intel_encoder *encoder) |
1968 | { |
1969 | return container_of(&encoder->base, struct intel_dp_mst_encoder, |
1970 | base.base); |
1971 | } |
1972 | |
1973 | static inline struct intel_digital_port * |
1974 | enc_to_dig_port(struct intel_encoder *encoder) |
1975 | { |
1976 | struct intel_encoder *intel_encoder = encoder; |
1977 | |
1978 | if (intel_encoder_is_dig_port(encoder: intel_encoder)) |
1979 | return container_of(&encoder->base, struct intel_digital_port, |
1980 | base.base); |
1981 | else if (intel_encoder_is_mst(encoder: intel_encoder)) |
1982 | return enc_to_mst(encoder)->primary; |
1983 | else |
1984 | return NULL; |
1985 | } |
1986 | |
1987 | static inline struct intel_digital_port * |
1988 | intel_attached_dig_port(struct intel_connector *connector) |
1989 | { |
1990 | return enc_to_dig_port(encoder: intel_attached_encoder(connector)); |
1991 | } |
1992 | |
1993 | static inline struct intel_hdmi * |
1994 | enc_to_intel_hdmi(struct intel_encoder *encoder) |
1995 | { |
1996 | return &enc_to_dig_port(encoder)->hdmi; |
1997 | } |
1998 | |
1999 | static inline struct intel_hdmi * |
2000 | intel_attached_hdmi(struct intel_connector *connector) |
2001 | { |
2002 | return enc_to_intel_hdmi(encoder: intel_attached_encoder(connector)); |
2003 | } |
2004 | |
2005 | static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder) |
2006 | { |
2007 | return &enc_to_dig_port(encoder)->dp; |
2008 | } |
2009 | |
2010 | static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector) |
2011 | { |
2012 | return enc_to_intel_dp(encoder: intel_attached_encoder(connector)); |
2013 | } |
2014 | |
2015 | static inline bool intel_encoder_is_dp(struct intel_encoder *encoder) |
2016 | { |
2017 | switch (encoder->type) { |
2018 | case INTEL_OUTPUT_DP: |
2019 | case INTEL_OUTPUT_EDP: |
2020 | return true; |
2021 | case INTEL_OUTPUT_DDI: |
2022 | /* Skip pure HDMI/DVI DDI encoders */ |
2023 | return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg); |
2024 | default: |
2025 | return false; |
2026 | } |
2027 | } |
2028 | |
2029 | static inline struct intel_lspcon * |
2030 | enc_to_intel_lspcon(struct intel_encoder *encoder) |
2031 | { |
2032 | return &enc_to_dig_port(encoder)->lspcon; |
2033 | } |
2034 | |
2035 | static inline struct intel_digital_port * |
2036 | dp_to_dig_port(struct intel_dp *intel_dp) |
2037 | { |
2038 | return container_of(intel_dp, struct intel_digital_port, dp); |
2039 | } |
2040 | |
2041 | static inline struct intel_lspcon * |
2042 | dp_to_lspcon(struct intel_dp *intel_dp) |
2043 | { |
2044 | return &dp_to_dig_port(intel_dp)->lspcon; |
2045 | } |
2046 | |
2047 | #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev) |
2048 | |
2049 | static inline struct intel_digital_port * |
2050 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) |
2051 | { |
2052 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); |
2053 | } |
2054 | |
2055 | static inline struct intel_plane_state * |
2056 | intel_atomic_get_plane_state(struct intel_atomic_state *state, |
2057 | struct intel_plane *plane) |
2058 | { |
2059 | struct drm_plane_state *ret = |
2060 | drm_atomic_get_plane_state(state: &state->base, plane: &plane->base); |
2061 | |
2062 | if (IS_ERR(ptr: ret)) |
2063 | return ERR_CAST(ptr: ret); |
2064 | |
2065 | return to_intel_plane_state(ret); |
2066 | } |
2067 | |
2068 | static inline struct intel_plane_state * |
2069 | intel_atomic_get_old_plane_state(struct intel_atomic_state *state, |
2070 | struct intel_plane *plane) |
2071 | { |
2072 | return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base, |
2073 | &plane->base)); |
2074 | } |
2075 | |
2076 | static inline struct intel_plane_state * |
2077 | intel_atomic_get_new_plane_state(struct intel_atomic_state *state, |
2078 | struct intel_plane *plane) |
2079 | { |
2080 | return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base, |
2081 | &plane->base)); |
2082 | } |
2083 | |
2084 | static inline struct intel_crtc_state * |
2085 | intel_atomic_get_old_crtc_state(struct intel_atomic_state *state, |
2086 | struct intel_crtc *crtc) |
2087 | { |
2088 | return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base, |
2089 | &crtc->base)); |
2090 | } |
2091 | |
2092 | static inline struct intel_crtc_state * |
2093 | intel_atomic_get_new_crtc_state(struct intel_atomic_state *state, |
2094 | struct intel_crtc *crtc) |
2095 | { |
2096 | return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base, |
2097 | &crtc->base)); |
2098 | } |
2099 | |
2100 | static inline struct intel_digital_connector_state * |
2101 | intel_atomic_get_new_connector_state(struct intel_atomic_state *state, |
2102 | struct intel_connector *connector) |
2103 | { |
2104 | return to_intel_digital_connector_state( |
2105 | drm_atomic_get_new_connector_state(&state->base, |
2106 | &connector->base)); |
2107 | } |
2108 | |
2109 | static inline struct intel_digital_connector_state * |
2110 | intel_atomic_get_old_connector_state(struct intel_atomic_state *state, |
2111 | struct intel_connector *connector) |
2112 | { |
2113 | return to_intel_digital_connector_state( |
2114 | drm_atomic_get_old_connector_state(&state->base, |
2115 | &connector->base)); |
2116 | } |
2117 | |
2118 | /* intel_display.c */ |
2119 | static inline bool |
2120 | intel_crtc_has_type(const struct intel_crtc_state *crtc_state, |
2121 | enum intel_output_type type) |
2122 | { |
2123 | return crtc_state->output_types & BIT(type); |
2124 | } |
2125 | |
2126 | static inline bool |
2127 | intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) |
2128 | { |
2129 | return crtc_state->output_types & |
2130 | (BIT(INTEL_OUTPUT_DP) | |
2131 | BIT(INTEL_OUTPUT_DP_MST) | |
2132 | BIT(INTEL_OUTPUT_EDP)); |
2133 | } |
2134 | |
2135 | static inline bool |
2136 | intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state) |
2137 | { |
2138 | return drm_atomic_crtc_needs_modeset(state: &crtc_state->uapi); |
2139 | } |
2140 | |
2141 | static inline bool |
2142 | intel_crtc_needs_fastset(const struct intel_crtc_state *crtc_state) |
2143 | { |
2144 | return crtc_state->update_pipe; |
2145 | } |
2146 | |
2147 | static inline bool |
2148 | intel_crtc_needs_color_update(const struct intel_crtc_state *crtc_state) |
2149 | { |
2150 | return crtc_state->uapi.color_mgmt_changed || |
2151 | intel_crtc_needs_fastset(crtc_state) || |
2152 | intel_crtc_needs_modeset(crtc_state); |
2153 | } |
2154 | |
2155 | static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state) |
2156 | { |
2157 | return i915_ggtt_offset(vma: plane_state->ggtt_vma); |
2158 | } |
2159 | |
2160 | static inline struct intel_frontbuffer * |
2161 | to_intel_frontbuffer(struct drm_framebuffer *fb) |
2162 | { |
2163 | return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; |
2164 | } |
2165 | |
2166 | static inline int to_bpp_int(int bpp_x16) |
2167 | { |
2168 | return bpp_x16 >> 4; |
2169 | } |
2170 | |
2171 | static inline int to_bpp_frac(int bpp_x16) |
2172 | { |
2173 | return bpp_x16 & 0xf; |
2174 | } |
2175 | |
2176 | #define BPP_X16_FMT "%d.%04d" |
2177 | #define BPP_X16_ARGS(bpp_x16) to_bpp_int(bpp_x16), (to_bpp_frac(bpp_x16) * 625) |
2178 | |
2179 | static inline int to_bpp_int_roundup(int bpp_x16) |
2180 | { |
2181 | return (bpp_x16 + 0xf) >> 4; |
2182 | } |
2183 | |
2184 | static inline int to_bpp_x16(int bpp) |
2185 | { |
2186 | return bpp << 4; |
2187 | } |
2188 | |
2189 | #endif /* __INTEL_DISPLAY_TYPES_H__ */ |
2190 | |