1	/*
2	* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3	* Copyright (c) 2007-2008 Intel Corporation
4	* Jesse Barnes <jesse.barnes@intel.com>
5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:
12	*
13	* The above copyright notice and this permission notice (including the next
14	* paragraph) shall be included in all copies or substantial portions of the
15	* Software.
16	*
17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23	* IN THE SOFTWARE.
24	*/
25
26	#ifndef __INTEL_DISPLAY_TYPES_H__
27	#define __INTEL_DISPLAY_TYPES_H__
28
29	#include <linux/pm_qos.h>
30	#include <linux/pwm.h>
31
32	#include <drm/display/drm_dp_dual_mode_helper.h>
33	#include <drm/display/drm_dp_mst_helper.h>
34	#include <drm/display/drm_dp_tunnel.h>
35	#include <drm/display/drm_dsc.h>
36	#include <drm/drm_atomic.h>
37	#include <drm/drm_crtc.h>
38	#include <drm/drm_encoder.h>
39	#include <drm/drm_framebuffer.h>
40	#include <drm/drm_rect.h>
41	#include <drm/drm_vblank_work.h>
42	#include <drm/intel/i915_hdcp_interface.h>
43	#include <uapi/drm/i915_drm.h>
44
45	#include "i915_gtt_view_types.h"
46	#include "intel_bios.h"
47	#include "intel_display.h"
48	#include "intel_display_conversion.h"
49	#include "intel_display_limits.h"
50	#include "intel_display_power.h"
51	#include "intel_dpll_mgr.h"
52	#include "intel_wm_types.h"
53
54	struct cec_notifier;
55	struct drm_printer;
56	struct __intel_global_objs_state;
57	struct intel_connector;
58	struct intel_ddi_buf_trans;
59	struct intel_fbc;
60	struct intel_hdcp_shim;
61	struct intel_tc_port;
62
63	/*
64	* Display related stuff
65	*/
66
67	/* these are outputs from the chip - integrated only
68	external chips are via DVO or SDVO output */
69	enum intel_output_type {
70	INTEL_OUTPUT_UNUSED = 0,
71	INTEL_OUTPUT_ANALOG = 1,
72	INTEL_OUTPUT_DVO = 2,
73	INTEL_OUTPUT_SDVO = 3,
74	INTEL_OUTPUT_LVDS = 4,
75	INTEL_OUTPUT_TVOUT = 5,
76	INTEL_OUTPUT_HDMI = 6,
77	INTEL_OUTPUT_DP = 7,
78	INTEL_OUTPUT_EDP = 8,
79	INTEL_OUTPUT_DSI = 9,
80	INTEL_OUTPUT_DDI = 10,
81	INTEL_OUTPUT_DP_MST = 11,
82	};
83
84	enum hdmi_force_audio {
85	HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
86	HDMI_AUDIO_OFF, /* force turn off HDMI audio */
87	HDMI_AUDIO_AUTO, /* trust EDID */
88	HDMI_AUDIO_ON, /* force turn on HDMI audio */
89	};
90
91	/* "Broadcast RGB" property */
92	enum intel_broadcast_rgb {
93	INTEL_BROADCAST_RGB_AUTO,
94	INTEL_BROADCAST_RGB_FULL,
95	INTEL_BROADCAST_RGB_LIMITED,
96	};
97
98	struct intel_fb_view {
99	/*
100	* The remap information used in the remapped and rotated views to
101	* create the DMA scatter-gather list for each FB color plane. This sg
102	* list is created along with the view type (gtt.type) specific
103	* i915_vma object and contains the list of FB object pages (reordered
104	* in the rotated view) that are visible in the view.
105	* In the normal view the FB object's backing store sg list is used
106	* directly and hence the remap information here is not used.
107	*/
108	struct i915_gtt_view gtt;
109
110	/*
111	* The GTT view (gtt.type) specific information for each FB color
112	* plane. In the normal GTT view all formats (up to 4 color planes),
113	* in the rotated and remapped GTT view all no-CCS formats (up to 2
114	* color planes) are supported.
115	*
116	* The view information shared by all FB color planes in the FB,
117	* like dst x/y and src/dst width, is stored separately in
118	* intel_plane_state.
119	*/
120	struct i915_color_plane_view {
121	u32 offset;
122	unsigned int x, y;
123	/*
124	* Plane stride in:
125	* bytes for 0/180 degree rotation
126	* pixels for 90/270 degree rotation
127	*/
128	unsigned int mapping_stride;
129	unsigned int scanout_stride;
130	} color_plane[4];
131	};
132
133	struct intel_framebuffer {
134	struct drm_framebuffer base;
135	struct intel_frontbuffer *frontbuffer;
136
137	/* Params to remap the FB pages and program the plane registers in each view. */
138	struct intel_fb_view normal_view;
139	union {
140	struct intel_fb_view rotated_view;
141	struct intel_fb_view remapped_view;
142	};
143
144	struct i915_address_space *dpt_vm;
145
146	unsigned int min_alignment;
147	unsigned int vtd_guard;
148	};
149
150	enum intel_hotplug_state {
151	INTEL_HOTPLUG_UNCHANGED,
152	INTEL_HOTPLUG_CHANGED,
153	INTEL_HOTPLUG_RETRY,
154	};
155
156	struct intel_encoder {
157	struct drm_encoder base;
158
159	enum intel_output_type type;
160	enum port port;
161	u16 cloneable;
162	u8 pipe_mask;
163
164	/* Check and recover a bad link state. */
165	struct delayed_work link_check_work;
166	void (*link_check)(struct intel_encoder *encoder);
167
168	enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
169	struct intel_connector *connector);
170	enum intel_output_type (*compute_output_type)(struct intel_encoder *,
171	struct intel_crtc_state *,
172	struct drm_connector_state *);
173	int (*compute_config)(struct intel_encoder *,
174	struct intel_crtc_state *,
175	struct drm_connector_state *);
176	int (*compute_config_late)(struct intel_encoder *,
177	struct intel_crtc_state *,
178	struct drm_connector_state *);
179	void (*pre_pll_enable)(struct intel_atomic_state *,
180	struct intel_encoder *,
181	const struct intel_crtc_state *,
182	const struct drm_connector_state *);
183	void (*pre_enable)(struct intel_atomic_state *,
184	struct intel_encoder *,
185	const struct intel_crtc_state *,
186	const struct drm_connector_state *);
187	void (*enable)(struct intel_atomic_state *,
188	struct intel_encoder *,
189	const struct intel_crtc_state *,
190	const struct drm_connector_state *);
191	void (*disable)(struct intel_atomic_state *,
192	struct intel_encoder *,
193	const struct intel_crtc_state *,
194	const struct drm_connector_state *);
195	void (*post_disable)(struct intel_atomic_state *,
196	struct intel_encoder *,
197	const struct intel_crtc_state *,
198	const struct drm_connector_state *);
199	void (*post_pll_disable)(struct intel_atomic_state *,
200	struct intel_encoder *,
201	const struct intel_crtc_state *,
202	const struct drm_connector_state *);
203	void (*update_pipe)(struct intel_atomic_state *,
204	struct intel_encoder *,
205	const struct intel_crtc_state *,
206	const struct drm_connector_state *);
207	void (*audio_enable)(struct intel_encoder *encoder,
208	const struct intel_crtc_state *crtc_state,
209	const struct drm_connector_state *conn_state);
210	void (*audio_disable)(struct intel_encoder *encoder,
211	const struct intel_crtc_state *old_crtc_state,
212	const struct drm_connector_state *old_conn_state);
213	/* Read out the current hw state of this connector, returning true if
214	* the encoder is active. If the encoder is enabled it also set the pipe
215	* it is connected to in the pipe parameter. */
216	bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
217	/* Reconstructs the equivalent mode flags for the current hardware
218	* state. This must be called _after_ display->get_pipe_config has
219	* pre-filled the pipe config. Note that intel_encoder->base.crtc must
220	* be set correctly before calling this function. */
221	void (*get_config)(struct intel_encoder *,
222	struct intel_crtc_state *pipe_config);
223
224	/*
225	* Optional hook called during init/resume to sync any state
226	* stored in the encoder (eg. DP link parameters) wrt. the HW state.
227	*/
228	void (*sync_state)(struct intel_encoder *encoder,
229	const struct intel_crtc_state *crtc_state);
230
231	/*
232	* Optional hook, returning true if this encoder allows a fastset
233	* during the initial commit, false otherwise.
234	*/
235	bool (*initial_fastset_check)(struct intel_encoder *encoder,
236	struct intel_crtc_state *crtc_state);
237
238	/*
239	* Acquires the power domains needed for an active encoder during
240	* hardware state readout.
241	*/
242	void (*get_power_domains)(struct intel_encoder *encoder,
243	struct intel_crtc_state *crtc_state);
244	/*
245	* Called during system suspend after all pending requests for the
246	* encoder are flushed (for example for DP AUX transactions) and
247	* device interrupts are disabled.
248	* All modeset locks are held while the hook is called.
249	*/
250	void (*suspend)(struct intel_encoder *);
251	/*
252	* Called without the modeset locks held after the suspend() hook for
253	* all encoders have been called.
254	*/
255	void (*suspend_complete)(struct intel_encoder *encoder);
256	/*
257	* Called during system reboot/shutdown after all the
258	* encoders have been disabled and suspended.
259	* All modeset locks are held while the hook is called.
260	*/
261	void (*shutdown)(struct intel_encoder *encoder);
262	/*
263	* Called without the modeset locks held after the shutdown() hook for
264	* all encoders have been called.
265	*/
266	void (*shutdown_complete)(struct intel_encoder *encoder);
267	/*
268	* Enable/disable the clock to the port.
269	*/
270	void (*enable_clock)(struct intel_encoder *encoder,
271	const struct intel_crtc_state *crtc_state);
272	void (*disable_clock)(struct intel_encoder *encoder);
273	/*
274	* Returns whether the port clock is enabled or not.
275	*/
276	bool (*is_clock_enabled)(struct intel_encoder *encoder);
277	/*
278	* Returns the PLL type the port uses.
279	*/
280	enum icl_port_dpll_id (*port_pll_type)(struct intel_encoder *encoder,
281	const struct intel_crtc_state *crtc_state);
282	const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder,
283	const struct intel_crtc_state *crtc_state,
284	int *n_entries);
285	void (*set_signal_levels)(struct intel_encoder *encoder,
286	const struct intel_crtc_state *crtc_state);
287
288	enum hpd_pin hpd_pin;
289	enum intel_display_power_domain power_domain;
290
291	/* VBT information for this encoder (may be NULL for older platforms) */
292	const struct intel_bios_encoder_data *devdata;
293	};
294
295	struct intel_panel_bl_funcs {
296	/* Connector and platform specific backlight functions */
297	int (*setup)(struct intel_connector *connector, enum pipe pipe);
298	u32 (*get)(struct intel_connector *connector, enum pipe pipe);
299	void (*set)(const struct drm_connector_state *conn_state, u32 level);
300	void (*disable)(const struct drm_connector_state *conn_state, u32 level);
301	void (*enable)(const struct intel_crtc_state *crtc_state,
302	const struct drm_connector_state *conn_state, u32 level);
303	u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
304	};
305
306	/* in 100us units */
307	struct intel_pps_delays {
308	u16 power_up; /* eDP: T1+T3, LVDS: T1+T2 */
309	u16 backlight_on; /* eDP: T8, LVDS: T5 */
310	u16 backlight_off; /* eDP: T9, LVDS: T6/TX */
311	u16 power_down; /* eDP: T10, LVDS: T3 */
312	u16 power_cycle; /* eDP: T11+T12, LVDS: T7+T4 */
313	};
314
315	enum drrs_type {
316	DRRS_TYPE_NONE,
317	DRRS_TYPE_STATIC,
318	DRRS_TYPE_SEAMLESS,
319	};
320
321	struct intel_vbt_panel_data {
322	struct drm_display_mode *lfp_vbt_mode; /* if any */
323	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
324
325	/* Feature bits */
326	int panel_type;
327	unsigned int lvds_dither:1;
328	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
329
330	bool vrr;
331
332	u8 seamless_drrs_min_refresh_rate;
333	enum drrs_type drrs_type;
334
335	struct {
336	int max_link_rate;
337	int rate;
338	int lanes;
339	int preemphasis;
340	int vswing;
341	int bpp;
342	struct intel_pps_delays pps;
343	u8 drrs_msa_timing_delay;
344	bool low_vswing;
345	bool hobl;
346	bool dsc_disable;
347	} edp;
348
349	struct {
350	bool enable;
351	bool full_link;
352	bool require_aux_wakeup;
353	int idle_frames;
354	int tp1_wakeup_time_us;
355	int tp2_tp3_wakeup_time_us;
356	int psr2_tp2_tp3_wakeup_time_us;
357	} psr;
358
359	struct {
360	u16 pwm_freq_hz;
361	u16 brightness_precision_bits;
362	u16 hdr_dpcd_refresh_timeout;
363	bool present;
364	bool active_low_pwm;
365	u8 min_brightness; /* min_brightness/255 of max */
366	s8 controller; /* brightness controller number */
367	enum intel_backlight_type type;
368	} backlight;
369
370	/* MIPI DSI */
371	struct {
372	u16 panel_id;
373	struct mipi_config *config;
374	struct mipi_pps_data *pps;
375	u16 bl_ports;
376	u16 cabc_ports;
377	u8 seq_version;
378	u32 size;
379	u8 *data;
380	const u8 *sequence[MIPI_SEQ_MAX];
381	u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
382	enum drm_panel_orientation orientation;
383	} dsi;
384	};
385
386	struct intel_panel {
387	/* Fixed EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
388	const struct drm_edid *fixed_edid;
389
390	struct list_head fixed_modes;
391
392	/* backlight */
393	struct {
394	bool present;
395	u32 level;
396	u32 min;
397	u32 max;
398	bool enabled;
399	bool combination_mode; /* gen 2/4 only */
400	bool active_low_pwm;
401	bool alternate_pwm_increment; /* lpt+ */
402
403	/* PWM chip */
404	u32 pwm_level_min;
405	u32 pwm_level_max;
406	bool pwm_enabled;
407	bool util_pin_active_low; /* bxt+ */
408	u8 controller; /* bxt+ only */
409	struct pwm_device *pwm;
410	struct pwm_state pwm_state;
411
412	/* DPCD backlight */
413	union {
414	struct {
415	struct drm_edp_backlight_info info;
416	bool luminance_control_support;
417	} vesa;
418	struct {
419	bool sdr_uses_aux;
420	bool supports_2084_decode;
421	bool supports_2020_gamut;
422	bool supports_segmented_backlight;
423	bool supports_sdp_colorimetry;
424	bool supports_tone_mapping;
425	} intel_cap;
426	} edp;
427
428	struct backlight_device *device;
429
430	const struct intel_panel_bl_funcs *funcs;
431	const struct intel_panel_bl_funcs *pwm_funcs;
432	void (*power)(struct intel_connector *, bool enable);
433	} backlight;
434
435	struct intel_vbt_panel_data vbt;
436	};
437
438	struct intel_digital_port;
439
440	struct intel_hdcp {
441	const struct intel_hdcp_shim *shim;
442	/* Mutex for hdcp state of the connector */
443	struct mutex mutex;
444	u64 value;
445	struct delayed_work check_work;
446	struct work_struct prop_work;
447
448	/* HDCP1.4 Encryption status */
449	bool hdcp_encrypted;
450
451	/* HDCP2.2 related definitions */
452	/* Flag indicates whether this connector supports HDCP2.2 or not. */
453	bool hdcp2_supported;
454
455	/* HDCP2.2 Encryption status */
456	bool hdcp2_encrypted;
457
458	/*
459	* Content Stream Type defined by content owner. TYPE0(0x0) content can
460	* flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
461	* content can flow only through a link protected by HDCP2.2.
462	*/
463	u8 content_type;
464
465	bool is_paired;
466	bool is_repeater;
467
468	/*
469	* Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
470	* Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
471	* When it rolls over re-auth has to be triggered.
472	*/
473	u32 seq_num_v;
474
475	/*
476	* Count of RepeaterAuth_Stream_Manage msg propagated.
477	* Initialized to 0 on AKE_INIT. Incremented after every successful
478	* transmission of RepeaterAuth_Stream_Manage message. When it rolls
479	* over re-Auth has to be triggered.
480	*/
481	u32 seq_num_m;
482
483	/*
484	* Work queue to signal the CP_IRQ. Used for the waiters to read the
485	* available information from HDCP DP sink.
486	*/
487	wait_queue_head_t cp_irq_queue;
488	atomic_t cp_irq_count;
489	int cp_irq_count_cached;
490
491	/*
492	* HDCP register access for gen12+ need the transcoder associated.
493	* Transcoder attached to the connector could be changed at modeset.
494	* Hence caching the transcoder here.
495	*/
496	enum transcoder cpu_transcoder;
497	/* Only used for DP MST stream encryption */
498	enum transcoder stream_transcoder;
499	/* Used to force HDCP 1.4 bypassing HDCP 2.x */
500	bool force_hdcp14;
501	};
502
503	struct intel_connector {
504	struct drm_connector base;
505	/*
506	* The fixed encoder this connector is connected to.
507	*/
508	struct intel_encoder *encoder;
509
510	/* ACPI device id for ACPI and driver cooperation */
511	u32 acpi_device_id;
512
513	/* Reads out the current hw, returning true if the connector is enabled
514	* and active (i.e. dpms ON state). */
515	bool (*get_hw_state)(struct intel_connector *);
516
517	/*
518	* Optional hook called during init/resume to sync any state
519	* stored in the connector (eg. DSC state) wrt. the HW state.
520	*/
521	void (*sync_state)(struct intel_connector *connector,
522	const struct intel_crtc_state *crtc_state);
523
524	/* Panel info for eDP and LVDS */
525	struct intel_panel panel;
526
527	/* Cached EDID for detect. */
528	const struct drm_edid *detect_edid;
529
530	/* Number of times hotplug detection was tried after an HPD interrupt */
531	int hotplug_retries;
532
533	/* since POLL and HPD connectors may use the same HPD line keep the native
534	state of connector->polled in case hotplug storm detection changes it */
535	u8 polled;
536
537	int force_joined_pipes;
538
539	struct {
540	struct drm_dp_aux *dsc_decompression_aux;
541	u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
542	u8 fec_capability;
543
544	u8 dsc_hblank_expansion_quirk:1;
545	u8 dsc_decompression_enabled:1;
546	} dp;
547
548	struct {
549	struct drm_dp_mst_port *port;
550	struct intel_dp *dp;
551	} mst;
552
553	/* Work struct to schedule a uevent on link train failure */
554	struct work_struct modeset_retry_work;
555
556	struct intel_hdcp hdcp;
557	};
558
559	struct intel_digital_connector_state {
560	struct drm_connector_state base;
561
562	enum hdmi_force_audio force_audio;
563	int broadcast_rgb;
564	};
565
566	#define to_intel_digital_connector_state(conn_state) \
567	container_of_const((conn_state), struct intel_digital_connector_state, base)
568
569	struct dpll {
570	/* given values */
571	int n;
572	int m1, m2;
573	int p1, p2;
574	/* derived values */
575	int dot;
576	int vco;
577	int m;
578	int p;
579	};
580
581	struct intel_atomic_state {
582	struct drm_atomic_state base;
583
584	struct ref_tracker *wakeref;
585
586	struct __intel_global_objs_state *global_objs;
587	int num_global_objs;
588
589	/* Internal commit, as opposed to userspace/client initiated one */
590	bool internal;
591
592	bool dpll_set, modeset;
593
594	struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
595
596	struct intel_dp_tunnel_inherited_state *inherited_dp_tunnels;
597
598	/*
599	* Current watermarks can't be trusted during hardware readout, so
600	* don't bother calculating intermediate watermarks.
601	*/
602	bool skip_intermediate_wm;
603
604	bool rps_interactive;
605
606	struct work_struct cleanup_work;
607	};
608
609	struct intel_plane_state {
610	struct drm_plane_state uapi;
611
612	/*
613	* actual hardware state, the state we program to the hardware.
614	* The following members are used to verify the hardware state:
615	* During initial hw readout, they need to be copied from uapi.
616	*/
617	struct {
618	struct drm_crtc *crtc;
619	struct drm_framebuffer *fb;
620
621	u16 alpha;
622	u16 pixel_blend_mode;
623	unsigned int rotation;
624	enum drm_color_encoding color_encoding;
625	enum drm_color_range color_range;
626	enum drm_scaling_filter scaling_filter;
627	} hw;
628
629	struct i915_vma *ggtt_vma;
630	struct i915_vma *dpt_vma;
631	unsigned long flags;
632	#define PLANE_HAS_FENCE BIT(0)
633
634	struct intel_fb_view view;
635	u32 phys_dma_addr; /* for cursor_needs_physical */
636
637	/* for legacy cursor fb unpin */
638	struct drm_vblank_work unpin_work;
639
640	/* Plane pxp decryption state */
641	bool decrypt;
642
643	/* Plane state to display black pixels when pxp is borked */
644	bool force_black;
645
646	/* Acting as Y plane for another UV plane? */
647	bool is_y_plane;
648
649	/* plane control register */
650	u32 ctl;
651
652	/* plane color control register */
653	u32 color_ctl;
654
655	/* chroma upsampler control register */
656	u32 cus_ctl;
657
658	/*
659	* scaler_id
660	* = -1 : not using a scaler
661	* >= 0 : using a scalers
662	*
663	* plane requiring a scaler:
664	* - During check_plane, its bit is set in
665	* crtc_state->scaler_state.scaler_users by calling helper function
666	* update_scaler_plane.
667	* - scaler_id indicates the scaler it got assigned.
668	*
669	* plane doesn't require a scaler:
670	* - this can happen when scaling is no more required or plane simply
671	* got disabled.
672	* - During check_plane, corresponding bit is reset in
673	* crtc_state->scaler_state.scaler_users by calling helper function
674	* update_scaler_plane.
675	*/
676	int scaler_id;
677
678	/*
679	* planar_linked_plane:
680	*
681	* ICL planar formats require 2 planes that are updated as pairs.
682	* This member is used to make sure the other plane is also updated
683	* when required, and for update_slave() to find the correct
684	* plane_state to pass as argument.
685	*/
686	struct intel_plane *planar_linked_plane;
687
688	struct drm_intel_sprite_colorkey ckey;
689
690	struct drm_rect psr2_sel_fetch_area;
691
692	/* Clear Color Value */
693	u64 ccval;
694
695	const char *no_fbc_reason;
696
697	struct drm_rect damage;
698	};
699
700	struct intel_initial_plane_config {
701	struct intel_framebuffer *fb;
702	struct intel_memory_region *mem;
703	resource_size_t phys_base;
704	struct i915_vma *vma;
705	unsigned int tiling;
706	int size;
707	u32 base;
708	u8 rotation;
709	};
710
711	struct intel_scaler {
712	u32 mode;
713	bool in_use;
714	int hscale;
715	int vscale;
716	};
717
718	struct intel_crtc_scaler_state {
719	#define SKL_NUM_SCALERS 2
720	struct intel_scaler scalers[SKL_NUM_SCALERS];
721
722	/*
723	* scaler_users: keeps track of users requesting scalers on this crtc.
724	*
725	* If a bit is set, a user is using a scaler.
726	* Here user can be a plane or crtc as defined below:
727	* bits 0-30 - plane (bit position is index from drm_plane_index)
728	* bit 31 - crtc
729	*
730	* Instead of creating a new index to cover planes and crtc, using
731	* existing drm_plane_index for planes which is well less than 31
732	* planes and bit 31 for crtc. This should be fine to cover all
733	* our platforms.
734	*
735	* intel_atomic_setup_scalers will setup available scalers to users
736	* requesting scalers. It will gracefully fail if request exceeds
737	* availability.
738	*/
739	#define SKL_CRTC_INDEX 31
740	unsigned scaler_users;
741
742	/* scaler used by crtc for panel fitting purpose */
743	int scaler_id;
744	};
745
746	/* {crtc,crtc_state}->mode_flags */
747	/* Flag to get scanline using frame time stamps */
748	#define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
749	/* Flag to use the scanline counter instead of the pixel counter */
750	#define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
751	/*
752	* TE0 or TE1 flag is set if the crtc has a DSI encoder which
753	* is operating in command mode.
754	* Flag to use TE from DSI0 instead of VBI in command mode
755	*/
756	#define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
757	/* Flag to use TE from DSI1 instead of VBI in command mode */
758	#define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
759	/* Flag to indicate mipi dsi periodic command mode where we do not get TE */
760	#define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
761	/* Do tricks to make vblank timestamps sane with VRR? */
762	#define I915_MODE_FLAG_VRR (1<<6)
763
764	struct intel_wm_level {
765	bool enable;
766	u32 pri_val;
767	u32 spr_val;
768	u32 cur_val;
769	u32 fbc_val;
770	};
771
772	struct intel_pipe_wm {
773	struct intel_wm_level wm[5];
774	bool fbc_wm_enabled;
775	bool pipe_enabled;
776	bool sprites_enabled;
777	bool sprites_scaled;
778	};
779
780	struct skl_wm_level {
781	u16 min_ddb_alloc;
782	u16 blocks;
783	u8 lines;
784	bool enable;
785	bool ignore_lines;
786	bool auto_min_alloc_wm_enable;
787	bool can_sagv;
788	};
789
790	struct skl_plane_wm {
791	struct skl_wm_level wm[8];
792	struct skl_wm_level uv_wm[8];
793	struct skl_wm_level trans_wm;
794	struct {
795	struct skl_wm_level wm0;
796	struct skl_wm_level trans_wm;
797	} sagv;
798	bool is_planar;
799	};
800
801	struct skl_pipe_wm {
802	struct skl_plane_wm planes[I915_MAX_PLANES];
803	bool use_sagv_wm;
804	};
805
806	enum vlv_wm_level {
807	VLV_WM_LEVEL_PM2,
808	VLV_WM_LEVEL_PM5,
809	VLV_WM_LEVEL_DDR_DVFS,
810	NUM_VLV_WM_LEVELS,
811	};
812
813	struct vlv_wm_state {
814	struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
815	struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
816	u8 num_levels;
817	bool cxsr;
818	};
819
820	struct vlv_fifo_state {
821	u16 plane[I915_MAX_PLANES];
822	};
823
824	enum g4x_wm_level {
825	G4X_WM_LEVEL_NORMAL,
826	G4X_WM_LEVEL_SR,
827	G4X_WM_LEVEL_HPLL,
828	NUM_G4X_WM_LEVELS,
829	};
830
831	struct g4x_wm_state {
832	struct g4x_pipe_wm wm;
833	struct g4x_sr_wm sr;
834	struct g4x_sr_wm hpll;
835	bool cxsr;
836	bool hpll_en;
837	bool fbc_en;
838	};
839
840	struct intel_crtc_wm_state {
841	union {
842	/*
843	* raw:
844	* The "raw" watermark values produced by the formula
845	* given the plane's current state. They do not consider
846	* how much FIFO is actually allocated for each plane.
847	*
848	* optimal:
849	* The "optimal" watermark values given the current
850	* state of the planes and the amount of FIFO
851	* allocated to each, ignoring any previous state
852	* of the planes.
853	*
854	* intermediate:
855	* The "intermediate" watermark values when transitioning
856	* between the old and new "optimal" values. Used when
857	* the watermark registers are single buffered and hence
858	* their state changes asynchronously with regards to the
859	* actual plane registers. These are essentially the
860	* worst case combination of the old and new "optimal"
861	* watermarks, which are therefore safe to use when the
862	* plane is in either its old or new state.
863	*/
864	struct {
865	struct intel_pipe_wm intermediate;
866	struct intel_pipe_wm optimal;
867	} ilk;
868
869	struct {
870	struct skl_pipe_wm raw;
871	/* gen9+ only needs 1-step wm programming */
872	struct skl_pipe_wm optimal;
873	struct skl_ddb_entry ddb;
874	/*
875	* pre-icl: for packed/planar CbCr
876	* icl+: for everything
877	*/
878	struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
879	/* pre-icl: for planar Y */
880	struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
881
882	/*
883	* xe3: Minimum amount of display blocks and minimum
884	* sagv allocation required for async flip
885	*/
886	u16 plane_min_ddb[I915_MAX_PLANES];
887	u16 plane_interim_ddb[I915_MAX_PLANES];
888	} skl;
889
890	struct {
891	struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
892	struct vlv_wm_state intermediate; /* inverted */
893	struct vlv_wm_state optimal; /* inverted */
894	struct vlv_fifo_state fifo_state;
895	} vlv;
896
897	struct {
898	struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
899	struct g4x_wm_state intermediate;
900	struct g4x_wm_state optimal;
901	} g4x;
902	};
903
904	/*
905	* Platforms with two-step watermark programming will need to
906	* update watermark programming post-vblank to switch from the
907	* safe intermediate watermarks to the optimal final
908	* watermarks.
909	*/
910	bool need_postvbl_update;
911	};
912
913	enum intel_output_format {
914	INTEL_OUTPUT_FORMAT_RGB,
915	INTEL_OUTPUT_FORMAT_YCBCR420,
916	INTEL_OUTPUT_FORMAT_YCBCR444,
917	};
918
919	/* Used by dp and fdi links */
920	struct intel_link_m_n {
921	u32 tu;
922	u32 data_m;
923	u32 data_n;
924	u32 link_m;
925	u32 link_n;
926	};
927
928	struct intel_csc_matrix {
929	u16 coeff[9];
930	u16 preoff[3];
931	u16 postoff[3];
932	};
933
934	void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val);
935
936	typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val);
937
938	struct intel_crtc_state {
939	/*
940	* uapi (drm) state. This is the software state shown to userspace.
941	* In particular, the following members are used for bookkeeping:
942	* - crtc
943	* - state
944	* - *_changed
945	* - event
946	* - commit
947	* - mode_blob
948	*/
949	struct drm_crtc_state uapi;
950
951	/*
952	* actual hardware state, the state we program to the hardware.
953	* The following members are used to verify the hardware state:
954	* - enable
955	* - active
956	* - mode / pipe_mode / adjusted_mode
957	* - color property blobs.
958	*
959	* During initial hw readout, they need to be copied to uapi.
960	*
961	* Joiner will allow a transcoder mode that spans 2 pipes;
962	* Use the pipe_mode for calculations like watermarks, pipe
963	* scaler, and bandwidth.
964	*
965	* Use adjusted_mode for things that need to know the full
966	* mode on the transcoder, which spans all pipes.
967	*/
968	struct {
969	bool active, enable;
970	/* logical state of LUTs */
971	struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
972	struct drm_display_mode mode, pipe_mode, adjusted_mode;
973	enum drm_scaling_filter scaling_filter;
974	} hw;
975
976	/* actual state of LUTs */
977	struct drm_property_blob *pre_csc_lut, *post_csc_lut;
978
979	struct intel_csc_matrix csc, output_csc;
980
981	/**
982	* quirks - bitfield with hw state readout quirks
983	*
984	* For various reasons the hw state readout code might not be able to
985	* completely faithfully read out the current state. These cases are
986	* tracked with quirk flags so that fastboot and state checker can act
987	* accordingly.
988	*/
989	#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
990	unsigned long quirks;
991
992	unsigned fb_bits; /* framebuffers to flip */
993	bool update_pipe; /* can a fast modeset be performed? */
994	bool update_m_n; /* update M/N seamlessly during fastset? */
995	bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */
996	bool disable_cxsr;
997	bool update_wm_pre, update_wm_post; /* watermarks are updated */
998	bool fifo_changed; /* FIFO split is changed */
999	bool preload_luts;
1000	bool inherited; /* state inherited from BIOS? */
1001
1002	/* Ask the hardware to actually async flip? */
1003	bool do_async_flip;
1004
1005	/* Pipe source size (ie. panel fitter input size)
1006	* All planes will be positioned inside this space,
1007	* and get clipped at the edges. */
1008	struct drm_rect pipe_src;
1009
1010	/*
1011	* Pipe pixel rate, adjusted for
1012	* panel fitter/pipe scaler downscaling.
1013	*/
1014	unsigned int pixel_rate;
1015
1016	/* Whether to set up the PCH/FDI. Note that we never allow sharing
1017	* between pch encoders and cpu encoders. */
1018	bool has_pch_encoder;
1019
1020	/* Are we sending infoframes on the attached port */
1021	bool has_infoframe;
1022
1023	/* CPU Transcoder for the pipe. Currently this can only differ from the
1024	* pipe on Haswell and later (where we have a special eDP transcoder)
1025	* and Broxton (where we have special DSI transcoders). */
1026	enum transcoder cpu_transcoder;
1027
1028	/*
1029	* Use reduced/limited/broadcast rbg range, compressing from the full
1030	* range fed into the crtcs.
1031	*/
1032	bool limited_color_range;
1033
1034	/* Bitmask of encoder types (enum intel_output_type)
1035	* driven by the pipe.
1036	*/
1037	unsigned int output_types;
1038
1039	/* Whether we should send NULL infoframes. Required for audio. */
1040	bool has_hdmi_sink;
1041
1042	/* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
1043	* has_dp_encoder is set. */
1044	bool has_audio;
1045
1046	/*
1047	* Enable dithering, used when the selected pipe bpp doesn't match the
1048	* plane bpp.
1049	*/
1050	bool dither;
1051
1052	/*
1053	* Dither gets enabled for 18bpp which causes CRC mismatch errors for
1054	* compliance video pattern tests.
1055	* Disable dither only if it is a compliance test request for
1056	* 18bpp.
1057	*/
1058	bool dither_force_disable;
1059
1060	/* Controls for the clock computation, to override various stages. */
1061	bool clock_set;
1062
1063	/* SDVO TV has a bunch of special case. To make multifunction encoders
1064	* work correctly, we need to track this at runtime.*/
1065	bool sdvo_tv_clock;
1066
1067	/*
1068	* crtc bandwidth limit, don't increase pipe bpp or clock if not really
1069	* required. This is set in the 2nd loop of calling encoder's
1070	* ->compute_config if the first pick doesn't work out.
1071	*/
1072	bool bw_constrained;
1073
1074	/* Settings for the intel dpll used on pretty much everything but
1075	* haswell. */
1076	struct dpll dpll;
1077
1078	/* Selected dpll when shared or NULL. */
1079	struct intel_shared_dpll *shared_dpll;
1080
1081	/* Actual register state of the dpll, for shared dpll cross-checking. */
1082	struct intel_dpll_hw_state dpll_hw_state;
1083
1084	/*
1085	* ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
1086	* setting shared_dpll and dpll_hw_state to one of these reserved ones.
1087	*/
1088	struct icl_port_dpll {
1089	struct intel_shared_dpll *pll;
1090	struct intel_dpll_hw_state hw_state;
1091	} icl_port_dplls[ICL_PORT_DPLL_COUNT];
1092
1093	/* DSI PLL registers */
1094	struct {
1095	u32 ctrl, div;
1096	} dsi_pll;
1097
1098	int max_link_bpp_x16; /* in 1/16 bpp units */
1099	int pipe_bpp; /* in 1 bpp units */
1100	int min_hblank;
1101	struct intel_link_m_n dp_m_n;
1102
1103	/* m2_n2 for eDP downclock */
1104	struct intel_link_m_n dp_m2_n2;
1105	bool has_drrs;
1106
1107	/* PSR is supported but might not be enabled due the lack of enabled planes */
1108	bool has_psr;
1109	bool has_sel_update;
1110	bool enable_psr2_sel_fetch;
1111	bool enable_psr2_su_region_et;
1112	bool req_psr2_sdp_prior_scanline;
1113	bool has_panel_replay;
1114	bool wm_level_disabled;
1115	u32 dc3co_exitline;
1116	u16 su_y_granularity;
1117	u8 active_non_psr_pipes;
1118
1119	/*
1120	* Frequency the dpll for the port should run at. Differs from the
1121	* adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
1122	* already multiplied by pixel_multiplier.
1123	*/
1124	int port_clock;
1125
1126	/* Used by SDVO (and if we ever fix it, HDMI). */
1127	unsigned pixel_multiplier;
1128
1129	/* I915_MODE_FLAG_* */
1130	u8 mode_flags;
1131
1132	u8 lane_count;
1133
1134	/*
1135	* Used by platforms having DP/HDMI PHY with programmable lane
1136	* latency optimization.
1137	*/
1138	u8 lane_lat_optim_mask;
1139
1140	/* minimum acceptable voltage level */
1141	u8 min_voltage_level;
1142
1143	/* Panel fitter controls for gen2-gen4 + VLV */
1144	struct {
1145	u32 control;
1146	u32 pgm_ratios;
1147	u32 lvds_border_bits;
1148	} gmch_pfit;
1149
1150	/* Panel fitter placement and size for Ironlake+ */
1151	struct {
1152	struct drm_rect dst;
1153	bool enabled;
1154	bool force_thru;
1155	} pch_pfit;
1156
1157	/* FDI configuration, only valid if has_pch_encoder is set. */
1158	int fdi_lanes;
1159	struct intel_link_m_n fdi_m_n;
1160
1161	bool ips_enabled;
1162
1163	bool crc_enabled;
1164
1165	bool double_wide;
1166
1167	struct intel_crtc_scaler_state scaler_state;
1168
1169	/* w/a for waiting 2 vblanks during crtc enable */
1170	enum pipe hsw_workaround_pipe;
1171
1172	struct intel_crtc_wm_state wm;
1173
1174	int min_cdclk[I915_MAX_PLANES];
1175
1176	/* for packed/planar CbCr */
1177	u32 data_rate[I915_MAX_PLANES];
1178	/* for planar Y */
1179	u32 data_rate_y[I915_MAX_PLANES];
1180
1181	/* FIXME unify with data_rate[]? */
1182	u64 rel_data_rate[I915_MAX_PLANES];
1183	u64 rel_data_rate_y[I915_MAX_PLANES];
1184
1185	/* Gamma mode programmed on the pipe */
1186	u32 gamma_mode;
1187
1188	union {
1189	/* CSC mode programmed on the pipe */
1190	u32 csc_mode;
1191
1192	/* CHV CGM mode */
1193	u32 cgm_mode;
1194	};
1195
1196	/* bitmask of logically enabled planes (enum plane_id) */
1197	u8 enabled_planes;
1198
1199	/* bitmask of actually visible planes (enum plane_id) */
1200	u8 active_planes;
1201	u8 scaled_planes;
1202	u8 nv12_planes;
1203	u8 c8_planes;
1204
1205	/* bitmask of planes that will be updated during the commit */
1206	u8 update_planes;
1207
1208	/* bitmask of planes with async flip active */
1209	u8 async_flip_planes;
1210
1211	u8 framestart_delay; /* 1-4 */
1212	u8 msa_timing_delay; /* 0-3 */
1213
1214	struct {
1215	u32 enable;
1216	u32 gcp;
1217	union hdmi_infoframe avi;
1218	union hdmi_infoframe spd;
1219	union hdmi_infoframe hdmi;
1220	union hdmi_infoframe drm;
1221	struct drm_dp_vsc_sdp vsc;
1222	struct drm_dp_as_sdp as_sdp;
1223	} infoframes;
1224
1225	u8 eld[MAX_ELD_BYTES];
1226
1227	/* HDMI scrambling status */
1228	bool hdmi_scrambling;
1229
1230	/* HDMI High TMDS char rate ratio */
1231	bool hdmi_high_tmds_clock_ratio;
1232
1233	/*
1234	* Output format RGB/YCBCR etc., that is coming out
1235	* at the end of the pipe.
1236	*/
1237	enum intel_output_format output_format;
1238
1239	/*
1240	* Sink output format RGB/YCBCR etc., that is going
1241	* into the sink.
1242	*/
1243	enum intel_output_format sink_format;
1244
1245	/* enable pipe gamma? */
1246	bool gamma_enable;
1247
1248	/* enable pipe csc? */
1249	bool csc_enable;
1250
1251	/* enable vlv/chv wgc csc? */
1252	bool wgc_enable;
1253
1254	/* joiner pipe bitmask */
1255	u8 joiner_pipes;
1256
1257	/* Display Stream compression state */
1258	struct {
1259	bool compression_enable;
1260	int num_streams;
1261	/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
1262	u16 compressed_bpp_x16;
1263	u8 slice_count;
1264	struct drm_dsc_config config;
1265	} dsc;
1266
1267	/* DP tunnel used for BW allocation. */
1268	struct drm_dp_tunnel_ref dp_tunnel_ref;
1269
1270	/* HSW+ linetime watermarks */
1271	u16 linetime;
1272	u16 ips_linetime;
1273
1274	bool enhanced_framing;
1275
1276	/*
1277	* Forward Error Correction.
1278	*
1279	* Note: This will be false for 128b/132b, which will always have FEC
1280	* enabled automatically.
1281	*/
1282	bool fec_enable;
1283
1284	bool sdp_split_enable;
1285
1286	/* Pointer to master transcoder in case of tiled displays */
1287	enum transcoder master_transcoder;
1288
1289	/* Bitmask to indicate slaves attached */
1290	u8 sync_mode_slaves_mask;
1291
1292	/* Only valid on TGL+ */
1293	enum transcoder mst_master_transcoder;
1294
1295	/* For DSB based pipe updates */
1296	struct intel_dsb *dsb_color_vblank, *dsb_commit;
1297	bool use_dsb;
1298
1299	u32 psr2_man_track_ctl;
1300
1301	u32 pipe_srcsz_early_tpt;
1302
1303	struct drm_rect psr2_su_area;
1304
1305	/* Variable Refresh Rate state */
1306	struct {
1307	bool enable, in_range;
1308	u8 pipeline_full;
1309	u16 flipline, vmin, vmax, guardband;
1310	u32 vsync_end, vsync_start;
1311	} vrr;
1312
1313	/* Content Match Refresh Rate state */
1314	struct {
1315	bool enable;
1316	u64 cmrr_n, cmrr_m;
1317	} cmrr;
1318
1319	/* Stream Splitter for eDP MSO */
1320	struct {
1321	bool enable;
1322	u8 link_count;
1323	u8 pixel_overlap;
1324	} splitter;
1325
1326	/* for loading single buffered registers during vblank */
1327	struct drm_vblank_work vblank_work;
1328
1329	/* LOBF flag */
1330	bool has_lobf;
1331	};
1332
1333	enum intel_pipe_crc_source {
1334	INTEL_PIPE_CRC_SOURCE_NONE,
1335	INTEL_PIPE_CRC_SOURCE_PLANE1,
1336	INTEL_PIPE_CRC_SOURCE_PLANE2,
1337	INTEL_PIPE_CRC_SOURCE_PLANE3,
1338	INTEL_PIPE_CRC_SOURCE_PLANE4,
1339	INTEL_PIPE_CRC_SOURCE_PLANE5,
1340	INTEL_PIPE_CRC_SOURCE_PLANE6,
1341	INTEL_PIPE_CRC_SOURCE_PLANE7,
1342	INTEL_PIPE_CRC_SOURCE_PIPE,
1343	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
1344	INTEL_PIPE_CRC_SOURCE_TV,
1345	INTEL_PIPE_CRC_SOURCE_DP_B,
1346	INTEL_PIPE_CRC_SOURCE_DP_C,
1347	INTEL_PIPE_CRC_SOURCE_DP_D,
1348	INTEL_PIPE_CRC_SOURCE_AUTO,
1349	INTEL_PIPE_CRC_SOURCE_MAX,
1350	};
1351
1352	enum drrs_refresh_rate {
1353	DRRS_REFRESH_RATE_HIGH,
1354	DRRS_REFRESH_RATE_LOW,
1355	};
1356
1357	#define INTEL_PIPE_CRC_ENTRIES_NR 128
1358	struct intel_pipe_crc {
1359	spinlock_t lock;
1360	int skipped;
1361	enum intel_pipe_crc_source source;
1362	};
1363
1364	struct intel_crtc {
1365	struct drm_crtc base;
1366	enum pipe pipe;
1367	/*
1368	* Whether the crtc and the connected output pipeline is active. Implies
1369	* that crtc->enabled is set, i.e. the current mode configuration has
1370	* some outputs connected to this crtc.
1371	*/
1372	bool active;
1373	u8 plane_ids_mask;
1374
1375	/* I915_MODE_FLAG_* */
1376	u8 mode_flags;
1377
1378	u16 vmax_vblank_start;
1379
1380	struct intel_display_power_domain_set enabled_power_domains;
1381	struct intel_display_power_domain_set hw_readout_power_domains;
1382	struct intel_overlay *overlay;
1383
1384	struct intel_crtc_state *config;
1385
1386	/* armed event for async flip */
1387	struct drm_pending_vblank_event *flip_done_event;
1388	/* armed event for DSB based updates */
1389	struct drm_pending_vblank_event *dsb_event;
1390
1391	/* Access to these should be protected by display->irq.lock. */
1392	bool cpu_fifo_underrun_disabled;
1393	bool pch_fifo_underrun_disabled;
1394
1395	/* per-pipe watermark state */
1396	struct {
1397	/* watermarks currently being used */
1398	union {
1399	struct intel_pipe_wm ilk;
1400	struct vlv_wm_state vlv;
1401	struct g4x_wm_state g4x;
1402	} active;
1403	} wm;
1404
1405	struct {
1406	struct mutex mutex;
1407	struct delayed_work work;
1408	enum drrs_refresh_rate refresh_rate;
1409	unsigned int frontbuffer_bits;
1410	unsigned int busy_frontbuffer_bits;
1411	enum transcoder cpu_transcoder;
1412	struct intel_link_m_n m_n, m2_n2;
1413	} drrs;
1414
1415	int scanline_offset;
1416
1417	struct {
1418	unsigned start_vbl_count;
1419	ktime_t start_vbl_time;
1420	int min_vbl, max_vbl;
1421	int scanline_start;
1422	#ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
1423	struct {
1424	u64 min;
1425	u64 max;
1426	u64 sum;
1427	unsigned int over;
1428	unsigned int times[17]; /* [1us, 16ms] */
1429	} vbl;
1430	#endif
1431	} debug;
1432
1433	/* scalers available on this crtc */
1434	int num_scalers;
1435
1436	/* for loading single buffered registers during vblank */
1437	struct pm_qos_request vblank_pm_qos;
1438
1439	#ifdef CONFIG_DEBUG_FS
1440	struct intel_pipe_crc pipe_crc;
1441	#endif
1442
1443	bool vblank_psr_notify;
1444	};
1445
1446	struct intel_plane_error {
1447	u32 ctl, surf, surflive;
1448	};
1449
1450	struct intel_plane {
1451	struct drm_plane base;
1452	enum i9xx_plane_id i9xx_plane;
1453	enum plane_id id;
1454	enum pipe pipe;
1455	bool need_async_flip_toggle_wa;
1456	u8 vtd_guard;
1457	u32 frontbuffer_bit;
1458
1459	struct {
1460	u32 base, cntl, size;
1461	} cursor;
1462
1463	struct intel_fbc *fbc;
1464
1465	/*
1466	* NOTE: Do not place new plane state fields here (e.g., when adding
1467	* new plane properties). New runtime state should now be placed in
1468	* the intel_plane_state structure and accessed via plane_state.
1469	*/
1470
1471	int (*min_width)(const struct drm_framebuffer *fb,
1472	int color_plane,
1473	unsigned int rotation);
1474	int (*max_width)(const struct drm_framebuffer *fb,
1475	int color_plane,
1476	unsigned int rotation);
1477	int (*max_height)(const struct drm_framebuffer *fb,
1478	int color_plane,
1479	unsigned int rotation);
1480	unsigned int (*min_alignment)(struct intel_plane *plane,
1481	const struct drm_framebuffer *fb,
1482	int color_plane);
1483	unsigned int (*max_stride)(struct intel_plane *plane,
1484	u32 pixel_format, u64 modifier,
1485	unsigned int rotation);
1486	bool (*can_async_flip)(u64 modifier);
1487	/* Write all non-self arming plane registers */
1488	void (*update_noarm)(struct intel_dsb *dsb,
1489	struct intel_plane *plane,
1490	const struct intel_crtc_state *crtc_state,
1491	const struct intel_plane_state *plane_state);
1492	/* Write all self-arming plane registers */
1493	void (*update_arm)(struct intel_dsb *dsb,
1494	struct intel_plane *plane,
1495	const struct intel_crtc_state *crtc_state,
1496	const struct intel_plane_state *plane_state);
1497	/* Disable the plane, must arm */
1498	void (*disable_arm)(struct intel_dsb *dsb,
1499	struct intel_plane *plane,
1500	const struct intel_crtc_state *crtc_state);
1501	void (*capture_error)(struct intel_crtc *crtc,
1502	struct intel_plane *plane,
1503	struct intel_plane_error *error);
1504	bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1505	int (*check_plane)(struct intel_crtc_state *crtc_state,
1506	struct intel_plane_state *plane_state);
1507	int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1508	const struct intel_plane_state *plane_state);
1509	void (*async_flip)(struct intel_dsb *dsb,
1510	struct intel_plane *plane,
1511	const struct intel_crtc_state *crtc_state,
1512	const struct intel_plane_state *plane_state,
1513	bool async_flip);
1514	void (*enable_flip_done)(struct intel_plane *plane);
1515	void (*disable_flip_done)(struct intel_plane *plane);
1516	};
1517
1518	#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1519	#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1520	#define to_intel_connector(x) container_of(x, struct intel_connector, base)
1521	#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1522	#define to_intel_plane(x) container_of(x, struct intel_plane, base)
1523
1524	#define to_intel_crtc_state(crtc_state) \
1525	container_of_const((crtc_state), struct intel_crtc_state, uapi)
1526	#define to_intel_plane_state(plane_state) \
1527	container_of_const((plane_state), struct intel_plane_state, uapi)
1528	#define to_intel_framebuffer(fb) \
1529	container_of_const((fb), struct intel_framebuffer, base)
1530
1531	struct intel_hdmi {
1532	i915_reg_t hdmi_reg;
1533	struct {
1534	enum drm_dp_dual_mode_type type;
1535	int max_tmds_clock;
1536	} dp_dual_mode;
1537	struct intel_connector *attached_connector;
1538	struct cec_notifier *cec_notifier;
1539	};
1540
1541	struct intel_dp_mst_encoder;
1542
1543	struct intel_dp_compliance_data {
1544	unsigned long edid;
1545	u8 video_pattern;
1546	u16 hdisplay, vdisplay;
1547	u8 bpc;
1548	struct drm_dp_phy_test_params phytest;
1549	};
1550
1551	struct intel_dp_compliance {
1552	unsigned long test_type;
1553	struct intel_dp_compliance_data test_data;
1554	bool test_active;
1555	int test_link_rate;
1556	u8 test_lane_count;
1557	};
1558
1559	struct intel_dp_pcon_frl {
1560	bool is_trained;
1561	int trained_rate_gbps;
1562	};
1563
1564	struct intel_pps {
1565	int panel_power_up_delay;
1566	int panel_power_down_delay;
1567	int panel_power_cycle_delay;
1568	int backlight_on_delay;
1569	int backlight_off_delay;
1570	struct delayed_work panel_vdd_work;
1571	bool want_panel_vdd;
1572	bool initializing;
1573	unsigned long last_power_on;
1574	unsigned long last_backlight_off;
1575	ktime_t panel_power_off_time;
1576	intel_wakeref_t vdd_wakeref;
1577
1578	union {
1579	/*
1580	* Pipe whose power sequencer is currently locked into
1581	* this port. Only relevant on VLV/CHV.
1582	*/
1583	enum pipe vlv_pps_pipe;
1584
1585	/*
1586	* Power sequencer index. Only relevant on BXT+.
1587	*/
1588	int pps_idx;
1589	};
1590
1591	/*
1592	* Pipe currently driving the port. Used for preventing
1593	* the use of the PPS for any pipe currentrly driving
1594	* external DP as that will mess things up on VLV.
1595	*/
1596	enum pipe vlv_active_pipe;
1597	/*
1598	* Set if the sequencer may be reset due to a power transition,
1599	* requiring a reinitialization. Only relevant on BXT+.
1600	*/
1601	bool bxt_pps_reset;
1602	struct intel_pps_delays pps_delays;
1603	struct intel_pps_delays bios_pps_delays;
1604	};
1605
1606	struct intel_psr {
1607	/* Mutex for PSR state of the transcoder */
1608	struct mutex lock;
1609
1610	#define I915_PSR_DEBUG_MODE_MASK 0x0f
1611	#define I915_PSR_DEBUG_DEFAULT 0x00
1612	#define I915_PSR_DEBUG_DISABLE 0x01
1613	#define I915_PSR_DEBUG_ENABLE 0x02
1614	#define I915_PSR_DEBUG_FORCE_PSR1 0x03
1615	#define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
1616	#define I915_PSR_DEBUG_IRQ 0x10
1617	#define I915_PSR_DEBUG_SU_REGION_ET_DISABLE 0x20
1618	#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
1619
1620	u32 debug;
1621	bool sink_support;
1622	bool source_support;
1623	bool enabled;
1624	int pause_counter;
1625	enum pipe pipe;
1626	enum transcoder transcoder;
1627	bool active;
1628	struct work_struct work;
1629	unsigned int busy_frontbuffer_bits;
1630	bool sink_psr2_support;
1631	bool link_standby;
1632	bool sel_update_enabled;
1633	bool psr2_sel_fetch_enabled;
1634	bool psr2_sel_fetch_cff_enabled;
1635	bool su_region_et_enabled;
1636	bool req_psr2_sdp_prior_scanline;
1637	u8 sink_sync_latency;
1638	ktime_t last_entry_attempt;
1639	ktime_t last_exit;
1640	bool sink_not_reliable;
1641	bool irq_aux_error;
1642	u16 su_w_granularity;
1643	u16 su_y_granularity;
1644	bool source_panel_replay_support;
1645	bool sink_panel_replay_support;
1646	bool sink_panel_replay_su_support;
1647	bool panel_replay_enabled;
1648	u32 dc3co_exitline;
1649	u32 dc3co_exit_delay;
1650	struct delayed_work dc3co_work;
1651	u8 entry_setup_frames;
1652
1653	bool link_ok;
1654
1655	u8 active_non_psr_pipes;
1656	};
1657
1658	struct intel_dp {
1659	i915_reg_t output_reg;
1660	u32 DP;
1661	int link_rate;
1662	u8 lane_count;
1663	u8 sink_count;
1664	bool needs_modeset_retry;
1665	bool use_max_params;
1666	u8 dpcd[DP_RECEIVER_CAP_SIZE];
1667	u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1668	u8 pr_dpcd;
1669	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1670	u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1671	u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1672	u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1673	u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1674	/* source rates */
1675	int num_source_rates;
1676	const int *source_rates;
1677	/* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1678	int num_sink_rates;
1679	int sink_rates[DP_MAX_SUPPORTED_RATES];
1680	bool use_rate_select;
1681	/* Max sink lane count as reported by DP_MAX_LANE_COUNT */
1682	int max_sink_lane_count;
1683	/* intersection of source and sink rates */
1684	int num_common_rates;
1685	int common_rates[DP_MAX_SUPPORTED_RATES];
1686	struct {
1687	/* TODO: move the rest of link specific fields to here */
1688	bool active;
1689	/* common rate,lane_count configs in bw order */
1690	int num_configs;
1691	#define INTEL_DP_MAX_LANE_COUNT 4
1692	#define INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS (ilog2(INTEL_DP_MAX_LANE_COUNT) + 1)
1693	#define INTEL_DP_LANE_COUNT_EXP_BITS order_base_2(INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS)
1694	#define INTEL_DP_LINK_RATE_IDX_BITS (BITS_PER_TYPE(u8) - INTEL_DP_LANE_COUNT_EXP_BITS)
1695	#define INTEL_DP_MAX_LINK_CONFIGS (DP_MAX_SUPPORTED_RATES * \
1696	INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS)
1697	struct intel_dp_link_config {
1698	u8 link_rate_idx:INTEL_DP_LINK_RATE_IDX_BITS;
1699	u8 lane_count_exp:INTEL_DP_LANE_COUNT_EXP_BITS;
1700	} configs[INTEL_DP_MAX_LINK_CONFIGS];
1701	/* Max lane count for the current link */
1702	int max_lane_count;
1703	/* Max rate for the current link */
1704	int max_rate;
1705	/*
1706	* Link parameters for which the MST topology was probed.
1707	* Tracking these ensures that the MST path resources are
1708	* re-enumerated whenever the link is retrained with new link
1709	* parameters, as required by the DP standard.
1710	*/
1711	int mst_probed_lane_count;
1712	int mst_probed_rate;
1713	int force_lane_count;
1714	int force_rate;
1715	bool retrain_disabled;
1716	/* Sequential link training failures after a passing LT */
1717	int seq_train_failures;
1718	int force_train_failure;
1719	bool force_retrain;
1720	} link;
1721	bool reset_link_params;
1722	int mso_link_count;
1723	int mso_pixel_overlap;
1724	/* sink or branch descriptor */
1725	struct drm_dp_desc desc;
1726	struct drm_dp_aux aux;
1727	u32 aux_busy_last_status;
1728	u8 train_set[4];
1729
1730	struct intel_pps pps;
1731
1732	bool is_mst;
1733	enum drm_dp_mst_mode mst_detect;
1734
1735	/* connector directly attached - won't be use for modeset in mst world */
1736	struct intel_connector *attached_connector;
1737	bool as_sdp_supported;
1738
1739	struct drm_dp_tunnel *tunnel;
1740	bool tunnel_suspended:1;
1741
1742	struct {
1743	struct intel_dp_mst_encoder *stream_encoders[I915_MAX_PIPES];
1744	struct drm_dp_mst_topology_mgr mgr;
1745	int active_streams;
1746	} mst;
1747
1748	u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1749	/*
1750	* This function returns the value we have to program the AUX_CTL
1751	* register with to kick off an AUX transaction.
1752	*/
1753	u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1754	u32 aux_clock_divider);
1755
1756	i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1757	i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1758
1759	/* This is called before a link training is starterd */
1760	void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1761	const struct intel_crtc_state *crtc_state);
1762	void (*set_link_train)(struct intel_dp *intel_dp,
1763	const struct intel_crtc_state *crtc_state,
1764	u8 dp_train_pat);
1765	void (*set_idle_link_train)(struct intel_dp *intel_dp,
1766	const struct intel_crtc_state *crtc_state);
1767
1768	u8 (*preemph_max)(struct intel_dp *intel_dp);
1769	u8 (*voltage_max)(struct intel_dp *intel_dp,
1770	const struct intel_crtc_state *crtc_state);
1771
1772	/* Displayport compliance testing */
1773	struct intel_dp_compliance compliance;
1774
1775	/* Downstream facing port caps */
1776	struct {
1777	int min_tmds_clock, max_tmds_clock;
1778	int max_dotclock;
1779	int pcon_max_frl_bw;
1780	u8 max_bpc;
1781	bool ycbcr_444_to_420;
1782	bool ycbcr420_passthrough;
1783	bool rgb_to_ycbcr;
1784	} dfp;
1785
1786	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1787	struct pm_qos_request pm_qos;
1788
1789	/* Display stream compression testing */
1790	bool force_dsc_en;
1791	int force_dsc_output_format;
1792	bool force_dsc_fractional_bpp_en;
1793	int force_dsc_bpc;
1794
1795	bool hobl_failed;
1796	bool hobl_active;
1797
1798	struct intel_dp_pcon_frl frl;
1799
1800	struct intel_psr psr;
1801
1802	/* When we last wrote the OUI for eDP */
1803	unsigned long last_oui_write;
1804	bool oui_valid;
1805
1806	bool colorimetry_support;
1807
1808	struct {
1809	u8 io_wake_lines;
1810	u8 fast_wake_lines;
1811	enum transcoder transcoder;
1812	struct mutex lock;
1813
1814	/* LNL and beyond */
1815	u8 check_entry_lines;
1816	u8 aux_less_wake_lines;
1817	u8 silence_period_sym_clocks;
1818	u8 lfps_half_cycle_num_of_syms;
1819	bool lobf_disable_debug;
1820	bool sink_alpm_error;
1821	} alpm_parameters;
1822
1823	u8 alpm_dpcd;
1824
1825	struct {
1826	unsigned long mask;
1827	} quirks;
1828	};
1829
1830	enum lspcon_vendor {
1831	LSPCON_VENDOR_MCA,
1832	LSPCON_VENDOR_PARADE
1833	};
1834
1835	struct intel_lspcon {
1836	bool active;
1837	bool hdr_supported;
1838	enum drm_lspcon_mode mode;
1839	enum lspcon_vendor vendor;
1840	};
1841
1842	struct intel_digital_port {
1843	struct intel_encoder base;
1844	struct intel_dp dp;
1845	struct intel_hdmi hdmi;
1846	struct intel_lspcon lspcon;
1847	enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1848
1849	bool lane_reversal;
1850	bool ddi_a_4_lanes;
1851	bool release_cl2_override;
1852	u8 max_lanes;
1853	/* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1854	enum aux_ch aux_ch;
1855	enum intel_display_power_domain ddi_io_power_domain;
1856	intel_wakeref_t ddi_io_wakeref;
1857	intel_wakeref_t aux_wakeref;
1858
1859	struct intel_tc_port *tc;
1860
1861	struct {
1862	/* protects num_streams reference count, port_data and auth_status */
1863	struct mutex mutex;
1864	/* the number of pipes using HDCP signalling out of this port */
1865	unsigned int num_streams;
1866	/* port HDCP auth status */
1867	bool auth_status;
1868	/* HDCP port data need to pass to security f/w */
1869	struct hdcp_port_data port_data;
1870	/* Whether the MST topology supports HDCP Type 1 Content */
1871	bool mst_type1_capable;
1872	} hdcp;
1873
1874	void (*write_infoframe)(struct intel_encoder *encoder,
1875	const struct intel_crtc_state *crtc_state,
1876	unsigned int type,
1877	const void *frame, ssize_t len);
1878	void (*read_infoframe)(struct intel_encoder *encoder,
1879	const struct intel_crtc_state *crtc_state,
1880	unsigned int type,
1881	void *frame, ssize_t len);
1882	void (*set_infoframes)(struct intel_encoder *encoder,
1883	bool enable,
1884	const struct intel_crtc_state *crtc_state,
1885	const struct drm_connector_state *conn_state);
1886	u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1887	const struct intel_crtc_state *pipe_config);
1888	bool (*connected)(struct intel_encoder *encoder);
1889
1890	void (*lock)(struct intel_digital_port *dig_port);
1891	void (*unlock)(struct intel_digital_port *dig_port);
1892	};
1893
1894	struct intel_dp_mst_encoder {
1895	struct intel_encoder base;
1896	enum pipe pipe;
1897	struct intel_digital_port *primary;
1898	struct intel_connector *connector;
1899	};
1900
1901	static inline struct intel_encoder *
1902	intel_attached_encoder(struct intel_connector *connector)
1903	{
1904	return connector->encoder;
1905	}
1906
1907	static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1908	{
1909	switch (encoder->type) {
1910	case INTEL_OUTPUT_DDI:
1911	case INTEL_OUTPUT_DP:
1912	case INTEL_OUTPUT_EDP:
1913	case INTEL_OUTPUT_HDMI:
1914	return true;
1915	default:
1916	return false;
1917	}
1918	}
1919
1920	static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1921	{
1922	return encoder->type == INTEL_OUTPUT_DP_MST;
1923	}
1924
1925	static inline struct intel_dp_mst_encoder *
1926	enc_to_mst(struct intel_encoder *encoder)
1927	{
1928	return container_of(&encoder->base, struct intel_dp_mst_encoder,
1929	base.base);
1930	}
1931
1932	static inline struct intel_digital_port *
1933	enc_to_dig_port(struct intel_encoder *encoder)
1934	{
1935	struct intel_encoder *intel_encoder = encoder;
1936
1937	if (intel_encoder_is_dig_port(encoder: intel_encoder))
1938	return container_of(&encoder->base, struct intel_digital_port,
1939	base.base);
1940	else if (intel_encoder_is_mst(encoder: intel_encoder))
1941	return enc_to_mst(encoder)->primary;
1942	else
1943	return NULL;
1944	}
1945
1946	static inline struct intel_digital_port *
1947	intel_attached_dig_port(struct intel_connector *connector)
1948	{
1949	return enc_to_dig_port(encoder: intel_attached_encoder(connector));
1950	}
1951
1952	static inline struct intel_hdmi *
1953	enc_to_intel_hdmi(struct intel_encoder *encoder)
1954	{
1955	return &enc_to_dig_port(encoder)->hdmi;
1956	}
1957
1958	static inline struct intel_hdmi *
1959	intel_attached_hdmi(struct intel_connector *connector)
1960	{
1961	return enc_to_intel_hdmi(encoder: intel_attached_encoder(connector));
1962	}
1963
1964	static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1965	{
1966	return &enc_to_dig_port(encoder)->dp;
1967	}
1968
1969	static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1970	{
1971	if (connector->mst.dp)
1972	return connector->mst.dp;
1973	else
1974	return enc_to_intel_dp(encoder: intel_attached_encoder(connector));
1975	}
1976
1977	static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1978	{
1979	switch (encoder->type) {
1980	case INTEL_OUTPUT_DP:
1981	case INTEL_OUTPUT_EDP:
1982	return true;
1983	case INTEL_OUTPUT_DDI:
1984	/* Skip pure HDMI/DVI DDI encoders */
1985	return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1986	default:
1987	return false;
1988	}
1989	}
1990
1991	static inline bool intel_encoder_is_hdmi(struct intel_encoder *encoder)
1992	{
1993	switch (encoder->type) {
1994	case INTEL_OUTPUT_HDMI:
1995	return true;
1996	case INTEL_OUTPUT_DDI:
1997	/* See if the HDMI encoder is valid. */
1998	return i915_mmio_reg_valid(enc_to_intel_hdmi(encoder)->hdmi_reg);
1999	default:
2000	return false;
2001	}
2002	}
2003
2004	static inline struct intel_digital_port *
2005	dp_to_dig_port(struct intel_dp *intel_dp)
2006	{
2007	return container_of(intel_dp, struct intel_digital_port, dp);
2008	}
2009
2010	static inline struct intel_digital_port *
2011	hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
2012	{
2013	return container_of(intel_hdmi, struct intel_digital_port, hdmi);
2014	}
2015
2016	static inline struct intel_plane_state *
2017	intel_atomic_get_plane_state(struct intel_atomic_state *state,
2018	struct intel_plane *plane)
2019	{
2020	struct drm_plane_state *ret =
2021	drm_atomic_get_plane_state(state: &state->base, plane: &plane->base);
2022
2023	if (IS_ERR(ptr: ret))
2024	return ERR_CAST(ptr: ret);
2025
2026	return to_intel_plane_state(ret);
2027	}
2028
2029	static inline struct intel_plane_state *
2030	intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
2031	struct intel_plane *plane)
2032	{
2033	return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
2034	&plane->base));
2035	}
2036
2037	static inline struct intel_plane_state *
2038	intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
2039	struct intel_plane *plane)
2040	{
2041	return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
2042	&plane->base));
2043	}
2044
2045	static inline struct intel_crtc_state *
2046	intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
2047	struct intel_crtc *crtc)
2048	{
2049	return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
2050	&crtc->base));
2051	}
2052
2053	static inline struct intel_crtc_state *
2054	intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
2055	struct intel_crtc *crtc)
2056	{
2057	return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
2058	&crtc->base));
2059	}
2060
2061	static inline struct intel_digital_connector_state *
2062	intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
2063	struct intel_connector *connector)
2064	{
2065	return to_intel_digital_connector_state(
2066	drm_atomic_get_new_connector_state(&state->base,
2067	&connector->base));
2068	}
2069
2070	static inline struct intel_digital_connector_state *
2071	intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
2072	struct intel_connector *connector)
2073	{
2074	return to_intel_digital_connector_state(
2075	drm_atomic_get_old_connector_state(&state->base,
2076	&connector->base));
2077	}
2078
2079	/* intel_display.c */
2080	static inline bool
2081	intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
2082	enum intel_output_type type)
2083	{
2084	return crtc_state->output_types & BIT(type);
2085	}
2086
2087	static inline bool
2088	intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
2089	{
2090	return crtc_state->output_types &
2091	(BIT(INTEL_OUTPUT_DP) |
2092	BIT(INTEL_OUTPUT_DP_MST) |
2093	BIT(INTEL_OUTPUT_EDP));
2094	}
2095
2096	static inline bool
2097	intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
2098	{
2099	return drm_atomic_crtc_needs_modeset(state: &crtc_state->uapi);
2100	}
2101
2102	static inline bool
2103	intel_crtc_needs_fastset(const struct intel_crtc_state *crtc_state)
2104	{
2105	return crtc_state->update_pipe;
2106	}
2107
2108	static inline bool
2109	intel_crtc_needs_color_update(const struct intel_crtc_state *crtc_state)
2110	{
2111	return crtc_state->uapi.color_mgmt_changed ||
2112	intel_crtc_needs_fastset(crtc_state) ||
2113	intel_crtc_needs_modeset(crtc_state);
2114	}
2115
2116	static inline struct intel_frontbuffer *
2117	to_intel_frontbuffer(struct drm_framebuffer *fb)
2118	{
2119	return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
2120	}
2121
2122	/*
2123	* Conversion functions/macros from various pointer types to struct
2124	* intel_display pointer.
2125	*/
2126	#define __drm_device_to_intel_display(p) \
2127	((p) ? __drm_to_display(p) : NULL)
2128	#define __device_to_intel_display(p) \
2129	__drm_device_to_intel_display(dev_get_drvdata(p))
2130	#define __pci_dev_to_intel_display(p) \
2131	__drm_device_to_intel_display(pci_get_drvdata(p))
2132	#define __intel_atomic_state_to_intel_display(p) \
2133	__drm_device_to_intel_display((p)->base.dev)
2134	#define __intel_connector_to_intel_display(p) \
2135	__drm_device_to_intel_display((p)->base.dev)
2136	#define __intel_crtc_to_intel_display(p) \
2137	__drm_device_to_intel_display((p)->base.dev)
2138	#define __intel_crtc_state_to_intel_display(p) \
2139	__drm_device_to_intel_display((p)->uapi.crtc->dev)
2140	#define __intel_digital_port_to_intel_display(p) \
2141	__drm_device_to_intel_display((p)->base.base.dev)
2142	#define __intel_dp_to_intel_display(p) \
2143	__drm_device_to_intel_display(dp_to_dig_port(p)->base.base.dev)
2144	#define __intel_encoder_to_intel_display(p) \
2145	__drm_device_to_intel_display((p)->base.dev)
2146	#define __intel_hdmi_to_intel_display(p) \
2147	__drm_device_to_intel_display(hdmi_to_dig_port(p)->base.base.dev)
2148	#define __intel_plane_to_intel_display(p) \
2149	__drm_device_to_intel_display((p)->base.dev)
2150	#define __intel_plane_state_to_intel_display(p) \
2151	__drm_device_to_intel_display((p)->uapi.plane->dev)
2152
2153	/* Helper for generic association. Map types to conversion functions/macros. */
2154	#define __assoc(type, p) \
2155	struct type: __##type##_to_intel_display((struct type *)(p))
2156
2157	/* Convert various pointer types to struct intel_display pointer. */
2158	#define to_intel_display(p) \
2159	_Generic(*p, \
2160	__assoc(drm_device, p), \
2161	__assoc(device, p), \
2162	__assoc(pci_dev, p), \
2163	__assoc(intel_atomic_state, p), \
2164	__assoc(intel_connector, p), \
2165	__assoc(intel_crtc, p), \
2166	__assoc(intel_crtc_state, p), \
2167	__assoc(intel_digital_port, p), \
2168	__assoc(intel_dp, p), \
2169	__assoc(intel_encoder, p), \
2170	__assoc(intel_hdmi, p), \
2171	__assoc(intel_plane, p), \
2172	__assoc(intel_plane_state, p))
2173
2174	#endif /* __INTEL_DISPLAY_TYPES_H__ */
2175