| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2023 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_DSB_REGS_H__ |
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| 7 | #define __INTEL_DSB_REGS_H__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | |
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| 11 | /* This register controls the Display State Buffer (DSB) engines. */ |
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| 12 | #define _DSBSL_INSTANCE_BASE 0x70B00 |
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| 13 | #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \ |
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| 14 | (pipe) * 0x1000 + (id) * 0x100) |
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| 15 | #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) |
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| 16 | #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) |
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| 17 | #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) |
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| 18 | #define DSB_ENABLE REG_BIT(31) |
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| 19 | #define DSB_BUF_REITERATE REG_BIT(29) |
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| 20 | #define DSB_WAIT_FOR_VBLANK REG_BIT(28) |
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| 21 | #define DSB_WAIT_FOR_LINE_IN REG_BIT(27) |
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| 22 | #define DSB_HALT REG_BIT(16) |
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| 23 | #define DSB_NON_POSTED REG_BIT(8) |
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| 24 | #define DSB_STATUS_BUSY REG_BIT(0) |
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| 25 | #define DSB_MMIOCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xc) |
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| 26 | #define DSB_MMIO_DEAD_CLOCKS_ENABLE REG_BIT(31) |
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| 27 | #define DSB_MMIO_DEAD_CLOCKS_COUNT_MASK REG_GENMASK(15, 8) |
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| 28 | #define DSB_MMIO_DEAD_CLOCKS_COUNT(x) REG_FIELD_PREP(DSB_MMIO_DEAD_CLOCK_COUNT_MASK, (x)) |
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| 29 | #define DSB_MMIO_CYCLES_MASK REG_GENMASK(7, 0) |
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| 30 | #define DSB_MMIO_CYCLES(x) REG_FIELD_PREP(DSB_MMIO_CYCLES_MASK, (x)) |
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| 31 | #define DSB_POLLFUNC(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x10) |
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| 32 | #define DSB_POLL_ENABLE REG_BIT(31) |
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| 33 | #define DSB_POLL_WAIT_MASK REG_GENMASK(30, 23) |
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| 34 | #define DSB_POLL_WAIT(x) REG_FIELD_PREP(DSB_POLL_WAIT_MASK, (x)) /* usec */ |
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| 35 | #define DSB_POLL_COUNT_MASK REG_GENMASK(22, 15) |
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| 36 | #define DSB_POLL_COUNT(x) REG_FIELD_PREP(DSB_POLL_COUNT_MASK, (x)) |
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| 37 | #define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14) |
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| 38 | #define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c) |
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| 39 | #define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24) |
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| 40 | #define DSB_HP_IDLE_STATUS REG_BIT(31) |
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| 41 | #define DSB_DEWAKE_STATUS REG_BIT(30) |
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| 42 | #define DSB_REQARB_SM_STATE_MASK REG_GENMASK(29, 27) |
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| 43 | #define DSB_SAFE_WINDOW_LIVE REG_BIT(26) |
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| 44 | #define DSB_VTDFAULT_ARB_SM_STATE_MASK REG_GENMASK(25, 23) |
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| 45 | #define DSB_TLBTRANS_SM_STATE_MASK REG_GENMASK(21, 20) |
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| 46 | #define DSB_SAFE_WINDOW REG_BIT(19) |
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| 47 | #define DSB_POINTERS_SM_STATE_MASK REG_GENMASK(18, 17) |
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| 48 | #define DSB_BUSY_ON_DELAYED_VBLANK REG_BIT(16) |
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| 49 | #define DSB_MMIO_ARB_SM_STATE_MASK REG_GENMASK(15, 13) |
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| 50 | #define DSB_MMIO_INST_SM_STATE_MASK REG_GENMASK(11, 7) |
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| 51 | #define DSB_RESET_SM_STATE_MASK REG_GENMASK(5, 4) |
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| 52 | #define DSB_RUN_SM_STATE_MASK REG_GENMASK(2, 0) |
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| 53 | #define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28) |
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| 54 | #define DSB_ATS_FAULT_INT_EN REG_BIT(20) |
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| 55 | #define DSB_GTT_FAULT_INT_EN REG_BIT(19) |
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| 56 | #define DSB_RSPTIMEOUT_INT_EN REG_BIT(18) |
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| 57 | #define DSB_POLL_ERR_INT_EN REG_BIT(17) |
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| 58 | #define DSB_PROG_INT_EN REG_BIT(16) |
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| 59 | #define DSB_ATS_FAULT_INT_STATUS REG_BIT(4) |
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| 60 | #define DSB_GTT_FAULT_INT_STATUS REG_BIT(3) |
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| 61 | #define DSB_RSPTIMEOUT_INT_STATUS REG_BIT(2) |
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| 62 | #define DSB_POLL_ERR_INT_STATUS REG_BIT(1) |
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| 63 | #define DSB_PROG_INT_STATUS REG_BIT(0) |
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| 64 | #define DSB_CURRENT_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x2c) |
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| 65 | #define DSB_RM_TIMEOUT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x30) |
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| 66 | #define DSB_RM_CLAIM_TIMEOUT REG_BIT(31) |
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| 67 | #define DSB_RM_READY_TIMEOUT REG_BIT(30) |
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| 68 | #define DSB_RM_CLAIM_TIMEOUT_COUNT_MASK REG_GENMASK(23, 16) |
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| 69 | #define DSB_RM_CLAIM_TIMEOUT_COUNT(x) REG_FIELD_PREP(DSB_RM_CLAIM_TIMEOUT_COUNT_MASK, (x)) /* clocks */ |
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| 70 | #define DSB_RM_READY_TIMEOUT_VALUE_MASK REG_GENMASK(15, 0) |
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| 71 | #define DSB_RM_READY_TIMEOUT_VALUE(x) REG_FIELD_PREP(DSB_RM_READY_TIMEOUT_VALUE, (x)) /* usec */ |
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| 72 | #define DSB_RMTIMEOUTREG_CAPTURE(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x34) |
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| 73 | #define DSB_PMCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x38) |
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| 74 | #define DSB_ENABLE_DEWAKE REG_BIT(31) |
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| 75 | #define DSB_SCANLINE_FOR_DEWAKE_MASK REG_GENMASK(30, 0) |
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| 76 | #define DSB_SCANLINE_FOR_DEWAKE(x) REG_FIELD_PREP(DSB_SCANLINE_FOR_DEWAKE_MASK, (x)) |
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| 77 | #define DSB_PMCTRL_2(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x3c) |
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| 78 | #define DSB_MMIOGEN_DEWAKE_DIS REG_BIT(31) |
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| 79 | #define DSB_FORCE_DEWAKE REG_BIT(23) |
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| 80 | #define DSB_BLOCK_DEWAKE_EXTENSION REG_BIT(15) |
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| 81 | #define DSB_OVERRIDE_DC5_DC6_OK REG_BIT(7) |
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| 82 | #define DSB_PF_LN_LOWER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x40) |
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| 83 | #define DSB_PF_LN_UPPER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x44) |
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| 84 | #define DSB_BUFRPT_CNT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x48) |
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| 85 | #define DSB_CHICKEN(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xf0) |
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| 86 | #define DSB_FORCE_DMA_SYNC_RESET REG_BIT(31) |
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| 87 | #define DSB_FORCE_VTD_ENGIE_RESET REG_BIT(30) |
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| 88 | #define DSB_DISABLE_IPC_DEMOTE REG_BIT(29) |
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| 89 | #define DSB_SKIP_WAITS_EN REG_BIT(23) |
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| 90 | #define DSB_EXTEND_HP_IDLE REG_BIT(16) |
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| 91 | #define DSB_CTRL_WAIT_SAFE_WINDOW REG_BIT(15) |
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| 92 | #define DSB_CTRL_NO_WAIT_VBLANK REG_BIT(14) |
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| 93 | #define DSB_INST_WAIT_SAFE_WINDOW REG_BIT(7) |
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| 94 | #define DSB_INST_NO_WAIT_VBLANK REG_BIT(6) |
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| 95 | #define DSB_MMIOGEN_DEWAKE_DIS_CHICKEN REG_BIT(2) |
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| 96 | #define DSB_DISABLE_MMIO_COUNT_FOR_INDEXED REG_BIT(0) |
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| 97 | |
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| 98 | #endif /* __INTEL_DSB_REGS_H__ */ |
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| 99 | |
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