| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2022 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_DVO_REGS_H__ |
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| 7 | #define __INTEL_DVO_REGS_H__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | |
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| 11 | #define _DVOA 0x61120 |
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| 12 | #define _DVOB 0x61140 |
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| 13 | #define _DVOC 0x61160 |
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| 14 | #define DVO(port) _MMIO_PORT((port), _DVOA, _DVOB) |
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| 15 | #define DVO_ENABLE REG_BIT(31) |
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| 16 | #define DVO_PIPE_SEL_MASK REG_BIT(30) |
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| 17 | #define DVO_PIPE_SEL(pipe) REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe)) |
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| 18 | #define DVO_PIPE_STALL_MASK REG_GENMASK(29, 28) |
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| 19 | #define DVO_PIPE_STALL_UNUSED REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0) |
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| 20 | #define DVO_PIPE_STALL REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1) |
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| 21 | #define DVO_PIPE_STALL_TV REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2) |
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| 22 | #define DVO_INTERRUPT_SELECT REG_BIT(27) |
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| 23 | #define DVO_DEDICATED_INT_ENABLE REG_BIT(26) |
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| 24 | #define DVO_PRESERVE_MASK REG_GENMASK(25, 24) |
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| 25 | #define DVO_USE_VGA_SYNC REG_BIT(15) |
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| 26 | #define DVO_DATA_ORDER_MASK REG_BIT(14) |
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| 27 | #define DVO_DATA_ORDER_I740 REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0) |
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| 28 | #define DVO_DATA_ORDER_FP REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1) |
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| 29 | #define DVO_VSYNC_DISABLE REG_BIT(11) |
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| 30 | #define DVO_HSYNC_DISABLE REG_BIT(10) |
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| 31 | #define DVO_VSYNC_TRISTATE REG_BIT(9) |
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| 32 | #define DVO_HSYNC_TRISTATE REG_BIT(8) |
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| 33 | #define DVO_BORDER_ENABLE REG_BIT(7) |
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| 34 | #define DVO_ACT_DATA_ORDER_MASK REG_BIT(6) |
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| 35 | #define DVO_ACT_DATA_ORDER_RGGB REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0) |
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| 36 | #define DVO_ACT_DATA_ORDER_GBRG REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1) |
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| 37 | #define DVO_ACT_DATA_ORDER_GBRG_ERRATA REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0) |
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| 38 | #define DVO_ACT_DATA_ORDER_RGGB_ERRATA REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1) |
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| 39 | #define DVO_VSYNC_ACTIVE_HIGH REG_BIT(4) |
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| 40 | #define DVO_HSYNC_ACTIVE_HIGH REG_BIT(3) |
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| 41 | #define DVO_BLANK_ACTIVE_HIGH REG_BIT(2) |
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| 42 | #define DVO_OUTPUT_CSTATE_PIXELS REG_BIT(1) /* SDG only */ |
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| 43 | #define DVO_OUTPUT_SOURCE_SIZE_PIXELS REG_BIT(0) /* SDG only */ |
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| 44 | |
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| 45 | #define _DVOA_SRCDIM 0x61124 |
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| 46 | #define _DVOB_SRCDIM 0x61144 |
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| 47 | #define _DVOC_SRCDIM 0x61164 |
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| 48 | #define DVO_SRCDIM(port) _MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM) |
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| 49 | #define DVO_SRCDIM_HORIZONTAL_MASK REG_GENMASK(22, 12) |
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| 50 | #define DVO_SRCDIM_HORIZONTAL(x) REG_FIELD_PREP(DVO_SRCDIM_HORIZONTAL_MASK, (x)) |
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| 51 | #define DVO_SRCDIM_VERTICAL_MASK REG_GENMASK(10, 0) |
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| 52 | #define DVO_SRCDIM_VERTICAL(x) REG_FIELD_PREP(DVO_SRCDIM_VERTICAL_MASK, (x)) |
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| 53 | |
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| 54 | #endif /* __INTEL_DVO_REGS_H__ */ |
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| 55 | |
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