| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2019 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_GMBUS_H__ |
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| 7 | #define __INTEL_GMBUS_H__ |
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| 8 | |
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| 9 | #include <linux/types.h> |
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| 10 | |
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| 11 | struct drm_i915_private; |
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| 12 | struct i2c_adapter; |
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| 13 | |
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| 14 | #define GMBUS_PIN_DISABLED 0 |
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| 15 | #define GMBUS_PIN_SSC 1 |
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| 16 | #define GMBUS_PIN_VGADDC 2 |
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| 17 | #define GMBUS_PIN_PANEL 3 |
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| 18 | #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */ |
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| 19 | #define GMBUS_PIN_DPC 4 /* HDMIC */ |
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| 20 | #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ |
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| 21 | #define GMBUS_PIN_DPD 6 /* HDMID */ |
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| 22 | #define GMBUS_PIN_RESERVED 7 /* 7 reserved */ |
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| 23 | #define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */ |
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| 24 | #define GMBUS_PIN_2_BXT 2 |
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| 25 | #define GMBUS_PIN_3_BXT 3 |
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| 26 | #define GMBUS_PIN_4_CNP 4 |
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| 27 | #define GMBUS_PIN_5_MTP 5 |
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| 28 | #define GMBUS_PIN_9_TC1_ICP 9 |
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| 29 | #define GMBUS_PIN_10_TC2_ICP 10 |
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| 30 | #define GMBUS_PIN_11_TC3_ICP 11 |
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| 31 | #define GMBUS_PIN_12_TC4_ICP 12 |
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| 32 | #define GMBUS_PIN_13_TC5_TGP 13 |
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| 33 | #define GMBUS_PIN_14_TC6_TGP 14 |
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| 34 | |
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| 35 | #define GMBUS_NUM_PINS 15 /* including 0 */ |
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| 36 | |
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| 37 | int intel_gmbus_setup(struct drm_i915_private *dev_priv); |
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| 38 | void intel_gmbus_teardown(struct drm_i915_private *dev_priv); |
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| 39 | bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
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| 40 | unsigned int pin); |
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| 41 | int intel_gmbus_output_aksv(struct i2c_adapter *adapter); |
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| 42 | |
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| 43 | struct i2c_adapter * |
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| 44 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); |
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| 45 | void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
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| 46 | bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter); |
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| 47 | void intel_gmbus_reset(struct drm_i915_private *dev_priv); |
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| 48 | |
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| 49 | void intel_gmbus_irq_handler(struct drm_i915_private *i915); |
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| 50 | |
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| 51 | #endif /* __INTEL_GMBUS_H__ */ |
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| 52 | |
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