1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34
35#include <linux/pm_qos.h>
36
37#include <drm/ttm/ttm_device.h>
38
39#include "display/intel_display_limits.h"
40#include "display/intel_display_core.h"
41
42#include "gem/i915_gem_context_types.h"
43#include "gem/i915_gem_shrinker.h"
44#include "gem/i915_gem_stolen.h"
45
46#include "gt/intel_engine.h"
47#include "gt/intel_gt_types.h"
48#include "gt/intel_region_lmem.h"
49#include "gt/intel_workarounds.h"
50#include "gt/uc/intel_uc.h"
51
52#include "soc/intel_pch.h"
53
54#include "i915_drm_client.h"
55#include "i915_gem.h"
56#include "i915_gpu_error.h"
57#include "i915_params.h"
58#include "i915_perf_types.h"
59#include "i915_scheduler.h"
60#include "i915_utils.h"
61#include "intel_device_info.h"
62#include "intel_memory_region.h"
63#include "intel_runtime_pm.h"
64#include "intel_step.h"
65#include "intel_uncore.h"
66
67struct drm_i915_clock_gating_funcs;
68struct vlv_s0ix_state;
69struct intel_pxp;
70
71#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
72
73/* Data Stolen Memory (DSM) aka "i915 stolen memory" */
74struct i915_dsm {
75 /*
76 * The start and end of DSM which we can optionally use to create GEM
77 * objects backed by stolen memory.
78 *
79 * Note that usable_size tells us exactly how much of this we are
80 * actually allowed to use, given that some portion of it is in fact
81 * reserved for use by hardware functions.
82 */
83 struct resource stolen;
84
85 /*
86 * Reserved portion of DSM.
87 */
88 struct resource reserved;
89
90 /*
91 * Total size minus reserved ranges.
92 *
93 * DSM is segmented in hardware with different portions offlimits to
94 * certain functions.
95 *
96 * The drm_mm is initialised to the total accessible range, as found
97 * from the PCI config. On Broadwell+, this is further restricted to
98 * avoid the first page! The upper end of DSM is reserved for hardware
99 * functions and similarly removed from the accessible range.
100 */
101 resource_size_t usable_size;
102};
103
104struct i915_suspend_saved_registers {
105 u32 saveDSPARB;
106 u32 saveSWF0[16];
107 u32 saveSWF1[16];
108 u32 saveSWF3[3];
109 u16 saveGCDGMBUS;
110};
111
112#define MAX_L3_SLICES 2
113struct intel_l3_parity {
114 u32 *remap_info[MAX_L3_SLICES];
115 struct work_struct error_work;
116 int which_slice;
117};
118
119struct i915_gem_mm {
120 /*
121 * Shortcut for the stolen region. This points to either
122 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
123 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
124 * support stolen.
125 */
126 struct intel_memory_region *stolen_region;
127 /** Memory allocator for GTT stolen memory */
128 struct drm_mm stolen;
129 /** Protects the usage of the GTT stolen memory allocator. This is
130 * always the inner lock when overlapping with struct_mutex. */
131 struct mutex stolen_lock;
132
133 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
134 spinlock_t obj_lock;
135
136 /**
137 * List of objects which are purgeable.
138 */
139 struct list_head purge_list;
140
141 /**
142 * List of objects which have allocated pages and are shrinkable.
143 */
144 struct list_head shrink_list;
145
146 /**
147 * List of objects which are pending destruction.
148 */
149 struct llist_head free_list;
150 struct work_struct free_work;
151 /**
152 * Count of objects pending destructions. Used to skip needlessly
153 * waiting on an RCU barrier if no objects are waiting to be freed.
154 */
155 atomic_t free_count;
156
157 /**
158 * tmpfs instance used for shmem backed objects
159 */
160 struct vfsmount *gemfs;
161
162 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
163
164 struct notifier_block oom_notifier;
165 struct notifier_block vmap_notifier;
166 struct shrinker *shrinker;
167
168#ifdef CONFIG_MMU_NOTIFIER
169 /**
170 * notifier_lock for mmu notifiers, memory may not be allocated
171 * while holding this lock.
172 */
173 rwlock_t notifier_lock;
174#endif
175
176 /* shrinker accounting, also useful for userland debugging */
177 u64 shrink_memory;
178 u32 shrink_count;
179};
180
181struct i915_virtual_gpu {
182 struct mutex lock; /* serialises sending of g2v_notify command pkts */
183 bool active;
184 u32 caps;
185 u32 *initial_mmio;
186 u8 *initial_cfg_space;
187 struct list_head entry;
188};
189
190struct i915_selftest_stash {
191 atomic_t counter;
192 struct ida mock_region_instances;
193};
194
195struct drm_i915_private {
196 struct drm_device drm;
197
198 struct intel_display display;
199
200 /* FIXME: Device release actions should all be moved to drmm_ */
201 bool do_release;
202
203 /* i915 device parameters */
204 struct i915_params params;
205
206 const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */
207 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
208 struct intel_driver_caps caps;
209
210 struct i915_dsm dsm;
211
212 struct intel_uncore uncore;
213 struct intel_uncore_mmio_debug mmio_debug;
214
215 struct i915_virtual_gpu vgpu;
216
217 struct intel_gvt *gvt;
218
219 struct {
220 struct pci_dev *pdev;
221 struct resource mch_res;
222 bool mchbar_need_disable;
223 } gmch;
224
225 /*
226 * Chaining user engines happens in multiple stages, starting with a
227 * simple lock-less linked list created by intel_engine_add_user(),
228 * which later gets sorted and converted to an intermediate regular
229 * list, just to be converted once again to its final rb tree structure
230 * in intel_engines_driver_register().
231 *
232 * Make sure to use the right iterator helper, depending on if the code
233 * in question runs before or after intel_engines_driver_register() --
234 * for_each_uabi_engine() can only be used afterwards!
235 */
236 union {
237 struct llist_head uabi_engines_llist;
238 struct list_head uabi_engines_list;
239 struct rb_root uabi_engines;
240 };
241 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
242
243 /* protects the irq masks */
244 spinlock_t irq_lock;
245
246 bool display_irqs_enabled;
247
248 /* Sideband mailbox protection */
249 struct mutex sb_lock;
250 struct pm_qos_request sb_qos;
251
252 /** Cached value of IMR to avoid reads in updating the bitfield */
253 union {
254 u32 irq_mask;
255 u32 de_irq_mask[I915_MAX_PIPES];
256 };
257 u32 pipestat_irq_mask[I915_MAX_PIPES];
258
259 bool preserve_bios_swizzle;
260
261 unsigned int fsb_freq, mem_freq, is_ddr3;
262 unsigned int skl_preferred_vco_freq;
263
264 unsigned int max_dotclk_freq;
265 unsigned int hpll_freq;
266 unsigned int czclk_freq;
267
268 /**
269 * wq - Driver workqueue for GEM.
270 *
271 * NOTE: Work items scheduled here are not allowed to grab any modeset
272 * locks, for otherwise the flushing done in the pageflip code will
273 * result in deadlocks.
274 */
275 struct workqueue_struct *wq;
276
277 /**
278 * unordered_wq - internal workqueue for unordered work
279 *
280 * This workqueue should be used for all unordered work
281 * scheduling within i915, which used to be scheduled on the
282 * system_wq before moving to a driver instance due
283 * deprecation of flush_scheduled_work().
284 */
285 struct workqueue_struct *unordered_wq;
286
287 /* pm private clock gating functions */
288 const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
289
290 /* PCH chipset type */
291 enum intel_pch pch_type;
292 unsigned short pch_id;
293
294 unsigned long gem_quirks;
295
296 struct i915_gem_mm mm;
297
298 struct intel_l3_parity l3_parity;
299
300 /*
301 * edram size in MB.
302 * Cannot be determined by PCIID. You must always read a register.
303 */
304 u32 edram_size_mb;
305
306 struct i915_gpu_error gpu_error;
307
308 u32 suspend_count;
309 struct i915_suspend_saved_registers regfile;
310 struct vlv_s0ix_state *vlv_s0ix_state;
311
312 struct dram_info {
313 bool wm_lv_0_adjust_needed;
314 u8 num_channels;
315 bool symmetric_memory;
316 enum intel_dram_type {
317 INTEL_DRAM_UNKNOWN,
318 INTEL_DRAM_DDR3,
319 INTEL_DRAM_DDR4,
320 INTEL_DRAM_LPDDR3,
321 INTEL_DRAM_LPDDR4,
322 INTEL_DRAM_DDR5,
323 INTEL_DRAM_LPDDR5,
324 } type;
325 u8 num_qgv_points;
326 u8 num_psf_gv_points;
327 } dram_info;
328
329 struct intel_runtime_pm runtime_pm;
330
331 struct i915_perf perf;
332
333 struct i915_hwmon *hwmon;
334
335 struct intel_gt *gt[I915_MAX_GT];
336
337 struct kobject *sysfs_gt;
338
339 /* Quick lookup of media GT (current platforms only have one) */
340 struct intel_gt *media_gt;
341
342 struct {
343 struct i915_gem_contexts {
344 spinlock_t lock; /* locks list */
345 struct list_head list;
346 } contexts;
347
348 /*
349 * We replace the local file with a global mappings as the
350 * backing storage for the mmap is on the device and not
351 * on the struct file, and we do not want to prolong the
352 * lifetime of the local fd. To minimise the number of
353 * anonymous inodes we create, we use a global singleton to
354 * share the global mapping.
355 */
356 struct file *mmap_singleton;
357 } gem;
358
359 struct intel_pxp *pxp;
360
361 /* For i915gm/i945gm vblank irq workaround */
362 u8 vblank_enabled;
363
364 bool irq_enabled;
365
366 struct i915_pmu pmu;
367
368 /* The TTM device structure. */
369 struct ttm_device bdev;
370
371 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
372
373 /*
374 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
375 * will be rejected. Instead look for a better place.
376 */
377};
378
379static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
380{
381 return container_of(dev, struct drm_i915_private, drm);
382}
383
384static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
385{
386 return dev_get_drvdata(dev: kdev);
387}
388
389static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
390{
391 return pci_get_drvdata(pdev);
392}
393
394static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
395{
396 return i915->gt[0];
397}
398
399/* Simple iterator over all initialised engines */
400#define for_each_engine(engine__, gt__, id__) \
401 for ((id__) = 0; \
402 (id__) < I915_NUM_ENGINES; \
403 (id__)++) \
404 for_each_if ((engine__) = (gt__)->engine[(id__)])
405
406/* Iterator over subset of engines selected by mask */
407#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
408 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
409 (tmp__) ? \
410 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
411 0;)
412
413#define rb_to_uabi_engine(rb) \
414 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
415
416#define for_each_uabi_engine(engine__, i915__) \
417 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
418 (engine__); \
419 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
420
421#define for_each_uabi_class_engine(engine__, class__, i915__) \
422 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
423 (engine__) && (engine__)->uabi_class == (class__); \
424 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
425
426#define INTEL_INFO(i915) ((i915)->__info)
427#define RUNTIME_INFO(i915) (&(i915)->__runtime)
428#define DRIVER_CAPS(i915) (&(i915)->caps)
429
430#define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)
431
432#define IP_VER(ver, rel) ((ver) << 8 | (rel))
433
434#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)
435#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
436 RUNTIME_INFO(i915)->graphics.ip.rel)
437#define IS_GRAPHICS_VER(i915, from, until) \
438 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
439
440#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
441#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
442 RUNTIME_INFO(i915)->media.ip.rel)
443#define IS_MEDIA_VER(i915, from, until) \
444 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
445
446#define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision)
447
448#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
449#define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
450#define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
451#define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
452
453#define IS_DISPLAY_STEP(__i915, since, until) \
454 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
455 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
456
457#define IS_GRAPHICS_STEP(__i915, since, until) \
458 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
459 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
460
461#define IS_MEDIA_STEP(__i915, since, until) \
462 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
463 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
464
465#define IS_BASEDIE_STEP(__i915, since, until) \
466 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
467 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
468
469static __always_inline unsigned int
470__platform_mask_index(const struct intel_runtime_info *info,
471 enum intel_platform p)
472{
473 const unsigned int pbits =
474 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
475
476 /* Expand the platform_mask array if this fails. */
477 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
478 pbits * ARRAY_SIZE(info->platform_mask));
479
480 return p / pbits;
481}
482
483static __always_inline unsigned int
484__platform_mask_bit(const struct intel_runtime_info *info,
485 enum intel_platform p)
486{
487 const unsigned int pbits =
488 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
489
490 return p % pbits + INTEL_SUBPLATFORM_BITS;
491}
492
493static inline u32
494intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
495{
496 const unsigned int pi = __platform_mask_index(info, p);
497
498 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
499}
500
501static __always_inline bool
502IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
503{
504 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
505 const unsigned int pi = __platform_mask_index(info, p);
506 const unsigned int pb = __platform_mask_bit(info, p);
507
508 BUILD_BUG_ON(!__builtin_constant_p(p));
509
510 return info->platform_mask[pi] & BIT(pb);
511}
512
513static __always_inline bool
514IS_SUBPLATFORM(const struct drm_i915_private *i915,
515 enum intel_platform p, unsigned int s)
516{
517 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
518 const unsigned int pi = __platform_mask_index(info, p);
519 const unsigned int pb = __platform_mask_bit(info, p);
520 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
521 const u32 mask = info->platform_mask[pi];
522
523 BUILD_BUG_ON(!__builtin_constant_p(p));
524 BUILD_BUG_ON(!__builtin_constant_p(s));
525 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
526
527 /* Shift and test on the MSB position so sign flag can be used. */
528 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
529}
530
531#define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile)
532#define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx)
533
534#define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830)
535#define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G)
536#define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X)
537#define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G)
538#define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G)
539#define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM)
540#define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G)
541#define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM)
542#define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G)
543#define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM)
544#define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45)
545#define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45)
546#define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915))
547#define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW)
548#define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33)
549#define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE)
550#define IS_IRONLAKE_M(i915) \
551 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
552#define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE)
553#define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE)
554#define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \
555 INTEL_INFO(i915)->gt == 1)
556#define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW)
557#define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW)
558#define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL)
559#define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL)
560#define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE)
561#define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON)
562#define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE)
563#define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE)
564#define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE)
565#define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE)
566#define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE)
567#define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE)
568#define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE)
569#define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE)
570#define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE)
571#define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
572#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
573#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
574#define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV)
575#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
576#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
577#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
578
579#define IS_DG2_G10(i915) \
580 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
581#define IS_DG2_G11(i915) \
582 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
583#define IS_DG2_G12(i915) \
584 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
585#define IS_RAPTORLAKE_S(i915) \
586 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
587#define IS_ALDERLAKE_P_N(i915) \
588 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
589#define IS_RAPTORLAKE_P(i915) \
590 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
591#define IS_RAPTORLAKE_U(i915) \
592 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
593#define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
594 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
595#define IS_BROADWELL_ULT(i915) \
596 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
597#define IS_BROADWELL_ULX(i915) \
598 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
599#define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \
600 INTEL_INFO(i915)->gt == 3)
601#define IS_HASWELL_ULT(i915) \
602 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
603#define IS_HASWELL_GT3(i915) (IS_HASWELL(i915) && \
604 INTEL_INFO(i915)->gt == 3)
605#define IS_HASWELL_GT1(i915) (IS_HASWELL(i915) && \
606 INTEL_INFO(i915)->gt == 1)
607/* ULX machines are also considered ULT. */
608#define IS_HASWELL_ULX(i915) \
609 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
610#define IS_SKYLAKE_ULT(i915) \
611 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
612#define IS_SKYLAKE_ULX(i915) \
613 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
614#define IS_KABYLAKE_ULT(i915) \
615 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
616#define IS_KABYLAKE_ULX(i915) \
617 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
618#define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \
619 INTEL_INFO(i915)->gt == 2)
620#define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \
621 INTEL_INFO(i915)->gt == 3)
622#define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \
623 INTEL_INFO(i915)->gt == 4)
624#define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \
625 INTEL_INFO(i915)->gt == 2)
626#define IS_KABYLAKE_GT3(i915) (IS_KABYLAKE(i915) && \
627 INTEL_INFO(i915)->gt == 3)
628#define IS_COFFEELAKE_ULT(i915) \
629 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
630#define IS_COFFEELAKE_ULX(i915) \
631 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
632#define IS_COFFEELAKE_GT2(i915) (IS_COFFEELAKE(i915) && \
633 INTEL_INFO(i915)->gt == 2)
634#define IS_COFFEELAKE_GT3(i915) (IS_COFFEELAKE(i915) && \
635 INTEL_INFO(i915)->gt == 3)
636
637#define IS_COMETLAKE_ULT(i915) \
638 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
639#define IS_COMETLAKE_ULX(i915) \
640 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
641#define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \
642 INTEL_INFO(i915)->gt == 2)
643
644#define IS_ICL_WITH_PORT_F(i915) \
645 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
646
647#define IS_TIGERLAKE_UY(i915) \
648 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
649
650#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
651 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
652
653#define IS_PVC_BD_STEP(__i915, since, until) \
654 (IS_PONTEVECCHIO(__i915) && \
655 IS_BASEDIE_STEP(__i915, since, until))
656
657#define IS_PVC_CT_STEP(__i915, since, until) \
658 (IS_PONTEVECCHIO(__i915) && \
659 IS_GRAPHICS_STEP(__i915, since, until))
660
661#define IS_LP(i915) (INTEL_INFO(i915)->is_lp)
662#define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915))
663#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915))
664
665#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
666#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
667
668#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
669 unsigned int first__ = (first); \
670 unsigned int count__ = (count); \
671 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
672})
673
674#define ENGINE_INSTANCES_MASK(gt, first, count) \
675 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
676
677#define RCS_MASK(gt) \
678 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
679#define BCS_MASK(gt) \
680 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
681#define VDBOX_MASK(gt) \
682 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
683#define VEBOX_MASK(gt) \
684 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
685#define CCS_MASK(gt) \
686 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
687
688#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
689
690/*
691 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
692 * All later gens can run the final buffer from the ppgtt
693 */
694#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
695
696#define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
697#define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
698#define HAS_EDRAM(i915) ((i915)->edram_size_mb)
699#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
700#define HAS_WT(i915) HAS_EDRAM(i915)
701
702#define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical)
703
704#define HAS_LOGICAL_RING_CONTEXTS(i915) \
705 (INTEL_INFO(i915)->has_logical_ring_contexts)
706#define HAS_LOGICAL_RING_ELSQ(i915) \
707 (INTEL_INFO(i915)->has_logical_ring_elsq)
708
709#define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)
710
711#define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
712#define HAS_PPGTT(i915) \
713 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)
714#define HAS_FULL_PPGTT(i915) \
715 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)
716
717#define HAS_PAGE_SIZES(i915, sizes) ({ \
718 GEM_BUG_ON((sizes) == 0); \
719 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
720})
721
722/* Early gen2 have a totally busted CS tlb and require pinned batches. */
723#define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915))
724
725#define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \
726 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)
727
728/* WaRsDisableCoarsePowerGating:skl,cnl */
729#define NEEDS_WaRsDisableCoarsePowerGating(i915) \
730 (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
731
732/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
733 * rows, which changed the alignment requirements and fence programming.
734 */
735#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
736 !(IS_I915G(i915) || IS_I915GM(i915)))
737
738#define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
739#define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
740#define HAS_RC6pp(i915) (false) /* HW was never validated */
741
742#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
743
744#define HAS_HECI_PXP(i915) \
745 (INTEL_INFO(i915)->has_heci_pxp)
746
747#define HAS_HECI_GSCFI(i915) \
748 (INTEL_INFO(i915)->has_heci_gscfi)
749
750#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
751
752#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
753#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
754
755#define HAS_OA_BPC_REPORTING(i915) \
756 (INTEL_INFO(i915)->has_oa_bpc_reporting)
757#define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \
758 (INTEL_INFO(i915)->has_oa_slice_contrib_limits)
759#define HAS_OAM(i915) \
760 (INTEL_INFO(i915)->has_oam)
761
762/*
763 * Set this flag, when platform requires 64K GTT page sizes or larger for
764 * device local memory access.
765 */
766#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
767
768#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
769#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
770
771#define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list)
772
773/*
774 * Platform has the dedicated compression control state for each lmem surfaces
775 * stored in lmem to support the 3D and media compression formats.
776 */
777#define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs)
778
779#define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc)
780
781#define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu)
782
783#define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
784
785#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
786
787#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
788
789/* DPF == dynamic parity feature */
790#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
791#define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \
792 2 : HAS_L3_DPF(i915))
793
794#define HAS_GUC_DEPRIVILEGE(i915) \
795 (INTEL_INFO(i915)->has_guc_deprivilege)
796
797#define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation)
798
799#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
800
801#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
802
803#define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
804 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
805
806#endif
807

source code of linux/drivers/gpu/drm/i915/i915_drv.h