1 | /* SPDX-License-Identifier: MIT */ |
2 | /* |
3 | * Copyright © 2020,2021 Intel Corporation |
4 | */ |
5 | |
6 | #ifndef __INTEL_STEP_H__ |
7 | #define __INTEL_STEP_H__ |
8 | |
9 | #include <linux/types.h> |
10 | |
11 | struct drm_i915_private; |
12 | |
13 | struct intel_step_info { |
14 | /* |
15 | * It is expected to have 4 number steps per letter. Deviation from |
16 | * the expectation breaks gmd_to_intel_step(). |
17 | */ |
18 | u8 graphics_step; /* Represents the compute tile on Xe_HPC */ |
19 | u8 display_step; |
20 | u8 media_step; |
21 | u8 basedie_step; |
22 | }; |
23 | |
24 | #define STEP_ENUM_VAL(name) STEP_##name, |
25 | |
26 | #define STEP_NAME_LIST(func) \ |
27 | func(A0) \ |
28 | func(A1) \ |
29 | func(A2) \ |
30 | func(A3) \ |
31 | func(B0) \ |
32 | func(B1) \ |
33 | func(B2) \ |
34 | func(B3) \ |
35 | func(C0) \ |
36 | func(C1) \ |
37 | func(C2) \ |
38 | func(C3) \ |
39 | func(D0) \ |
40 | func(D1) \ |
41 | func(D2) \ |
42 | func(D3) \ |
43 | func(E0) \ |
44 | func(E1) \ |
45 | func(E2) \ |
46 | func(E3) \ |
47 | func(F0) \ |
48 | func(F1) \ |
49 | func(F2) \ |
50 | func(F3) \ |
51 | func(G0) \ |
52 | func(G1) \ |
53 | func(G2) \ |
54 | func(G3) \ |
55 | func(H0) \ |
56 | func(H1) \ |
57 | func(H2) \ |
58 | func(H3) \ |
59 | func(I0) \ |
60 | func(I1) \ |
61 | func(I2) \ |
62 | func(I3) \ |
63 | func(J0) \ |
64 | func(J1) \ |
65 | func(J2) \ |
66 | func(J3) |
67 | |
68 | /* |
69 | * Symbolic steppings that do not match the hardware. These are valid both as gt |
70 | * and display steppings as symbolic names. |
71 | */ |
72 | enum intel_step { |
73 | STEP_NONE = 0, |
74 | STEP_NAME_LIST(STEP_ENUM_VAL) |
75 | STEP_FUTURE, |
76 | STEP_FOREVER, |
77 | }; |
78 | |
79 | void intel_step_init(struct drm_i915_private *i915); |
80 | const char *intel_step_name(enum intel_step step); |
81 | const char *intel_display_step_name(struct drm_i915_private *i915); |
82 | |
83 | #endif /* __INTEL_STEP_H__ */ |
84 | |