| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2023 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_LVDS_REGS_H__ |
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| 7 | #define __INTEL_LVDS_REGS_H__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | |
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| 11 | /* LVDS port control */ |
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| 12 | #define LVDS _MMIO(0x61180) |
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| 13 | /* |
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| 14 | * Enables the LVDS port. This bit must be set before DPLLs are enabled, as |
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| 15 | * the DPLL semantics change when the LVDS is assigned to that pipe. |
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| 16 | */ |
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| 17 | #define LVDS_PORT_EN REG_BIT(31) |
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| 18 | /* Selects pipe B for LVDS data. Must be set on pre-965. */ |
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| 19 | #define LVDS_PIPE_SEL_MASK REG_BIT(30) |
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| 20 | #define LVDS_PIPE_SEL(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK, (pipe)) |
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| 21 | #define LVDS_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29) |
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| 22 | #define LVDS_PIPE_SEL_CPT(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK_CPT, (pipe)) |
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| 23 | /* LVDS dithering flag on 965/g4x platform */ |
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| 24 | #define LVDS_ENABLE_DITHER REG_BIT(25) |
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| 25 | /* LVDS sync polarity flags. Set to invert (i.e. negative) */ |
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| 26 | #define LVDS_VSYNC_POLARITY REG_BIT(21) |
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| 27 | #define LVDS_HSYNC_POLARITY REG_BIT(20) |
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| 28 | |
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| 29 | /* Enable border for unscaled (or aspect-scaled) display */ |
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| 30 | #define LVDS_BORDER_ENABLE REG_BIT(15) |
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| 31 | /* |
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| 32 | * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per |
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| 33 | * pixel. |
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| 34 | */ |
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| 35 | #define LVDS_A0A2_CLKA_POWER_MASK REG_GENMASK(9, 8) |
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| 36 | #define LVDS_A0A2_CLKA_POWER_DOWN REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 0) |
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| 37 | #define LVDS_A0A2_CLKA_POWER_UP REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 3) |
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| 38 | /* |
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| 39 | * Controls the A3 data pair, which contains the additional LSBs for 24 bit |
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| 40 | * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be |
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| 41 | * on. |
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| 42 | */ |
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| 43 | #define LVDS_A3_POWER_MASK REG_GENMASK(7, 6) |
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| 44 | #define LVDS_A3_POWER_DOWN REG_FIELD_PREP(LVDS_A3_POWER_MASK, 0) |
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| 45 | #define LVDS_A3_POWER_UP REG_FIELD_PREP(LVDS_A3_POWER_MASK, 3) |
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| 46 | /* |
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| 47 | * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP |
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| 48 | * is set. |
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| 49 | */ |
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| 50 | #define LVDS_CLKB_POWER_MASK REG_GENMASK(5, 4) |
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| 51 | #define LVDS_CLKB_POWER_DOWN REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 0) |
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| 52 | #define LVDS_CLKB_POWER_UP REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 3) |
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| 53 | /* |
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| 54 | * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 |
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| 55 | * setting for whether we are in dual-channel mode. The B3 pair will |
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| 56 | * additionally only be powered up when LVDS_A3_POWER_UP is set. |
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| 57 | */ |
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| 58 | #define LVDS_B0B3_POWER_MASK REG_GENMASK(3, 2) |
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| 59 | #define LVDS_B0B3_POWER_DOWN REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 0) |
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| 60 | #define LVDS_B0B3_POWER_UP REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 3) |
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| 61 | |
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| 62 | #define PCH_LVDS _MMIO(0xe1180) |
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| 63 | #define LVDS_DETECTED REG_BIT(1) |
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| 64 | |
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| 65 | #endif /* __INTEL_LVDS_REGS_H__ */ |
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| 66 | |
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