| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2023 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_PPS_REGS_H__ |
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| 7 | #define __INTEL_PPS_REGS_H__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | |
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| 11 | /* Panel power sequencing */ |
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| 12 | #define PPS_BASE 0x61200 |
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| 13 | #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) |
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| 14 | #define PCH_PPS_BASE 0xC7200 |
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| 15 | |
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| 16 | #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display.pps.mmio_base - \ |
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| 17 | PPS_BASE + (reg) + \ |
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| 18 | (pps_idx) * 0x100) |
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| 19 | |
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| 20 | #define _PP_STATUS 0x61200 |
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| 21 | #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) |
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| 22 | #define PP_ON REG_BIT(31) |
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| 23 | /* |
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| 24 | * Indicates that all dependencies of the panel are on: |
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| 25 | * |
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| 26 | * - PLL enabled |
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| 27 | * - pipe enabled |
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| 28 | * - LVDS/DVOB/DVOC on |
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| 29 | */ |
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| 30 | #define PP_READY REG_BIT(30) |
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| 31 | #define PP_SEQUENCE_MASK REG_GENMASK(29, 28) |
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| 32 | #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0) |
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| 33 | #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1) |
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| 34 | #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2) |
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| 35 | #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27) |
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| 36 | #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0) |
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| 37 | #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0) |
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| 38 | #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1) |
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| 39 | #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2) |
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| 40 | #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3) |
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| 41 | #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8) |
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| 42 | #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9) |
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| 43 | #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa) |
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| 44 | #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb) |
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| 45 | #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) |
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| 46 | |
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| 47 | #define _PP_CONTROL 0x61204 |
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| 48 | #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) |
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| 49 | #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) |
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| 50 | #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) |
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| 51 | #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) |
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| 52 | #define EDP_FORCE_VDD REG_BIT(3) |
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| 53 | #define EDP_BLC_ENABLE REG_BIT(2) |
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| 54 | #define PANEL_POWER_RESET REG_BIT(1) |
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| 55 | #define PANEL_POWER_ON REG_BIT(0) |
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| 56 | |
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| 57 | #define _PP_ON_DELAYS 0x61208 |
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| 58 | #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) |
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| 59 | #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) |
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| 60 | #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) |
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| 61 | #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) |
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| 62 | #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2) |
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| 63 | #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3) |
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| 64 | #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port) |
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| 65 | #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16) |
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| 66 | #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) |
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| 67 | |
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| 68 | #define _PP_OFF_DELAYS 0x6120C |
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| 69 | #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) |
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| 70 | #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) |
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| 71 | #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) |
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| 72 | |
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| 73 | #define _PP_DIVISOR 0x61210 |
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| 74 | #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) |
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| 75 | #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) |
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| 76 | #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) |
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| 77 | |
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| 78 | #endif /* __INTEL_PPS_REGS_H__ */ |
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| 79 | |
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