1 | /* |
2 | * Copyright © 2006-2016 Intel Corporation |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
21 | * SOFTWARE. |
22 | * |
23 | * Authors: |
24 | * Eric Anholt <eric@anholt.net> |
25 | * |
26 | */ |
27 | |
28 | /* |
29 | * This information is private to VBT parsing in intel_bios.c. |
30 | * |
31 | * Please do NOT include anywhere else. |
32 | */ |
33 | #ifndef _INTEL_BIOS_PRIVATE |
34 | #error "intel_vbt_defs.h is private to intel_bios.c" |
35 | #endif |
36 | |
37 | #ifndef _INTEL_VBT_DEFS_H_ |
38 | #define _INTEL_VBT_DEFS_H_ |
39 | |
40 | #include "intel_bios.h" |
41 | |
42 | /** |
43 | * struct vbt_header - VBT Header structure |
44 | * @signature: VBT signature, always starts with "$VBT" |
45 | * @version: Version of this structure |
46 | * @header_size: Size of this structure |
47 | * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks) |
48 | * @vbt_checksum: Checksum |
49 | * @reserved0: Reserved |
50 | * @bdb_offset: Offset of &struct bdb_header from beginning of VBT |
51 | * @aim_offset: Offsets of add-in data blocks from beginning of VBT |
52 | */ |
53 | struct { |
54 | u8 [20]; |
55 | u16 ; |
56 | u16 ; |
57 | u16 ; |
58 | u8 ; |
59 | u8 ; |
60 | u32 ; |
61 | u32 [4]; |
62 | } __packed; |
63 | |
64 | /** |
65 | * struct bdb_header - BDB Header structure |
66 | * @signature: BDB signature "BIOS_DATA_BLOCK" |
67 | * @version: Version of the data block definitions |
68 | * @header_size: Size of this structure |
69 | * @bdb_size: Size of BDB (BDB Header and data blocks) |
70 | */ |
71 | struct { |
72 | u8 [16]; |
73 | u16 ; |
74 | u16 ; |
75 | u16 ; |
76 | } __packed; |
77 | |
78 | /* |
79 | * BDB version number dependencies are documented as: |
80 | * |
81 | * <start>+ |
82 | * indicates the field was introduced in version <start> |
83 | * and is still valid |
84 | * |
85 | * <start>-<end> |
86 | * indicates the field was introduced in version <start> |
87 | * and obsoleted in version <end>+1. |
88 | * |
89 | * ??? indicates the specific version number is unknown |
90 | */ |
91 | |
92 | /* |
93 | * There are several types of BIOS data blocks (BDBs), each block has |
94 | * an ID and size in the first 3 bytes (ID in first, size in next 2). |
95 | * Known types are listed below. |
96 | */ |
97 | enum bdb_block_id { |
98 | BDB_GENERAL_FEATURES = 1, |
99 | BDB_GENERAL_DEFINITIONS = 2, |
100 | BDB_OLD_TOGGLE_LIST = 3, |
101 | BDB_MODE_SUPPORT_LIST = 4, |
102 | BDB_GENERIC_MODE_TABLE = 5, |
103 | BDB_EXT_MMIO_REGS = 6, |
104 | BDB_SWF_IO = 7, |
105 | BDB_SWF_MMIO = 8, |
106 | BDB_PSR = 9, |
107 | BDB_MODE_REMOVAL_TABLE = 10, |
108 | BDB_CHILD_DEVICE_TABLE = 11, |
109 | BDB_DRIVER_FEATURES = 12, |
110 | BDB_DRIVER_PERSISTENCE = 13, |
111 | BDB_EXT_TABLE_PTRS = 14, |
112 | BDB_DOT_CLOCK_OVERRIDE = 15, |
113 | BDB_DISPLAY_SELECT = 16, |
114 | BDB_DRIVER_ROTATION = 18, |
115 | BDB_DISPLAY_REMOVE = 19, |
116 | BDB_OEM_CUSTOM = 20, |
117 | BDB_EFP_LIST = 21, /* workarounds for VGA hsync/vsync */ |
118 | BDB_SDVO_LVDS_OPTIONS = 22, |
119 | BDB_SDVO_PANEL_DTDS = 23, |
120 | BDB_SDVO_LVDS_PNP_IDS = 24, |
121 | BDB_SDVO_LVDS_POWER_SEQ = 25, |
122 | BDB_TV_OPTIONS = 26, |
123 | BDB_EDP = 27, |
124 | BDB_LVDS_OPTIONS = 40, |
125 | BDB_LVDS_LFP_DATA_PTRS = 41, |
126 | BDB_LVDS_LFP_DATA = 42, |
127 | BDB_LVDS_BACKLIGHT = 43, |
128 | BDB_LFP_POWER = 44, |
129 | BDB_MIPI_CONFIG = 52, |
130 | BDB_MIPI_SEQUENCE = 53, |
131 | BDB_COMPRESSION_PARAMETERS = 56, |
132 | BDB_GENERIC_DTD = 58, |
133 | BDB_SKIP = 254, /* VBIOS private block, ignore */ |
134 | }; |
135 | |
136 | /* |
137 | * Block 1 - General Bit Definitions |
138 | */ |
139 | |
140 | struct bdb_general_features { |
141 | /* bits 1 */ |
142 | u8 panel_fitting:2; |
143 | u8 flexaim:1; |
144 | u8 msg_enable:1; |
145 | u8 clear_screen:3; |
146 | u8 color_flip:1; |
147 | |
148 | /* bits 2 */ |
149 | u8 download_ext_vbt:1; |
150 | u8 enable_ssc:1; |
151 | u8 ssc_freq:1; |
152 | u8 enable_lfp_on_override:1; |
153 | u8 disable_ssc_ddt:1; |
154 | u8 underscan_vga_timings:1; |
155 | u8 display_clock_mode:1; |
156 | u8 vbios_hotplug_support:1; |
157 | |
158 | /* bits 3 */ |
159 | u8 disable_smooth_vision:1; |
160 | u8 single_dvi:1; |
161 | u8 rotate_180:1; /* 181+ */ |
162 | u8 fdi_rx_polarity_inverted:1; |
163 | u8 vbios_extended_mode:1; /* 160+ */ |
164 | u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160+ */ |
165 | u8 panel_best_fit_timing:1; /* 160+ */ |
166 | u8 ignore_strap_state:1; /* 160+ */ |
167 | |
168 | /* bits 4 */ |
169 | u8 legacy_monitor_detect; |
170 | |
171 | /* bits 5 */ |
172 | u8 int_crt_support:1; |
173 | u8 int_tv_support:1; |
174 | u8 int_efp_support:1; |
175 | u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */ |
176 | u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ |
177 | u8 dp_ssc_dongle_supported:1; |
178 | u8 rsvd11:2; /* finish byte */ |
179 | |
180 | /* bits 6 */ |
181 | u8 tc_hpd_retry_timeout:7; /* 242+ */ |
182 | u8 rsvd12:1; |
183 | |
184 | /* bits 7 */ |
185 | u8 afc_startup_config:2; /* 249+ */ |
186 | u8 rsvd13:6; |
187 | } __packed; |
188 | |
189 | /* |
190 | * Block 2 - General Bytes Definition |
191 | */ |
192 | |
193 | /* pre-915 */ |
194 | #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ |
195 | #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ |
196 | #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ |
197 | #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ |
198 | |
199 | /* Device handle */ |
200 | #define DEVICE_HANDLE_CRT 0x0001 |
201 | #define DEVICE_HANDLE_EFP1 0x0004 |
202 | #define DEVICE_HANDLE_EFP2 0x0040 |
203 | #define DEVICE_HANDLE_EFP3 0x0020 |
204 | #define DEVICE_HANDLE_EFP4 0x0010 /* 194+ */ |
205 | #define DEVICE_HANDLE_EFP5 0x0002 /* 215+ */ |
206 | #define DEVICE_HANDLE_EFP6 0x0001 /* 217+ */ |
207 | #define DEVICE_HANDLE_EFP7 0x0100 /* 217+ */ |
208 | #define DEVICE_HANDLE_EFP8 0x0200 /* 217+ */ |
209 | #define DEVICE_HANDLE_LFP1 0x0008 |
210 | #define DEVICE_HANDLE_LFP2 0x0080 |
211 | |
212 | /* Pre 915 */ |
213 | #define DEVICE_TYPE_NONE 0x00 |
214 | #define DEVICE_TYPE_CRT 0x01 |
215 | #define DEVICE_TYPE_TV 0x09 |
216 | #define DEVICE_TYPE_EFP 0x12 |
217 | #define DEVICE_TYPE_LFP 0x22 |
218 | /* On 915+ */ |
219 | #define DEVICE_TYPE_CRT_DPMS 0x6001 |
220 | #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 |
221 | #define DEVICE_TYPE_TV_COMPOSITE 0x0209 |
222 | #define DEVICE_TYPE_TV_MACROVISION 0x0289 |
223 | #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c |
224 | #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 |
225 | #define DEVICE_TYPE_TV_SCART 0x0209 |
226 | #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 |
227 | #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 |
228 | #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 |
229 | #define DEVICE_TYPE_EFP_DVI_I 0x6053 |
230 | #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 |
231 | #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 |
232 | #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 |
233 | #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 |
234 | #define DEVICE_TYPE_LFP_PANELLINK 0x5012 |
235 | #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 |
236 | #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 |
237 | #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 |
238 | #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 |
239 | |
240 | /* Add the device class for LFP, TV, HDMI */ |
241 | #define DEVICE_TYPE_INT_LFP 0x1022 |
242 | #define DEVICE_TYPE_INT_TV 0x1009 |
243 | #define DEVICE_TYPE_HDMI 0x60D2 |
244 | #define DEVICE_TYPE_DP 0x68C6 |
245 | #define DEVICE_TYPE_DP_DUAL_MODE 0x60D6 |
246 | #define DEVICE_TYPE_eDP 0x78C6 |
247 | |
248 | #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) |
249 | #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) |
250 | #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) |
251 | #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) |
252 | #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) |
253 | #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) |
254 | #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) |
255 | #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) |
256 | #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) |
257 | #define DEVICE_TYPE_LVDS_SIGNALING (1 << 5) |
258 | #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) |
259 | #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) |
260 | #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) |
261 | #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) |
262 | #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) |
263 | |
264 | #define DEVICE_CFG_NONE 0x00 |
265 | #define DEVICE_CFG_12BIT_DVOB 0x01 |
266 | #define DEVICE_CFG_12BIT_DVOC 0x02 |
267 | #define DEVICE_CFG_24BIT_DVOBC 0x09 |
268 | #define DEVICE_CFG_24BIT_DVOCB 0x0a |
269 | #define DEVICE_CFG_DUAL_DVOB 0x11 |
270 | #define DEVICE_CFG_DUAL_DVOC 0x12 |
271 | #define DEVICE_CFG_DUAL_DVOBC 0x13 |
272 | #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 |
273 | #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a |
274 | |
275 | #define DEVICE_WIRE_NONE 0x00 |
276 | #define DEVICE_WIRE_DVOB 0x01 |
277 | #define DEVICE_WIRE_DVOC 0x02 |
278 | #define DEVICE_WIRE_DVOBC 0x03 |
279 | #define DEVICE_WIRE_DVOBB 0x05 |
280 | #define DEVICE_WIRE_DVOCC 0x06 |
281 | #define DEVICE_WIRE_DVOB_MASTER 0x0d |
282 | #define DEVICE_WIRE_DVOC_MASTER 0x0e |
283 | |
284 | /* dvo_port pre BDB 155 */ |
285 | #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ |
286 | #define DEVICE_PORT_DVOB 0x01 |
287 | #define DEVICE_PORT_DVOC 0x02 |
288 | |
289 | /* dvo_port BDB 155+ */ |
290 | #define DVO_PORT_HDMIA 0 |
291 | #define DVO_PORT_HDMIB 1 |
292 | #define DVO_PORT_HDMIC 2 |
293 | #define DVO_PORT_HDMID 3 |
294 | #define DVO_PORT_LVDS 4 |
295 | #define DVO_PORT_TV 5 |
296 | #define DVO_PORT_CRT 6 |
297 | #define DVO_PORT_DPB 7 |
298 | #define DVO_PORT_DPC 8 |
299 | #define DVO_PORT_DPD 9 |
300 | #define DVO_PORT_DPA 10 |
301 | #define DVO_PORT_DPE 11 /* 193+ */ |
302 | #define DVO_PORT_HDMIE 12 /* 193+ */ |
303 | #define DVO_PORT_DPF 13 /* N/A */ |
304 | #define DVO_PORT_HDMIF 14 /* N/A */ |
305 | #define DVO_PORT_DPG 15 /* 217+ */ |
306 | #define DVO_PORT_HDMIG 16 /* 217+ */ |
307 | #define DVO_PORT_DPH 17 /* 217+ */ |
308 | #define DVO_PORT_HDMIH 18 /* 217+ */ |
309 | #define DVO_PORT_DPI 19 /* 217+ */ |
310 | #define DVO_PORT_HDMII 20 /* 217+ */ |
311 | #define DVO_PORT_MIPIA 21 /* 171+ */ |
312 | #define DVO_PORT_MIPIB 22 /* 171+ */ |
313 | #define DVO_PORT_MIPIC 23 /* 171+ */ |
314 | #define DVO_PORT_MIPID 24 /* 171+ */ |
315 | |
316 | #define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204+ */ |
317 | #define HDMI_MAX_DATA_RATE_297 1 /* 204+ */ |
318 | #define HDMI_MAX_DATA_RATE_165 2 /* 204+ */ |
319 | #define HDMI_MAX_DATA_RATE_594 3 /* 249+ */ |
320 | #define HDMI_MAX_DATA_RATE_340 4 /* 249+ */ |
321 | #define HDMI_MAX_DATA_RATE_300 5 /* 249+ */ |
322 | |
323 | #define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33 |
324 | |
325 | /* DDC Bus DDI Type 155+ */ |
326 | enum vbt_gmbus_ddi { |
327 | DDC_BUS_DDI_B = 0x1, |
328 | DDC_BUS_DDI_C, |
329 | DDC_BUS_DDI_D, |
330 | DDC_BUS_DDI_F, |
331 | ICL_DDC_BUS_DDI_A = 0x1, |
332 | ICL_DDC_BUS_DDI_B, |
333 | TGL_DDC_BUS_DDI_C, |
334 | RKL_DDC_BUS_DDI_D = 0x3, |
335 | RKL_DDC_BUS_DDI_E, |
336 | ICL_DDC_BUS_PORT_1 = 0x4, |
337 | ICL_DDC_BUS_PORT_2, |
338 | ICL_DDC_BUS_PORT_3, |
339 | ICL_DDC_BUS_PORT_4, |
340 | TGL_DDC_BUS_PORT_5, |
341 | TGL_DDC_BUS_PORT_6, |
342 | ADLS_DDC_BUS_PORT_TC1 = 0x2, |
343 | ADLS_DDC_BUS_PORT_TC2, |
344 | ADLS_DDC_BUS_PORT_TC3, |
345 | ADLS_DDC_BUS_PORT_TC4, |
346 | ADLP_DDC_BUS_PORT_TC1 = 0x3, |
347 | ADLP_DDC_BUS_PORT_TC2, |
348 | ADLP_DDC_BUS_PORT_TC3, |
349 | ADLP_DDC_BUS_PORT_TC4 |
350 | |
351 | }; |
352 | |
353 | #define DP_AUX_A 0x40 |
354 | #define DP_AUX_B 0x10 |
355 | #define DP_AUX_C 0x20 |
356 | #define DP_AUX_D 0x30 |
357 | #define DP_AUX_E 0x50 |
358 | #define DP_AUX_F 0x60 |
359 | #define DP_AUX_G 0x70 |
360 | #define DP_AUX_H 0x80 |
361 | #define DP_AUX_I 0x90 |
362 | |
363 | /* DP max link rate 216+ */ |
364 | #define BDB_216_VBT_DP_MAX_LINK_RATE_HBR3 0 |
365 | #define BDB_216_VBT_DP_MAX_LINK_RATE_HBR2 1 |
366 | #define BDB_216_VBT_DP_MAX_LINK_RATE_HBR 2 |
367 | #define BDB_216_VBT_DP_MAX_LINK_RATE_LBR 3 |
368 | |
369 | /* DP max link rate 230+ */ |
370 | #define BDB_230_VBT_DP_MAX_LINK_RATE_DEF 0 |
371 | #define BDB_230_VBT_DP_MAX_LINK_RATE_LBR 1 |
372 | #define BDB_230_VBT_DP_MAX_LINK_RATE_HBR 2 |
373 | #define BDB_230_VBT_DP_MAX_LINK_RATE_HBR2 3 |
374 | #define BDB_230_VBT_DP_MAX_LINK_RATE_HBR3 4 |
375 | #define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR10 5 |
376 | #define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR13P5 6 |
377 | #define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR20 7 |
378 | |
379 | /* |
380 | * The child device config, aka the display device data structure, provides a |
381 | * description of a port and its configuration on the platform. |
382 | * |
383 | * The child device config size has been increased, and fields have been added |
384 | * and their meaning has changed over time. Care must be taken when accessing |
385 | * basically any of the fields to ensure the correct interpretation for the BDB |
386 | * version in question. |
387 | * |
388 | * When we copy the child device configs to dev_priv->display.vbt.child_dev, we |
389 | * reserve space for the full structure below, and initialize the tail not |
390 | * actually present in VBT to zeros. Accessing those fields is fine, as long as |
391 | * the default zero is taken into account, again according to the BDB version. |
392 | * |
393 | * BDB versions 155 and below are considered legacy, and version 155 seems to be |
394 | * a baseline for some of the VBT documentation. When adding new fields, please |
395 | * include the BDB version when the field was added, if it's above that. |
396 | */ |
397 | struct child_device_config { |
398 | u16 handle; |
399 | u16 device_type; /* See DEVICE_TYPE_* above */ |
400 | |
401 | union { |
402 | u8 device_id[10]; /* ascii string */ |
403 | struct { |
404 | u8 i2c_speed; |
405 | u8 dp_onboard_redriver_preemph:3; /* 158+ */ |
406 | u8 dp_onboard_redriver_vswing:3; /* 158+ */ |
407 | u8 dp_onboard_redriver_present:1; /* 158+ */ |
408 | u8 reserved0:1; |
409 | u8 dp_ondock_redriver_preemph:3; /* 158+ */ |
410 | u8 dp_ondock_redriver_vswing:3; /* 158+ */ |
411 | u8 dp_ondock_redriver_present:1; /* 158+ */ |
412 | u8 reserved1:1; |
413 | u8 hdmi_level_shifter_value:5; /* 158+ */ |
414 | u8 hdmi_max_data_rate:3; /* 204+ */ |
415 | u16 dtd_buf_ptr; /* 161+ */ |
416 | u8 edidless_efp:1; /* 161+ */ |
417 | u8 compression_enable:1; /* 198+ */ |
418 | u8 compression_method_cps:1; /* 198+ */ |
419 | u8 ganged_edp:1; /* 202+ */ |
420 | u8 lttpr_non_transparent:1; /* 235+ */ |
421 | u8 disable_compression_for_ext_disp:1; /* 251+ */ |
422 | u8 reserved2:2; |
423 | u8 compression_structure_index:4; /* 198+ */ |
424 | u8 reserved3:4; |
425 | u8 hdmi_max_frl_rate:4; /* 237+ */ |
426 | u8 hdmi_max_frl_rate_valid:1; /* 237+ */ |
427 | u8 reserved4:3; /* 237+ */ |
428 | u8 reserved5; |
429 | } __packed; |
430 | } __packed; |
431 | |
432 | u16 addin_offset; |
433 | u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */ |
434 | u8 i2c_pin; |
435 | u8 slave_addr; |
436 | u8 ddc_pin; |
437 | u16 edid_ptr; |
438 | u8 dvo_cfg; /* See DEVICE_CFG_* above */ |
439 | |
440 | union { |
441 | struct { |
442 | u8 dvo2_port; |
443 | u8 i2c2_pin; |
444 | u8 slave2_addr; |
445 | u8 ddc2_pin; |
446 | } __packed; |
447 | struct { |
448 | u8 efp_routed:1; /* 158+ */ |
449 | u8 lane_reversal:1; /* 184+ */ |
450 | u8 lspcon:1; /* 192+ */ |
451 | u8 iboost:1; /* 196+ */ |
452 | u8 hpd_invert:1; /* 196+ */ |
453 | u8 use_vbt_vswing:1; /* 218+ */ |
454 | u8 dp_max_lane_count:2; /* 244+ */ |
455 | u8 hdmi_support:1; /* 158+ */ |
456 | u8 dp_support:1; /* 158+ */ |
457 | u8 tmds_support:1; /* 158+ */ |
458 | u8 support_reserved:5; |
459 | u8 aux_channel; |
460 | u8 dongle_detect; |
461 | } __packed; |
462 | } __packed; |
463 | |
464 | u8 pipe_cap:2; |
465 | u8 sdvo_stall:1; /* 158+ */ |
466 | u8 hpd_status:2; |
467 | u8 integrated_encoder:1; |
468 | u8 capabilities_reserved:2; |
469 | u8 dvo_wiring; /* See DEVICE_WIRE_* above */ |
470 | |
471 | union { |
472 | u8 dvo2_wiring; |
473 | u8 mipi_bridge_type; /* 171+ */ |
474 | } __packed; |
475 | |
476 | u16 extended_type; |
477 | u8 dvo_function; |
478 | u8 dp_usb_type_c:1; /* 195+ */ |
479 | u8 tbt:1; /* 209+ */ |
480 | u8 flags2_reserved:2; /* 195+ */ |
481 | u8 dp_port_trace_length:4; /* 209+ */ |
482 | u8 dp_gpio_index; /* 195+ */ |
483 | u16 dp_gpio_pin_num; /* 195+ */ |
484 | u8 dp_iboost_level:4; /* 196+ */ |
485 | u8 hdmi_iboost_level:4; /* 196+ */ |
486 | u8 dp_max_link_rate:3; /* 216+ */ |
487 | u8 dp_max_link_rate_reserved:5; /* 216+ */ |
488 | } __packed; |
489 | |
490 | struct bdb_general_definitions { |
491 | /* DDC GPIO */ |
492 | u8 crt_ddc_gmbus_pin; |
493 | |
494 | /* DPMS bits */ |
495 | u8 dpms_non_acpi:1; |
496 | u8 skip_boot_crt_detect:1; |
497 | u8 dpms_aim:1; |
498 | u8 rsvd1:5; /* finish byte */ |
499 | |
500 | /* boot device bits */ |
501 | u8 boot_display[2]; |
502 | u8 child_dev_size; |
503 | |
504 | /* |
505 | * Device info: |
506 | * If TV is present, it'll be at devices[0]. |
507 | * LVDS will be next, either devices[0] or [1], if present. |
508 | * On some platforms the number of device is 6. But could be as few as |
509 | * 4 if both TV and LVDS are missing. |
510 | * And the device num is related with the size of general definition |
511 | * block. It is obtained by using the following formula: |
512 | * number = (block_size - sizeof(bdb_general_definitions))/ |
513 | * defs->child_dev_size; |
514 | */ |
515 | u8 devices[]; |
516 | } __packed; |
517 | |
518 | /* |
519 | * Block 9 - SRD Feature Block |
520 | */ |
521 | |
522 | struct psr_table { |
523 | /* Feature bits */ |
524 | u8 full_link:1; /* 165+ */ |
525 | u8 require_aux_to_wakeup:1; /* 165+ */ |
526 | u8 feature_bits_rsvd:6; |
527 | |
528 | /* Wait times */ |
529 | u8 idle_frames:4; /* 165+ */ |
530 | u8 lines_to_wait:3; /* 165+ */ |
531 | u8 wait_times_rsvd:1; |
532 | |
533 | /* TP wake up time in multiple of 100 */ |
534 | u16 tp1_wakeup_time; /* 165+ */ |
535 | u16 tp2_tp3_wakeup_time; /* 165+ */ |
536 | } __packed; |
537 | |
538 | struct bdb_psr { |
539 | struct psr_table psr_table[16]; |
540 | |
541 | /* PSR2 TP2/TP3 wakeup time for 16 panels */ |
542 | u32 psr2_tp2_tp3_wakeup_time; /* 226+ */ |
543 | } __packed; |
544 | |
545 | /* |
546 | * Block 12 - Driver Features Data Block |
547 | */ |
548 | |
549 | #define BDB_DRIVER_FEATURE_NO_LVDS 0 |
550 | #define BDB_DRIVER_FEATURE_INT_LVDS 1 |
551 | #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 |
552 | #define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3 |
553 | |
554 | struct bdb_driver_features { |
555 | /* Driver bits */ |
556 | u8 boot_dev_algorithm:1; |
557 | u8 allow_display_switch_dvd:1; |
558 | u8 allow_display_switch_dos:1; |
559 | u8 hotplug_dvo:1; |
560 | u8 dual_view_zoom:1; |
561 | u8 int15h_hook:1; |
562 | u8 sprite_in_clone:1; |
563 | u8 primary_lfp_id:1; |
564 | |
565 | u16 boot_mode_x; |
566 | u16 boot_mode_y; |
567 | u8 boot_mode_bpp; |
568 | u8 boot_mode_refresh; |
569 | |
570 | /* Extended Driver Bits 1 */ |
571 | u16 enable_lfp_primary:1; |
572 | u16 selective_mode_pruning:1; |
573 | u16 dual_frequency:1; |
574 | u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ |
575 | u16 nt_clone_support:1; |
576 | u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ |
577 | u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ |
578 | u16 cui_aspect_scaling:1; |
579 | u16 preserve_aspect_ratio:1; |
580 | u16 sdvo_device_power_down:1; |
581 | u16 crt_hotplug:1; |
582 | u16 lvds_config:2; |
583 | u16 tv_hotplug:1; |
584 | u16 hdmi_config:2; |
585 | |
586 | /* Driver Flags 1 */ |
587 | u8 static_display:1; /* 163+ */ |
588 | u8 embedded_platform:1; /* 163+ */ |
589 | u8 display_subsystem_enable:1; /* 163+ */ |
590 | u8 reserved0:5; |
591 | |
592 | u16 legacy_crt_max_x; |
593 | u16 legacy_crt_max_y; |
594 | u8 legacy_crt_max_refresh; |
595 | |
596 | /* Extended Driver Bits 2 */ |
597 | u8 hdmi_termination:1; |
598 | u8 cea861d_hdmi_support:1; |
599 | u8 self_refresh_enable:1; |
600 | u8 reserved1:5; |
601 | |
602 | u8 custom_vbt_version; /* 155+ */ |
603 | |
604 | /* Driver Feature Flags */ |
605 | u16 rmpm_enabled:1; /* 165+ */ |
606 | u16 s2ddt_enabled:1; /* 165+ */ |
607 | u16 dpst_enabled:1; /* 165-227 */ |
608 | u16 bltclt_enabled:1; /* 165+ */ |
609 | u16 adb_enabled:1; /* 165-227 */ |
610 | u16 drrs_enabled:1; /* 165-227 */ |
611 | u16 grs_enabled:1; /* 165+ */ |
612 | u16 gpmt_enabled:1; /* 165+ */ |
613 | u16 tbt_enabled:1; /* 165+ */ |
614 | u16 psr_enabled:1; /* 165-227 */ |
615 | u16 ips_enabled:1; /* 165+ */ |
616 | u16 dpfs_enabled:1; /* 165+ */ |
617 | u16 dmrrs_enabled:1; /* 174-227 */ |
618 | u16 adt_enabled:1; /* ???-228 */ |
619 | u16 hpd_wake:1; /* 201-240 */ |
620 | u16 pc_feature_valid:1; |
621 | } __packed; |
622 | |
623 | /* |
624 | * Block 22 - SDVO LVDS General Options |
625 | */ |
626 | |
627 | struct bdb_sdvo_lvds_options { |
628 | u8 panel_backlight; |
629 | u8 h40_set_panel_type; |
630 | u8 panel_type; |
631 | u8 ssc_clk_freq; |
632 | u16 als_low_trip; |
633 | u16 als_high_trip; |
634 | u8 sclalarcoeff_tab_row_num; |
635 | u8 sclalarcoeff_tab_row_size; |
636 | u8 coefficient[8]; |
637 | u8 panel_misc_bits_1; |
638 | u8 panel_misc_bits_2; |
639 | u8 panel_misc_bits_3; |
640 | u8 panel_misc_bits_4; |
641 | } __packed; |
642 | |
643 | /* |
644 | * Block 23 - SDVO LVDS Panel DTDs |
645 | */ |
646 | |
647 | struct lvds_dvo_timing { |
648 | u16 clock; /**< In 10khz */ |
649 | u8 hactive_lo; |
650 | u8 hblank_lo; |
651 | u8 hblank_hi:4; |
652 | u8 hactive_hi:4; |
653 | u8 vactive_lo; |
654 | u8 vblank_lo; |
655 | u8 vblank_hi:4; |
656 | u8 vactive_hi:4; |
657 | u8 hsync_off_lo; |
658 | u8 hsync_pulse_width_lo; |
659 | u8 vsync_pulse_width_lo:4; |
660 | u8 vsync_off_lo:4; |
661 | u8 vsync_pulse_width_hi:2; |
662 | u8 vsync_off_hi:2; |
663 | u8 hsync_pulse_width_hi:2; |
664 | u8 hsync_off_hi:2; |
665 | u8 himage_lo; |
666 | u8 vimage_lo; |
667 | u8 vimage_hi:4; |
668 | u8 himage_hi:4; |
669 | u8 h_border; |
670 | u8 v_border; |
671 | u8 rsvd1:3; |
672 | u8 digital:2; |
673 | u8 vsync_positive:1; |
674 | u8 hsync_positive:1; |
675 | u8 non_interlaced:1; |
676 | } __packed; |
677 | |
678 | struct bdb_sdvo_panel_dtds { |
679 | struct lvds_dvo_timing dtds[4]; |
680 | } __packed; |
681 | |
682 | /* |
683 | * Block 27 - eDP VBT Block |
684 | */ |
685 | |
686 | #define EDP_18BPP 0 |
687 | #define EDP_24BPP 1 |
688 | #define EDP_30BPP 2 |
689 | #define EDP_RATE_1_62 0 |
690 | #define EDP_RATE_2_7 1 |
691 | #define EDP_RATE_5_4 2 |
692 | #define EDP_LANE_1 0 |
693 | #define EDP_LANE_2 1 |
694 | #define EDP_LANE_4 3 |
695 | #define EDP_PREEMPHASIS_NONE 0 |
696 | #define EDP_PREEMPHASIS_3_5dB 1 |
697 | #define EDP_PREEMPHASIS_6dB 2 |
698 | #define EDP_PREEMPHASIS_9_5dB 3 |
699 | #define EDP_VSWING_0_4V 0 |
700 | #define EDP_VSWING_0_6V 1 |
701 | #define EDP_VSWING_0_8V 2 |
702 | #define EDP_VSWING_1_2V 3 |
703 | |
704 | |
705 | struct edp_fast_link_params { |
706 | u8 rate:4; /* ???-223 */ |
707 | u8 lanes:4; |
708 | u8 preemphasis:4; |
709 | u8 vswing:4; |
710 | } __packed; |
711 | |
712 | struct edp_pwm_delays { |
713 | u16 pwm_on_to_backlight_enable; |
714 | u16 backlight_disable_to_pwm_off; |
715 | } __packed; |
716 | |
717 | struct edp_full_link_params { |
718 | u8 preemphasis:4; |
719 | u8 vswing:4; |
720 | } __packed; |
721 | |
722 | struct edp_apical_params { |
723 | u32 panel_oui; |
724 | u32 dpcd_base_address; |
725 | u32 dpcd_idridix_control_0; |
726 | u32 dpcd_option_select; |
727 | u32 dpcd_backlight; |
728 | u32 ambient_light; |
729 | u32 backlight_scale; |
730 | } __packed; |
731 | |
732 | struct bdb_edp { |
733 | struct edp_power_seq power_seqs[16]; |
734 | u32 color_depth; |
735 | struct edp_fast_link_params fast_link_params[16]; |
736 | u32 sdrrs_msa_timing_delay; |
737 | |
738 | /* ith bit indicates enabled/disabled for (i+1)th panel */ |
739 | u16 edp_s3d_feature; /* 162+ */ |
740 | u16 edp_t3_optimization; /* 165+ */ |
741 | u64 edp_vswing_preemph; /* 173+ */ |
742 | u16 fast_link_training; /* 182+ */ |
743 | u16 dpcd_600h_write_required; /* 185+ */ |
744 | struct edp_pwm_delays pwm_delays[16]; /* 186+ */ |
745 | u16 full_link_params_provided; /* 199+ */ |
746 | struct edp_full_link_params full_link_params[16]; /* 199+ */ |
747 | u16 apical_enable; /* 203+ */ |
748 | struct edp_apical_params apical_params[16]; /* 203+ */ |
749 | u16 edp_fast_link_training_rate[16]; /* 224+ */ |
750 | u16 edp_max_port_link_rate[16]; /* 244+ */ |
751 | } __packed; |
752 | |
753 | /* |
754 | * Block 40 - LFP Data Block |
755 | */ |
756 | |
757 | struct bdb_lvds_options { |
758 | u8 panel_type; |
759 | u8 panel_type2; /* 212+ */ |
760 | /* LVDS capabilities, stored in a dword */ |
761 | u8 pfit_mode:2; |
762 | u8 pfit_text_mode_enhanced:1; |
763 | u8 pfit_gfx_mode_enhanced:1; |
764 | u8 pfit_ratio_auto:1; |
765 | u8 pixel_dither:1; |
766 | u8 lvds_edid:1; /* ???-240 */ |
767 | u8 rsvd2:1; |
768 | u8 rsvd4; |
769 | /* LVDS Panel channel bits stored here */ |
770 | u32 lvds_panel_channel_bits; |
771 | /* LVDS SSC (Spread Spectrum Clock) bits stored here. */ |
772 | u16 ssc_bits; |
773 | u16 ssc_freq; |
774 | u16 ssc_ddt; |
775 | /* Panel color depth defined here */ |
776 | u16 panel_color_depth; |
777 | /* LVDS panel type bits stored here */ |
778 | u32 dps_panel_type_bits; |
779 | /* LVDS backlight control type bits stored here */ |
780 | u32 blt_control_type_bits; /* ???-240 */ |
781 | |
782 | u16 lcdvcc_s0_enable; /* 200+ */ |
783 | u32 rotation; /* 228+ */ |
784 | u32 position; /* 240+ */ |
785 | } __packed; |
786 | |
787 | /* |
788 | * Block 41 - LFP Data Table Pointers |
789 | */ |
790 | struct lvds_lfp_data_ptr_table { |
791 | u16 offset; /* offsets are from start of bdb */ |
792 | u8 table_size; |
793 | } __packed; |
794 | |
795 | /* LFP pointer table contains entries to the struct below */ |
796 | struct lvds_lfp_data_ptr { |
797 | struct lvds_lfp_data_ptr_table fp_timing; |
798 | struct lvds_lfp_data_ptr_table dvo_timing; |
799 | struct lvds_lfp_data_ptr_table panel_pnp_id; |
800 | } __packed; |
801 | |
802 | struct bdb_lvds_lfp_data_ptrs { |
803 | u8 lvds_entries; |
804 | struct lvds_lfp_data_ptr ptr[16]; |
805 | struct lvds_lfp_data_ptr_table panel_name; /* (156-163?)+ */ |
806 | } __packed; |
807 | |
808 | /* |
809 | * Block 42 - LFP Data Tables |
810 | */ |
811 | |
812 | /* LFP data has 3 blocks per entry */ |
813 | struct lvds_fp_timing { |
814 | u16 x_res; |
815 | u16 y_res; |
816 | u32 lvds_reg; |
817 | u32 lvds_reg_val; |
818 | u32 pp_on_reg; |
819 | u32 pp_on_reg_val; |
820 | u32 pp_off_reg; |
821 | u32 pp_off_reg_val; |
822 | u32 pp_cycle_reg; |
823 | u32 pp_cycle_reg_val; |
824 | u32 pfit_reg; |
825 | u32 pfit_reg_val; |
826 | u16 terminator; |
827 | } __packed; |
828 | |
829 | struct lvds_pnp_id { |
830 | u16 mfg_name; |
831 | u16 product_code; |
832 | u32 serial; |
833 | u8 mfg_week; |
834 | u8 mfg_year; |
835 | } __packed; |
836 | |
837 | /* |
838 | * For reference only. fp_timing has variable size so |
839 | * the data must be accessed using the data table pointers. |
840 | * Do not use this directly! |
841 | */ |
842 | struct lvds_lfp_data_entry { |
843 | struct lvds_fp_timing fp_timing; |
844 | struct lvds_dvo_timing dvo_timing; |
845 | struct lvds_pnp_id pnp_id; |
846 | } __packed; |
847 | |
848 | struct bdb_lvds_lfp_data { |
849 | struct lvds_lfp_data_entry data[16]; |
850 | } __packed; |
851 | |
852 | struct lvds_lfp_panel_name { |
853 | u8 name[13]; |
854 | } __packed; |
855 | |
856 | struct lvds_lfp_black_border { |
857 | u8 top; /* 227+ */ |
858 | u8 bottom; /* 227+ */ |
859 | u8 left; /* 238+ */ |
860 | u8 right; /* 238+ */ |
861 | } __packed; |
862 | |
863 | struct bdb_lvds_lfp_data_tail { |
864 | struct lvds_lfp_panel_name panel_name[16]; /* (156-163?)+ */ |
865 | u16 scaling_enable; /* 187+ */ |
866 | u8 seamless_drrs_min_refresh_rate[16]; /* 188+ */ |
867 | u8 pixel_overlap_count[16]; /* 208+ */ |
868 | struct lvds_lfp_black_border black_border[16]; /* 227+ */ |
869 | u16 dual_lfp_port_sync_enable; /* 231+ */ |
870 | u16 gpu_dithering_for_banding_artifacts; /* 245+ */ |
871 | } __packed; |
872 | |
873 | /* |
874 | * Block 43 - LFP Backlight Control Data Block |
875 | */ |
876 | |
877 | #define BDB_BACKLIGHT_TYPE_NONE 0 |
878 | #define BDB_BACKLIGHT_TYPE_PWM 2 |
879 | |
880 | struct lfp_backlight_data_entry { |
881 | u8 type:2; |
882 | u8 active_low_pwm:1; |
883 | u8 obsolete1:5; |
884 | u16 pwm_freq_hz; |
885 | u8 min_brightness; /* ???-233 */ |
886 | u8 obsolete2; |
887 | u8 obsolete3; |
888 | } __packed; |
889 | |
890 | struct lfp_backlight_control_method { |
891 | u8 type:4; |
892 | u8 controller:4; |
893 | } __packed; |
894 | |
895 | struct lfp_brightness_level { |
896 | u16 level; |
897 | u16 reserved; |
898 | } __packed; |
899 | |
900 | #define EXP_BDB_LFP_BL_DATA_SIZE_REV_191 \ |
901 | offsetof(struct bdb_lfp_backlight_data, brightness_level) |
902 | #define EXP_BDB_LFP_BL_DATA_SIZE_REV_234 \ |
903 | offsetof(struct bdb_lfp_backlight_data, brightness_precision_bits) |
904 | |
905 | struct bdb_lfp_backlight_data { |
906 | u8 entry_size; |
907 | struct lfp_backlight_data_entry data[16]; |
908 | u8 level[16]; /* ???-233 */ |
909 | struct lfp_backlight_control_method backlight_control[16]; |
910 | struct lfp_brightness_level brightness_level[16]; /* 234+ */ |
911 | struct lfp_brightness_level brightness_min_level[16]; /* 234+ */ |
912 | u8 brightness_precision_bits[16]; /* 236+ */ |
913 | u16 hdr_dpcd_refresh_timeout[16]; /* 239+ */ |
914 | } __packed; |
915 | |
916 | /* |
917 | * Block 44 - LFP Power Conservation Features Block |
918 | */ |
919 | struct lfp_power_features { |
920 | u8 reserved1:1; |
921 | u8 power_conservation_pref:3; |
922 | u8 reserved2:1; |
923 | u8 lace_enabled_status:1; /* 210+ */ |
924 | u8 lace_support:1; /* 210+ */ |
925 | u8 als_enable:1; |
926 | } __packed; |
927 | |
928 | struct als_data_entry { |
929 | u16 backlight_adjust; |
930 | u16 lux; |
931 | } __packed; |
932 | |
933 | struct aggressiveness_profile_entry { |
934 | u8 dpst_aggressiveness : 4; |
935 | u8 lace_aggressiveness : 4; |
936 | } __packed; |
937 | |
938 | struct aggressiveness_profile2_entry { |
939 | u8 opst_aggressiveness : 4; |
940 | u8 elp_aggressiveness : 4; |
941 | } __packed; |
942 | |
943 | struct bdb_lfp_power { |
944 | struct lfp_power_features features; /* ???-227 */ |
945 | struct als_data_entry als[5]; |
946 | u8 lace_aggressiveness_profile:3; /* 210-227 */ |
947 | u8 reserved1:5; |
948 | u16 dpst; /* 228+ */ |
949 | u16 psr; /* 228+ */ |
950 | u16 drrs; /* 228+ */ |
951 | u16 lace_support; /* 228+ */ |
952 | u16 adt; /* 228+ */ |
953 | u16 dmrrs; /* 228+ */ |
954 | u16 adb; /* 228+ */ |
955 | u16 lace_enabled_status; /* 228+ */ |
956 | struct aggressiveness_profile_entry aggressiveness[16]; /* 228+ */ |
957 | u16 hobl; /* 232+ */ |
958 | u16 vrr_feature_enabled; /* 233+ */ |
959 | u16 elp; /* 247+ */ |
960 | u16 opst; /* 247+ */ |
961 | struct aggressiveness_profile2_entry aggressiveness2[16]; /* 247+ */ |
962 | } __packed; |
963 | |
964 | /* |
965 | * Block 52 - MIPI Configuration Block |
966 | */ |
967 | |
968 | #define MAX_MIPI_CONFIGURATIONS 6 |
969 | |
970 | struct bdb_mipi_config { |
971 | struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; /* 175+ */ |
972 | struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; /* 177+ */ |
973 | struct edp_pwm_delays pwm_delays[MAX_MIPI_CONFIGURATIONS]; /* 186+ */ |
974 | u8 pmic_i2c_bus_number[MAX_MIPI_CONFIGURATIONS]; /* 190+ */ |
975 | } __packed; |
976 | |
977 | /* |
978 | * Block 53 - MIPI Sequence Block |
979 | */ |
980 | |
981 | struct bdb_mipi_sequence { |
982 | u8 version; |
983 | u8 data[]; /* up to 6 variable length blocks */ |
984 | } __packed; |
985 | |
986 | /* |
987 | * Block 56 - Compression Parameters |
988 | */ |
989 | |
990 | #define VBT_RC_BUFFER_BLOCK_SIZE_1KB 0 |
991 | #define VBT_RC_BUFFER_BLOCK_SIZE_4KB 1 |
992 | #define VBT_RC_BUFFER_BLOCK_SIZE_16KB 2 |
993 | #define VBT_RC_BUFFER_BLOCK_SIZE_64KB 3 |
994 | |
995 | #define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value) ((vbt_value) + 8) /* bits */ |
996 | #define VBT_DSC_MAX_BPP(vbt_value) (6 + (vbt_value) * 2) |
997 | |
998 | struct dsc_compression_parameters_entry { |
999 | u8 version_major:4; |
1000 | u8 version_minor:4; |
1001 | |
1002 | u8 rc_buffer_block_size:2; |
1003 | u8 reserved1:6; |
1004 | |
1005 | /* |
1006 | * Buffer size in bytes: |
1007 | * |
1008 | * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes |
1009 | */ |
1010 | u8 rc_buffer_size; |
1011 | u32 slices_per_line; |
1012 | |
1013 | u8 line_buffer_depth:4; |
1014 | u8 reserved2:4; |
1015 | |
1016 | /* Flag Bits 1 */ |
1017 | u8 block_prediction_enable:1; |
1018 | u8 reserved3:7; |
1019 | |
1020 | u8 max_bpp; /* mapping */ |
1021 | |
1022 | /* Color depth capabilities */ |
1023 | u8 reserved4:1; |
1024 | u8 support_8bpc:1; |
1025 | u8 support_10bpc:1; |
1026 | u8 support_12bpc:1; |
1027 | u8 reserved5:4; |
1028 | |
1029 | u16 slice_height; |
1030 | } __packed; |
1031 | |
1032 | struct bdb_compression_parameters { |
1033 | u16 entry_size; |
1034 | struct dsc_compression_parameters_entry data[16]; |
1035 | } __packed; |
1036 | |
1037 | /* |
1038 | * Block 58 - Generic DTD Block |
1039 | */ |
1040 | |
1041 | struct generic_dtd_entry { |
1042 | u32 pixel_clock; |
1043 | u16 hactive; |
1044 | u16 hblank; |
1045 | u16 hfront_porch; |
1046 | u16 hsync; |
1047 | u16 vactive; |
1048 | u16 vblank; |
1049 | u16 vfront_porch; |
1050 | u16 vsync; |
1051 | u16 width_mm; |
1052 | u16 height_mm; |
1053 | |
1054 | /* Flags */ |
1055 | u8 rsvd_flags:6; |
1056 | u8 vsync_positive_polarity:1; |
1057 | u8 hsync_positive_polarity:1; |
1058 | |
1059 | u8 rsvd[3]; |
1060 | } __packed; |
1061 | |
1062 | struct bdb_generic_dtd { |
1063 | u16 gdtd_size; |
1064 | struct generic_dtd_entry dtd[]; /* up to 24 DTD's */ |
1065 | } __packed; |
1066 | |
1067 | #endif /* _INTEL_VBT_DEFS_H_ */ |
1068 | |