| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2022 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __VLV_DSI_REGS_H__ |
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| 7 | #define __VLV_DSI_REGS_H__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | |
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| 11 | #define VLV_MIPI_BASE VLV_DISPLAY_BASE |
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| 12 | #define BXT_MIPI_BASE 0x60000 |
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| 13 | |
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| 14 | #define _MIPI_MMIO_BASE(__i915) ((__i915)->display.dsi.mmio_base) |
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| 15 | |
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| 16 | #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ |
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| 17 | #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) |
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| 18 | |
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| 19 | /* BXT MIPI mode configure */ |
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| 20 | #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 |
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| 21 | #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 |
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| 22 | #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ |
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| 23 | _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) |
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| 24 | |
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| 25 | #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC |
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| 26 | #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC |
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| 27 | #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ |
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| 28 | _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) |
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| 29 | |
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| 30 | #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 |
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| 31 | #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 |
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| 32 | #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ |
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| 33 | _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) |
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| 34 | |
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| 35 | #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) |
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| 36 | #define STAP_SELECT (1 << 0) |
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| 37 | |
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| 38 | #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) |
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| 39 | #define HS_IO_CTRL_SELECT (1 << 0) |
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| 40 | |
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| 41 | #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) |
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| 42 | #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) |
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| 43 | #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) |
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| 44 | |
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| 45 | /* BXT port control */ |
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| 46 | #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 |
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| 47 | #define _BXT_MIPIC_PORT_CTRL 0x6B8C0 |
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| 48 | #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) |
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| 49 | |
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| 50 | #define DPI_ENABLE (1 << 31) /* A + C */ |
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| 51 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 |
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| 52 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) |
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| 53 | #define DUAL_LINK_MODE_SHIFT 26 |
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| 54 | #define DUAL_LINK_MODE_MASK (1 << 26) |
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| 55 | #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) |
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| 56 | #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) |
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| 57 | #define DITHERING_ENABLE (1 << 25) /* A + C */ |
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| 58 | #define FLOPPED_HSTX (1 << 23) |
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| 59 | #define DE_INVERT (1 << 19) /* XXX */ |
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| 60 | #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 |
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| 61 | #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) |
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| 62 | #define AFE_LATCHOUT (1 << 17) |
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| 63 | #define LP_OUTPUT_HOLD (1 << 16) |
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| 64 | #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 |
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| 65 | #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) |
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| 66 | #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 |
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| 67 | #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) |
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| 68 | #define CSB_SHIFT 9 |
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| 69 | #define CSB_MASK (3 << 9) |
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| 70 | #define CSB_20MHZ (0 << 9) |
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| 71 | #define CSB_10MHZ (1 << 9) |
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| 72 | #define CSB_40MHZ (2 << 9) |
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| 73 | #define BANDGAP_MASK (1 << 8) |
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| 74 | #define BANDGAP_PNW_CIRCUIT (0 << 8) |
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| 75 | #define BANDGAP_LNC_CIRCUIT (1 << 8) |
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| 76 | #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 |
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| 77 | #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) |
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| 78 | #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ |
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| 79 | #define TEARING_EFFECT_SHIFT 2 /* A + C */ |
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| 80 | #define TEARING_EFFECT_MASK (3 << 2) |
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| 81 | #define TEARING_EFFECT_OFF (0 << 2) |
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| 82 | #define TEARING_EFFECT_DSI (1 << 2) |
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| 83 | #define TEARING_EFFECT_GPIO (2 << 2) |
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| 84 | #define LANE_CONFIGURATION_SHIFT 0 |
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| 85 | #define LANE_CONFIGURATION_MASK (3 << 0) |
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| 86 | #define LANE_CONFIGURATION_4LANE (0 << 0) |
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| 87 | #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) |
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| 88 | #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) |
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| 89 | |
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| 90 | #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) |
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| 91 | #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) |
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| 92 | #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) |
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| 93 | #define TEARING_EFFECT_DELAY_SHIFT 0 |
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| 94 | #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) |
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| 95 | |
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| 96 | /* XXX: all bits reserved */ |
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| 97 | #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) |
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| 98 | |
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| 99 | /* MIPI DSI Controller and D-PHY registers */ |
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| 100 | |
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| 101 | #define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000) |
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| 102 | #define _MIPIC_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb800) |
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| 103 | #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) |
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| 104 | #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ |
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| 105 | #define ULPS_STATE_MASK (3 << 1) |
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| 106 | #define ULPS_STATE_ENTER (2 << 1) |
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| 107 | #define ULPS_STATE_EXIT (1 << 1) |
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| 108 | #define ULPS_STATE_NORMAL_OPERATION (0 << 1) |
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| 109 | #define DEVICE_READY (1 << 0) |
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| 110 | |
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| 111 | #define _MIPIA_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb004) |
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| 112 | #define _MIPIC_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb804) |
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| 113 | #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) |
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| 114 | #define _MIPIA_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb008) |
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| 115 | #define _MIPIC_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb808) |
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| 116 | #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) |
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| 117 | #define TEARING_EFFECT (1 << 31) |
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| 118 | #define SPL_PKT_SENT_INTERRUPT (1 << 30) |
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| 119 | #define GEN_READ_DATA_AVAIL (1 << 29) |
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| 120 | #define LP_GENERIC_WR_FIFO_FULL (1 << 28) |
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| 121 | #define HS_GENERIC_WR_FIFO_FULL (1 << 27) |
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| 122 | #define RX_PROT_VIOLATION (1 << 26) |
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| 123 | #define RX_INVALID_TX_LENGTH (1 << 25) |
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| 124 | #define ACK_WITH_NO_ERROR (1 << 24) |
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| 125 | #define TURN_AROUND_ACK_TIMEOUT (1 << 23) |
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| 126 | #define LP_RX_TIMEOUT (1 << 22) |
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| 127 | #define HS_TX_TIMEOUT (1 << 21) |
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| 128 | #define DPI_FIFO_UNDERRUN (1 << 20) |
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| 129 | #define LOW_CONTENTION (1 << 19) |
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| 130 | #define HIGH_CONTENTION (1 << 18) |
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| 131 | #define TXDSI_VC_ID_INVALID (1 << 17) |
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| 132 | #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) |
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| 133 | #define TXCHECKSUM_ERROR (1 << 15) |
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| 134 | #define TXECC_MULTIBIT_ERROR (1 << 14) |
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| 135 | #define TXECC_SINGLE_BIT_ERROR (1 << 13) |
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| 136 | #define TXFALSE_CONTROL_ERROR (1 << 12) |
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| 137 | #define RXDSI_VC_ID_INVALID (1 << 11) |
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| 138 | #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) |
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| 139 | #define RXCHECKSUM_ERROR (1 << 9) |
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| 140 | #define RXECC_MULTIBIT_ERROR (1 << 8) |
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| 141 | #define RXECC_SINGLE_BIT_ERROR (1 << 7) |
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| 142 | #define RXFALSE_CONTROL_ERROR (1 << 6) |
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| 143 | #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) |
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| 144 | #define RX_LP_TX_SYNC_ERROR (1 << 4) |
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| 145 | #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) |
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| 146 | #define RXEOT_SYNC_ERROR (1 << 2) |
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| 147 | #define RXSOT_SYNC_ERROR (1 << 1) |
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| 148 | #define RXSOT_ERROR (1 << 0) |
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| 149 | |
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| 150 | #define _MIPIA_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb00c) |
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| 151 | #define _MIPIC_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb80c) |
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| 152 | #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) |
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| 153 | #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) |
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| 154 | #define CMD_MODE_NOT_SUPPORTED (0 << 13) |
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| 155 | #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) |
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| 156 | #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) |
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| 157 | #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) |
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| 158 | #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) |
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| 159 | #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) |
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| 160 | #define VID_MODE_FORMAT_MASK (0xf << 7) |
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| 161 | #define VID_MODE_NOT_SUPPORTED (0 << 7) |
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| 162 | #define VID_MODE_FORMAT_RGB565 (1 << 7) |
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| 163 | #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7) |
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| 164 | #define VID_MODE_FORMAT_RGB666 (3 << 7) |
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| 165 | #define VID_MODE_FORMAT_RGB888 (4 << 7) |
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| 166 | #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 |
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| 167 | #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) |
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| 168 | #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 |
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| 169 | #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) |
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| 170 | #define DATA_LANES_PRG_REG_SHIFT 0 |
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| 171 | #define DATA_LANES_PRG_REG_MASK (7 << 0) |
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| 172 | |
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| 173 | #define _MIPIA_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb010) |
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| 174 | #define _MIPIC_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb810) |
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| 175 | #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) |
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| 176 | #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff |
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| 177 | |
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| 178 | #define _MIPIA_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb014) |
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| 179 | #define _MIPIC_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb814) |
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| 180 | #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) |
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| 181 | #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff |
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| 182 | |
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| 183 | #define _MIPIA_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb018) |
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| 184 | #define _MIPIC_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb818) |
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| 185 | #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) |
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| 186 | #define TURN_AROUND_TIMEOUT_MASK 0x3f |
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| 187 | |
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| 188 | #define _MIPIA_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb01c) |
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| 189 | #define _MIPIC_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb81c) |
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| 190 | #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) |
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| 191 | #define DEVICE_RESET_TIMER_MASK 0xffff |
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| 192 | |
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| 193 | #define _MIPIA_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb020) |
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| 194 | #define _MIPIC_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb820) |
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| 195 | #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) |
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| 196 | #define VERTICAL_ADDRESS_SHIFT 16 |
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| 197 | #define VERTICAL_ADDRESS_MASK (0xffff << 16) |
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| 198 | #define HORIZONTAL_ADDRESS_SHIFT 0 |
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| 199 | #define HORIZONTAL_ADDRESS_MASK 0xffff |
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| 200 | |
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| 201 | #define _MIPIA_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb024) |
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| 202 | #define _MIPIC_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb824) |
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| 203 | #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) |
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| 204 | #define DBI_FIFO_EMPTY_HALF (0 << 0) |
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| 205 | #define DBI_FIFO_EMPTY_QUARTER (1 << 0) |
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| 206 | #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) |
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| 207 | |
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| 208 | /* regs below are bits 15:0 */ |
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| 209 | #define _MIPIA_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb028) |
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| 210 | #define _MIPIC_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb828) |
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| 211 | #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) |
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| 212 | |
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| 213 | #define _MIPIA_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb02c) |
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| 214 | #define _MIPIC_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb82c) |
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| 215 | #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) |
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| 216 | |
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| 217 | #define _MIPIA_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb030) |
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| 218 | #define _MIPIC_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb830) |
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| 219 | #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) |
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| 220 | |
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| 221 | #define _MIPIA_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb034) |
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| 222 | #define _MIPIC_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb834) |
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| 223 | #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) |
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| 224 | |
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| 225 | #define _MIPIA_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb038) |
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| 226 | #define _MIPIC_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb838) |
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| 227 | #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) |
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| 228 | |
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| 229 | #define _MIPIA_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb03c) |
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| 230 | #define _MIPIC_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb83c) |
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| 231 | #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) |
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| 232 | |
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| 233 | #define _MIPIA_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb040) |
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| 234 | #define _MIPIC_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb840) |
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| 235 | #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) |
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| 236 | |
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| 237 | #define _MIPIA_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb044) |
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| 238 | #define _MIPIC_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb844) |
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| 239 | #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) |
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| 240 | |
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| 241 | #define _MIPIA_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb048) |
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| 242 | #define _MIPIC_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb848) |
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| 243 | #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) |
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| 244 | #define DPI_LP_MODE (1 << 6) |
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| 245 | #define BACKLIGHT_OFF (1 << 5) |
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| 246 | #define BACKLIGHT_ON (1 << 4) |
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| 247 | #define COLOR_MODE_OFF (1 << 3) |
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| 248 | #define COLOR_MODE_ON (1 << 2) |
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| 249 | #define TURN_ON (1 << 1) |
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| 250 | #define SHUTDOWN (1 << 0) |
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| 251 | |
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| 252 | #define _MIPIA_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb04c) |
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| 253 | #define _MIPIC_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb84c) |
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| 254 | #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) |
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| 255 | #define COMMAND_BYTE_SHIFT 0 |
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| 256 | #define COMMAND_BYTE_MASK (0x3f << 0) |
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| 257 | |
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| 258 | #define _MIPIA_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb050) |
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| 259 | #define _MIPIC_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb850) |
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| 260 | #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) |
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| 261 | #define MASTER_INIT_TIMER_SHIFT 0 |
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| 262 | #define MASTER_INIT_TIMER_MASK (0xffff << 0) |
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| 263 | |
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| 264 | #define _MIPIA_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb054) |
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| 265 | #define _MIPIC_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb854) |
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| 266 | #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ |
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| 267 | _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) |
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| 268 | #define MAX_RETURN_PKT_SIZE_SHIFT 0 |
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| 269 | #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) |
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| 270 | |
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| 271 | #define _MIPIA_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb058) |
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| 272 | #define _MIPIC_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb858) |
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| 273 | #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) |
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| 274 | #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) |
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| 275 | #define DISABLE_VIDEO_BTA (1 << 3) |
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| 276 | #define IP_TG_CONFIG (1 << 2) |
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| 277 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) |
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| 278 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) |
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| 279 | #define VIDEO_MODE_BURST (3 << 0) |
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| 280 | |
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| 281 | #define _MIPIA_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb05c) |
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| 282 | #define _MIPIC_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb85c) |
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| 283 | #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) |
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| 284 | #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) |
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| 285 | #define BXT_DPHY_DEFEATURE_EN (1 << 8) |
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| 286 | #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) |
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| 287 | #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) |
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| 288 | #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) |
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| 289 | #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) |
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| 290 | #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) |
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| 291 | #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) |
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| 292 | #define CLOCKSTOP (1 << 1) |
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| 293 | #define EOT_DISABLE (1 << 0) |
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| 294 | |
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| 295 | #define _MIPIA_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb060) |
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| 296 | #define _MIPIC_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb860) |
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| 297 | #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) |
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| 298 | #define LP_BYTECLK_SHIFT 0 |
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| 299 | #define LP_BYTECLK_MASK (0xffff << 0) |
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| 300 | |
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| 301 | #define _MIPIA_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb0a4) |
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| 302 | #define _MIPIC_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb8a4) |
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| 303 | #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) |
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| 304 | |
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| 305 | #define _MIPIA_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb098) |
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| 306 | #define _MIPIC_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb898) |
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| 307 | #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) |
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| 308 | |
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| 309 | /* bits 31:0 */ |
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| 310 | #define _MIPIA_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb064) |
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| 311 | #define _MIPIC_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb864) |
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| 312 | #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) |
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| 313 | |
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| 314 | /* bits 31:0 */ |
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| 315 | #define _MIPIA_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb068) |
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| 316 | #define _MIPIC_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb868) |
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| 317 | #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) |
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| 318 | |
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| 319 | #define _MIPIA_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb06c) |
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| 320 | #define _MIPIC_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb86c) |
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| 321 | #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) |
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| 322 | #define _MIPIA_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb070) |
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| 323 | #define _MIPIC_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb870) |
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| 324 | #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) |
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| 325 | #define LONG_PACKET_WORD_COUNT_SHIFT 8 |
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| 326 | #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) |
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| 327 | #define SHORT_PACKET_PARAM_SHIFT 8 |
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| 328 | #define SHORT_PACKET_PARAM_MASK (0xffff << 8) |
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| 329 | #define VIRTUAL_CHANNEL_SHIFT 6 |
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| 330 | #define VIRTUAL_CHANNEL_MASK (3 << 6) |
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| 331 | #define DATA_TYPE_SHIFT 0 |
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| 332 | #define DATA_TYPE_MASK (0x3f << 0) |
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| 333 | /* data type values, see include/video/mipi_display.h */ |
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| 334 | |
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| 335 | #define _MIPIA_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb074) |
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| 336 | #define _MIPIC_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb874) |
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| 337 | #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) |
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| 338 | #define DPI_FIFO_EMPTY (1 << 28) |
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| 339 | #define DBI_FIFO_EMPTY (1 << 27) |
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| 340 | #define LP_CTRL_FIFO_EMPTY (1 << 26) |
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| 341 | #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) |
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| 342 | #define LP_CTRL_FIFO_FULL (1 << 24) |
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| 343 | #define HS_CTRL_FIFO_EMPTY (1 << 18) |
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| 344 | #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) |
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| 345 | #define HS_CTRL_FIFO_FULL (1 << 16) |
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| 346 | #define LP_DATA_FIFO_EMPTY (1 << 10) |
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| 347 | #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) |
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| 348 | #define LP_DATA_FIFO_FULL (1 << 8) |
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| 349 | #define HS_DATA_FIFO_EMPTY (1 << 2) |
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| 350 | #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) |
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| 351 | #define HS_DATA_FIFO_FULL (1 << 0) |
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| 352 | |
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| 353 | #define _MIPIA_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb078) |
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| 354 | #define _MIPIC_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb878) |
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| 355 | #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) |
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| 356 | #define DBI_HS_LP_MODE_MASK (1 << 0) |
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| 357 | #define DBI_LP_MODE (1 << 0) |
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| 358 | #define DBI_HS_MODE (0 << 0) |
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| 359 | |
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| 360 | #define _MIPIA_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb080) |
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| 361 | #define _MIPIC_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb880) |
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| 362 | #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) |
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| 363 | #define EXIT_ZERO_COUNT_SHIFT 24 |
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| 364 | #define EXIT_ZERO_COUNT_MASK (0x3f << 24) |
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| 365 | #define TRAIL_COUNT_SHIFT 16 |
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| 366 | #define TRAIL_COUNT_MASK (0x1f << 16) |
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| 367 | #define CLK_ZERO_COUNT_SHIFT 8 |
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| 368 | #define CLK_ZERO_COUNT_MASK (0xff << 8) |
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| 369 | #define PREPARE_COUNT_SHIFT 0 |
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| 370 | #define PREPARE_COUNT_MASK (0x3f << 0) |
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| 371 | |
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| 372 | #define _MIPIA_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb084) |
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| 373 | #define _MIPIC_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb884) |
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| 374 | #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) |
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| 375 | |
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| 376 | #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb088) |
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| 377 | #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb888) |
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| 378 | #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) |
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| 379 | #define LP_HS_SSW_CNT_SHIFT 16 |
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| 380 | #define LP_HS_SSW_CNT_MASK (0xffff << 16) |
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| 381 | #define HS_LP_PWR_SW_CNT_SHIFT 0 |
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| 382 | #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) |
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| 383 | |
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| 384 | #define _MIPIA_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb08c) |
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| 385 | #define _MIPIC_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb88c) |
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| 386 | #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) |
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| 387 | #define STOP_STATE_STALL_COUNTER_SHIFT 0 |
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| 388 | #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) |
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| 389 | |
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| 390 | #define _MIPIA_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb090) |
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| 391 | #define _MIPIC_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb890) |
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| 392 | #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) |
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| 393 | #define _MIPIA_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb094) |
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| 394 | #define _MIPIC_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb894) |
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| 395 | #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) |
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| 396 | #define RX_CONTENTION_DETECTED (1 << 0) |
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| 397 | |
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| 398 | /* XXX: only pipe A ?!? */ |
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| 399 | #define MIPIA_DBI_TYPEC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb100) |
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| 400 | #define DBI_TYPEC_ENABLE (1 << 31) |
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| 401 | #define DBI_TYPEC_WIP (1 << 30) |
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| 402 | #define DBI_TYPEC_OPTION_SHIFT 28 |
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| 403 | #define DBI_TYPEC_OPTION_MASK (3 << 28) |
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| 404 | #define DBI_TYPEC_FREQ_SHIFT 24 |
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| 405 | #define DBI_TYPEC_FREQ_MASK (0xf << 24) |
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| 406 | #define DBI_TYPEC_OVERRIDE (1 << 8) |
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| 407 | #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 |
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| 408 | #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) |
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| 409 | |
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| 410 | /* MIPI adapter registers */ |
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| 411 | |
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| 412 | #define _MIPIA_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb104) |
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| 413 | #define _MIPIC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb904) |
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| 414 | #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) |
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| 415 | #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ |
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| 416 | #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) |
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| 417 | #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) |
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| 418 | #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) |
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| 419 | #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) |
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| 420 | #define READ_REQUEST_PRIORITY_SHIFT 3 |
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| 421 | #define READ_REQUEST_PRIORITY_MASK (3 << 3) |
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| 422 | #define READ_REQUEST_PRIORITY_LOW (0 << 3) |
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| 423 | #define READ_REQUEST_PRIORITY_HIGH (3 << 3) |
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| 424 | #define RGB_FLIP_TO_BGR (1 << 2) |
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| 425 | |
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| 426 | #define BXT_PIPE_SELECT_SHIFT 7 |
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| 427 | #define BXT_PIPE_SELECT_MASK (7 << 7) |
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| 428 | #define BXT_PIPE_SELECT(pipe) ((pipe) << 7) |
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| 429 | #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */ |
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| 430 | #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */ |
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| 431 | #define GLK_MIPIIO_RESET_RELEASED (1 << 28) |
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| 432 | #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */ |
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| 433 | #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */ |
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| 434 | #define GLK_LP_WAKE (1 << 22) |
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| 435 | #define GLK_LP11_LOW_PWR_MODE (1 << 21) |
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| 436 | #define GLK_LP00_LOW_PWR_MODE (1 << 20) |
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| 437 | #define GLK_FIREWALL_ENABLE (1 << 16) |
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| 438 | #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) |
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| 439 | #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10 |
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| 440 | #define BXT_DSC_ENABLE (1 << 3) |
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| 441 | #define BXT_RGB_FLIP (1 << 2) |
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| 442 | #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ |
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| 443 | #define GLK_MIPIIO_ENABLE (1 << 0) |
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| 444 | |
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| 445 | #define _MIPIA_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb108) |
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| 446 | #define _MIPIC_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb908) |
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| 447 | #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) |
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| 448 | #define DATA_MEM_ADDRESS_SHIFT 5 |
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| 449 | #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) |
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| 450 | #define DATA_VALID (1 << 0) |
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| 451 | |
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| 452 | #define _MIPIA_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb10c) |
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| 453 | #define _MIPIC_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb90c) |
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| 454 | #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) |
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| 455 | #define DATA_LENGTH_SHIFT 0 |
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| 456 | #define DATA_LENGTH_MASK (0xfffff << 0) |
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| 457 | |
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| 458 | #define _MIPIA_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb110) |
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| 459 | #define _MIPIC_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb910) |
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| 460 | #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) |
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| 461 | #define COMMAND_MEM_ADDRESS_SHIFT 5 |
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| 462 | #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) |
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| 463 | #define AUTO_PWG_ENABLE (1 << 2) |
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| 464 | #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) |
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| 465 | #define COMMAND_VALID (1 << 0) |
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| 466 | |
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| 467 | #define _MIPIA_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb114) |
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| 468 | #define _MIPIC_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb914) |
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| 469 | #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) |
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| 470 | #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ |
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| 471 | #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) |
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| 472 | |
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| 473 | #define _MIPIA_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb118) |
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| 474 | #define _MIPIC_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb918) |
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| 475 | #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ |
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| 476 | |
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| 477 | #define _MIPIA_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb138) |
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| 478 | #define _MIPIC_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb938) |
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| 479 | #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) |
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| 480 | #define READ_DATA_VALID(n) (1 << (n)) |
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| 481 | |
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| 482 | #endif /* __VLV_DSI_REGS_H__ */ |
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| 483 | |
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