| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright(c) 2019-2022, Intel Corporation. All rights reserved. |
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| 4 | */ |
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| 5 | #ifndef __INTEL_GSC_DEV_H__ |
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| 6 | #define __INTEL_GSC_DEV_H__ |
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| 7 | |
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| 8 | #include <linux/types.h> |
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| 9 | |
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| 10 | struct drm_i915_private; |
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| 11 | struct intel_gt; |
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| 12 | struct mei_aux_device; |
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| 13 | |
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| 14 | #define INTEL_GSC_NUM_INTERFACES 2 |
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| 15 | /* |
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| 16 | * The HECI1 bit corresponds to bit15 and HECI2 to bit14. |
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| 17 | * The reason for this is to allow growth for more interfaces in the future. |
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| 18 | */ |
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| 19 | #define GSC_IRQ_INTF(_x) BIT(15 - (_x)) |
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| 20 | |
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| 21 | /** |
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| 22 | * struct intel_gsc - graphics security controller |
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| 23 | * |
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| 24 | * @intf: gsc interface |
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| 25 | * @intf.adev: MEI aux. device for this @intf |
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| 26 | * @intf.gem_obj: scratch memory GSC operations |
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| 27 | * @intf.irq: IRQ for this device (%-1 for no IRQ) |
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| 28 | * @intf.id: this interface's id number/index |
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| 29 | */ |
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| 30 | struct intel_gsc { |
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| 31 | struct intel_gsc_intf { |
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| 32 | struct mei_aux_device *adev; |
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| 33 | struct drm_i915_gem_object *gem_obj; |
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| 34 | int irq; |
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| 35 | unsigned int id; |
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| 36 | } intf[INTEL_GSC_NUM_INTERFACES]; |
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| 37 | }; |
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| 38 | |
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| 39 | void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915); |
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| 40 | void intel_gsc_fini(struct intel_gsc *gsc); |
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| 41 | void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir); |
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| 42 | |
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| 43 | #endif /* __INTEL_GSC_DEV_H__ */ |
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| 44 | |
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