| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2019 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef INTEL_GT_IRQ_H |
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| 7 | #define INTEL_GT_IRQ_H |
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| 8 | |
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| 9 | #include <linux/types.h> |
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| 10 | |
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| 11 | #include "intel_engine_types.h" |
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| 12 | |
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| 13 | struct intel_gt; |
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| 14 | |
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| 15 | #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \ |
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| 16 | GEN8_GT_BCS_IRQ | \ |
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| 17 | GEN8_GT_VCS0_IRQ | \ |
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| 18 | GEN8_GT_VCS1_IRQ | \ |
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| 19 | GEN8_GT_VECS_IRQ | \ |
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| 20 | GEN8_GT_PM_IRQ | \ |
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| 21 | GEN8_GT_GUC_IRQ) |
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| 22 | |
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| 23 | void gen11_gt_irq_reset(struct intel_gt *gt); |
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| 24 | void gen11_gt_irq_postinstall(struct intel_gt *gt); |
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| 25 | void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl); |
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| 26 | |
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| 27 | bool gen11_gt_reset_one_iir(struct intel_gt *gt, |
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| 28 | const unsigned int bank, |
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| 29 | const unsigned int bit); |
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| 30 | |
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| 31 | void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir); |
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| 32 | |
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| 33 | void gen5_gt_irq_postinstall(struct intel_gt *gt); |
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| 34 | void gen5_gt_irq_reset(struct intel_gt *gt); |
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| 35 | void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask); |
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| 36 | void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask); |
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| 37 | |
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| 38 | void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir); |
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| 39 | |
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| 40 | void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl); |
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| 41 | void gen8_gt_irq_reset(struct intel_gt *gt); |
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| 42 | void gen8_gt_irq_postinstall(struct intel_gt *gt); |
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| 43 | |
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| 44 | static inline void intel_engine_cs_irq(struct intel_engine_cs *engine, u16 iir) |
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| 45 | { |
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| 46 | if (iir) |
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| 47 | engine->irq_handler(engine, iir); |
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| 48 | } |
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| 49 | |
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| 50 | static inline void |
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| 51 | intel_engine_set_irq_handler(struct intel_engine_cs *engine, |
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| 52 | void (*fn)(struct intel_engine_cs *engine, |
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| 53 | u16 iir)) |
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| 54 | { |
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| 55 | /* |
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| 56 | * As the interrupt is live as allocate and setup the engines, |
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| 57 | * err on the side of caution and apply barriers to updating |
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| 58 | * the irq handler callback. This assures that when we do use |
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| 59 | * the engine, we will receive interrupts only to ourselves, |
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| 60 | * and not lose any. |
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| 61 | */ |
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| 62 | smp_store_mb(engine->irq_handler, fn); |
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| 63 | } |
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| 64 | |
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| 65 | #endif /* INTEL_GT_IRQ_H */ |
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| 66 | |
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