| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | // |
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| 3 | // Ingenic JZ47xx KMS driver - Register definitions and private API |
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| 4 | // |
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| 5 | // Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net> |
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| 6 | |
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| 7 | #ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H |
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| 8 | #define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H |
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| 9 | |
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| 10 | #include <linux/bitops.h> |
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| 11 | #include <linux/types.h> |
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| 12 | |
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| 13 | #define JZ_REG_LCD_CFG 0x00 |
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| 14 | #define JZ_REG_LCD_VSYNC 0x04 |
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| 15 | #define JZ_REG_LCD_HSYNC 0x08 |
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| 16 | #define JZ_REG_LCD_VAT 0x0C |
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| 17 | #define JZ_REG_LCD_DAH 0x10 |
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| 18 | #define JZ_REG_LCD_DAV 0x14 |
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| 19 | #define JZ_REG_LCD_PS 0x18 |
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| 20 | #define JZ_REG_LCD_CLS 0x1C |
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| 21 | #define JZ_REG_LCD_SPL 0x20 |
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| 22 | #define JZ_REG_LCD_REV 0x24 |
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| 23 | #define JZ_REG_LCD_CTRL 0x30 |
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| 24 | #define JZ_REG_LCD_STATE 0x34 |
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| 25 | #define JZ_REG_LCD_IID 0x38 |
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| 26 | #define JZ_REG_LCD_DA0 0x40 |
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| 27 | #define JZ_REG_LCD_SA0 0x44 |
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| 28 | #define JZ_REG_LCD_FID0 0x48 |
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| 29 | #define JZ_REG_LCD_CMD0 0x4C |
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| 30 | #define JZ_REG_LCD_DA1 0x50 |
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| 31 | #define JZ_REG_LCD_SA1 0x54 |
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| 32 | #define JZ_REG_LCD_FID1 0x58 |
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| 33 | #define JZ_REG_LCD_CMD1 0x5C |
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| 34 | #define JZ_REG_LCD_RGBC 0x90 |
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| 35 | #define JZ_REG_LCD_OSDC 0x100 |
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| 36 | #define JZ_REG_LCD_OSDCTRL 0x104 |
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| 37 | #define JZ_REG_LCD_OSDS 0x108 |
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| 38 | #define JZ_REG_LCD_BGC 0x10c |
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| 39 | #define JZ_REG_LCD_KEY0 0x110 |
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| 40 | #define JZ_REG_LCD_KEY1 0x114 |
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| 41 | #define JZ_REG_LCD_ALPHA 0x118 |
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| 42 | #define JZ_REG_LCD_IPUR 0x11c |
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| 43 | #define JZ_REG_LCD_XYP0 0x120 |
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| 44 | #define JZ_REG_LCD_XYP1 0x124 |
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| 45 | #define JZ_REG_LCD_SIZE0 0x128 |
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| 46 | #define JZ_REG_LCD_SIZE1 0x12c |
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| 47 | #define JZ_REG_LCD_PCFG 0x2c0 |
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| 48 | |
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| 49 | #define JZ_LCD_CFG_SLCD BIT(31) |
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| 50 | #define JZ_LCD_CFG_DESCRIPTOR_8 BIT(28) |
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| 51 | #define JZ_LCD_CFG_RECOVER_FIFO_UNDERRUN BIT(25) |
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| 52 | #define JZ_LCD_CFG_PS_DISABLE BIT(23) |
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| 53 | #define JZ_LCD_CFG_CLS_DISABLE BIT(22) |
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| 54 | #define JZ_LCD_CFG_SPL_DISABLE BIT(21) |
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| 55 | #define JZ_LCD_CFG_REV_DISABLE BIT(20) |
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| 56 | #define JZ_LCD_CFG_HSYNCM BIT(19) |
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| 57 | #define JZ_LCD_CFG_PCLKM BIT(18) |
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| 58 | #define JZ_LCD_CFG_INV BIT(17) |
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| 59 | #define JZ_LCD_CFG_SYNC_DIR BIT(16) |
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| 60 | #define JZ_LCD_CFG_PS_POLARITY BIT(15) |
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| 61 | #define JZ_LCD_CFG_CLS_POLARITY BIT(14) |
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| 62 | #define JZ_LCD_CFG_SPL_POLARITY BIT(13) |
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| 63 | #define JZ_LCD_CFG_REV_POLARITY BIT(12) |
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| 64 | #define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11) |
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| 65 | #define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10) |
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| 66 | #define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) |
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| 67 | #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8) |
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| 68 | #define JZ_LCD_CFG_18_BIT BIT(7) |
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| 69 | #define JZ_LCD_CFG_24_BIT BIT(6) |
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| 70 | #define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) |
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| 71 | |
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| 72 | #define JZ_LCD_CFG_MODE_GENERIC_16BIT 0 |
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| 73 | #define JZ_LCD_CFG_MODE_GENERIC_18BIT BIT(7) |
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| 74 | #define JZ_LCD_CFG_MODE_GENERIC_24BIT BIT(6) |
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| 75 | |
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| 76 | #define JZ_LCD_CFG_MODE_SPECIAL_TFT_1 1 |
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| 77 | #define JZ_LCD_CFG_MODE_SPECIAL_TFT_2 2 |
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| 78 | #define JZ_LCD_CFG_MODE_SPECIAL_TFT_3 3 |
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| 79 | |
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| 80 | #define JZ_LCD_CFG_MODE_TV_OUT_P 4 |
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| 81 | #define JZ_LCD_CFG_MODE_TV_OUT_I 6 |
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| 82 | |
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| 83 | #define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN 8 |
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| 84 | #define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN 9 |
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| 85 | #define JZ_LCD_CFG_MODE_DUAL_COLOR_STN 10 |
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| 86 | #define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN 11 |
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| 87 | |
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| 88 | #define JZ_LCD_CFG_MODE_8BIT_SERIAL 12 |
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| 89 | #define JZ_LCD_CFG_MODE_LCM 13 |
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| 90 | |
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| 91 | #define JZ_LCD_VSYNC_VPS_OFFSET 16 |
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| 92 | #define JZ_LCD_VSYNC_VPE_OFFSET 0 |
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| 93 | |
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| 94 | #define JZ_LCD_HSYNC_HPS_OFFSET 16 |
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| 95 | #define JZ_LCD_HSYNC_HPE_OFFSET 0 |
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| 96 | |
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| 97 | #define JZ_LCD_VAT_HT_OFFSET 16 |
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| 98 | #define JZ_LCD_VAT_VT_OFFSET 0 |
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| 99 | |
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| 100 | #define JZ_LCD_DAH_HDS_OFFSET 16 |
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| 101 | #define JZ_LCD_DAH_HDE_OFFSET 0 |
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| 102 | |
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| 103 | #define JZ_LCD_DAV_VDS_OFFSET 16 |
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| 104 | #define JZ_LCD_DAV_VDE_OFFSET 0 |
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| 105 | |
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| 106 | #define JZ_LCD_CTRL_BURST_4 (0x0 << 28) |
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| 107 | #define JZ_LCD_CTRL_BURST_8 (0x1 << 28) |
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| 108 | #define JZ_LCD_CTRL_BURST_16 (0x2 << 28) |
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| 109 | #define JZ_LCD_CTRL_BURST_32 (0x3 << 28) |
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| 110 | #define JZ_LCD_CTRL_BURST_64 (0x4 << 28) |
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| 111 | #define JZ_LCD_CTRL_BURST_MASK (0x7 << 28) |
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| 112 | #define JZ_LCD_CTRL_RGB555 BIT(27) |
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| 113 | #define JZ_LCD_CTRL_OFUP BIT(26) |
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| 114 | #define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24) |
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| 115 | #define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24) |
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| 116 | #define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24) |
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| 117 | #define JZ_LCD_CTRL_PDD_MASK (0xff << 16) |
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| 118 | #define JZ_LCD_CTRL_EOF_IRQ BIT(13) |
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| 119 | #define JZ_LCD_CTRL_SOF_IRQ BIT(12) |
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| 120 | #define JZ_LCD_CTRL_OFU_IRQ BIT(11) |
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| 121 | #define JZ_LCD_CTRL_IFU0_IRQ BIT(10) |
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| 122 | #define JZ_LCD_CTRL_IFU1_IRQ BIT(9) |
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| 123 | #define JZ_LCD_CTRL_DD_IRQ BIT(8) |
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| 124 | #define JZ_LCD_CTRL_QDD_IRQ BIT(7) |
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| 125 | #define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6) |
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| 126 | #define JZ_LCD_CTRL_LSB_FISRT BIT(5) |
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| 127 | #define JZ_LCD_CTRL_DISABLE BIT(4) |
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| 128 | #define JZ_LCD_CTRL_ENABLE BIT(3) |
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| 129 | #define JZ_LCD_CTRL_BPP_1 0x0 |
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| 130 | #define JZ_LCD_CTRL_BPP_2 0x1 |
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| 131 | #define JZ_LCD_CTRL_BPP_4 0x2 |
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| 132 | #define JZ_LCD_CTRL_BPP_8 0x3 |
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| 133 | #define JZ_LCD_CTRL_BPP_15_16 0x4 |
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| 134 | #define JZ_LCD_CTRL_BPP_18_24 0x5 |
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| 135 | #define JZ_LCD_CTRL_BPP_24_COMP 0x6 |
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| 136 | #define JZ_LCD_CTRL_BPP_30 0x7 |
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| 137 | #define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7) |
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| 138 | |
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| 139 | #define JZ_LCD_CMD_SOF_IRQ BIT(31) |
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| 140 | #define JZ_LCD_CMD_EOF_IRQ BIT(30) |
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| 141 | #define JZ_LCD_CMD_ENABLE_PAL BIT(28) |
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| 142 | #define JZ_LCD_CMD_FRM_ENABLE BIT(26) |
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| 143 | |
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| 144 | #define JZ_LCD_SYNC_MASK 0x3ff |
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| 145 | |
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| 146 | #define JZ_LCD_STATE_EOF_IRQ BIT(5) |
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| 147 | #define JZ_LCD_STATE_SOF_IRQ BIT(4) |
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| 148 | #define JZ_LCD_STATE_DISABLED BIT(0) |
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| 149 | |
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| 150 | #define JZ_LCD_RGBC_ODD_RGB (0x0 << 4) |
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| 151 | #define JZ_LCD_RGBC_ODD_RBG (0x1 << 4) |
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| 152 | #define JZ_LCD_RGBC_ODD_GRB (0x2 << 4) |
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| 153 | #define JZ_LCD_RGBC_ODD_GBR (0x3 << 4) |
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| 154 | #define JZ_LCD_RGBC_ODD_BRG (0x4 << 4) |
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| 155 | #define JZ_LCD_RGBC_ODD_BGR (0x5 << 4) |
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| 156 | #define JZ_LCD_RGBC_EVEN_RGB (0x0 << 0) |
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| 157 | #define JZ_LCD_RGBC_EVEN_RBG (0x1 << 0) |
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| 158 | #define JZ_LCD_RGBC_EVEN_GRB (0x2 << 0) |
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| 159 | #define JZ_LCD_RGBC_EVEN_GBR (0x3 << 0) |
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| 160 | #define JZ_LCD_RGBC_EVEN_BRG (0x4 << 0) |
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| 161 | #define JZ_LCD_RGBC_EVEN_BGR (0x5 << 0) |
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| 162 | |
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| 163 | #define JZ_LCD_OSDC_OSDEN BIT(0) |
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| 164 | #define JZ_LCD_OSDC_ALPHAEN BIT(2) |
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| 165 | #define JZ_LCD_OSDC_F0EN BIT(3) |
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| 166 | #define JZ_LCD_OSDC_F1EN BIT(4) |
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| 167 | |
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| 168 | #define JZ_LCD_OSDCTRL_IPU BIT(15) |
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| 169 | #define JZ_LCD_OSDCTRL_RGB555 BIT(4) |
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| 170 | #define JZ_LCD_OSDCTRL_CHANGE BIT(3) |
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| 171 | #define JZ_LCD_OSDCTRL_BPP_15_16 0x4 |
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| 172 | #define JZ_LCD_OSDCTRL_BPP_18_24 0x5 |
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| 173 | #define JZ_LCD_OSDCTRL_BPP_24_COMP 0x6 |
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| 174 | #define JZ_LCD_OSDCTRL_BPP_30 0x7 |
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| 175 | #define JZ_LCD_OSDCTRL_BPP_MASK (JZ_LCD_OSDCTRL_RGB555 | 0x7) |
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| 176 | |
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| 177 | #define JZ_LCD_OSDS_READY BIT(0) |
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| 178 | |
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| 179 | #define JZ_LCD_IPUR_IPUREN BIT(31) |
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| 180 | #define JZ_LCD_IPUR_IPUR_LSB 0 |
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| 181 | |
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| 182 | #define JZ_LCD_XYP01_XPOS_LSB 0 |
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| 183 | #define JZ_LCD_XYP01_YPOS_LSB 16 |
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| 184 | |
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| 185 | #define JZ_LCD_SIZE01_WIDTH_LSB 0 |
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| 186 | #define JZ_LCD_SIZE01_HEIGHT_LSB 16 |
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| 187 | |
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| 188 | #define JZ_LCD_DESSIZE_ALPHA_OFFSET 24 |
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| 189 | #define JZ_LCD_DESSIZE_HEIGHT_MASK GENMASK(23, 12) |
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| 190 | #define JZ_LCD_DESSIZE_WIDTH_MASK GENMASK(11, 0) |
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| 191 | |
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| 192 | #define JZ_LCD_CPOS_BPP_15_16 (4 << 27) |
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| 193 | #define JZ_LCD_CPOS_BPP_18_24 (5 << 27) |
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| 194 | #define JZ_LCD_CPOS_BPP_30 (7 << 27) |
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| 195 | #define JZ_LCD_CPOS_RGB555 BIT(30) |
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| 196 | #define JZ_LCD_CPOS_PREMULTIPLY_LCD BIT(26) |
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| 197 | #define JZ_LCD_CPOS_COEFFICIENT_OFFSET 24 |
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| 198 | #define JZ_LCD_CPOS_COEFFICIENT_0 0 |
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| 199 | #define JZ_LCD_CPOS_COEFFICIENT_1 1 |
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| 200 | #define JZ_LCD_CPOS_COEFFICIENT_ALPHA1 2 |
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| 201 | #define JZ_LCD_CPOS_COEFFICIENT_1_ALPHA1 3 |
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| 202 | |
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| 203 | #define JZ_LCD_RGBC_RGB_PADDING BIT(15) |
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| 204 | #define JZ_LCD_RGBC_RGB_PADDING_FIRST BIT(14) |
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| 205 | #define JZ_LCD_RGBC_422 BIT(8) |
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| 206 | #define JZ_LCD_RGBC_RGB_FORMAT_ENABLE BIT(7) |
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| 207 | |
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| 208 | #define JZ_LCD_PCFG_PRI_MODE BIT(31) |
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| 209 | #define JZ_LCD_PCFG_HP_BST_4 (0 << 28) |
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| 210 | #define JZ_LCD_PCFG_HP_BST_8 (1 << 28) |
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| 211 | #define JZ_LCD_PCFG_HP_BST_16 (2 << 28) |
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| 212 | #define JZ_LCD_PCFG_HP_BST_32 (3 << 28) |
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| 213 | #define JZ_LCD_PCFG_HP_BST_64 (4 << 28) |
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| 214 | #define JZ_LCD_PCFG_HP_BST_16_CONT (5 << 28) |
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| 215 | #define JZ_LCD_PCFG_HP_BST_DISABLE (7 << 28) |
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| 216 | #define JZ_LCD_PCFG_THRESHOLD2_OFFSET 18 |
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| 217 | #define JZ_LCD_PCFG_THRESHOLD1_OFFSET 9 |
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| 218 | #define JZ_LCD_PCFG_THRESHOLD0_OFFSET 0 |
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| 219 | |
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| 220 | struct device; |
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| 221 | struct drm_plane; |
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| 222 | struct drm_plane_state; |
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| 223 | struct platform_driver; |
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| 224 | |
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| 225 | void ingenic_drm_plane_config(struct device *dev, |
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| 226 | struct drm_plane *plane, u32 fourcc); |
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| 227 | void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane); |
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| 228 | bool ingenic_drm_map_noncoherent(const struct device *dev); |
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| 229 | |
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| 230 | extern struct platform_driver *ingenic_ipu_driver_ptr; |
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| 231 | |
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| 232 | #endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */ |
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| 233 | |
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