| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2014 MediaTek Inc. |
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| 4 | * Author: Jie Qiu <jie.qiu@mediatek.com> |
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| 5 | */ |
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| 6 | #ifndef __MTK_DPI_REGS_H |
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| 7 | #define __MTK_DPI_REGS_H |
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| 8 | |
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| 9 | #define DPI_EN 0x00 |
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| 10 | #define EN BIT(0) |
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| 11 | |
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| 12 | #define DPI_RET 0x04 |
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| 13 | #define RST BIT(0) |
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| 14 | |
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| 15 | #define DPI_INTEN 0x08 |
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| 16 | #define INT_VSYNC_EN BIT(0) |
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| 17 | #define INT_VDE_EN BIT(1) |
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| 18 | #define INT_UNDERFLOW_EN BIT(2) |
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| 19 | |
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| 20 | #define DPI_INTSTA 0x0C |
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| 21 | #define INT_VSYNC_STA BIT(0) |
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| 22 | #define INT_VDE_STA BIT(1) |
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| 23 | #define INT_UNDERFLOW_STA BIT(2) |
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| 24 | |
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| 25 | #define DPI_CON 0x10 |
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| 26 | #define BG_ENABLE BIT(0) |
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| 27 | #define IN_RB_SWAP BIT(1) |
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| 28 | #define INTL_EN BIT(2) |
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| 29 | #define TDFP_EN BIT(3) |
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| 30 | #define CLPF_EN BIT(4) |
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| 31 | #define YUV422_EN BIT(5) |
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| 32 | #define CSC_ENABLE BIT(6) |
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| 33 | #define R601_SEL BIT(7) |
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| 34 | #define EMBSYNC_EN BIT(8) |
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| 35 | #define VS_LODD_EN BIT(16) |
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| 36 | #define VS_LEVEN_EN BIT(17) |
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| 37 | #define VS_RODD_EN BIT(18) |
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| 38 | #define VS_REVEN BIT(19) |
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| 39 | #define FAKE_DE_LODD BIT(20) |
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| 40 | #define FAKE_DE_LEVEN BIT(21) |
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| 41 | #define FAKE_DE_RODD BIT(22) |
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| 42 | #define FAKE_DE_REVEN BIT(23) |
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| 43 | #define DPINTF_YUV422_EN BIT(24) |
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| 44 | #define DPINTF_CSC_ENABLE BIT(26) |
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| 45 | #define DPINTF_INPUT_2P_EN BIT(29) |
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| 46 | |
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| 47 | #define DPI_OUTPUT_SETTING 0x14 |
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| 48 | #define CH_SWAP 0 |
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| 49 | #define DPINTF_CH_SWAP 1 |
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| 50 | #define CH_SWAP_MASK (0x7 << 0) |
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| 51 | #define SWAP_RGB 0x00 |
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| 52 | #define SWAP_GBR 0x01 |
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| 53 | #define SWAP_BRG 0x02 |
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| 54 | #define SWAP_RBG 0x03 |
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| 55 | #define SWAP_GRB 0x04 |
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| 56 | #define SWAP_BGR 0x05 |
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| 57 | #define BIT_SWAP BIT(3) |
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| 58 | #define B_MASK BIT(4) |
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| 59 | #define G_MASK BIT(5) |
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| 60 | #define R_MASK BIT(6) |
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| 61 | #define DE_MASK BIT(8) |
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| 62 | #define HS_MASK BIT(9) |
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| 63 | #define VS_MASK BIT(10) |
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| 64 | #define DE_POL BIT(12) |
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| 65 | #define HSYNC_POL BIT(13) |
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| 66 | #define VSYNC_POL BIT(14) |
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| 67 | #define CK_POL BIT(15) |
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| 68 | #define OEN_OFF BIT(16) |
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| 69 | #define EDGE_SEL BIT(17) |
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| 70 | #define OUT_BIT 18 |
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| 71 | #define OUT_BIT_MASK (0x3 << 18) |
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| 72 | #define OUT_BIT_8 0x00 |
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| 73 | #define OUT_BIT_10 0x01 |
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| 74 | #define OUT_BIT_12 0x02 |
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| 75 | #define OUT_BIT_16 0x03 |
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| 76 | #define YC_MAP 20 |
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| 77 | #define YC_MAP_MASK (0x7 << 20) |
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| 78 | #define YC_MAP_RGB 0x00 |
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| 79 | #define YC_MAP_CYCY 0x04 |
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| 80 | #define YC_MAP_YCYC 0x05 |
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| 81 | #define YC_MAP_CY 0x06 |
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| 82 | #define YC_MAP_YC 0x07 |
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| 83 | |
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| 84 | #define DPI_SIZE 0x18 |
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| 85 | #define HSIZE 0 |
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| 86 | #define HSIZE_MASK (0x1FFF << 0) |
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| 87 | #define DPINTF_HSIZE_MASK (0xFFFF << 0) |
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| 88 | #define VSIZE 16 |
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| 89 | #define VSIZE_MASK (0x1FFF << 16) |
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| 90 | #define DPINTF_VSIZE_MASK (0xFFFF << 16) |
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| 91 | |
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| 92 | #define DPI_DDR_SETTING 0x1C |
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| 93 | #define DDR_EN BIT(0) |
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| 94 | #define DDDR_SEL BIT(1) |
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| 95 | #define DDR_4PHASE BIT(2) |
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| 96 | #define DDR_WIDTH (0x3 << 4) |
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| 97 | #define DDR_PAD_MODE (0x1 << 8) |
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| 98 | |
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| 99 | #define DPI_TGEN_HWIDTH 0x20 |
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| 100 | #define HPW 0 |
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| 101 | #define HPW_MASK (0xFFF << 0) |
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| 102 | #define DPINTF_HPW_MASK (0xFFFF << 0) |
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| 103 | |
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| 104 | #define DPI_TGEN_HPORCH 0x24 |
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| 105 | #define HBP 0 |
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| 106 | #define HBP_MASK (0xFFF << 0) |
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| 107 | #define DPINTF_HBP_MASK (0xFFFF << 0) |
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| 108 | #define HFP 16 |
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| 109 | #define HFP_MASK (0xFFF << 16) |
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| 110 | #define DPINTF_HFP_MASK (0xFFFF << 16) |
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| 111 | |
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| 112 | #define DPI_TGEN_VWIDTH 0x28 |
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| 113 | #define DPI_TGEN_VPORCH 0x2C |
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| 114 | |
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| 115 | #define VSYNC_WIDTH_SHIFT 0 |
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| 116 | #define VSYNC_WIDTH_MASK (0xFFF << 0) |
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| 117 | #define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0) |
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| 118 | #define VSYNC_HALF_LINE_SHIFT 16 |
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| 119 | #define VSYNC_HALF_LINE_MASK BIT(16) |
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| 120 | #define VSYNC_BACK_PORCH_SHIFT 0 |
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| 121 | #define VSYNC_BACK_PORCH_MASK (0xFFF << 0) |
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| 122 | #define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0) |
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| 123 | #define VSYNC_FRONT_PORCH_SHIFT 16 |
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| 124 | #define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) |
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| 125 | #define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16) |
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| 126 | |
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| 127 | #define DPI_BG_HCNTL 0x30 |
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| 128 | #define BG_RIGHT (0x1FFF << 0) |
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| 129 | #define BG_LEFT (0x1FFF << 16) |
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| 130 | |
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| 131 | #define DPI_BG_VCNTL 0x34 |
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| 132 | #define BG_BOT (0x1FFF << 0) |
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| 133 | #define BG_TOP (0x1FFF << 16) |
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| 134 | |
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| 135 | #define DPI_BG_COLOR 0x38 |
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| 136 | #define BG_B (0xF << 0) |
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| 137 | #define BG_G (0xF << 8) |
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| 138 | #define BG_R (0xF << 16) |
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| 139 | |
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| 140 | #define DPI_FIFO_CTL 0x3C |
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| 141 | #define FIFO_VALID_SET (0x1F << 0) |
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| 142 | #define FIFO_RST_SEL (0x1 << 8) |
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| 143 | |
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| 144 | #define DPI_STATUS 0x40 |
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| 145 | #define VCOUNTER (0x1FFF << 0) |
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| 146 | #define DPI_BUSY BIT(16) |
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| 147 | #define OUTEN BIT(17) |
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| 148 | #define FIELD BIT(20) |
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| 149 | #define TDLR BIT(21) |
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| 150 | |
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| 151 | #define DPI_TMODE 0x44 |
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| 152 | #define DPI_OEN_ON BIT(0) |
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| 153 | |
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| 154 | #define DPI_CHECKSUM 0x48 |
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| 155 | #define DPI_CHECKSUM_MASK (0xFFFFFF << 0) |
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| 156 | #define DPI_CHECKSUM_READY BIT(30) |
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| 157 | #define DPI_CHECKSUM_EN BIT(31) |
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| 158 | |
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| 159 | #define DPI_DUMMY 0x50 |
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| 160 | #define DPI_DUMMY_MASK (0xFFFFFFFF << 0) |
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| 161 | |
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| 162 | #define DPI_TGEN_VWIDTH_LEVEN 0x68 |
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| 163 | #define DPI_TGEN_VPORCH_LEVEN 0x6C |
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| 164 | #define DPI_TGEN_VWIDTH_RODD 0x70 |
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| 165 | #define DPI_TGEN_VPORCH_RODD 0x74 |
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| 166 | #define DPI_TGEN_VWIDTH_REVEN 0x78 |
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| 167 | #define DPI_TGEN_VPORCH_REVEN 0x7C |
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| 168 | |
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| 169 | #define DPI_ESAV_VTIMING_LODD 0x80 |
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| 170 | #define ESAV_VOFST_LODD (0xFFF << 0) |
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| 171 | #define ESAV_VWID_LODD (0xFFF << 16) |
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| 172 | |
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| 173 | #define DPI_ESAV_VTIMING_LEVEN 0x84 |
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| 174 | #define ESAV_VOFST_LEVEN (0xFFF << 0) |
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| 175 | #define ESAV_VWID_LEVEN (0xFFF << 16) |
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| 176 | |
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| 177 | #define DPI_ESAV_VTIMING_RODD 0x88 |
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| 178 | #define ESAV_VOFST_RODD (0xFFF << 0) |
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| 179 | #define ESAV_VWID_RODD (0xFFF << 16) |
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| 180 | |
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| 181 | #define DPI_ESAV_VTIMING_REVEN 0x8C |
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| 182 | #define ESAV_VOFST_REVEN (0xFFF << 0) |
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| 183 | #define ESAV_VWID_REVEN (0xFFF << 16) |
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| 184 | |
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| 185 | #define DPI_ESAV_FTIMING 0x90 |
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| 186 | #define ESAV_FOFST_ODD (0xFFF << 0) |
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| 187 | #define ESAV_FOFST_EVEN (0xFFF << 16) |
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| 188 | |
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| 189 | #define DPI_CLPF_SETTING 0x94 |
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| 190 | #define CLPF_TYPE (0x3 << 0) |
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| 191 | #define ROUND_EN BIT(4) |
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| 192 | |
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| 193 | #define DPI_Y_LIMIT 0x98 |
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| 194 | #define Y_LIMINT_BOT 0 |
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| 195 | #define Y_LIMINT_BOT_MASK (0xFFF << 0) |
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| 196 | #define Y_LIMINT_TOP 16 |
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| 197 | #define Y_LIMINT_TOP_MASK (0xFFF << 16) |
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| 198 | |
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| 199 | #define DPI_C_LIMIT 0x9C |
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| 200 | #define C_LIMIT_BOT 0 |
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| 201 | #define C_LIMIT_BOT_MASK (0xFFF << 0) |
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| 202 | #define C_LIMIT_TOP 16 |
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| 203 | #define C_LIMIT_TOP_MASK (0xFFF << 16) |
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| 204 | |
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| 205 | #define DPI_YUV422_SETTING 0xA0 |
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| 206 | #define UV_SWAP BIT(0) |
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| 207 | #define CR_DELSEL BIT(4) |
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| 208 | #define CB_DELSEL BIT(5) |
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| 209 | #define Y_DELSEL BIT(6) |
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| 210 | #define DE_DELSEL BIT(7) |
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| 211 | |
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| 212 | #define DPI_EMBSYNC_SETTING 0xA4 |
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| 213 | #define EMBSYNC_R_CR_EN BIT(0) |
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| 214 | #define EMPSYNC_G_Y_EN BIT(1) |
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| 215 | #define EMPSYNC_B_CB_EN BIT(2) |
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| 216 | #define ESAV_F_INV BIT(4) |
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| 217 | #define ESAV_V_INV BIT(5) |
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| 218 | #define ESAV_H_INV BIT(6) |
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| 219 | #define ESAV_CODE_MAN BIT(8) |
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| 220 | #define VS_OUT_SEL (0x7 << 12) |
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| 221 | |
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| 222 | #define DPI_ESAV_CODE_SET0 0xA8 |
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| 223 | #define ESAV_CODE0 (0xFFF << 0) |
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| 224 | #define ESAV_CODE1 (0xFFF << 16) |
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| 225 | |
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| 226 | #define DPI_ESAV_CODE_SET1 0xAC |
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| 227 | #define ESAV_CODE2 (0xFFF << 0) |
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| 228 | #define ESAV_CODE3_MSB BIT(16) |
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| 229 | |
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| 230 | #define EDGE_SEL_EN BIT(5) |
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| 231 | #define H_FRE_2N BIT(25) |
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| 232 | |
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| 233 | #define DPI_MATRIX_SET 0xB4 |
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| 234 | #define INT_MATRIX_SEL_MASK GENMASK(4, 0) |
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| 235 | #define MATRIX_SEL_RGB_TO_JPEG 0 |
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| 236 | #define MATRIX_SEL_RGB_TO_BT601 2 |
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| 237 | |
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| 238 | #endif /* __MTK_DPI_REGS_H */ |
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| 239 | |
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