1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2014 MediaTek Inc. |
4 | * Author: Jie Qiu <jie.qiu@mediatek.com> |
5 | */ |
6 | |
7 | #include <linux/clk.h> |
8 | #include <linux/component.h> |
9 | #include <linux/interrupt.h> |
10 | #include <linux/kernel.h> |
11 | #include <linux/media-bus-format.h> |
12 | #include <linux/of.h> |
13 | #include <linux/of_graph.h> |
14 | #include <linux/pinctrl/consumer.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/soc/mediatek/mtk-mmsys.h> |
17 | #include <linux/types.h> |
18 | |
19 | #include <video/videomode.h> |
20 | |
21 | #include <drm/drm_atomic_helper.h> |
22 | #include <drm/drm_bridge.h> |
23 | #include <drm/drm_bridge_connector.h> |
24 | #include <drm/drm_crtc.h> |
25 | #include <drm/drm_edid.h> |
26 | #include <drm/drm_of.h> |
27 | #include <drm/drm_simple_kms_helper.h> |
28 | |
29 | #include "mtk_disp_drv.h" |
30 | #include "mtk_dpi_regs.h" |
31 | #include "mtk_drm_ddp_comp.h" |
32 | #include "mtk_drm_drv.h" |
33 | |
34 | enum mtk_dpi_out_bit_num { |
35 | MTK_DPI_OUT_BIT_NUM_8BITS, |
36 | MTK_DPI_OUT_BIT_NUM_10BITS, |
37 | MTK_DPI_OUT_BIT_NUM_12BITS, |
38 | MTK_DPI_OUT_BIT_NUM_16BITS |
39 | }; |
40 | |
41 | enum mtk_dpi_out_yc_map { |
42 | MTK_DPI_OUT_YC_MAP_RGB, |
43 | MTK_DPI_OUT_YC_MAP_CYCY, |
44 | MTK_DPI_OUT_YC_MAP_YCYC, |
45 | MTK_DPI_OUT_YC_MAP_CY, |
46 | MTK_DPI_OUT_YC_MAP_YC |
47 | }; |
48 | |
49 | enum mtk_dpi_out_channel_swap { |
50 | MTK_DPI_OUT_CHANNEL_SWAP_RGB, |
51 | MTK_DPI_OUT_CHANNEL_SWAP_GBR, |
52 | MTK_DPI_OUT_CHANNEL_SWAP_BRG, |
53 | MTK_DPI_OUT_CHANNEL_SWAP_RBG, |
54 | MTK_DPI_OUT_CHANNEL_SWAP_GRB, |
55 | MTK_DPI_OUT_CHANNEL_SWAP_BGR |
56 | }; |
57 | |
58 | enum mtk_dpi_out_color_format { |
59 | MTK_DPI_COLOR_FORMAT_RGB, |
60 | MTK_DPI_COLOR_FORMAT_YCBCR_422 |
61 | }; |
62 | |
63 | struct mtk_dpi { |
64 | struct drm_encoder encoder; |
65 | struct drm_bridge bridge; |
66 | struct drm_bridge *next_bridge; |
67 | struct drm_connector *connector; |
68 | void __iomem *regs; |
69 | struct device *dev; |
70 | struct device *mmsys_dev; |
71 | struct clk *engine_clk; |
72 | struct clk *pixel_clk; |
73 | struct clk *tvd_clk; |
74 | int irq; |
75 | struct drm_display_mode mode; |
76 | const struct mtk_dpi_conf *conf; |
77 | enum mtk_dpi_out_color_format color_format; |
78 | enum mtk_dpi_out_yc_map yc_map; |
79 | enum mtk_dpi_out_bit_num bit_num; |
80 | enum mtk_dpi_out_channel_swap channel_swap; |
81 | struct pinctrl *pinctrl; |
82 | struct pinctrl_state *pins_gpio; |
83 | struct pinctrl_state *pins_dpi; |
84 | u32 output_fmt; |
85 | int refcount; |
86 | }; |
87 | |
88 | static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b) |
89 | { |
90 | return container_of(b, struct mtk_dpi, bridge); |
91 | } |
92 | |
93 | enum mtk_dpi_polarity { |
94 | MTK_DPI_POLARITY_RISING, |
95 | MTK_DPI_POLARITY_FALLING, |
96 | }; |
97 | |
98 | struct mtk_dpi_polarities { |
99 | enum mtk_dpi_polarity de_pol; |
100 | enum mtk_dpi_polarity ck_pol; |
101 | enum mtk_dpi_polarity hsync_pol; |
102 | enum mtk_dpi_polarity vsync_pol; |
103 | }; |
104 | |
105 | struct mtk_dpi_sync_param { |
106 | u32 sync_width; |
107 | u32 front_porch; |
108 | u32 back_porch; |
109 | bool shift_half_line; |
110 | }; |
111 | |
112 | struct mtk_dpi_yc_limit { |
113 | u16 y_top; |
114 | u16 y_bottom; |
115 | u16 c_top; |
116 | u16 c_bottom; |
117 | }; |
118 | |
119 | /** |
120 | * struct mtk_dpi_conf - Configuration of mediatek dpi. |
121 | * @cal_factor: Callback function to calculate factor value. |
122 | * @reg_h_fre_con: Register address of frequency control. |
123 | * @max_clock_khz: Max clock frequency supported for this SoCs in khz units. |
124 | * @edge_sel_en: Enable of edge selection. |
125 | * @output_fmts: Array of supported output formats. |
126 | * @num_output_fmts: Quantity of supported output formats. |
127 | * @is_ck_de_pol: Support CK/DE polarity. |
128 | * @swap_input_support: Support input swap function. |
129 | * @support_direct_pin: IP supports direct connection to dpi panels. |
130 | * @input_2pixel: Input pixel of dp_intf is 2 pixel per round, so enable this |
131 | * config to enable this feature. |
132 | * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH |
133 | * (no shift). |
134 | * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). |
135 | * @channel_swap_shift: Shift value of channel swap. |
136 | * @yuv422_en_bit: Enable bit of yuv422. |
137 | * @csc_enable_bit: Enable bit of CSC. |
138 | * @pixels_per_iter: Quantity of transferred pixels per iteration. |
139 | * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS. |
140 | */ |
141 | struct mtk_dpi_conf { |
142 | unsigned int (*cal_factor)(int clock); |
143 | u32 reg_h_fre_con; |
144 | u32 max_clock_khz; |
145 | bool edge_sel_en; |
146 | const u32 *output_fmts; |
147 | u32 num_output_fmts; |
148 | bool is_ck_de_pol; |
149 | bool swap_input_support; |
150 | bool support_direct_pin; |
151 | bool input_2pixel; |
152 | u32 dimension_mask; |
153 | u32 hvsize_mask; |
154 | u32 channel_swap_shift; |
155 | u32 yuv422_en_bit; |
156 | u32 csc_enable_bit; |
157 | u32 pixels_per_iter; |
158 | bool edge_cfg_in_mmsys; |
159 | }; |
160 | |
161 | static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) |
162 | { |
163 | u32 tmp = readl(addr: dpi->regs + offset) & ~mask; |
164 | |
165 | tmp |= (val & mask); |
166 | writel(val: tmp, addr: dpi->regs + offset); |
167 | } |
168 | |
169 | static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset) |
170 | { |
171 | mtk_dpi_mask(dpi, DPI_RET, val: reset ? RST : 0, RST); |
172 | } |
173 | |
174 | static void mtk_dpi_enable(struct mtk_dpi *dpi) |
175 | { |
176 | mtk_dpi_mask(dpi, DPI_EN, EN, EN); |
177 | } |
178 | |
179 | static void mtk_dpi_disable(struct mtk_dpi *dpi) |
180 | { |
181 | mtk_dpi_mask(dpi, DPI_EN, val: 0, EN); |
182 | } |
183 | |
184 | static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, |
185 | struct mtk_dpi_sync_param *sync) |
186 | { |
187 | mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, val: sync->sync_width << HPW, |
188 | mask: dpi->conf->dimension_mask << HPW); |
189 | mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, val: sync->back_porch << HBP, |
190 | mask: dpi->conf->dimension_mask << HBP); |
191 | mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, val: sync->front_porch << HFP, |
192 | mask: dpi->conf->dimension_mask << HFP); |
193 | } |
194 | |
195 | static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, |
196 | struct mtk_dpi_sync_param *sync, |
197 | u32 width_addr, u32 porch_addr) |
198 | { |
199 | mtk_dpi_mask(dpi, offset: width_addr, |
200 | val: sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, |
201 | VSYNC_HALF_LINE_MASK); |
202 | mtk_dpi_mask(dpi, offset: width_addr, |
203 | val: sync->sync_width << VSYNC_WIDTH_SHIFT, |
204 | mask: dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT); |
205 | mtk_dpi_mask(dpi, offset: porch_addr, |
206 | val: sync->back_porch << VSYNC_BACK_PORCH_SHIFT, |
207 | mask: dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT); |
208 | mtk_dpi_mask(dpi, offset: porch_addr, |
209 | val: sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, |
210 | mask: dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT); |
211 | } |
212 | |
213 | static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, |
214 | struct mtk_dpi_sync_param *sync) |
215 | { |
216 | mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH); |
217 | } |
218 | |
219 | static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi, |
220 | struct mtk_dpi_sync_param *sync) |
221 | { |
222 | mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN, |
223 | DPI_TGEN_VPORCH_LEVEN); |
224 | } |
225 | |
226 | static void mtk_dpi_config_vsync_rodd(struct mtk_dpi *dpi, |
227 | struct mtk_dpi_sync_param *sync) |
228 | { |
229 | mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_RODD, |
230 | DPI_TGEN_VPORCH_RODD); |
231 | } |
232 | |
233 | static void mtk_dpi_config_vsync_reven(struct mtk_dpi *dpi, |
234 | struct mtk_dpi_sync_param *sync) |
235 | { |
236 | mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_REVEN, |
237 | DPI_TGEN_VPORCH_REVEN); |
238 | } |
239 | |
240 | static void mtk_dpi_config_pol(struct mtk_dpi *dpi, |
241 | struct mtk_dpi_polarities *dpi_pol) |
242 | { |
243 | unsigned int pol; |
244 | unsigned int mask; |
245 | |
246 | mask = HSYNC_POL | VSYNC_POL; |
247 | pol = (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) | |
248 | (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); |
249 | if (dpi->conf->is_ck_de_pol) { |
250 | mask |= CK_POL | DE_POL; |
251 | pol |= (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? |
252 | 0 : CK_POL) | |
253 | (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? |
254 | 0 : DE_POL); |
255 | } |
256 | |
257 | mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val: pol, mask); |
258 | } |
259 | |
260 | static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) |
261 | { |
262 | mtk_dpi_mask(dpi, DPI_CON, val: en_3d ? TDFP_EN : 0, TDFP_EN); |
263 | } |
264 | |
265 | static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter) |
266 | { |
267 | mtk_dpi_mask(dpi, DPI_CON, val: inter ? INTL_EN : 0, INTL_EN); |
268 | } |
269 | |
270 | static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) |
271 | { |
272 | mtk_dpi_mask(dpi, DPI_SIZE, val: width << HSIZE, |
273 | mask: dpi->conf->hvsize_mask << HSIZE); |
274 | mtk_dpi_mask(dpi, DPI_SIZE, val: height << VSIZE, |
275 | mask: dpi->conf->hvsize_mask << VSIZE); |
276 | } |
277 | |
278 | static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) |
279 | { |
280 | struct mtk_dpi_yc_limit limit; |
281 | |
282 | if (drm_default_rgb_quant_range(mode: &dpi->mode) == |
283 | HDMI_QUANTIZATION_RANGE_LIMITED) { |
284 | limit.y_bottom = 0x10; |
285 | limit.y_top = 0xfe0; |
286 | limit.c_bottom = 0x10; |
287 | limit.c_top = 0xfe0; |
288 | } else { |
289 | limit.y_bottom = 0; |
290 | limit.y_top = 0xfff; |
291 | limit.c_bottom = 0; |
292 | limit.c_top = 0xfff; |
293 | } |
294 | |
295 | mtk_dpi_mask(dpi, DPI_Y_LIMIT, val: limit.y_bottom << Y_LIMINT_BOT, |
296 | Y_LIMINT_BOT_MASK); |
297 | mtk_dpi_mask(dpi, DPI_Y_LIMIT, val: limit.y_top << Y_LIMINT_TOP, |
298 | Y_LIMINT_TOP_MASK); |
299 | mtk_dpi_mask(dpi, DPI_C_LIMIT, val: limit.c_bottom << C_LIMIT_BOT, |
300 | C_LIMIT_BOT_MASK); |
301 | mtk_dpi_mask(dpi, DPI_C_LIMIT, val: limit.c_top << C_LIMIT_TOP, |
302 | C_LIMIT_TOP_MASK); |
303 | } |
304 | |
305 | static void mtk_dpi_config_bit_num(struct mtk_dpi *dpi, |
306 | enum mtk_dpi_out_bit_num num) |
307 | { |
308 | u32 val; |
309 | |
310 | switch (num) { |
311 | case MTK_DPI_OUT_BIT_NUM_8BITS: |
312 | val = OUT_BIT_8; |
313 | break; |
314 | case MTK_DPI_OUT_BIT_NUM_10BITS: |
315 | val = OUT_BIT_10; |
316 | break; |
317 | case MTK_DPI_OUT_BIT_NUM_12BITS: |
318 | val = OUT_BIT_12; |
319 | break; |
320 | case MTK_DPI_OUT_BIT_NUM_16BITS: |
321 | val = OUT_BIT_16; |
322 | break; |
323 | default: |
324 | val = OUT_BIT_8; |
325 | break; |
326 | } |
327 | mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val: val << OUT_BIT, |
328 | OUT_BIT_MASK); |
329 | } |
330 | |
331 | static void mtk_dpi_config_yc_map(struct mtk_dpi *dpi, |
332 | enum mtk_dpi_out_yc_map map) |
333 | { |
334 | u32 val; |
335 | |
336 | switch (map) { |
337 | case MTK_DPI_OUT_YC_MAP_RGB: |
338 | val = YC_MAP_RGB; |
339 | break; |
340 | case MTK_DPI_OUT_YC_MAP_CYCY: |
341 | val = YC_MAP_CYCY; |
342 | break; |
343 | case MTK_DPI_OUT_YC_MAP_YCYC: |
344 | val = YC_MAP_YCYC; |
345 | break; |
346 | case MTK_DPI_OUT_YC_MAP_CY: |
347 | val = YC_MAP_CY; |
348 | break; |
349 | case MTK_DPI_OUT_YC_MAP_YC: |
350 | val = YC_MAP_YC; |
351 | break; |
352 | default: |
353 | val = YC_MAP_RGB; |
354 | break; |
355 | } |
356 | |
357 | mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val: val << YC_MAP, YC_MAP_MASK); |
358 | } |
359 | |
360 | static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi, |
361 | enum mtk_dpi_out_channel_swap swap) |
362 | { |
363 | u32 val; |
364 | |
365 | switch (swap) { |
366 | case MTK_DPI_OUT_CHANNEL_SWAP_RGB: |
367 | val = SWAP_RGB; |
368 | break; |
369 | case MTK_DPI_OUT_CHANNEL_SWAP_GBR: |
370 | val = SWAP_GBR; |
371 | break; |
372 | case MTK_DPI_OUT_CHANNEL_SWAP_BRG: |
373 | val = SWAP_BRG; |
374 | break; |
375 | case MTK_DPI_OUT_CHANNEL_SWAP_RBG: |
376 | val = SWAP_RBG; |
377 | break; |
378 | case MTK_DPI_OUT_CHANNEL_SWAP_GRB: |
379 | val = SWAP_GRB; |
380 | break; |
381 | case MTK_DPI_OUT_CHANNEL_SWAP_BGR: |
382 | val = SWAP_BGR; |
383 | break; |
384 | default: |
385 | val = SWAP_RGB; |
386 | break; |
387 | } |
388 | |
389 | mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, |
390 | val: val << dpi->conf->channel_swap_shift, |
391 | CH_SWAP_MASK << dpi->conf->channel_swap_shift); |
392 | } |
393 | |
394 | static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) |
395 | { |
396 | mtk_dpi_mask(dpi, DPI_CON, val: enable ? dpi->conf->yuv422_en_bit : 0, |
397 | mask: dpi->conf->yuv422_en_bit); |
398 | } |
399 | |
400 | static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) |
401 | { |
402 | mtk_dpi_mask(dpi, DPI_CON, val: enable ? dpi->conf->csc_enable_bit : 0, |
403 | mask: dpi->conf->csc_enable_bit); |
404 | } |
405 | |
406 | static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) |
407 | { |
408 | mtk_dpi_mask(dpi, DPI_CON, val: enable ? IN_RB_SWAP : 0, IN_RB_SWAP); |
409 | } |
410 | |
411 | static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi) |
412 | { |
413 | mtk_dpi_mask(dpi, offset: dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N); |
414 | } |
415 | |
416 | static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) |
417 | { |
418 | if (dpi->conf->edge_sel_en) |
419 | mtk_dpi_mask(dpi, offset: dpi->conf->reg_h_fre_con, val: 0, EDGE_SEL_EN); |
420 | } |
421 | |
422 | static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, |
423 | enum mtk_dpi_out_color_format format) |
424 | { |
425 | mtk_dpi_config_channel_swap(dpi, swap: MTK_DPI_OUT_CHANNEL_SWAP_RGB); |
426 | |
427 | if (format == MTK_DPI_COLOR_FORMAT_YCBCR_422) { |
428 | mtk_dpi_config_yuv422_enable(dpi, enable: true); |
429 | mtk_dpi_config_csc_enable(dpi, enable: true); |
430 | |
431 | /* |
432 | * If height is smaller than 720, we need to use RGB_TO_BT601 |
433 | * to transfer to yuv422. Otherwise, we use RGB_TO_JPEG. |
434 | */ |
435 | mtk_dpi_mask(dpi, DPI_MATRIX_SET, val: dpi->mode.hdisplay <= 720 ? |
436 | MATRIX_SEL_RGB_TO_BT601 : MATRIX_SEL_RGB_TO_JPEG, |
437 | INT_MATRIX_SEL_MASK); |
438 | } else { |
439 | mtk_dpi_config_yuv422_enable(dpi, enable: false); |
440 | mtk_dpi_config_csc_enable(dpi, enable: false); |
441 | if (dpi->conf->swap_input_support) |
442 | mtk_dpi_config_swap_input(dpi, enable: false); |
443 | } |
444 | } |
445 | |
446 | static void mtk_dpi_dual_edge(struct mtk_dpi *dpi) |
447 | { |
448 | if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || |
449 | (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) { |
450 | mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, |
451 | DDR_EN | DDR_4PHASE); |
452 | mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, |
453 | val: dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE ? |
454 | EDGE_SEL : 0, EDGE_SEL); |
455 | if (dpi->conf->edge_cfg_in_mmsys) |
456 | mtk_mmsys_ddp_dpi_fmt_config(dev: dpi->mmsys_dev, val: MTK_DPI_RGB888_DDR_CON); |
457 | } else { |
458 | mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, mask: 0); |
459 | if (dpi->conf->edge_cfg_in_mmsys) |
460 | mtk_mmsys_ddp_dpi_fmt_config(dev: dpi->mmsys_dev, val: MTK_DPI_RGB888_SDR_CON); |
461 | } |
462 | } |
463 | |
464 | static void mtk_dpi_power_off(struct mtk_dpi *dpi) |
465 | { |
466 | if (WARN_ON(dpi->refcount == 0)) |
467 | return; |
468 | |
469 | if (--dpi->refcount != 0) |
470 | return; |
471 | |
472 | mtk_dpi_disable(dpi); |
473 | clk_disable_unprepare(clk: dpi->pixel_clk); |
474 | clk_disable_unprepare(clk: dpi->engine_clk); |
475 | } |
476 | |
477 | static int mtk_dpi_power_on(struct mtk_dpi *dpi) |
478 | { |
479 | int ret; |
480 | |
481 | if (++dpi->refcount != 1) |
482 | return 0; |
483 | |
484 | ret = clk_prepare_enable(clk: dpi->engine_clk); |
485 | if (ret) { |
486 | dev_err(dpi->dev, "Failed to enable engine clock: %d\n" , ret); |
487 | goto err_refcount; |
488 | } |
489 | |
490 | ret = clk_prepare_enable(clk: dpi->pixel_clk); |
491 | if (ret) { |
492 | dev_err(dpi->dev, "Failed to enable pixel clock: %d\n" , ret); |
493 | goto err_pixel; |
494 | } |
495 | |
496 | return 0; |
497 | |
498 | err_pixel: |
499 | clk_disable_unprepare(clk: dpi->engine_clk); |
500 | err_refcount: |
501 | dpi->refcount--; |
502 | return ret; |
503 | } |
504 | |
505 | static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, |
506 | struct drm_display_mode *mode) |
507 | { |
508 | struct mtk_dpi_polarities dpi_pol; |
509 | struct mtk_dpi_sync_param hsync; |
510 | struct mtk_dpi_sync_param vsync_lodd = { 0 }; |
511 | struct mtk_dpi_sync_param vsync_leven = { 0 }; |
512 | struct mtk_dpi_sync_param vsync_rodd = { 0 }; |
513 | struct mtk_dpi_sync_param vsync_reven = { 0 }; |
514 | struct videomode vm = { 0 }; |
515 | unsigned long pll_rate; |
516 | unsigned int factor; |
517 | |
518 | /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ |
519 | factor = dpi->conf->cal_factor(mode->clock); |
520 | drm_display_mode_to_videomode(dmode: mode, vm: &vm); |
521 | pll_rate = vm.pixelclock * factor; |
522 | |
523 | dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n" , |
524 | pll_rate, vm.pixelclock); |
525 | |
526 | clk_set_rate(clk: dpi->tvd_clk, rate: pll_rate); |
527 | pll_rate = clk_get_rate(clk: dpi->tvd_clk); |
528 | |
529 | /* |
530 | * Depending on the IP version, we may output a different amount of |
531 | * pixels for each iteration: divide the clock by this number and |
532 | * adjust the display porches accordingly. |
533 | */ |
534 | vm.pixelclock = pll_rate / factor; |
535 | vm.pixelclock /= dpi->conf->pixels_per_iter; |
536 | |
537 | if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || |
538 | (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) |
539 | clk_set_rate(clk: dpi->pixel_clk, rate: vm.pixelclock * 2); |
540 | else |
541 | clk_set_rate(clk: dpi->pixel_clk, rate: vm.pixelclock); |
542 | |
543 | |
544 | vm.pixelclock = clk_get_rate(clk: dpi->pixel_clk); |
545 | |
546 | dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n" , |
547 | pll_rate, vm.pixelclock); |
548 | |
549 | dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; |
550 | dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; |
551 | dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? |
552 | MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; |
553 | dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? |
554 | MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; |
555 | |
556 | /* |
557 | * Depending on the IP version, we may output a different amount of |
558 | * pixels for each iteration: divide the clock by this number and |
559 | * adjust the display porches accordingly. |
560 | */ |
561 | hsync.sync_width = vm.hsync_len / dpi->conf->pixels_per_iter; |
562 | hsync.back_porch = vm.hback_porch / dpi->conf->pixels_per_iter; |
563 | hsync.front_porch = vm.hfront_porch / dpi->conf->pixels_per_iter; |
564 | |
565 | hsync.shift_half_line = false; |
566 | vsync_lodd.sync_width = vm.vsync_len; |
567 | vsync_lodd.back_porch = vm.vback_porch; |
568 | vsync_lodd.front_porch = vm.vfront_porch; |
569 | vsync_lodd.shift_half_line = false; |
570 | |
571 | if (vm.flags & DISPLAY_FLAGS_INTERLACED && |
572 | mode->flags & DRM_MODE_FLAG_3D_MASK) { |
573 | vsync_leven = vsync_lodd; |
574 | vsync_rodd = vsync_lodd; |
575 | vsync_reven = vsync_lodd; |
576 | vsync_leven.shift_half_line = true; |
577 | vsync_reven.shift_half_line = true; |
578 | } else if (vm.flags & DISPLAY_FLAGS_INTERLACED && |
579 | !(mode->flags & DRM_MODE_FLAG_3D_MASK)) { |
580 | vsync_leven = vsync_lodd; |
581 | vsync_leven.shift_half_line = true; |
582 | } else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) && |
583 | mode->flags & DRM_MODE_FLAG_3D_MASK) { |
584 | vsync_rodd = vsync_lodd; |
585 | } |
586 | mtk_dpi_sw_reset(dpi, reset: true); |
587 | mtk_dpi_config_pol(dpi, dpi_pol: &dpi_pol); |
588 | |
589 | mtk_dpi_config_hsync(dpi, sync: &hsync); |
590 | mtk_dpi_config_vsync_lodd(dpi, sync: &vsync_lodd); |
591 | mtk_dpi_config_vsync_rodd(dpi, sync: &vsync_rodd); |
592 | mtk_dpi_config_vsync_leven(dpi, sync: &vsync_leven); |
593 | mtk_dpi_config_vsync_reven(dpi, sync: &vsync_reven); |
594 | |
595 | mtk_dpi_config_3d(dpi, en_3d: !!(mode->flags & DRM_MODE_FLAG_3D_MASK)); |
596 | mtk_dpi_config_interface(dpi, inter: !!(vm.flags & |
597 | DISPLAY_FLAGS_INTERLACED)); |
598 | if (vm.flags & DISPLAY_FLAGS_INTERLACED) |
599 | mtk_dpi_config_fb_size(dpi, width: vm.hactive, height: vm.vactive >> 1); |
600 | else |
601 | mtk_dpi_config_fb_size(dpi, width: vm.hactive, height: vm.vactive); |
602 | |
603 | mtk_dpi_config_channel_limit(dpi); |
604 | mtk_dpi_config_bit_num(dpi, num: dpi->bit_num); |
605 | mtk_dpi_config_channel_swap(dpi, swap: dpi->channel_swap); |
606 | mtk_dpi_config_color_format(dpi, format: dpi->color_format); |
607 | if (dpi->conf->support_direct_pin) { |
608 | mtk_dpi_config_yc_map(dpi, map: dpi->yc_map); |
609 | mtk_dpi_config_2n_h_fre(dpi); |
610 | mtk_dpi_dual_edge(dpi); |
611 | mtk_dpi_config_disable_edge(dpi); |
612 | } |
613 | if (dpi->conf->input_2pixel) { |
614 | mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, |
615 | DPINTF_INPUT_2P_EN); |
616 | } |
617 | mtk_dpi_sw_reset(dpi, reset: false); |
618 | |
619 | return 0; |
620 | } |
621 | |
622 | static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, |
623 | struct drm_bridge_state *bridge_state, |
624 | struct drm_crtc_state *crtc_state, |
625 | struct drm_connector_state *conn_state, |
626 | unsigned int *num_output_fmts) |
627 | { |
628 | struct mtk_dpi *dpi = bridge_to_dpi(b: bridge); |
629 | u32 *output_fmts; |
630 | |
631 | *num_output_fmts = 0; |
632 | |
633 | if (!dpi->conf->output_fmts) { |
634 | dev_err(dpi->dev, "output_fmts should not be null\n" ); |
635 | return NULL; |
636 | } |
637 | |
638 | output_fmts = kcalloc(n: dpi->conf->num_output_fmts, size: sizeof(*output_fmts), |
639 | GFP_KERNEL); |
640 | if (!output_fmts) |
641 | return NULL; |
642 | |
643 | *num_output_fmts = dpi->conf->num_output_fmts; |
644 | |
645 | memcpy(output_fmts, dpi->conf->output_fmts, |
646 | sizeof(*output_fmts) * dpi->conf->num_output_fmts); |
647 | |
648 | return output_fmts; |
649 | } |
650 | |
651 | static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, |
652 | struct drm_bridge_state *bridge_state, |
653 | struct drm_crtc_state *crtc_state, |
654 | struct drm_connector_state *conn_state, |
655 | u32 output_fmt, |
656 | unsigned int *num_input_fmts) |
657 | { |
658 | u32 *input_fmts; |
659 | |
660 | *num_input_fmts = 0; |
661 | |
662 | input_fmts = kcalloc(n: 1, size: sizeof(*input_fmts), |
663 | GFP_KERNEL); |
664 | if (!input_fmts) |
665 | return NULL; |
666 | |
667 | *num_input_fmts = 1; |
668 | input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; |
669 | |
670 | return input_fmts; |
671 | } |
672 | |
673 | static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, |
674 | struct drm_bridge_state *bridge_state, |
675 | struct drm_crtc_state *crtc_state, |
676 | struct drm_connector_state *conn_state) |
677 | { |
678 | struct mtk_dpi *dpi = bridge_to_dpi(b: bridge); |
679 | unsigned int out_bus_format; |
680 | |
681 | out_bus_format = bridge_state->output_bus_cfg.format; |
682 | |
683 | if (out_bus_format == MEDIA_BUS_FMT_FIXED) |
684 | if (dpi->conf->num_output_fmts) |
685 | out_bus_format = dpi->conf->output_fmts[0]; |
686 | |
687 | dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n" , |
688 | bridge_state->input_bus_cfg.format, |
689 | bridge_state->output_bus_cfg.format); |
690 | |
691 | dpi->output_fmt = out_bus_format; |
692 | dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; |
693 | dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; |
694 | dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; |
695 | if (out_bus_format == MEDIA_BUS_FMT_YUYV8_1X16) |
696 | dpi->color_format = MTK_DPI_COLOR_FORMAT_YCBCR_422; |
697 | else |
698 | dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; |
699 | |
700 | return 0; |
701 | } |
702 | |
703 | static int mtk_dpi_bridge_attach(struct drm_bridge *bridge, |
704 | enum drm_bridge_attach_flags flags) |
705 | { |
706 | struct mtk_dpi *dpi = bridge_to_dpi(b: bridge); |
707 | |
708 | return drm_bridge_attach(encoder: bridge->encoder, bridge: dpi->next_bridge, |
709 | previous: &dpi->bridge, flags); |
710 | } |
711 | |
712 | static void mtk_dpi_bridge_mode_set(struct drm_bridge *bridge, |
713 | const struct drm_display_mode *mode, |
714 | const struct drm_display_mode *adjusted_mode) |
715 | { |
716 | struct mtk_dpi *dpi = bridge_to_dpi(b: bridge); |
717 | |
718 | drm_mode_copy(dst: &dpi->mode, src: adjusted_mode); |
719 | } |
720 | |
721 | static void mtk_dpi_bridge_disable(struct drm_bridge *bridge) |
722 | { |
723 | struct mtk_dpi *dpi = bridge_to_dpi(b: bridge); |
724 | |
725 | mtk_dpi_power_off(dpi); |
726 | |
727 | if (dpi->pinctrl && dpi->pins_gpio) |
728 | pinctrl_select_state(p: dpi->pinctrl, s: dpi->pins_gpio); |
729 | } |
730 | |
731 | static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) |
732 | { |
733 | struct mtk_dpi *dpi = bridge_to_dpi(b: bridge); |
734 | |
735 | if (dpi->pinctrl && dpi->pins_dpi) |
736 | pinctrl_select_state(p: dpi->pinctrl, s: dpi->pins_dpi); |
737 | |
738 | mtk_dpi_power_on(dpi); |
739 | mtk_dpi_set_display_mode(dpi, mode: &dpi->mode); |
740 | mtk_dpi_enable(dpi); |
741 | } |
742 | |
743 | static enum drm_mode_status |
744 | mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, |
745 | const struct drm_display_info *info, |
746 | const struct drm_display_mode *mode) |
747 | { |
748 | struct mtk_dpi *dpi = bridge_to_dpi(b: bridge); |
749 | |
750 | if (mode->clock > dpi->conf->max_clock_khz) |
751 | return MODE_CLOCK_HIGH; |
752 | |
753 | return MODE_OK; |
754 | } |
755 | |
756 | static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { |
757 | .attach = mtk_dpi_bridge_attach, |
758 | .mode_set = mtk_dpi_bridge_mode_set, |
759 | .mode_valid = mtk_dpi_bridge_mode_valid, |
760 | .disable = mtk_dpi_bridge_disable, |
761 | .enable = mtk_dpi_bridge_enable, |
762 | .atomic_check = mtk_dpi_bridge_atomic_check, |
763 | .atomic_get_output_bus_fmts = mtk_dpi_bridge_atomic_get_output_bus_fmts, |
764 | .atomic_get_input_bus_fmts = mtk_dpi_bridge_atomic_get_input_bus_fmts, |
765 | .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, |
766 | .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, |
767 | .atomic_reset = drm_atomic_helper_bridge_reset, |
768 | }; |
769 | |
770 | void mtk_dpi_start(struct device *dev) |
771 | { |
772 | struct mtk_dpi *dpi = dev_get_drvdata(dev); |
773 | |
774 | mtk_dpi_power_on(dpi); |
775 | } |
776 | |
777 | void mtk_dpi_stop(struct device *dev) |
778 | { |
779 | struct mtk_dpi *dpi = dev_get_drvdata(dev); |
780 | |
781 | mtk_dpi_power_off(dpi); |
782 | } |
783 | |
784 | unsigned int mtk_dpi_encoder_index(struct device *dev) |
785 | { |
786 | struct mtk_dpi *dpi = dev_get_drvdata(dev); |
787 | unsigned int encoder_index = drm_encoder_index(encoder: &dpi->encoder); |
788 | |
789 | dev_dbg(dev, "encoder index:%d\n" , encoder_index); |
790 | return encoder_index; |
791 | } |
792 | |
793 | static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) |
794 | { |
795 | struct mtk_dpi *dpi = dev_get_drvdata(dev); |
796 | struct drm_device *drm_dev = data; |
797 | struct mtk_drm_private *priv = drm_dev->dev_private; |
798 | int ret; |
799 | |
800 | dpi->mmsys_dev = priv->mmsys_dev; |
801 | ret = drm_simple_encoder_init(dev: drm_dev, encoder: &dpi->encoder, |
802 | DRM_MODE_ENCODER_TMDS); |
803 | if (ret) { |
804 | dev_err(dev, "Failed to initialize decoder: %d\n" , ret); |
805 | return ret; |
806 | } |
807 | |
808 | dpi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm: drm_dev, dev: dpi->dev); |
809 | |
810 | ret = drm_bridge_attach(encoder: &dpi->encoder, bridge: &dpi->bridge, NULL, |
811 | flags: DRM_BRIDGE_ATTACH_NO_CONNECTOR); |
812 | if (ret) |
813 | goto err_cleanup; |
814 | |
815 | dpi->connector = drm_bridge_connector_init(drm: drm_dev, encoder: &dpi->encoder); |
816 | if (IS_ERR(ptr: dpi->connector)) { |
817 | dev_err(dev, "Unable to create bridge connector\n" ); |
818 | ret = PTR_ERR(ptr: dpi->connector); |
819 | goto err_cleanup; |
820 | } |
821 | drm_connector_attach_encoder(connector: dpi->connector, encoder: &dpi->encoder); |
822 | |
823 | return 0; |
824 | |
825 | err_cleanup: |
826 | drm_encoder_cleanup(encoder: &dpi->encoder); |
827 | return ret; |
828 | } |
829 | |
830 | static void mtk_dpi_unbind(struct device *dev, struct device *master, |
831 | void *data) |
832 | { |
833 | struct mtk_dpi *dpi = dev_get_drvdata(dev); |
834 | |
835 | drm_encoder_cleanup(encoder: &dpi->encoder); |
836 | } |
837 | |
838 | static const struct component_ops mtk_dpi_component_ops = { |
839 | .bind = mtk_dpi_bind, |
840 | .unbind = mtk_dpi_unbind, |
841 | }; |
842 | |
843 | static unsigned int mt8173_calculate_factor(int clock) |
844 | { |
845 | if (clock <= 27000) |
846 | return 3 << 4; |
847 | else if (clock <= 84000) |
848 | return 3 << 3; |
849 | else if (clock <= 167000) |
850 | return 3 << 2; |
851 | else |
852 | return 3 << 1; |
853 | } |
854 | |
855 | static unsigned int mt2701_calculate_factor(int clock) |
856 | { |
857 | if (clock <= 64000) |
858 | return 4; |
859 | else if (clock <= 128000) |
860 | return 2; |
861 | else |
862 | return 1; |
863 | } |
864 | |
865 | static unsigned int mt8183_calculate_factor(int clock) |
866 | { |
867 | if (clock <= 27000) |
868 | return 8; |
869 | else if (clock <= 167000) |
870 | return 4; |
871 | else |
872 | return 2; |
873 | } |
874 | |
875 | static unsigned int mt8195_dpintf_calculate_factor(int clock) |
876 | { |
877 | if (clock < 70000) |
878 | return 4; |
879 | else if (clock < 200000) |
880 | return 2; |
881 | else |
882 | return 1; |
883 | } |
884 | |
885 | static const u32 mt8173_output_fmts[] = { |
886 | MEDIA_BUS_FMT_RGB888_1X24, |
887 | }; |
888 | |
889 | static const u32 mt8183_output_fmts[] = { |
890 | MEDIA_BUS_FMT_RGB888_2X12_LE, |
891 | MEDIA_BUS_FMT_RGB888_2X12_BE, |
892 | }; |
893 | |
894 | static const u32 mt8195_output_fmts[] = { |
895 | MEDIA_BUS_FMT_RGB888_1X24, |
896 | MEDIA_BUS_FMT_YUYV8_1X16, |
897 | }; |
898 | |
899 | static const struct mtk_dpi_conf mt8173_conf = { |
900 | .cal_factor = mt8173_calculate_factor, |
901 | .reg_h_fre_con = 0xe0, |
902 | .max_clock_khz = 300000, |
903 | .output_fmts = mt8173_output_fmts, |
904 | .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), |
905 | .pixels_per_iter = 1, |
906 | .is_ck_de_pol = true, |
907 | .swap_input_support = true, |
908 | .support_direct_pin = true, |
909 | .dimension_mask = HPW_MASK, |
910 | .hvsize_mask = HSIZE_MASK, |
911 | .channel_swap_shift = CH_SWAP, |
912 | .yuv422_en_bit = YUV422_EN, |
913 | .csc_enable_bit = CSC_ENABLE, |
914 | }; |
915 | |
916 | static const struct mtk_dpi_conf mt2701_conf = { |
917 | .cal_factor = mt2701_calculate_factor, |
918 | .reg_h_fre_con = 0xb0, |
919 | .edge_sel_en = true, |
920 | .max_clock_khz = 150000, |
921 | .output_fmts = mt8173_output_fmts, |
922 | .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), |
923 | .pixels_per_iter = 1, |
924 | .is_ck_de_pol = true, |
925 | .swap_input_support = true, |
926 | .support_direct_pin = true, |
927 | .dimension_mask = HPW_MASK, |
928 | .hvsize_mask = HSIZE_MASK, |
929 | .channel_swap_shift = CH_SWAP, |
930 | .yuv422_en_bit = YUV422_EN, |
931 | .csc_enable_bit = CSC_ENABLE, |
932 | }; |
933 | |
934 | static const struct mtk_dpi_conf mt8183_conf = { |
935 | .cal_factor = mt8183_calculate_factor, |
936 | .reg_h_fre_con = 0xe0, |
937 | .max_clock_khz = 100000, |
938 | .output_fmts = mt8183_output_fmts, |
939 | .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), |
940 | .pixels_per_iter = 1, |
941 | .is_ck_de_pol = true, |
942 | .swap_input_support = true, |
943 | .support_direct_pin = true, |
944 | .dimension_mask = HPW_MASK, |
945 | .hvsize_mask = HSIZE_MASK, |
946 | .channel_swap_shift = CH_SWAP, |
947 | .yuv422_en_bit = YUV422_EN, |
948 | .csc_enable_bit = CSC_ENABLE, |
949 | }; |
950 | |
951 | static const struct mtk_dpi_conf mt8186_conf = { |
952 | .cal_factor = mt8183_calculate_factor, |
953 | .reg_h_fre_con = 0xe0, |
954 | .max_clock_khz = 150000, |
955 | .output_fmts = mt8183_output_fmts, |
956 | .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), |
957 | .edge_cfg_in_mmsys = true, |
958 | .pixels_per_iter = 1, |
959 | .is_ck_de_pol = true, |
960 | .swap_input_support = true, |
961 | .support_direct_pin = true, |
962 | .dimension_mask = HPW_MASK, |
963 | .hvsize_mask = HSIZE_MASK, |
964 | .channel_swap_shift = CH_SWAP, |
965 | .yuv422_en_bit = YUV422_EN, |
966 | .csc_enable_bit = CSC_ENABLE, |
967 | }; |
968 | |
969 | static const struct mtk_dpi_conf mt8192_conf = { |
970 | .cal_factor = mt8183_calculate_factor, |
971 | .reg_h_fre_con = 0xe0, |
972 | .max_clock_khz = 150000, |
973 | .output_fmts = mt8183_output_fmts, |
974 | .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), |
975 | .pixels_per_iter = 1, |
976 | .is_ck_de_pol = true, |
977 | .swap_input_support = true, |
978 | .support_direct_pin = true, |
979 | .dimension_mask = HPW_MASK, |
980 | .hvsize_mask = HSIZE_MASK, |
981 | .channel_swap_shift = CH_SWAP, |
982 | .yuv422_en_bit = YUV422_EN, |
983 | .csc_enable_bit = CSC_ENABLE, |
984 | }; |
985 | |
986 | static const struct mtk_dpi_conf mt8195_dpintf_conf = { |
987 | .cal_factor = mt8195_dpintf_calculate_factor, |
988 | .max_clock_khz = 600000, |
989 | .output_fmts = mt8195_output_fmts, |
990 | .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts), |
991 | .pixels_per_iter = 4, |
992 | .input_2pixel = true, |
993 | .dimension_mask = DPINTF_HPW_MASK, |
994 | .hvsize_mask = DPINTF_HSIZE_MASK, |
995 | .channel_swap_shift = DPINTF_CH_SWAP, |
996 | .yuv422_en_bit = DPINTF_YUV422_EN, |
997 | .csc_enable_bit = DPINTF_CSC_ENABLE, |
998 | }; |
999 | |
1000 | static int mtk_dpi_probe(struct platform_device *pdev) |
1001 | { |
1002 | struct device *dev = &pdev->dev; |
1003 | struct mtk_dpi *dpi; |
1004 | int ret; |
1005 | |
1006 | dpi = devm_kzalloc(dev, size: sizeof(*dpi), GFP_KERNEL); |
1007 | if (!dpi) |
1008 | return -ENOMEM; |
1009 | |
1010 | dpi->dev = dev; |
1011 | dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev); |
1012 | dpi->output_fmt = MEDIA_BUS_FMT_RGB888_1X24; |
1013 | |
1014 | dpi->pinctrl = devm_pinctrl_get(dev: &pdev->dev); |
1015 | if (IS_ERR(ptr: dpi->pinctrl)) { |
1016 | dpi->pinctrl = NULL; |
1017 | dev_dbg(&pdev->dev, "Cannot find pinctrl!\n" ); |
1018 | } |
1019 | if (dpi->pinctrl) { |
1020 | dpi->pins_gpio = pinctrl_lookup_state(p: dpi->pinctrl, name: "sleep" ); |
1021 | if (IS_ERR(ptr: dpi->pins_gpio)) { |
1022 | dpi->pins_gpio = NULL; |
1023 | dev_dbg(&pdev->dev, "Cannot find pinctrl idle!\n" ); |
1024 | } |
1025 | if (dpi->pins_gpio) |
1026 | pinctrl_select_state(p: dpi->pinctrl, s: dpi->pins_gpio); |
1027 | |
1028 | dpi->pins_dpi = pinctrl_lookup_state(p: dpi->pinctrl, name: "default" ); |
1029 | if (IS_ERR(ptr: dpi->pins_dpi)) { |
1030 | dpi->pins_dpi = NULL; |
1031 | dev_dbg(&pdev->dev, "Cannot find pinctrl active!\n" ); |
1032 | } |
1033 | } |
1034 | dpi->regs = devm_platform_ioremap_resource(pdev, index: 0); |
1035 | if (IS_ERR(ptr: dpi->regs)) |
1036 | return dev_err_probe(dev, err: PTR_ERR(ptr: dpi->regs), |
1037 | fmt: "Failed to ioremap mem resource\n" ); |
1038 | |
1039 | dpi->engine_clk = devm_clk_get(dev, id: "engine" ); |
1040 | if (IS_ERR(ptr: dpi->engine_clk)) |
1041 | return dev_err_probe(dev, err: PTR_ERR(ptr: dpi->engine_clk), |
1042 | fmt: "Failed to get engine clock\n" ); |
1043 | |
1044 | dpi->pixel_clk = devm_clk_get(dev, id: "pixel" ); |
1045 | if (IS_ERR(ptr: dpi->pixel_clk)) |
1046 | return dev_err_probe(dev, err: PTR_ERR(ptr: dpi->pixel_clk), |
1047 | fmt: "Failed to get pixel clock\n" ); |
1048 | |
1049 | dpi->tvd_clk = devm_clk_get(dev, id: "pll" ); |
1050 | if (IS_ERR(ptr: dpi->tvd_clk)) |
1051 | return dev_err_probe(dev, err: PTR_ERR(ptr: dpi->tvd_clk), |
1052 | fmt: "Failed to get tvdpll clock\n" ); |
1053 | |
1054 | dpi->irq = platform_get_irq(pdev, 0); |
1055 | if (dpi->irq < 0) |
1056 | return dpi->irq; |
1057 | |
1058 | dpi->next_bridge = devm_drm_of_get_bridge(dev, node: dev->of_node, port: 0, endpoint: 0); |
1059 | if (IS_ERR(ptr: dpi->next_bridge)) |
1060 | return dev_err_probe(dev, err: PTR_ERR(ptr: dpi->next_bridge), |
1061 | fmt: "Failed to get bridge\n" ); |
1062 | |
1063 | dev_info(dev, "Found bridge node: %pOF\n" , dpi->next_bridge->of_node); |
1064 | |
1065 | platform_set_drvdata(pdev, data: dpi); |
1066 | |
1067 | dpi->bridge.funcs = &mtk_dpi_bridge_funcs; |
1068 | dpi->bridge.of_node = dev->of_node; |
1069 | dpi->bridge.type = DRM_MODE_CONNECTOR_DPI; |
1070 | |
1071 | ret = devm_drm_bridge_add(dev, bridge: &dpi->bridge); |
1072 | if (ret) |
1073 | return ret; |
1074 | |
1075 | ret = component_add(dev, &mtk_dpi_component_ops); |
1076 | if (ret) |
1077 | return dev_err_probe(dev, err: ret, fmt: "Failed to add component.\n" ); |
1078 | |
1079 | return 0; |
1080 | } |
1081 | |
1082 | static void mtk_dpi_remove(struct platform_device *pdev) |
1083 | { |
1084 | component_del(&pdev->dev, &mtk_dpi_component_ops); |
1085 | } |
1086 | |
1087 | static const struct of_device_id mtk_dpi_of_ids[] = { |
1088 | { .compatible = "mediatek,mt2701-dpi" , .data = &mt2701_conf }, |
1089 | { .compatible = "mediatek,mt8173-dpi" , .data = &mt8173_conf }, |
1090 | { .compatible = "mediatek,mt8183-dpi" , .data = &mt8183_conf }, |
1091 | { .compatible = "mediatek,mt8186-dpi" , .data = &mt8186_conf }, |
1092 | { .compatible = "mediatek,mt8188-dp-intf" , .data = &mt8195_dpintf_conf }, |
1093 | { .compatible = "mediatek,mt8192-dpi" , .data = &mt8192_conf }, |
1094 | { .compatible = "mediatek,mt8195-dp-intf" , .data = &mt8195_dpintf_conf }, |
1095 | { /* sentinel */ }, |
1096 | }; |
1097 | MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); |
1098 | |
1099 | struct platform_driver mtk_dpi_driver = { |
1100 | .probe = mtk_dpi_probe, |
1101 | .remove_new = mtk_dpi_remove, |
1102 | .driver = { |
1103 | .name = "mediatek-dpi" , |
1104 | .of_match_table = mtk_dpi_of_ids, |
1105 | }, |
1106 | }; |
1107 | |