1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | |
3 | #include <linux/delay.h> |
4 | #include <linux/pci.h> |
5 | |
6 | #include <drm/drm_atomic.h> |
7 | #include <drm/drm_atomic_helper.h> |
8 | #include <drm/drm_drv.h> |
9 | #include <drm/drm_gem_atomic_helper.h> |
10 | #include <drm/drm_probe_helper.h> |
11 | |
12 | #include "mgag200_drv.h" |
13 | |
14 | static int mgag200_g200se_init_pci_options(struct pci_dev *pdev) |
15 | { |
16 | struct device *dev = &pdev->dev; |
17 | bool has_sgram; |
18 | u32 option; |
19 | int err; |
20 | |
21 | err = pci_read_config_dword(dev: pdev, PCI_MGA_OPTION, val: &option); |
22 | if (err != PCIBIOS_SUCCESSFUL) { |
23 | dev_err(dev, "pci_read_config_dword(PCI_MGA_OPTION) failed: %d\n" , err); |
24 | return pcibios_err_to_errno(err); |
25 | } |
26 | |
27 | has_sgram = !!(option & PCI_MGA_OPTION_HARDPWMSK); |
28 | |
29 | option = 0x40049120; |
30 | if (has_sgram) |
31 | option |= PCI_MGA_OPTION_HARDPWMSK; |
32 | |
33 | return mgag200_init_pci_options(pdev, option, option2: 0x00008000); |
34 | } |
35 | |
36 | static void mgag200_g200se_init_registers(struct mgag200_g200se_device *g200se) |
37 | { |
38 | static const u8 dacvalue[] = { |
39 | MGAG200_DAC_DEFAULT(0x03, |
40 | MGA1064_PIX_CLK_CTL_SEL_PLL, |
41 | MGA1064_MISC_CTL_DAC_EN | |
42 | MGA1064_MISC_CTL_VGA8 | |
43 | MGA1064_MISC_CTL_DAC_RAM_CS, |
44 | 0x00, 0x00, 0x00) |
45 | }; |
46 | |
47 | struct mga_device *mdev = &g200se->base; |
48 | size_t i; |
49 | |
50 | for (i = 0; i < ARRAY_SIZE(dacvalue); i++) { |
51 | if ((i <= 0x17) || |
52 | (i == 0x1b) || |
53 | (i == 0x1c) || |
54 | ((i >= 0x1f) && (i <= 0x29)) || |
55 | ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)) || |
56 | ((i >= 0x30) && (i <= 0x37))) |
57 | continue; |
58 | WREG_DAC(i, dacvalue[i]); |
59 | } |
60 | |
61 | mgag200_init_registers(mdev); |
62 | } |
63 | |
64 | static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev, |
65 | const struct drm_display_mode *mode, |
66 | const struct drm_format_info *format) |
67 | { |
68 | struct mgag200_g200se_device *g200se = to_mgag200_g200se_device(dev: &mdev->base); |
69 | unsigned int hiprilvl; |
70 | u8 crtcext6; |
71 | |
72 | if (g200se->unique_rev_id >= 0x04) { |
73 | hiprilvl = 0; |
74 | } else if (g200se->unique_rev_id >= 0x02) { |
75 | unsigned int bpp; |
76 | unsigned long mb; |
77 | |
78 | if (format->cpp[0] * 8 > 16) |
79 | bpp = 32; |
80 | else if (format->cpp[0] * 8 > 8) |
81 | bpp = 16; |
82 | else |
83 | bpp = 8; |
84 | |
85 | mb = (mode->clock * bpp) / 1000; |
86 | if (mb > 3100) |
87 | hiprilvl = 0; |
88 | else if (mb > 2600) |
89 | hiprilvl = 1; |
90 | else if (mb > 1900) |
91 | hiprilvl = 2; |
92 | else if (mb > 1160) |
93 | hiprilvl = 3; |
94 | else if (mb > 440) |
95 | hiprilvl = 4; |
96 | else |
97 | hiprilvl = 5; |
98 | |
99 | } else if (g200se->unique_rev_id >= 0x01) { |
100 | hiprilvl = 3; |
101 | } else { |
102 | hiprilvl = 4; |
103 | } |
104 | |
105 | crtcext6 = hiprilvl; /* implicitly sets maxhipri to 0 */ |
106 | |
107 | WREG_ECRT(0x06, crtcext6); |
108 | } |
109 | |
110 | /* |
111 | * PIXPLLC |
112 | */ |
113 | |
114 | static int mgag200_g200se_00_pixpllc_atomic_check(struct drm_crtc *crtc, |
115 | struct drm_atomic_state *new_state) |
116 | { |
117 | static const unsigned int vcomax = 320000; |
118 | static const unsigned int vcomin = 160000; |
119 | static const unsigned int pllreffreq = 25000; |
120 | |
121 | struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(state: new_state, crtc); |
122 | struct mgag200_crtc_state *new_mgag200_crtc_state = to_mgag200_crtc_state(base: new_crtc_state); |
123 | long clock = new_crtc_state->mode.clock; |
124 | struct mgag200_pll_values *pixpllc = &new_mgag200_crtc_state->pixpllc; |
125 | unsigned int delta, tmpdelta, permitteddelta; |
126 | unsigned int testp, testm, testn; |
127 | unsigned int p, m, n, s; |
128 | unsigned int computed; |
129 | |
130 | m = n = p = s = 0; |
131 | delta = 0xffffffff; |
132 | permitteddelta = clock * 5 / 1000; |
133 | |
134 | for (testp = 8; testp > 0; testp /= 2) { |
135 | if (clock * testp > vcomax) |
136 | continue; |
137 | if (clock * testp < vcomin) |
138 | continue; |
139 | |
140 | for (testn = 17; testn < 256; testn++) { |
141 | for (testm = 1; testm < 32; testm++) { |
142 | computed = (pllreffreq * testn) / (testm * testp); |
143 | if (computed > clock) |
144 | tmpdelta = computed - clock; |
145 | else |
146 | tmpdelta = clock - computed; |
147 | if (tmpdelta < delta) { |
148 | delta = tmpdelta; |
149 | m = testm; |
150 | n = testn; |
151 | p = testp; |
152 | } |
153 | } |
154 | } |
155 | } |
156 | |
157 | if (delta > permitteddelta) { |
158 | pr_warn("PLL delta too large\n" ); |
159 | return -EINVAL; |
160 | } |
161 | |
162 | pixpllc->m = m; |
163 | pixpllc->n = n; |
164 | pixpllc->p = p; |
165 | pixpllc->s = s; |
166 | |
167 | return 0; |
168 | } |
169 | |
170 | static void mgag200_g200se_00_pixpllc_atomic_update(struct drm_crtc *crtc, |
171 | struct drm_atomic_state *old_state) |
172 | { |
173 | struct drm_device *dev = crtc->dev; |
174 | struct mga_device *mdev = to_mga_device(dev); |
175 | struct drm_crtc_state *crtc_state = crtc->state; |
176 | struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(base: crtc_state); |
177 | struct mgag200_pll_values *pixpllc = &mgag200_crtc_state->pixpllc; |
178 | unsigned int pixpllcm, pixpllcn, pixpllcp, pixpllcs; |
179 | u8 xpixpllcm, xpixpllcn, xpixpllcp; |
180 | |
181 | pixpllcm = pixpllc->m - 1; |
182 | pixpllcn = pixpllc->n - 1; |
183 | pixpllcp = pixpllc->p - 1; |
184 | pixpllcs = pixpllc->s; |
185 | |
186 | xpixpllcm = pixpllcm | ((pixpllcn & BIT(8)) >> 1); |
187 | xpixpllcn = pixpllcn; |
188 | xpixpllcp = (pixpllcs << 3) | pixpllcp; |
189 | |
190 | WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK); |
191 | |
192 | WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm); |
193 | WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn); |
194 | WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp); |
195 | } |
196 | |
197 | static int mgag200_g200se_04_pixpllc_atomic_check(struct drm_crtc *crtc, |
198 | struct drm_atomic_state *new_state) |
199 | { |
200 | static const unsigned int vcomax = 1600000; |
201 | static const unsigned int vcomin = 800000; |
202 | static const unsigned int pllreffreq = 25000; |
203 | static const unsigned int pvalues_e4[] = {16, 14, 12, 10, 8, 6, 4, 2, 1}; |
204 | |
205 | struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(state: new_state, crtc); |
206 | struct mgag200_crtc_state *new_mgag200_crtc_state = to_mgag200_crtc_state(base: new_crtc_state); |
207 | long clock = new_crtc_state->mode.clock; |
208 | struct mgag200_pll_values *pixpllc = &new_mgag200_crtc_state->pixpllc; |
209 | unsigned int delta, tmpdelta, permitteddelta; |
210 | unsigned int testp, testm, testn; |
211 | unsigned int p, m, n, s; |
212 | unsigned int computed; |
213 | unsigned int fvv; |
214 | unsigned int i; |
215 | |
216 | m = n = p = s = 0; |
217 | delta = 0xffffffff; |
218 | |
219 | if (clock < 25000) |
220 | clock = 25000; |
221 | clock = clock * 2; |
222 | |
223 | /* Permited delta is 0.5% as VESA Specification */ |
224 | permitteddelta = clock * 5 / 1000; |
225 | |
226 | for (i = 0 ; i < ARRAY_SIZE(pvalues_e4); i++) { |
227 | testp = pvalues_e4[i]; |
228 | |
229 | if ((clock * testp) > vcomax) |
230 | continue; |
231 | if ((clock * testp) < vcomin) |
232 | continue; |
233 | |
234 | for (testn = 50; testn <= 256; testn++) { |
235 | for (testm = 1; testm <= 32; testm++) { |
236 | computed = (pllreffreq * testn) / (testm * testp); |
237 | if (computed > clock) |
238 | tmpdelta = computed - clock; |
239 | else |
240 | tmpdelta = clock - computed; |
241 | |
242 | if (tmpdelta < delta) { |
243 | delta = tmpdelta; |
244 | m = testm; |
245 | n = testn; |
246 | p = testp; |
247 | } |
248 | } |
249 | } |
250 | } |
251 | |
252 | fvv = pllreffreq * n / m; |
253 | fvv = (fvv - 800000) / 50000; |
254 | if (fvv > 15) |
255 | fvv = 15; |
256 | s = fvv << 1; |
257 | |
258 | if (delta > permitteddelta) { |
259 | pr_warn("PLL delta too large\n" ); |
260 | return -EINVAL; |
261 | } |
262 | |
263 | pixpllc->m = m; |
264 | pixpllc->n = n; |
265 | pixpllc->p = p; |
266 | pixpllc->s = s; |
267 | |
268 | return 0; |
269 | } |
270 | |
271 | static void mgag200_g200se_04_pixpllc_atomic_update(struct drm_crtc *crtc, |
272 | struct drm_atomic_state *old_state) |
273 | { |
274 | struct drm_device *dev = crtc->dev; |
275 | struct mga_device *mdev = to_mga_device(dev); |
276 | struct drm_crtc_state *crtc_state = crtc->state; |
277 | struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(base: crtc_state); |
278 | struct mgag200_pll_values *pixpllc = &mgag200_crtc_state->pixpllc; |
279 | unsigned int pixpllcm, pixpllcn, pixpllcp, pixpllcs; |
280 | u8 xpixpllcm, xpixpllcn, xpixpllcp; |
281 | |
282 | pixpllcm = pixpllc->m - 1; |
283 | pixpllcn = pixpllc->n - 1; |
284 | pixpllcp = pixpllc->p - 1; |
285 | pixpllcs = pixpllc->s; |
286 | |
287 | // For G200SE A, BIT(7) should be set unconditionally. |
288 | xpixpllcm = BIT(7) | pixpllcm; |
289 | xpixpllcn = pixpllcn; |
290 | xpixpllcp = (pixpllcs << 3) | pixpllcp; |
291 | |
292 | WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK); |
293 | |
294 | WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm); |
295 | WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn); |
296 | WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp); |
297 | |
298 | WREG_DAC(0x1a, 0x09); |
299 | msleep(msecs: 20); |
300 | WREG_DAC(0x1a, 0x01); |
301 | } |
302 | |
303 | /* |
304 | * Mode-setting pipeline |
305 | */ |
306 | |
307 | static const struct drm_plane_helper_funcs mgag200_g200se_primary_plane_helper_funcs = { |
308 | MGAG200_PRIMARY_PLANE_HELPER_FUNCS, |
309 | }; |
310 | |
311 | static const struct drm_plane_funcs mgag200_g200se_primary_plane_funcs = { |
312 | MGAG200_PRIMARY_PLANE_FUNCS, |
313 | }; |
314 | |
315 | static void mgag200_g200se_crtc_helper_atomic_enable(struct drm_crtc *crtc, |
316 | struct drm_atomic_state *old_state) |
317 | { |
318 | struct drm_device *dev = crtc->dev; |
319 | struct mga_device *mdev = to_mga_device(dev); |
320 | const struct mgag200_device_funcs *funcs = mdev->funcs; |
321 | struct drm_crtc_state *crtc_state = crtc->state; |
322 | struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; |
323 | struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(base: crtc_state); |
324 | const struct drm_format_info *format = mgag200_crtc_state->format; |
325 | |
326 | if (funcs->disable_vidrst) |
327 | funcs->disable_vidrst(mdev); |
328 | |
329 | mgag200_set_format_regs(mdev, format); |
330 | mgag200_set_mode_regs(mdev, mode: adjusted_mode); |
331 | |
332 | if (funcs->pixpllc_atomic_update) |
333 | funcs->pixpllc_atomic_update(crtc, old_state); |
334 | |
335 | mgag200_g200se_set_hiprilvl(mdev, mode: adjusted_mode, format); |
336 | |
337 | if (crtc_state->gamma_lut) |
338 | mgag200_crtc_set_gamma(mdev, format, lut: crtc_state->gamma_lut->data); |
339 | else |
340 | mgag200_crtc_set_gamma_linear(mdev, format); |
341 | |
342 | mgag200_enable_display(mdev); |
343 | |
344 | if (funcs->enable_vidrst) |
345 | funcs->enable_vidrst(mdev); |
346 | } |
347 | |
348 | static const struct drm_crtc_helper_funcs mgag200_g200se_crtc_helper_funcs = { |
349 | .mode_valid = mgag200_crtc_helper_mode_valid, |
350 | .atomic_check = mgag200_crtc_helper_atomic_check, |
351 | .atomic_flush = mgag200_crtc_helper_atomic_flush, |
352 | .atomic_enable = mgag200_g200se_crtc_helper_atomic_enable, |
353 | .atomic_disable = mgag200_crtc_helper_atomic_disable |
354 | }; |
355 | |
356 | static const struct drm_crtc_funcs mgag200_g200se_crtc_funcs = { |
357 | MGAG200_CRTC_FUNCS, |
358 | }; |
359 | |
360 | static const struct drm_encoder_funcs mgag200_g200se_dac_encoder_funcs = { |
361 | MGAG200_DAC_ENCODER_FUNCS, |
362 | }; |
363 | |
364 | static const struct drm_connector_helper_funcs mgag200_g200se_vga_connector_helper_funcs = { |
365 | MGAG200_VGA_CONNECTOR_HELPER_FUNCS, |
366 | }; |
367 | |
368 | static const struct drm_connector_funcs mgag200_g200se_vga_connector_funcs = { |
369 | MGAG200_VGA_CONNECTOR_FUNCS, |
370 | }; |
371 | |
372 | static int mgag200_g200se_pipeline_init(struct mga_device *mdev) |
373 | { |
374 | struct drm_device *dev = &mdev->base; |
375 | struct drm_plane *primary_plane = &mdev->primary_plane; |
376 | struct drm_crtc *crtc = &mdev->crtc; |
377 | struct drm_encoder *encoder = &mdev->encoder; |
378 | struct mga_i2c_chan *i2c = &mdev->i2c; |
379 | struct drm_connector *connector = &mdev->connector; |
380 | int ret; |
381 | |
382 | ret = drm_universal_plane_init(dev, plane: primary_plane, possible_crtcs: 0, |
383 | funcs: &mgag200_g200se_primary_plane_funcs, |
384 | formats: mgag200_primary_plane_formats, |
385 | format_count: mgag200_primary_plane_formats_size, |
386 | format_modifiers: mgag200_primary_plane_fmtmods, |
387 | type: DRM_PLANE_TYPE_PRIMARY, NULL); |
388 | if (ret) { |
389 | drm_err(dev, "drm_universal_plane_init() failed: %d\n" , ret); |
390 | return ret; |
391 | } |
392 | drm_plane_helper_add(plane: primary_plane, funcs: &mgag200_g200se_primary_plane_helper_funcs); |
393 | drm_plane_enable_fb_damage_clips(plane: primary_plane); |
394 | |
395 | ret = drm_crtc_init_with_planes(dev, crtc, primary: primary_plane, NULL, |
396 | funcs: &mgag200_g200se_crtc_funcs, NULL); |
397 | if (ret) { |
398 | drm_err(dev, "drm_crtc_init_with_planes() failed: %d\n" , ret); |
399 | return ret; |
400 | } |
401 | drm_crtc_helper_add(crtc, funcs: &mgag200_g200se_crtc_helper_funcs); |
402 | |
403 | /* FIXME: legacy gamma tables, but atomic gamma doesn't work without */ |
404 | drm_mode_crtc_set_gamma_size(crtc, MGAG200_LUT_SIZE); |
405 | drm_crtc_enable_color_mgmt(crtc, degamma_lut_size: 0, has_ctm: false, MGAG200_LUT_SIZE); |
406 | |
407 | encoder->possible_crtcs = drm_crtc_mask(crtc); |
408 | ret = drm_encoder_init(dev, encoder, funcs: &mgag200_g200se_dac_encoder_funcs, |
409 | DRM_MODE_ENCODER_DAC, NULL); |
410 | if (ret) { |
411 | drm_err(dev, "drm_encoder_init() failed: %d\n" , ret); |
412 | return ret; |
413 | } |
414 | |
415 | ret = mgag200_i2c_init(mdev, i2c); |
416 | if (ret) { |
417 | drm_err(dev, "failed to add DDC bus: %d\n" , ret); |
418 | return ret; |
419 | } |
420 | |
421 | ret = drm_connector_init_with_ddc(dev, connector, |
422 | funcs: &mgag200_g200se_vga_connector_funcs, |
423 | DRM_MODE_CONNECTOR_VGA, |
424 | ddc: &i2c->adapter); |
425 | if (ret) { |
426 | drm_err(dev, "drm_connector_init_with_ddc() failed: %d\n" , ret); |
427 | return ret; |
428 | } |
429 | drm_connector_helper_add(connector, funcs: &mgag200_g200se_vga_connector_helper_funcs); |
430 | |
431 | ret = drm_connector_attach_encoder(connector, encoder); |
432 | if (ret) { |
433 | drm_err(dev, "drm_connector_attach_encoder() failed: %d\n" , ret); |
434 | return ret; |
435 | } |
436 | |
437 | return 0; |
438 | } |
439 | |
440 | /* |
441 | * DRM device |
442 | */ |
443 | |
444 | static const struct mgag200_device_info mgag200_g200se_a_01_device_info = |
445 | MGAG200_DEVICE_INFO_INIT(1600, 1200, 24400, false, 0, 1, true); |
446 | |
447 | static const struct mgag200_device_info mgag200_g200se_a_02_device_info = |
448 | MGAG200_DEVICE_INFO_INIT(1920, 1200, 30100, false, 0, 1, true); |
449 | |
450 | static const struct mgag200_device_info mgag200_g200se_a_03_device_info = |
451 | MGAG200_DEVICE_INFO_INIT(2048, 2048, 55000, false, 0, 1, false); |
452 | |
453 | static const struct mgag200_device_info mgag200_g200se_b_01_device_info = |
454 | MGAG200_DEVICE_INFO_INIT(1600, 1200, 24400, false, 0, 1, false); |
455 | |
456 | static const struct mgag200_device_info mgag200_g200se_b_02_device_info = |
457 | MGAG200_DEVICE_INFO_INIT(1920, 1200, 30100, false, 0, 1, false); |
458 | |
459 | static const struct mgag200_device_info mgag200_g200se_b_03_device_info = |
460 | MGAG200_DEVICE_INFO_INIT(2048, 2048, 55000, false, 0, 1, false); |
461 | |
462 | static int mgag200_g200se_init_unique_rev_id(struct mgag200_g200se_device *g200se) |
463 | { |
464 | struct mga_device *mdev = &g200se->base; |
465 | struct drm_device *dev = &mdev->base; |
466 | |
467 | /* stash G200 SE model number for later use */ |
468 | g200se->unique_rev_id = RREG32(0x1e24); |
469 | if (!g200se->unique_rev_id) |
470 | return -ENODEV; |
471 | |
472 | drm_dbg(dev, "G200 SE unique revision id is 0x%x\n" , g200se->unique_rev_id); |
473 | |
474 | return 0; |
475 | } |
476 | |
477 | static const struct mgag200_device_funcs mgag200_g200se_00_device_funcs = { |
478 | .pixpllc_atomic_check = mgag200_g200se_00_pixpllc_atomic_check, |
479 | .pixpllc_atomic_update = mgag200_g200se_00_pixpllc_atomic_update, |
480 | }; |
481 | |
482 | static const struct mgag200_device_funcs mgag200_g200se_04_device_funcs = { |
483 | .pixpllc_atomic_check = mgag200_g200se_04_pixpllc_atomic_check, |
484 | .pixpllc_atomic_update = mgag200_g200se_04_pixpllc_atomic_update, |
485 | }; |
486 | |
487 | struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const struct drm_driver *drv, |
488 | enum mga_type type) |
489 | { |
490 | struct mgag200_g200se_device *g200se; |
491 | const struct mgag200_device_info *info; |
492 | const struct mgag200_device_funcs *funcs; |
493 | struct mga_device *mdev; |
494 | struct drm_device *dev; |
495 | resource_size_t vram_available; |
496 | int ret; |
497 | |
498 | g200se = devm_drm_dev_alloc(&pdev->dev, drv, struct mgag200_g200se_device, base.base); |
499 | if (IS_ERR(ptr: g200se)) |
500 | return ERR_CAST(ptr: g200se); |
501 | mdev = &g200se->base; |
502 | dev = &mdev->base; |
503 | |
504 | pci_set_drvdata(pdev, data: dev); |
505 | |
506 | ret = mgag200_g200se_init_pci_options(pdev); |
507 | if (ret) |
508 | return ERR_PTR(error: ret); |
509 | |
510 | ret = mgag200_device_preinit(mdev); |
511 | if (ret) |
512 | return ERR_PTR(error: ret); |
513 | |
514 | ret = mgag200_g200se_init_unique_rev_id(g200se); |
515 | if (ret) |
516 | return ERR_PTR(error: ret); |
517 | |
518 | switch (type) { |
519 | case G200_SE_A: |
520 | if (g200se->unique_rev_id >= 0x03) |
521 | info = &mgag200_g200se_a_03_device_info; |
522 | else if (g200se->unique_rev_id >= 0x02) |
523 | info = &mgag200_g200se_a_02_device_info; |
524 | else |
525 | info = &mgag200_g200se_a_01_device_info; |
526 | break; |
527 | case G200_SE_B: |
528 | if (g200se->unique_rev_id >= 0x03) |
529 | info = &mgag200_g200se_b_03_device_info; |
530 | else if (g200se->unique_rev_id >= 0x02) |
531 | info = &mgag200_g200se_b_02_device_info; |
532 | else |
533 | info = &mgag200_g200se_b_01_device_info; |
534 | break; |
535 | default: |
536 | return ERR_PTR(error: -EINVAL); |
537 | } |
538 | |
539 | if (g200se->unique_rev_id >= 0x04) |
540 | funcs = &mgag200_g200se_04_device_funcs; |
541 | else |
542 | funcs = &mgag200_g200se_00_device_funcs; |
543 | |
544 | ret = mgag200_device_init(mdev, info, funcs); |
545 | if (ret) |
546 | return ERR_PTR(error: ret); |
547 | |
548 | mgag200_g200se_init_registers(g200se); |
549 | |
550 | vram_available = mgag200_device_probe_vram(mdev); |
551 | |
552 | ret = mgag200_mode_config_init(mdev, vram_available); |
553 | if (ret) |
554 | return ERR_PTR(error: ret); |
555 | |
556 | ret = mgag200_g200se_pipeline_init(mdev); |
557 | if (ret) |
558 | return ERR_PTR(error: ret); |
559 | |
560 | drm_mode_config_reset(dev); |
561 | |
562 | return mdev; |
563 | } |
564 | |