1 | /* |
---|---|
2 | * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sub license, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice (including the |
12 | * next paragraph) shall be included in all copies or substantial portions |
13 | * of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
21 | * DEALINGS IN THE SOFTWARE. |
22 | */ |
23 | |
24 | #include <linux/delay.h> |
25 | #include <linux/gpio/consumer.h> |
26 | #include <linux/i2c.h> |
27 | #include <linux/media-bus-format.h> |
28 | #include <linux/module.h> |
29 | #include <linux/of_platform.h> |
30 | #include <linux/platform_device.h> |
31 | #include <linux/pm_runtime.h> |
32 | #include <linux/regulator/consumer.h> |
33 | |
34 | #include <video/display_timing.h> |
35 | #include <video/of_display_timing.h> |
36 | #include <video/videomode.h> |
37 | |
38 | #include <drm/drm_crtc.h> |
39 | #include <drm/drm_device.h> |
40 | #include <drm/drm_edid.h> |
41 | #include <drm/drm_mipi_dsi.h> |
42 | #include <drm/drm_panel.h> |
43 | #include <drm/drm_of.h> |
44 | |
45 | /** |
46 | * struct panel_desc - Describes a simple panel. |
47 | */ |
48 | struct panel_desc { |
49 | /** |
50 | * @modes: Pointer to array of fixed modes appropriate for this panel. |
51 | * |
52 | * If only one mode then this can just be the address of the mode. |
53 | * NOTE: cannot be used with "timings" and also if this is specified |
54 | * then you cannot override the mode in the device tree. |
55 | */ |
56 | const struct drm_display_mode *modes; |
57 | |
58 | /** @num_modes: Number of elements in modes array. */ |
59 | unsigned int num_modes; |
60 | |
61 | /** |
62 | * @timings: Pointer to array of display timings |
63 | * |
64 | * NOTE: cannot be used with "modes" and also these will be used to |
65 | * validate a device tree override if one is present. |
66 | */ |
67 | const struct display_timing *timings; |
68 | |
69 | /** @num_timings: Number of elements in timings array. */ |
70 | unsigned int num_timings; |
71 | |
72 | /** @bpc: Bits per color. */ |
73 | unsigned int bpc; |
74 | |
75 | /** @size: Structure containing the physical size of this panel. */ |
76 | struct { |
77 | /** |
78 | * @size.width: Width (in mm) of the active display area. |
79 | */ |
80 | unsigned int width; |
81 | |
82 | /** |
83 | * @size.height: Height (in mm) of the active display area. |
84 | */ |
85 | unsigned int height; |
86 | } size; |
87 | |
88 | /** @delay: Structure containing various delay values for this panel. */ |
89 | struct { |
90 | /** |
91 | * @delay.prepare: Time for the panel to become ready. |
92 | * |
93 | * The time (in milliseconds) that it takes for the panel to |
94 | * become ready and start receiving video data |
95 | */ |
96 | unsigned int prepare; |
97 | |
98 | /** |
99 | * @delay.enable: Time for the panel to display a valid frame. |
100 | * |
101 | * The time (in milliseconds) that it takes for the panel to |
102 | * display the first valid frame after starting to receive |
103 | * video data. |
104 | */ |
105 | unsigned int enable; |
106 | |
107 | /** |
108 | * @delay.disable: Time for the panel to turn the display off. |
109 | * |
110 | * The time (in milliseconds) that it takes for the panel to |
111 | * turn the display off (no content is visible). |
112 | */ |
113 | unsigned int disable; |
114 | |
115 | /** |
116 | * @delay.unprepare: Time to power down completely. |
117 | * |
118 | * The time (in milliseconds) that it takes for the panel |
119 | * to power itself down completely. |
120 | * |
121 | * This time is used to prevent a future "prepare" from |
122 | * starting until at least this many milliseconds has passed. |
123 | * If at prepare time less time has passed since unprepare |
124 | * finished, the driver waits for the remaining time. |
125 | */ |
126 | unsigned int unprepare; |
127 | } delay; |
128 | |
129 | /** @bus_format: See MEDIA_BUS_FMT_... defines. */ |
130 | u32 bus_format; |
131 | |
132 | /** @bus_flags: See DRM_BUS_FLAG_... defines. */ |
133 | u32 bus_flags; |
134 | |
135 | /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ |
136 | int connector_type; |
137 | }; |
138 | |
139 | struct panel_simple { |
140 | struct drm_panel base; |
141 | |
142 | ktime_t unprepared_time; |
143 | |
144 | const struct panel_desc *desc; |
145 | |
146 | struct regulator *supply; |
147 | struct i2c_adapter *ddc; |
148 | |
149 | struct gpio_desc *enable_gpio; |
150 | |
151 | const struct drm_edid *drm_edid; |
152 | |
153 | struct drm_display_mode override_mode; |
154 | |
155 | enum drm_panel_orientation orientation; |
156 | }; |
157 | |
158 | static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) |
159 | { |
160 | return container_of(panel, struct panel_simple, base); |
161 | } |
162 | |
163 | static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, |
164 | struct drm_connector *connector) |
165 | { |
166 | struct drm_display_mode *mode; |
167 | unsigned int i, num = 0; |
168 | |
169 | for (i = 0; i < panel->desc->num_timings; i++) { |
170 | const struct display_timing *dt = &panel->desc->timings[i]; |
171 | struct videomode vm; |
172 | |
173 | videomode_from_timing(dt, vm: &vm); |
174 | mode = drm_mode_create(dev: connector->dev); |
175 | if (!mode) { |
176 | dev_err(panel->base.dev, "failed to add mode %ux%u\n", |
177 | dt->hactive.typ, dt->vactive.typ); |
178 | continue; |
179 | } |
180 | |
181 | drm_display_mode_from_videomode(vm: &vm, dmode: mode); |
182 | |
183 | mode->type |= DRM_MODE_TYPE_DRIVER; |
184 | |
185 | if (panel->desc->num_timings == 1) |
186 | mode->type |= DRM_MODE_TYPE_PREFERRED; |
187 | |
188 | drm_mode_probed_add(connector, mode); |
189 | num++; |
190 | } |
191 | |
192 | return num; |
193 | } |
194 | |
195 | static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, |
196 | struct drm_connector *connector) |
197 | { |
198 | struct drm_display_mode *mode; |
199 | unsigned int i, num = 0; |
200 | |
201 | for (i = 0; i < panel->desc->num_modes; i++) { |
202 | const struct drm_display_mode *m = &panel->desc->modes[i]; |
203 | |
204 | mode = drm_mode_duplicate(dev: connector->dev, mode: m); |
205 | if (!mode) { |
206 | dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", |
207 | m->hdisplay, m->vdisplay, |
208 | drm_mode_vrefresh(m)); |
209 | continue; |
210 | } |
211 | |
212 | mode->type |= DRM_MODE_TYPE_DRIVER; |
213 | |
214 | if (panel->desc->num_modes == 1) |
215 | mode->type |= DRM_MODE_TYPE_PREFERRED; |
216 | |
217 | drm_mode_set_name(mode); |
218 | |
219 | drm_mode_probed_add(connector, mode); |
220 | num++; |
221 | } |
222 | |
223 | return num; |
224 | } |
225 | |
226 | static int panel_simple_get_non_edid_modes(struct panel_simple *panel, |
227 | struct drm_connector *connector) |
228 | { |
229 | struct drm_display_mode *mode; |
230 | bool has_override = panel->override_mode.type; |
231 | unsigned int num = 0; |
232 | |
233 | if (!panel->desc) |
234 | return 0; |
235 | |
236 | if (has_override) { |
237 | mode = drm_mode_duplicate(dev: connector->dev, |
238 | mode: &panel->override_mode); |
239 | if (mode) { |
240 | drm_mode_probed_add(connector, mode); |
241 | num = 1; |
242 | } else { |
243 | dev_err(panel->base.dev, "failed to add override mode\n"); |
244 | } |
245 | } |
246 | |
247 | /* Only add timings if override was not there or failed to validate */ |
248 | if (num == 0 && panel->desc->num_timings) |
249 | num = panel_simple_get_timings_modes(panel, connector); |
250 | |
251 | /* |
252 | * Only add fixed modes if timings/override added no mode. |
253 | * |
254 | * We should only ever have either the display timings specified |
255 | * or a fixed mode. Anything else is rather bogus. |
256 | */ |
257 | WARN_ON(panel->desc->num_timings && panel->desc->num_modes); |
258 | if (num == 0) |
259 | num = panel_simple_get_display_modes(panel, connector); |
260 | |
261 | connector->display_info.bpc = panel->desc->bpc; |
262 | connector->display_info.width_mm = panel->desc->size.width; |
263 | connector->display_info.height_mm = panel->desc->size.height; |
264 | if (panel->desc->bus_format) |
265 | drm_display_info_set_bus_formats(info: &connector->display_info, |
266 | formats: &panel->desc->bus_format, num_formats: 1); |
267 | connector->display_info.bus_flags = panel->desc->bus_flags; |
268 | |
269 | return num; |
270 | } |
271 | |
272 | static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) |
273 | { |
274 | ktime_t now_ktime, min_ktime; |
275 | |
276 | if (!min_ms) |
277 | return; |
278 | |
279 | min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); |
280 | now_ktime = ktime_get_boottime(); |
281 | |
282 | if (ktime_before(cmp1: now_ktime, cmp2: min_ktime)) |
283 | msleep(msecs: ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); |
284 | } |
285 | |
286 | static int panel_simple_disable(struct drm_panel *panel) |
287 | { |
288 | struct panel_simple *p = to_panel_simple(panel); |
289 | |
290 | if (p->desc->delay.disable) |
291 | msleep(msecs: p->desc->delay.disable); |
292 | |
293 | return 0; |
294 | } |
295 | |
296 | static int panel_simple_suspend(struct device *dev) |
297 | { |
298 | struct panel_simple *p = dev_get_drvdata(dev); |
299 | |
300 | gpiod_set_value_cansleep(desc: p->enable_gpio, value: 0); |
301 | regulator_disable(regulator: p->supply); |
302 | p->unprepared_time = ktime_get_boottime(); |
303 | |
304 | drm_edid_free(drm_edid: p->drm_edid); |
305 | p->drm_edid = NULL; |
306 | |
307 | return 0; |
308 | } |
309 | |
310 | static int panel_simple_unprepare(struct drm_panel *panel) |
311 | { |
312 | int ret; |
313 | |
314 | pm_runtime_mark_last_busy(dev: panel->dev); |
315 | ret = pm_runtime_put_autosuspend(dev: panel->dev); |
316 | if (ret < 0) |
317 | return ret; |
318 | |
319 | return 0; |
320 | } |
321 | |
322 | static int panel_simple_resume(struct device *dev) |
323 | { |
324 | struct panel_simple *p = dev_get_drvdata(dev); |
325 | int err; |
326 | |
327 | panel_simple_wait(start_ktime: p->unprepared_time, min_ms: p->desc->delay.unprepare); |
328 | |
329 | err = regulator_enable(regulator: p->supply); |
330 | if (err < 0) { |
331 | dev_err(dev, "failed to enable supply: %d\n", err); |
332 | return err; |
333 | } |
334 | |
335 | gpiod_set_value_cansleep(desc: p->enable_gpio, value: 1); |
336 | |
337 | if (p->desc->delay.prepare) |
338 | msleep(msecs: p->desc->delay.prepare); |
339 | |
340 | return 0; |
341 | } |
342 | |
343 | static int panel_simple_prepare(struct drm_panel *panel) |
344 | { |
345 | int ret; |
346 | |
347 | ret = pm_runtime_get_sync(dev: panel->dev); |
348 | if (ret < 0) { |
349 | pm_runtime_put_autosuspend(dev: panel->dev); |
350 | return ret; |
351 | } |
352 | |
353 | return 0; |
354 | } |
355 | |
356 | static int panel_simple_enable(struct drm_panel *panel) |
357 | { |
358 | struct panel_simple *p = to_panel_simple(panel); |
359 | |
360 | if (p->desc->delay.enable) |
361 | msleep(msecs: p->desc->delay.enable); |
362 | |
363 | return 0; |
364 | } |
365 | |
366 | static int panel_simple_get_modes(struct drm_panel *panel, |
367 | struct drm_connector *connector) |
368 | { |
369 | struct panel_simple *p = to_panel_simple(panel); |
370 | int num = 0; |
371 | |
372 | /* probe EDID if a DDC bus is available */ |
373 | if (p->ddc) { |
374 | pm_runtime_get_sync(dev: panel->dev); |
375 | |
376 | if (!p->drm_edid) |
377 | p->drm_edid = drm_edid_read_ddc(connector, adapter: p->ddc); |
378 | |
379 | drm_edid_connector_update(connector, edid: p->drm_edid); |
380 | |
381 | num += drm_edid_connector_add_modes(connector); |
382 | |
383 | pm_runtime_mark_last_busy(dev: panel->dev); |
384 | pm_runtime_put_autosuspend(dev: panel->dev); |
385 | } |
386 | |
387 | /* add hard-coded panel modes */ |
388 | num += panel_simple_get_non_edid_modes(panel: p, connector); |
389 | |
390 | /* |
391 | * TODO: Remove once all drm drivers call |
392 | * drm_connector_set_orientation_from_panel() |
393 | */ |
394 | drm_connector_set_panel_orientation(connector, panel_orientation: p->orientation); |
395 | |
396 | return num; |
397 | } |
398 | |
399 | static int panel_simple_get_timings(struct drm_panel *panel, |
400 | unsigned int num_timings, |
401 | struct display_timing *timings) |
402 | { |
403 | struct panel_simple *p = to_panel_simple(panel); |
404 | unsigned int i; |
405 | |
406 | if (p->desc->num_timings < num_timings) |
407 | num_timings = p->desc->num_timings; |
408 | |
409 | if (timings) |
410 | for (i = 0; i < num_timings; i++) |
411 | timings[i] = p->desc->timings[i]; |
412 | |
413 | return p->desc->num_timings; |
414 | } |
415 | |
416 | static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) |
417 | { |
418 | struct panel_simple *p = to_panel_simple(panel); |
419 | |
420 | return p->orientation; |
421 | } |
422 | |
423 | static const struct drm_panel_funcs panel_simple_funcs = { |
424 | .disable = panel_simple_disable, |
425 | .unprepare = panel_simple_unprepare, |
426 | .prepare = panel_simple_prepare, |
427 | .enable = panel_simple_enable, |
428 | .get_modes = panel_simple_get_modes, |
429 | .get_orientation = panel_simple_get_orientation, |
430 | .get_timings = panel_simple_get_timings, |
431 | }; |
432 | |
433 | static struct panel_desc panel_dpi; |
434 | |
435 | static int panel_dpi_probe(struct device *dev, |
436 | struct panel_simple *panel) |
437 | { |
438 | struct display_timing *timing; |
439 | const struct device_node *np; |
440 | struct panel_desc *desc; |
441 | unsigned int bus_flags; |
442 | struct videomode vm; |
443 | int ret; |
444 | |
445 | np = dev->of_node; |
446 | desc = devm_kzalloc(dev, size: sizeof(*desc), GFP_KERNEL); |
447 | if (!desc) |
448 | return -ENOMEM; |
449 | |
450 | timing = devm_kzalloc(dev, size: sizeof(*timing), GFP_KERNEL); |
451 | if (!timing) |
452 | return -ENOMEM; |
453 | |
454 | ret = of_get_display_timing(np, name: "panel-timing", dt: timing); |
455 | if (ret < 0) { |
456 | dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", |
457 | np); |
458 | return ret; |
459 | } |
460 | |
461 | desc->timings = timing; |
462 | desc->num_timings = 1; |
463 | |
464 | of_property_read_u32(np, propname: "width-mm", out_value: &desc->size.width); |
465 | of_property_read_u32(np, propname: "height-mm", out_value: &desc->size.height); |
466 | |
467 | /* Extract bus_flags from display_timing */ |
468 | bus_flags = 0; |
469 | vm.flags = timing->flags; |
470 | drm_bus_flags_from_videomode(vm: &vm, bus_flags: &bus_flags); |
471 | desc->bus_flags = bus_flags; |
472 | |
473 | /* We do not know the connector for the DT node, so guess it */ |
474 | desc->connector_type = DRM_MODE_CONNECTOR_DPI; |
475 | |
476 | panel->desc = desc; |
477 | |
478 | return 0; |
479 | } |
480 | |
481 | #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ |
482 | (to_check->field.typ >= bounds->field.min && \ |
483 | to_check->field.typ <= bounds->field.max) |
484 | static void panel_simple_parse_panel_timing_node(struct device *dev, |
485 | struct panel_simple *panel, |
486 | const struct display_timing *ot) |
487 | { |
488 | const struct panel_desc *desc = panel->desc; |
489 | struct videomode vm; |
490 | unsigned int i; |
491 | |
492 | if (WARN_ON(desc->num_modes)) { |
493 | dev_err(dev, "Reject override mode: panel has a fixed mode\n"); |
494 | return; |
495 | } |
496 | if (WARN_ON(!desc->num_timings)) { |
497 | dev_err(dev, "Reject override mode: no timings specified\n"); |
498 | return; |
499 | } |
500 | |
501 | for (i = 0; i < panel->desc->num_timings; i++) { |
502 | const struct display_timing *dt = &panel->desc->timings[i]; |
503 | |
504 | if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || |
505 | !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || |
506 | !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || |
507 | !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || |
508 | !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || |
509 | !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || |
510 | !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || |
511 | !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) |
512 | continue; |
513 | |
514 | if (ot->flags != dt->flags) |
515 | continue; |
516 | |
517 | videomode_from_timing(dt: ot, vm: &vm); |
518 | drm_display_mode_from_videomode(vm: &vm, dmode: &panel->override_mode); |
519 | panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | |
520 | DRM_MODE_TYPE_PREFERRED; |
521 | break; |
522 | } |
523 | |
524 | if (WARN_ON(!panel->override_mode.type)) |
525 | dev_err(dev, "Reject override mode: No display_timing found\n"); |
526 | } |
527 | |
528 | static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, |
529 | struct panel_simple *panel) |
530 | { |
531 | int ret, bpc; |
532 | |
533 | ret = drm_of_lvds_get_data_mapping(port: dev->of_node); |
534 | if (ret < 0) { |
535 | if (ret == -EINVAL) |
536 | dev_warn(dev, "Ignore invalid data-mapping property\n"); |
537 | |
538 | /* |
539 | * Ignore non-existing or malformatted property, fallback to |
540 | * default data-mapping, and return 0. |
541 | */ |
542 | return 0; |
543 | } |
544 | |
545 | switch (ret) { |
546 | default: |
547 | WARN_ON(1); |
548 | fallthrough; |
549 | case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: |
550 | fallthrough; |
551 | case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: |
552 | bpc = 8; |
553 | break; |
554 | case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: |
555 | bpc = 6; |
556 | } |
557 | |
558 | if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { |
559 | struct panel_desc *override_desc; |
560 | |
561 | override_desc = devm_kmemdup(dev, src: panel->desc, len: sizeof(*panel->desc), GFP_KERNEL); |
562 | if (!override_desc) |
563 | return -ENOMEM; |
564 | |
565 | override_desc->bus_format = ret; |
566 | override_desc->bpc = bpc; |
567 | panel->desc = override_desc; |
568 | } |
569 | |
570 | return 0; |
571 | } |
572 | |
573 | static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) |
574 | { |
575 | struct panel_simple *panel; |
576 | struct display_timing dt; |
577 | struct device_node *ddc; |
578 | int connector_type; |
579 | u32 bus_flags; |
580 | int err; |
581 | |
582 | panel = devm_drm_panel_alloc(dev, struct panel_simple, base, |
583 | &panel_simple_funcs, desc->connector_type); |
584 | if (IS_ERR(ptr: panel)) |
585 | return PTR_ERR(ptr: panel); |
586 | |
587 | panel->desc = desc; |
588 | |
589 | panel->supply = devm_regulator_get(dev, id: "power"); |
590 | if (IS_ERR(ptr: panel->supply)) |
591 | return PTR_ERR(ptr: panel->supply); |
592 | |
593 | panel->enable_gpio = devm_gpiod_get_optional(dev, con_id: "enable", |
594 | flags: GPIOD_OUT_LOW); |
595 | if (IS_ERR(ptr: panel->enable_gpio)) |
596 | return dev_err_probe(dev, err: PTR_ERR(ptr: panel->enable_gpio), |
597 | fmt: "failed to request GPIO\n"); |
598 | |
599 | err = of_drm_get_panel_orientation(np: dev->of_node, orientation: &panel->orientation); |
600 | if (err) { |
601 | dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); |
602 | return err; |
603 | } |
604 | |
605 | ddc = of_parse_phandle(np: dev->of_node, phandle_name: "ddc-i2c-bus", index: 0); |
606 | if (ddc) { |
607 | panel->ddc = of_find_i2c_adapter_by_node(node: ddc); |
608 | of_node_put(node: ddc); |
609 | |
610 | if (!panel->ddc) |
611 | return -EPROBE_DEFER; |
612 | } |
613 | |
614 | if (desc == &panel_dpi) { |
615 | /* Handle the generic panel-dpi binding */ |
616 | err = panel_dpi_probe(dev, panel); |
617 | if (err) |
618 | goto free_ddc; |
619 | desc = panel->desc; |
620 | } else { |
621 | if (!of_get_display_timing(np: dev->of_node, name: "panel-timing", dt: &dt)) |
622 | panel_simple_parse_panel_timing_node(dev, panel, ot: &dt); |
623 | } |
624 | |
625 | if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { |
626 | /* Optional data-mapping property for overriding bus format */ |
627 | err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); |
628 | if (err) |
629 | goto free_ddc; |
630 | } |
631 | |
632 | connector_type = desc->connector_type; |
633 | /* Catch common mistakes for panels. */ |
634 | switch (connector_type) { |
635 | case 0: |
636 | dev_warn(dev, "Specify missing connector_type\n"); |
637 | connector_type = DRM_MODE_CONNECTOR_DPI; |
638 | break; |
639 | case DRM_MODE_CONNECTOR_LVDS: |
640 | WARN_ON(desc->bus_flags & |
641 | ~(DRM_BUS_FLAG_DE_LOW | |
642 | DRM_BUS_FLAG_DE_HIGH | |
643 | DRM_BUS_FLAG_DATA_MSB_TO_LSB | |
644 | DRM_BUS_FLAG_DATA_LSB_TO_MSB)); |
645 | WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && |
646 | desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && |
647 | desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); |
648 | WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && |
649 | desc->bpc != 6); |
650 | WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || |
651 | desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && |
652 | desc->bpc != 8); |
653 | break; |
654 | case DRM_MODE_CONNECTOR_eDP: |
655 | dev_warn(dev, "eDP panels moved to panel-edp\n"); |
656 | err = -EINVAL; |
657 | goto free_ddc; |
658 | case DRM_MODE_CONNECTOR_DSI: |
659 | if (desc->bpc != 6 && desc->bpc != 8) |
660 | dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); |
661 | break; |
662 | case DRM_MODE_CONNECTOR_DPI: |
663 | bus_flags = DRM_BUS_FLAG_DE_LOW | |
664 | DRM_BUS_FLAG_DE_HIGH | |
665 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | |
666 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | |
667 | DRM_BUS_FLAG_DATA_MSB_TO_LSB | |
668 | DRM_BUS_FLAG_DATA_LSB_TO_MSB | |
669 | DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | |
670 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; |
671 | if (desc->bus_flags & ~bus_flags) |
672 | dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); |
673 | if (!(desc->bus_flags & bus_flags)) |
674 | dev_warn(dev, "Specify missing bus_flags\n"); |
675 | if (desc->bus_format == 0) |
676 | dev_warn(dev, "Specify missing bus_format\n"); |
677 | if (desc->bpc != 6 && desc->bpc != 8) |
678 | dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); |
679 | break; |
680 | default: |
681 | dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); |
682 | connector_type = DRM_MODE_CONNECTOR_DPI; |
683 | break; |
684 | } |
685 | |
686 | dev_set_drvdata(dev, data: panel); |
687 | |
688 | /* |
689 | * We use runtime PM for prepare / unprepare since those power the panel |
690 | * on and off and those can be very slow operations. This is important |
691 | * to optimize powering the panel on briefly to read the EDID before |
692 | * fully enabling the panel. |
693 | */ |
694 | pm_runtime_enable(dev); |
695 | pm_runtime_set_autosuspend_delay(dev, delay: 1000); |
696 | pm_runtime_use_autosuspend(dev); |
697 | |
698 | err = drm_panel_of_backlight(panel: &panel->base); |
699 | if (err) { |
700 | dev_err_probe(dev, err, fmt: "Could not find backlight\n"); |
701 | goto disable_pm_runtime; |
702 | } |
703 | |
704 | drm_panel_add(panel: &panel->base); |
705 | |
706 | return 0; |
707 | |
708 | disable_pm_runtime: |
709 | pm_runtime_dont_use_autosuspend(dev); |
710 | pm_runtime_disable(dev); |
711 | free_ddc: |
712 | if (panel->ddc) |
713 | put_device(dev: &panel->ddc->dev); |
714 | |
715 | return err; |
716 | } |
717 | |
718 | static void panel_simple_shutdown(struct device *dev) |
719 | { |
720 | struct panel_simple *panel = dev_get_drvdata(dev); |
721 | |
722 | /* |
723 | * NOTE: the following two calls don't really belong here. It is the |
724 | * responsibility of a correctly written DRM modeset driver to call |
725 | * drm_atomic_helper_shutdown() at shutdown time and that should |
726 | * cause the panel to be disabled / unprepared if needed. For now, |
727 | * however, we'll keep these calls due to the sheer number of |
728 | * different DRM modeset drivers used with panel-simple. Once we've |
729 | * confirmed that all DRM modeset drivers using this panel properly |
730 | * call drm_atomic_helper_shutdown() we can simply delete the two |
731 | * calls below. |
732 | * |
733 | * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW |
734 | * PANEL DRIVERS. |
735 | * |
736 | * FIXME: If we're still haven't figured out if all DRM modeset |
737 | * drivers properly call drm_atomic_helper_shutdown() but we _have_ |
738 | * managed to make sure that DRM modeset drivers get their shutdown() |
739 | * callback before the panel's shutdown() callback (perhaps using |
740 | * device link), we could add a WARN_ON here to help move forward. |
741 | */ |
742 | if (panel->base.enabled) |
743 | drm_panel_disable(panel: &panel->base); |
744 | if (panel->base.prepared) |
745 | drm_panel_unprepare(panel: &panel->base); |
746 | } |
747 | |
748 | static void panel_simple_remove(struct device *dev) |
749 | { |
750 | struct panel_simple *panel = dev_get_drvdata(dev); |
751 | |
752 | drm_panel_remove(panel: &panel->base); |
753 | panel_simple_shutdown(dev); |
754 | |
755 | pm_runtime_dont_use_autosuspend(dev); |
756 | pm_runtime_disable(dev); |
757 | if (panel->ddc) |
758 | put_device(dev: &panel->ddc->dev); |
759 | } |
760 | |
761 | static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { |
762 | .clock = 71100, |
763 | .hdisplay = 1280, |
764 | .hsync_start = 1280 + 40, |
765 | .hsync_end = 1280 + 40 + 80, |
766 | .htotal = 1280 + 40 + 80 + 40, |
767 | .vdisplay = 800, |
768 | .vsync_start = 800 + 3, |
769 | .vsync_end = 800 + 3 + 10, |
770 | .vtotal = 800 + 3 + 10 + 10, |
771 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, |
772 | }; |
773 | |
774 | static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { |
775 | .modes = &ire_am_1280800n3tzqw_t00h_mode, |
776 | .num_modes = 1, |
777 | .bpc = 8, |
778 | .size = { |
779 | .width = 217, |
780 | .height = 136, |
781 | }, |
782 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
783 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
784 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
785 | }; |
786 | |
787 | static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { |
788 | .clock = 9000, |
789 | .hdisplay = 480, |
790 | .hsync_start = 480 + 2, |
791 | .hsync_end = 480 + 2 + 41, |
792 | .htotal = 480 + 2 + 41 + 2, |
793 | .vdisplay = 272, |
794 | .vsync_start = 272 + 2, |
795 | .vsync_end = 272 + 2 + 10, |
796 | .vtotal = 272 + 2 + 10 + 2, |
797 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, |
798 | }; |
799 | |
800 | static const struct panel_desc ampire_am_480272h3tmqw_t01h = { |
801 | .modes = &ire_am_480272h3tmqw_t01h_mode, |
802 | .num_modes = 1, |
803 | .bpc = 8, |
804 | .size = { |
805 | .width = 99, |
806 | .height = 58, |
807 | }, |
808 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
809 | }; |
810 | |
811 | static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { |
812 | .clock = 33333, |
813 | .hdisplay = 800, |
814 | .hsync_start = 800 + 0, |
815 | .hsync_end = 800 + 0 + 255, |
816 | .htotal = 800 + 0 + 255 + 0, |
817 | .vdisplay = 480, |
818 | .vsync_start = 480 + 2, |
819 | .vsync_end = 480 + 2 + 45, |
820 | .vtotal = 480 + 2 + 45 + 0, |
821 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, |
822 | }; |
823 | |
824 | static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { |
825 | .pixelclock = { 29930000, 33260000, 36590000 }, |
826 | .hactive = { 800, 800, 800 }, |
827 | .hfront_porch = { 1, 40, 168 }, |
828 | .hback_porch = { 88, 88, 88 }, |
829 | .hsync_len = { 1, 128, 128 }, |
830 | .vactive = { 480, 480, 480 }, |
831 | .vfront_porch = { 1, 35, 37 }, |
832 | .vback_porch = { 8, 8, 8 }, |
833 | .vsync_len = { 1, 2, 2 }, |
834 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
835 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | |
836 | DISPLAY_FLAGS_SYNC_POSEDGE, |
837 | }; |
838 | |
839 | static const struct panel_desc ampire_am_800480l1tmqw_t00h = { |
840 | .timings = &ire_am_800480l1tmqw_t00h_timing, |
841 | .num_timings = 1, |
842 | .bpc = 8, |
843 | .size = { |
844 | .width = 111, |
845 | .height = 67, |
846 | }, |
847 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
848 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | |
849 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | |
850 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, |
851 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
852 | }; |
853 | |
854 | static const struct panel_desc ampire_am800480r3tmqwa1h = { |
855 | .modes = &ire_am800480r3tmqwa1h_mode, |
856 | .num_modes = 1, |
857 | .bpc = 6, |
858 | .size = { |
859 | .width = 152, |
860 | .height = 91, |
861 | }, |
862 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
863 | }; |
864 | |
865 | static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { |
866 | .pixelclock = { 34500000, 39600000, 50400000 }, |
867 | .hactive = { 800, 800, 800 }, |
868 | .hfront_porch = { 12, 112, 312 }, |
869 | .hback_porch = { 87, 87, 48 }, |
870 | .hsync_len = { 1, 1, 40 }, |
871 | .vactive = { 600, 600, 600 }, |
872 | .vfront_porch = { 1, 21, 61 }, |
873 | .vback_porch = { 38, 38, 19 }, |
874 | .vsync_len = { 1, 1, 20 }, |
875 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
876 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | |
877 | DISPLAY_FLAGS_SYNC_POSEDGE, |
878 | }; |
879 | |
880 | static const struct panel_desc ampire_am800600p5tmqwtb8h = { |
881 | .timings = &ire_am800600p5tmqw_tb8h_timing, |
882 | .num_timings = 1, |
883 | .bpc = 6, |
884 | .size = { |
885 | .width = 162, |
886 | .height = 122, |
887 | }, |
888 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
889 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | |
890 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | |
891 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, |
892 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
893 | }; |
894 | |
895 | static const struct display_timing santek_st0700i5y_rbslw_f_timing = { |
896 | .pixelclock = { 26400000, 33300000, 46800000 }, |
897 | .hactive = { 800, 800, 800 }, |
898 | .hfront_porch = { 16, 210, 354 }, |
899 | .hback_porch = { 45, 36, 6 }, |
900 | .hsync_len = { 1, 10, 40 }, |
901 | .vactive = { 480, 480, 480 }, |
902 | .vfront_porch = { 7, 22, 147 }, |
903 | .vback_porch = { 22, 13, 3 }, |
904 | .vsync_len = { 1, 10, 20 }, |
905 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
906 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
907 | }; |
908 | |
909 | static const struct panel_desc armadeus_st0700_adapt = { |
910 | .timings = &santek_st0700i5y_rbslw_f_timing, |
911 | .num_timings = 1, |
912 | .bpc = 6, |
913 | .size = { |
914 | .width = 154, |
915 | .height = 86, |
916 | }, |
917 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
918 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
919 | }; |
920 | |
921 | static const struct drm_display_mode auo_b101aw03_mode = { |
922 | .clock = 51450, |
923 | .hdisplay = 1024, |
924 | .hsync_start = 1024 + 156, |
925 | .hsync_end = 1024 + 156 + 8, |
926 | .htotal = 1024 + 156 + 8 + 156, |
927 | .vdisplay = 600, |
928 | .vsync_start = 600 + 16, |
929 | .vsync_end = 600 + 16 + 6, |
930 | .vtotal = 600 + 16 + 6 + 16, |
931 | }; |
932 | |
933 | static const struct panel_desc auo_b101aw03 = { |
934 | .modes = &auo_b101aw03_mode, |
935 | .num_modes = 1, |
936 | .bpc = 6, |
937 | .size = { |
938 | .width = 223, |
939 | .height = 125, |
940 | }, |
941 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
942 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
943 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
944 | }; |
945 | |
946 | static const struct drm_display_mode auo_b101xtn01_mode = { |
947 | .clock = 72000, |
948 | .hdisplay = 1366, |
949 | .hsync_start = 1366 + 20, |
950 | .hsync_end = 1366 + 20 + 70, |
951 | .htotal = 1366 + 20 + 70, |
952 | .vdisplay = 768, |
953 | .vsync_start = 768 + 14, |
954 | .vsync_end = 768 + 14 + 42, |
955 | .vtotal = 768 + 14 + 42, |
956 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
957 | }; |
958 | |
959 | static const struct panel_desc auo_b101xtn01 = { |
960 | .modes = &auo_b101xtn01_mode, |
961 | .num_modes = 1, |
962 | .bpc = 6, |
963 | .size = { |
964 | .width = 223, |
965 | .height = 125, |
966 | }, |
967 | }; |
968 | |
969 | static const struct drm_display_mode auo_b116xw03_mode = { |
970 | .clock = 70589, |
971 | .hdisplay = 1366, |
972 | .hsync_start = 1366 + 40, |
973 | .hsync_end = 1366 + 40 + 40, |
974 | .htotal = 1366 + 40 + 40 + 32, |
975 | .vdisplay = 768, |
976 | .vsync_start = 768 + 10, |
977 | .vsync_end = 768 + 10 + 12, |
978 | .vtotal = 768 + 10 + 12 + 6, |
979 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
980 | }; |
981 | |
982 | static const struct panel_desc auo_b116xw03 = { |
983 | .modes = &auo_b116xw03_mode, |
984 | .num_modes = 1, |
985 | .bpc = 6, |
986 | .size = { |
987 | .width = 256, |
988 | .height = 144, |
989 | }, |
990 | .delay = { |
991 | .prepare = 1, |
992 | .enable = 200, |
993 | .disable = 200, |
994 | .unprepare = 500, |
995 | }, |
996 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
997 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
998 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
999 | }; |
1000 | |
1001 | static const struct display_timing auo_g070vvn01_timings = { |
1002 | .pixelclock = { 33300000, 34209000, 45000000 }, |
1003 | .hactive = { 800, 800, 800 }, |
1004 | .hfront_porch = { 20, 40, 200 }, |
1005 | .hback_porch = { 87, 40, 1 }, |
1006 | .hsync_len = { 1, 48, 87 }, |
1007 | .vactive = { 480, 480, 480 }, |
1008 | .vfront_porch = { 5, 13, 200 }, |
1009 | .vback_porch = { 31, 31, 29 }, |
1010 | .vsync_len = { 1, 1, 3 }, |
1011 | }; |
1012 | |
1013 | static const struct panel_desc auo_g070vvn01 = { |
1014 | .timings = &auo_g070vvn01_timings, |
1015 | .num_timings = 1, |
1016 | .bpc = 8, |
1017 | .size = { |
1018 | .width = 152, |
1019 | .height = 91, |
1020 | }, |
1021 | .delay = { |
1022 | .prepare = 200, |
1023 | .enable = 50, |
1024 | .disable = 50, |
1025 | .unprepare = 1000, |
1026 | }, |
1027 | }; |
1028 | |
1029 | static const struct display_timing auo_g101evn010_timing = { |
1030 | .pixelclock = { 64000000, 68930000, 85000000 }, |
1031 | .hactive = { 1280, 1280, 1280 }, |
1032 | .hfront_porch = { 8, 64, 256 }, |
1033 | .hback_porch = { 8, 64, 256 }, |
1034 | .hsync_len = { 40, 168, 767 }, |
1035 | .vactive = { 800, 800, 800 }, |
1036 | .vfront_porch = { 4, 8, 100 }, |
1037 | .vback_porch = { 4, 8, 100 }, |
1038 | .vsync_len = { 8, 16, 223 }, |
1039 | }; |
1040 | |
1041 | static const struct panel_desc auo_g101evn010 = { |
1042 | .timings = &auo_g101evn010_timing, |
1043 | .num_timings = 1, |
1044 | .bpc = 6, |
1045 | .size = { |
1046 | .width = 216, |
1047 | .height = 135, |
1048 | }, |
1049 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
1050 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
1051 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1052 | }; |
1053 | |
1054 | static const struct drm_display_mode auo_g104sn02_mode = { |
1055 | .clock = 40000, |
1056 | .hdisplay = 800, |
1057 | .hsync_start = 800 + 40, |
1058 | .hsync_end = 800 + 40 + 216, |
1059 | .htotal = 800 + 40 + 216 + 128, |
1060 | .vdisplay = 600, |
1061 | .vsync_start = 600 + 10, |
1062 | .vsync_end = 600 + 10 + 35, |
1063 | .vtotal = 600 + 10 + 35 + 2, |
1064 | }; |
1065 | |
1066 | static const struct panel_desc auo_g104sn02 = { |
1067 | .modes = &auo_g104sn02_mode, |
1068 | .num_modes = 1, |
1069 | .bpc = 8, |
1070 | .size = { |
1071 | .width = 211, |
1072 | .height = 158, |
1073 | }, |
1074 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1075 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1076 | }; |
1077 | |
1078 | static const struct drm_display_mode auo_g104stn01_mode = { |
1079 | .clock = 40000, |
1080 | .hdisplay = 800, |
1081 | .hsync_start = 800 + 40, |
1082 | .hsync_end = 800 + 40 + 88, |
1083 | .htotal = 800 + 40 + 88 + 128, |
1084 | .vdisplay = 600, |
1085 | .vsync_start = 600 + 1, |
1086 | .vsync_end = 600 + 1 + 23, |
1087 | .vtotal = 600 + 1 + 23 + 4, |
1088 | }; |
1089 | |
1090 | static const struct panel_desc auo_g104stn01 = { |
1091 | .modes = &auo_g104stn01_mode, |
1092 | .num_modes = 1, |
1093 | .bpc = 8, |
1094 | .size = { |
1095 | .width = 211, |
1096 | .height = 158, |
1097 | }, |
1098 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1099 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1100 | }; |
1101 | |
1102 | static const struct display_timing auo_g121ean01_timing = { |
1103 | .pixelclock = { 60000000, 74400000, 90000000 }, |
1104 | .hactive = { 1280, 1280, 1280 }, |
1105 | .hfront_porch = { 20, 50, 100 }, |
1106 | .hback_porch = { 20, 50, 100 }, |
1107 | .hsync_len = { 30, 100, 200 }, |
1108 | .vactive = { 800, 800, 800 }, |
1109 | .vfront_porch = { 2, 10, 25 }, |
1110 | .vback_porch = { 2, 10, 25 }, |
1111 | .vsync_len = { 4, 18, 50 }, |
1112 | }; |
1113 | |
1114 | static const struct panel_desc auo_g121ean01 = { |
1115 | .timings = &auo_g121ean01_timing, |
1116 | .num_timings = 1, |
1117 | .bpc = 8, |
1118 | .size = { |
1119 | .width = 261, |
1120 | .height = 163, |
1121 | }, |
1122 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1123 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1124 | }; |
1125 | |
1126 | static const struct display_timing auo_g133han01_timings = { |
1127 | .pixelclock = { 134000000, 141200000, 149000000 }, |
1128 | .hactive = { 1920, 1920, 1920 }, |
1129 | .hfront_porch = { 39, 58, 77 }, |
1130 | .hback_porch = { 59, 88, 117 }, |
1131 | .hsync_len = { 28, 42, 56 }, |
1132 | .vactive = { 1080, 1080, 1080 }, |
1133 | .vfront_porch = { 3, 8, 11 }, |
1134 | .vback_porch = { 5, 14, 19 }, |
1135 | .vsync_len = { 4, 14, 19 }, |
1136 | }; |
1137 | |
1138 | static const struct panel_desc auo_g133han01 = { |
1139 | .timings = &auo_g133han01_timings, |
1140 | .num_timings = 1, |
1141 | .bpc = 8, |
1142 | .size = { |
1143 | .width = 293, |
1144 | .height = 165, |
1145 | }, |
1146 | .delay = { |
1147 | .prepare = 200, |
1148 | .enable = 50, |
1149 | .disable = 50, |
1150 | .unprepare = 1000, |
1151 | }, |
1152 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, |
1153 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1154 | }; |
1155 | |
1156 | static const struct display_timing auo_g156han04_timings = { |
1157 | .pixelclock = { 137000000, 141000000, 146000000 }, |
1158 | .hactive = { 1920, 1920, 1920 }, |
1159 | .hfront_porch = { 60, 60, 60 }, |
1160 | .hback_porch = { 90, 92, 111 }, |
1161 | .hsync_len = { 32, 32, 32 }, |
1162 | .vactive = { 1080, 1080, 1080 }, |
1163 | .vfront_porch = { 12, 12, 12 }, |
1164 | .vback_porch = { 24, 36, 56 }, |
1165 | .vsync_len = { 8, 8, 8 }, |
1166 | }; |
1167 | |
1168 | static const struct panel_desc auo_g156han04 = { |
1169 | .timings = &auo_g156han04_timings, |
1170 | .num_timings = 1, |
1171 | .bpc = 8, |
1172 | .size = { |
1173 | .width = 344, |
1174 | .height = 194, |
1175 | }, |
1176 | .delay = { |
1177 | .prepare = 50, /* T2 */ |
1178 | .enable = 200, /* T3 */ |
1179 | .disable = 110, /* T10 */ |
1180 | .unprepare = 1000, /* T13 */ |
1181 | }, |
1182 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1183 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
1184 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1185 | }; |
1186 | |
1187 | static const struct drm_display_mode auo_g156xtn01_mode = { |
1188 | .clock = 76000, |
1189 | .hdisplay = 1366, |
1190 | .hsync_start = 1366 + 33, |
1191 | .hsync_end = 1366 + 33 + 67, |
1192 | .htotal = 1560, |
1193 | .vdisplay = 768, |
1194 | .vsync_start = 768 + 4, |
1195 | .vsync_end = 768 + 4 + 4, |
1196 | .vtotal = 806, |
1197 | }; |
1198 | |
1199 | static const struct panel_desc auo_g156xtn01 = { |
1200 | .modes = &auo_g156xtn01_mode, |
1201 | .num_modes = 1, |
1202 | .bpc = 8, |
1203 | .size = { |
1204 | .width = 344, |
1205 | .height = 194, |
1206 | }, |
1207 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1208 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1209 | }; |
1210 | |
1211 | static const struct display_timing auo_g185han01_timings = { |
1212 | .pixelclock = { 120000000, 144000000, 175000000 }, |
1213 | .hactive = { 1920, 1920, 1920 }, |
1214 | .hfront_porch = { 36, 120, 148 }, |
1215 | .hback_porch = { 24, 88, 108 }, |
1216 | .hsync_len = { 20, 48, 64 }, |
1217 | .vactive = { 1080, 1080, 1080 }, |
1218 | .vfront_porch = { 6, 10, 40 }, |
1219 | .vback_porch = { 2, 5, 20 }, |
1220 | .vsync_len = { 2, 5, 20 }, |
1221 | }; |
1222 | |
1223 | static const struct panel_desc auo_g185han01 = { |
1224 | .timings = &auo_g185han01_timings, |
1225 | .num_timings = 1, |
1226 | .bpc = 8, |
1227 | .size = { |
1228 | .width = 409, |
1229 | .height = 230, |
1230 | }, |
1231 | .delay = { |
1232 | .prepare = 50, |
1233 | .enable = 200, |
1234 | .disable = 110, |
1235 | .unprepare = 1000, |
1236 | }, |
1237 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1238 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1239 | }; |
1240 | |
1241 | static const struct display_timing auo_g190ean01_timings = { |
1242 | .pixelclock = { 90000000, 108000000, 135000000 }, |
1243 | .hactive = { 1280, 1280, 1280 }, |
1244 | .hfront_porch = { 126, 184, 1266 }, |
1245 | .hback_porch = { 84, 122, 844 }, |
1246 | .hsync_len = { 70, 102, 704 }, |
1247 | .vactive = { 1024, 1024, 1024 }, |
1248 | .vfront_porch = { 4, 26, 76 }, |
1249 | .vback_porch = { 2, 8, 25 }, |
1250 | .vsync_len = { 2, 8, 25 }, |
1251 | }; |
1252 | |
1253 | static const struct panel_desc auo_g190ean01 = { |
1254 | .timings = &auo_g190ean01_timings, |
1255 | .num_timings = 1, |
1256 | .bpc = 8, |
1257 | .size = { |
1258 | .width = 376, |
1259 | .height = 301, |
1260 | }, |
1261 | .delay = { |
1262 | .prepare = 50, |
1263 | .enable = 200, |
1264 | .disable = 110, |
1265 | .unprepare = 1000, |
1266 | }, |
1267 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1268 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1269 | }; |
1270 | |
1271 | static const struct display_timing auo_p320hvn03_timings = { |
1272 | .pixelclock = { 106000000, 148500000, 164000000 }, |
1273 | .hactive = { 1920, 1920, 1920 }, |
1274 | .hfront_porch = { 25, 50, 130 }, |
1275 | .hback_porch = { 25, 50, 130 }, |
1276 | .hsync_len = { 20, 40, 105 }, |
1277 | .vactive = { 1080, 1080, 1080 }, |
1278 | .vfront_porch = { 8, 17, 150 }, |
1279 | .vback_porch = { 8, 17, 150 }, |
1280 | .vsync_len = { 4, 11, 100 }, |
1281 | }; |
1282 | |
1283 | static const struct panel_desc auo_p320hvn03 = { |
1284 | .timings = &auo_p320hvn03_timings, |
1285 | .num_timings = 1, |
1286 | .bpc = 8, |
1287 | .size = { |
1288 | .width = 698, |
1289 | .height = 393, |
1290 | }, |
1291 | .delay = { |
1292 | .prepare = 1, |
1293 | .enable = 450, |
1294 | .unprepare = 500, |
1295 | }, |
1296 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1297 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1298 | }; |
1299 | |
1300 | static const struct drm_display_mode auo_t215hvn01_mode = { |
1301 | .clock = 148800, |
1302 | .hdisplay = 1920, |
1303 | .hsync_start = 1920 + 88, |
1304 | .hsync_end = 1920 + 88 + 44, |
1305 | .htotal = 1920 + 88 + 44 + 148, |
1306 | .vdisplay = 1080, |
1307 | .vsync_start = 1080 + 4, |
1308 | .vsync_end = 1080 + 4 + 5, |
1309 | .vtotal = 1080 + 4 + 5 + 36, |
1310 | }; |
1311 | |
1312 | static const struct panel_desc auo_t215hvn01 = { |
1313 | .modes = &auo_t215hvn01_mode, |
1314 | .num_modes = 1, |
1315 | .bpc = 8, |
1316 | .size = { |
1317 | .width = 430, |
1318 | .height = 270, |
1319 | }, |
1320 | .delay = { |
1321 | .disable = 5, |
1322 | .unprepare = 1000, |
1323 | }, |
1324 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1325 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1326 | }; |
1327 | |
1328 | static const struct drm_display_mode avic_tm070ddh03_mode = { |
1329 | .clock = 51200, |
1330 | .hdisplay = 1024, |
1331 | .hsync_start = 1024 + 160, |
1332 | .hsync_end = 1024 + 160 + 4, |
1333 | .htotal = 1024 + 160 + 4 + 156, |
1334 | .vdisplay = 600, |
1335 | .vsync_start = 600 + 17, |
1336 | .vsync_end = 600 + 17 + 1, |
1337 | .vtotal = 600 + 17 + 1 + 17, |
1338 | }; |
1339 | |
1340 | static const struct panel_desc avic_tm070ddh03 = { |
1341 | .modes = &avic_tm070ddh03_mode, |
1342 | .num_modes = 1, |
1343 | .bpc = 8, |
1344 | .size = { |
1345 | .width = 154, |
1346 | .height = 90, |
1347 | }, |
1348 | .delay = { |
1349 | .prepare = 20, |
1350 | .enable = 200, |
1351 | .disable = 200, |
1352 | }, |
1353 | }; |
1354 | |
1355 | static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { |
1356 | .clock = 30000, |
1357 | .hdisplay = 800, |
1358 | .hsync_start = 800 + 40, |
1359 | .hsync_end = 800 + 40 + 48, |
1360 | .htotal = 800 + 40 + 48 + 40, |
1361 | .vdisplay = 480, |
1362 | .vsync_start = 480 + 13, |
1363 | .vsync_end = 480 + 13 + 3, |
1364 | .vtotal = 480 + 13 + 3 + 29, |
1365 | }; |
1366 | |
1367 | static const struct panel_desc bananapi_s070wv20_ct16 = { |
1368 | .modes = &bananapi_s070wv20_ct16_mode, |
1369 | .num_modes = 1, |
1370 | .bpc = 6, |
1371 | .size = { |
1372 | .width = 154, |
1373 | .height = 86, |
1374 | }, |
1375 | }; |
1376 | |
1377 | static const struct display_timing boe_av101hdt_a10_timing = { |
1378 | .pixelclock = { 74210000, 75330000, 76780000, }, |
1379 | .hactive = { 1280, 1280, 1280, }, |
1380 | .hfront_porch = { 10, 42, 33, }, |
1381 | .hback_porch = { 10, 18, 33, }, |
1382 | .hsync_len = { 30, 10, 30, }, |
1383 | .vactive = { 720, 720, 720, }, |
1384 | .vfront_porch = { 200, 183, 200, }, |
1385 | .vback_porch = { 8, 8, 8, }, |
1386 | .vsync_len = { 2, 19, 2, }, |
1387 | .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, |
1388 | }; |
1389 | |
1390 | static const struct panel_desc boe_av101hdt_a10 = { |
1391 | .timings = &boe_av101hdt_a10_timing, |
1392 | .num_timings = 1, |
1393 | .bpc = 8, |
1394 | .size = { |
1395 | .width = 224, |
1396 | .height = 126, |
1397 | }, |
1398 | .delay = { |
1399 | .enable = 50, |
1400 | .disable = 50, |
1401 | }, |
1402 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1403 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1404 | }; |
1405 | |
1406 | static const struct display_timing boe_av123z7m_n17_timing = { |
1407 | .pixelclock = { 86600000, 88000000, 90800000, }, |
1408 | .hactive = { 1920, 1920, 1920, }, |
1409 | .hfront_porch = { 10, 10, 10, }, |
1410 | .hback_porch = { 10, 10, 10, }, |
1411 | .hsync_len = { 9, 12, 25, }, |
1412 | .vactive = { 720, 720, 720, }, |
1413 | .vfront_porch = { 7, 10, 13, }, |
1414 | .vback_porch = { 7, 10, 13, }, |
1415 | .vsync_len = { 7, 11, 14, }, |
1416 | .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, |
1417 | }; |
1418 | |
1419 | static const struct panel_desc boe_av123z7m_n17 = { |
1420 | .timings = &boe_av123z7m_n17_timing, |
1421 | .bpc = 8, |
1422 | .num_timings = 1, |
1423 | .size = { |
1424 | .width = 292, |
1425 | .height = 110, |
1426 | }, |
1427 | .delay = { |
1428 | .prepare = 50, |
1429 | .disable = 50, |
1430 | }, |
1431 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1432 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1433 | }; |
1434 | |
1435 | static const struct drm_display_mode boe_bp101wx1_100_mode = { |
1436 | .clock = 78945, |
1437 | .hdisplay = 1280, |
1438 | .hsync_start = 1280 + 0, |
1439 | .hsync_end = 1280 + 0 + 2, |
1440 | .htotal = 1280 + 62 + 0 + 2, |
1441 | .vdisplay = 800, |
1442 | .vsync_start = 800 + 8, |
1443 | .vsync_end = 800 + 8 + 2, |
1444 | .vtotal = 800 + 6 + 8 + 2, |
1445 | }; |
1446 | |
1447 | static const struct panel_desc boe_bp082wx1_100 = { |
1448 | .modes = &boe_bp101wx1_100_mode, |
1449 | .num_modes = 1, |
1450 | .bpc = 8, |
1451 | .size = { |
1452 | .width = 177, |
1453 | .height = 110, |
1454 | }, |
1455 | .delay = { |
1456 | .enable = 50, |
1457 | .disable = 50, |
1458 | }, |
1459 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, |
1460 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
1461 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1462 | }; |
1463 | |
1464 | static const struct panel_desc boe_bp101wx1_100 = { |
1465 | .modes = &boe_bp101wx1_100_mode, |
1466 | .num_modes = 1, |
1467 | .bpc = 8, |
1468 | .size = { |
1469 | .width = 217, |
1470 | .height = 136, |
1471 | }, |
1472 | .delay = { |
1473 | .enable = 50, |
1474 | .disable = 50, |
1475 | }, |
1476 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, |
1477 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
1478 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1479 | }; |
1480 | |
1481 | static const struct display_timing boe_ev121wxm_n10_1850_timing = { |
1482 | .pixelclock = { 69922000, 71000000, 72293000 }, |
1483 | .hactive = { 1280, 1280, 1280 }, |
1484 | .hfront_porch = { 48, 48, 48 }, |
1485 | .hback_porch = { 80, 80, 80 }, |
1486 | .hsync_len = { 32, 32, 32 }, |
1487 | .vactive = { 800, 800, 800 }, |
1488 | .vfront_porch = { 3, 3, 3 }, |
1489 | .vback_porch = { 14, 14, 14 }, |
1490 | .vsync_len = { 6, 6, 6 }, |
1491 | }; |
1492 | |
1493 | static const struct panel_desc boe_ev121wxm_n10_1850 = { |
1494 | .timings = &boe_ev121wxm_n10_1850_timing, |
1495 | .num_timings = 1, |
1496 | .bpc = 8, |
1497 | .size = { |
1498 | .width = 261, |
1499 | .height = 163, |
1500 | }, |
1501 | .delay = { |
1502 | .prepare = 9, |
1503 | .enable = 300, |
1504 | .unprepare = 300, |
1505 | .disable = 560, |
1506 | }, |
1507 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1508 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
1509 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1510 | }; |
1511 | |
1512 | static const struct drm_display_mode boe_hv070wsa_mode = { |
1513 | .clock = 42105, |
1514 | .hdisplay = 1024, |
1515 | .hsync_start = 1024 + 30, |
1516 | .hsync_end = 1024 + 30 + 30, |
1517 | .htotal = 1024 + 30 + 30 + 30, |
1518 | .vdisplay = 600, |
1519 | .vsync_start = 600 + 10, |
1520 | .vsync_end = 600 + 10 + 10, |
1521 | .vtotal = 600 + 10 + 10 + 10, |
1522 | }; |
1523 | |
1524 | static const struct panel_desc boe_hv070wsa = { |
1525 | .modes = &boe_hv070wsa_mode, |
1526 | .num_modes = 1, |
1527 | .bpc = 8, |
1528 | .size = { |
1529 | .width = 154, |
1530 | .height = 90, |
1531 | }, |
1532 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1533 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
1534 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1535 | }; |
1536 | |
1537 | static const struct display_timing cct_cmt430b19n00_timing = { |
1538 | .pixelclock = { 8000000, 9000000, 12000000 }, |
1539 | .hactive = { 480, 480, 480 }, |
1540 | .hfront_porch = { 2, 8, 75 }, |
1541 | .hback_porch = { 3, 43, 43 }, |
1542 | .hsync_len = { 2, 4, 75 }, |
1543 | .vactive = { 272, 272, 272 }, |
1544 | .vfront_porch = { 2, 8, 37 }, |
1545 | .vback_porch = { 2, 12, 12 }, |
1546 | .vsync_len = { 2, 4, 37 }, |
1547 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1548 | }; |
1549 | |
1550 | static const struct panel_desc cct_cmt430b19n00 = { |
1551 | .timings = &cct_cmt430b19n00_timing, |
1552 | .num_timings = 1, |
1553 | .bpc = 8, |
1554 | .size = { |
1555 | .width = 95, |
1556 | .height = 53, |
1557 | }, |
1558 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
1559 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, |
1560 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
1561 | }; |
1562 | |
1563 | static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { |
1564 | .clock = 9000, |
1565 | .hdisplay = 480, |
1566 | .hsync_start = 480 + 5, |
1567 | .hsync_end = 480 + 5 + 5, |
1568 | .htotal = 480 + 5 + 5 + 40, |
1569 | .vdisplay = 272, |
1570 | .vsync_start = 272 + 8, |
1571 | .vsync_end = 272 + 8 + 8, |
1572 | .vtotal = 272 + 8 + 8 + 8, |
1573 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
1574 | }; |
1575 | |
1576 | static const struct panel_desc cdtech_s043wq26h_ct7 = { |
1577 | .modes = &cdtech_s043wq26h_ct7_mode, |
1578 | .num_modes = 1, |
1579 | .bpc = 8, |
1580 | .size = { |
1581 | .width = 95, |
1582 | .height = 54, |
1583 | }, |
1584 | .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
1585 | }; |
1586 | |
1587 | /* S070PWS19HP-FC21 2017/04/22 */ |
1588 | static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { |
1589 | .clock = 51200, |
1590 | .hdisplay = 1024, |
1591 | .hsync_start = 1024 + 160, |
1592 | .hsync_end = 1024 + 160 + 20, |
1593 | .htotal = 1024 + 160 + 20 + 140, |
1594 | .vdisplay = 600, |
1595 | .vsync_start = 600 + 12, |
1596 | .vsync_end = 600 + 12 + 3, |
1597 | .vtotal = 600 + 12 + 3 + 20, |
1598 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
1599 | }; |
1600 | |
1601 | static const struct panel_desc cdtech_s070pws19hp_fc21 = { |
1602 | .modes = &cdtech_s070pws19hp_fc21_mode, |
1603 | .num_modes = 1, |
1604 | .bpc = 6, |
1605 | .size = { |
1606 | .width = 154, |
1607 | .height = 86, |
1608 | }, |
1609 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
1610 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
1611 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
1612 | }; |
1613 | |
1614 | /* S070SWV29HG-DC44 2017/09/21 */ |
1615 | static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { |
1616 | .clock = 33300, |
1617 | .hdisplay = 800, |
1618 | .hsync_start = 800 + 210, |
1619 | .hsync_end = 800 + 210 + 2, |
1620 | .htotal = 800 + 210 + 2 + 44, |
1621 | .vdisplay = 480, |
1622 | .vsync_start = 480 + 22, |
1623 | .vsync_end = 480 + 22 + 2, |
1624 | .vtotal = 480 + 22 + 2 + 21, |
1625 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
1626 | }; |
1627 | |
1628 | static const struct panel_desc cdtech_s070swv29hg_dc44 = { |
1629 | .modes = &cdtech_s070swv29hg_dc44_mode, |
1630 | .num_modes = 1, |
1631 | .bpc = 6, |
1632 | .size = { |
1633 | .width = 154, |
1634 | .height = 86, |
1635 | }, |
1636 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
1637 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
1638 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
1639 | }; |
1640 | |
1641 | static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { |
1642 | .clock = 35000, |
1643 | .hdisplay = 800, |
1644 | .hsync_start = 800 + 40, |
1645 | .hsync_end = 800 + 40 + 40, |
1646 | .htotal = 800 + 40 + 40 + 48, |
1647 | .vdisplay = 480, |
1648 | .vsync_start = 480 + 29, |
1649 | .vsync_end = 480 + 29 + 13, |
1650 | .vtotal = 480 + 29 + 13 + 3, |
1651 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
1652 | }; |
1653 | |
1654 | static const struct panel_desc cdtech_s070wv95_ct16 = { |
1655 | .modes = &cdtech_s070wv95_ct16_mode, |
1656 | .num_modes = 1, |
1657 | .bpc = 8, |
1658 | .size = { |
1659 | .width = 154, |
1660 | .height = 85, |
1661 | }, |
1662 | }; |
1663 | |
1664 | static const struct display_timing chefree_ch101olhlwh_002_timing = { |
1665 | .pixelclock = { 68900000, 71100000, 73400000 }, |
1666 | .hactive = { 1280, 1280, 1280 }, |
1667 | .hfront_porch = { 65, 80, 95 }, |
1668 | .hback_porch = { 64, 79, 94 }, |
1669 | .hsync_len = { 1, 1, 1 }, |
1670 | .vactive = { 800, 800, 800 }, |
1671 | .vfront_porch = { 7, 11, 14 }, |
1672 | .vback_porch = { 7, 11, 14 }, |
1673 | .vsync_len = { 1, 1, 1 }, |
1674 | .flags = DISPLAY_FLAGS_DE_HIGH, |
1675 | }; |
1676 | |
1677 | static const struct panel_desc chefree_ch101olhlwh_002 = { |
1678 | .timings = &chefree_ch101olhlwh_002_timing, |
1679 | .num_timings = 1, |
1680 | .bpc = 8, |
1681 | .size = { |
1682 | .width = 217, |
1683 | .height = 135, |
1684 | }, |
1685 | .delay = { |
1686 | .enable = 200, |
1687 | .disable = 200, |
1688 | }, |
1689 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
1690 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1691 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1692 | }; |
1693 | |
1694 | static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { |
1695 | .clock = 66770, |
1696 | .hdisplay = 800, |
1697 | .hsync_start = 800 + 49, |
1698 | .hsync_end = 800 + 49 + 33, |
1699 | .htotal = 800 + 49 + 33 + 17, |
1700 | .vdisplay = 1280, |
1701 | .vsync_start = 1280 + 1, |
1702 | .vsync_end = 1280 + 1 + 7, |
1703 | .vtotal = 1280 + 1 + 7 + 15, |
1704 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
1705 | }; |
1706 | |
1707 | static const struct panel_desc chunghwa_claa070wp03xg = { |
1708 | .modes = &chunghwa_claa070wp03xg_mode, |
1709 | .num_modes = 1, |
1710 | .bpc = 6, |
1711 | .size = { |
1712 | .width = 94, |
1713 | .height = 150, |
1714 | }, |
1715 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
1716 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
1717 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1718 | }; |
1719 | |
1720 | static const struct drm_display_mode chunghwa_claa101wa01a_mode = { |
1721 | .clock = 72070, |
1722 | .hdisplay = 1366, |
1723 | .hsync_start = 1366 + 58, |
1724 | .hsync_end = 1366 + 58 + 58, |
1725 | .htotal = 1366 + 58 + 58 + 58, |
1726 | .vdisplay = 768, |
1727 | .vsync_start = 768 + 4, |
1728 | .vsync_end = 768 + 4 + 4, |
1729 | .vtotal = 768 + 4 + 4 + 4, |
1730 | }; |
1731 | |
1732 | static const struct panel_desc chunghwa_claa101wa01a = { |
1733 | .modes = &chunghwa_claa101wa01a_mode, |
1734 | .num_modes = 1, |
1735 | .bpc = 6, |
1736 | .size = { |
1737 | .width = 220, |
1738 | .height = 120, |
1739 | }, |
1740 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
1741 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
1742 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1743 | }; |
1744 | |
1745 | static const struct drm_display_mode chunghwa_claa101wb01_mode = { |
1746 | .clock = 69300, |
1747 | .hdisplay = 1366, |
1748 | .hsync_start = 1366 + 48, |
1749 | .hsync_end = 1366 + 48 + 32, |
1750 | .htotal = 1366 + 48 + 32 + 20, |
1751 | .vdisplay = 768, |
1752 | .vsync_start = 768 + 16, |
1753 | .vsync_end = 768 + 16 + 8, |
1754 | .vtotal = 768 + 16 + 8 + 16, |
1755 | }; |
1756 | |
1757 | static const struct panel_desc chunghwa_claa101wb01 = { |
1758 | .modes = &chunghwa_claa101wb01_mode, |
1759 | .num_modes = 1, |
1760 | .bpc = 6, |
1761 | .size = { |
1762 | .width = 223, |
1763 | .height = 125, |
1764 | }, |
1765 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
1766 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
1767 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1768 | }; |
1769 | |
1770 | static const struct display_timing dataimage_fg040346dsswbg04_timing = { |
1771 | .pixelclock = { 5000000, 9000000, 12000000 }, |
1772 | .hactive = { 480, 480, 480 }, |
1773 | .hfront_porch = { 12, 12, 12 }, |
1774 | .hback_porch = { 12, 12, 12 }, |
1775 | .hsync_len = { 21, 21, 21 }, |
1776 | .vactive = { 272, 272, 272 }, |
1777 | .vfront_porch = { 4, 4, 4 }, |
1778 | .vback_porch = { 4, 4, 4 }, |
1779 | .vsync_len = { 8, 8, 8 }, |
1780 | }; |
1781 | |
1782 | static const struct panel_desc dataimage_fg040346dsswbg04 = { |
1783 | .timings = &dataimage_fg040346dsswbg04_timing, |
1784 | .num_timings = 1, |
1785 | .bpc = 8, |
1786 | .size = { |
1787 | .width = 95, |
1788 | .height = 54, |
1789 | }, |
1790 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
1791 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
1792 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
1793 | }; |
1794 | |
1795 | static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { |
1796 | .pixelclock = { 68900000, 71110000, 73400000 }, |
1797 | .hactive = { 1280, 1280, 1280 }, |
1798 | .vactive = { 800, 800, 800 }, |
1799 | .hback_porch = { 100, 100, 100 }, |
1800 | .hfront_porch = { 100, 100, 100 }, |
1801 | .vback_porch = { 5, 5, 5 }, |
1802 | .vfront_porch = { 5, 5, 5 }, |
1803 | .hsync_len = { 24, 24, 24 }, |
1804 | .vsync_len = { 3, 3, 3 }, |
1805 | .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | |
1806 | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, |
1807 | }; |
1808 | |
1809 | static const struct panel_desc dataimage_fg1001l0dsswmg01 = { |
1810 | .timings = &dataimage_fg1001l0dsswmg01_timing, |
1811 | .num_timings = 1, |
1812 | .bpc = 8, |
1813 | .size = { |
1814 | .width = 217, |
1815 | .height = 136, |
1816 | }, |
1817 | }; |
1818 | |
1819 | static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { |
1820 | .clock = 33260, |
1821 | .hdisplay = 800, |
1822 | .hsync_start = 800 + 40, |
1823 | .hsync_end = 800 + 40 + 128, |
1824 | .htotal = 800 + 40 + 128 + 88, |
1825 | .vdisplay = 480, |
1826 | .vsync_start = 480 + 10, |
1827 | .vsync_end = 480 + 10 + 2, |
1828 | .vtotal = 480 + 10 + 2 + 33, |
1829 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
1830 | }; |
1831 | |
1832 | static const struct panel_desc dataimage_scf0700c48ggu18 = { |
1833 | .modes = &dataimage_scf0700c48ggu18_mode, |
1834 | .num_modes = 1, |
1835 | .bpc = 8, |
1836 | .size = { |
1837 | .width = 152, |
1838 | .height = 91, |
1839 | }, |
1840 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
1841 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
1842 | }; |
1843 | |
1844 | static const struct display_timing dlc_dlc0700yzg_1_timing = { |
1845 | .pixelclock = { 45000000, 51200000, 57000000 }, |
1846 | .hactive = { 1024, 1024, 1024 }, |
1847 | .hfront_porch = { 100, 106, 113 }, |
1848 | .hback_porch = { 100, 106, 113 }, |
1849 | .hsync_len = { 100, 108, 114 }, |
1850 | .vactive = { 600, 600, 600 }, |
1851 | .vfront_porch = { 8, 11, 15 }, |
1852 | .vback_porch = { 8, 11, 15 }, |
1853 | .vsync_len = { 9, 13, 15 }, |
1854 | .flags = DISPLAY_FLAGS_DE_HIGH, |
1855 | }; |
1856 | |
1857 | static const struct panel_desc dlc_dlc0700yzg_1 = { |
1858 | .timings = &dlc_dlc0700yzg_1_timing, |
1859 | .num_timings = 1, |
1860 | .bpc = 6, |
1861 | .size = { |
1862 | .width = 154, |
1863 | .height = 86, |
1864 | }, |
1865 | .delay = { |
1866 | .prepare = 30, |
1867 | .enable = 200, |
1868 | .disable = 200, |
1869 | }, |
1870 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
1871 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1872 | }; |
1873 | |
1874 | static const struct display_timing dlc_dlc1010gig_timing = { |
1875 | .pixelclock = { 68900000, 71100000, 73400000 }, |
1876 | .hactive = { 1280, 1280, 1280 }, |
1877 | .hfront_porch = { 43, 53, 63 }, |
1878 | .hback_porch = { 43, 53, 63 }, |
1879 | .hsync_len = { 44, 54, 64 }, |
1880 | .vactive = { 800, 800, 800 }, |
1881 | .vfront_porch = { 5, 8, 11 }, |
1882 | .vback_porch = { 5, 8, 11 }, |
1883 | .vsync_len = { 5, 7, 11 }, |
1884 | .flags = DISPLAY_FLAGS_DE_HIGH, |
1885 | }; |
1886 | |
1887 | static const struct panel_desc dlc_dlc1010gig = { |
1888 | .timings = &dlc_dlc1010gig_timing, |
1889 | .num_timings = 1, |
1890 | .bpc = 8, |
1891 | .size = { |
1892 | .width = 216, |
1893 | .height = 135, |
1894 | }, |
1895 | .delay = { |
1896 | .prepare = 60, |
1897 | .enable = 150, |
1898 | .disable = 100, |
1899 | .unprepare = 60, |
1900 | }, |
1901 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1902 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1903 | }; |
1904 | |
1905 | static const struct drm_display_mode edt_et035012dm6_mode = { |
1906 | .clock = 6500, |
1907 | .hdisplay = 320, |
1908 | .hsync_start = 320 + 20, |
1909 | .hsync_end = 320 + 20 + 30, |
1910 | .htotal = 320 + 20 + 68, |
1911 | .vdisplay = 240, |
1912 | .vsync_start = 240 + 4, |
1913 | .vsync_end = 240 + 4 + 4, |
1914 | .vtotal = 240 + 4 + 4 + 14, |
1915 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
1916 | }; |
1917 | |
1918 | static const struct panel_desc edt_et035012dm6 = { |
1919 | .modes = &edt_et035012dm6_mode, |
1920 | .num_modes = 1, |
1921 | .bpc = 8, |
1922 | .size = { |
1923 | .width = 70, |
1924 | .height = 52, |
1925 | }, |
1926 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
1927 | .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, |
1928 | }; |
1929 | |
1930 | static const struct drm_display_mode edt_etm0350g0dh6_mode = { |
1931 | .clock = 6520, |
1932 | .hdisplay = 320, |
1933 | .hsync_start = 320 + 20, |
1934 | .hsync_end = 320 + 20 + 68, |
1935 | .htotal = 320 + 20 + 68, |
1936 | .vdisplay = 240, |
1937 | .vsync_start = 240 + 4, |
1938 | .vsync_end = 240 + 4 + 18, |
1939 | .vtotal = 240 + 4 + 18, |
1940 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
1941 | }; |
1942 | |
1943 | static const struct panel_desc edt_etm0350g0dh6 = { |
1944 | .modes = &edt_etm0350g0dh6_mode, |
1945 | .num_modes = 1, |
1946 | .bpc = 6, |
1947 | .size = { |
1948 | .width = 70, |
1949 | .height = 53, |
1950 | }, |
1951 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
1952 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, |
1953 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
1954 | }; |
1955 | |
1956 | static const struct drm_display_mode edt_etm043080dh6gp_mode = { |
1957 | .clock = 10870, |
1958 | .hdisplay = 480, |
1959 | .hsync_start = 480 + 8, |
1960 | .hsync_end = 480 + 8 + 4, |
1961 | .htotal = 480 + 8 + 4 + 41, |
1962 | |
1963 | /* |
1964 | * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while |
1965 | * fb_align |
1966 | */ |
1967 | |
1968 | .vdisplay = 288, |
1969 | .vsync_start = 288 + 2, |
1970 | .vsync_end = 288 + 2 + 4, |
1971 | .vtotal = 288 + 2 + 4 + 10, |
1972 | }; |
1973 | |
1974 | static const struct panel_desc edt_etm043080dh6gp = { |
1975 | .modes = &edt_etm043080dh6gp_mode, |
1976 | .num_modes = 1, |
1977 | .bpc = 8, |
1978 | .size = { |
1979 | .width = 100, |
1980 | .height = 65, |
1981 | }, |
1982 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
1983 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
1984 | }; |
1985 | |
1986 | static const struct drm_display_mode edt_etm0430g0dh6_mode = { |
1987 | .clock = 9000, |
1988 | .hdisplay = 480, |
1989 | .hsync_start = 480 + 2, |
1990 | .hsync_end = 480 + 2 + 41, |
1991 | .htotal = 480 + 2 + 41 + 2, |
1992 | .vdisplay = 272, |
1993 | .vsync_start = 272 + 2, |
1994 | .vsync_end = 272 + 2 + 10, |
1995 | .vtotal = 272 + 2 + 10 + 2, |
1996 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
1997 | }; |
1998 | |
1999 | static const struct panel_desc edt_etm0430g0dh6 = { |
2000 | .modes = &edt_etm0430g0dh6_mode, |
2001 | .num_modes = 1, |
2002 | .bpc = 6, |
2003 | .size = { |
2004 | .width = 95, |
2005 | .height = 54, |
2006 | }, |
2007 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
2008 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, |
2009 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
2010 | }; |
2011 | |
2012 | static const struct drm_display_mode edt_et057090dhu_mode = { |
2013 | .clock = 25175, |
2014 | .hdisplay = 640, |
2015 | .hsync_start = 640 + 16, |
2016 | .hsync_end = 640 + 16 + 30, |
2017 | .htotal = 640 + 16 + 30 + 114, |
2018 | .vdisplay = 480, |
2019 | .vsync_start = 480 + 10, |
2020 | .vsync_end = 480 + 10 + 3, |
2021 | .vtotal = 480 + 10 + 3 + 32, |
2022 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
2023 | }; |
2024 | |
2025 | static const struct panel_desc edt_et057090dhu = { |
2026 | .modes = &edt_et057090dhu_mode, |
2027 | .num_modes = 1, |
2028 | .bpc = 6, |
2029 | .size = { |
2030 | .width = 115, |
2031 | .height = 86, |
2032 | }, |
2033 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
2034 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, |
2035 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
2036 | }; |
2037 | |
2038 | static const struct drm_display_mode edt_etm0700g0dh6_mode = { |
2039 | .clock = 33260, |
2040 | .hdisplay = 800, |
2041 | .hsync_start = 800 + 40, |
2042 | .hsync_end = 800 + 40 + 128, |
2043 | .htotal = 800 + 40 + 128 + 88, |
2044 | .vdisplay = 480, |
2045 | .vsync_start = 480 + 10, |
2046 | .vsync_end = 480 + 10 + 2, |
2047 | .vtotal = 480 + 10 + 2 + 33, |
2048 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
2049 | }; |
2050 | |
2051 | static const struct panel_desc edt_etm0700g0dh6 = { |
2052 | .modes = &edt_etm0700g0dh6_mode, |
2053 | .num_modes = 1, |
2054 | .bpc = 6, |
2055 | .size = { |
2056 | .width = 152, |
2057 | .height = 91, |
2058 | }, |
2059 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
2060 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, |
2061 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
2062 | }; |
2063 | |
2064 | static const struct panel_desc edt_etm0700g0bdh6 = { |
2065 | .modes = &edt_etm0700g0dh6_mode, |
2066 | .num_modes = 1, |
2067 | .bpc = 6, |
2068 | .size = { |
2069 | .width = 152, |
2070 | .height = 91, |
2071 | }, |
2072 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
2073 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
2074 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
2075 | }; |
2076 | |
2077 | static const struct display_timing edt_etml0700y5dha_timing = { |
2078 | .pixelclock = { 40800000, 51200000, 67200000 }, |
2079 | .hactive = { 1024, 1024, 1024 }, |
2080 | .hfront_porch = { 30, 106, 125 }, |
2081 | .hback_porch = { 30, 106, 125 }, |
2082 | .hsync_len = { 30, 108, 126 }, |
2083 | .vactive = { 600, 600, 600 }, |
2084 | .vfront_porch = { 3, 12, 67}, |
2085 | .vback_porch = { 3, 12, 67 }, |
2086 | .vsync_len = { 4, 11, 66 }, |
2087 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
2088 | DISPLAY_FLAGS_DE_HIGH, |
2089 | }; |
2090 | |
2091 | static const struct panel_desc edt_etml0700y5dha = { |
2092 | .timings = &edt_etml0700y5dha_timing, |
2093 | .num_timings = 1, |
2094 | .bpc = 8, |
2095 | .size = { |
2096 | .width = 155, |
2097 | .height = 86, |
2098 | }, |
2099 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
2100 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2101 | }; |
2102 | |
2103 | static const struct display_timing edt_etml1010g3dra_timing = { |
2104 | .pixelclock = { 66300000, 72400000, 78900000 }, |
2105 | .hactive = { 1280, 1280, 1280 }, |
2106 | .hfront_porch = { 12, 72, 132 }, |
2107 | .hback_porch = { 86, 86, 86 }, |
2108 | .hsync_len = { 2, 2, 2 }, |
2109 | .vactive = { 800, 800, 800 }, |
2110 | .vfront_porch = { 1, 15, 49 }, |
2111 | .vback_porch = { 21, 21, 21 }, |
2112 | .vsync_len = { 2, 2, 2 }, |
2113 | .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | |
2114 | DISPLAY_FLAGS_DE_HIGH, |
2115 | }; |
2116 | |
2117 | static const struct panel_desc edt_etml1010g3dra = { |
2118 | .timings = &edt_etml1010g3dra_timing, |
2119 | .num_timings = 1, |
2120 | .bpc = 8, |
2121 | .size = { |
2122 | .width = 216, |
2123 | .height = 135, |
2124 | }, |
2125 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
2126 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
2127 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2128 | }; |
2129 | |
2130 | static const struct drm_display_mode edt_etmv570g2dhu_mode = { |
2131 | .clock = 25175, |
2132 | .hdisplay = 640, |
2133 | .hsync_start = 640, |
2134 | .hsync_end = 640 + 16, |
2135 | .htotal = 640 + 16 + 30 + 114, |
2136 | .vdisplay = 480, |
2137 | .vsync_start = 480 + 10, |
2138 | .vsync_end = 480 + 10 + 3, |
2139 | .vtotal = 480 + 10 + 3 + 35, |
2140 | .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, |
2141 | }; |
2142 | |
2143 | static const struct panel_desc edt_etmv570g2dhu = { |
2144 | .modes = &edt_etmv570g2dhu_mode, |
2145 | .num_modes = 1, |
2146 | .bpc = 6, |
2147 | .size = { |
2148 | .width = 115, |
2149 | .height = 86, |
2150 | }, |
2151 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
2152 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, |
2153 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
2154 | }; |
2155 | |
2156 | static const struct display_timing eink_vb3300_kca_timing = { |
2157 | .pixelclock = { 40000000, 40000000, 40000000 }, |
2158 | .hactive = { 334, 334, 334 }, |
2159 | .hfront_porch = { 1, 1, 1 }, |
2160 | .hback_porch = { 1, 1, 1 }, |
2161 | .hsync_len = { 1, 1, 1 }, |
2162 | .vactive = { 1405, 1405, 1405 }, |
2163 | .vfront_porch = { 1, 1, 1 }, |
2164 | .vback_porch = { 1, 1, 1 }, |
2165 | .vsync_len = { 1, 1, 1 }, |
2166 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
2167 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, |
2168 | }; |
2169 | |
2170 | static const struct panel_desc eink_vb3300_kca = { |
2171 | .timings = &eink_vb3300_kca_timing, |
2172 | .num_timings = 1, |
2173 | .bpc = 6, |
2174 | .size = { |
2175 | .width = 157, |
2176 | .height = 209, |
2177 | }, |
2178 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
2179 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
2180 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
2181 | }; |
2182 | |
2183 | static const struct display_timing evervision_vgg644804_timing = { |
2184 | .pixelclock = { 25175000, 25175000, 25175000 }, |
2185 | .hactive = { 640, 640, 640 }, |
2186 | .hfront_porch = { 16, 16, 16 }, |
2187 | .hback_porch = { 82, 114, 170 }, |
2188 | .hsync_len = { 5, 30, 30 }, |
2189 | .vactive = { 480, 480, 480 }, |
2190 | .vfront_porch = { 10, 10, 10 }, |
2191 | .vback_porch = { 30, 32, 34 }, |
2192 | .vsync_len = { 1, 3, 5 }, |
2193 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
2194 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | |
2195 | DISPLAY_FLAGS_SYNC_POSEDGE, |
2196 | }; |
2197 | |
2198 | static const struct panel_desc evervision_vgg644804 = { |
2199 | .timings = &evervision_vgg644804_timing, |
2200 | .num_timings = 1, |
2201 | .bpc = 6, |
2202 | .size = { |
2203 | .width = 115, |
2204 | .height = 86, |
2205 | }, |
2206 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
2207 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
2208 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2209 | }; |
2210 | |
2211 | static const struct display_timing evervision_vgg804821_timing = { |
2212 | .pixelclock = { 27600000, 33300000, 50000000 }, |
2213 | .hactive = { 800, 800, 800 }, |
2214 | .hfront_porch = { 40, 66, 70 }, |
2215 | .hback_porch = { 40, 67, 70 }, |
2216 | .hsync_len = { 40, 67, 70 }, |
2217 | .vactive = { 480, 480, 480 }, |
2218 | .vfront_porch = { 6, 10, 10 }, |
2219 | .vback_porch = { 7, 11, 11 }, |
2220 | .vsync_len = { 7, 11, 11 }, |
2221 | .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | |
2222 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | |
2223 | DISPLAY_FLAGS_SYNC_NEGEDGE, |
2224 | }; |
2225 | |
2226 | static const struct panel_desc evervision_vgg804821 = { |
2227 | .timings = &evervision_vgg804821_timing, |
2228 | .num_timings = 1, |
2229 | .bpc = 8, |
2230 | .size = { |
2231 | .width = 108, |
2232 | .height = 64, |
2233 | }, |
2234 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
2235 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, |
2236 | }; |
2237 | |
2238 | static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { |
2239 | .clock = 32260, |
2240 | .hdisplay = 800, |
2241 | .hsync_start = 800 + 168, |
2242 | .hsync_end = 800 + 168 + 64, |
2243 | .htotal = 800 + 168 + 64 + 88, |
2244 | .vdisplay = 480, |
2245 | .vsync_start = 480 + 37, |
2246 | .vsync_end = 480 + 37 + 2, |
2247 | .vtotal = 480 + 37 + 2 + 8, |
2248 | }; |
2249 | |
2250 | static const struct panel_desc foxlink_fl500wvr00_a0t = { |
2251 | .modes = &foxlink_fl500wvr00_a0t_mode, |
2252 | .num_modes = 1, |
2253 | .bpc = 8, |
2254 | .size = { |
2255 | .width = 108, |
2256 | .height = 65, |
2257 | }, |
2258 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
2259 | }; |
2260 | |
2261 | static const struct drm_display_mode frida_frd350h54004_modes[] = { |
2262 | { /* 60 Hz */ |
2263 | .clock = 6000, |
2264 | .hdisplay = 320, |
2265 | .hsync_start = 320 + 44, |
2266 | .hsync_end = 320 + 44 + 16, |
2267 | .htotal = 320 + 44 + 16 + 20, |
2268 | .vdisplay = 240, |
2269 | .vsync_start = 240 + 2, |
2270 | .vsync_end = 240 + 2 + 6, |
2271 | .vtotal = 240 + 2 + 6 + 2, |
2272 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
2273 | }, |
2274 | { /* 50 Hz */ |
2275 | .clock = 5400, |
2276 | .hdisplay = 320, |
2277 | .hsync_start = 320 + 56, |
2278 | .hsync_end = 320 + 56 + 16, |
2279 | .htotal = 320 + 56 + 16 + 40, |
2280 | .vdisplay = 240, |
2281 | .vsync_start = 240 + 2, |
2282 | .vsync_end = 240 + 2 + 6, |
2283 | .vtotal = 240 + 2 + 6 + 2, |
2284 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
2285 | }, |
2286 | }; |
2287 | |
2288 | static const struct panel_desc frida_frd350h54004 = { |
2289 | .modes = frida_frd350h54004_modes, |
2290 | .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), |
2291 | .bpc = 8, |
2292 | .size = { |
2293 | .width = 77, |
2294 | .height = 64, |
2295 | }, |
2296 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
2297 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
2298 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
2299 | }; |
2300 | |
2301 | static const struct drm_display_mode friendlyarm_hd702e_mode = { |
2302 | .clock = 67185, |
2303 | .hdisplay = 800, |
2304 | .hsync_start = 800 + 20, |
2305 | .hsync_end = 800 + 20 + 24, |
2306 | .htotal = 800 + 20 + 24 + 20, |
2307 | .vdisplay = 1280, |
2308 | .vsync_start = 1280 + 4, |
2309 | .vsync_end = 1280 + 4 + 8, |
2310 | .vtotal = 1280 + 4 + 8 + 4, |
2311 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
2312 | }; |
2313 | |
2314 | static const struct panel_desc friendlyarm_hd702e = { |
2315 | .modes = &friendlyarm_hd702e_mode, |
2316 | .num_modes = 1, |
2317 | .size = { |
2318 | .width = 94, |
2319 | .height = 151, |
2320 | }, |
2321 | }; |
2322 | |
2323 | static const struct drm_display_mode giantplus_gpg482739qs5_mode = { |
2324 | .clock = 9000, |
2325 | .hdisplay = 480, |
2326 | .hsync_start = 480 + 5, |
2327 | .hsync_end = 480 + 5 + 1, |
2328 | .htotal = 480 + 5 + 1 + 40, |
2329 | .vdisplay = 272, |
2330 | .vsync_start = 272 + 8, |
2331 | .vsync_end = 272 + 8 + 1, |
2332 | .vtotal = 272 + 8 + 1 + 8, |
2333 | }; |
2334 | |
2335 | static const struct panel_desc giantplus_gpg482739qs5 = { |
2336 | .modes = &giantplus_gpg482739qs5_mode, |
2337 | .num_modes = 1, |
2338 | .bpc = 8, |
2339 | .size = { |
2340 | .width = 95, |
2341 | .height = 54, |
2342 | }, |
2343 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
2344 | }; |
2345 | |
2346 | static const struct display_timing giantplus_gpm940b0_timing = { |
2347 | .pixelclock = { 13500000, 27000000, 27500000 }, |
2348 | .hactive = { 320, 320, 320 }, |
2349 | .hfront_porch = { 14, 686, 718 }, |
2350 | .hback_porch = { 50, 70, 255 }, |
2351 | .hsync_len = { 1, 1, 1 }, |
2352 | .vactive = { 240, 240, 240 }, |
2353 | .vfront_porch = { 1, 1, 179 }, |
2354 | .vback_porch = { 1, 21, 31 }, |
2355 | .vsync_len = { 1, 1, 6 }, |
2356 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, |
2357 | }; |
2358 | |
2359 | static const struct panel_desc giantplus_gpm940b0 = { |
2360 | .timings = &giantplus_gpm940b0_timing, |
2361 | .num_timings = 1, |
2362 | .bpc = 8, |
2363 | .size = { |
2364 | .width = 60, |
2365 | .height = 45, |
2366 | }, |
2367 | .bus_format = MEDIA_BUS_FMT_RGB888_3X8, |
2368 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, |
2369 | }; |
2370 | |
2371 | static const struct display_timing hannstar_hsd070pww1_timing = { |
2372 | .pixelclock = { 64300000, 71100000, 82000000 }, |
2373 | .hactive = { 1280, 1280, 1280 }, |
2374 | .hfront_porch = { 1, 1, 10 }, |
2375 | .hback_porch = { 1, 1, 10 }, |
2376 | /* |
2377 | * According to the data sheet, the minimum horizontal blanking interval |
2378 | * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the |
2379 | * minimum working horizontal blanking interval to be 60 clocks. |
2380 | */ |
2381 | .hsync_len = { 58, 158, 661 }, |
2382 | .vactive = { 800, 800, 800 }, |
2383 | .vfront_porch = { 1, 1, 10 }, |
2384 | .vback_porch = { 1, 1, 10 }, |
2385 | .vsync_len = { 1, 21, 203 }, |
2386 | .flags = DISPLAY_FLAGS_DE_HIGH, |
2387 | }; |
2388 | |
2389 | static const struct panel_desc hannstar_hsd070pww1 = { |
2390 | .timings = &hannstar_hsd070pww1_timing, |
2391 | .num_timings = 1, |
2392 | .bpc = 6, |
2393 | .size = { |
2394 | .width = 151, |
2395 | .height = 94, |
2396 | }, |
2397 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
2398 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2399 | }; |
2400 | |
2401 | static const struct display_timing hannstar_hsd100pxn1_timing = { |
2402 | .pixelclock = { 55000000, 65000000, 75000000 }, |
2403 | .hactive = { 1024, 1024, 1024 }, |
2404 | .hfront_porch = { 40, 40, 40 }, |
2405 | .hback_porch = { 220, 220, 220 }, |
2406 | .hsync_len = { 20, 60, 100 }, |
2407 | .vactive = { 768, 768, 768 }, |
2408 | .vfront_porch = { 7, 7, 7 }, |
2409 | .vback_porch = { 21, 21, 21 }, |
2410 | .vsync_len = { 10, 10, 10 }, |
2411 | .flags = DISPLAY_FLAGS_DE_HIGH, |
2412 | }; |
2413 | |
2414 | static const struct panel_desc hannstar_hsd100pxn1 = { |
2415 | .timings = &hannstar_hsd100pxn1_timing, |
2416 | .num_timings = 1, |
2417 | .bpc = 6, |
2418 | .size = { |
2419 | .width = 203, |
2420 | .height = 152, |
2421 | }, |
2422 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
2423 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2424 | }; |
2425 | |
2426 | static const struct display_timing hannstar_hsd101pww2_timing = { |
2427 | .pixelclock = { 64300000, 71100000, 82000000 }, |
2428 | .hactive = { 1280, 1280, 1280 }, |
2429 | .hfront_porch = { 1, 1, 10 }, |
2430 | .hback_porch = { 1, 1, 10 }, |
2431 | .hsync_len = { 58, 158, 661 }, |
2432 | .vactive = { 800, 800, 800 }, |
2433 | .vfront_porch = { 1, 1, 10 }, |
2434 | .vback_porch = { 1, 1, 10 }, |
2435 | .vsync_len = { 1, 21, 203 }, |
2436 | .flags = DISPLAY_FLAGS_DE_HIGH, |
2437 | }; |
2438 | |
2439 | static const struct panel_desc hannstar_hsd101pww2 = { |
2440 | .timings = &hannstar_hsd101pww2_timing, |
2441 | .num_timings = 1, |
2442 | .bpc = 8, |
2443 | .size = { |
2444 | .width = 217, |
2445 | .height = 136, |
2446 | }, |
2447 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
2448 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2449 | }; |
2450 | |
2451 | static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { |
2452 | .clock = 33333, |
2453 | .hdisplay = 800, |
2454 | .hsync_start = 800 + 85, |
2455 | .hsync_end = 800 + 85 + 86, |
2456 | .htotal = 800 + 85 + 86 + 85, |
2457 | .vdisplay = 480, |
2458 | .vsync_start = 480 + 16, |
2459 | .vsync_end = 480 + 16 + 13, |
2460 | .vtotal = 480 + 16 + 13 + 16, |
2461 | }; |
2462 | |
2463 | static const struct panel_desc hitachi_tx23d38vm0caa = { |
2464 | .modes = &hitachi_tx23d38vm0caa_mode, |
2465 | .num_modes = 1, |
2466 | .bpc = 6, |
2467 | .size = { |
2468 | .width = 195, |
2469 | .height = 117, |
2470 | }, |
2471 | .delay = { |
2472 | .enable = 160, |
2473 | .disable = 160, |
2474 | }, |
2475 | }; |
2476 | |
2477 | static const struct drm_display_mode innolux_at043tn24_mode = { |
2478 | .clock = 9000, |
2479 | .hdisplay = 480, |
2480 | .hsync_start = 480 + 2, |
2481 | .hsync_end = 480 + 2 + 41, |
2482 | .htotal = 480 + 2 + 41 + 2, |
2483 | .vdisplay = 272, |
2484 | .vsync_start = 272 + 2, |
2485 | .vsync_end = 272 + 2 + 10, |
2486 | .vtotal = 272 + 2 + 10 + 2, |
2487 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
2488 | }; |
2489 | |
2490 | static const struct panel_desc innolux_at043tn24 = { |
2491 | .modes = &innolux_at043tn24_mode, |
2492 | .num_modes = 1, |
2493 | .bpc = 8, |
2494 | .size = { |
2495 | .width = 95, |
2496 | .height = 54, |
2497 | }, |
2498 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
2499 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
2500 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
2501 | }; |
2502 | |
2503 | static const struct drm_display_mode innolux_at070tn92_mode = { |
2504 | .clock = 33333, |
2505 | .hdisplay = 800, |
2506 | .hsync_start = 800 + 210, |
2507 | .hsync_end = 800 + 210 + 20, |
2508 | .htotal = 800 + 210 + 20 + 46, |
2509 | .vdisplay = 480, |
2510 | .vsync_start = 480 + 22, |
2511 | .vsync_end = 480 + 22 + 10, |
2512 | .vtotal = 480 + 22 + 23 + 10, |
2513 | }; |
2514 | |
2515 | static const struct panel_desc innolux_at070tn92 = { |
2516 | .modes = &innolux_at070tn92_mode, |
2517 | .num_modes = 1, |
2518 | .size = { |
2519 | .width = 154, |
2520 | .height = 86, |
2521 | }, |
2522 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
2523 | }; |
2524 | |
2525 | static const struct display_timing innolux_g070ace_l01_timing = { |
2526 | .pixelclock = { 25200000, 35000000, 35700000 }, |
2527 | .hactive = { 800, 800, 800 }, |
2528 | .hfront_porch = { 30, 32, 87 }, |
2529 | .hback_porch = { 30, 32, 87 }, |
2530 | .hsync_len = { 1, 1, 1 }, |
2531 | .vactive = { 480, 480, 480 }, |
2532 | .vfront_porch = { 3, 3, 3 }, |
2533 | .vback_porch = { 13, 13, 13 }, |
2534 | .vsync_len = { 1, 1, 4 }, |
2535 | .flags = DISPLAY_FLAGS_DE_HIGH, |
2536 | }; |
2537 | |
2538 | static const struct panel_desc innolux_g070ace_l01 = { |
2539 | .timings = &innolux_g070ace_l01_timing, |
2540 | .num_timings = 1, |
2541 | .bpc = 8, |
2542 | .size = { |
2543 | .width = 152, |
2544 | .height = 91, |
2545 | }, |
2546 | .delay = { |
2547 | .prepare = 10, |
2548 | .enable = 50, |
2549 | .disable = 50, |
2550 | .unprepare = 500, |
2551 | }, |
2552 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
2553 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
2554 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2555 | }; |
2556 | |
2557 | static const struct display_timing innolux_g070y2_l01_timing = { |
2558 | .pixelclock = { 28000000, 29500000, 32000000 }, |
2559 | .hactive = { 800, 800, 800 }, |
2560 | .hfront_porch = { 61, 91, 141 }, |
2561 | .hback_porch = { 60, 90, 140 }, |
2562 | .hsync_len = { 12, 12, 12 }, |
2563 | .vactive = { 480, 480, 480 }, |
2564 | .vfront_porch = { 4, 9, 30 }, |
2565 | .vback_porch = { 4, 8, 28 }, |
2566 | .vsync_len = { 2, 2, 2 }, |
2567 | .flags = DISPLAY_FLAGS_DE_HIGH, |
2568 | }; |
2569 | |
2570 | static const struct panel_desc innolux_g070y2_l01 = { |
2571 | .timings = &innolux_g070y2_l01_timing, |
2572 | .num_timings = 1, |
2573 | .bpc = 8, |
2574 | .size = { |
2575 | .width = 152, |
2576 | .height = 91, |
2577 | }, |
2578 | .delay = { |
2579 | .prepare = 10, |
2580 | .enable = 100, |
2581 | .disable = 100, |
2582 | .unprepare = 800, |
2583 | }, |
2584 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
2585 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
2586 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2587 | }; |
2588 | |
2589 | static const struct display_timing innolux_g070ace_lh3_timing = { |
2590 | .pixelclock = { 25200000, 25400000, 35700000 }, |
2591 | .hactive = { 800, 800, 800 }, |
2592 | .hfront_porch = { 30, 32, 87 }, |
2593 | .hback_porch = { 29, 31, 86 }, |
2594 | .hsync_len = { 1, 1, 1 }, |
2595 | .vactive = { 480, 480, 480 }, |
2596 | .vfront_porch = { 4, 5, 65 }, |
2597 | .vback_porch = { 3, 4, 65 }, |
2598 | .vsync_len = { 1, 1, 1 }, |
2599 | .flags = DISPLAY_FLAGS_DE_HIGH, |
2600 | }; |
2601 | |
2602 | static const struct panel_desc innolux_g070ace_lh3 = { |
2603 | .timings = &innolux_g070ace_lh3_timing, |
2604 | .num_timings = 1, |
2605 | .bpc = 8, |
2606 | .size = { |
2607 | .width = 152, |
2608 | .height = 91, |
2609 | }, |
2610 | .delay = { |
2611 | .prepare = 10, |
2612 | .enable = 450, |
2613 | .disable = 200, |
2614 | .unprepare = 510, |
2615 | }, |
2616 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
2617 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
2618 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2619 | }; |
2620 | |
2621 | static const struct drm_display_mode innolux_g070y2_t02_mode = { |
2622 | .clock = 33333, |
2623 | .hdisplay = 800, |
2624 | .hsync_start = 800 + 210, |
2625 | .hsync_end = 800 + 210 + 20, |
2626 | .htotal = 800 + 210 + 20 + 46, |
2627 | .vdisplay = 480, |
2628 | .vsync_start = 480 + 22, |
2629 | .vsync_end = 480 + 22 + 10, |
2630 | .vtotal = 480 + 22 + 23 + 10, |
2631 | }; |
2632 | |
2633 | static const struct panel_desc innolux_g070y2_t02 = { |
2634 | .modes = &innolux_g070y2_t02_mode, |
2635 | .num_modes = 1, |
2636 | .bpc = 8, |
2637 | .size = { |
2638 | .width = 152, |
2639 | .height = 92, |
2640 | }, |
2641 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
2642 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
2643 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
2644 | }; |
2645 | |
2646 | static const struct display_timing innolux_g101ice_l01_timing = { |
2647 | .pixelclock = { 60400000, 71100000, 74700000 }, |
2648 | .hactive = { 1280, 1280, 1280 }, |
2649 | .hfront_porch = { 30, 60, 70 }, |
2650 | .hback_porch = { 30, 60, 70 }, |
2651 | .hsync_len = { 22, 40, 60 }, |
2652 | .vactive = { 800, 800, 800 }, |
2653 | .vfront_porch = { 3, 8, 14 }, |
2654 | .vback_porch = { 3, 8, 14 }, |
2655 | .vsync_len = { 4, 7, 12 }, |
2656 | .flags = DISPLAY_FLAGS_DE_HIGH, |
2657 | }; |
2658 | |
2659 | static const struct panel_desc innolux_g101ice_l01 = { |
2660 | .timings = &innolux_g101ice_l01_timing, |
2661 | .num_timings = 1, |
2662 | .bpc = 8, |
2663 | .size = { |
2664 | .width = 217, |
2665 | .height = 135, |
2666 | }, |
2667 | .delay = { |
2668 | .enable = 200, |
2669 | .disable = 200, |
2670 | }, |
2671 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
2672 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
2673 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2674 | }; |
2675 | |
2676 | static const struct display_timing innolux_g121i1_l01_timing = { |
2677 | .pixelclock = { 67450000, 71000000, 74550000 }, |
2678 | .hactive = { 1280, 1280, 1280 }, |
2679 | .hfront_porch = { 40, 80, 160 }, |
2680 | .hback_porch = { 39, 79, 159 }, |
2681 | .hsync_len = { 1, 1, 1 }, |
2682 | .vactive = { 800, 800, 800 }, |
2683 | .vfront_porch = { 5, 11, 100 }, |
2684 | .vback_porch = { 4, 11, 99 }, |
2685 | .vsync_len = { 1, 1, 1 }, |
2686 | }; |
2687 | |
2688 | static const struct panel_desc innolux_g121i1_l01 = { |
2689 | .timings = &innolux_g121i1_l01_timing, |
2690 | .num_timings = 1, |
2691 | .bpc = 6, |
2692 | .size = { |
2693 | .width = 261, |
2694 | .height = 163, |
2695 | }, |
2696 | .delay = { |
2697 | .enable = 200, |
2698 | .disable = 20, |
2699 | }, |
2700 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
2701 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2702 | }; |
2703 | |
2704 | static const struct display_timing innolux_g121x1_l03_timings = { |
2705 | .pixelclock = { 57500000, 64900000, 74400000 }, |
2706 | .hactive = { 1024, 1024, 1024 }, |
2707 | .hfront_porch = { 90, 140, 190 }, |
2708 | .hback_porch = { 90, 140, 190 }, |
2709 | .hsync_len = { 36, 40, 60 }, |
2710 | .vactive = { 768, 768, 768 }, |
2711 | .vfront_porch = { 2, 15, 30 }, |
2712 | .vback_porch = { 2, 15, 30 }, |
2713 | .vsync_len = { 2, 8, 20 }, |
2714 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, |
2715 | }; |
2716 | |
2717 | static const struct panel_desc innolux_g121x1_l03 = { |
2718 | .timings = &innolux_g121x1_l03_timings, |
2719 | .num_timings = 1, |
2720 | .bpc = 6, |
2721 | .size = { |
2722 | .width = 246, |
2723 | .height = 185, |
2724 | }, |
2725 | .delay = { |
2726 | .enable = 200, |
2727 | .unprepare = 200, |
2728 | .disable = 400, |
2729 | }, |
2730 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
2731 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
2732 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2733 | }; |
2734 | |
2735 | static const struct panel_desc innolux_g121xce_l01 = { |
2736 | .timings = &innolux_g121x1_l03_timings, |
2737 | .num_timings = 1, |
2738 | .bpc = 8, |
2739 | .size = { |
2740 | .width = 246, |
2741 | .height = 185, |
2742 | }, |
2743 | .delay = { |
2744 | .enable = 200, |
2745 | .unprepare = 200, |
2746 | .disable = 400, |
2747 | }, |
2748 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
2749 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
2750 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2751 | }; |
2752 | |
2753 | static const struct display_timing innolux_g156hce_l01_timings = { |
2754 | .pixelclock = { 120000000, 141860000, 150000000 }, |
2755 | .hactive = { 1920, 1920, 1920 }, |
2756 | .hfront_porch = { 80, 90, 100 }, |
2757 | .hback_porch = { 80, 90, 100 }, |
2758 | .hsync_len = { 20, 30, 30 }, |
2759 | .vactive = { 1080, 1080, 1080 }, |
2760 | .vfront_porch = { 3, 10, 20 }, |
2761 | .vback_porch = { 3, 10, 20 }, |
2762 | .vsync_len = { 4, 10, 10 }, |
2763 | }; |
2764 | |
2765 | static const struct panel_desc innolux_g156hce_l01 = { |
2766 | .timings = &innolux_g156hce_l01_timings, |
2767 | .num_timings = 1, |
2768 | .bpc = 8, |
2769 | .size = { |
2770 | .width = 344, |
2771 | .height = 194, |
2772 | }, |
2773 | .delay = { |
2774 | .prepare = 1, /* T1+T2 */ |
2775 | .enable = 450, /* T5 */ |
2776 | .disable = 200, /* T6 */ |
2777 | .unprepare = 10, /* T3+T7 */ |
2778 | }, |
2779 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
2780 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
2781 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2782 | }; |
2783 | |
2784 | static const struct drm_display_mode innolux_n156bge_l21_mode = { |
2785 | .clock = 69300, |
2786 | .hdisplay = 1366, |
2787 | .hsync_start = 1366 + 16, |
2788 | .hsync_end = 1366 + 16 + 34, |
2789 | .htotal = 1366 + 16 + 34 + 50, |
2790 | .vdisplay = 768, |
2791 | .vsync_start = 768 + 2, |
2792 | .vsync_end = 768 + 2 + 6, |
2793 | .vtotal = 768 + 2 + 6 + 12, |
2794 | }; |
2795 | |
2796 | static const struct panel_desc innolux_n156bge_l21 = { |
2797 | .modes = &innolux_n156bge_l21_mode, |
2798 | .num_modes = 1, |
2799 | .bpc = 6, |
2800 | .size = { |
2801 | .width = 344, |
2802 | .height = 193, |
2803 | }, |
2804 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
2805 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
2806 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2807 | }; |
2808 | |
2809 | static const struct drm_display_mode innolux_zj070na_01p_mode = { |
2810 | .clock = 51501, |
2811 | .hdisplay = 1024, |
2812 | .hsync_start = 1024 + 128, |
2813 | .hsync_end = 1024 + 128 + 64, |
2814 | .htotal = 1024 + 128 + 64 + 128, |
2815 | .vdisplay = 600, |
2816 | .vsync_start = 600 + 16, |
2817 | .vsync_end = 600 + 16 + 4, |
2818 | .vtotal = 600 + 16 + 4 + 16, |
2819 | }; |
2820 | |
2821 | static const struct panel_desc innolux_zj070na_01p = { |
2822 | .modes = &innolux_zj070na_01p_mode, |
2823 | .num_modes = 1, |
2824 | .bpc = 6, |
2825 | .size = { |
2826 | .width = 154, |
2827 | .height = 90, |
2828 | }, |
2829 | }; |
2830 | |
2831 | static const struct display_timing koe_tx14d24vm1bpa_timing = { |
2832 | .pixelclock = { 5580000, 5850000, 6200000 }, |
2833 | .hactive = { 320, 320, 320 }, |
2834 | .hfront_porch = { 30, 30, 30 }, |
2835 | .hback_porch = { 30, 30, 30 }, |
2836 | .hsync_len = { 1, 5, 17 }, |
2837 | .vactive = { 240, 240, 240 }, |
2838 | .vfront_porch = { 6, 6, 6 }, |
2839 | .vback_porch = { 5, 5, 5 }, |
2840 | .vsync_len = { 1, 2, 11 }, |
2841 | .flags = DISPLAY_FLAGS_DE_HIGH, |
2842 | }; |
2843 | |
2844 | static const struct panel_desc koe_tx14d24vm1bpa = { |
2845 | .timings = &koe_tx14d24vm1bpa_timing, |
2846 | .num_timings = 1, |
2847 | .bpc = 6, |
2848 | .size = { |
2849 | .width = 115, |
2850 | .height = 86, |
2851 | }, |
2852 | }; |
2853 | |
2854 | static const struct display_timing koe_tx26d202vm0bwa_timing = { |
2855 | .pixelclock = { 151820000, 156720000, 159780000 }, |
2856 | .hactive = { 1920, 1920, 1920 }, |
2857 | .hfront_porch = { 105, 130, 142 }, |
2858 | .hback_porch = { 45, 70, 82 }, |
2859 | .hsync_len = { 30, 30, 30 }, |
2860 | .vactive = { 1200, 1200, 1200}, |
2861 | .vfront_porch = { 3, 5, 10 }, |
2862 | .vback_porch = { 2, 5, 10 }, |
2863 | .vsync_len = { 5, 5, 5 }, |
2864 | .flags = DISPLAY_FLAGS_DE_HIGH, |
2865 | }; |
2866 | |
2867 | static const struct panel_desc koe_tx26d202vm0bwa = { |
2868 | .timings = &koe_tx26d202vm0bwa_timing, |
2869 | .num_timings = 1, |
2870 | .bpc = 8, |
2871 | .size = { |
2872 | .width = 217, |
2873 | .height = 136, |
2874 | }, |
2875 | .delay = { |
2876 | .prepare = 1000, |
2877 | .enable = 1000, |
2878 | .unprepare = 1000, |
2879 | .disable = 1000, |
2880 | }, |
2881 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
2882 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
2883 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2884 | }; |
2885 | |
2886 | static const struct display_timing koe_tx31d200vm0baa_timing = { |
2887 | .pixelclock = { 39600000, 43200000, 48000000 }, |
2888 | .hactive = { 1280, 1280, 1280 }, |
2889 | .hfront_porch = { 16, 36, 56 }, |
2890 | .hback_porch = { 16, 36, 56 }, |
2891 | .hsync_len = { 8, 8, 8 }, |
2892 | .vactive = { 480, 480, 480 }, |
2893 | .vfront_porch = { 6, 21, 33 }, |
2894 | .vback_porch = { 6, 21, 33 }, |
2895 | .vsync_len = { 8, 8, 8 }, |
2896 | .flags = DISPLAY_FLAGS_DE_HIGH, |
2897 | }; |
2898 | |
2899 | static const struct panel_desc koe_tx31d200vm0baa = { |
2900 | .timings = &koe_tx31d200vm0baa_timing, |
2901 | .num_timings = 1, |
2902 | .bpc = 6, |
2903 | .size = { |
2904 | .width = 292, |
2905 | .height = 109, |
2906 | }, |
2907 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
2908 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2909 | }; |
2910 | |
2911 | static const struct display_timing kyo_tcg121xglp_timing = { |
2912 | .pixelclock = { 52000000, 65000000, 71000000 }, |
2913 | .hactive = { 1024, 1024, 1024 }, |
2914 | .hfront_porch = { 2, 2, 2 }, |
2915 | .hback_porch = { 2, 2, 2 }, |
2916 | .hsync_len = { 86, 124, 244 }, |
2917 | .vactive = { 768, 768, 768 }, |
2918 | .vfront_porch = { 2, 2, 2 }, |
2919 | .vback_porch = { 2, 2, 2 }, |
2920 | .vsync_len = { 6, 34, 73 }, |
2921 | .flags = DISPLAY_FLAGS_DE_HIGH, |
2922 | }; |
2923 | |
2924 | static const struct panel_desc kyo_tcg121xglp = { |
2925 | .timings = &kyo_tcg121xglp_timing, |
2926 | .num_timings = 1, |
2927 | .bpc = 8, |
2928 | .size = { |
2929 | .width = 246, |
2930 | .height = 184, |
2931 | }, |
2932 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
2933 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2934 | }; |
2935 | |
2936 | static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { |
2937 | .clock = 7000, |
2938 | .hdisplay = 320, |
2939 | .hsync_start = 320 + 20, |
2940 | .hsync_end = 320 + 20 + 30, |
2941 | .htotal = 320 + 20 + 30 + 38, |
2942 | .vdisplay = 240, |
2943 | .vsync_start = 240 + 4, |
2944 | .vsync_end = 240 + 4 + 3, |
2945 | .vtotal = 240 + 4 + 3 + 15, |
2946 | }; |
2947 | |
2948 | static const struct panel_desc lemaker_bl035_rgb_002 = { |
2949 | .modes = &lemaker_bl035_rgb_002_mode, |
2950 | .num_modes = 1, |
2951 | .size = { |
2952 | .width = 70, |
2953 | .height = 52, |
2954 | }, |
2955 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
2956 | .bus_flags = DRM_BUS_FLAG_DE_LOW, |
2957 | }; |
2958 | |
2959 | static const struct display_timing lg_lb070wv8_timing = { |
2960 | .pixelclock = { 31950000, 33260000, 34600000 }, |
2961 | .hactive = { 800, 800, 800 }, |
2962 | .hfront_porch = { 88, 88, 88 }, |
2963 | .hback_porch = { 88, 88, 88 }, |
2964 | .hsync_len = { 80, 80, 80 }, |
2965 | .vactive = { 480, 480, 480 }, |
2966 | .vfront_porch = { 10, 10, 10 }, |
2967 | .vback_porch = { 10, 10, 10 }, |
2968 | .vsync_len = { 25, 25, 25 }, |
2969 | }; |
2970 | |
2971 | static const struct panel_desc lg_lb070wv8 = { |
2972 | .timings = &lg_lb070wv8_timing, |
2973 | .num_timings = 1, |
2974 | .bpc = 8, |
2975 | .size = { |
2976 | .width = 151, |
2977 | .height = 91, |
2978 | }, |
2979 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
2980 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2981 | }; |
2982 | |
2983 | static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { |
2984 | .clock = 155127, |
2985 | .hdisplay = 1920, |
2986 | .hsync_start = 1920 + 128, |
2987 | .hsync_end = 1920 + 128 + 20, |
2988 | .htotal = 1920 + 128 + 20 + 12, |
2989 | .vdisplay = 1200, |
2990 | .vsync_start = 1200 + 19, |
2991 | .vsync_end = 1200 + 19 + 4, |
2992 | .vtotal = 1200 + 19 + 4 + 20, |
2993 | }; |
2994 | |
2995 | static const struct panel_desc lincolntech_lcd185_101ct = { |
2996 | .modes = &lincolntech_lcd185_101ct_mode, |
2997 | .bpc = 8, |
2998 | .num_modes = 1, |
2999 | .size = { |
3000 | .width = 217, |
3001 | .height = 136, |
3002 | }, |
3003 | .delay = { |
3004 | .prepare = 50, |
3005 | .disable = 50, |
3006 | }, |
3007 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
3008 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
3009 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3010 | }; |
3011 | |
3012 | static const struct display_timing logictechno_lt161010_2nh_timing = { |
3013 | .pixelclock = { 26400000, 33300000, 46800000 }, |
3014 | .hactive = { 800, 800, 800 }, |
3015 | .hfront_porch = { 16, 210, 354 }, |
3016 | .hback_porch = { 46, 46, 46 }, |
3017 | .hsync_len = { 1, 20, 40 }, |
3018 | .vactive = { 480, 480, 480 }, |
3019 | .vfront_porch = { 7, 22, 147 }, |
3020 | .vback_porch = { 23, 23, 23 }, |
3021 | .vsync_len = { 1, 10, 20 }, |
3022 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
3023 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | |
3024 | DISPLAY_FLAGS_SYNC_POSEDGE, |
3025 | }; |
3026 | |
3027 | static const struct panel_desc logictechno_lt161010_2nh = { |
3028 | .timings = &logictechno_lt161010_2nh_timing, |
3029 | .num_timings = 1, |
3030 | .bpc = 6, |
3031 | .size = { |
3032 | .width = 154, |
3033 | .height = 86, |
3034 | }, |
3035 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
3036 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | |
3037 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | |
3038 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, |
3039 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
3040 | }; |
3041 | |
3042 | static const struct display_timing logictechno_lt170410_2whc_timing = { |
3043 | .pixelclock = { 68900000, 71100000, 73400000 }, |
3044 | .hactive = { 1280, 1280, 1280 }, |
3045 | .hfront_porch = { 23, 60, 71 }, |
3046 | .hback_porch = { 23, 60, 71 }, |
3047 | .hsync_len = { 15, 40, 47 }, |
3048 | .vactive = { 800, 800, 800 }, |
3049 | .vfront_porch = { 5, 7, 10 }, |
3050 | .vback_porch = { 5, 7, 10 }, |
3051 | .vsync_len = { 6, 9, 12 }, |
3052 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
3053 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | |
3054 | DISPLAY_FLAGS_SYNC_POSEDGE, |
3055 | }; |
3056 | |
3057 | static const struct panel_desc logictechno_lt170410_2whc = { |
3058 | .timings = &logictechno_lt170410_2whc_timing, |
3059 | .num_timings = 1, |
3060 | .bpc = 8, |
3061 | .size = { |
3062 | .width = 217, |
3063 | .height = 136, |
3064 | }, |
3065 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
3066 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
3067 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3068 | }; |
3069 | |
3070 | static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { |
3071 | .clock = 33000, |
3072 | .hdisplay = 800, |
3073 | .hsync_start = 800 + 112, |
3074 | .hsync_end = 800 + 112 + 3, |
3075 | .htotal = 800 + 112 + 3 + 85, |
3076 | .vdisplay = 480, |
3077 | .vsync_start = 480 + 38, |
3078 | .vsync_end = 480 + 38 + 3, |
3079 | .vtotal = 480 + 38 + 3 + 29, |
3080 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
3081 | }; |
3082 | |
3083 | static const struct panel_desc logictechno_lttd800480070_l2rt = { |
3084 | .modes = &logictechno_lttd800480070_l2rt_mode, |
3085 | .num_modes = 1, |
3086 | .bpc = 8, |
3087 | .size = { |
3088 | .width = 154, |
3089 | .height = 86, |
3090 | }, |
3091 | .delay = { |
3092 | .prepare = 45, |
3093 | .enable = 100, |
3094 | .disable = 100, |
3095 | .unprepare = 45 |
3096 | }, |
3097 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
3098 | .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
3099 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
3100 | }; |
3101 | |
3102 | static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { |
3103 | .clock = 33000, |
3104 | .hdisplay = 800, |
3105 | .hsync_start = 800 + 154, |
3106 | .hsync_end = 800 + 154 + 3, |
3107 | .htotal = 800 + 154 + 3 + 43, |
3108 | .vdisplay = 480, |
3109 | .vsync_start = 480 + 47, |
3110 | .vsync_end = 480 + 47 + 3, |
3111 | .vtotal = 480 + 47 + 3 + 20, |
3112 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
3113 | }; |
3114 | |
3115 | static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { |
3116 | .modes = &logictechno_lttd800480070_l6wh_rt_mode, |
3117 | .num_modes = 1, |
3118 | .bpc = 8, |
3119 | .size = { |
3120 | .width = 154, |
3121 | .height = 86, |
3122 | }, |
3123 | .delay = { |
3124 | .prepare = 45, |
3125 | .enable = 100, |
3126 | .disable = 100, |
3127 | .unprepare = 45 |
3128 | }, |
3129 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
3130 | .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
3131 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
3132 | }; |
3133 | |
3134 | static const struct drm_display_mode logicpd_type_28_mode = { |
3135 | .clock = 9107, |
3136 | .hdisplay = 480, |
3137 | .hsync_start = 480 + 3, |
3138 | .hsync_end = 480 + 3 + 42, |
3139 | .htotal = 480 + 3 + 42 + 2, |
3140 | |
3141 | .vdisplay = 272, |
3142 | .vsync_start = 272 + 2, |
3143 | .vsync_end = 272 + 2 + 11, |
3144 | .vtotal = 272 + 2 + 11 + 3, |
3145 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, |
3146 | }; |
3147 | |
3148 | static const struct panel_desc logicpd_type_28 = { |
3149 | .modes = &logicpd_type_28_mode, |
3150 | .num_modes = 1, |
3151 | .bpc = 8, |
3152 | .size = { |
3153 | .width = 105, |
3154 | .height = 67, |
3155 | }, |
3156 | .delay = { |
3157 | .prepare = 200, |
3158 | .enable = 200, |
3159 | .unprepare = 200, |
3160 | .disable = 200, |
3161 | }, |
3162 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
3163 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | |
3164 | DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, |
3165 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
3166 | }; |
3167 | |
3168 | static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { |
3169 | .clock = 150275, |
3170 | .hdisplay = 1920, |
3171 | .hsync_start = 1920 + 32, |
3172 | .hsync_end = 1920 + 32 + 52, |
3173 | .htotal = 1920 + 32 + 52 + 24, |
3174 | .vdisplay = 1200, |
3175 | .vsync_start = 1200 + 24, |
3176 | .vsync_end = 1200 + 24 + 8, |
3177 | .vtotal = 1200 + 24 + 8 + 3, |
3178 | }; |
3179 | |
3180 | static const struct panel_desc microtips_mf_101hiebcaf0_c = { |
3181 | .modes = µtips_mf_101hiebcaf0_c_mode, |
3182 | .bpc = 8, |
3183 | .num_modes = 1, |
3184 | .size = { |
3185 | .width = 217, |
3186 | .height = 136, |
3187 | }, |
3188 | .delay = { |
3189 | .prepare = 50, |
3190 | .disable = 50, |
3191 | }, |
3192 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
3193 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
3194 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3195 | }; |
3196 | |
3197 | static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { |
3198 | .clock = 93301, |
3199 | .hdisplay = 1920, |
3200 | .hsync_start = 1920 + 72, |
3201 | .hsync_end = 1920 + 72 + 72, |
3202 | .htotal = 1920 + 72 + 72 + 72, |
3203 | .vdisplay = 720, |
3204 | .vsync_start = 720 + 3, |
3205 | .vsync_end = 720 + 3 + 3, |
3206 | .vtotal = 720 + 3 + 3 + 2, |
3207 | }; |
3208 | |
3209 | static const struct panel_desc microtips_mf_103hieb0ga0 = { |
3210 | .modes = µtips_mf_103hieb0ga0_mode, |
3211 | .bpc = 8, |
3212 | .num_modes = 1, |
3213 | .size = { |
3214 | .width = 244, |
3215 | .height = 92, |
3216 | }, |
3217 | .delay = { |
3218 | .prepare = 50, |
3219 | .disable = 50, |
3220 | }, |
3221 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
3222 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
3223 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3224 | }; |
3225 | |
3226 | static const struct drm_display_mode mitsubishi_aa070mc01_mode = { |
3227 | .clock = 30400, |
3228 | .hdisplay = 800, |
3229 | .hsync_start = 800 + 0, |
3230 | .hsync_end = 800 + 1, |
3231 | .htotal = 800 + 0 + 1 + 160, |
3232 | .vdisplay = 480, |
3233 | .vsync_start = 480 + 0, |
3234 | .vsync_end = 480 + 48 + 1, |
3235 | .vtotal = 480 + 48 + 1 + 0, |
3236 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
3237 | }; |
3238 | |
3239 | static const struct panel_desc mitsubishi_aa070mc01 = { |
3240 | .modes = &mitsubishi_aa070mc01_mode, |
3241 | .num_modes = 1, |
3242 | .bpc = 8, |
3243 | .size = { |
3244 | .width = 152, |
3245 | .height = 91, |
3246 | }, |
3247 | |
3248 | .delay = { |
3249 | .enable = 200, |
3250 | .unprepare = 200, |
3251 | .disable = 400, |
3252 | }, |
3253 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
3254 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3255 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
3256 | }; |
3257 | |
3258 | static const struct drm_display_mode mitsubishi_aa084xe01_mode = { |
3259 | .clock = 56234, |
3260 | .hdisplay = 1024, |
3261 | .hsync_start = 1024 + 24, |
3262 | .hsync_end = 1024 + 24 + 63, |
3263 | .htotal = 1024 + 24 + 63 + 1, |
3264 | .vdisplay = 768, |
3265 | .vsync_start = 768 + 3, |
3266 | .vsync_end = 768 + 3 + 6, |
3267 | .vtotal = 768 + 3 + 6 + 1, |
3268 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, |
3269 | }; |
3270 | |
3271 | static const struct panel_desc mitsubishi_aa084xe01 = { |
3272 | .modes = &mitsubishi_aa084xe01_mode, |
3273 | .num_modes = 1, |
3274 | .bpc = 8, |
3275 | .size = { |
3276 | .width = 1024, |
3277 | .height = 768, |
3278 | }, |
3279 | .bus_format = MEDIA_BUS_FMT_RGB565_1X16, |
3280 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
3281 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
3282 | }; |
3283 | |
3284 | static const struct display_timing multi_inno_mi0700a2t_30_timing = { |
3285 | .pixelclock = { 26400000, 33000000, 46800000 }, |
3286 | .hactive = { 800, 800, 800 }, |
3287 | .hfront_porch = { 16, 204, 354 }, |
3288 | .hback_porch = { 46, 46, 46 }, |
3289 | .hsync_len = { 1, 6, 40 }, |
3290 | .vactive = { 480, 480, 480 }, |
3291 | .vfront_porch = { 7, 22, 147 }, |
3292 | .vback_porch = { 23, 23, 23 }, |
3293 | .vsync_len = { 1, 3, 20 }, |
3294 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
3295 | DISPLAY_FLAGS_DE_HIGH, |
3296 | }; |
3297 | |
3298 | static const struct panel_desc multi_inno_mi0700a2t_30 = { |
3299 | .timings = &multi_inno_mi0700a2t_30_timing, |
3300 | .num_timings = 1, |
3301 | .bpc = 6, |
3302 | .size = { |
3303 | .width = 153, |
3304 | .height = 92, |
3305 | }, |
3306 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
3307 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
3308 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3309 | }; |
3310 | |
3311 | static const struct display_timing multi_inno_mi0700s4t_6_timing = { |
3312 | .pixelclock = { 29000000, 33000000, 38000000 }, |
3313 | .hactive = { 800, 800, 800 }, |
3314 | .hfront_porch = { 180, 210, 240 }, |
3315 | .hback_porch = { 16, 16, 16 }, |
3316 | .hsync_len = { 30, 30, 30 }, |
3317 | .vactive = { 480, 480, 480 }, |
3318 | .vfront_porch = { 12, 22, 32 }, |
3319 | .vback_porch = { 10, 10, 10 }, |
3320 | .vsync_len = { 13, 13, 13 }, |
3321 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
3322 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | |
3323 | DISPLAY_FLAGS_SYNC_POSEDGE, |
3324 | }; |
3325 | |
3326 | static const struct panel_desc multi_inno_mi0700s4t_6 = { |
3327 | .timings = &multi_inno_mi0700s4t_6_timing, |
3328 | .num_timings = 1, |
3329 | .bpc = 8, |
3330 | .size = { |
3331 | .width = 154, |
3332 | .height = 86, |
3333 | }, |
3334 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
3335 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | |
3336 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | |
3337 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, |
3338 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
3339 | }; |
3340 | |
3341 | static const struct display_timing multi_inno_mi0800ft_9_timing = { |
3342 | .pixelclock = { 32000000, 40000000, 50000000 }, |
3343 | .hactive = { 800, 800, 800 }, |
3344 | .hfront_porch = { 16, 210, 354 }, |
3345 | .hback_porch = { 6, 26, 45 }, |
3346 | .hsync_len = { 1, 20, 40 }, |
3347 | .vactive = { 600, 600, 600 }, |
3348 | .vfront_porch = { 1, 12, 77 }, |
3349 | .vback_porch = { 3, 13, 22 }, |
3350 | .vsync_len = { 1, 10, 20 }, |
3351 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
3352 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | |
3353 | DISPLAY_FLAGS_SYNC_POSEDGE, |
3354 | }; |
3355 | |
3356 | static const struct panel_desc multi_inno_mi0800ft_9 = { |
3357 | .timings = &multi_inno_mi0800ft_9_timing, |
3358 | .num_timings = 1, |
3359 | .bpc = 8, |
3360 | .size = { |
3361 | .width = 162, |
3362 | .height = 122, |
3363 | }, |
3364 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
3365 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | |
3366 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | |
3367 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, |
3368 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
3369 | }; |
3370 | |
3371 | static const struct display_timing multi_inno_mi1010ait_1cp_timing = { |
3372 | .pixelclock = { 68900000, 70000000, 73400000 }, |
3373 | .hactive = { 1280, 1280, 1280 }, |
3374 | .hfront_porch = { 30, 60, 71 }, |
3375 | .hback_porch = { 30, 60, 71 }, |
3376 | .hsync_len = { 10, 10, 48 }, |
3377 | .vactive = { 800, 800, 800 }, |
3378 | .vfront_porch = { 5, 10, 10 }, |
3379 | .vback_porch = { 5, 10, 10 }, |
3380 | .vsync_len = { 5, 6, 13 }, |
3381 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
3382 | DISPLAY_FLAGS_DE_HIGH, |
3383 | }; |
3384 | |
3385 | static const struct panel_desc multi_inno_mi1010ait_1cp = { |
3386 | .timings = &multi_inno_mi1010ait_1cp_timing, |
3387 | .num_timings = 1, |
3388 | .bpc = 8, |
3389 | .size = { |
3390 | .width = 217, |
3391 | .height = 136, |
3392 | }, |
3393 | .delay = { |
3394 | .enable = 50, |
3395 | .disable = 50, |
3396 | }, |
3397 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
3398 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
3399 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3400 | }; |
3401 | |
3402 | static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { |
3403 | .pixelclock = { 40800000, 51200000, 67200000 }, |
3404 | .hactive = { 1024, 1024, 1024 }, |
3405 | .hfront_porch = { 30, 110, 130 }, |
3406 | .hback_porch = { 30, 110, 130 }, |
3407 | .hsync_len = { 30, 100, 116 }, |
3408 | .vactive = { 600, 600, 600 }, |
3409 | .vfront_porch = { 4, 13, 80 }, |
3410 | .vback_porch = { 4, 13, 80 }, |
3411 | .vsync_len = { 2, 9, 40 }, |
3412 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
3413 | DISPLAY_FLAGS_DE_HIGH, |
3414 | }; |
3415 | |
3416 | static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { |
3417 | .timings = &multi_inno_mi1010z1t_1cp11_timing, |
3418 | .num_timings = 1, |
3419 | .bpc = 6, |
3420 | .size = { |
3421 | .width = 260, |
3422 | .height = 162, |
3423 | }, |
3424 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
3425 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
3426 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3427 | }; |
3428 | |
3429 | static const struct display_timing nec_nl12880bc20_05_timing = { |
3430 | .pixelclock = { 67000000, 71000000, 75000000 }, |
3431 | .hactive = { 1280, 1280, 1280 }, |
3432 | .hfront_porch = { 2, 30, 30 }, |
3433 | .hback_porch = { 6, 100, 100 }, |
3434 | .hsync_len = { 2, 30, 30 }, |
3435 | .vactive = { 800, 800, 800 }, |
3436 | .vfront_porch = { 5, 5, 5 }, |
3437 | .vback_porch = { 11, 11, 11 }, |
3438 | .vsync_len = { 7, 7, 7 }, |
3439 | }; |
3440 | |
3441 | static const struct panel_desc nec_nl12880bc20_05 = { |
3442 | .timings = &nec_nl12880bc20_05_timing, |
3443 | .num_timings = 1, |
3444 | .bpc = 8, |
3445 | .size = { |
3446 | .width = 261, |
3447 | .height = 163, |
3448 | }, |
3449 | .delay = { |
3450 | .enable = 50, |
3451 | .disable = 50, |
3452 | }, |
3453 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
3454 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3455 | }; |
3456 | |
3457 | static const struct drm_display_mode nec_nl4827hc19_05b_mode = { |
3458 | .clock = 10870, |
3459 | .hdisplay = 480, |
3460 | .hsync_start = 480 + 2, |
3461 | .hsync_end = 480 + 2 + 41, |
3462 | .htotal = 480 + 2 + 41 + 2, |
3463 | .vdisplay = 272, |
3464 | .vsync_start = 272 + 2, |
3465 | .vsync_end = 272 + 2 + 4, |
3466 | .vtotal = 272 + 2 + 4 + 2, |
3467 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
3468 | }; |
3469 | |
3470 | static const struct panel_desc nec_nl4827hc19_05b = { |
3471 | .modes = &nec_nl4827hc19_05b_mode, |
3472 | .num_modes = 1, |
3473 | .bpc = 8, |
3474 | .size = { |
3475 | .width = 95, |
3476 | .height = 54, |
3477 | }, |
3478 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
3479 | .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
3480 | }; |
3481 | |
3482 | static const struct drm_display_mode netron_dy_e231732_mode = { |
3483 | .clock = 66000, |
3484 | .hdisplay = 1024, |
3485 | .hsync_start = 1024 + 160, |
3486 | .hsync_end = 1024 + 160 + 70, |
3487 | .htotal = 1024 + 160 + 70 + 90, |
3488 | .vdisplay = 600, |
3489 | .vsync_start = 600 + 127, |
3490 | .vsync_end = 600 + 127 + 20, |
3491 | .vtotal = 600 + 127 + 20 + 3, |
3492 | }; |
3493 | |
3494 | static const struct panel_desc netron_dy_e231732 = { |
3495 | .modes = &netron_dy_e231732_mode, |
3496 | .num_modes = 1, |
3497 | .size = { |
3498 | .width = 154, |
3499 | .height = 87, |
3500 | }, |
3501 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
3502 | }; |
3503 | |
3504 | static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { |
3505 | .clock = 9000, |
3506 | .hdisplay = 480, |
3507 | .hsync_start = 480 + 2, |
3508 | .hsync_end = 480 + 2 + 41, |
3509 | .htotal = 480 + 2 + 41 + 2, |
3510 | .vdisplay = 272, |
3511 | .vsync_start = 272 + 2, |
3512 | .vsync_end = 272 + 2 + 10, |
3513 | .vtotal = 272 + 2 + 10 + 2, |
3514 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
3515 | }; |
3516 | |
3517 | static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { |
3518 | .modes = &newhaven_nhd_43_480272ef_atxl_mode, |
3519 | .num_modes = 1, |
3520 | .bpc = 8, |
3521 | .size = { |
3522 | .width = 95, |
3523 | .height = 54, |
3524 | }, |
3525 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
3526 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | |
3527 | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, |
3528 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
3529 | }; |
3530 | |
3531 | static const struct drm_display_mode nlt_nl13676bc25_03f_mode = { |
3532 | .clock = 75400, |
3533 | .hdisplay = 1366, |
3534 | .hsync_start = 1366 + 14, |
3535 | .hsync_end = 1366 + 14 + 56, |
3536 | .htotal = 1366 + 14 + 56 + 64, |
3537 | .vdisplay = 768, |
3538 | .vsync_start = 768 + 1, |
3539 | .vsync_end = 768 + 1 + 3, |
3540 | .vtotal = 768 + 1 + 3 + 22, |
3541 | }; |
3542 | |
3543 | static const struct panel_desc nlt_nl13676bc25_03f = { |
3544 | .modes = &nlt_nl13676bc25_03f_mode, |
3545 | .num_modes = 1, |
3546 | .bpc = 8, |
3547 | .size = { |
3548 | .width = 363, |
3549 | .height = 215, |
3550 | }, |
3551 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
3552 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3553 | }; |
3554 | |
3555 | static const struct display_timing nlt_nl192108ac18_02d_timing = { |
3556 | .pixelclock = { 130000000, 148350000, 163000000 }, |
3557 | .hactive = { 1920, 1920, 1920 }, |
3558 | .hfront_porch = { 80, 100, 100 }, |
3559 | .hback_porch = { 100, 120, 120 }, |
3560 | .hsync_len = { 50, 60, 60 }, |
3561 | .vactive = { 1080, 1080, 1080 }, |
3562 | .vfront_porch = { 12, 30, 30 }, |
3563 | .vback_porch = { 4, 10, 10 }, |
3564 | .vsync_len = { 4, 5, 5 }, |
3565 | }; |
3566 | |
3567 | static const struct panel_desc nlt_nl192108ac18_02d = { |
3568 | .timings = &nlt_nl192108ac18_02d_timing, |
3569 | .num_timings = 1, |
3570 | .bpc = 8, |
3571 | .size = { |
3572 | .width = 344, |
3573 | .height = 194, |
3574 | }, |
3575 | .delay = { |
3576 | .unprepare = 500, |
3577 | }, |
3578 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
3579 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3580 | }; |
3581 | |
3582 | static const struct drm_display_mode nvd_9128_mode = { |
3583 | .clock = 29500, |
3584 | .hdisplay = 800, |
3585 | .hsync_start = 800 + 130, |
3586 | .hsync_end = 800 + 130 + 98, |
3587 | .htotal = 800 + 0 + 130 + 98, |
3588 | .vdisplay = 480, |
3589 | .vsync_start = 480 + 10, |
3590 | .vsync_end = 480 + 10 + 50, |
3591 | .vtotal = 480 + 0 + 10 + 50, |
3592 | }; |
3593 | |
3594 | static const struct panel_desc nvd_9128 = { |
3595 | .modes = &nvd_9128_mode, |
3596 | .num_modes = 1, |
3597 | .bpc = 8, |
3598 | .size = { |
3599 | .width = 156, |
3600 | .height = 88, |
3601 | }, |
3602 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
3603 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3604 | }; |
3605 | |
3606 | static const struct display_timing okaya_rs800480t_7x0gp_timing = { |
3607 | .pixelclock = { 30000000, 30000000, 40000000 }, |
3608 | .hactive = { 800, 800, 800 }, |
3609 | .hfront_porch = { 40, 40, 40 }, |
3610 | .hback_porch = { 40, 40, 40 }, |
3611 | .hsync_len = { 1, 48, 48 }, |
3612 | .vactive = { 480, 480, 480 }, |
3613 | .vfront_porch = { 13, 13, 13 }, |
3614 | .vback_porch = { 29, 29, 29 }, |
3615 | .vsync_len = { 3, 3, 3 }, |
3616 | .flags = DISPLAY_FLAGS_DE_HIGH, |
3617 | }; |
3618 | |
3619 | static const struct panel_desc okaya_rs800480t_7x0gp = { |
3620 | .timings = &okaya_rs800480t_7x0gp_timing, |
3621 | .num_timings = 1, |
3622 | .bpc = 6, |
3623 | .size = { |
3624 | .width = 154, |
3625 | .height = 87, |
3626 | }, |
3627 | .delay = { |
3628 | .prepare = 41, |
3629 | .enable = 50, |
3630 | .unprepare = 41, |
3631 | .disable = 50, |
3632 | }, |
3633 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
3634 | }; |
3635 | |
3636 | static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { |
3637 | .clock = 9000, |
3638 | .hdisplay = 480, |
3639 | .hsync_start = 480 + 5, |
3640 | .hsync_end = 480 + 5 + 30, |
3641 | .htotal = 480 + 5 + 30 + 10, |
3642 | .vdisplay = 272, |
3643 | .vsync_start = 272 + 8, |
3644 | .vsync_end = 272 + 8 + 5, |
3645 | .vtotal = 272 + 8 + 5 + 3, |
3646 | }; |
3647 | |
3648 | static const struct panel_desc olimex_lcd_olinuxino_43ts = { |
3649 | .modes = &olimex_lcd_olinuxino_43ts_mode, |
3650 | .num_modes = 1, |
3651 | .size = { |
3652 | .width = 95, |
3653 | .height = 54, |
3654 | }, |
3655 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
3656 | }; |
3657 | |
3658 | static const struct display_timing ontat_kd50g21_40nt_a1_timing = { |
3659 | .pixelclock = { 30000000, 30000000, 50000000 }, |
3660 | .hactive = { 800, 800, 800 }, |
3661 | .hfront_porch = { 1, 40, 255 }, |
3662 | .hback_porch = { 1, 40, 87 }, |
3663 | .hsync_len = { 1, 48, 87 }, |
3664 | .vactive = { 480, 480, 480 }, |
3665 | .vfront_porch = { 1, 13, 255 }, |
3666 | .vback_porch = { 1, 29, 29 }, |
3667 | .vsync_len = { 3, 3, 31 }, |
3668 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
3669 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, |
3670 | }; |
3671 | |
3672 | static const struct panel_desc ontat_kd50g21_40nt_a1 = { |
3673 | .timings = &ontat_kd50g21_40nt_a1_timing, |
3674 | .num_timings = 1, |
3675 | .bpc = 8, |
3676 | .size = { |
3677 | .width = 108, |
3678 | .height = 65, |
3679 | }, |
3680 | .delay = { |
3681 | .prepare = 147, /* 5 VSDs */ |
3682 | .enable = 147, /* 5 VSDs */ |
3683 | .disable = 88, /* 3 VSDs */ |
3684 | .unprepare = 117, /* 4 VSDs */ |
3685 | }, |
3686 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
3687 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
3688 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
3689 | }; |
3690 | |
3691 | /* |
3692 | * 800x480 CVT. The panel appears to be quite accepting, at least as far as |
3693 | * pixel clocks, but this is the timing that was being used in the Adafruit |
3694 | * installation instructions. |
3695 | */ |
3696 | static const struct drm_display_mode ontat_yx700wv03_mode = { |
3697 | .clock = 29500, |
3698 | .hdisplay = 800, |
3699 | .hsync_start = 824, |
3700 | .hsync_end = 896, |
3701 | .htotal = 992, |
3702 | .vdisplay = 480, |
3703 | .vsync_start = 483, |
3704 | .vsync_end = 493, |
3705 | .vtotal = 500, |
3706 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
3707 | }; |
3708 | |
3709 | /* |
3710 | * Specification at: |
3711 | * https://www.adafruit.com/images/product-files/2406/c3163.pdf |
3712 | */ |
3713 | static const struct panel_desc ontat_yx700wv03 = { |
3714 | .modes = &ontat_yx700wv03_mode, |
3715 | .num_modes = 1, |
3716 | .bpc = 8, |
3717 | .size = { |
3718 | .width = 154, |
3719 | .height = 83, |
3720 | }, |
3721 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
3722 | }; |
3723 | |
3724 | static const struct drm_display_mode ortustech_com37h3m_mode = { |
3725 | .clock = 22230, |
3726 | .hdisplay = 480, |
3727 | .hsync_start = 480 + 40, |
3728 | .hsync_end = 480 + 40 + 10, |
3729 | .htotal = 480 + 40 + 10 + 40, |
3730 | .vdisplay = 640, |
3731 | .vsync_start = 640 + 4, |
3732 | .vsync_end = 640 + 4 + 2, |
3733 | .vtotal = 640 + 4 + 2 + 4, |
3734 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
3735 | }; |
3736 | |
3737 | static const struct panel_desc ortustech_com37h3m = { |
3738 | .modes = &ortustech_com37h3m_mode, |
3739 | .num_modes = 1, |
3740 | .bpc = 8, |
3741 | .size = { |
3742 | .width = 56, /* 56.16mm */ |
3743 | .height = 75, /* 74.88mm */ |
3744 | }, |
3745 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
3746 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | |
3747 | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, |
3748 | }; |
3749 | |
3750 | static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { |
3751 | .clock = 25000, |
3752 | .hdisplay = 480, |
3753 | .hsync_start = 480 + 10, |
3754 | .hsync_end = 480 + 10 + 10, |
3755 | .htotal = 480 + 10 + 10 + 15, |
3756 | .vdisplay = 800, |
3757 | .vsync_start = 800 + 3, |
3758 | .vsync_end = 800 + 3 + 3, |
3759 | .vtotal = 800 + 3 + 3 + 3, |
3760 | }; |
3761 | |
3762 | static const struct panel_desc ortustech_com43h4m85ulc = { |
3763 | .modes = &ortustech_com43h4m85ulc_mode, |
3764 | .num_modes = 1, |
3765 | .bpc = 6, |
3766 | .size = { |
3767 | .width = 56, |
3768 | .height = 93, |
3769 | }, |
3770 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
3771 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
3772 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
3773 | }; |
3774 | |
3775 | static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { |
3776 | .clock = 33000, |
3777 | .hdisplay = 800, |
3778 | .hsync_start = 800 + 210, |
3779 | .hsync_end = 800 + 210 + 30, |
3780 | .htotal = 800 + 210 + 30 + 16, |
3781 | .vdisplay = 480, |
3782 | .vsync_start = 480 + 22, |
3783 | .vsync_end = 480 + 22 + 13, |
3784 | .vtotal = 480 + 22 + 13 + 10, |
3785 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
3786 | }; |
3787 | |
3788 | static const struct panel_desc osddisplays_osd070t1718_19ts = { |
3789 | .modes = &osddisplays_osd070t1718_19ts_mode, |
3790 | .num_modes = 1, |
3791 | .bpc = 8, |
3792 | .size = { |
3793 | .width = 152, |
3794 | .height = 91, |
3795 | }, |
3796 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
3797 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | |
3798 | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, |
3799 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
3800 | }; |
3801 | |
3802 | static const struct drm_display_mode pda_91_00156_a0_mode = { |
3803 | .clock = 33300, |
3804 | .hdisplay = 800, |
3805 | .hsync_start = 800 + 1, |
3806 | .hsync_end = 800 + 1 + 64, |
3807 | .htotal = 800 + 1 + 64 + 64, |
3808 | .vdisplay = 480, |
3809 | .vsync_start = 480 + 1, |
3810 | .vsync_end = 480 + 1 + 23, |
3811 | .vtotal = 480 + 1 + 23 + 22, |
3812 | }; |
3813 | |
3814 | static const struct panel_desc pda_91_00156_a0 = { |
3815 | .modes = &pda_91_00156_a0_mode, |
3816 | .num_modes = 1, |
3817 | .size = { |
3818 | .width = 152, |
3819 | .height = 91, |
3820 | }, |
3821 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
3822 | }; |
3823 | |
3824 | static const struct drm_display_mode powertip_ph128800t004_zza01_mode = { |
3825 | .clock = 71150, |
3826 | .hdisplay = 1280, |
3827 | .hsync_start = 1280 + 48, |
3828 | .hsync_end = 1280 + 48 + 32, |
3829 | .htotal = 1280 + 48 + 32 + 80, |
3830 | .vdisplay = 800, |
3831 | .vsync_start = 800 + 9, |
3832 | .vsync_end = 800 + 9 + 8, |
3833 | .vtotal = 800 + 9 + 8 + 6, |
3834 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, |
3835 | }; |
3836 | |
3837 | static const struct panel_desc powertip_ph128800t004_zza01 = { |
3838 | .modes = &powertip_ph128800t004_zza01_mode, |
3839 | .num_modes = 1, |
3840 | .bpc = 8, |
3841 | .size = { |
3842 | .width = 216, |
3843 | .height = 135, |
3844 | }, |
3845 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
3846 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
3847 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3848 | }; |
3849 | |
3850 | static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { |
3851 | .clock = 66500, |
3852 | .hdisplay = 1280, |
3853 | .hsync_start = 1280 + 12, |
3854 | .hsync_end = 1280 + 12 + 20, |
3855 | .htotal = 1280 + 12 + 20 + 56, |
3856 | .vdisplay = 800, |
3857 | .vsync_start = 800 + 1, |
3858 | .vsync_end = 800 + 1 + 3, |
3859 | .vtotal = 800 + 1 + 3 + 20, |
3860 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, |
3861 | }; |
3862 | |
3863 | static const struct panel_desc powertip_ph128800t006_zhc01 = { |
3864 | .modes = &powertip_ph128800t006_zhc01_mode, |
3865 | .num_modes = 1, |
3866 | .bpc = 8, |
3867 | .size = { |
3868 | .width = 216, |
3869 | .height = 135, |
3870 | }, |
3871 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
3872 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
3873 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3874 | }; |
3875 | |
3876 | static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { |
3877 | .clock = 24750, |
3878 | .hdisplay = 800, |
3879 | .hsync_start = 800 + 54, |
3880 | .hsync_end = 800 + 54 + 2, |
3881 | .htotal = 800 + 54 + 2 + 44, |
3882 | .vdisplay = 480, |
3883 | .vsync_start = 480 + 49, |
3884 | .vsync_end = 480 + 49 + 2, |
3885 | .vtotal = 480 + 49 + 2 + 22, |
3886 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
3887 | }; |
3888 | |
3889 | static const struct panel_desc powertip_ph800480t013_idf02 = { |
3890 | .modes = &powertip_ph800480t013_idf02_mode, |
3891 | .num_modes = 1, |
3892 | .bpc = 8, |
3893 | .size = { |
3894 | .width = 152, |
3895 | .height = 91, |
3896 | }, |
3897 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | |
3898 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | |
3899 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, |
3900 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
3901 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
3902 | }; |
3903 | |
3904 | static const struct drm_display_mode primeview_pm070wl4_mode = { |
3905 | .clock = 32000, |
3906 | .hdisplay = 800, |
3907 | .hsync_start = 800 + 42, |
3908 | .hsync_end = 800 + 42 + 128, |
3909 | .htotal = 800 + 42 + 128 + 86, |
3910 | .vdisplay = 480, |
3911 | .vsync_start = 480 + 10, |
3912 | .vsync_end = 480 + 10 + 2, |
3913 | .vtotal = 480 + 10 + 2 + 33, |
3914 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
3915 | }; |
3916 | |
3917 | static const struct panel_desc primeview_pm070wl4 = { |
3918 | .modes = &primeview_pm070wl4_mode, |
3919 | .num_modes = 1, |
3920 | .bpc = 6, |
3921 | .size = { |
3922 | .width = 152, |
3923 | .height = 91, |
3924 | }, |
3925 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, |
3926 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
3927 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
3928 | }; |
3929 | |
3930 | static const struct drm_display_mode qd43003c0_40_mode = { |
3931 | .clock = 9000, |
3932 | .hdisplay = 480, |
3933 | .hsync_start = 480 + 8, |
3934 | .hsync_end = 480 + 8 + 4, |
3935 | .htotal = 480 + 8 + 4 + 39, |
3936 | .vdisplay = 272, |
3937 | .vsync_start = 272 + 4, |
3938 | .vsync_end = 272 + 4 + 10, |
3939 | .vtotal = 272 + 4 + 10 + 2, |
3940 | }; |
3941 | |
3942 | static const struct panel_desc qd43003c0_40 = { |
3943 | .modes = &qd43003c0_40_mode, |
3944 | .num_modes = 1, |
3945 | .bpc = 8, |
3946 | .size = { |
3947 | .width = 95, |
3948 | .height = 53, |
3949 | }, |
3950 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
3951 | }; |
3952 | |
3953 | static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { |
3954 | { /* 60 Hz */ |
3955 | .clock = 10800, |
3956 | .hdisplay = 480, |
3957 | .hsync_start = 480 + 77, |
3958 | .hsync_end = 480 + 77 + 41, |
3959 | .htotal = 480 + 77 + 41 + 2, |
3960 | .vdisplay = 272, |
3961 | .vsync_start = 272 + 16, |
3962 | .vsync_end = 272 + 16 + 10, |
3963 | .vtotal = 272 + 16 + 10 + 2, |
3964 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
3965 | }, |
3966 | { /* 50 Hz */ |
3967 | .clock = 10800, |
3968 | .hdisplay = 480, |
3969 | .hsync_start = 480 + 17, |
3970 | .hsync_end = 480 + 17 + 41, |
3971 | .htotal = 480 + 17 + 41 + 2, |
3972 | .vdisplay = 272, |
3973 | .vsync_start = 272 + 116, |
3974 | .vsync_end = 272 + 116 + 10, |
3975 | .vtotal = 272 + 116 + 10 + 2, |
3976 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
3977 | }, |
3978 | }; |
3979 | |
3980 | static const struct panel_desc qishenglong_gopher2b_lcd = { |
3981 | .modes = qishenglong_gopher2b_lcd_modes, |
3982 | .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), |
3983 | .bpc = 8, |
3984 | .size = { |
3985 | .width = 95, |
3986 | .height = 54, |
3987 | }, |
3988 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
3989 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
3990 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
3991 | }; |
3992 | |
3993 | static const struct display_timing rocktech_rk043fn48h_timing = { |
3994 | .pixelclock = { 6000000, 9000000, 12000000 }, |
3995 | .hactive = { 480, 480, 480 }, |
3996 | .hback_porch = { 8, 43, 43 }, |
3997 | .hfront_porch = { 2, 8, 10 }, |
3998 | .hsync_len = { 1, 1, 1 }, |
3999 | .vactive = { 272, 272, 272 }, |
4000 | .vback_porch = { 2, 12, 26 }, |
4001 | .vfront_porch = { 1, 4, 4 }, |
4002 | .vsync_len = { 1, 10, 10 }, |
4003 | .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | |
4004 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | |
4005 | DISPLAY_FLAGS_SYNC_POSEDGE, |
4006 | }; |
4007 | |
4008 | static const struct panel_desc rocktech_rk043fn48h = { |
4009 | .timings = &rocktech_rk043fn48h_timing, |
4010 | .num_timings = 1, |
4011 | .bpc = 8, |
4012 | .size = { |
4013 | .width = 95, |
4014 | .height = 54, |
4015 | }, |
4016 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
4017 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
4018 | }; |
4019 | |
4020 | static const struct display_timing rocktech_rk070er9427_timing = { |
4021 | .pixelclock = { 26400000, 33300000, 46800000 }, |
4022 | .hactive = { 800, 800, 800 }, |
4023 | .hfront_porch = { 16, 210, 354 }, |
4024 | .hback_porch = { 46, 46, 46 }, |
4025 | .hsync_len = { 1, 1, 1 }, |
4026 | .vactive = { 480, 480, 480 }, |
4027 | .vfront_porch = { 7, 22, 147 }, |
4028 | .vback_porch = { 23, 23, 23 }, |
4029 | .vsync_len = { 1, 1, 1 }, |
4030 | .flags = DISPLAY_FLAGS_DE_HIGH, |
4031 | }; |
4032 | |
4033 | static const struct panel_desc rocktech_rk070er9427 = { |
4034 | .timings = &rocktech_rk070er9427_timing, |
4035 | .num_timings = 1, |
4036 | .bpc = 6, |
4037 | .size = { |
4038 | .width = 154, |
4039 | .height = 86, |
4040 | }, |
4041 | .delay = { |
4042 | .prepare = 41, |
4043 | .enable = 50, |
4044 | .unprepare = 41, |
4045 | .disable = 50, |
4046 | }, |
4047 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
4048 | }; |
4049 | |
4050 | static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { |
4051 | .clock = 71100, |
4052 | .hdisplay = 1280, |
4053 | .hsync_start = 1280 + 48, |
4054 | .hsync_end = 1280 + 48 + 32, |
4055 | .htotal = 1280 + 48 + 32 + 80, |
4056 | .vdisplay = 800, |
4057 | .vsync_start = 800 + 2, |
4058 | .vsync_end = 800 + 2 + 5, |
4059 | .vtotal = 800 + 2 + 5 + 16, |
4060 | }; |
4061 | |
4062 | static const struct panel_desc rocktech_rk101ii01d_ct = { |
4063 | .modes = &rocktech_rk101ii01d_ct_mode, |
4064 | .bpc = 8, |
4065 | .num_modes = 1, |
4066 | .size = { |
4067 | .width = 217, |
4068 | .height = 136, |
4069 | }, |
4070 | .delay = { |
4071 | .prepare = 50, |
4072 | .disable = 50, |
4073 | }, |
4074 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
4075 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
4076 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4077 | }; |
4078 | |
4079 | static const struct display_timing samsung_ltl101al01_timing = { |
4080 | .pixelclock = { 66663000, 66663000, 66663000 }, |
4081 | .hactive = { 1280, 1280, 1280 }, |
4082 | .hfront_porch = { 18, 18, 18 }, |
4083 | .hback_porch = { 36, 36, 36 }, |
4084 | .hsync_len = { 16, 16, 16 }, |
4085 | .vactive = { 800, 800, 800 }, |
4086 | .vfront_porch = { 4, 4, 4 }, |
4087 | .vback_porch = { 16, 16, 16 }, |
4088 | .vsync_len = { 3, 3, 3 }, |
4089 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, |
4090 | }; |
4091 | |
4092 | static const struct panel_desc samsung_ltl101al01 = { |
4093 | .timings = &samsung_ltl101al01_timing, |
4094 | .num_timings = 1, |
4095 | .bpc = 8, |
4096 | .size = { |
4097 | .width = 217, |
4098 | .height = 135, |
4099 | }, |
4100 | .delay = { |
4101 | .prepare = 40, |
4102 | .enable = 300, |
4103 | .disable = 200, |
4104 | .unprepare = 600, |
4105 | }, |
4106 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
4107 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4108 | }; |
4109 | |
4110 | static const struct drm_display_mode samsung_ltn101nt05_mode = { |
4111 | .clock = 54030, |
4112 | .hdisplay = 1024, |
4113 | .hsync_start = 1024 + 24, |
4114 | .hsync_end = 1024 + 24 + 136, |
4115 | .htotal = 1024 + 24 + 136 + 160, |
4116 | .vdisplay = 600, |
4117 | .vsync_start = 600 + 3, |
4118 | .vsync_end = 600 + 3 + 6, |
4119 | .vtotal = 600 + 3 + 6 + 61, |
4120 | }; |
4121 | |
4122 | static const struct panel_desc samsung_ltn101nt05 = { |
4123 | .modes = &samsung_ltn101nt05_mode, |
4124 | .num_modes = 1, |
4125 | .bpc = 6, |
4126 | .size = { |
4127 | .width = 223, |
4128 | .height = 125, |
4129 | }, |
4130 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
4131 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
4132 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4133 | }; |
4134 | |
4135 | static const struct display_timing satoz_sat050at40h12r2_timing = { |
4136 | .pixelclock = {33300000, 33300000, 50000000}, |
4137 | .hactive = {800, 800, 800}, |
4138 | .hfront_porch = {16, 210, 354}, |
4139 | .hback_porch = {46, 46, 46}, |
4140 | .hsync_len = {1, 1, 40}, |
4141 | .vactive = {480, 480, 480}, |
4142 | .vfront_porch = {7, 22, 147}, |
4143 | .vback_porch = {23, 23, 23}, |
4144 | .vsync_len = {1, 1, 20}, |
4145 | }; |
4146 | |
4147 | static const struct panel_desc satoz_sat050at40h12r2 = { |
4148 | .timings = &satoz_sat050at40h12r2_timing, |
4149 | .num_timings = 1, |
4150 | .bpc = 8, |
4151 | .size = { |
4152 | .width = 108, |
4153 | .height = 65, |
4154 | }, |
4155 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
4156 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4157 | }; |
4158 | |
4159 | static const struct drm_display_mode sharp_lq070y3dg3b_mode = { |
4160 | .clock = 33260, |
4161 | .hdisplay = 800, |
4162 | .hsync_start = 800 + 64, |
4163 | .hsync_end = 800 + 64 + 128, |
4164 | .htotal = 800 + 64 + 128 + 64, |
4165 | .vdisplay = 480, |
4166 | .vsync_start = 480 + 8, |
4167 | .vsync_end = 480 + 8 + 2, |
4168 | .vtotal = 480 + 8 + 2 + 35, |
4169 | .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, |
4170 | }; |
4171 | |
4172 | static const struct panel_desc sharp_lq070y3dg3b = { |
4173 | .modes = &sharp_lq070y3dg3b_mode, |
4174 | .num_modes = 1, |
4175 | .bpc = 8, |
4176 | .size = { |
4177 | .width = 152, /* 152.4mm */ |
4178 | .height = 91, /* 91.4mm */ |
4179 | }, |
4180 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
4181 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | |
4182 | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, |
4183 | }; |
4184 | |
4185 | static const struct drm_display_mode sharp_lq035q7db03_mode = { |
4186 | .clock = 5500, |
4187 | .hdisplay = 240, |
4188 | .hsync_start = 240 + 16, |
4189 | .hsync_end = 240 + 16 + 7, |
4190 | .htotal = 240 + 16 + 7 + 5, |
4191 | .vdisplay = 320, |
4192 | .vsync_start = 320 + 9, |
4193 | .vsync_end = 320 + 9 + 1, |
4194 | .vtotal = 320 + 9 + 1 + 7, |
4195 | }; |
4196 | |
4197 | static const struct panel_desc sharp_lq035q7db03 = { |
4198 | .modes = &sharp_lq035q7db03_mode, |
4199 | .num_modes = 1, |
4200 | .bpc = 6, |
4201 | .size = { |
4202 | .width = 54, |
4203 | .height = 72, |
4204 | }, |
4205 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
4206 | }; |
4207 | |
4208 | static const struct display_timing sharp_lq101k1ly04_timing = { |
4209 | .pixelclock = { 60000000, 65000000, 80000000 }, |
4210 | .hactive = { 1280, 1280, 1280 }, |
4211 | .hfront_porch = { 20, 20, 20 }, |
4212 | .hback_porch = { 20, 20, 20 }, |
4213 | .hsync_len = { 10, 10, 10 }, |
4214 | .vactive = { 800, 800, 800 }, |
4215 | .vfront_porch = { 4, 4, 4 }, |
4216 | .vback_porch = { 4, 4, 4 }, |
4217 | .vsync_len = { 4, 4, 4 }, |
4218 | .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, |
4219 | }; |
4220 | |
4221 | static const struct panel_desc sharp_lq101k1ly04 = { |
4222 | .timings = &sharp_lq101k1ly04_timing, |
4223 | .num_timings = 1, |
4224 | .bpc = 8, |
4225 | .size = { |
4226 | .width = 217, |
4227 | .height = 136, |
4228 | }, |
4229 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, |
4230 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4231 | }; |
4232 | |
4233 | static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { |
4234 | { /* 50 Hz */ |
4235 | .clock = 3000, |
4236 | .hdisplay = 240, |
4237 | .hsync_start = 240 + 58, |
4238 | .hsync_end = 240 + 58 + 1, |
4239 | .htotal = 240 + 58 + 1 + 1, |
4240 | .vdisplay = 160, |
4241 | .vsync_start = 160 + 24, |
4242 | .vsync_end = 160 + 24 + 10, |
4243 | .vtotal = 160 + 24 + 10 + 6, |
4244 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, |
4245 | }, |
4246 | { /* 60 Hz */ |
4247 | .clock = 3000, |
4248 | .hdisplay = 240, |
4249 | .hsync_start = 240 + 8, |
4250 | .hsync_end = 240 + 8 + 1, |
4251 | .htotal = 240 + 8 + 1 + 1, |
4252 | .vdisplay = 160, |
4253 | .vsync_start = 160 + 24, |
4254 | .vsync_end = 160 + 24 + 10, |
4255 | .vtotal = 160 + 24 + 10 + 6, |
4256 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, |
4257 | }, |
4258 | }; |
4259 | |
4260 | static const struct panel_desc sharp_ls020b1dd01d = { |
4261 | .modes = sharp_ls020b1dd01d_modes, |
4262 | .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), |
4263 | .bpc = 6, |
4264 | .size = { |
4265 | .width = 42, |
4266 | .height = 28, |
4267 | }, |
4268 | .bus_format = MEDIA_BUS_FMT_RGB565_1X16, |
4269 | .bus_flags = DRM_BUS_FLAG_DE_HIGH |
4270 | | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
4271 | | DRM_BUS_FLAG_SHARP_SIGNALS, |
4272 | }; |
4273 | |
4274 | static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { |
4275 | .clock = 33300, |
4276 | .hdisplay = 800, |
4277 | .hsync_start = 800 + 1, |
4278 | .hsync_end = 800 + 1 + 64, |
4279 | .htotal = 800 + 1 + 64 + 64, |
4280 | .vdisplay = 480, |
4281 | .vsync_start = 480 + 1, |
4282 | .vsync_end = 480 + 1 + 23, |
4283 | .vtotal = 480 + 1 + 23 + 22, |
4284 | }; |
4285 | |
4286 | static const struct panel_desc shelly_sca07010_bfn_lnn = { |
4287 | .modes = &shelly_sca07010_bfn_lnn_mode, |
4288 | .num_modes = 1, |
4289 | .size = { |
4290 | .width = 152, |
4291 | .height = 91, |
4292 | }, |
4293 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
4294 | }; |
4295 | |
4296 | static const struct drm_display_mode starry_kr070pe2t_mode = { |
4297 | .clock = 33000, |
4298 | .hdisplay = 800, |
4299 | .hsync_start = 800 + 209, |
4300 | .hsync_end = 800 + 209 + 1, |
4301 | .htotal = 800 + 209 + 1 + 45, |
4302 | .vdisplay = 480, |
4303 | .vsync_start = 480 + 22, |
4304 | .vsync_end = 480 + 22 + 1, |
4305 | .vtotal = 480 + 22 + 1 + 22, |
4306 | }; |
4307 | |
4308 | static const struct panel_desc starry_kr070pe2t = { |
4309 | .modes = &starry_kr070pe2t_mode, |
4310 | .num_modes = 1, |
4311 | .bpc = 8, |
4312 | .size = { |
4313 | .width = 152, |
4314 | .height = 86, |
4315 | }, |
4316 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
4317 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, |
4318 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
4319 | }; |
4320 | |
4321 | static const struct display_timing startek_kd070wvfpa_mode = { |
4322 | .pixelclock = { 25200000, 27200000, 30500000 }, |
4323 | .hactive = { 800, 800, 800 }, |
4324 | .hfront_porch = { 19, 44, 115 }, |
4325 | .hback_porch = { 5, 16, 101 }, |
4326 | .hsync_len = { 1, 2, 100 }, |
4327 | .vactive = { 480, 480, 480 }, |
4328 | .vfront_porch = { 5, 43, 67 }, |
4329 | .vback_porch = { 5, 5, 67 }, |
4330 | .vsync_len = { 1, 2, 66 }, |
4331 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
4332 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | |
4333 | DISPLAY_FLAGS_SYNC_POSEDGE, |
4334 | }; |
4335 | |
4336 | static const struct panel_desc startek_kd070wvfpa = { |
4337 | .timings = &startek_kd070wvfpa_mode, |
4338 | .num_timings = 1, |
4339 | .bpc = 8, |
4340 | .size = { |
4341 | .width = 152, |
4342 | .height = 91, |
4343 | }, |
4344 | .delay = { |
4345 | .prepare = 20, |
4346 | .enable = 200, |
4347 | .disable = 200, |
4348 | }, |
4349 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
4350 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
4351 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | |
4352 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | |
4353 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, |
4354 | }; |
4355 | |
4356 | static const struct display_timing tsd_tst043015cmhx_timing = { |
4357 | .pixelclock = { 5000000, 9000000, 12000000 }, |
4358 | .hactive = { 480, 480, 480 }, |
4359 | .hfront_porch = { 4, 5, 65 }, |
4360 | .hback_porch = { 36, 40, 255 }, |
4361 | .hsync_len = { 1, 1, 1 }, |
4362 | .vactive = { 272, 272, 272 }, |
4363 | .vfront_porch = { 2, 8, 97 }, |
4364 | .vback_porch = { 3, 8, 31 }, |
4365 | .vsync_len = { 1, 1, 1 }, |
4366 | |
4367 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
4368 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, |
4369 | }; |
4370 | |
4371 | static const struct panel_desc tsd_tst043015cmhx = { |
4372 | .timings = &tsd_tst043015cmhx_timing, |
4373 | .num_timings = 1, |
4374 | .bpc = 8, |
4375 | .size = { |
4376 | .width = 105, |
4377 | .height = 67, |
4378 | }, |
4379 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
4380 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
4381 | }; |
4382 | |
4383 | static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { |
4384 | .clock = 30000, |
4385 | .hdisplay = 800, |
4386 | .hsync_start = 800 + 39, |
4387 | .hsync_end = 800 + 39 + 47, |
4388 | .htotal = 800 + 39 + 47 + 39, |
4389 | .vdisplay = 480, |
4390 | .vsync_start = 480 + 13, |
4391 | .vsync_end = 480 + 13 + 2, |
4392 | .vtotal = 480 + 13 + 2 + 29, |
4393 | }; |
4394 | |
4395 | static const struct panel_desc tfc_s9700rtwv43tr_01b = { |
4396 | .modes = &tfc_s9700rtwv43tr_01b_mode, |
4397 | .num_modes = 1, |
4398 | .bpc = 8, |
4399 | .size = { |
4400 | .width = 155, |
4401 | .height = 90, |
4402 | }, |
4403 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
4404 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
4405 | }; |
4406 | |
4407 | static const struct display_timing tianma_tm070jdhg30_timing = { |
4408 | .pixelclock = { 62600000, 68200000, 78100000 }, |
4409 | .hactive = { 1280, 1280, 1280 }, |
4410 | .hfront_porch = { 15, 64, 159 }, |
4411 | .hback_porch = { 5, 5, 5 }, |
4412 | .hsync_len = { 1, 1, 256 }, |
4413 | .vactive = { 800, 800, 800 }, |
4414 | .vfront_porch = { 3, 40, 99 }, |
4415 | .vback_porch = { 2, 2, 2 }, |
4416 | .vsync_len = { 1, 1, 128 }, |
4417 | .flags = DISPLAY_FLAGS_DE_HIGH, |
4418 | }; |
4419 | |
4420 | static const struct panel_desc tianma_tm070jdhg30 = { |
4421 | .timings = &tianma_tm070jdhg30_timing, |
4422 | .num_timings = 1, |
4423 | .bpc = 8, |
4424 | .size = { |
4425 | .width = 151, |
4426 | .height = 95, |
4427 | }, |
4428 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
4429 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4430 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
4431 | }; |
4432 | |
4433 | static const struct panel_desc tianma_tm070jvhg33 = { |
4434 | .timings = &tianma_tm070jdhg30_timing, |
4435 | .num_timings = 1, |
4436 | .bpc = 8, |
4437 | .size = { |
4438 | .width = 150, |
4439 | .height = 94, |
4440 | }, |
4441 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
4442 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4443 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
4444 | }; |
4445 | |
4446 | /* |
4447 | * The TM070JDHG34-00 datasheet computes total blanking as back porch + |
4448 | * front porch, not including sync pulse width. This is for both H and |
4449 | * V. To make the total blanking and period correct, subtract the pulse |
4450 | * width from the front porch. |
4451 | * |
4452 | * This works well for the Min and Typ values, but for Max values the sync |
4453 | * pulse width is higher than back porch + front porch, so work around that |
4454 | * by reducing the Max sync length value to 1 and then treating the Max |
4455 | * porches as in the Min and Typ cases. |
4456 | * |
4457 | * Exact datasheet values are added as a comment where they differ from the |
4458 | * ones implemented for the above reason. |
4459 | * |
4460 | * The P0700WXF1MBAA datasheet is even less detailed, only listing period |
4461 | * and total blanking time, however the resulting values are the same as |
4462 | * the TM070JDHG34-00. |
4463 | */ |
4464 | static const struct display_timing tianma_tm070jdhg34_00_timing = { |
4465 | .pixelclock = { 68400000, 71900000, 78100000 }, |
4466 | .hactive = { 1280, 1280, 1280 }, |
4467 | .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ |
4468 | .hback_porch = { 5, 5, 5 }, |
4469 | .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ |
4470 | .vactive = { 800, 800, 800 }, |
4471 | .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ |
4472 | .vback_porch = { 2, 2, 2 }, |
4473 | .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ |
4474 | .flags = DISPLAY_FLAGS_DE_HIGH, |
4475 | }; |
4476 | |
4477 | static const struct panel_desc tianma_tm070jdhg34_00 = { |
4478 | .timings = &tianma_tm070jdhg34_00_timing, |
4479 | .num_timings = 1, |
4480 | .bpc = 8, |
4481 | .size = { |
4482 | .width = 150, /* 149.76 */ |
4483 | .height = 94, /* 93.60 */ |
4484 | }, |
4485 | .delay = { |
4486 | .prepare = 15, /* Tp1 */ |
4487 | .enable = 150, /* Tp2 */ |
4488 | .disable = 150, /* Tp4 */ |
4489 | .unprepare = 120, /* Tp3 */ |
4490 | }, |
4491 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
4492 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4493 | }; |
4494 | |
4495 | static const struct panel_desc tianma_p0700wxf1mbaa = { |
4496 | .timings = &tianma_tm070jdhg34_00_timing, |
4497 | .num_timings = 1, |
4498 | .bpc = 8, |
4499 | .size = { |
4500 | .width = 150, /* 149.76 */ |
4501 | .height = 94, /* 93.60 */ |
4502 | }, |
4503 | .delay = { |
4504 | .prepare = 18, /* Tr + Tp1 */ |
4505 | .enable = 152, /* Tp2 + Tp5 */ |
4506 | .disable = 152, /* Tp6 + Tp4 */ |
4507 | .unprepare = 120, /* Tp3 */ |
4508 | }, |
4509 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
4510 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4511 | }; |
4512 | |
4513 | static const struct display_timing tianma_tm070rvhg71_timing = { |
4514 | .pixelclock = { 27700000, 29200000, 39600000 }, |
4515 | .hactive = { 800, 800, 800 }, |
4516 | .hfront_porch = { 12, 40, 212 }, |
4517 | .hback_porch = { 88, 88, 88 }, |
4518 | .hsync_len = { 1, 1, 40 }, |
4519 | .vactive = { 480, 480, 480 }, |
4520 | .vfront_porch = { 1, 13, 88 }, |
4521 | .vback_porch = { 32, 32, 32 }, |
4522 | .vsync_len = { 1, 1, 3 }, |
4523 | .flags = DISPLAY_FLAGS_DE_HIGH, |
4524 | }; |
4525 | |
4526 | static const struct panel_desc tianma_tm070rvhg71 = { |
4527 | .timings = &tianma_tm070rvhg71_timing, |
4528 | .num_timings = 1, |
4529 | .bpc = 8, |
4530 | .size = { |
4531 | .width = 154, |
4532 | .height = 86, |
4533 | }, |
4534 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
4535 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4536 | }; |
4537 | |
4538 | static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { |
4539 | { |
4540 | .clock = 10000, |
4541 | .hdisplay = 320, |
4542 | .hsync_start = 320 + 50, |
4543 | .hsync_end = 320 + 50 + 6, |
4544 | .htotal = 320 + 50 + 6 + 38, |
4545 | .vdisplay = 240, |
4546 | .vsync_start = 240 + 3, |
4547 | .vsync_end = 240 + 3 + 1, |
4548 | .vtotal = 240 + 3 + 1 + 17, |
4549 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
4550 | }, |
4551 | }; |
4552 | |
4553 | static const struct panel_desc ti_nspire_cx_lcd_panel = { |
4554 | .modes = ti_nspire_cx_lcd_mode, |
4555 | .num_modes = 1, |
4556 | .bpc = 8, |
4557 | .size = { |
4558 | .width = 65, |
4559 | .height = 49, |
4560 | }, |
4561 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
4562 | .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, |
4563 | }; |
4564 | |
4565 | static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { |
4566 | { |
4567 | .clock = 10000, |
4568 | .hdisplay = 320, |
4569 | .hsync_start = 320 + 6, |
4570 | .hsync_end = 320 + 6 + 6, |
4571 | .htotal = 320 + 6 + 6 + 6, |
4572 | .vdisplay = 240, |
4573 | .vsync_start = 240 + 0, |
4574 | .vsync_end = 240 + 0 + 1, |
4575 | .vtotal = 240 + 0 + 1 + 0, |
4576 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, |
4577 | }, |
4578 | }; |
4579 | |
4580 | static const struct panel_desc ti_nspire_classic_lcd_panel = { |
4581 | .modes = ti_nspire_classic_lcd_mode, |
4582 | .num_modes = 1, |
4583 | /* The grayscale panel has 8 bit for the color .. Y (black) */ |
4584 | .bpc = 8, |
4585 | .size = { |
4586 | .width = 71, |
4587 | .height = 53, |
4588 | }, |
4589 | /* This is the grayscale bus format */ |
4590 | .bus_format = MEDIA_BUS_FMT_Y8_1X8, |
4591 | .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
4592 | }; |
4593 | |
4594 | static const struct display_timing topland_tian_g07017_01_timing = { |
4595 | .pixelclock = { 44900000, 51200000, 63000000 }, |
4596 | .hactive = { 1024, 1024, 1024 }, |
4597 | .hfront_porch = { 16, 160, 216 }, |
4598 | .hback_porch = { 160, 160, 160 }, |
4599 | .hsync_len = { 1, 1, 140 }, |
4600 | .vactive = { 600, 600, 600 }, |
4601 | .vfront_porch = { 1, 12, 127 }, |
4602 | .vback_porch = { 23, 23, 23 }, |
4603 | .vsync_len = { 1, 1, 20 }, |
4604 | }; |
4605 | |
4606 | static const struct panel_desc topland_tian_g07017_01 = { |
4607 | .timings = &topland_tian_g07017_01_timing, |
4608 | .num_timings = 1, |
4609 | .bpc = 8, |
4610 | .size = { |
4611 | .width = 154, |
4612 | .height = 86, |
4613 | }, |
4614 | .delay = { |
4615 | .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ |
4616 | .enable = 100, /* 6.4 - Power on: 6 VSyncs */ |
4617 | .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ |
4618 | .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ |
4619 | }, |
4620 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
4621 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4622 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
4623 | }; |
4624 | |
4625 | static const struct drm_display_mode toshiba_lt089ac29000_mode = { |
4626 | .clock = 79500, |
4627 | .hdisplay = 1280, |
4628 | .hsync_start = 1280 + 192, |
4629 | .hsync_end = 1280 + 192 + 128, |
4630 | .htotal = 1280 + 192 + 128 + 64, |
4631 | .vdisplay = 768, |
4632 | .vsync_start = 768 + 20, |
4633 | .vsync_end = 768 + 20 + 7, |
4634 | .vtotal = 768 + 20 + 7 + 3, |
4635 | }; |
4636 | |
4637 | static const struct panel_desc toshiba_lt089ac29000 = { |
4638 | .modes = &toshiba_lt089ac29000_mode, |
4639 | .num_modes = 1, |
4640 | .size = { |
4641 | .width = 194, |
4642 | .height = 116, |
4643 | }, |
4644 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, |
4645 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
4646 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4647 | }; |
4648 | |
4649 | static const struct drm_display_mode tpk_f07a_0102_mode = { |
4650 | .clock = 33260, |
4651 | .hdisplay = 800, |
4652 | .hsync_start = 800 + 40, |
4653 | .hsync_end = 800 + 40 + 128, |
4654 | .htotal = 800 + 40 + 128 + 88, |
4655 | .vdisplay = 480, |
4656 | .vsync_start = 480 + 10, |
4657 | .vsync_end = 480 + 10 + 2, |
4658 | .vtotal = 480 + 10 + 2 + 33, |
4659 | }; |
4660 | |
4661 | static const struct panel_desc tpk_f07a_0102 = { |
4662 | .modes = &tpk_f07a_0102_mode, |
4663 | .num_modes = 1, |
4664 | .size = { |
4665 | .width = 152, |
4666 | .height = 91, |
4667 | }, |
4668 | .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
4669 | }; |
4670 | |
4671 | static const struct drm_display_mode tpk_f10a_0102_mode = { |
4672 | .clock = 45000, |
4673 | .hdisplay = 1024, |
4674 | .hsync_start = 1024 + 176, |
4675 | .hsync_end = 1024 + 176 + 5, |
4676 | .htotal = 1024 + 176 + 5 + 88, |
4677 | .vdisplay = 600, |
4678 | .vsync_start = 600 + 20, |
4679 | .vsync_end = 600 + 20 + 5, |
4680 | .vtotal = 600 + 20 + 5 + 25, |
4681 | }; |
4682 | |
4683 | static const struct panel_desc tpk_f10a_0102 = { |
4684 | .modes = &tpk_f10a_0102_mode, |
4685 | .num_modes = 1, |
4686 | .size = { |
4687 | .width = 223, |
4688 | .height = 125, |
4689 | }, |
4690 | }; |
4691 | |
4692 | static const struct display_timing urt_umsh_8596md_timing = { |
4693 | .pixelclock = { 33260000, 33260000, 33260000 }, |
4694 | .hactive = { 800, 800, 800 }, |
4695 | .hfront_porch = { 41, 41, 41 }, |
4696 | .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, |
4697 | .hsync_len = { 71, 128, 128 }, |
4698 | .vactive = { 480, 480, 480 }, |
4699 | .vfront_porch = { 10, 10, 10 }, |
4700 | .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, |
4701 | .vsync_len = { 2, 2, 2 }, |
4702 | .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | |
4703 | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, |
4704 | }; |
4705 | |
4706 | static const struct panel_desc urt_umsh_8596md_lvds = { |
4707 | .timings = &urt_umsh_8596md_timing, |
4708 | .num_timings = 1, |
4709 | .bpc = 6, |
4710 | .size = { |
4711 | .width = 152, |
4712 | .height = 91, |
4713 | }, |
4714 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
4715 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4716 | }; |
4717 | |
4718 | static const struct panel_desc urt_umsh_8596md_parallel = { |
4719 | .timings = &urt_umsh_8596md_timing, |
4720 | .num_timings = 1, |
4721 | .bpc = 6, |
4722 | .size = { |
4723 | .width = 152, |
4724 | .height = 91, |
4725 | }, |
4726 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
4727 | }; |
4728 | |
4729 | static const struct drm_display_mode vivax_tpc9150_panel_mode = { |
4730 | .clock = 60000, |
4731 | .hdisplay = 1024, |
4732 | .hsync_start = 1024 + 160, |
4733 | .hsync_end = 1024 + 160 + 100, |
4734 | .htotal = 1024 + 160 + 100 + 60, |
4735 | .vdisplay = 600, |
4736 | .vsync_start = 600 + 12, |
4737 | .vsync_end = 600 + 12 + 10, |
4738 | .vtotal = 600 + 12 + 10 + 13, |
4739 | }; |
4740 | |
4741 | static const struct panel_desc vivax_tpc9150_panel = { |
4742 | .modes = &vivax_tpc9150_panel_mode, |
4743 | .num_modes = 1, |
4744 | .bpc = 6, |
4745 | .size = { |
4746 | .width = 200, |
4747 | .height = 115, |
4748 | }, |
4749 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
4750 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
4751 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4752 | }; |
4753 | |
4754 | static const struct drm_display_mode vl050_8048nt_c01_mode = { |
4755 | .clock = 33333, |
4756 | .hdisplay = 800, |
4757 | .hsync_start = 800 + 210, |
4758 | .hsync_end = 800 + 210 + 20, |
4759 | .htotal = 800 + 210 + 20 + 46, |
4760 | .vdisplay = 480, |
4761 | .vsync_start = 480 + 22, |
4762 | .vsync_end = 480 + 22 + 10, |
4763 | .vtotal = 480 + 22 + 10 + 23, |
4764 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
4765 | }; |
4766 | |
4767 | static const struct panel_desc vl050_8048nt_c01 = { |
4768 | .modes = &vl050_8048nt_c01_mode, |
4769 | .num_modes = 1, |
4770 | .bpc = 8, |
4771 | .size = { |
4772 | .width = 120, |
4773 | .height = 76, |
4774 | }, |
4775 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
4776 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
4777 | }; |
4778 | |
4779 | static const struct drm_display_mode winstar_wf35ltiacd_mode = { |
4780 | .clock = 6410, |
4781 | .hdisplay = 320, |
4782 | .hsync_start = 320 + 20, |
4783 | .hsync_end = 320 + 20 + 30, |
4784 | .htotal = 320 + 20 + 30 + 38, |
4785 | .vdisplay = 240, |
4786 | .vsync_start = 240 + 4, |
4787 | .vsync_end = 240 + 4 + 3, |
4788 | .vtotal = 240 + 4 + 3 + 15, |
4789 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
4790 | }; |
4791 | |
4792 | static const struct panel_desc winstar_wf35ltiacd = { |
4793 | .modes = &winstar_wf35ltiacd_mode, |
4794 | .num_modes = 1, |
4795 | .bpc = 8, |
4796 | .size = { |
4797 | .width = 70, |
4798 | .height = 53, |
4799 | }, |
4800 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
4801 | }; |
4802 | |
4803 | static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { |
4804 | .clock = 51200, |
4805 | .hdisplay = 1024, |
4806 | .hsync_start = 1024 + 100, |
4807 | .hsync_end = 1024 + 100 + 100, |
4808 | .htotal = 1024 + 100 + 100 + 120, |
4809 | .vdisplay = 600, |
4810 | .vsync_start = 600 + 10, |
4811 | .vsync_end = 600 + 10 + 10, |
4812 | .vtotal = 600 + 10 + 10 + 15, |
4813 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, |
4814 | }; |
4815 | |
4816 | static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { |
4817 | .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, |
4818 | .num_modes = 1, |
4819 | .bpc = 8, |
4820 | .size = { |
4821 | .width = 154, |
4822 | .height = 90, |
4823 | }, |
4824 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
4825 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
4826 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4827 | }; |
4828 | |
4829 | static const struct drm_display_mode mchp_ac69t88a_mode = { |
4830 | .clock = 25000, |
4831 | .hdisplay = 800, |
4832 | .hsync_start = 800 + 88, |
4833 | .hsync_end = 800 + 88 + 5, |
4834 | .htotal = 800 + 88 + 5 + 40, |
4835 | .vdisplay = 480, |
4836 | .vsync_start = 480 + 23, |
4837 | .vsync_end = 480 + 23 + 5, |
4838 | .vtotal = 480 + 23 + 5 + 1, |
4839 | }; |
4840 | |
4841 | static const struct panel_desc mchp_ac69t88a = { |
4842 | .modes = &mchp_ac69t88a_mode, |
4843 | .num_modes = 1, |
4844 | .bpc = 8, |
4845 | .size = { |
4846 | .width = 108, |
4847 | .height = 65, |
4848 | }, |
4849 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
4850 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, |
4851 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4852 | }; |
4853 | |
4854 | static const struct drm_display_mode arm_rtsm_mode[] = { |
4855 | { |
4856 | .clock = 65000, |
4857 | .hdisplay = 1024, |
4858 | .hsync_start = 1024 + 24, |
4859 | .hsync_end = 1024 + 24 + 136, |
4860 | .htotal = 1024 + 24 + 136 + 160, |
4861 | .vdisplay = 768, |
4862 | .vsync_start = 768 + 3, |
4863 | .vsync_end = 768 + 3 + 6, |
4864 | .vtotal = 768 + 3 + 6 + 29, |
4865 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
4866 | }, |
4867 | }; |
4868 | |
4869 | static const struct panel_desc arm_rtsm = { |
4870 | .modes = arm_rtsm_mode, |
4871 | .num_modes = 1, |
4872 | .bpc = 8, |
4873 | .size = { |
4874 | .width = 400, |
4875 | .height = 300, |
4876 | }, |
4877 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
4878 | }; |
4879 | |
4880 | static const struct of_device_id platform_of_match[] = { |
4881 | { |
4882 | .compatible = "ampire,am-1280800n3tzqw-t00h", |
4883 | .data = &ire_am_1280800n3tzqw_t00h, |
4884 | }, { |
4885 | .compatible = "ampire,am-480272h3tmqw-t01h", |
4886 | .data = &ire_am_480272h3tmqw_t01h, |
4887 | }, { |
4888 | .compatible = "ampire,am-800480l1tmqw-t00h", |
4889 | .data = &ire_am_800480l1tmqw_t00h, |
4890 | }, { |
4891 | .compatible = "ampire,am800480r3tmqwa1h", |
4892 | .data = &ire_am800480r3tmqwa1h, |
4893 | }, { |
4894 | .compatible = "ampire,am800600p5tmqw-tb8h", |
4895 | .data = &ire_am800600p5tmqwtb8h, |
4896 | }, { |
4897 | .compatible = "arm,rtsm-display", |
4898 | .data = &arm_rtsm, |
4899 | }, { |
4900 | .compatible = "armadeus,st0700-adapt", |
4901 | .data = &armadeus_st0700_adapt, |
4902 | }, { |
4903 | .compatible = "auo,b101aw03", |
4904 | .data = &auo_b101aw03, |
4905 | }, { |
4906 | .compatible = "auo,b101xtn01", |
4907 | .data = &auo_b101xtn01, |
4908 | }, { |
4909 | .compatible = "auo,b116xw03", |
4910 | .data = &auo_b116xw03, |
4911 | }, { |
4912 | .compatible = "auo,g070vvn01", |
4913 | .data = &auo_g070vvn01, |
4914 | }, { |
4915 | .compatible = "auo,g101evn010", |
4916 | .data = &auo_g101evn010, |
4917 | }, { |
4918 | .compatible = "auo,g104sn02", |
4919 | .data = &auo_g104sn02, |
4920 | }, { |
4921 | .compatible = "auo,g104stn01", |
4922 | .data = &auo_g104stn01, |
4923 | }, { |
4924 | .compatible = "auo,g121ean01", |
4925 | .data = &auo_g121ean01, |
4926 | }, { |
4927 | .compatible = "auo,g133han01", |
4928 | .data = &auo_g133han01, |
4929 | }, { |
4930 | .compatible = "auo,g156han04", |
4931 | .data = &auo_g156han04, |
4932 | }, { |
4933 | .compatible = "auo,g156xtn01", |
4934 | .data = &auo_g156xtn01, |
4935 | }, { |
4936 | .compatible = "auo,g185han01", |
4937 | .data = &auo_g185han01, |
4938 | }, { |
4939 | .compatible = "auo,g190ean01", |
4940 | .data = &auo_g190ean01, |
4941 | }, { |
4942 | .compatible = "auo,p320hvn03", |
4943 | .data = &auo_p320hvn03, |
4944 | }, { |
4945 | .compatible = "auo,t215hvn01", |
4946 | .data = &auo_t215hvn01, |
4947 | }, { |
4948 | .compatible = "avic,tm070ddh03", |
4949 | .data = &avic_tm070ddh03, |
4950 | }, { |
4951 | .compatible = "bananapi,s070wv20-ct16", |
4952 | .data = &bananapi_s070wv20_ct16, |
4953 | }, { |
4954 | .compatible = "boe,av101hdt-a10", |
4955 | .data = &boe_av101hdt_a10, |
4956 | }, { |
4957 | .compatible = "boe,av123z7m-n17", |
4958 | .data = &boe_av123z7m_n17, |
4959 | }, { |
4960 | .compatible = "boe,bp082wx1-100", |
4961 | .data = &boe_bp082wx1_100, |
4962 | }, { |
4963 | .compatible = "boe,bp101wx1-100", |
4964 | .data = &boe_bp101wx1_100, |
4965 | }, { |
4966 | .compatible = "boe,ev121wxm-n10-1850", |
4967 | .data = &boe_ev121wxm_n10_1850, |
4968 | }, { |
4969 | .compatible = "boe,hv070wsa-100", |
4970 | .data = &boe_hv070wsa |
4971 | }, { |
4972 | .compatible = "cct,cmt430b19n00", |
4973 | .data = &cct_cmt430b19n00, |
4974 | }, { |
4975 | .compatible = "cdtech,s043wq26h-ct7", |
4976 | .data = &cdtech_s043wq26h_ct7, |
4977 | }, { |
4978 | .compatible = "cdtech,s070pws19hp-fc21", |
4979 | .data = &cdtech_s070pws19hp_fc21, |
4980 | }, { |
4981 | .compatible = "cdtech,s070swv29hg-dc44", |
4982 | .data = &cdtech_s070swv29hg_dc44, |
4983 | }, { |
4984 | .compatible = "cdtech,s070wv95-ct16", |
4985 | .data = &cdtech_s070wv95_ct16, |
4986 | }, { |
4987 | .compatible = "chefree,ch101olhlwh-002", |
4988 | .data = &chefree_ch101olhlwh_002, |
4989 | }, { |
4990 | .compatible = "chunghwa,claa070wp03xg", |
4991 | .data = &chunghwa_claa070wp03xg, |
4992 | }, { |
4993 | .compatible = "chunghwa,claa101wa01a", |
4994 | .data = &chunghwa_claa101wa01a |
4995 | }, { |
4996 | .compatible = "chunghwa,claa101wb01", |
4997 | .data = &chunghwa_claa101wb01 |
4998 | }, { |
4999 | .compatible = "dataimage,fg040346dsswbg04", |
5000 | .data = &dataimage_fg040346dsswbg04, |
5001 | }, { |
5002 | .compatible = "dataimage,fg1001l0dsswmg01", |
5003 | .data = &dataimage_fg1001l0dsswmg01, |
5004 | }, { |
5005 | .compatible = "dataimage,scf0700c48ggu18", |
5006 | .data = &dataimage_scf0700c48ggu18, |
5007 | }, { |
5008 | .compatible = "dlc,dlc0700yzg-1", |
5009 | .data = &dlc_dlc0700yzg_1, |
5010 | }, { |
5011 | .compatible = "dlc,dlc1010gig", |
5012 | .data = &dlc_dlc1010gig, |
5013 | }, { |
5014 | .compatible = "edt,et035012dm6", |
5015 | .data = &edt_et035012dm6, |
5016 | }, { |
5017 | .compatible = "edt,etm0350g0dh6", |
5018 | .data = &edt_etm0350g0dh6, |
5019 | }, { |
5020 | .compatible = "edt,etm043080dh6gp", |
5021 | .data = &edt_etm043080dh6gp, |
5022 | }, { |
5023 | .compatible = "edt,etm0430g0dh6", |
5024 | .data = &edt_etm0430g0dh6, |
5025 | }, { |
5026 | .compatible = "edt,et057090dhu", |
5027 | .data = &edt_et057090dhu, |
5028 | }, { |
5029 | .compatible = "edt,et070080dh6", |
5030 | .data = &edt_etm0700g0dh6, |
5031 | }, { |
5032 | .compatible = "edt,etm0700g0dh6", |
5033 | .data = &edt_etm0700g0dh6, |
5034 | }, { |
5035 | .compatible = "edt,etm0700g0bdh6", |
5036 | .data = &edt_etm0700g0bdh6, |
5037 | }, { |
5038 | .compatible = "edt,etm0700g0edh6", |
5039 | .data = &edt_etm0700g0bdh6, |
5040 | }, { |
5041 | .compatible = "edt,etml0700y5dha", |
5042 | .data = &edt_etml0700y5dha, |
5043 | }, { |
5044 | .compatible = "edt,etml1010g3dra", |
5045 | .data = &edt_etml1010g3dra, |
5046 | }, { |
5047 | .compatible = "edt,etmv570g2dhu", |
5048 | .data = &edt_etmv570g2dhu, |
5049 | }, { |
5050 | .compatible = "eink,vb3300-kca", |
5051 | .data = &eink_vb3300_kca, |
5052 | }, { |
5053 | .compatible = "evervision,vgg644804", |
5054 | .data = &evervision_vgg644804, |
5055 | }, { |
5056 | .compatible = "evervision,vgg804821", |
5057 | .data = &evervision_vgg804821, |
5058 | }, { |
5059 | .compatible = "foxlink,fl500wvr00-a0t", |
5060 | .data = &foxlink_fl500wvr00_a0t, |
5061 | }, { |
5062 | .compatible = "frida,frd350h54004", |
5063 | .data = &frida_frd350h54004, |
5064 | }, { |
5065 | .compatible = "friendlyarm,hd702e", |
5066 | .data = &friendlyarm_hd702e, |
5067 | }, { |
5068 | .compatible = "giantplus,gpg482739qs5", |
5069 | .data = &giantplus_gpg482739qs5 |
5070 | }, { |
5071 | .compatible = "giantplus,gpm940b0", |
5072 | .data = &giantplus_gpm940b0, |
5073 | }, { |
5074 | .compatible = "hannstar,hsd070pww1", |
5075 | .data = &hannstar_hsd070pww1, |
5076 | }, { |
5077 | .compatible = "hannstar,hsd100pxn1", |
5078 | .data = &hannstar_hsd100pxn1, |
5079 | }, { |
5080 | .compatible = "hannstar,hsd101pww2", |
5081 | .data = &hannstar_hsd101pww2, |
5082 | }, { |
5083 | .compatible = "hit,tx23d38vm0caa", |
5084 | .data = &hitachi_tx23d38vm0caa |
5085 | }, { |
5086 | .compatible = "innolux,at043tn24", |
5087 | .data = &innolux_at043tn24, |
5088 | }, { |
5089 | .compatible = "innolux,at070tn92", |
5090 | .data = &innolux_at070tn92, |
5091 | }, { |
5092 | .compatible = "innolux,g070ace-l01", |
5093 | .data = &innolux_g070ace_l01, |
5094 | }, { |
5095 | .compatible = "innolux,g070ace-lh3", |
5096 | .data = &innolux_g070ace_lh3, |
5097 | }, { |
5098 | .compatible = "innolux,g070y2-l01", |
5099 | .data = &innolux_g070y2_l01, |
5100 | }, { |
5101 | .compatible = "innolux,g070y2-t02", |
5102 | .data = &innolux_g070y2_t02, |
5103 | }, { |
5104 | .compatible = "innolux,g101ice-l01", |
5105 | .data = &innolux_g101ice_l01 |
5106 | }, { |
5107 | .compatible = "innolux,g121i1-l01", |
5108 | .data = &innolux_g121i1_l01 |
5109 | }, { |
5110 | .compatible = "innolux,g121x1-l03", |
5111 | .data = &innolux_g121x1_l03, |
5112 | }, { |
5113 | .compatible = "innolux,g121xce-l01", |
5114 | .data = &innolux_g121xce_l01, |
5115 | }, { |
5116 | .compatible = "innolux,g156hce-l01", |
5117 | .data = &innolux_g156hce_l01, |
5118 | }, { |
5119 | .compatible = "innolux,n156bge-l21", |
5120 | .data = &innolux_n156bge_l21, |
5121 | }, { |
5122 | .compatible = "innolux,zj070na-01p", |
5123 | .data = &innolux_zj070na_01p, |
5124 | }, { |
5125 | .compatible = "koe,tx14d24vm1bpa", |
5126 | .data = &koe_tx14d24vm1bpa, |
5127 | }, { |
5128 | .compatible = "koe,tx26d202vm0bwa", |
5129 | .data = &koe_tx26d202vm0bwa, |
5130 | }, { |
5131 | .compatible = "koe,tx31d200vm0baa", |
5132 | .data = &koe_tx31d200vm0baa, |
5133 | }, { |
5134 | .compatible = "kyo,tcg121xglp", |
5135 | .data = &kyo_tcg121xglp, |
5136 | }, { |
5137 | .compatible = "lemaker,bl035-rgb-002", |
5138 | .data = &lemaker_bl035_rgb_002, |
5139 | }, { |
5140 | .compatible = "lg,lb070wv8", |
5141 | .data = &lg_lb070wv8, |
5142 | }, { |
5143 | .compatible = "lincolntech,lcd185-101ct", |
5144 | .data = &lincolntech_lcd185_101ct, |
5145 | }, { |
5146 | .compatible = "logicpd,type28", |
5147 | .data = &logicpd_type_28, |
5148 | }, { |
5149 | .compatible = "logictechno,lt161010-2nhc", |
5150 | .data = &logictechno_lt161010_2nh, |
5151 | }, { |
5152 | .compatible = "logictechno,lt161010-2nhr", |
5153 | .data = &logictechno_lt161010_2nh, |
5154 | }, { |
5155 | .compatible = "logictechno,lt170410-2whc", |
5156 | .data = &logictechno_lt170410_2whc, |
5157 | }, { |
5158 | .compatible = "logictechno,lttd800480070-l2rt", |
5159 | .data = &logictechno_lttd800480070_l2rt, |
5160 | }, { |
5161 | .compatible = "logictechno,lttd800480070-l6wh-rt", |
5162 | .data = &logictechno_lttd800480070_l6wh_rt, |
5163 | }, { |
5164 | .compatible = "microtips,mf-101hiebcaf0", |
5165 | .data = µtips_mf_101hiebcaf0_c, |
5166 | }, { |
5167 | .compatible = "microtips,mf-103hieb0ga0", |
5168 | .data = µtips_mf_103hieb0ga0, |
5169 | }, { |
5170 | .compatible = "mitsubishi,aa070mc01-ca1", |
5171 | .data = &mitsubishi_aa070mc01, |
5172 | }, { |
5173 | .compatible = "mitsubishi,aa084xe01", |
5174 | .data = &mitsubishi_aa084xe01, |
5175 | }, { |
5176 | .compatible = "multi-inno,mi0700a2t-30", |
5177 | .data = &multi_inno_mi0700a2t_30, |
5178 | }, { |
5179 | .compatible = "multi-inno,mi0700s4t-6", |
5180 | .data = &multi_inno_mi0700s4t_6, |
5181 | }, { |
5182 | .compatible = "multi-inno,mi0800ft-9", |
5183 | .data = &multi_inno_mi0800ft_9, |
5184 | }, { |
5185 | .compatible = "multi-inno,mi1010ait-1cp", |
5186 | .data = &multi_inno_mi1010ait_1cp, |
5187 | }, { |
5188 | .compatible = "multi-inno,mi1010z1t-1cp11", |
5189 | .data = &multi_inno_mi1010z1t_1cp11, |
5190 | }, { |
5191 | .compatible = "nec,nl12880bc20-05", |
5192 | .data = &nec_nl12880bc20_05, |
5193 | }, { |
5194 | .compatible = "nec,nl4827hc19-05b", |
5195 | .data = &nec_nl4827hc19_05b, |
5196 | }, { |
5197 | .compatible = "netron-dy,e231732", |
5198 | .data = &netron_dy_e231732, |
5199 | }, { |
5200 | .compatible = "newhaven,nhd-4.3-480272ef-atxl", |
5201 | .data = &newhaven_nhd_43_480272ef_atxl, |
5202 | }, { |
5203 | .compatible = "nlt,nl13676bc25-03f", |
5204 | .data = &nlt_nl13676bc25_03f, |
5205 | }, { |
5206 | .compatible = "nlt,nl192108ac18-02d", |
5207 | .data = &nlt_nl192108ac18_02d, |
5208 | }, { |
5209 | .compatible = "nvd,9128", |
5210 | .data = &nvd_9128, |
5211 | }, { |
5212 | .compatible = "okaya,rs800480t-7x0gp", |
5213 | .data = &okaya_rs800480t_7x0gp, |
5214 | }, { |
5215 | .compatible = "olimex,lcd-olinuxino-43-ts", |
5216 | .data = &olimex_lcd_olinuxino_43ts, |
5217 | }, { |
5218 | .compatible = "ontat,kd50g21-40nt-a1", |
5219 | .data = &ontat_kd50g21_40nt_a1, |
5220 | }, { |
5221 | .compatible = "ontat,yx700wv03", |
5222 | .data = &ontat_yx700wv03, |
5223 | }, { |
5224 | .compatible = "ortustech,com37h3m05dtc", |
5225 | .data = &ortustech_com37h3m, |
5226 | }, { |
5227 | .compatible = "ortustech,com37h3m99dtc", |
5228 | .data = &ortustech_com37h3m, |
5229 | }, { |
5230 | .compatible = "ortustech,com43h4m85ulc", |
5231 | .data = &ortustech_com43h4m85ulc, |
5232 | }, { |
5233 | .compatible = "osddisplays,osd070t1718-19ts", |
5234 | .data = &osddisplays_osd070t1718_19ts, |
5235 | }, { |
5236 | .compatible = "pda,91-00156-a0", |
5237 | .data = &pda_91_00156_a0, |
5238 | }, { |
5239 | .compatible = "powertip,ph128800t004-zza01", |
5240 | .data = &powertip_ph128800t004_zza01, |
5241 | }, { |
5242 | .compatible = "powertip,ph128800t006-zhc01", |
5243 | .data = &powertip_ph128800t006_zhc01, |
5244 | }, { |
5245 | .compatible = "powertip,ph800480t013-idf02", |
5246 | .data = &powertip_ph800480t013_idf02, |
5247 | }, { |
5248 | .compatible = "primeview,pm070wl4", |
5249 | .data = &primeview_pm070wl4, |
5250 | }, { |
5251 | .compatible = "qiaodian,qd43003c0-40", |
5252 | .data = &qd43003c0_40, |
5253 | }, { |
5254 | .compatible = "qishenglong,gopher2b-lcd", |
5255 | .data = &qishenglong_gopher2b_lcd, |
5256 | }, { |
5257 | .compatible = "rocktech,rk043fn48h", |
5258 | .data = &rocktech_rk043fn48h, |
5259 | }, { |
5260 | .compatible = "rocktech,rk070er9427", |
5261 | .data = &rocktech_rk070er9427, |
5262 | }, { |
5263 | .compatible = "rocktech,rk101ii01d-ct", |
5264 | .data = &rocktech_rk101ii01d_ct, |
5265 | }, { |
5266 | .compatible = "samsung,ltl101al01", |
5267 | .data = &samsung_ltl101al01, |
5268 | }, { |
5269 | .compatible = "samsung,ltn101nt05", |
5270 | .data = &samsung_ltn101nt05, |
5271 | }, { |
5272 | .compatible = "satoz,sat050at40h12r2", |
5273 | .data = &satoz_sat050at40h12r2, |
5274 | }, { |
5275 | .compatible = "sharp,lq035q7db03", |
5276 | .data = &sharp_lq035q7db03, |
5277 | }, { |
5278 | .compatible = "sharp,lq070y3dg3b", |
5279 | .data = &sharp_lq070y3dg3b, |
5280 | }, { |
5281 | .compatible = "sharp,lq101k1ly04", |
5282 | .data = &sharp_lq101k1ly04, |
5283 | }, { |
5284 | .compatible = "sharp,ls020b1dd01d", |
5285 | .data = &sharp_ls020b1dd01d, |
5286 | }, { |
5287 | .compatible = "shelly,sca07010-bfn-lnn", |
5288 | .data = &shelly_sca07010_bfn_lnn, |
5289 | }, { |
5290 | .compatible = "starry,kr070pe2t", |
5291 | .data = &starry_kr070pe2t, |
5292 | }, { |
5293 | .compatible = "startek,kd070wvfpa", |
5294 | .data = &startek_kd070wvfpa, |
5295 | }, { |
5296 | .compatible = "team-source-display,tst043015cmhx", |
5297 | .data = &tsd_tst043015cmhx, |
5298 | }, { |
5299 | .compatible = "tfc,s9700rtwv43tr-01b", |
5300 | .data = &tfc_s9700rtwv43tr_01b, |
5301 | }, { |
5302 | .compatible = "tianma,p0700wxf1mbaa", |
5303 | .data = &tianma_p0700wxf1mbaa, |
5304 | }, { |
5305 | .compatible = "tianma,tm070jdhg30", |
5306 | .data = &tianma_tm070jdhg30, |
5307 | }, { |
5308 | .compatible = "tianma,tm070jdhg34-00", |
5309 | .data = &tianma_tm070jdhg34_00, |
5310 | }, { |
5311 | .compatible = "tianma,tm070jvhg33", |
5312 | .data = &tianma_tm070jvhg33, |
5313 | }, { |
5314 | .compatible = "tianma,tm070rvhg71", |
5315 | .data = &tianma_tm070rvhg71, |
5316 | }, { |
5317 | .compatible = "ti,nspire-cx-lcd-panel", |
5318 | .data = &ti_nspire_cx_lcd_panel, |
5319 | }, { |
5320 | .compatible = "ti,nspire-classic-lcd-panel", |
5321 | .data = &ti_nspire_classic_lcd_panel, |
5322 | }, { |
5323 | .compatible = "toshiba,lt089ac29000", |
5324 | .data = &toshiba_lt089ac29000, |
5325 | }, { |
5326 | .compatible = "topland,tian-g07017-01", |
5327 | .data = &topland_tian_g07017_01, |
5328 | }, { |
5329 | .compatible = "tpk,f07a-0102", |
5330 | .data = &tpk_f07a_0102, |
5331 | }, { |
5332 | .compatible = "tpk,f10a-0102", |
5333 | .data = &tpk_f10a_0102, |
5334 | }, { |
5335 | .compatible = "urt,umsh-8596md-t", |
5336 | .data = &urt_umsh_8596md_parallel, |
5337 | }, { |
5338 | .compatible = "urt,umsh-8596md-1t", |
5339 | .data = &urt_umsh_8596md_parallel, |
5340 | }, { |
5341 | .compatible = "urt,umsh-8596md-7t", |
5342 | .data = &urt_umsh_8596md_parallel, |
5343 | }, { |
5344 | .compatible = "urt,umsh-8596md-11t", |
5345 | .data = &urt_umsh_8596md_lvds, |
5346 | }, { |
5347 | .compatible = "urt,umsh-8596md-19t", |
5348 | .data = &urt_umsh_8596md_lvds, |
5349 | }, { |
5350 | .compatible = "urt,umsh-8596md-20t", |
5351 | .data = &urt_umsh_8596md_parallel, |
5352 | }, { |
5353 | .compatible = "vivax,tpc9150-panel", |
5354 | .data = &vivax_tpc9150_panel, |
5355 | }, { |
5356 | .compatible = "vxt,vl050-8048nt-c01", |
5357 | .data = &vl050_8048nt_c01, |
5358 | }, { |
5359 | .compatible = "winstar,wf35ltiacd", |
5360 | .data = &winstar_wf35ltiacd, |
5361 | }, { |
5362 | .compatible = "yes-optoelectronics,ytc700tlag-05-201c", |
5363 | .data = &yes_optoelectronics_ytc700tlag_05_201c, |
5364 | }, { |
5365 | .compatible = "microchip,ac69t88a", |
5366 | .data = &mchp_ac69t88a, |
5367 | }, { |
5368 | /* Must be the last entry */ |
5369 | .compatible = "panel-dpi", |
5370 | .data = &panel_dpi, |
5371 | }, { |
5372 | /* sentinel */ |
5373 | } |
5374 | }; |
5375 | MODULE_DEVICE_TABLE(of, platform_of_match); |
5376 | |
5377 | static int panel_simple_platform_probe(struct platform_device *pdev) |
5378 | { |
5379 | const struct panel_desc *desc; |
5380 | |
5381 | desc = of_device_get_match_data(dev: &pdev->dev); |
5382 | if (!desc) |
5383 | return -ENODEV; |
5384 | |
5385 | return panel_simple_probe(dev: &pdev->dev, desc); |
5386 | } |
5387 | |
5388 | static void panel_simple_platform_remove(struct platform_device *pdev) |
5389 | { |
5390 | panel_simple_remove(dev: &pdev->dev); |
5391 | } |
5392 | |
5393 | static void panel_simple_platform_shutdown(struct platform_device *pdev) |
5394 | { |
5395 | panel_simple_shutdown(dev: &pdev->dev); |
5396 | } |
5397 | |
5398 | static const struct dev_pm_ops panel_simple_pm_ops = { |
5399 | SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) |
5400 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
5401 | pm_runtime_force_resume) |
5402 | }; |
5403 | |
5404 | static struct platform_driver panel_simple_platform_driver = { |
5405 | .driver = { |
5406 | .name = "panel-simple", |
5407 | .of_match_table = platform_of_match, |
5408 | .pm = &panel_simple_pm_ops, |
5409 | }, |
5410 | .probe = panel_simple_platform_probe, |
5411 | .remove = panel_simple_platform_remove, |
5412 | .shutdown = panel_simple_platform_shutdown, |
5413 | }; |
5414 | |
5415 | struct panel_desc_dsi { |
5416 | struct panel_desc desc; |
5417 | |
5418 | unsigned long flags; |
5419 | enum mipi_dsi_pixel_format format; |
5420 | unsigned int lanes; |
5421 | }; |
5422 | |
5423 | static const struct drm_display_mode auo_b080uan01_mode = { |
5424 | .clock = 154500, |
5425 | .hdisplay = 1200, |
5426 | .hsync_start = 1200 + 62, |
5427 | .hsync_end = 1200 + 62 + 4, |
5428 | .htotal = 1200 + 62 + 4 + 62, |
5429 | .vdisplay = 1920, |
5430 | .vsync_start = 1920 + 9, |
5431 | .vsync_end = 1920 + 9 + 2, |
5432 | .vtotal = 1920 + 9 + 2 + 8, |
5433 | }; |
5434 | |
5435 | static const struct panel_desc_dsi auo_b080uan01 = { |
5436 | .desc = { |
5437 | .modes = &auo_b080uan01_mode, |
5438 | .num_modes = 1, |
5439 | .bpc = 8, |
5440 | .size = { |
5441 | .width = 108, |
5442 | .height = 272, |
5443 | }, |
5444 | .connector_type = DRM_MODE_CONNECTOR_DSI, |
5445 | }, |
5446 | .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, |
5447 | .format = MIPI_DSI_FMT_RGB888, |
5448 | .lanes = 4, |
5449 | }; |
5450 | |
5451 | static const struct drm_display_mode boe_tv080wum_nl0_mode = { |
5452 | .clock = 160000, |
5453 | .hdisplay = 1200, |
5454 | .hsync_start = 1200 + 120, |
5455 | .hsync_end = 1200 + 120 + 20, |
5456 | .htotal = 1200 + 120 + 20 + 21, |
5457 | .vdisplay = 1920, |
5458 | .vsync_start = 1920 + 21, |
5459 | .vsync_end = 1920 + 21 + 3, |
5460 | .vtotal = 1920 + 21 + 3 + 18, |
5461 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
5462 | }; |
5463 | |
5464 | static const struct panel_desc_dsi boe_tv080wum_nl0 = { |
5465 | .desc = { |
5466 | .modes = &boe_tv080wum_nl0_mode, |
5467 | .num_modes = 1, |
5468 | .size = { |
5469 | .width = 107, |
5470 | .height = 172, |
5471 | }, |
5472 | .connector_type = DRM_MODE_CONNECTOR_DSI, |
5473 | }, |
5474 | .flags = MIPI_DSI_MODE_VIDEO | |
5475 | MIPI_DSI_MODE_VIDEO_BURST | |
5476 | MIPI_DSI_MODE_VIDEO_SYNC_PULSE, |
5477 | .format = MIPI_DSI_FMT_RGB888, |
5478 | .lanes = 4, |
5479 | }; |
5480 | |
5481 | static const struct drm_display_mode lg_ld070wx3_sl01_mode = { |
5482 | .clock = 71000, |
5483 | .hdisplay = 800, |
5484 | .hsync_start = 800 + 32, |
5485 | .hsync_end = 800 + 32 + 1, |
5486 | .htotal = 800 + 32 + 1 + 57, |
5487 | .vdisplay = 1280, |
5488 | .vsync_start = 1280 + 28, |
5489 | .vsync_end = 1280 + 28 + 1, |
5490 | .vtotal = 1280 + 28 + 1 + 14, |
5491 | }; |
5492 | |
5493 | static const struct panel_desc_dsi lg_ld070wx3_sl01 = { |
5494 | .desc = { |
5495 | .modes = &lg_ld070wx3_sl01_mode, |
5496 | .num_modes = 1, |
5497 | .bpc = 8, |
5498 | .size = { |
5499 | .width = 94, |
5500 | .height = 151, |
5501 | }, |
5502 | .connector_type = DRM_MODE_CONNECTOR_DSI, |
5503 | }, |
5504 | .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, |
5505 | .format = MIPI_DSI_FMT_RGB888, |
5506 | .lanes = 4, |
5507 | }; |
5508 | |
5509 | static const struct drm_display_mode lg_lh500wx1_sd03_mode = { |
5510 | .clock = 67000, |
5511 | .hdisplay = 720, |
5512 | .hsync_start = 720 + 12, |
5513 | .hsync_end = 720 + 12 + 4, |
5514 | .htotal = 720 + 12 + 4 + 112, |
5515 | .vdisplay = 1280, |
5516 | .vsync_start = 1280 + 8, |
5517 | .vsync_end = 1280 + 8 + 4, |
5518 | .vtotal = 1280 + 8 + 4 + 12, |
5519 | }; |
5520 | |
5521 | static const struct panel_desc_dsi lg_lh500wx1_sd03 = { |
5522 | .desc = { |
5523 | .modes = &lg_lh500wx1_sd03_mode, |
5524 | .num_modes = 1, |
5525 | .bpc = 8, |
5526 | .size = { |
5527 | .width = 62, |
5528 | .height = 110, |
5529 | }, |
5530 | .connector_type = DRM_MODE_CONNECTOR_DSI, |
5531 | }, |
5532 | .flags = MIPI_DSI_MODE_VIDEO, |
5533 | .format = MIPI_DSI_FMT_RGB888, |
5534 | .lanes = 4, |
5535 | }; |
5536 | |
5537 | static const struct drm_display_mode panasonic_vvx10f004b00_mode = { |
5538 | .clock = 157200, |
5539 | .hdisplay = 1920, |
5540 | .hsync_start = 1920 + 154, |
5541 | .hsync_end = 1920 + 154 + 16, |
5542 | .htotal = 1920 + 154 + 16 + 32, |
5543 | .vdisplay = 1200, |
5544 | .vsync_start = 1200 + 17, |
5545 | .vsync_end = 1200 + 17 + 2, |
5546 | .vtotal = 1200 + 17 + 2 + 16, |
5547 | }; |
5548 | |
5549 | static const struct panel_desc_dsi panasonic_vvx10f004b00 = { |
5550 | .desc = { |
5551 | .modes = &panasonic_vvx10f004b00_mode, |
5552 | .num_modes = 1, |
5553 | .bpc = 8, |
5554 | .size = { |
5555 | .width = 217, |
5556 | .height = 136, |
5557 | }, |
5558 | .connector_type = DRM_MODE_CONNECTOR_DSI, |
5559 | }, |
5560 | .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | |
5561 | MIPI_DSI_CLOCK_NON_CONTINUOUS, |
5562 | .format = MIPI_DSI_FMT_RGB888, |
5563 | .lanes = 4, |
5564 | }; |
5565 | |
5566 | static const struct drm_display_mode lg_acx467akm_7_mode = { |
5567 | .clock = 150000, |
5568 | .hdisplay = 1080, |
5569 | .hsync_start = 1080 + 2, |
5570 | .hsync_end = 1080 + 2 + 2, |
5571 | .htotal = 1080 + 2 + 2 + 2, |
5572 | .vdisplay = 1920, |
5573 | .vsync_start = 1920 + 2, |
5574 | .vsync_end = 1920 + 2 + 2, |
5575 | .vtotal = 1920 + 2 + 2 + 2, |
5576 | }; |
5577 | |
5578 | static const struct panel_desc_dsi lg_acx467akm_7 = { |
5579 | .desc = { |
5580 | .modes = &lg_acx467akm_7_mode, |
5581 | .num_modes = 1, |
5582 | .bpc = 8, |
5583 | .size = { |
5584 | .width = 62, |
5585 | .height = 110, |
5586 | }, |
5587 | .connector_type = DRM_MODE_CONNECTOR_DSI, |
5588 | }, |
5589 | .flags = 0, |
5590 | .format = MIPI_DSI_FMT_RGB888, |
5591 | .lanes = 4, |
5592 | }; |
5593 | |
5594 | static const struct drm_display_mode osd101t2045_53ts_mode = { |
5595 | .clock = 154500, |
5596 | .hdisplay = 1920, |
5597 | .hsync_start = 1920 + 112, |
5598 | .hsync_end = 1920 + 112 + 16, |
5599 | .htotal = 1920 + 112 + 16 + 32, |
5600 | .vdisplay = 1200, |
5601 | .vsync_start = 1200 + 16, |
5602 | .vsync_end = 1200 + 16 + 2, |
5603 | .vtotal = 1200 + 16 + 2 + 16, |
5604 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
5605 | }; |
5606 | |
5607 | static const struct panel_desc_dsi osd101t2045_53ts = { |
5608 | .desc = { |
5609 | .modes = &osd101t2045_53ts_mode, |
5610 | .num_modes = 1, |
5611 | .bpc = 8, |
5612 | .size = { |
5613 | .width = 217, |
5614 | .height = 136, |
5615 | }, |
5616 | .connector_type = DRM_MODE_CONNECTOR_DSI, |
5617 | }, |
5618 | .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | |
5619 | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | |
5620 | MIPI_DSI_MODE_NO_EOT_PACKET, |
5621 | .format = MIPI_DSI_FMT_RGB888, |
5622 | .lanes = 4, |
5623 | }; |
5624 | |
5625 | static const struct of_device_id dsi_of_match[] = { |
5626 | { |
5627 | .compatible = "auo,b080uan01", |
5628 | .data = &auo_b080uan01 |
5629 | }, { |
5630 | .compatible = "boe,tv080wum-nl0", |
5631 | .data = &boe_tv080wum_nl0 |
5632 | }, { |
5633 | .compatible = "lg,ld070wx3-sl01", |
5634 | .data = &lg_ld070wx3_sl01 |
5635 | }, { |
5636 | .compatible = "lg,lh500wx1-sd03", |
5637 | .data = &lg_lh500wx1_sd03 |
5638 | }, { |
5639 | .compatible = "panasonic,vvx10f004b00", |
5640 | .data = &panasonic_vvx10f004b00 |
5641 | }, { |
5642 | .compatible = "lg,acx467akm-7", |
5643 | .data = &lg_acx467akm_7 |
5644 | }, { |
5645 | .compatible = "osddisplays,osd101t2045-53ts", |
5646 | .data = &osd101t2045_53ts |
5647 | }, { |
5648 | /* sentinel */ |
5649 | } |
5650 | }; |
5651 | MODULE_DEVICE_TABLE(of, dsi_of_match); |
5652 | |
5653 | static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) |
5654 | { |
5655 | const struct panel_desc_dsi *desc; |
5656 | int err; |
5657 | |
5658 | desc = of_device_get_match_data(dev: &dsi->dev); |
5659 | if (!desc) |
5660 | return -ENODEV; |
5661 | |
5662 | err = panel_simple_probe(dev: &dsi->dev, desc: &desc->desc); |
5663 | if (err < 0) |
5664 | return err; |
5665 | |
5666 | dsi->mode_flags = desc->flags; |
5667 | dsi->format = desc->format; |
5668 | dsi->lanes = desc->lanes; |
5669 | |
5670 | err = mipi_dsi_attach(dsi); |
5671 | if (err) { |
5672 | struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); |
5673 | |
5674 | drm_panel_remove(panel: &panel->base); |
5675 | } |
5676 | |
5677 | return err; |
5678 | } |
5679 | |
5680 | static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) |
5681 | { |
5682 | int err; |
5683 | |
5684 | err = mipi_dsi_detach(dsi); |
5685 | if (err < 0) |
5686 | dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); |
5687 | |
5688 | panel_simple_remove(dev: &dsi->dev); |
5689 | } |
5690 | |
5691 | static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) |
5692 | { |
5693 | panel_simple_shutdown(dev: &dsi->dev); |
5694 | } |
5695 | |
5696 | static struct mipi_dsi_driver panel_simple_dsi_driver = { |
5697 | .driver = { |
5698 | .name = "panel-simple-dsi", |
5699 | .of_match_table = dsi_of_match, |
5700 | .pm = &panel_simple_pm_ops, |
5701 | }, |
5702 | .probe = panel_simple_dsi_probe, |
5703 | .remove = panel_simple_dsi_remove, |
5704 | .shutdown = panel_simple_dsi_shutdown, |
5705 | }; |
5706 | |
5707 | static int __init panel_simple_init(void) |
5708 | { |
5709 | int err; |
5710 | |
5711 | err = platform_driver_register(&panel_simple_platform_driver); |
5712 | if (err < 0) |
5713 | return err; |
5714 | |
5715 | if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { |
5716 | err = mipi_dsi_driver_register(&panel_simple_dsi_driver); |
5717 | if (err < 0) |
5718 | goto err_did_platform_register; |
5719 | } |
5720 | |
5721 | return 0; |
5722 | |
5723 | err_did_platform_register: |
5724 | platform_driver_unregister(&panel_simple_platform_driver); |
5725 | |
5726 | return err; |
5727 | } |
5728 | module_init(panel_simple_init); |
5729 | |
5730 | static void __exit panel_simple_exit(void) |
5731 | { |
5732 | if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) |
5733 | mipi_dsi_driver_unregister(driver: &panel_simple_dsi_driver); |
5734 | |
5735 | platform_driver_unregister(&panel_simple_platform_driver); |
5736 | } |
5737 | module_exit(panel_simple_exit); |
5738 | |
5739 | MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); |
5740 | MODULE_DESCRIPTION("DRM Driver for Simple Panels"); |
5741 | MODULE_LICENSE("GPL and additional rights"); |
5742 |
Definitions
- panel_desc
- panel_simple
- to_panel_simple
- panel_simple_get_timings_modes
- panel_simple_get_display_modes
- panel_simple_get_non_edid_modes
- panel_simple_wait
- panel_simple_disable
- panel_simple_suspend
- panel_simple_unprepare
- panel_simple_resume
- panel_simple_prepare
- panel_simple_enable
- panel_simple_get_modes
- panel_simple_get_timings
- panel_simple_get_orientation
- panel_simple_funcs
- panel_dpi
- panel_dpi_probe
- panel_simple_parse_panel_timing_node
- panel_simple_override_nondefault_lvds_datamapping
- panel_simple_probe
- panel_simple_shutdown
- panel_simple_remove
- ampire_am_1280800n3tzqw_t00h_mode
- ampire_am_1280800n3tzqw_t00h
- ampire_am_480272h3tmqw_t01h_mode
- ampire_am_480272h3tmqw_t01h
- ampire_am800480r3tmqwa1h_mode
- ampire_am_800480l1tmqw_t00h_timing
- ampire_am_800480l1tmqw_t00h
- ampire_am800480r3tmqwa1h
- ampire_am800600p5tmqw_tb8h_timing
- ampire_am800600p5tmqwtb8h
- santek_st0700i5y_rbslw_f_timing
- armadeus_st0700_adapt
- auo_b101aw03_mode
- auo_b101aw03
- auo_b101xtn01_mode
- auo_b101xtn01
- auo_b116xw03_mode
- auo_b116xw03
- auo_g070vvn01_timings
- auo_g070vvn01
- auo_g101evn010_timing
- auo_g101evn010
- auo_g104sn02_mode
- auo_g104sn02
- auo_g104stn01_mode
- auo_g104stn01
- auo_g121ean01_timing
- auo_g121ean01
- auo_g133han01_timings
- auo_g133han01
- auo_g156han04_timings
- auo_g156han04
- auo_g156xtn01_mode
- auo_g156xtn01
- auo_g185han01_timings
- auo_g185han01
- auo_g190ean01_timings
- auo_g190ean01
- auo_p320hvn03_timings
- auo_p320hvn03
- auo_t215hvn01_mode
- auo_t215hvn01
- avic_tm070ddh03_mode
- avic_tm070ddh03
- bananapi_s070wv20_ct16_mode
- bananapi_s070wv20_ct16
- boe_av101hdt_a10_timing
- boe_av101hdt_a10
- boe_av123z7m_n17_timing
- boe_av123z7m_n17
- boe_bp101wx1_100_mode
- boe_bp082wx1_100
- boe_bp101wx1_100
- boe_ev121wxm_n10_1850_timing
- boe_ev121wxm_n10_1850
- boe_hv070wsa_mode
- boe_hv070wsa
- cct_cmt430b19n00_timing
- cct_cmt430b19n00
- cdtech_s043wq26h_ct7_mode
- cdtech_s043wq26h_ct7
- cdtech_s070pws19hp_fc21_mode
- cdtech_s070pws19hp_fc21
- cdtech_s070swv29hg_dc44_mode
- cdtech_s070swv29hg_dc44
- cdtech_s070wv95_ct16_mode
- cdtech_s070wv95_ct16
- chefree_ch101olhlwh_002_timing
- chefree_ch101olhlwh_002
- chunghwa_claa070wp03xg_mode
- chunghwa_claa070wp03xg
- chunghwa_claa101wa01a_mode
- chunghwa_claa101wa01a
- chunghwa_claa101wb01_mode
- chunghwa_claa101wb01
- dataimage_fg040346dsswbg04_timing
- dataimage_fg040346dsswbg04
- dataimage_fg1001l0dsswmg01_timing
- dataimage_fg1001l0dsswmg01
- dataimage_scf0700c48ggu18_mode
- dataimage_scf0700c48ggu18
- dlc_dlc0700yzg_1_timing
- dlc_dlc0700yzg_1
- dlc_dlc1010gig_timing
- dlc_dlc1010gig
- edt_et035012dm6_mode
- edt_et035012dm6
- edt_etm0350g0dh6_mode
- edt_etm0350g0dh6
- edt_etm043080dh6gp_mode
- edt_etm043080dh6gp
- edt_etm0430g0dh6_mode
- edt_etm0430g0dh6
- edt_et057090dhu_mode
- edt_et057090dhu
- edt_etm0700g0dh6_mode
- edt_etm0700g0dh6
- edt_etm0700g0bdh6
- edt_etml0700y5dha_timing
- edt_etml0700y5dha
- edt_etml1010g3dra_timing
- edt_etml1010g3dra
- edt_etmv570g2dhu_mode
- edt_etmv570g2dhu
- eink_vb3300_kca_timing
- eink_vb3300_kca
- evervision_vgg644804_timing
- evervision_vgg644804
- evervision_vgg804821_timing
- evervision_vgg804821
- foxlink_fl500wvr00_a0t_mode
- foxlink_fl500wvr00_a0t
- frida_frd350h54004_modes
- frida_frd350h54004
- friendlyarm_hd702e_mode
- friendlyarm_hd702e
- giantplus_gpg482739qs5_mode
- giantplus_gpg482739qs5
- giantplus_gpm940b0_timing
- giantplus_gpm940b0
- hannstar_hsd070pww1_timing
- hannstar_hsd070pww1
- hannstar_hsd100pxn1_timing
- hannstar_hsd100pxn1
- hannstar_hsd101pww2_timing
- hannstar_hsd101pww2
- hitachi_tx23d38vm0caa_mode
- hitachi_tx23d38vm0caa
- innolux_at043tn24_mode
- innolux_at043tn24
- innolux_at070tn92_mode
- innolux_at070tn92
- innolux_g070ace_l01_timing
- innolux_g070ace_l01
- innolux_g070y2_l01_timing
- innolux_g070y2_l01
- innolux_g070ace_lh3_timing
- innolux_g070ace_lh3
- innolux_g070y2_t02_mode
- innolux_g070y2_t02
- innolux_g101ice_l01_timing
- innolux_g101ice_l01
- innolux_g121i1_l01_timing
- innolux_g121i1_l01
- innolux_g121x1_l03_timings
- innolux_g121x1_l03
- innolux_g121xce_l01
- innolux_g156hce_l01_timings
- innolux_g156hce_l01
- innolux_n156bge_l21_mode
- innolux_n156bge_l21
- innolux_zj070na_01p_mode
- innolux_zj070na_01p
- koe_tx14d24vm1bpa_timing
- koe_tx14d24vm1bpa
- koe_tx26d202vm0bwa_timing
- koe_tx26d202vm0bwa
- koe_tx31d200vm0baa_timing
- koe_tx31d200vm0baa
- kyo_tcg121xglp_timing
- kyo_tcg121xglp
- lemaker_bl035_rgb_002_mode
- lemaker_bl035_rgb_002
- lg_lb070wv8_timing
- lg_lb070wv8
- lincolntech_lcd185_101ct_mode
- lincolntech_lcd185_101ct
- logictechno_lt161010_2nh_timing
- logictechno_lt161010_2nh
- logictechno_lt170410_2whc_timing
- logictechno_lt170410_2whc
- logictechno_lttd800480070_l2rt_mode
- logictechno_lttd800480070_l2rt
- logictechno_lttd800480070_l6wh_rt_mode
- logictechno_lttd800480070_l6wh_rt
- logicpd_type_28_mode
- logicpd_type_28
- microtips_mf_101hiebcaf0_c_mode
- microtips_mf_101hiebcaf0_c
- microtips_mf_103hieb0ga0_mode
- microtips_mf_103hieb0ga0
- mitsubishi_aa070mc01_mode
- mitsubishi_aa070mc01
- mitsubishi_aa084xe01_mode
- mitsubishi_aa084xe01
- multi_inno_mi0700a2t_30_timing
- multi_inno_mi0700a2t_30
- multi_inno_mi0700s4t_6_timing
- multi_inno_mi0700s4t_6
- multi_inno_mi0800ft_9_timing
- multi_inno_mi0800ft_9
- multi_inno_mi1010ait_1cp_timing
- multi_inno_mi1010ait_1cp
- multi_inno_mi1010z1t_1cp11_timing
- multi_inno_mi1010z1t_1cp11
- nec_nl12880bc20_05_timing
- nec_nl12880bc20_05
- nec_nl4827hc19_05b_mode
- nec_nl4827hc19_05b
- netron_dy_e231732_mode
- netron_dy_e231732
- newhaven_nhd_43_480272ef_atxl_mode
- newhaven_nhd_43_480272ef_atxl
- nlt_nl13676bc25_03f_mode
- nlt_nl13676bc25_03f
- nlt_nl192108ac18_02d_timing
- nlt_nl192108ac18_02d
- nvd_9128_mode
- nvd_9128
- okaya_rs800480t_7x0gp_timing
- okaya_rs800480t_7x0gp
- olimex_lcd_olinuxino_43ts_mode
- olimex_lcd_olinuxino_43ts
- ontat_kd50g21_40nt_a1_timing
- ontat_kd50g21_40nt_a1
- ontat_yx700wv03_mode
- ontat_yx700wv03
- ortustech_com37h3m_mode
- ortustech_com37h3m
- ortustech_com43h4m85ulc_mode
- ortustech_com43h4m85ulc
- osddisplays_osd070t1718_19ts_mode
- osddisplays_osd070t1718_19ts
- pda_91_00156_a0_mode
- pda_91_00156_a0
- powertip_ph128800t004_zza01_mode
- powertip_ph128800t004_zza01
- powertip_ph128800t006_zhc01_mode
- powertip_ph128800t006_zhc01
- powertip_ph800480t013_idf02_mode
- powertip_ph800480t013_idf02
- primeview_pm070wl4_mode
- primeview_pm070wl4
- qd43003c0_40_mode
- qd43003c0_40
- qishenglong_gopher2b_lcd_modes
- qishenglong_gopher2b_lcd
- rocktech_rk043fn48h_timing
- rocktech_rk043fn48h
- rocktech_rk070er9427_timing
- rocktech_rk070er9427
- rocktech_rk101ii01d_ct_mode
- rocktech_rk101ii01d_ct
- samsung_ltl101al01_timing
- samsung_ltl101al01
- samsung_ltn101nt05_mode
- samsung_ltn101nt05
- satoz_sat050at40h12r2_timing
- satoz_sat050at40h12r2
- sharp_lq070y3dg3b_mode
- sharp_lq070y3dg3b
- sharp_lq035q7db03_mode
- sharp_lq035q7db03
- sharp_lq101k1ly04_timing
- sharp_lq101k1ly04
- sharp_ls020b1dd01d_modes
- sharp_ls020b1dd01d
- shelly_sca07010_bfn_lnn_mode
- shelly_sca07010_bfn_lnn
- starry_kr070pe2t_mode
- starry_kr070pe2t
- startek_kd070wvfpa_mode
- startek_kd070wvfpa
- tsd_tst043015cmhx_timing
- tsd_tst043015cmhx
- tfc_s9700rtwv43tr_01b_mode
- tfc_s9700rtwv43tr_01b
- tianma_tm070jdhg30_timing
- tianma_tm070jdhg30
- tianma_tm070jvhg33
- tianma_tm070jdhg34_00_timing
- tianma_tm070jdhg34_00
- tianma_p0700wxf1mbaa
- tianma_tm070rvhg71_timing
- tianma_tm070rvhg71
- ti_nspire_cx_lcd_mode
- ti_nspire_cx_lcd_panel
- ti_nspire_classic_lcd_mode
- ti_nspire_classic_lcd_panel
- topland_tian_g07017_01_timing
- topland_tian_g07017_01
- toshiba_lt089ac29000_mode
- toshiba_lt089ac29000
- tpk_f07a_0102_mode
- tpk_f07a_0102
- tpk_f10a_0102_mode
- tpk_f10a_0102
- urt_umsh_8596md_timing
- urt_umsh_8596md_lvds
- urt_umsh_8596md_parallel
- vivax_tpc9150_panel_mode
- vivax_tpc9150_panel
- vl050_8048nt_c01_mode
- vl050_8048nt_c01
- winstar_wf35ltiacd_mode
- winstar_wf35ltiacd
- yes_optoelectronics_ytc700tlag_05_201c_mode
- yes_optoelectronics_ytc700tlag_05_201c
- mchp_ac69t88a_mode
- mchp_ac69t88a
- arm_rtsm_mode
- arm_rtsm
- platform_of_match
- panel_simple_platform_probe
- panel_simple_platform_remove
- panel_simple_platform_shutdown
- panel_simple_pm_ops
- panel_simple_platform_driver
- panel_desc_dsi
- auo_b080uan01_mode
- auo_b080uan01
- boe_tv080wum_nl0_mode
- boe_tv080wum_nl0
- lg_ld070wx3_sl01_mode
- lg_ld070wx3_sl01
- lg_lh500wx1_sd03_mode
- lg_lh500wx1_sd03
- panasonic_vvx10f004b00_mode
- panasonic_vvx10f004b00
- lg_acx467akm_7_mode
- lg_acx467akm_7
- osd101t2045_53ts_mode
- osd101t2045_53ts
- dsi_of_match
- panel_simple_dsi_probe
- panel_simple_dsi_remove
- panel_simple_dsi_shutdown
- panel_simple_dsi_driver
- panel_simple_init
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