1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019, Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <drm/drm_mipi_dsi.h>
8#include <drm/drm_modes.h>
9#include <drm/drm_panel.h>
10
11#include <linux/bitfield.h>
12#include <linux/gpio/consumer.h>
13#include <linux/delay.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/regulator/consumer.h>
17
18#include <video/mipi_display.h>
19
20/* Command2 BKx selection command */
21#define DSI_CMD2BKX_SEL 0xFF
22#define DSI_CMD1 0
23#define DSI_CMD2 BIT(4)
24#define DSI_CMD2BK_MASK GENMASK(3, 0)
25
26/* Command2, BK0 commands */
27#define DSI_CMD2_BK0_PVGAMCTRL 0xB0 /* Positive Voltage Gamma Control */
28#define DSI_CMD2_BK0_NVGAMCTRL 0xB1 /* Negative Voltage Gamma Control */
29#define DSI_CMD2_BK0_LNESET 0xC0 /* Display Line setting */
30#define DSI_CMD2_BK0_PORCTRL 0xC1 /* Porch control */
31#define DSI_CMD2_BK0_INVSEL 0xC2 /* Inversion selection, Frame Rate Control */
32
33/* Command2, BK1 commands */
34#define DSI_CMD2_BK1_VRHS 0xB0 /* Vop amplitude setting */
35#define DSI_CMD2_BK1_VCOM 0xB1 /* VCOM amplitude setting */
36#define DSI_CMD2_BK1_VGHSS 0xB2 /* VGH Voltage setting */
37#define DSI_CMD2_BK1_TESTCMD 0xB3 /* TEST Command Setting */
38#define DSI_CMD2_BK1_VGLS 0xB5 /* VGL Voltage setting */
39#define DSI_CMD2_BK1_PWCTLR1 0xB7 /* Power Control 1 */
40#define DSI_CMD2_BK1_PWCTLR2 0xB8 /* Power Control 2 */
41#define DSI_CMD2_BK1_SPD1 0xC1 /* Source pre_drive timing set1 */
42#define DSI_CMD2_BK1_SPD2 0xC2 /* Source EQ2 Setting */
43#define DSI_CMD2_BK1_MIPISET1 0xD0 /* MIPI Setting 1 */
44
45/* Command2, BK0 bytes */
46#define DSI_CMD2_BK0_GAMCTRL_AJ_MASK GENMASK(7, 6)
47#define DSI_CMD2_BK0_GAMCTRL_VC0_MASK GENMASK(3, 0)
48#define DSI_CMD2_BK0_GAMCTRL_VC4_MASK GENMASK(5, 0)
49#define DSI_CMD2_BK0_GAMCTRL_VC8_MASK GENMASK(5, 0)
50#define DSI_CMD2_BK0_GAMCTRL_VC16_MASK GENMASK(4, 0)
51#define DSI_CMD2_BK0_GAMCTRL_VC24_MASK GENMASK(4, 0)
52#define DSI_CMD2_BK0_GAMCTRL_VC52_MASK GENMASK(3, 0)
53#define DSI_CMD2_BK0_GAMCTRL_VC80_MASK GENMASK(5, 0)
54#define DSI_CMD2_BK0_GAMCTRL_VC108_MASK GENMASK(3, 0)
55#define DSI_CMD2_BK0_GAMCTRL_VC147_MASK GENMASK(3, 0)
56#define DSI_CMD2_BK0_GAMCTRL_VC175_MASK GENMASK(5, 0)
57#define DSI_CMD2_BK0_GAMCTRL_VC203_MASK GENMASK(3, 0)
58#define DSI_CMD2_BK0_GAMCTRL_VC231_MASK GENMASK(4, 0)
59#define DSI_CMD2_BK0_GAMCTRL_VC239_MASK GENMASK(4, 0)
60#define DSI_CMD2_BK0_GAMCTRL_VC247_MASK GENMASK(5, 0)
61#define DSI_CMD2_BK0_GAMCTRL_VC251_MASK GENMASK(5, 0)
62#define DSI_CMD2_BK0_GAMCTRL_VC255_MASK GENMASK(4, 0)
63#define DSI_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0)
64#define DSI_CMD2_BK0_LNESET_LDE_EN BIT(7)
65#define DSI_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0)
66#define DSI_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0)
67#define DSI_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0)
68#define DSI_CMD2_BK0_INVSEL_ONES_MASK GENMASK(5, 4)
69#define DSI_CMD2_BK0_INVSEL_NLINV_MASK GENMASK(2, 0)
70#define DSI_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0)
71
72/* Command2, BK1 bytes */
73#define DSI_CMD2_BK1_VRHA_MASK GENMASK(7, 0)
74#define DSI_CMD2_BK1_VCOM_MASK GENMASK(7, 0)
75#define DSI_CMD2_BK1_VGHSS_MASK GENMASK(3, 0)
76#define DSI_CMD2_BK1_TESTCMD_VAL BIT(7)
77#define DSI_CMD2_BK1_VGLS_ONES BIT(6)
78#define DSI_CMD2_BK1_VGLS_MASK GENMASK(3, 0)
79#define DSI_CMD2_BK1_PWRCTRL1_AP_MASK GENMASK(7, 6)
80#define DSI_CMD2_BK1_PWRCTRL1_APIS_MASK GENMASK(3, 2)
81#define DSI_CMD2_BK1_PWRCTRL1_APOS_MASK GENMASK(1, 0)
82#define DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK GENMASK(5, 4)
83#define DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK GENMASK(1, 0)
84#define DSI_CMD2_BK1_SPD1_ONES_MASK GENMASK(6, 4)
85#define DSI_CMD2_BK1_SPD1_T2D_MASK GENMASK(3, 0)
86#define DSI_CMD2_BK1_SPD2_ONES_MASK GENMASK(6, 4)
87#define DSI_CMD2_BK1_SPD2_T3D_MASK GENMASK(3, 0)
88#define DSI_CMD2_BK1_MIPISET1_ONES BIT(7)
89#define DSI_CMD2_BK1_MIPISET1_EOT_EN BIT(3)
90
91#define CFIELD_PREP(_mask, _val) \
92 (((typeof(_mask))(_val) << (__builtin_ffsll(_mask) - 1)) & (_mask))
93
94enum op_bias {
95 OP_BIAS_OFF = 0,
96 OP_BIAS_MIN,
97 OP_BIAS_MIDDLE,
98 OP_BIAS_MAX
99};
100
101struct st7701;
102
103struct st7701_panel_desc {
104 const struct drm_display_mode *mode;
105 unsigned int lanes;
106 enum mipi_dsi_pixel_format format;
107 unsigned int panel_sleep_delay;
108
109 /* TFT matrix driver configuration, panel specific. */
110 const u8 pv_gamma[16]; /* Positive voltage gamma control */
111 const u8 nv_gamma[16]; /* Negative voltage gamma control */
112 const u8 nlinv; /* Inversion selection */
113 const u32 vop_uv; /* Vop in uV */
114 const u32 vcom_uv; /* Vcom in uV */
115 const u16 vgh_mv; /* Vgh in mV */
116 const s16 vgl_mv; /* Vgl in mV */
117 const u16 avdd_mv; /* Avdd in mV */
118 const s16 avcl_mv; /* Avcl in mV */
119 const enum op_bias gamma_op_bias;
120 const enum op_bias input_op_bias;
121 const enum op_bias output_op_bias;
122 const u16 t2d_ns; /* T2D in ns */
123 const u16 t3d_ns; /* T3D in ns */
124 const bool eot_en;
125
126 /* GIP sequence, fully custom and undocumented. */
127 void (*gip_sequence)(struct st7701 *st7701);
128};
129
130struct st7701 {
131 struct drm_panel panel;
132 struct mipi_dsi_device *dsi;
133 const struct st7701_panel_desc *desc;
134
135 struct regulator_bulk_data supplies[2];
136 struct gpio_desc *reset;
137 unsigned int sleep_delay;
138 enum drm_panel_orientation orientation;
139};
140
141static inline struct st7701 *panel_to_st7701(struct drm_panel *panel)
142{
143 return container_of(panel, struct st7701, panel);
144}
145
146static inline int st7701_dsi_write(struct st7701 *st7701, const void *seq,
147 size_t len)
148{
149 return mipi_dsi_dcs_write_buffer(dsi: st7701->dsi, data: seq, len);
150}
151
152#define ST7701_DSI(st7701, seq...) \
153 { \
154 const u8 d[] = { seq }; \
155 st7701_dsi_write(st7701, d, ARRAY_SIZE(d)); \
156 }
157
158static u8 st7701_vgls_map(struct st7701 *st7701)
159{
160 const struct st7701_panel_desc *desc = st7701->desc;
161 struct {
162 s32 vgl;
163 u8 val;
164 } map[16] = {
165 { -7060, 0x0 }, { -7470, 0x1 },
166 { -7910, 0x2 }, { -8140, 0x3 },
167 { -8650, 0x4 }, { -8920, 0x5 },
168 { -9210, 0x6 }, { -9510, 0x7 },
169 { -9830, 0x8 }, { -10170, 0x9 },
170 { -10530, 0xa }, { -10910, 0xb },
171 { -11310, 0xc }, { -11730, 0xd },
172 { -12200, 0xe }, { -12690, 0xf }
173 };
174 int i;
175
176 for (i = 0; i < ARRAY_SIZE(map); i++)
177 if (desc->vgl_mv == map[i].vgl)
178 return map[i].val;
179
180 return 0;
181}
182
183static void st7701_switch_cmd_bkx(struct st7701 *st7701, bool cmd2, u8 bkx)
184{
185 u8 val;
186
187 if (cmd2)
188 val = DSI_CMD2 | FIELD_PREP(DSI_CMD2BK_MASK, bkx);
189 else
190 val = DSI_CMD1;
191
192 ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, val);
193}
194
195static void st7701_init_sequence(struct st7701 *st7701)
196{
197 const struct st7701_panel_desc *desc = st7701->desc;
198 const struct drm_display_mode *mode = desc->mode;
199 const u8 linecount8 = mode->vdisplay / 8;
200 const u8 linecountrem2 = (mode->vdisplay % 8) / 2;
201
202 ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00);
203
204 /* We need to wait 5ms before sending new commands */
205 msleep(msecs: 5);
206
207 ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
208
209 msleep(msecs: st7701->sleep_delay);
210
211 /* Command2, BK0 */
212 st7701_switch_cmd_bkx(st7701, cmd2: true, bkx: 0);
213
214 mipi_dsi_dcs_write(dsi: st7701->dsi, DSI_CMD2_BK0_PVGAMCTRL,
215 data: desc->pv_gamma, ARRAY_SIZE(desc->pv_gamma));
216 mipi_dsi_dcs_write(dsi: st7701->dsi, DSI_CMD2_BK0_NVGAMCTRL,
217 data: desc->nv_gamma, ARRAY_SIZE(desc->nv_gamma));
218 /*
219 * Vertical line count configuration:
220 * Line[6:0]: select number of vertical lines of the TFT matrix in
221 * multiples of 8 lines
222 * LDE_EN: enable sub-8-line granularity line count
223 * Line_delta[1:0]: add 0/2/4/6 extra lines to line count selected
224 * using Line[6:0]
225 *
226 * Total number of vertical lines:
227 * LN = ((Line[6:0] + 1) * 8) + (LDE_EN ? Line_delta[1:0] * 2 : 0)
228 */
229 ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET,
230 FIELD_PREP(DSI_CMD2_BK0_LNESET_LINE_MASK, linecount8 - 1) |
231 (linecountrem2 ? DSI_CMD2_BK0_LNESET_LDE_EN : 0),
232 FIELD_PREP(DSI_CMD2_BK0_LNESET_LINEDELTA, linecountrem2));
233 ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL,
234 FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VBP_MASK,
235 mode->vtotal - mode->vsync_end),
236 FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VFP_MASK,
237 mode->vsync_start - mode->vdisplay));
238 /*
239 * Horizontal pixel count configuration:
240 * PCLK = 512 + (RTNI[4:0] * 16)
241 * The PCLK is number of pixel clock per line, which matches
242 * mode htotal. The minimum is 512 PCLK.
243 */
244 ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL,
245 DSI_CMD2_BK0_INVSEL_ONES_MASK |
246 FIELD_PREP(DSI_CMD2_BK0_INVSEL_NLINV_MASK, desc->nlinv),
247 FIELD_PREP(DSI_CMD2_BK0_INVSEL_RTNI_MASK,
248 (clamp((u32)mode->htotal, 512U, 1008U) - 512) / 16));
249
250 /* Command2, BK1 */
251 st7701_switch_cmd_bkx(st7701, cmd2: true, bkx: 1);
252
253 /* Vop = 3.5375V + (VRHA[7:0] * 0.0125V) */
254 ST7701_DSI(st7701, DSI_CMD2_BK1_VRHS,
255 FIELD_PREP(DSI_CMD2_BK1_VRHA_MASK,
256 DIV_ROUND_CLOSEST(desc->vop_uv - 3537500, 12500)));
257
258 /* Vcom = 0.1V + (VCOM[7:0] * 0.0125V) */
259 ST7701_DSI(st7701, DSI_CMD2_BK1_VCOM,
260 FIELD_PREP(DSI_CMD2_BK1_VCOM_MASK,
261 DIV_ROUND_CLOSEST(desc->vcom_uv - 100000, 12500)));
262
263 /* Vgh = 11.5V + (VGHSS[7:0] * 0.5V) */
264 ST7701_DSI(st7701, DSI_CMD2_BK1_VGHSS,
265 FIELD_PREP(DSI_CMD2_BK1_VGHSS_MASK,
266 DIV_ROUND_CLOSEST(clamp(desc->vgh_mv,
267 (u16)11500,
268 (u16)17000) - 11500,
269 500)));
270
271 ST7701_DSI(st7701, DSI_CMD2_BK1_TESTCMD, DSI_CMD2_BK1_TESTCMD_VAL);
272
273 /* Vgl is non-linear */
274 ST7701_DSI(st7701, DSI_CMD2_BK1_VGLS,
275 DSI_CMD2_BK1_VGLS_ONES |
276 FIELD_PREP(DSI_CMD2_BK1_VGLS_MASK, st7701_vgls_map(st7701)));
277
278 ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR1,
279 FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_AP_MASK,
280 desc->gamma_op_bias) |
281 FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APIS_MASK,
282 desc->input_op_bias) |
283 FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APOS_MASK,
284 desc->output_op_bias));
285
286 /* Avdd = 6.2V + (AVDD[1:0] * 0.2V) , Avcl = -4.4V - (AVCL[1:0] * 0.2V) */
287 ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR2,
288 FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK,
289 DIV_ROUND_CLOSEST(desc->avdd_mv - 6200, 200)) |
290 FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK,
291 DIV_ROUND_CLOSEST(-4400 - desc->avcl_mv, 200)));
292
293 /* T2D = 0.2us * T2D[3:0] */
294 ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1,
295 DSI_CMD2_BK1_SPD1_ONES_MASK |
296 FIELD_PREP(DSI_CMD2_BK1_SPD1_T2D_MASK,
297 DIV_ROUND_CLOSEST(desc->t2d_ns, 200)));
298
299 /* T3D = 4us + (0.8us * T3D[3:0]) */
300 ST7701_DSI(st7701, DSI_CMD2_BK1_SPD2,
301 DSI_CMD2_BK1_SPD2_ONES_MASK |
302 FIELD_PREP(DSI_CMD2_BK1_SPD2_T3D_MASK,
303 DIV_ROUND_CLOSEST(desc->t3d_ns - 4000, 800)));
304
305 ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1,
306 DSI_CMD2_BK1_MIPISET1_ONES |
307 (desc->eot_en ? DSI_CMD2_BK1_MIPISET1_EOT_EN : 0));
308}
309
310static void ts8550b_gip_sequence(struct st7701 *st7701)
311{
312 /**
313 * ST7701_SPEC_V1.2 is unable to provide enough information above this
314 * specific command sequence, so grab the same from vendor BSP driver.
315 */
316 ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
317 ST7701_DSI(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E,
318 0x00, 0x00, 0x44, 0x44);
319 ST7701_DSI(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66,
320 0x00, 0x65, 0x00, 0x67, 0x00, 0x00);
321 ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);
322 ST7701_DSI(st7701, 0xE4, 0x44, 0x44);
323 ST7701_DSI(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C,
324 0xA0, 0x10, 0x78, 0x3C, 0xA0, 0x12, 0x78, 0x3C, 0xA0);
325 ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);
326 ST7701_DSI(st7701, 0xE7, 0x44, 0x44);
327 ST7701_DSI(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C,
328 0xA0, 0x11, 0x78, 0x3C, 0xA0, 0x13, 0x78, 0x3C, 0xA0);
329 ST7701_DSI(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00);
330 ST7701_DSI(st7701, 0xEC, 0x00, 0x00);
331 ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF,
332 0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF);
333}
334
335static void dmt028vghmcmi_1a_gip_sequence(struct st7701 *st7701)
336{
337 ST7701_DSI(st7701, 0xEE, 0x42);
338 ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
339
340 ST7701_DSI(st7701, 0xE1,
341 0x04, 0xA0, 0x06, 0xA0,
342 0x05, 0xA0, 0x07, 0xA0,
343 0x00, 0x44, 0x44);
344 ST7701_DSI(st7701, 0xE2,
345 0x00, 0x00, 0x00, 0x00,
346 0x00, 0x00, 0x00, 0x00,
347 0x00, 0x00, 0x00, 0x00);
348 ST7701_DSI(st7701, 0xE3,
349 0x00, 0x00, 0x22, 0x22);
350 ST7701_DSI(st7701, 0xE4, 0x44, 0x44);
351 ST7701_DSI(st7701, 0xE5,
352 0x0C, 0x90, 0xA0, 0xA0,
353 0x0E, 0x92, 0xA0, 0xA0,
354 0x08, 0x8C, 0xA0, 0xA0,
355 0x0A, 0x8E, 0xA0, 0xA0);
356 ST7701_DSI(st7701, 0xE6,
357 0x00, 0x00, 0x22, 0x22);
358 ST7701_DSI(st7701, 0xE7, 0x44, 0x44);
359 ST7701_DSI(st7701, 0xE8,
360 0x0D, 0x91, 0xA0, 0xA0,
361 0x0F, 0x93, 0xA0, 0xA0,
362 0x09, 0x8D, 0xA0, 0xA0,
363 0x0B, 0x8F, 0xA0, 0xA0);
364 ST7701_DSI(st7701, 0xEB,
365 0x00, 0x00, 0xE4, 0xE4,
366 0x44, 0x00, 0x00);
367 ST7701_DSI(st7701, 0xED,
368 0xFF, 0xF5, 0x47, 0x6F,
369 0x0B, 0xA1, 0xAB, 0xFF,
370 0xFF, 0xBA, 0x1A, 0xB0,
371 0xF6, 0x74, 0x5F, 0xFF);
372 ST7701_DSI(st7701, 0xEF,
373 0x08, 0x08, 0x08, 0x40,
374 0x3F, 0x64);
375
376 st7701_switch_cmd_bkx(st7701, cmd2: false, bkx: 0);
377
378 st7701_switch_cmd_bkx(st7701, cmd2: true, bkx: 3);
379 ST7701_DSI(st7701, 0xE6, 0x7C);
380 ST7701_DSI(st7701, 0xE8, 0x00, 0x0E);
381
382 st7701_switch_cmd_bkx(st7701, cmd2: false, bkx: 0);
383 ST7701_DSI(st7701, 0x11);
384 msleep(msecs: 120);
385
386 st7701_switch_cmd_bkx(st7701, cmd2: true, bkx: 3);
387 ST7701_DSI(st7701, 0xE8, 0x00, 0x0C);
388 msleep(msecs: 10);
389 ST7701_DSI(st7701, 0xE8, 0x00, 0x00);
390
391 st7701_switch_cmd_bkx(st7701, cmd2: false, bkx: 0);
392 ST7701_DSI(st7701, 0x11);
393 msleep(msecs: 120);
394 ST7701_DSI(st7701, 0xE8, 0x00, 0x00);
395
396 st7701_switch_cmd_bkx(st7701, cmd2: false, bkx: 0);
397
398 ST7701_DSI(st7701, 0x3A, 0x70);
399}
400
401static void kd50t048a_gip_sequence(struct st7701 *st7701)
402{
403 /**
404 * ST7701_SPEC_V1.2 is unable to provide enough information above this
405 * specific command sequence, so grab the same from vendor BSP driver.
406 */
407 ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
408 ST7701_DSI(st7701, 0xE1, 0x08, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x09,
409 0x00, 0x00, 0x33, 0x33);
410 ST7701_DSI(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
412 ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);
413 ST7701_DSI(st7701, 0xE4, 0x44, 0x44);
414 ST7701_DSI(st7701, 0xE5, 0x0E, 0x60, 0xA0, 0xA0, 0x10, 0x60, 0xA0,
415 0xA0, 0x0A, 0x60, 0xA0, 0xA0, 0x0C, 0x60, 0xA0, 0xA0);
416 ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);
417 ST7701_DSI(st7701, 0xE7, 0x44, 0x44);
418 ST7701_DSI(st7701, 0xE8, 0x0D, 0x60, 0xA0, 0xA0, 0x0F, 0x60, 0xA0,
419 0xA0, 0x09, 0x60, 0xA0, 0xA0, 0x0B, 0x60, 0xA0, 0xA0);
420 ST7701_DSI(st7701, 0xEB, 0x02, 0x01, 0xE4, 0xE4, 0x44, 0x00, 0x40);
421 ST7701_DSI(st7701, 0xEC, 0x02, 0x01);
422 ST7701_DSI(st7701, 0xED, 0xAB, 0x89, 0x76, 0x54, 0x01, 0xFF, 0xFF,
423 0xFF, 0xFF, 0xFF, 0xFF, 0x10, 0x45, 0x67, 0x98, 0xBA);
424}
425
426static void rg_arc_gip_sequence(struct st7701 *st7701)
427{
428 st7701_switch_cmd_bkx(st7701, cmd2: true, bkx: 3);
429 ST7701_DSI(st7701, 0xEF, 0x08);
430 st7701_switch_cmd_bkx(st7701, cmd2: true, bkx: 0);
431 ST7701_DSI(st7701, 0xC7, 0x04);
432 ST7701_DSI(st7701, 0xCC, 0x38);
433 st7701_switch_cmd_bkx(st7701, cmd2: true, bkx: 1);
434 ST7701_DSI(st7701, 0xB9, 0x10);
435 ST7701_DSI(st7701, 0xBC, 0x03);
436 ST7701_DSI(st7701, 0xC0, 0x89);
437 ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
438 ST7701_DSI(st7701, 0xE1, 0x04, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00,
439 0x00, 0x00, 0x20, 0x20);
440 ST7701_DSI(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
441 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
442 ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x00);
443 ST7701_DSI(st7701, 0xE4, 0x22, 0x00);
444 ST7701_DSI(st7701, 0xE5, 0x04, 0x5C, 0xA0, 0xA0, 0x06, 0x5C, 0xA0,
445 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
446 ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x00);
447 ST7701_DSI(st7701, 0xE7, 0x22, 0x00);
448 ST7701_DSI(st7701, 0xE8, 0x05, 0x5C, 0xA0, 0xA0, 0x07, 0x5C, 0xA0,
449 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
450 ST7701_DSI(st7701, 0xEB, 0x02, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00);
451 ST7701_DSI(st7701, 0xEC, 0x00, 0x00);
452 ST7701_DSI(st7701, 0xED, 0xFA, 0x45, 0x0B, 0xFF, 0xFF, 0xFF, 0xFF,
453 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xB0, 0x54, 0xAF);
454 ST7701_DSI(st7701, 0xEF, 0x08, 0x08, 0x08, 0x45, 0x3F, 0x54);
455 st7701_switch_cmd_bkx(st7701, cmd2: false, bkx: 0);
456 ST7701_DSI(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0x17);
457 ST7701_DSI(st7701, MIPI_DCS_SET_PIXEL_FORMAT, 0x77);
458 ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
459 msleep(msecs: 120);
460}
461
462static int st7701_prepare(struct drm_panel *panel)
463{
464 struct st7701 *st7701 = panel_to_st7701(panel);
465 int ret;
466
467 gpiod_set_value(desc: st7701->reset, value: 0);
468
469 ret = regulator_bulk_enable(ARRAY_SIZE(st7701->supplies),
470 consumers: st7701->supplies);
471 if (ret < 0)
472 return ret;
473 msleep(msecs: 20);
474
475 gpiod_set_value(desc: st7701->reset, value: 1);
476 msleep(msecs: 150);
477
478 st7701_init_sequence(st7701);
479
480 if (st7701->desc->gip_sequence)
481 st7701->desc->gip_sequence(st7701);
482
483 /* Disable Command2 */
484 st7701_switch_cmd_bkx(st7701, cmd2: false, bkx: 0);
485
486 return 0;
487}
488
489static int st7701_enable(struct drm_panel *panel)
490{
491 struct st7701 *st7701 = panel_to_st7701(panel);
492
493 ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00);
494
495 return 0;
496}
497
498static int st7701_disable(struct drm_panel *panel)
499{
500 struct st7701 *st7701 = panel_to_st7701(panel);
501
502 ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00);
503
504 return 0;
505}
506
507static int st7701_unprepare(struct drm_panel *panel)
508{
509 struct st7701 *st7701 = panel_to_st7701(panel);
510
511 ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00);
512
513 msleep(msecs: st7701->sleep_delay);
514
515 gpiod_set_value(desc: st7701->reset, value: 0);
516
517 /**
518 * During the Resetting period, the display will be blanked
519 * (The display is entering blanking sequence, which maximum
520 * time is 120 ms, when Reset Starts in Sleep Out –mode. The
521 * display remains the blank state in Sleep In –mode.) and
522 * then return to Default condition for Hardware Reset.
523 *
524 * So we need wait sleep_delay time to make sure reset completed.
525 */
526 msleep(msecs: st7701->sleep_delay);
527
528 regulator_bulk_disable(ARRAY_SIZE(st7701->supplies), consumers: st7701->supplies);
529
530 return 0;
531}
532
533static int st7701_get_modes(struct drm_panel *panel,
534 struct drm_connector *connector)
535{
536 struct st7701 *st7701 = panel_to_st7701(panel);
537 const struct drm_display_mode *desc_mode = st7701->desc->mode;
538 struct drm_display_mode *mode;
539
540 mode = drm_mode_duplicate(dev: connector->dev, mode: desc_mode);
541 if (!mode) {
542 dev_err(&st7701->dsi->dev, "failed to add mode %ux%u@%u\n",
543 desc_mode->hdisplay, desc_mode->vdisplay,
544 drm_mode_vrefresh(desc_mode));
545 return -ENOMEM;
546 }
547
548 drm_mode_set_name(mode);
549 drm_mode_probed_add(connector, mode);
550
551 connector->display_info.width_mm = desc_mode->width_mm;
552 connector->display_info.height_mm = desc_mode->height_mm;
553
554 /*
555 * TODO: Remove once all drm drivers call
556 * drm_connector_set_orientation_from_panel()
557 */
558 drm_connector_set_panel_orientation(connector, panel_orientation: st7701->orientation);
559
560 return 1;
561}
562
563static enum drm_panel_orientation st7701_get_orientation(struct drm_panel *panel)
564{
565 struct st7701 *st7701 = panel_to_st7701(panel);
566
567 return st7701->orientation;
568}
569
570static const struct drm_panel_funcs st7701_funcs = {
571 .disable = st7701_disable,
572 .unprepare = st7701_unprepare,
573 .prepare = st7701_prepare,
574 .enable = st7701_enable,
575 .get_modes = st7701_get_modes,
576 .get_orientation = st7701_get_orientation,
577};
578
579static const struct drm_display_mode ts8550b_mode = {
580 .clock = 27500,
581
582 .hdisplay = 480,
583 .hsync_start = 480 + 38,
584 .hsync_end = 480 + 38 + 12,
585 .htotal = 480 + 38 + 12 + 12,
586
587 .vdisplay = 854,
588 .vsync_start = 854 + 18,
589 .vsync_end = 854 + 18 + 8,
590 .vtotal = 854 + 18 + 8 + 4,
591
592 .width_mm = 69,
593 .height_mm = 139,
594
595 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
596};
597
598static const struct st7701_panel_desc ts8550b_desc = {
599 .mode = &ts8550b_mode,
600 .lanes = 2,
601 .format = MIPI_DSI_FMT_RGB888,
602 .panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */
603
604 .pv_gamma = {
605 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
606 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
607 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
608 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
609 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
610 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
611 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
612
613 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
614 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
615 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x8),
616 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x8),
617 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
618
619 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
620 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x23),
621 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
622 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
623 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
624
625 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12),
626 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
627 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2b),
628 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
629 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
630 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
631 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
632 },
633 .nv_gamma = {
634 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
635 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
636 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
637 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
638 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x2) |
639 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
640 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
641
642 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
643 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x13),
644 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x7),
645 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x9),
646 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
647
648 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
649 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22),
650 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
651 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
652 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x10),
653
654 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
655 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
656 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2c),
657 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
658 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
659 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
660 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
661 },
662 .nlinv = 7,
663 .vop_uv = 4400000,
664 .vcom_uv = 337500,
665 .vgh_mv = 15000,
666 .vgl_mv = -9510,
667 .avdd_mv = 6600,
668 .avcl_mv = -4400,
669 .gamma_op_bias = OP_BIAS_MAX,
670 .input_op_bias = OP_BIAS_MIN,
671 .output_op_bias = OP_BIAS_MIN,
672 .t2d_ns = 1600,
673 .t3d_ns = 10400,
674 .eot_en = true,
675 .gip_sequence = ts8550b_gip_sequence,
676};
677
678static const struct drm_display_mode dmt028vghmcmi_1a_mode = {
679 .clock = 22325,
680
681 .hdisplay = 480,
682 .hsync_start = 480 + 40,
683 .hsync_end = 480 + 40 + 4,
684 .htotal = 480 + 40 + 4 + 20,
685
686 .vdisplay = 640,
687 .vsync_start = 640 + 2,
688 .vsync_end = 640 + 2 + 40,
689 .vtotal = 640 + 2 + 40 + 16,
690
691 .width_mm = 56,
692 .height_mm = 78,
693
694 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
695
696 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
697};
698
699static const struct st7701_panel_desc dmt028vghmcmi_1a_desc = {
700 .mode = &dmt028vghmcmi_1a_mode,
701 .lanes = 2,
702 .format = MIPI_DSI_FMT_RGB888,
703 .panel_sleep_delay = 5, /* panel need extra 5ms for sleep out cmd */
704
705 .pv_gamma = {
706 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
707 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
708 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
709 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10),
710 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
711 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17),
712 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
713
714 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
715 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
716 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
717 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5),
718 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
719
720 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
721 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f),
722 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
723 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
724 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11),
725
726 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
727 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
728 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29),
729 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
730 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
731 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
732 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
733 },
734 .nv_gamma = {
735 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
736 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
737 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
738 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
739 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
740 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
741 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe),
742
743 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
744 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
745 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
746 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4),
747 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
748
749 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
750 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
751 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
752 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
753 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
754
755 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13),
756 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
757 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26),
758 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
759 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
760 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
761 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
762 },
763 .nlinv = 1,
764 .vop_uv = 4800000,
765 .vcom_uv = 1650000,
766 .vgh_mv = 15000,
767 .vgl_mv = -10170,
768 .avdd_mv = 6600,
769 .avcl_mv = -4400,
770 .gamma_op_bias = OP_BIAS_MIDDLE,
771 .input_op_bias = OP_BIAS_MIN,
772 .output_op_bias = OP_BIAS_MIN,
773 .t2d_ns = 1600,
774 .t3d_ns = 10400,
775 .eot_en = true,
776 .gip_sequence = dmt028vghmcmi_1a_gip_sequence,
777};
778
779static const struct drm_display_mode kd50t048a_mode = {
780 .clock = 27500,
781
782 .hdisplay = 480,
783 .hsync_start = 480 + 2,
784 .hsync_end = 480 + 2 + 10,
785 .htotal = 480 + 2 + 10 + 2,
786
787 .vdisplay = 854,
788 .vsync_start = 854 + 2,
789 .vsync_end = 854 + 2 + 2,
790 .vtotal = 854 + 2 + 2 + 17,
791
792 .width_mm = 69,
793 .height_mm = 139,
794
795 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
796};
797
798static const struct st7701_panel_desc kd50t048a_desc = {
799 .mode = &kd50t048a_mode,
800 .lanes = 2,
801 .format = MIPI_DSI_FMT_RGB888,
802 .panel_sleep_delay = 0,
803
804 .pv_gamma = {
805 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
806 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
807 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
808 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
809 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
810 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
811 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
812
813 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
814 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
815 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
816 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x2),
817 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
818
819 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
820 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1e),
821 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
822 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
823 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
824
825 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
826 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 2) |
827 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x23),
828 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
829 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
830 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
831 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
832 },
833 .nv_gamma = {
834 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
835 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
836 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
837 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xc),
838 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
839 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
840 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xc),
841
842 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
843 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
844 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
845 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x3),
846 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
847
848 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
849 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
850 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
851 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
852 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
853
854 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
855 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 2) |
856 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x24),
857 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
858 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
859 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
860 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
861 },
862 .nlinv = 1,
863 .vop_uv = 4887500,
864 .vcom_uv = 937500,
865 .vgh_mv = 15000,
866 .vgl_mv = -9510,
867 .avdd_mv = 6600,
868 .avcl_mv = -4400,
869 .gamma_op_bias = OP_BIAS_MIDDLE,
870 .input_op_bias = OP_BIAS_MIN,
871 .output_op_bias = OP_BIAS_MIN,
872 .t2d_ns = 1600,
873 .t3d_ns = 10400,
874 .eot_en = true,
875 .gip_sequence = kd50t048a_gip_sequence,
876};
877
878static const struct drm_display_mode rg_arc_mode = {
879 .clock = 25600,
880
881 .hdisplay = 480,
882 .hsync_start = 480 + 60,
883 .hsync_end = 480 + 60 + 42,
884 .htotal = 480 + 60 + 42 + 60,
885
886 .vdisplay = 640,
887 .vsync_start = 640 + 10,
888 .vsync_end = 640 + 10 + 4,
889 .vtotal = 640 + 10 + 4 + 16,
890
891 .width_mm = 63,
892 .height_mm = 84,
893
894 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
895};
896
897static const struct st7701_panel_desc rg_arc_desc = {
898 .mode = &rg_arc_mode,
899 .lanes = 2,
900 .format = MIPI_DSI_FMT_RGB888,
901 .panel_sleep_delay = 80,
902
903 .pv_gamma = {
904 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x01) |
905 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
906 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
907 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x16),
908 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
909 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1d),
910 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0e),
911
912 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
913 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x12),
914 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x06),
915 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x0c),
916 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x0a),
917
918 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x09),
919 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x25),
920 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x00),
921 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
922 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x03),
923
924 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x00),
925 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
926 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x3f),
927 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
928 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3f),
929 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
930 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1c)
931 },
932 .nv_gamma = {
933 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x01) |
934 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
935 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
936 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x16),
937 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
938 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1e),
939 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0e),
940
941 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
942 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
943 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x06),
944 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x0c),
945 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x08),
946
947 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x09),
948 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x26),
949 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x00),
950 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
951 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x15),
952
953 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x00),
954 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
955 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x3f),
956 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
957 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3f),
958 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
959 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1c)
960 },
961 .nlinv = 0,
962 .vop_uv = 4500000,
963 .vcom_uv = 762500,
964 .vgh_mv = 15000,
965 .vgl_mv = -9510,
966 .avdd_mv = 6600,
967 .avcl_mv = -4400,
968 .gamma_op_bias = OP_BIAS_MIDDLE,
969 .input_op_bias = OP_BIAS_MIN,
970 .output_op_bias = OP_BIAS_MIN,
971 .t2d_ns = 1600,
972 .t3d_ns = 10400,
973 .eot_en = true,
974 .gip_sequence = rg_arc_gip_sequence,
975};
976
977static int st7701_dsi_probe(struct mipi_dsi_device *dsi)
978{
979 const struct st7701_panel_desc *desc;
980 struct st7701 *st7701;
981 int ret;
982
983 st7701 = devm_kzalloc(dev: &dsi->dev, size: sizeof(*st7701), GFP_KERNEL);
984 if (!st7701)
985 return -ENOMEM;
986
987 desc = of_device_get_match_data(dev: &dsi->dev);
988 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
989 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
990 dsi->format = desc->format;
991 dsi->lanes = desc->lanes;
992
993 st7701->supplies[0].supply = "VCC";
994 st7701->supplies[1].supply = "IOVCC";
995
996 ret = devm_regulator_bulk_get(dev: &dsi->dev, ARRAY_SIZE(st7701->supplies),
997 consumers: st7701->supplies);
998 if (ret < 0)
999 return ret;
1000
1001 st7701->reset = devm_gpiod_get(dev: &dsi->dev, con_id: "reset", flags: GPIOD_OUT_LOW);
1002 if (IS_ERR(ptr: st7701->reset)) {
1003 dev_err(&dsi->dev, "Couldn't get our reset GPIO\n");
1004 return PTR_ERR(ptr: st7701->reset);
1005 }
1006
1007 ret = of_drm_get_panel_orientation(np: dsi->dev.of_node, orientation: &st7701->orientation);
1008 if (ret < 0)
1009 return dev_err_probe(dev: &dsi->dev, err: ret, fmt: "Failed to get orientation\n");
1010
1011 drm_panel_init(panel: &st7701->panel, dev: &dsi->dev, funcs: &st7701_funcs,
1012 DRM_MODE_CONNECTOR_DSI);
1013
1014 /**
1015 * Once sleep out has been issued, ST7701 IC required to wait 120ms
1016 * before initiating new commands.
1017 *
1018 * On top of that some panels might need an extra delay to wait, so
1019 * add panel specific delay for those cases. As now this panel specific
1020 * delay information is referenced from those panel BSP driver, example
1021 * ts8550b and there is no valid documentation for that.
1022 */
1023 st7701->sleep_delay = 120 + desc->panel_sleep_delay;
1024
1025 ret = drm_panel_of_backlight(panel: &st7701->panel);
1026 if (ret)
1027 return ret;
1028
1029 drm_panel_add(panel: &st7701->panel);
1030
1031 mipi_dsi_set_drvdata(dsi, data: st7701);
1032 st7701->dsi = dsi;
1033 st7701->desc = desc;
1034
1035 ret = mipi_dsi_attach(dsi);
1036 if (ret)
1037 goto err_attach;
1038
1039 return 0;
1040
1041err_attach:
1042 drm_panel_remove(panel: &st7701->panel);
1043 return ret;
1044}
1045
1046static void st7701_dsi_remove(struct mipi_dsi_device *dsi)
1047{
1048 struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi);
1049
1050 mipi_dsi_detach(dsi);
1051 drm_panel_remove(panel: &st7701->panel);
1052}
1053
1054static const struct of_device_id st7701_of_match[] = {
1055 { .compatible = "anbernic,rg-arc-panel", .data = &rg_arc_desc },
1056 { .compatible = "densitron,dmt028vghmcmi-1a", .data = &dmt028vghmcmi_1a_desc },
1057 { .compatible = "elida,kd50t048a", .data = &kd50t048a_desc },
1058 { .compatible = "techstar,ts8550b", .data = &ts8550b_desc },
1059 { }
1060};
1061MODULE_DEVICE_TABLE(of, st7701_of_match);
1062
1063static struct mipi_dsi_driver st7701_dsi_driver = {
1064 .probe = st7701_dsi_probe,
1065 .remove = st7701_dsi_remove,
1066 .driver = {
1067 .name = "st7701",
1068 .of_match_table = st7701_of_match,
1069 },
1070};
1071module_mipi_dsi_driver(st7701_dsi_driver);
1072
1073MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
1074MODULE_DESCRIPTION("Sitronix ST7701 LCD Panel Driver");
1075MODULE_LICENSE("GPL");
1076

source code of linux/drivers/gpu/drm/panel/panel-sitronix-st7701.c