1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
3/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
4
5#ifndef __PANFROST_DEVICE_H__
6#define __PANFROST_DEVICE_H__
7
8#include <linux/atomic.h>
9#include <linux/io-pgtable.h>
10#include <linux/pm.h>
11#include <linux/regulator/consumer.h>
12#include <linux/spinlock.h>
13#include <drm/drm_device.h>
14#include <drm/drm_mm.h>
15#include <drm/gpu_scheduler.h>
16
17#include "panfrost_devfreq.h"
18
19struct panfrost_device;
20struct panfrost_mmu;
21struct panfrost_job_slot;
22struct panfrost_job;
23struct panfrost_perfcnt;
24
25#define NUM_JOB_SLOTS 3
26#define MAX_PM_DOMAINS 5
27
28enum panfrost_drv_comp_bits {
29 PANFROST_COMP_BIT_GPU,
30 PANFROST_COMP_BIT_JOB,
31 PANFROST_COMP_BIT_MMU,
32 PANFROST_COMP_BIT_MAX
33};
34
35/**
36 * enum panfrost_gpu_pm - Supported kernel power management features
37 * @GPU_PM_CLK_DIS: Allow disabling clocks during system suspend
38 * @GPU_PM_VREG_OFF: Allow turning off regulators during system suspend
39 * @GPU_PM_RT: Allow disabling clocks and asserting the reset control during
40 * system runtime suspend
41 */
42enum panfrost_gpu_pm {
43 GPU_PM_CLK_DIS,
44 GPU_PM_VREG_OFF,
45 GPU_PM_RT
46};
47
48/**
49 * enum panfrost_gpu_quirks - GPU optional quirks
50 * @GPU_QUIRK_FORCE_AARCH64_PGTABLE: Use AARCH64_4K page table format
51 */
52enum panfrost_gpu_quirks {
53 GPU_QUIRK_FORCE_AARCH64_PGTABLE,
54};
55
56struct panfrost_features {
57 u16 id;
58 u16 revision;
59
60 u64 shader_present;
61 u64 tiler_present;
62 u64 l2_present;
63 u64 stack_present;
64 u32 as_present;
65 u32 js_present;
66
67 u32 l2_features;
68 u32 core_features;
69 u32 tiler_features;
70 u32 mem_features;
71 u32 mmu_features;
72 u32 thread_features;
73 u32 max_threads;
74 u32 thread_max_workgroup_sz;
75 u32 thread_max_barrier_sz;
76 u32 coherency_features;
77 u32 afbc_features;
78 u32 texture_features[4];
79 u32 js_features[16];
80
81 u32 nr_core_groups;
82 u32 thread_tls_alloc;
83
84 unsigned long hw_features[64 / BITS_PER_LONG];
85 unsigned long hw_issues[64 / BITS_PER_LONG];
86};
87
88/*
89 * Features that cannot be automatically detected and need matching using the
90 * compatible string, typically SoC-specific.
91 */
92struct panfrost_compatible {
93 /* Supplies count and names. */
94 int num_supplies;
95 const char * const *supply_names;
96 /*
97 * Number of power domains required, note that values 0 and 1 are
98 * handled identically, as only values > 1 need special handling.
99 */
100 int num_pm_domains;
101 /* Only required if num_pm_domains > 1. */
102 const char * const *pm_domain_names;
103
104 /* Vendor implementation quirks callback */
105 void (*vendor_quirk)(struct panfrost_device *pfdev);
106
107 /* Allowed PM features */
108 u8 pm_features;
109
110 /* GPU configuration quirks */
111 u8 gpu_quirks;
112};
113
114struct panfrost_device {
115 struct device *dev;
116 struct drm_device *ddev;
117 struct platform_device *pdev;
118 int gpu_irq;
119 int mmu_irq;
120
121 void __iomem *iomem;
122 struct clk *clock;
123 struct clk *bus_clock;
124 struct regulator_bulk_data *regulators;
125 struct reset_control *rstc;
126 /* pm_domains for devices with more than one. */
127 struct device *pm_domain_devs[MAX_PM_DOMAINS];
128 struct device_link *pm_domain_links[MAX_PM_DOMAINS];
129 bool coherent;
130
131 struct panfrost_features features;
132 const struct panfrost_compatible *comp;
133 DECLARE_BITMAP(is_suspended, PANFROST_COMP_BIT_MAX);
134
135 spinlock_t as_lock;
136 unsigned long as_in_use_mask;
137 unsigned long as_alloc_mask;
138 unsigned long as_faulty_mask;
139 struct list_head as_lru_list;
140
141 struct panfrost_job_slot *js;
142
143 struct panfrost_job *jobs[NUM_JOB_SLOTS][2];
144 struct list_head scheduled_jobs;
145
146 struct panfrost_perfcnt *perfcnt;
147 bool profile_mode;
148
149 struct mutex sched_lock;
150
151 struct {
152 struct workqueue_struct *wq;
153 struct work_struct work;
154 atomic_t pending;
155 } reset;
156
157 struct mutex shrinker_lock;
158 struct list_head shrinker_list;
159 struct shrinker *shrinker;
160
161 struct panfrost_devfreq pfdevfreq;
162
163 struct {
164 atomic_t use_count;
165 spinlock_t lock;
166 } cycle_counter;
167};
168
169struct panfrost_mmu {
170 struct panfrost_device *pfdev;
171 struct kref refcount;
172 struct io_pgtable_cfg pgtbl_cfg;
173 struct io_pgtable_ops *pgtbl_ops;
174 struct drm_mm mm;
175 spinlock_t mm_lock;
176 int as;
177 atomic_t as_count;
178 struct list_head list;
179 struct {
180 u64 transtab;
181 u64 memattr;
182 u64 transcfg;
183 } cfg;
184};
185
186struct panfrost_engine_usage {
187 unsigned long long elapsed_ns[NUM_JOB_SLOTS];
188 unsigned long long cycles[NUM_JOB_SLOTS];
189};
190
191struct panfrost_file_priv {
192 struct panfrost_device *pfdev;
193
194 struct drm_sched_entity sched_entity[NUM_JOB_SLOTS];
195
196 struct panfrost_mmu *mmu;
197
198 struct panfrost_engine_usage engine_usage;
199};
200
201static inline struct panfrost_device *to_panfrost_device(struct drm_device *ddev)
202{
203 return ddev->dev_private;
204}
205
206static inline int panfrost_model_cmp(struct panfrost_device *pfdev, s32 id)
207{
208 s32 match_id = pfdev->features.id;
209
210 if (match_id & 0xf000)
211 match_id &= 0xf00f;
212 return match_id - id;
213}
214
215static inline bool panfrost_model_is_bifrost(struct panfrost_device *pfdev)
216{
217 return panfrost_model_cmp(pfdev, id: 0x1000) >= 0;
218}
219
220static inline bool panfrost_model_eq(struct panfrost_device *pfdev, s32 id)
221{
222 return !panfrost_model_cmp(pfdev, id);
223}
224
225int panfrost_unstable_ioctl_check(void);
226
227int panfrost_device_init(struct panfrost_device *pfdev);
228void panfrost_device_fini(struct panfrost_device *pfdev);
229void panfrost_device_reset(struct panfrost_device *pfdev);
230
231extern const struct dev_pm_ops panfrost_pm_ops;
232
233enum drm_panfrost_exception_type {
234 DRM_PANFROST_EXCEPTION_OK = 0x00,
235 DRM_PANFROST_EXCEPTION_DONE = 0x01,
236 DRM_PANFROST_EXCEPTION_INTERRUPTED = 0x02,
237 DRM_PANFROST_EXCEPTION_STOPPED = 0x03,
238 DRM_PANFROST_EXCEPTION_TERMINATED = 0x04,
239 DRM_PANFROST_EXCEPTION_KABOOM = 0x05,
240 DRM_PANFROST_EXCEPTION_EUREKA = 0x06,
241 DRM_PANFROST_EXCEPTION_ACTIVE = 0x08,
242 DRM_PANFROST_EXCEPTION_MAX_NON_FAULT = 0x3f,
243 DRM_PANFROST_EXCEPTION_JOB_CONFIG_FAULT = 0x40,
244 DRM_PANFROST_EXCEPTION_JOB_POWER_FAULT = 0x41,
245 DRM_PANFROST_EXCEPTION_JOB_READ_FAULT = 0x42,
246 DRM_PANFROST_EXCEPTION_JOB_WRITE_FAULT = 0x43,
247 DRM_PANFROST_EXCEPTION_JOB_AFFINITY_FAULT = 0x44,
248 DRM_PANFROST_EXCEPTION_JOB_BUS_FAULT = 0x48,
249 DRM_PANFROST_EXCEPTION_INSTR_INVALID_PC = 0x50,
250 DRM_PANFROST_EXCEPTION_INSTR_INVALID_ENC = 0x51,
251 DRM_PANFROST_EXCEPTION_INSTR_TYPE_MISMATCH = 0x52,
252 DRM_PANFROST_EXCEPTION_INSTR_OPERAND_FAULT = 0x53,
253 DRM_PANFROST_EXCEPTION_INSTR_TLS_FAULT = 0x54,
254 DRM_PANFROST_EXCEPTION_INSTR_BARRIER_FAULT = 0x55,
255 DRM_PANFROST_EXCEPTION_INSTR_ALIGN_FAULT = 0x56,
256 DRM_PANFROST_EXCEPTION_DATA_INVALID_FAULT = 0x58,
257 DRM_PANFROST_EXCEPTION_TILE_RANGE_FAULT = 0x59,
258 DRM_PANFROST_EXCEPTION_ADDR_RANGE_FAULT = 0x5a,
259 DRM_PANFROST_EXCEPTION_IMPRECISE_FAULT = 0x5b,
260 DRM_PANFROST_EXCEPTION_OOM = 0x60,
261 DRM_PANFROST_EXCEPTION_OOM_AFBC = 0x61,
262 DRM_PANFROST_EXCEPTION_UNKNOWN = 0x7f,
263 DRM_PANFROST_EXCEPTION_DELAYED_BUS_FAULT = 0x80,
264 DRM_PANFROST_EXCEPTION_GPU_SHAREABILITY_FAULT = 0x88,
265 DRM_PANFROST_EXCEPTION_SYS_SHAREABILITY_FAULT = 0x89,
266 DRM_PANFROST_EXCEPTION_GPU_CACHEABILITY_FAULT = 0x8a,
267 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_0 = 0xc0,
268 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_1 = 0xc1,
269 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_2 = 0xc2,
270 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_3 = 0xc3,
271 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_4 = 0xc4,
272 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_IDENTITY = 0xc7,
273 DRM_PANFROST_EXCEPTION_PERM_FAULT_0 = 0xc8,
274 DRM_PANFROST_EXCEPTION_PERM_FAULT_1 = 0xc9,
275 DRM_PANFROST_EXCEPTION_PERM_FAULT_2 = 0xca,
276 DRM_PANFROST_EXCEPTION_PERM_FAULT_3 = 0xcb,
277 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_0 = 0xd0,
278 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_1 = 0xd1,
279 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_2 = 0xd2,
280 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_3 = 0xd3,
281 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_0 = 0xd8,
282 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_1 = 0xd9,
283 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_2 = 0xda,
284 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_3 = 0xdb,
285 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN0 = 0xe0,
286 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN1 = 0xe1,
287 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN2 = 0xe2,
288 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN3 = 0xe3,
289 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT0 = 0xe4,
290 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT1 = 0xe5,
291 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT2 = 0xe6,
292 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT3 = 0xe7,
293 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_0 = 0xe8,
294 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_1 = 0xe9,
295 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_2 = 0xea,
296 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_3 = 0xeb,
297 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_0 = 0xec,
298 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_1 = 0xed,
299 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_2 = 0xee,
300 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_3 = 0xef,
301};
302
303static inline bool
304panfrost_exception_is_fault(u32 exception_code)
305{
306 return exception_code > DRM_PANFROST_EXCEPTION_MAX_NON_FAULT;
307}
308
309const char *panfrost_exception_name(u32 exception_code);
310bool panfrost_exception_needs_reset(const struct panfrost_device *pfdev,
311 u32 exception_code);
312
313static inline void
314panfrost_device_schedule_reset(struct panfrost_device *pfdev)
315{
316 atomic_set(v: &pfdev->reset.pending, i: 1);
317 queue_work(wq: pfdev->reset.wq, work: &pfdev->reset.work);
318}
319
320#endif
321

source code of linux/drivers/gpu/drm/panfrost/panfrost_device.h