1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
---|---|
2 | /* |
3 | * Copyright (C) 2016 Chris Zhong <zyw@rock-chips.com> |
4 | * Copyright (C) 2016 ROCKCHIP, Inc. |
5 | */ |
6 | |
7 | #ifndef _CDN_DP_CORE_H |
8 | #define _CDN_DP_CORE_H |
9 | |
10 | #include <drm/display/drm_dp_helper.h> |
11 | #include <drm/drm_panel.h> |
12 | #include <drm/drm_probe_helper.h> |
13 | #include <sound/hdmi-codec.h> |
14 | |
15 | #include "rockchip_drm_drv.h" |
16 | |
17 | #define MAX_PHY 2 |
18 | |
19 | enum audio_format { |
20 | AFMT_I2S = 0, |
21 | AFMT_SPDIF = 1, |
22 | AFMT_UNUSED, |
23 | }; |
24 | |
25 | struct audio_info { |
26 | enum audio_format format; |
27 | int sample_rate; |
28 | int channels; |
29 | int sample_width; |
30 | }; |
31 | |
32 | enum vic_pxl_encoding_format { |
33 | PXL_RGB = 0x1, |
34 | YCBCR_4_4_4 = 0x2, |
35 | YCBCR_4_2_2 = 0x4, |
36 | YCBCR_4_2_0 = 0x8, |
37 | Y_ONLY = 0x10, |
38 | }; |
39 | |
40 | struct video_info { |
41 | bool h_sync_polarity; |
42 | bool v_sync_polarity; |
43 | bool interlaced; |
44 | int color_depth; |
45 | enum vic_pxl_encoding_format color_fmt; |
46 | }; |
47 | |
48 | struct cdn_firmware_header { |
49 | u32 size_bytes; /* size of the entire header+image(s) in bytes */ |
50 | u32 header_size; /* size of just the header in bytes */ |
51 | u32 iram_size; /* size of iram */ |
52 | u32 dram_size; /* size of dram */ |
53 | }; |
54 | |
55 | struct cdn_dp_port { |
56 | struct cdn_dp_device *dp; |
57 | struct notifier_block event_nb; |
58 | struct extcon_dev *extcon; |
59 | struct phy *phy; |
60 | u8 lanes; |
61 | bool phy_enabled; |
62 | u8 id; |
63 | }; |
64 | |
65 | struct cdn_dp_device { |
66 | struct device *dev; |
67 | struct drm_device *drm_dev; |
68 | struct drm_connector connector; |
69 | struct rockchip_encoder encoder; |
70 | struct drm_display_mode mode; |
71 | struct platform_device *audio_pdev; |
72 | struct work_struct event_work; |
73 | struct edid *edid; |
74 | |
75 | struct mutex lock; |
76 | bool connected; |
77 | bool active; |
78 | bool suspended; |
79 | |
80 | const struct firmware *fw; /* cdn dp firmware */ |
81 | unsigned int fw_version; /* cdn fw version */ |
82 | bool fw_loaded; |
83 | |
84 | void __iomem *regs; |
85 | struct regmap *grf; |
86 | struct clk *core_clk; |
87 | struct clk *pclk; |
88 | struct clk *spdif_clk; |
89 | struct clk *grf_clk; |
90 | struct reset_control *spdif_rst; |
91 | struct reset_control *dptx_rst; |
92 | struct reset_control *apb_rst; |
93 | struct reset_control *core_rst; |
94 | struct audio_info audio_info; |
95 | struct video_info video_info; |
96 | struct cdn_dp_port *port[MAX_PHY]; |
97 | u8 ports; |
98 | u8 max_lanes; |
99 | unsigned int max_rate; |
100 | u8 lanes; |
101 | int active_port; |
102 | |
103 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
104 | bool sink_has_audio; |
105 | |
106 | hdmi_codec_plugged_cb plugged_cb; |
107 | struct device *codec_dev; |
108 | }; |
109 | #endif /* _CDN_DP_CORE_H */ |
110 |