1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
5 */
6
7#ifndef _ROCKCHIP_DRM_VOP_H
8#define _ROCKCHIP_DRM_VOP_H
9
10/*
11 * major: IP major version, used for IP structure
12 * minor: big feature change under same structure
13 */
14#define VOP_VERSION(major, minor) ((major) << 8 | (minor))
15#define VOP_MAJOR(version) ((version) >> 8)
16#define VOP_MINOR(version) ((version) & 0xff)
17
18#define NUM_YUV2YUV_COEFFICIENTS 12
19
20/* AFBC supports a number of configurable modes. Relevant to us is block size
21 * (16x16 or 32x8), storage modifiers (SPARSE, SPLIT), and the YUV-like
22 * colourspace transform (YTR). 16x16 SPARSE mode is always used. SPLIT mode
23 * could be enabled via the hreg_block_split register, but is not currently
24 * handled. The colourspace transform is implicitly always assumed by the
25 * decoder, so consumers must use this transform as well.
26 *
27 * Failure to match modifiers will cause errors displaying AFBC buffers
28 * produced by conformant AFBC producers, including Mesa.
29 */
30#define ROCKCHIP_AFBC_MOD \
31 DRM_FORMAT_MOD_ARM_AFBC( \
32 AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | AFBC_FORMAT_MOD_SPARSE \
33 | AFBC_FORMAT_MOD_YTR \
34 )
35
36enum vop_data_format {
37 VOP_FMT_ARGB8888 = 0,
38 VOP_FMT_RGB888,
39 VOP_FMT_RGB565,
40 VOP_FMT_YUV420SP = 4,
41 VOP_FMT_YUV422SP,
42 VOP_FMT_YUV444SP,
43};
44
45struct vop_rect {
46 int width;
47 int height;
48};
49
50struct vop_reg {
51 uint32_t mask;
52 uint16_t offset;
53 uint8_t shift;
54 bool write_mask;
55 bool relaxed;
56};
57
58struct vop_afbc {
59 struct vop_reg enable;
60 struct vop_reg win_sel;
61 struct vop_reg format;
62 struct vop_reg rb_swap;
63 struct vop_reg uv_swap;
64 struct vop_reg auto_gating_en;
65 struct vop_reg block_split_en;
66 struct vop_reg pic_vir_width;
67 struct vop_reg tile_num;
68 struct vop_reg hreg_block_split;
69 struct vop_reg pic_offset;
70 struct vop_reg pic_size;
71 struct vop_reg dsp_offset;
72 struct vop_reg transform_offset;
73 struct vop_reg hdr_ptr;
74 struct vop_reg half_block_en;
75 struct vop_reg xmirror;
76 struct vop_reg ymirror;
77 struct vop_reg rotate_270;
78 struct vop_reg rotate_90;
79 struct vop_reg rstn;
80};
81
82struct vop_modeset {
83 struct vop_reg htotal_pw;
84 struct vop_reg hact_st_end;
85 struct vop_reg hpost_st_end;
86 struct vop_reg vtotal_pw;
87 struct vop_reg vact_st_end;
88 struct vop_reg vpost_st_end;
89};
90
91struct vop_output {
92 struct vop_reg pin_pol;
93 struct vop_reg dp_pin_pol;
94 struct vop_reg dp_dclk_pol;
95 struct vop_reg edp_pin_pol;
96 struct vop_reg edp_dclk_pol;
97 struct vop_reg hdmi_pin_pol;
98 struct vop_reg hdmi_dclk_pol;
99 struct vop_reg mipi_pin_pol;
100 struct vop_reg mipi_dclk_pol;
101 struct vop_reg rgb_pin_pol;
102 struct vop_reg rgb_dclk_pol;
103 struct vop_reg dp_en;
104 struct vop_reg edp_en;
105 struct vop_reg hdmi_en;
106 struct vop_reg mipi_en;
107 struct vop_reg mipi_dual_channel_en;
108 struct vop_reg rgb_en;
109};
110
111struct vop_common {
112 struct vop_reg cfg_done;
113 struct vop_reg dsp_blank;
114 struct vop_reg data_blank;
115 struct vop_reg pre_dither_down;
116 struct vop_reg dither_down_sel;
117 struct vop_reg dither_down_mode;
118 struct vop_reg dither_down_en;
119 struct vop_reg dither_up;
120 struct vop_reg dsp_lut_en;
121 struct vop_reg update_gamma_lut;
122 struct vop_reg lut_buffer_index;
123 struct vop_reg gate_en;
124 struct vop_reg mmu_en;
125 struct vop_reg out_mode;
126 struct vop_reg standby;
127};
128
129struct vop_misc {
130 struct vop_reg global_regdone_en;
131};
132
133struct vop_intr {
134 const int *intrs;
135 uint32_t nintrs;
136
137 struct vop_reg line_flag_num[2];
138 struct vop_reg enable;
139 struct vop_reg clear;
140 struct vop_reg status;
141};
142
143struct vop_scl_extension {
144 struct vop_reg cbcr_vsd_mode;
145 struct vop_reg cbcr_vsu_mode;
146 struct vop_reg cbcr_hsd_mode;
147 struct vop_reg cbcr_ver_scl_mode;
148 struct vop_reg cbcr_hor_scl_mode;
149 struct vop_reg yrgb_vsd_mode;
150 struct vop_reg yrgb_vsu_mode;
151 struct vop_reg yrgb_hsd_mode;
152 struct vop_reg yrgb_ver_scl_mode;
153 struct vop_reg yrgb_hor_scl_mode;
154 struct vop_reg line_load_mode;
155 struct vop_reg cbcr_axi_gather_num;
156 struct vop_reg yrgb_axi_gather_num;
157 struct vop_reg vsd_cbcr_gt2;
158 struct vop_reg vsd_cbcr_gt4;
159 struct vop_reg vsd_yrgb_gt2;
160 struct vop_reg vsd_yrgb_gt4;
161 struct vop_reg bic_coe_sel;
162 struct vop_reg cbcr_axi_gather_en;
163 struct vop_reg yrgb_axi_gather_en;
164 struct vop_reg lb_mode;
165};
166
167struct vop_scl_regs {
168 const struct vop_scl_extension *ext;
169
170 struct vop_reg scale_yrgb_x;
171 struct vop_reg scale_yrgb_y;
172 struct vop_reg scale_cbcr_x;
173 struct vop_reg scale_cbcr_y;
174};
175
176struct vop_yuv2yuv_phy {
177 struct vop_reg y2r_coefficients[NUM_YUV2YUV_COEFFICIENTS];
178};
179
180struct vop_win_phy {
181 const struct vop_scl_regs *scl;
182 const uint32_t *data_formats;
183 uint32_t nformats;
184 const uint64_t *format_modifiers;
185
186 struct vop_reg enable;
187 struct vop_reg gate;
188 struct vop_reg format;
189 struct vop_reg fmt_10;
190 struct vop_reg rb_swap;
191 struct vop_reg uv_swap;
192 struct vop_reg act_info;
193 struct vop_reg dsp_info;
194 struct vop_reg dsp_st;
195 struct vop_reg yrgb_mst;
196 struct vop_reg uv_mst;
197 struct vop_reg yrgb_vir;
198 struct vop_reg uv_vir;
199 struct vop_reg y_mir_en;
200 struct vop_reg x_mir_en;
201
202 struct vop_reg dst_alpha_ctl;
203 struct vop_reg src_alpha_ctl;
204 struct vop_reg alpha_pre_mul;
205 struct vop_reg alpha_mode;
206 struct vop_reg alpha_en;
207 struct vop_reg channel;
208};
209
210struct vop_win_yuv2yuv_data {
211 uint32_t base;
212 const struct vop_yuv2yuv_phy *phy;
213 struct vop_reg y2r_en;
214};
215
216struct vop_win_data {
217 uint32_t base;
218 const struct vop_win_phy *phy;
219 enum drm_plane_type type;
220};
221
222struct vop_data {
223 uint32_t version;
224 const struct vop_intr *intr;
225 const struct vop_common *common;
226 const struct vop_misc *misc;
227 const struct vop_modeset *modeset;
228 const struct vop_output *output;
229 const struct vop_afbc *afbc;
230 const struct vop_win_yuv2yuv_data *win_yuv2yuv;
231 const struct vop_win_data *win;
232 unsigned int win_size;
233 unsigned int lut_size;
234 struct vop_rect max_output;
235
236#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
237#define VOP_FEATURE_INTERNAL_RGB BIT(1)
238 u64 feature;
239};
240
241/* interrupt define */
242#define DSP_HOLD_VALID_INTR (1 << 0)
243#define FS_INTR (1 << 1)
244#define LINE_FLAG_INTR (1 << 2)
245#define BUS_ERROR_INTR (1 << 3)
246
247#define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
248 LINE_FLAG_INTR | BUS_ERROR_INTR)
249
250#define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
251#define FS_INTR_EN(x) ((x) << 5)
252#define LINE_FLAG_INTR_EN(x) ((x) << 6)
253#define BUS_ERROR_INTR_EN(x) ((x) << 7)
254#define DSP_HOLD_VALID_INTR_MASK (1 << 4)
255#define FS_INTR_MASK (1 << 5)
256#define LINE_FLAG_INTR_MASK (1 << 6)
257#define BUS_ERROR_INTR_MASK (1 << 7)
258
259#define INTR_CLR_SHIFT 8
260#define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
261#define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
262#define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
263#define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
264
265#define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
266#define DSP_LINE_NUM_MASK (0x1fff << 12)
267
268/* src alpha ctrl define */
269#define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
270#define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
271#define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
272#define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
273#define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
274#define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
275#define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
276#define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
277/* dst alpha ctrl define */
278#define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
279
280enum alpha_mode {
281 ALPHA_STRAIGHT,
282 ALPHA_INVERSE,
283};
284
285enum global_blend_mode {
286 ALPHA_GLOBAL,
287 ALPHA_PER_PIX,
288 ALPHA_PER_PIX_GLOBAL,
289};
290
291enum alpha_cal_mode {
292 ALPHA_SATURATION,
293 ALPHA_NO_SATURATION,
294};
295
296enum color_mode {
297 ALPHA_SRC_PRE_MUL,
298 ALPHA_SRC_NO_PRE_MUL,
299};
300
301enum factor_mode {
302 ALPHA_ZERO,
303 ALPHA_ONE,
304 ALPHA_SRC,
305 ALPHA_SRC_INVERSE,
306 ALPHA_SRC_GLOBAL,
307};
308
309enum scale_mode {
310 SCALE_NONE = 0x0,
311 SCALE_UP = 0x1,
312 SCALE_DOWN = 0x2
313};
314
315enum lb_mode {
316 LB_YUV_3840X5 = 0x0,
317 LB_YUV_2560X8 = 0x1,
318 LB_RGB_3840X2 = 0x2,
319 LB_RGB_2560X4 = 0x3,
320 LB_RGB_1920X5 = 0x4,
321 LB_RGB_1280X8 = 0x5
322};
323
324enum sacle_up_mode {
325 SCALE_UP_BIL = 0x0,
326 SCALE_UP_BIC = 0x1
327};
328
329enum scale_down_mode {
330 SCALE_DOWN_BIL = 0x0,
331 SCALE_DOWN_AVG = 0x1
332};
333
334enum dither_down_mode {
335 RGB888_TO_RGB565 = 0x0,
336 RGB888_TO_RGB666 = 0x1
337};
338
339enum dither_down_mode_sel {
340 DITHER_DOWN_ALLEGRO = 0x0,
341 DITHER_DOWN_FRC = 0x1
342};
343
344enum vop_pol {
345 HSYNC_POSITIVE = 0,
346 VSYNC_POSITIVE = 1,
347 DEN_NEGATIVE = 2
348};
349
350#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
351#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
352#define SCL_MAX_VSKIPLINES 4
353#define MIN_SCL_FT_AFTER_VSKIP 1
354
355static inline uint16_t scl_cal_scale(int src, int dst, int shift)
356{
357 return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
358}
359
360static inline uint16_t scl_cal_scale2(int src, int dst)
361{
362 return ((src - 1) << 12) / (dst - 1);
363}
364
365#define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
366#define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
367#define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
368
369static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
370 int vskiplines)
371{
372 int act_height;
373
374 act_height = DIV_ROUND_UP(src_h, vskiplines);
375
376 if (act_height == dst_h)
377 return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
378
379 return GET_SCL_FT_BILI_DN(act_height, dst_h);
380}
381
382static inline enum scale_mode scl_get_scl_mode(int src, int dst)
383{
384 if (src < dst)
385 return SCALE_UP;
386 else if (src > dst)
387 return SCALE_DOWN;
388
389 return SCALE_NONE;
390}
391
392static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
393{
394 uint32_t vskiplines;
395
396 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
397 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
398 break;
399
400 return vskiplines;
401}
402
403static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
404{
405 int lb_mode;
406
407 if (is_yuv) {
408 if (width > 1280)
409 lb_mode = LB_YUV_3840X5;
410 else
411 lb_mode = LB_YUV_2560X8;
412 } else {
413 if (width > 2560)
414 lb_mode = LB_RGB_3840X2;
415 else if (width > 1920)
416 lb_mode = LB_RGB_2560X4;
417 else
418 lb_mode = LB_RGB_1920X5;
419 }
420
421 return lb_mode;
422}
423
424extern const struct component_ops vop_component_ops;
425#endif /* _ROCKCHIP_DRM_VOP_H */
426

source code of linux/drivers/gpu/drm/rockchip/rockchip_drm_vop.h