1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd |
4 | * Author:Mark Yao <mark.yao@rock-chips.com> |
5 | */ |
6 | |
7 | #include <linux/clk.h> |
8 | #include <linux/component.h> |
9 | #include <linux/delay.h> |
10 | #include <linux/iopoll.h> |
11 | #include <linux/kernel.h> |
12 | #include <linux/log2.h> |
13 | #include <linux/module.h> |
14 | #include <linux/of.h> |
15 | #include <linux/overflow.h> |
16 | #include <linux/platform_device.h> |
17 | #include <linux/pm_runtime.h> |
18 | #include <linux/reset.h> |
19 | |
20 | #include <drm/drm.h> |
21 | #include <drm/drm_atomic.h> |
22 | #include <drm/drm_atomic_uapi.h> |
23 | #include <drm/drm_blend.h> |
24 | #include <drm/drm_crtc.h> |
25 | #include <drm/drm_flip_work.h> |
26 | #include <drm/drm_fourcc.h> |
27 | #include <drm/drm_framebuffer.h> |
28 | #include <drm/drm_gem_atomic_helper.h> |
29 | #include <drm/drm_gem_framebuffer_helper.h> |
30 | #include <drm/drm_probe_helper.h> |
31 | #include <drm/drm_self_refresh_helper.h> |
32 | #include <drm/drm_vblank.h> |
33 | |
34 | #ifdef CONFIG_DRM_ANALOGIX_DP |
35 | #include <drm/bridge/analogix_dp.h> |
36 | #endif |
37 | |
38 | #include "rockchip_drm_drv.h" |
39 | #include "rockchip_drm_gem.h" |
40 | #include "rockchip_drm_fb.h" |
41 | #include "rockchip_drm_vop.h" |
42 | #include "rockchip_rgb.h" |
43 | |
44 | #define VOP_WIN_SET(vop, win, name, v) \ |
45 | vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) |
46 | #define VOP_SCL_SET(vop, win, name, v) \ |
47 | vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) |
48 | #define VOP_SCL_SET_EXT(vop, win, name, v) \ |
49 | vop_reg_set(vop, &win->phy->scl->ext->name, \ |
50 | win->base, ~0, v, #name) |
51 | |
52 | #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ |
53 | do { \ |
54 | if (win_yuv2yuv && win_yuv2yuv->name.mask) \ |
55 | vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ |
56 | } while (0) |
57 | |
58 | #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ |
59 | do { \ |
60 | if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ |
61 | vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ |
62 | } while (0) |
63 | |
64 | #define VOP_INTR_SET_MASK(vop, name, mask, v) \ |
65 | vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) |
66 | |
67 | #define VOP_REG_SET(vop, group, name, v) \ |
68 | vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) |
69 | |
70 | #define VOP_HAS_REG(vop, group, name) \ |
71 | (!!(vop->data->group->name.mask)) |
72 | |
73 | #define VOP_INTR_SET_TYPE(vop, name, type, v) \ |
74 | do { \ |
75 | int i, reg = 0, mask = 0; \ |
76 | for (i = 0; i < vop->data->intr->nintrs; i++) { \ |
77 | if (vop->data->intr->intrs[i] & type) { \ |
78 | reg |= (v) << i; \ |
79 | mask |= 1 << i; \ |
80 | } \ |
81 | } \ |
82 | VOP_INTR_SET_MASK(vop, name, mask, reg); \ |
83 | } while (0) |
84 | #define VOP_INTR_GET_TYPE(vop, name, type) \ |
85 | vop_get_intr_type(vop, &vop->data->intr->name, type) |
86 | |
87 | #define VOP_WIN_GET(vop, win, name) \ |
88 | vop_read_reg(vop, win->base, &win->phy->name) |
89 | |
90 | #define VOP_WIN_HAS_REG(win, name) \ |
91 | (!!(win->phy->name.mask)) |
92 | |
93 | #define VOP_WIN_GET_YRGBADDR(vop, win) \ |
94 | vop_readl(vop, win->base + win->phy->yrgb_mst.offset) |
95 | |
96 | #define VOP_WIN_TO_INDEX(vop_win) \ |
97 | ((vop_win) - (vop_win)->vop->win) |
98 | |
99 | #define VOP_AFBC_SET(vop, name, v) \ |
100 | do { \ |
101 | if ((vop)->data->afbc) \ |
102 | vop_reg_set((vop), &(vop)->data->afbc->name, \ |
103 | 0, ~0, v, #name); \ |
104 | } while (0) |
105 | |
106 | #define to_vop(x) container_of(x, struct vop, crtc) |
107 | #define to_vop_win(x) container_of(x, struct vop_win, base) |
108 | |
109 | #define AFBC_FMT_RGB565 0x0 |
110 | #define AFBC_FMT_U8U8U8U8 0x5 |
111 | #define AFBC_FMT_U8U8U8 0x4 |
112 | |
113 | #define AFBC_TILE_16x16 BIT(4) |
114 | |
115 | /* |
116 | * The coefficients of the following matrix are all fixed points. |
117 | * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. |
118 | * They are all represented in two's complement. |
119 | */ |
120 | static const uint32_t bt601_yuv2rgb[] = { |
121 | 0x4A8, 0x0, 0x662, |
122 | 0x4A8, 0x1E6F, 0x1CBF, |
123 | 0x4A8, 0x812, 0x0, |
124 | 0x321168, 0x0877CF, 0x2EB127 |
125 | }; |
126 | |
127 | enum vop_pending { |
128 | VOP_PENDING_FB_UNREF, |
129 | }; |
130 | |
131 | struct vop_win { |
132 | struct drm_plane base; |
133 | const struct vop_win_data *data; |
134 | const struct vop_win_yuv2yuv_data *yuv2yuv_data; |
135 | struct vop *vop; |
136 | }; |
137 | |
138 | struct rockchip_rgb; |
139 | struct vop { |
140 | struct drm_crtc crtc; |
141 | struct device *dev; |
142 | struct drm_device *drm_dev; |
143 | bool is_enabled; |
144 | |
145 | struct completion dsp_hold_completion; |
146 | unsigned int win_enabled; |
147 | |
148 | /* protected by dev->event_lock */ |
149 | struct drm_pending_vblank_event *event; |
150 | |
151 | struct drm_flip_work fb_unref_work; |
152 | unsigned long pending; |
153 | |
154 | struct completion line_flag_completion; |
155 | |
156 | const struct vop_data *data; |
157 | |
158 | uint32_t *regsbak; |
159 | void __iomem *regs; |
160 | void __iomem *lut_regs; |
161 | |
162 | /* physical map length of vop register */ |
163 | uint32_t len; |
164 | |
165 | /* one time only one process allowed to config the register */ |
166 | spinlock_t reg_lock; |
167 | /* lock vop irq reg */ |
168 | spinlock_t irq_lock; |
169 | /* protects crtc enable/disable */ |
170 | struct mutex vop_lock; |
171 | |
172 | unsigned int irq; |
173 | |
174 | /* vop AHP clk */ |
175 | struct clk *hclk; |
176 | /* vop dclk */ |
177 | struct clk *dclk; |
178 | /* vop share memory frequency */ |
179 | struct clk *aclk; |
180 | |
181 | /* vop dclk reset */ |
182 | struct reset_control *dclk_rst; |
183 | |
184 | /* optional internal rgb encoder */ |
185 | struct rockchip_rgb *rgb; |
186 | |
187 | struct vop_win win[]; |
188 | }; |
189 | |
190 | static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) |
191 | { |
192 | return readl(addr: vop->regs + offset); |
193 | } |
194 | |
195 | static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, |
196 | const struct vop_reg *reg) |
197 | { |
198 | return (vop_readl(vop, offset: base + reg->offset) >> reg->shift) & reg->mask; |
199 | } |
200 | |
201 | static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, |
202 | uint32_t _offset, uint32_t _mask, uint32_t v, |
203 | const char *reg_name) |
204 | { |
205 | int offset, mask, shift; |
206 | |
207 | if (!reg || !reg->mask) { |
208 | DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n" , reg_name); |
209 | return; |
210 | } |
211 | |
212 | offset = reg->offset + _offset; |
213 | mask = reg->mask & _mask; |
214 | shift = reg->shift; |
215 | |
216 | if (reg->write_mask) { |
217 | v = ((v << shift) & 0xffff) | (mask << (shift + 16)); |
218 | } else { |
219 | uint32_t cached_val = vop->regsbak[offset >> 2]; |
220 | |
221 | v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); |
222 | vop->regsbak[offset >> 2] = v; |
223 | } |
224 | |
225 | if (reg->relaxed) |
226 | writel_relaxed(v, vop->regs + offset); |
227 | else |
228 | writel(val: v, addr: vop->regs + offset); |
229 | } |
230 | |
231 | static inline uint32_t vop_get_intr_type(struct vop *vop, |
232 | const struct vop_reg *reg, int type) |
233 | { |
234 | uint32_t i, ret = 0; |
235 | uint32_t regs = vop_read_reg(vop, base: 0, reg); |
236 | |
237 | for (i = 0; i < vop->data->intr->nintrs; i++) { |
238 | if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) |
239 | ret |= vop->data->intr->intrs[i]; |
240 | } |
241 | |
242 | return ret; |
243 | } |
244 | |
245 | static inline void vop_cfg_done(struct vop *vop) |
246 | { |
247 | VOP_REG_SET(vop, common, cfg_done, 1); |
248 | } |
249 | |
250 | static bool has_rb_swapped(uint32_t version, uint32_t format) |
251 | { |
252 | switch (format) { |
253 | case DRM_FORMAT_XBGR8888: |
254 | case DRM_FORMAT_ABGR8888: |
255 | case DRM_FORMAT_BGR565: |
256 | return true; |
257 | /* |
258 | * full framework (IP version 3.x) only need rb swapped for RGB888 and |
259 | * little framework (IP version 2.x) only need rb swapped for BGR888, |
260 | * check for 3.x to also only rb swap BGR888 for unknown vop version |
261 | */ |
262 | case DRM_FORMAT_RGB888: |
263 | return VOP_MAJOR(version) == 3; |
264 | case DRM_FORMAT_BGR888: |
265 | return VOP_MAJOR(version) != 3; |
266 | default: |
267 | return false; |
268 | } |
269 | } |
270 | |
271 | static bool has_uv_swapped(uint32_t format) |
272 | { |
273 | switch (format) { |
274 | case DRM_FORMAT_NV21: |
275 | case DRM_FORMAT_NV61: |
276 | case DRM_FORMAT_NV42: |
277 | return true; |
278 | default: |
279 | return false; |
280 | } |
281 | } |
282 | |
283 | static bool is_fmt_10(uint32_t format) |
284 | { |
285 | switch (format) { |
286 | case DRM_FORMAT_NV15: |
287 | case DRM_FORMAT_NV20: |
288 | case DRM_FORMAT_NV30: |
289 | return true; |
290 | default: |
291 | return false; |
292 | } |
293 | } |
294 | |
295 | static enum vop_data_format vop_convert_format(uint32_t format) |
296 | { |
297 | switch (format) { |
298 | case DRM_FORMAT_XRGB8888: |
299 | case DRM_FORMAT_ARGB8888: |
300 | case DRM_FORMAT_XBGR8888: |
301 | case DRM_FORMAT_ABGR8888: |
302 | return VOP_FMT_ARGB8888; |
303 | case DRM_FORMAT_RGB888: |
304 | case DRM_FORMAT_BGR888: |
305 | return VOP_FMT_RGB888; |
306 | case DRM_FORMAT_RGB565: |
307 | case DRM_FORMAT_BGR565: |
308 | return VOP_FMT_RGB565; |
309 | case DRM_FORMAT_NV12: |
310 | case DRM_FORMAT_NV15: |
311 | case DRM_FORMAT_NV21: |
312 | return VOP_FMT_YUV420SP; |
313 | case DRM_FORMAT_NV16: |
314 | case DRM_FORMAT_NV20: |
315 | case DRM_FORMAT_NV61: |
316 | return VOP_FMT_YUV422SP; |
317 | case DRM_FORMAT_NV24: |
318 | case DRM_FORMAT_NV30: |
319 | case DRM_FORMAT_NV42: |
320 | return VOP_FMT_YUV444SP; |
321 | default: |
322 | DRM_ERROR("unsupported format[%08x]\n" , format); |
323 | return -EINVAL; |
324 | } |
325 | } |
326 | |
327 | static int vop_convert_afbc_format(uint32_t format) |
328 | { |
329 | switch (format) { |
330 | case DRM_FORMAT_XRGB8888: |
331 | case DRM_FORMAT_ARGB8888: |
332 | case DRM_FORMAT_XBGR8888: |
333 | case DRM_FORMAT_ABGR8888: |
334 | return AFBC_FMT_U8U8U8U8; |
335 | case DRM_FORMAT_RGB888: |
336 | case DRM_FORMAT_BGR888: |
337 | return AFBC_FMT_U8U8U8; |
338 | case DRM_FORMAT_RGB565: |
339 | case DRM_FORMAT_BGR565: |
340 | return AFBC_FMT_RGB565; |
341 | default: |
342 | DRM_DEBUG_KMS("unsupported AFBC format[%08x]\n" , format); |
343 | return -EINVAL; |
344 | } |
345 | } |
346 | |
347 | static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, |
348 | uint32_t dst, bool is_horizontal, |
349 | int vsu_mode, int *vskiplines) |
350 | { |
351 | uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; |
352 | |
353 | if (vskiplines) |
354 | *vskiplines = 0; |
355 | |
356 | if (is_horizontal) { |
357 | if (mode == SCALE_UP) |
358 | val = GET_SCL_FT_BIC(src, dst); |
359 | else if (mode == SCALE_DOWN) |
360 | val = GET_SCL_FT_BILI_DN(src, dst); |
361 | } else { |
362 | if (mode == SCALE_UP) { |
363 | if (vsu_mode == SCALE_UP_BIL) |
364 | val = GET_SCL_FT_BILI_UP(src, dst); |
365 | else |
366 | val = GET_SCL_FT_BIC(src, dst); |
367 | } else if (mode == SCALE_DOWN) { |
368 | if (vskiplines) { |
369 | *vskiplines = scl_get_vskiplines(srch: src, dsth: dst); |
370 | val = scl_get_bili_dn_vskip(src_h: src, dst_h: dst, |
371 | vskiplines: *vskiplines); |
372 | } else { |
373 | val = GET_SCL_FT_BILI_DN(src, dst); |
374 | } |
375 | } |
376 | } |
377 | |
378 | return val; |
379 | } |
380 | |
381 | static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, |
382 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, |
383 | uint32_t dst_h, const struct drm_format_info *info) |
384 | { |
385 | uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; |
386 | uint16_t cbcr_hor_scl_mode = SCALE_NONE; |
387 | uint16_t cbcr_ver_scl_mode = SCALE_NONE; |
388 | bool is_yuv = false; |
389 | uint16_t cbcr_src_w = src_w / info->hsub; |
390 | uint16_t cbcr_src_h = src_h / info->vsub; |
391 | uint16_t vsu_mode; |
392 | uint16_t lb_mode; |
393 | uint32_t val; |
394 | int vskiplines; |
395 | |
396 | if (info->is_yuv) |
397 | is_yuv = true; |
398 | |
399 | if (dst_w > 3840) { |
400 | DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n" ); |
401 | return; |
402 | } |
403 | |
404 | if (!win->phy->scl->ext) { |
405 | VOP_SCL_SET(vop, win, scale_yrgb_x, |
406 | scl_cal_scale2(src_w, dst_w)); |
407 | VOP_SCL_SET(vop, win, scale_yrgb_y, |
408 | scl_cal_scale2(src_h, dst_h)); |
409 | if (is_yuv) { |
410 | VOP_SCL_SET(vop, win, scale_cbcr_x, |
411 | scl_cal_scale2(cbcr_src_w, dst_w)); |
412 | VOP_SCL_SET(vop, win, scale_cbcr_y, |
413 | scl_cal_scale2(cbcr_src_h, dst_h)); |
414 | } |
415 | return; |
416 | } |
417 | |
418 | yrgb_hor_scl_mode = scl_get_scl_mode(src: src_w, dst: dst_w); |
419 | yrgb_ver_scl_mode = scl_get_scl_mode(src: src_h, dst: dst_h); |
420 | |
421 | if (is_yuv) { |
422 | cbcr_hor_scl_mode = scl_get_scl_mode(src: cbcr_src_w, dst: dst_w); |
423 | cbcr_ver_scl_mode = scl_get_scl_mode(src: cbcr_src_h, dst: dst_h); |
424 | if (cbcr_hor_scl_mode == SCALE_DOWN) |
425 | lb_mode = scl_vop_cal_lb_mode(width: dst_w, is_yuv: true); |
426 | else |
427 | lb_mode = scl_vop_cal_lb_mode(width: cbcr_src_w, is_yuv: true); |
428 | } else { |
429 | if (yrgb_hor_scl_mode == SCALE_DOWN) |
430 | lb_mode = scl_vop_cal_lb_mode(width: dst_w, is_yuv: false); |
431 | else |
432 | lb_mode = scl_vop_cal_lb_mode(width: src_w, is_yuv: false); |
433 | } |
434 | |
435 | VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); |
436 | if (lb_mode == LB_RGB_3840X2) { |
437 | if (yrgb_ver_scl_mode != SCALE_NONE) { |
438 | DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n" ); |
439 | return; |
440 | } |
441 | if (cbcr_ver_scl_mode != SCALE_NONE) { |
442 | DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n" ); |
443 | return; |
444 | } |
445 | vsu_mode = SCALE_UP_BIL; |
446 | } else if (lb_mode == LB_RGB_2560X4) { |
447 | vsu_mode = SCALE_UP_BIL; |
448 | } else { |
449 | vsu_mode = SCALE_UP_BIC; |
450 | } |
451 | |
452 | val = scl_vop_cal_scale(mode: yrgb_hor_scl_mode, src: src_w, dst: dst_w, |
453 | is_horizontal: true, vsu_mode: 0, NULL); |
454 | VOP_SCL_SET(vop, win, scale_yrgb_x, val); |
455 | val = scl_vop_cal_scale(mode: yrgb_ver_scl_mode, src: src_h, dst: dst_h, |
456 | is_horizontal: false, vsu_mode, vskiplines: &vskiplines); |
457 | VOP_SCL_SET(vop, win, scale_yrgb_y, val); |
458 | |
459 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); |
460 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); |
461 | |
462 | VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); |
463 | VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); |
464 | VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); |
465 | VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); |
466 | VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); |
467 | if (is_yuv) { |
468 | val = scl_vop_cal_scale(mode: cbcr_hor_scl_mode, src: cbcr_src_w, |
469 | dst: dst_w, is_horizontal: true, vsu_mode: 0, NULL); |
470 | VOP_SCL_SET(vop, win, scale_cbcr_x, val); |
471 | val = scl_vop_cal_scale(mode: cbcr_ver_scl_mode, src: cbcr_src_h, |
472 | dst: dst_h, is_horizontal: false, vsu_mode, vskiplines: &vskiplines); |
473 | VOP_SCL_SET(vop, win, scale_cbcr_y, val); |
474 | |
475 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); |
476 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); |
477 | VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); |
478 | VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); |
479 | VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); |
480 | VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); |
481 | VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); |
482 | } |
483 | } |
484 | |
485 | static void vop_dsp_hold_valid_irq_enable(struct vop *vop) |
486 | { |
487 | unsigned long flags; |
488 | |
489 | if (WARN_ON(!vop->is_enabled)) |
490 | return; |
491 | |
492 | spin_lock_irqsave(&vop->irq_lock, flags); |
493 | |
494 | VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); |
495 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); |
496 | |
497 | spin_unlock_irqrestore(lock: &vop->irq_lock, flags); |
498 | } |
499 | |
500 | static void vop_dsp_hold_valid_irq_disable(struct vop *vop) |
501 | { |
502 | unsigned long flags; |
503 | |
504 | if (WARN_ON(!vop->is_enabled)) |
505 | return; |
506 | |
507 | spin_lock_irqsave(&vop->irq_lock, flags); |
508 | |
509 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); |
510 | |
511 | spin_unlock_irqrestore(lock: &vop->irq_lock, flags); |
512 | } |
513 | |
514 | /* |
515 | * (1) each frame starts at the start of the Vsync pulse which is signaled by |
516 | * the "FRAME_SYNC" interrupt. |
517 | * (2) the active data region of each frame ends at dsp_vact_end |
518 | * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, |
519 | * to get "LINE_FLAG" interrupt at the end of the active on screen data. |
520 | * |
521 | * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end |
522 | * Interrupts |
523 | * LINE_FLAG -------------------------------+ |
524 | * FRAME_SYNC ----+ | |
525 | * | | |
526 | * v v |
527 | * | Vsync | Vbp | Vactive | Vfp | |
528 | * ^ ^ ^ ^ |
529 | * | | | | |
530 | * | | | | |
531 | * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END |
532 | * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END |
533 | * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END |
534 | * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END |
535 | */ |
536 | static bool vop_line_flag_irq_is_enabled(struct vop *vop) |
537 | { |
538 | uint32_t line_flag_irq; |
539 | unsigned long flags; |
540 | |
541 | spin_lock_irqsave(&vop->irq_lock, flags); |
542 | |
543 | line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); |
544 | |
545 | spin_unlock_irqrestore(lock: &vop->irq_lock, flags); |
546 | |
547 | return !!line_flag_irq; |
548 | } |
549 | |
550 | static void vop_line_flag_irq_enable(struct vop *vop) |
551 | { |
552 | unsigned long flags; |
553 | |
554 | if (WARN_ON(!vop->is_enabled)) |
555 | return; |
556 | |
557 | spin_lock_irqsave(&vop->irq_lock, flags); |
558 | |
559 | VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); |
560 | VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); |
561 | |
562 | spin_unlock_irqrestore(lock: &vop->irq_lock, flags); |
563 | } |
564 | |
565 | static void vop_line_flag_irq_disable(struct vop *vop) |
566 | { |
567 | unsigned long flags; |
568 | |
569 | if (WARN_ON(!vop->is_enabled)) |
570 | return; |
571 | |
572 | spin_lock_irqsave(&vop->irq_lock, flags); |
573 | |
574 | VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); |
575 | |
576 | spin_unlock_irqrestore(lock: &vop->irq_lock, flags); |
577 | } |
578 | |
579 | static int vop_core_clks_enable(struct vop *vop) |
580 | { |
581 | int ret; |
582 | |
583 | ret = clk_enable(clk: vop->hclk); |
584 | if (ret < 0) |
585 | return ret; |
586 | |
587 | ret = clk_enable(clk: vop->aclk); |
588 | if (ret < 0) |
589 | goto err_disable_hclk; |
590 | |
591 | return 0; |
592 | |
593 | err_disable_hclk: |
594 | clk_disable(clk: vop->hclk); |
595 | return ret; |
596 | } |
597 | |
598 | static void vop_core_clks_disable(struct vop *vop) |
599 | { |
600 | clk_disable(clk: vop->aclk); |
601 | clk_disable(clk: vop->hclk); |
602 | } |
603 | |
604 | static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) |
605 | { |
606 | const struct vop_win_data *win = vop_win->data; |
607 | |
608 | if (win->phy->scl && win->phy->scl->ext) { |
609 | VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); |
610 | VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); |
611 | VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); |
612 | VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); |
613 | } |
614 | |
615 | VOP_WIN_SET(vop, win, enable, 0); |
616 | vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); |
617 | } |
618 | |
619 | static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) |
620 | { |
621 | struct vop *vop = to_vop(crtc); |
622 | int ret, i; |
623 | |
624 | ret = pm_runtime_resume_and_get(dev: vop->dev); |
625 | if (ret < 0) { |
626 | DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n" , ret); |
627 | return ret; |
628 | } |
629 | |
630 | ret = vop_core_clks_enable(vop); |
631 | if (WARN_ON(ret < 0)) |
632 | goto err_put_pm_runtime; |
633 | |
634 | ret = clk_enable(clk: vop->dclk); |
635 | if (WARN_ON(ret < 0)) |
636 | goto err_disable_core; |
637 | |
638 | /* |
639 | * Slave iommu shares power, irq and clock with vop. It was associated |
640 | * automatically with this master device via common driver code. |
641 | * Now that we have enabled the clock we attach it to the shared drm |
642 | * mapping. |
643 | */ |
644 | ret = rockchip_drm_dma_attach_device(drm_dev: vop->drm_dev, dev: vop->dev); |
645 | if (ret) { |
646 | DRM_DEV_ERROR(vop->dev, |
647 | "failed to attach dma mapping, %d\n" , ret); |
648 | goto err_disable_dclk; |
649 | } |
650 | |
651 | spin_lock(lock: &vop->reg_lock); |
652 | for (i = 0; i < vop->len; i += 4) |
653 | writel_relaxed(vop->regsbak[i / 4], vop->regs + i); |
654 | |
655 | /* |
656 | * We need to make sure that all windows are disabled before we |
657 | * enable the crtc. Otherwise we might try to scan from a destroyed |
658 | * buffer later. |
659 | * |
660 | * In the case of enable-after-PSR, we don't need to worry about this |
661 | * case since the buffer is guaranteed to be valid and disabling the |
662 | * window will result in screen glitches on PSR exit. |
663 | */ |
664 | if (!old_state || !old_state->self_refresh_active) { |
665 | for (i = 0; i < vop->data->win_size; i++) { |
666 | struct vop_win *vop_win = &vop->win[i]; |
667 | |
668 | vop_win_disable(vop, vop_win); |
669 | } |
670 | } |
671 | |
672 | if (vop->data->afbc) { |
673 | struct rockchip_crtc_state *s; |
674 | /* |
675 | * Disable AFBC and forget there was a vop window with AFBC |
676 | */ |
677 | VOP_AFBC_SET(vop, enable, 0); |
678 | s = to_rockchip_crtc_state(crtc->state); |
679 | s->enable_afbc = false; |
680 | } |
681 | |
682 | vop_cfg_done(vop); |
683 | |
684 | spin_unlock(lock: &vop->reg_lock); |
685 | |
686 | /* |
687 | * At here, vop clock & iommu is enable, R/W vop regs would be safe. |
688 | */ |
689 | vop->is_enabled = true; |
690 | |
691 | spin_lock(lock: &vop->reg_lock); |
692 | |
693 | VOP_REG_SET(vop, common, standby, 1); |
694 | |
695 | spin_unlock(lock: &vop->reg_lock); |
696 | |
697 | drm_crtc_vblank_on(crtc); |
698 | |
699 | return 0; |
700 | |
701 | err_disable_dclk: |
702 | clk_disable(clk: vop->dclk); |
703 | err_disable_core: |
704 | vop_core_clks_disable(vop); |
705 | err_put_pm_runtime: |
706 | pm_runtime_put_sync(dev: vop->dev); |
707 | return ret; |
708 | } |
709 | |
710 | static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) |
711 | { |
712 | struct vop *vop = to_vop(crtc); |
713 | int i; |
714 | |
715 | spin_lock(lock: &vop->reg_lock); |
716 | |
717 | for (i = 0; i < vop->data->win_size; i++) { |
718 | struct vop_win *vop_win = &vop->win[i]; |
719 | const struct vop_win_data *win = vop_win->data; |
720 | |
721 | VOP_WIN_SET(vop, win, enable, |
722 | enabled && (vop->win_enabled & BIT(i))); |
723 | } |
724 | vop_cfg_done(vop); |
725 | |
726 | spin_unlock(lock: &vop->reg_lock); |
727 | } |
728 | |
729 | static void vop_crtc_atomic_disable(struct drm_crtc *crtc, |
730 | struct drm_atomic_state *state) |
731 | { |
732 | struct vop *vop = to_vop(crtc); |
733 | |
734 | WARN_ON(vop->event); |
735 | |
736 | if (crtc->state->self_refresh_active) |
737 | rockchip_drm_set_win_enabled(crtc, enabled: false); |
738 | |
739 | if (crtc->state->self_refresh_active) |
740 | goto out; |
741 | |
742 | mutex_lock(&vop->vop_lock); |
743 | |
744 | drm_crtc_vblank_off(crtc); |
745 | |
746 | /* |
747 | * Vop standby will take effect at end of current frame, |
748 | * if dsp hold valid irq happen, it means standby complete. |
749 | * |
750 | * we must wait standby complete when we want to disable aclk, |
751 | * if not, memory bus maybe dead. |
752 | */ |
753 | reinit_completion(x: &vop->dsp_hold_completion); |
754 | vop_dsp_hold_valid_irq_enable(vop); |
755 | |
756 | spin_lock(lock: &vop->reg_lock); |
757 | |
758 | VOP_REG_SET(vop, common, standby, 1); |
759 | |
760 | spin_unlock(lock: &vop->reg_lock); |
761 | |
762 | if (!wait_for_completion_timeout(x: &vop->dsp_hold_completion, |
763 | timeout: msecs_to_jiffies(m: 200))) |
764 | WARN(1, "%s: timed out waiting for DSP hold" , crtc->name); |
765 | |
766 | vop_dsp_hold_valid_irq_disable(vop); |
767 | |
768 | vop->is_enabled = false; |
769 | |
770 | /* |
771 | * vop standby complete, so iommu detach is safe. |
772 | */ |
773 | rockchip_drm_dma_detach_device(drm_dev: vop->drm_dev, dev: vop->dev); |
774 | |
775 | clk_disable(clk: vop->dclk); |
776 | vop_core_clks_disable(vop); |
777 | pm_runtime_put(dev: vop->dev); |
778 | |
779 | mutex_unlock(lock: &vop->vop_lock); |
780 | |
781 | out: |
782 | if (crtc->state->event && !crtc->state->active) { |
783 | spin_lock_irq(lock: &crtc->dev->event_lock); |
784 | drm_crtc_send_vblank_event(crtc, e: crtc->state->event); |
785 | spin_unlock_irq(lock: &crtc->dev->event_lock); |
786 | |
787 | crtc->state->event = NULL; |
788 | } |
789 | } |
790 | |
791 | static inline bool rockchip_afbc(u64 modifier) |
792 | { |
793 | return modifier == ROCKCHIP_AFBC_MOD; |
794 | } |
795 | |
796 | static bool rockchip_mod_supported(struct drm_plane *plane, |
797 | u32 format, u64 modifier) |
798 | { |
799 | if (modifier == DRM_FORMAT_MOD_LINEAR) |
800 | return true; |
801 | |
802 | if (!rockchip_afbc(modifier)) { |
803 | DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n" , modifier); |
804 | |
805 | return false; |
806 | } |
807 | |
808 | return vop_convert_afbc_format(format) >= 0; |
809 | } |
810 | |
811 | static int vop_plane_atomic_check(struct drm_plane *plane, |
812 | struct drm_atomic_state *state) |
813 | { |
814 | struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, |
815 | plane); |
816 | struct drm_crtc *crtc = new_plane_state->crtc; |
817 | struct drm_crtc_state *crtc_state; |
818 | struct drm_framebuffer *fb = new_plane_state->fb; |
819 | struct vop_win *vop_win = to_vop_win(plane); |
820 | const struct vop_win_data *win = vop_win->data; |
821 | int ret; |
822 | int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : |
823 | DRM_PLANE_NO_SCALING; |
824 | int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : |
825 | DRM_PLANE_NO_SCALING; |
826 | |
827 | if (!crtc || WARN_ON(!fb)) |
828 | return 0; |
829 | |
830 | crtc_state = drm_atomic_get_existing_crtc_state(state, |
831 | crtc); |
832 | if (WARN_ON(!crtc_state)) |
833 | return -EINVAL; |
834 | |
835 | ret = drm_atomic_helper_check_plane_state(plane_state: new_plane_state, crtc_state, |
836 | min_scale, max_scale, |
837 | can_position: true, can_update_disabled: true); |
838 | if (ret) |
839 | return ret; |
840 | |
841 | if (!new_plane_state->visible) |
842 | return 0; |
843 | |
844 | ret = vop_convert_format(format: fb->format->format); |
845 | if (ret < 0) |
846 | return ret; |
847 | |
848 | /* |
849 | * Src.x1 can be odd when do clip, but yuv plane start point |
850 | * need align with 2 pixel. |
851 | */ |
852 | if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) { |
853 | DRM_DEBUG_KMS("Invalid Source: Yuv format not support odd xpos\n" ); |
854 | return -EINVAL; |
855 | } |
856 | |
857 | if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) { |
858 | DRM_DEBUG_KMS("Invalid Source: Yuv format does not support this rotation\n" ); |
859 | return -EINVAL; |
860 | } |
861 | |
862 | if (rockchip_afbc(modifier: fb->modifier)) { |
863 | struct vop *vop = to_vop(crtc); |
864 | |
865 | if (!vop->data->afbc) { |
866 | DRM_DEBUG_KMS("vop does not support AFBC\n" ); |
867 | return -EINVAL; |
868 | } |
869 | |
870 | ret = vop_convert_afbc_format(format: fb->format->format); |
871 | if (ret < 0) |
872 | return ret; |
873 | |
874 | if (new_plane_state->src.x1 || new_plane_state->src.y1) { |
875 | DRM_DEBUG_KMS("AFBC does not support offset display, " \ |
876 | "xpos=%d, ypos=%d, offset=%d\n" , |
877 | new_plane_state->src.x1, new_plane_state->src.y1, |
878 | fb->offsets[0]); |
879 | return -EINVAL; |
880 | } |
881 | |
882 | if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) { |
883 | DRM_DEBUG_KMS("No rotation support in AFBC, rotation=%d\n" , |
884 | new_plane_state->rotation); |
885 | return -EINVAL; |
886 | } |
887 | } |
888 | |
889 | return 0; |
890 | } |
891 | |
892 | static void vop_plane_atomic_disable(struct drm_plane *plane, |
893 | struct drm_atomic_state *state) |
894 | { |
895 | struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, |
896 | plane); |
897 | struct vop_win *vop_win = to_vop_win(plane); |
898 | struct vop *vop = to_vop(old_state->crtc); |
899 | |
900 | if (!old_state->crtc) |
901 | return; |
902 | |
903 | spin_lock(lock: &vop->reg_lock); |
904 | |
905 | vop_win_disable(vop, vop_win); |
906 | |
907 | spin_unlock(lock: &vop->reg_lock); |
908 | } |
909 | |
910 | static void vop_plane_atomic_update(struct drm_plane *plane, |
911 | struct drm_atomic_state *state) |
912 | { |
913 | struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, |
914 | plane); |
915 | struct drm_crtc *crtc = new_state->crtc; |
916 | struct vop_win *vop_win = to_vop_win(plane); |
917 | const struct vop_win_data *win = vop_win->data; |
918 | const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; |
919 | struct vop *vop = to_vop(new_state->crtc); |
920 | struct drm_framebuffer *fb = new_state->fb; |
921 | unsigned int actual_w, actual_h; |
922 | unsigned int dsp_stx, dsp_sty; |
923 | uint32_t act_info, dsp_info, dsp_st; |
924 | struct drm_rect *src = &new_state->src; |
925 | struct drm_rect *dest = &new_state->dst; |
926 | struct drm_gem_object *obj, *uv_obj; |
927 | struct rockchip_gem_object *rk_obj, *rk_uv_obj; |
928 | unsigned long offset; |
929 | dma_addr_t dma_addr; |
930 | uint32_t val; |
931 | bool rb_swap, uv_swap; |
932 | int win_index = VOP_WIN_TO_INDEX(vop_win); |
933 | int format; |
934 | int is_yuv = fb->format->is_yuv; |
935 | int i; |
936 | |
937 | /* |
938 | * can't update plane when vop is disabled. |
939 | */ |
940 | if (WARN_ON(!crtc)) |
941 | return; |
942 | |
943 | if (WARN_ON(!vop->is_enabled)) |
944 | return; |
945 | |
946 | if (!new_state->visible) { |
947 | vop_plane_atomic_disable(plane, state); |
948 | return; |
949 | } |
950 | |
951 | obj = fb->obj[0]; |
952 | rk_obj = to_rockchip_obj(obj); |
953 | |
954 | actual_w = drm_rect_width(r: src) >> 16; |
955 | actual_h = drm_rect_height(r: src) >> 16; |
956 | act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); |
957 | |
958 | dsp_info = (drm_rect_height(r: dest) - 1) << 16; |
959 | dsp_info |= (drm_rect_width(r: dest) - 1) & 0xffff; |
960 | |
961 | dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; |
962 | dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; |
963 | dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); |
964 | |
965 | if (fb->format->char_per_block[0]) |
966 | offset = drm_format_info_min_pitch(info: fb->format, plane: 0, |
967 | buffer_width: src->x1 >> 16); |
968 | else |
969 | offset = (src->x1 >> 16) * fb->format->cpp[0]; |
970 | |
971 | offset += (src->y1 >> 16) * fb->pitches[0]; |
972 | dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; |
973 | |
974 | /* |
975 | * For y-mirroring we need to move address |
976 | * to the beginning of the last line. |
977 | */ |
978 | if (new_state->rotation & DRM_MODE_REFLECT_Y) |
979 | dma_addr += (actual_h - 1) * fb->pitches[0]; |
980 | |
981 | format = vop_convert_format(format: fb->format->format); |
982 | |
983 | spin_lock(lock: &vop->reg_lock); |
984 | |
985 | if (rockchip_afbc(modifier: fb->modifier)) { |
986 | int afbc_format = vop_convert_afbc_format(format: fb->format->format); |
987 | |
988 | VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16); |
989 | VOP_AFBC_SET(vop, hreg_block_split, 0); |
990 | VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win)); |
991 | VOP_AFBC_SET(vop, hdr_ptr, dma_addr); |
992 | VOP_AFBC_SET(vop, pic_size, act_info); |
993 | } |
994 | |
995 | VOP_WIN_SET(vop, win, format, format); |
996 | VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format)); |
997 | VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); |
998 | VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); |
999 | VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); |
1000 | VOP_WIN_SET(vop, win, y_mir_en, |
1001 | (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); |
1002 | VOP_WIN_SET(vop, win, x_mir_en, |
1003 | (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); |
1004 | |
1005 | if (is_yuv) { |
1006 | uv_obj = fb->obj[1]; |
1007 | rk_uv_obj = to_rockchip_obj(uv_obj); |
1008 | |
1009 | if (fb->format->char_per_block[1]) |
1010 | offset = drm_format_info_min_pitch(info: fb->format, plane: 1, |
1011 | buffer_width: src->x1 >> 16); |
1012 | else |
1013 | offset = (src->x1 >> 16) * fb->format->cpp[1]; |
1014 | offset /= fb->format->hsub; |
1015 | offset += (src->y1 >> 16) * fb->pitches[1] / fb->format->vsub; |
1016 | |
1017 | dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; |
1018 | VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); |
1019 | VOP_WIN_SET(vop, win, uv_mst, dma_addr); |
1020 | |
1021 | for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { |
1022 | VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, |
1023 | win_yuv2yuv, |
1024 | y2r_coefficients[i], |
1025 | bt601_yuv2rgb[i]); |
1026 | } |
1027 | |
1028 | uv_swap = has_uv_swapped(format: fb->format->format); |
1029 | VOP_WIN_SET(vop, win, uv_swap, uv_swap); |
1030 | } |
1031 | |
1032 | if (win->phy->scl) |
1033 | scl_vop_cal_scl_fac(vop, win, src_w: actual_w, src_h: actual_h, |
1034 | dst_w: drm_rect_width(r: dest), dst_h: drm_rect_height(r: dest), |
1035 | info: fb->format); |
1036 | |
1037 | VOP_WIN_SET(vop, win, act_info, act_info); |
1038 | VOP_WIN_SET(vop, win, dsp_info, dsp_info); |
1039 | VOP_WIN_SET(vop, win, dsp_st, dsp_st); |
1040 | |
1041 | rb_swap = has_rb_swapped(version: vop->data->version, format: fb->format->format); |
1042 | VOP_WIN_SET(vop, win, rb_swap, rb_swap); |
1043 | |
1044 | /* |
1045 | * Blending win0 with the background color doesn't seem to work |
1046 | * correctly. We only get the background color, no matter the contents |
1047 | * of the win0 framebuffer. However, blending pre-multiplied color |
1048 | * with the default opaque black default background color is a no-op, |
1049 | * so we can just disable blending to get the correct result. |
1050 | */ |
1051 | if (fb->format->has_alpha && win_index > 0) { |
1052 | VOP_WIN_SET(vop, win, dst_alpha_ctl, |
1053 | DST_FACTOR_M0(ALPHA_SRC_INVERSE)); |
1054 | val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | |
1055 | SRC_ALPHA_M0(ALPHA_STRAIGHT) | |
1056 | SRC_BLEND_M0(ALPHA_PER_PIX) | |
1057 | SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | |
1058 | SRC_FACTOR_M0(ALPHA_ONE); |
1059 | VOP_WIN_SET(vop, win, src_alpha_ctl, val); |
1060 | |
1061 | VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL); |
1062 | VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX); |
1063 | VOP_WIN_SET(vop, win, alpha_en, 1); |
1064 | } else { |
1065 | VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); |
1066 | VOP_WIN_SET(vop, win, alpha_en, 0); |
1067 | } |
1068 | |
1069 | VOP_WIN_SET(vop, win, enable, 1); |
1070 | vop->win_enabled |= BIT(win_index); |
1071 | spin_unlock(lock: &vop->reg_lock); |
1072 | } |
1073 | |
1074 | static int vop_plane_atomic_async_check(struct drm_plane *plane, |
1075 | struct drm_atomic_state *state) |
1076 | { |
1077 | struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, |
1078 | plane); |
1079 | struct vop_win *vop_win = to_vop_win(plane); |
1080 | const struct vop_win_data *win = vop_win->data; |
1081 | int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : |
1082 | DRM_PLANE_NO_SCALING; |
1083 | int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : |
1084 | DRM_PLANE_NO_SCALING; |
1085 | struct drm_crtc_state *crtc_state; |
1086 | |
1087 | if (plane != new_plane_state->crtc->cursor) |
1088 | return -EINVAL; |
1089 | |
1090 | if (!plane->state) |
1091 | return -EINVAL; |
1092 | |
1093 | if (!plane->state->fb) |
1094 | return -EINVAL; |
1095 | |
1096 | if (state) |
1097 | crtc_state = drm_atomic_get_existing_crtc_state(state, |
1098 | crtc: new_plane_state->crtc); |
1099 | else /* Special case for asynchronous cursor updates. */ |
1100 | crtc_state = plane->crtc->state; |
1101 | |
1102 | return drm_atomic_helper_check_plane_state(plane_state: plane->state, crtc_state, |
1103 | min_scale, max_scale, |
1104 | can_position: true, can_update_disabled: true); |
1105 | } |
1106 | |
1107 | static void vop_plane_atomic_async_update(struct drm_plane *plane, |
1108 | struct drm_atomic_state *state) |
1109 | { |
1110 | struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, |
1111 | plane); |
1112 | struct vop *vop = to_vop(plane->state->crtc); |
1113 | struct drm_framebuffer *old_fb = plane->state->fb; |
1114 | |
1115 | plane->state->crtc_x = new_state->crtc_x; |
1116 | plane->state->crtc_y = new_state->crtc_y; |
1117 | plane->state->crtc_h = new_state->crtc_h; |
1118 | plane->state->crtc_w = new_state->crtc_w; |
1119 | plane->state->src_x = new_state->src_x; |
1120 | plane->state->src_y = new_state->src_y; |
1121 | plane->state->src_h = new_state->src_h; |
1122 | plane->state->src_w = new_state->src_w; |
1123 | swap(plane->state->fb, new_state->fb); |
1124 | |
1125 | if (vop->is_enabled) { |
1126 | vop_plane_atomic_update(plane, state); |
1127 | spin_lock(lock: &vop->reg_lock); |
1128 | vop_cfg_done(vop); |
1129 | spin_unlock(lock: &vop->reg_lock); |
1130 | |
1131 | /* |
1132 | * A scanout can still be occurring, so we can't drop the |
1133 | * reference to the old framebuffer. To solve this we get a |
1134 | * reference to old_fb and set a worker to release it later. |
1135 | * FIXME: if we perform 500 async_update calls before the |
1136 | * vblank, then we can have 500 different framebuffers waiting |
1137 | * to be released. |
1138 | */ |
1139 | if (old_fb && plane->state->fb != old_fb) { |
1140 | drm_framebuffer_get(fb: old_fb); |
1141 | WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); |
1142 | drm_flip_work_queue(work: &vop->fb_unref_work, val: old_fb); |
1143 | set_bit(nr: VOP_PENDING_FB_UNREF, addr: &vop->pending); |
1144 | } |
1145 | } |
1146 | } |
1147 | |
1148 | static const struct drm_plane_helper_funcs plane_helper_funcs = { |
1149 | .atomic_check = vop_plane_atomic_check, |
1150 | .atomic_update = vop_plane_atomic_update, |
1151 | .atomic_disable = vop_plane_atomic_disable, |
1152 | .atomic_async_check = vop_plane_atomic_async_check, |
1153 | .atomic_async_update = vop_plane_atomic_async_update, |
1154 | }; |
1155 | |
1156 | static const struct drm_plane_funcs vop_plane_funcs = { |
1157 | .update_plane = drm_atomic_helper_update_plane, |
1158 | .disable_plane = drm_atomic_helper_disable_plane, |
1159 | .destroy = drm_plane_cleanup, |
1160 | .reset = drm_atomic_helper_plane_reset, |
1161 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, |
1162 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, |
1163 | .format_mod_supported = rockchip_mod_supported, |
1164 | }; |
1165 | |
1166 | static int vop_crtc_enable_vblank(struct drm_crtc *crtc) |
1167 | { |
1168 | struct vop *vop = to_vop(crtc); |
1169 | unsigned long flags; |
1170 | |
1171 | if (WARN_ON(!vop->is_enabled)) |
1172 | return -EPERM; |
1173 | |
1174 | spin_lock_irqsave(&vop->irq_lock, flags); |
1175 | |
1176 | VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); |
1177 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); |
1178 | |
1179 | spin_unlock_irqrestore(lock: &vop->irq_lock, flags); |
1180 | |
1181 | return 0; |
1182 | } |
1183 | |
1184 | static void vop_crtc_disable_vblank(struct drm_crtc *crtc) |
1185 | { |
1186 | struct vop *vop = to_vop(crtc); |
1187 | unsigned long flags; |
1188 | |
1189 | if (WARN_ON(!vop->is_enabled)) |
1190 | return; |
1191 | |
1192 | spin_lock_irqsave(&vop->irq_lock, flags); |
1193 | |
1194 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); |
1195 | |
1196 | spin_unlock_irqrestore(lock: &vop->irq_lock, flags); |
1197 | } |
1198 | |
1199 | static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, |
1200 | const struct drm_display_mode *mode) |
1201 | { |
1202 | struct vop *vop = to_vop(crtc); |
1203 | |
1204 | if (vop->data->max_output.width && mode->hdisplay > vop->data->max_output.width) |
1205 | return MODE_BAD_HVALUE; |
1206 | |
1207 | return MODE_OK; |
1208 | } |
1209 | |
1210 | static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, |
1211 | const struct drm_display_mode *mode, |
1212 | struct drm_display_mode *adjusted_mode) |
1213 | { |
1214 | struct vop *vop = to_vop(crtc); |
1215 | unsigned long rate; |
1216 | |
1217 | /* |
1218 | * Clock craziness. |
1219 | * |
1220 | * Key points: |
1221 | * |
1222 | * - DRM works in kHz. |
1223 | * - Clock framework works in Hz. |
1224 | * - Rockchip's clock driver picks the clock rate that is the |
1225 | * same _OR LOWER_ than the one requested. |
1226 | * |
1227 | * Action plan: |
1228 | * |
1229 | * 1. Try to set the exact rate first, and confirm the clock framework |
1230 | * can provide it. |
1231 | * |
1232 | * 2. If the clock framework cannot provide the exact rate, we should |
1233 | * add 999 Hz to the requested rate. That way if the clock we need |
1234 | * is 60000001 Hz (~60 MHz) and DRM tells us to make 60000 kHz then |
1235 | * the clock framework will actually give us the right clock. |
1236 | * |
1237 | * 3. Get the clock framework to round the rate for us to tell us |
1238 | * what it will actually make. |
1239 | * |
1240 | * 4. Store the rounded up rate so that we don't need to worry about |
1241 | * this in the actual clk_set_rate(). |
1242 | */ |
1243 | rate = clk_round_rate(clk: vop->dclk, rate: adjusted_mode->clock * 1000); |
1244 | if (rate / 1000 != adjusted_mode->clock) |
1245 | rate = clk_round_rate(clk: vop->dclk, |
1246 | rate: adjusted_mode->clock * 1000 + 999); |
1247 | adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); |
1248 | |
1249 | return true; |
1250 | } |
1251 | |
1252 | static bool vop_dsp_lut_is_enabled(struct vop *vop) |
1253 | { |
1254 | return vop_read_reg(vop, base: 0, reg: &vop->data->common->dsp_lut_en); |
1255 | } |
1256 | |
1257 | static u32 vop_lut_buffer_index(struct vop *vop) |
1258 | { |
1259 | return vop_read_reg(vop, base: 0, reg: &vop->data->common->lut_buffer_index); |
1260 | } |
1261 | |
1262 | static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) |
1263 | { |
1264 | struct drm_color_lut *lut = crtc->state->gamma_lut->data; |
1265 | unsigned int i, bpc = ilog2(vop->data->lut_size); |
1266 | |
1267 | for (i = 0; i < crtc->gamma_size; i++) { |
1268 | u32 word; |
1269 | |
1270 | word = (drm_color_lut_extract(user_input: lut[i].red, bit_precision: bpc) << (2 * bpc)) | |
1271 | (drm_color_lut_extract(user_input: lut[i].green, bit_precision: bpc) << bpc) | |
1272 | drm_color_lut_extract(user_input: lut[i].blue, bit_precision: bpc); |
1273 | writel(val: word, addr: vop->lut_regs + i * 4); |
1274 | } |
1275 | } |
1276 | |
1277 | static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, |
1278 | struct drm_crtc_state *old_state) |
1279 | { |
1280 | struct drm_crtc_state *state = crtc->state; |
1281 | unsigned int idle; |
1282 | u32 lut_idx, old_idx; |
1283 | int ret; |
1284 | |
1285 | if (!vop->lut_regs) |
1286 | return; |
1287 | |
1288 | if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) { |
1289 | /* |
1290 | * To disable gamma (gamma_lut is null) or to write |
1291 | * an update to the LUT, clear dsp_lut_en. |
1292 | */ |
1293 | spin_lock(lock: &vop->reg_lock); |
1294 | VOP_REG_SET(vop, common, dsp_lut_en, 0); |
1295 | vop_cfg_done(vop); |
1296 | spin_unlock(lock: &vop->reg_lock); |
1297 | |
1298 | /* |
1299 | * In order to write the LUT to the internal memory, |
1300 | * we need to first make sure the dsp_lut_en bit is cleared. |
1301 | */ |
1302 | ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, |
1303 | idle, !idle, 5, 30 * 1000); |
1304 | if (ret) { |
1305 | DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n" ); |
1306 | return; |
1307 | } |
1308 | |
1309 | if (!state->gamma_lut) |
1310 | return; |
1311 | } else { |
1312 | /* |
1313 | * On RK3399 the gamma LUT can updated without clearing dsp_lut_en, |
1314 | * by setting update_gamma_lut then waiting for lut_buffer_index change |
1315 | */ |
1316 | old_idx = vop_lut_buffer_index(vop); |
1317 | } |
1318 | |
1319 | spin_lock(lock: &vop->reg_lock); |
1320 | vop_crtc_write_gamma_lut(vop, crtc); |
1321 | VOP_REG_SET(vop, common, dsp_lut_en, 1); |
1322 | VOP_REG_SET(vop, common, update_gamma_lut, 1); |
1323 | vop_cfg_done(vop); |
1324 | spin_unlock(lock: &vop->reg_lock); |
1325 | |
1326 | if (VOP_HAS_REG(vop, common, update_gamma_lut)) { |
1327 | ret = readx_poll_timeout(vop_lut_buffer_index, vop, |
1328 | lut_idx, lut_idx != old_idx, 5, 30 * 1000); |
1329 | if (ret) { |
1330 | DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n" ); |
1331 | return; |
1332 | } |
1333 | |
1334 | /* |
1335 | * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit |
1336 | * in our backup of the regs. |
1337 | */ |
1338 | spin_lock(lock: &vop->reg_lock); |
1339 | VOP_REG_SET(vop, common, update_gamma_lut, 0); |
1340 | spin_unlock(lock: &vop->reg_lock); |
1341 | } |
1342 | } |
1343 | |
1344 | static void vop_crtc_atomic_begin(struct drm_crtc *crtc, |
1345 | struct drm_atomic_state *state) |
1346 | { |
1347 | struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, |
1348 | crtc); |
1349 | struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, |
1350 | crtc); |
1351 | struct vop *vop = to_vop(crtc); |
1352 | |
1353 | /* |
1354 | * Only update GAMMA if the 'active' flag is not changed, |
1355 | * otherwise it's updated by .atomic_enable. |
1356 | */ |
1357 | if (crtc_state->color_mgmt_changed && |
1358 | !crtc_state->active_changed) |
1359 | vop_crtc_gamma_set(vop, crtc, old_state: old_crtc_state); |
1360 | } |
1361 | |
1362 | static void vop_crtc_atomic_enable(struct drm_crtc *crtc, |
1363 | struct drm_atomic_state *state) |
1364 | { |
1365 | struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, |
1366 | crtc); |
1367 | struct vop *vop = to_vop(crtc); |
1368 | const struct vop_data *vop_data = vop->data; |
1369 | struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); |
1370 | struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; |
1371 | u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; |
1372 | u16 hdisplay = adjusted_mode->hdisplay; |
1373 | u16 htotal = adjusted_mode->htotal; |
1374 | u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; |
1375 | u16 hact_end = hact_st + hdisplay; |
1376 | u16 vdisplay = adjusted_mode->vdisplay; |
1377 | u16 vtotal = adjusted_mode->vtotal; |
1378 | u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; |
1379 | u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; |
1380 | u16 vact_end = vact_st + vdisplay; |
1381 | uint32_t pin_pol, val; |
1382 | int dither_bpc = s->output_bpc ? s->output_bpc : 10; |
1383 | int ret; |
1384 | |
1385 | if (old_state && old_state->self_refresh_active) { |
1386 | drm_crtc_vblank_on(crtc); |
1387 | rockchip_drm_set_win_enabled(crtc, enabled: true); |
1388 | return; |
1389 | } |
1390 | |
1391 | mutex_lock(&vop->vop_lock); |
1392 | |
1393 | WARN_ON(vop->event); |
1394 | |
1395 | ret = vop_enable(crtc, old_state); |
1396 | if (ret) { |
1397 | mutex_unlock(lock: &vop->vop_lock); |
1398 | DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n" , ret); |
1399 | return; |
1400 | } |
1401 | pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? |
1402 | BIT(HSYNC_POSITIVE) : 0; |
1403 | pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? |
1404 | BIT(VSYNC_POSITIVE) : 0; |
1405 | VOP_REG_SET(vop, output, pin_pol, pin_pol); |
1406 | VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); |
1407 | |
1408 | switch (s->output_type) { |
1409 | case DRM_MODE_CONNECTOR_LVDS: |
1410 | VOP_REG_SET(vop, output, rgb_dclk_pol, 1); |
1411 | VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); |
1412 | VOP_REG_SET(vop, output, rgb_en, 1); |
1413 | break; |
1414 | case DRM_MODE_CONNECTOR_eDP: |
1415 | VOP_REG_SET(vop, output, edp_dclk_pol, 1); |
1416 | VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); |
1417 | VOP_REG_SET(vop, output, edp_en, 1); |
1418 | break; |
1419 | case DRM_MODE_CONNECTOR_HDMIA: |
1420 | VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); |
1421 | VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); |
1422 | VOP_REG_SET(vop, output, hdmi_en, 1); |
1423 | break; |
1424 | case DRM_MODE_CONNECTOR_DSI: |
1425 | VOP_REG_SET(vop, output, mipi_dclk_pol, 1); |
1426 | VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); |
1427 | VOP_REG_SET(vop, output, mipi_en, 1); |
1428 | VOP_REG_SET(vop, output, mipi_dual_channel_en, |
1429 | !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); |
1430 | break; |
1431 | case DRM_MODE_CONNECTOR_DisplayPort: |
1432 | VOP_REG_SET(vop, output, dp_dclk_pol, 0); |
1433 | VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); |
1434 | VOP_REG_SET(vop, output, dp_en, 1); |
1435 | break; |
1436 | default: |
1437 | DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n" , |
1438 | s->output_type); |
1439 | } |
1440 | |
1441 | /* |
1442 | * if vop is not support RGB10 output, need force RGB10 to RGB888. |
1443 | */ |
1444 | if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && |
1445 | !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) |
1446 | s->output_mode = ROCKCHIP_OUT_MODE_P888; |
1447 | |
1448 | if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) |
1449 | VOP_REG_SET(vop, common, pre_dither_down, 1); |
1450 | else |
1451 | VOP_REG_SET(vop, common, pre_dither_down, 0); |
1452 | |
1453 | if (dither_bpc == 6) { |
1454 | VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); |
1455 | VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); |
1456 | VOP_REG_SET(vop, common, dither_down_en, 1); |
1457 | } else { |
1458 | VOP_REG_SET(vop, common, dither_down_en, 0); |
1459 | } |
1460 | |
1461 | VOP_REG_SET(vop, common, out_mode, s->output_mode); |
1462 | |
1463 | VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); |
1464 | val = hact_st << 16; |
1465 | val |= hact_end; |
1466 | VOP_REG_SET(vop, modeset, hact_st_end, val); |
1467 | VOP_REG_SET(vop, modeset, hpost_st_end, val); |
1468 | |
1469 | VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); |
1470 | val = vact_st << 16; |
1471 | val |= vact_end; |
1472 | VOP_REG_SET(vop, modeset, vact_st_end, val); |
1473 | VOP_REG_SET(vop, modeset, vpost_st_end, val); |
1474 | |
1475 | VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); |
1476 | |
1477 | clk_set_rate(clk: vop->dclk, rate: adjusted_mode->clock * 1000); |
1478 | |
1479 | VOP_REG_SET(vop, common, standby, 0); |
1480 | mutex_unlock(lock: &vop->vop_lock); |
1481 | |
1482 | /* |
1483 | * If we have a GAMMA LUT in the state, then let's make sure |
1484 | * it's updated. We might be coming out of suspend, |
1485 | * which means the LUT internal memory needs to be re-written. |
1486 | */ |
1487 | if (crtc->state->gamma_lut) |
1488 | vop_crtc_gamma_set(vop, crtc, old_state); |
1489 | } |
1490 | |
1491 | static bool vop_fs_irq_is_pending(struct vop *vop) |
1492 | { |
1493 | return VOP_INTR_GET_TYPE(vop, status, FS_INTR); |
1494 | } |
1495 | |
1496 | static void vop_wait_for_irq_handler(struct vop *vop) |
1497 | { |
1498 | bool pending; |
1499 | int ret; |
1500 | |
1501 | /* |
1502 | * Spin until frame start interrupt status bit goes low, which means |
1503 | * that interrupt handler was invoked and cleared it. The timeout of |
1504 | * 10 msecs is really too long, but it is just a safety measure if |
1505 | * something goes really wrong. The wait will only happen in the very |
1506 | * unlikely case of a vblank happening exactly at the same time and |
1507 | * shouldn't exceed microseconds range. |
1508 | */ |
1509 | ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, |
1510 | !pending, 0, 10 * 1000); |
1511 | if (ret) |
1512 | DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n" ); |
1513 | |
1514 | synchronize_irq(irq: vop->irq); |
1515 | } |
1516 | |
1517 | static int vop_crtc_atomic_check(struct drm_crtc *crtc, |
1518 | struct drm_atomic_state *state) |
1519 | { |
1520 | struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, |
1521 | crtc); |
1522 | struct vop *vop = to_vop(crtc); |
1523 | struct drm_plane *plane; |
1524 | struct drm_plane_state *plane_state; |
1525 | struct rockchip_crtc_state *s; |
1526 | int afbc_planes = 0; |
1527 | |
1528 | if (vop->lut_regs && crtc_state->color_mgmt_changed && |
1529 | crtc_state->gamma_lut) { |
1530 | unsigned int len; |
1531 | |
1532 | len = drm_color_lut_size(blob: crtc_state->gamma_lut); |
1533 | if (len != crtc->gamma_size) { |
1534 | DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n" , |
1535 | len, crtc->gamma_size); |
1536 | return -EINVAL; |
1537 | } |
1538 | } |
1539 | |
1540 | drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { |
1541 | plane_state = |
1542 | drm_atomic_get_plane_state(state: crtc_state->state, plane); |
1543 | if (IS_ERR(ptr: plane_state)) { |
1544 | DRM_DEBUG_KMS("Cannot get plane state for plane %s\n" , |
1545 | plane->name); |
1546 | return PTR_ERR(ptr: plane_state); |
1547 | } |
1548 | |
1549 | if (drm_is_afbc(plane_state->fb->modifier)) |
1550 | ++afbc_planes; |
1551 | } |
1552 | |
1553 | if (afbc_planes > 1) { |
1554 | DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n" , afbc_planes); |
1555 | return -EINVAL; |
1556 | } |
1557 | |
1558 | s = to_rockchip_crtc_state(crtc_state); |
1559 | s->enable_afbc = afbc_planes > 0; |
1560 | |
1561 | return 0; |
1562 | } |
1563 | |
1564 | static void vop_crtc_atomic_flush(struct drm_crtc *crtc, |
1565 | struct drm_atomic_state *state) |
1566 | { |
1567 | struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, |
1568 | crtc); |
1569 | struct drm_atomic_state *old_state = old_crtc_state->state; |
1570 | struct drm_plane_state *old_plane_state, *new_plane_state; |
1571 | struct vop *vop = to_vop(crtc); |
1572 | struct drm_plane *plane; |
1573 | struct rockchip_crtc_state *s; |
1574 | int i; |
1575 | |
1576 | if (WARN_ON(!vop->is_enabled)) |
1577 | return; |
1578 | |
1579 | spin_lock(lock: &vop->reg_lock); |
1580 | |
1581 | /* Enable AFBC if there is some AFBC window, disable otherwise. */ |
1582 | s = to_rockchip_crtc_state(crtc->state); |
1583 | VOP_AFBC_SET(vop, enable, s->enable_afbc); |
1584 | vop_cfg_done(vop); |
1585 | |
1586 | spin_unlock(lock: &vop->reg_lock); |
1587 | |
1588 | /* |
1589 | * There is a (rather unlikely) possiblity that a vblank interrupt |
1590 | * fired before we set the cfg_done bit. To avoid spuriously |
1591 | * signalling flip completion we need to wait for it to finish. |
1592 | */ |
1593 | vop_wait_for_irq_handler(vop); |
1594 | |
1595 | spin_lock_irq(lock: &crtc->dev->event_lock); |
1596 | if (crtc->state->event) { |
1597 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); |
1598 | WARN_ON(vop->event); |
1599 | |
1600 | vop->event = crtc->state->event; |
1601 | crtc->state->event = NULL; |
1602 | } |
1603 | spin_unlock_irq(lock: &crtc->dev->event_lock); |
1604 | |
1605 | for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, |
1606 | new_plane_state, i) { |
1607 | if (!old_plane_state->fb) |
1608 | continue; |
1609 | |
1610 | if (old_plane_state->fb == new_plane_state->fb) |
1611 | continue; |
1612 | |
1613 | drm_framebuffer_get(fb: old_plane_state->fb); |
1614 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); |
1615 | drm_flip_work_queue(work: &vop->fb_unref_work, val: old_plane_state->fb); |
1616 | set_bit(nr: VOP_PENDING_FB_UNREF, addr: &vop->pending); |
1617 | } |
1618 | } |
1619 | |
1620 | static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { |
1621 | .mode_valid = vop_crtc_mode_valid, |
1622 | .mode_fixup = vop_crtc_mode_fixup, |
1623 | .atomic_check = vop_crtc_atomic_check, |
1624 | .atomic_begin = vop_crtc_atomic_begin, |
1625 | .atomic_flush = vop_crtc_atomic_flush, |
1626 | .atomic_enable = vop_crtc_atomic_enable, |
1627 | .atomic_disable = vop_crtc_atomic_disable, |
1628 | }; |
1629 | |
1630 | static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) |
1631 | { |
1632 | struct rockchip_crtc_state *rockchip_state; |
1633 | |
1634 | if (WARN_ON(!crtc->state)) |
1635 | return NULL; |
1636 | |
1637 | rockchip_state = kmemdup(to_rockchip_crtc_state(crtc->state), |
1638 | size: sizeof(*rockchip_state), GFP_KERNEL); |
1639 | if (!rockchip_state) |
1640 | return NULL; |
1641 | |
1642 | __drm_atomic_helper_crtc_duplicate_state(crtc, state: &rockchip_state->base); |
1643 | return &rockchip_state->base; |
1644 | } |
1645 | |
1646 | static void vop_crtc_destroy_state(struct drm_crtc *crtc, |
1647 | struct drm_crtc_state *state) |
1648 | { |
1649 | struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); |
1650 | |
1651 | __drm_atomic_helper_crtc_destroy_state(state: &s->base); |
1652 | kfree(objp: s); |
1653 | } |
1654 | |
1655 | static void vop_crtc_reset(struct drm_crtc *crtc) |
1656 | { |
1657 | struct rockchip_crtc_state *crtc_state = |
1658 | kzalloc(size: sizeof(*crtc_state), GFP_KERNEL); |
1659 | |
1660 | if (crtc->state) |
1661 | vop_crtc_destroy_state(crtc, state: crtc->state); |
1662 | |
1663 | if (crtc_state) |
1664 | __drm_atomic_helper_crtc_reset(crtc, state: &crtc_state->base); |
1665 | else |
1666 | __drm_atomic_helper_crtc_reset(crtc, NULL); |
1667 | } |
1668 | |
1669 | #ifdef CONFIG_DRM_ANALOGIX_DP |
1670 | static struct drm_connector *vop_get_edp_connector(struct vop *vop) |
1671 | { |
1672 | struct drm_connector *connector; |
1673 | struct drm_connector_list_iter conn_iter; |
1674 | |
1675 | drm_connector_list_iter_begin(dev: vop->drm_dev, iter: &conn_iter); |
1676 | drm_for_each_connector_iter(connector, &conn_iter) { |
1677 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
1678 | drm_connector_list_iter_end(iter: &conn_iter); |
1679 | return connector; |
1680 | } |
1681 | } |
1682 | drm_connector_list_iter_end(iter: &conn_iter); |
1683 | |
1684 | return NULL; |
1685 | } |
1686 | |
1687 | static int vop_crtc_set_crc_source(struct drm_crtc *crtc, |
1688 | const char *source_name) |
1689 | { |
1690 | struct vop *vop = to_vop(crtc); |
1691 | struct drm_connector *connector; |
1692 | int ret; |
1693 | |
1694 | connector = vop_get_edp_connector(vop); |
1695 | if (!connector) |
1696 | return -EINVAL; |
1697 | |
1698 | if (source_name && strcmp(source_name, "auto" ) == 0) |
1699 | ret = analogix_dp_start_crc(connector); |
1700 | else if (!source_name) |
1701 | ret = analogix_dp_stop_crc(connector); |
1702 | else |
1703 | ret = -EINVAL; |
1704 | |
1705 | return ret; |
1706 | } |
1707 | |
1708 | static int |
1709 | vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, |
1710 | size_t *values_cnt) |
1711 | { |
1712 | if (source_name && strcmp(source_name, "auto" ) != 0) |
1713 | return -EINVAL; |
1714 | |
1715 | *values_cnt = 3; |
1716 | return 0; |
1717 | } |
1718 | |
1719 | #else |
1720 | static int vop_crtc_set_crc_source(struct drm_crtc *crtc, |
1721 | const char *source_name) |
1722 | { |
1723 | return -ENODEV; |
1724 | } |
1725 | |
1726 | static int |
1727 | vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, |
1728 | size_t *values_cnt) |
1729 | { |
1730 | return -ENODEV; |
1731 | } |
1732 | #endif |
1733 | |
1734 | static const struct drm_crtc_funcs vop_crtc_funcs = { |
1735 | .set_config = drm_atomic_helper_set_config, |
1736 | .page_flip = drm_atomic_helper_page_flip, |
1737 | .destroy = drm_crtc_cleanup, |
1738 | .reset = vop_crtc_reset, |
1739 | .atomic_duplicate_state = vop_crtc_duplicate_state, |
1740 | .atomic_destroy_state = vop_crtc_destroy_state, |
1741 | .enable_vblank = vop_crtc_enable_vblank, |
1742 | .disable_vblank = vop_crtc_disable_vblank, |
1743 | .set_crc_source = vop_crtc_set_crc_source, |
1744 | .verify_crc_source = vop_crtc_verify_crc_source, |
1745 | }; |
1746 | |
1747 | static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) |
1748 | { |
1749 | struct vop *vop = container_of(work, struct vop, fb_unref_work); |
1750 | struct drm_framebuffer *fb = val; |
1751 | |
1752 | drm_crtc_vblank_put(crtc: &vop->crtc); |
1753 | drm_framebuffer_put(fb); |
1754 | } |
1755 | |
1756 | static void vop_handle_vblank(struct vop *vop) |
1757 | { |
1758 | struct drm_device *drm = vop->drm_dev; |
1759 | struct drm_crtc *crtc = &vop->crtc; |
1760 | |
1761 | spin_lock(lock: &drm->event_lock); |
1762 | if (vop->event) { |
1763 | drm_crtc_send_vblank_event(crtc, e: vop->event); |
1764 | drm_crtc_vblank_put(crtc); |
1765 | vop->event = NULL; |
1766 | } |
1767 | spin_unlock(lock: &drm->event_lock); |
1768 | |
1769 | if (test_and_clear_bit(nr: VOP_PENDING_FB_UNREF, addr: &vop->pending)) |
1770 | drm_flip_work_commit(work: &vop->fb_unref_work, wq: system_unbound_wq); |
1771 | } |
1772 | |
1773 | static irqreturn_t vop_isr(int irq, void *data) |
1774 | { |
1775 | struct vop *vop = data; |
1776 | struct drm_crtc *crtc = &vop->crtc; |
1777 | uint32_t active_irqs; |
1778 | int ret = IRQ_NONE; |
1779 | |
1780 | /* |
1781 | * The irq is shared with the iommu. If the runtime-pm state of the |
1782 | * vop-device is disabled the irq has to be targeted at the iommu. |
1783 | */ |
1784 | if (!pm_runtime_get_if_in_use(dev: vop->dev)) |
1785 | return IRQ_NONE; |
1786 | |
1787 | if (vop_core_clks_enable(vop)) { |
1788 | DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n" ); |
1789 | goto out; |
1790 | } |
1791 | |
1792 | /* |
1793 | * interrupt register has interrupt status, enable and clear bits, we |
1794 | * must hold irq_lock to avoid a race with enable/disable_vblank(). |
1795 | */ |
1796 | spin_lock(lock: &vop->irq_lock); |
1797 | |
1798 | active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); |
1799 | /* Clear all active interrupt sources */ |
1800 | if (active_irqs) |
1801 | VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); |
1802 | |
1803 | spin_unlock(lock: &vop->irq_lock); |
1804 | |
1805 | /* This is expected for vop iommu irqs, since the irq is shared */ |
1806 | if (!active_irqs) |
1807 | goto out_disable; |
1808 | |
1809 | if (active_irqs & DSP_HOLD_VALID_INTR) { |
1810 | complete(&vop->dsp_hold_completion); |
1811 | active_irqs &= ~DSP_HOLD_VALID_INTR; |
1812 | ret = IRQ_HANDLED; |
1813 | } |
1814 | |
1815 | if (active_irqs & LINE_FLAG_INTR) { |
1816 | complete(&vop->line_flag_completion); |
1817 | active_irqs &= ~LINE_FLAG_INTR; |
1818 | ret = IRQ_HANDLED; |
1819 | } |
1820 | |
1821 | if (active_irqs & FS_INTR) { |
1822 | drm_crtc_handle_vblank(crtc); |
1823 | vop_handle_vblank(vop); |
1824 | active_irqs &= ~FS_INTR; |
1825 | ret = IRQ_HANDLED; |
1826 | } |
1827 | |
1828 | /* Unhandled irqs are spurious. */ |
1829 | if (active_irqs) |
1830 | DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n" , |
1831 | active_irqs); |
1832 | |
1833 | out_disable: |
1834 | vop_core_clks_disable(vop); |
1835 | out: |
1836 | pm_runtime_put(dev: vop->dev); |
1837 | return ret; |
1838 | } |
1839 | |
1840 | static void vop_plane_add_properties(struct drm_plane *plane, |
1841 | const struct vop_win_data *win_data) |
1842 | { |
1843 | unsigned int flags = 0; |
1844 | |
1845 | flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; |
1846 | flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; |
1847 | if (flags) |
1848 | drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, |
1849 | DRM_MODE_ROTATE_0 | flags); |
1850 | } |
1851 | |
1852 | static int vop_create_crtc(struct vop *vop) |
1853 | { |
1854 | const struct vop_data *vop_data = vop->data; |
1855 | struct device *dev = vop->dev; |
1856 | struct drm_device *drm_dev = vop->drm_dev; |
1857 | struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; |
1858 | struct drm_crtc *crtc = &vop->crtc; |
1859 | struct device_node *port; |
1860 | int ret; |
1861 | int i; |
1862 | |
1863 | /* |
1864 | * Create drm_plane for primary and cursor planes first, since we need |
1865 | * to pass them to drm_crtc_init_with_planes, which sets the |
1866 | * "possible_crtcs" to the newly initialized crtc. |
1867 | */ |
1868 | for (i = 0; i < vop_data->win_size; i++) { |
1869 | struct vop_win *vop_win = &vop->win[i]; |
1870 | const struct vop_win_data *win_data = vop_win->data; |
1871 | |
1872 | if (win_data->type != DRM_PLANE_TYPE_PRIMARY && |
1873 | win_data->type != DRM_PLANE_TYPE_CURSOR) |
1874 | continue; |
1875 | |
1876 | ret = drm_universal_plane_init(dev: vop->drm_dev, plane: &vop_win->base, |
1877 | possible_crtcs: 0, funcs: &vop_plane_funcs, |
1878 | formats: win_data->phy->data_formats, |
1879 | format_count: win_data->phy->nformats, |
1880 | format_modifiers: win_data->phy->format_modifiers, |
1881 | type: win_data->type, NULL); |
1882 | if (ret) { |
1883 | DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n" , |
1884 | ret); |
1885 | goto err_cleanup_planes; |
1886 | } |
1887 | |
1888 | plane = &vop_win->base; |
1889 | drm_plane_helper_add(plane, funcs: &plane_helper_funcs); |
1890 | vop_plane_add_properties(plane, win_data); |
1891 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) |
1892 | primary = plane; |
1893 | else if (plane->type == DRM_PLANE_TYPE_CURSOR) |
1894 | cursor = plane; |
1895 | } |
1896 | |
1897 | ret = drm_crtc_init_with_planes(dev: drm_dev, crtc, primary, cursor, |
1898 | funcs: &vop_crtc_funcs, NULL); |
1899 | if (ret) |
1900 | goto err_cleanup_planes; |
1901 | |
1902 | drm_crtc_helper_add(crtc, funcs: &vop_crtc_helper_funcs); |
1903 | if (vop->lut_regs) { |
1904 | drm_mode_crtc_set_gamma_size(crtc, gamma_size: vop_data->lut_size); |
1905 | drm_crtc_enable_color_mgmt(crtc, degamma_lut_size: 0, has_ctm: false, gamma_lut_size: vop_data->lut_size); |
1906 | } |
1907 | |
1908 | /* |
1909 | * Create drm_planes for overlay windows with possible_crtcs restricted |
1910 | * to the newly created crtc. |
1911 | */ |
1912 | for (i = 0; i < vop_data->win_size; i++) { |
1913 | struct vop_win *vop_win = &vop->win[i]; |
1914 | const struct vop_win_data *win_data = vop_win->data; |
1915 | unsigned long possible_crtcs = drm_crtc_mask(crtc); |
1916 | |
1917 | if (win_data->type != DRM_PLANE_TYPE_OVERLAY) |
1918 | continue; |
1919 | |
1920 | ret = drm_universal_plane_init(dev: vop->drm_dev, plane: &vop_win->base, |
1921 | possible_crtcs, |
1922 | funcs: &vop_plane_funcs, |
1923 | formats: win_data->phy->data_formats, |
1924 | format_count: win_data->phy->nformats, |
1925 | format_modifiers: win_data->phy->format_modifiers, |
1926 | type: win_data->type, NULL); |
1927 | if (ret) { |
1928 | DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n" , |
1929 | ret); |
1930 | goto err_cleanup_crtc; |
1931 | } |
1932 | drm_plane_helper_add(plane: &vop_win->base, funcs: &plane_helper_funcs); |
1933 | vop_plane_add_properties(plane: &vop_win->base, win_data); |
1934 | } |
1935 | |
1936 | port = of_get_child_by_name(node: dev->of_node, name: "port" ); |
1937 | if (!port) { |
1938 | DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n" , |
1939 | dev->of_node); |
1940 | ret = -ENOENT; |
1941 | goto err_cleanup_crtc; |
1942 | } |
1943 | |
1944 | drm_flip_work_init(work: &vop->fb_unref_work, name: "fb_unref" , |
1945 | func: vop_fb_unref_worker); |
1946 | |
1947 | init_completion(x: &vop->dsp_hold_completion); |
1948 | init_completion(x: &vop->line_flag_completion); |
1949 | crtc->port = port; |
1950 | |
1951 | ret = drm_self_refresh_helper_init(crtc); |
1952 | if (ret) |
1953 | DRM_DEV_DEBUG_KMS(vop->dev, |
1954 | "Failed to init %s with SR helpers %d, ignoring\n" , |
1955 | crtc->name, ret); |
1956 | |
1957 | return 0; |
1958 | |
1959 | err_cleanup_crtc: |
1960 | drm_crtc_cleanup(crtc); |
1961 | err_cleanup_planes: |
1962 | list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, |
1963 | head) |
1964 | drm_plane_cleanup(plane); |
1965 | return ret; |
1966 | } |
1967 | |
1968 | static void vop_destroy_crtc(struct vop *vop) |
1969 | { |
1970 | struct drm_crtc *crtc = &vop->crtc; |
1971 | struct drm_device *drm_dev = vop->drm_dev; |
1972 | struct drm_plane *plane, *tmp; |
1973 | |
1974 | drm_self_refresh_helper_cleanup(crtc); |
1975 | |
1976 | of_node_put(node: crtc->port); |
1977 | |
1978 | /* |
1979 | * We need to cleanup the planes now. Why? |
1980 | * |
1981 | * The planes are "&vop->win[i].base". That means the memory is |
1982 | * all part of the big "struct vop" chunk of memory. That memory |
1983 | * was devm allocated and associated with this component. We need to |
1984 | * free it ourselves before vop_unbind() finishes. |
1985 | */ |
1986 | list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, |
1987 | head) |
1988 | drm_plane_cleanup(plane); |
1989 | |
1990 | /* |
1991 | * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() |
1992 | * references the CRTC. |
1993 | */ |
1994 | drm_crtc_cleanup(crtc); |
1995 | drm_flip_work_cleanup(work: &vop->fb_unref_work); |
1996 | } |
1997 | |
1998 | static int vop_initial(struct vop *vop) |
1999 | { |
2000 | struct reset_control *ahb_rst; |
2001 | int i, ret; |
2002 | |
2003 | vop->hclk = devm_clk_get(dev: vop->dev, id: "hclk_vop" ); |
2004 | if (IS_ERR(ptr: vop->hclk)) { |
2005 | DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n" ); |
2006 | return PTR_ERR(ptr: vop->hclk); |
2007 | } |
2008 | vop->aclk = devm_clk_get(dev: vop->dev, id: "aclk_vop" ); |
2009 | if (IS_ERR(ptr: vop->aclk)) { |
2010 | DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n" ); |
2011 | return PTR_ERR(ptr: vop->aclk); |
2012 | } |
2013 | vop->dclk = devm_clk_get(dev: vop->dev, id: "dclk_vop" ); |
2014 | if (IS_ERR(ptr: vop->dclk)) { |
2015 | DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n" ); |
2016 | return PTR_ERR(ptr: vop->dclk); |
2017 | } |
2018 | |
2019 | ret = pm_runtime_resume_and_get(dev: vop->dev); |
2020 | if (ret < 0) { |
2021 | DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n" , ret); |
2022 | return ret; |
2023 | } |
2024 | |
2025 | ret = clk_prepare(clk: vop->dclk); |
2026 | if (ret < 0) { |
2027 | DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n" ); |
2028 | goto err_put_pm_runtime; |
2029 | } |
2030 | |
2031 | /* Enable both the hclk and aclk to setup the vop */ |
2032 | ret = clk_prepare_enable(clk: vop->hclk); |
2033 | if (ret < 0) { |
2034 | DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n" ); |
2035 | goto err_unprepare_dclk; |
2036 | } |
2037 | |
2038 | ret = clk_prepare_enable(clk: vop->aclk); |
2039 | if (ret < 0) { |
2040 | DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n" ); |
2041 | goto err_disable_hclk; |
2042 | } |
2043 | |
2044 | /* |
2045 | * do hclk_reset, reset all vop registers. |
2046 | */ |
2047 | ahb_rst = devm_reset_control_get(dev: vop->dev, id: "ahb" ); |
2048 | if (IS_ERR(ptr: ahb_rst)) { |
2049 | DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n" ); |
2050 | ret = PTR_ERR(ptr: ahb_rst); |
2051 | goto err_disable_aclk; |
2052 | } |
2053 | reset_control_assert(rstc: ahb_rst); |
2054 | usleep_range(min: 10, max: 20); |
2055 | reset_control_deassert(rstc: ahb_rst); |
2056 | |
2057 | VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); |
2058 | VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); |
2059 | |
2060 | for (i = 0; i < vop->len; i += sizeof(u32)) |
2061 | vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); |
2062 | |
2063 | VOP_REG_SET(vop, misc, global_regdone_en, 1); |
2064 | VOP_REG_SET(vop, common, dsp_blank, 0); |
2065 | |
2066 | for (i = 0; i < vop->data->win_size; i++) { |
2067 | struct vop_win *vop_win = &vop->win[i]; |
2068 | const struct vop_win_data *win = vop_win->data; |
2069 | int channel = i * 2 + 1; |
2070 | |
2071 | VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); |
2072 | vop_win_disable(vop, vop_win); |
2073 | VOP_WIN_SET(vop, win, gate, 1); |
2074 | } |
2075 | |
2076 | vop_cfg_done(vop); |
2077 | |
2078 | /* |
2079 | * do dclk_reset, let all config take affect. |
2080 | */ |
2081 | vop->dclk_rst = devm_reset_control_get(dev: vop->dev, id: "dclk" ); |
2082 | if (IS_ERR(ptr: vop->dclk_rst)) { |
2083 | DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n" ); |
2084 | ret = PTR_ERR(ptr: vop->dclk_rst); |
2085 | goto err_disable_aclk; |
2086 | } |
2087 | reset_control_assert(rstc: vop->dclk_rst); |
2088 | usleep_range(min: 10, max: 20); |
2089 | reset_control_deassert(rstc: vop->dclk_rst); |
2090 | |
2091 | clk_disable(clk: vop->hclk); |
2092 | clk_disable(clk: vop->aclk); |
2093 | |
2094 | vop->is_enabled = false; |
2095 | |
2096 | pm_runtime_put_sync(dev: vop->dev); |
2097 | |
2098 | return 0; |
2099 | |
2100 | err_disable_aclk: |
2101 | clk_disable_unprepare(clk: vop->aclk); |
2102 | err_disable_hclk: |
2103 | clk_disable_unprepare(clk: vop->hclk); |
2104 | err_unprepare_dclk: |
2105 | clk_unprepare(clk: vop->dclk); |
2106 | err_put_pm_runtime: |
2107 | pm_runtime_put_sync(dev: vop->dev); |
2108 | return ret; |
2109 | } |
2110 | |
2111 | /* |
2112 | * Initialize the vop->win array elements. |
2113 | */ |
2114 | static void vop_win_init(struct vop *vop) |
2115 | { |
2116 | const struct vop_data *vop_data = vop->data; |
2117 | unsigned int i; |
2118 | |
2119 | for (i = 0; i < vop_data->win_size; i++) { |
2120 | struct vop_win *vop_win = &vop->win[i]; |
2121 | const struct vop_win_data *win_data = &vop_data->win[i]; |
2122 | |
2123 | vop_win->data = win_data; |
2124 | vop_win->vop = vop; |
2125 | |
2126 | if (vop_data->win_yuv2yuv) |
2127 | vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; |
2128 | } |
2129 | } |
2130 | |
2131 | /** |
2132 | * rockchip_drm_wait_vact_end |
2133 | * @crtc: CRTC to enable line flag |
2134 | * @mstimeout: millisecond for timeout |
2135 | * |
2136 | * Wait for vact_end line flag irq or timeout. |
2137 | * |
2138 | * Returns: |
2139 | * Zero on success, negative errno on failure. |
2140 | */ |
2141 | int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) |
2142 | { |
2143 | struct vop *vop = to_vop(crtc); |
2144 | unsigned long jiffies_left; |
2145 | int ret = 0; |
2146 | |
2147 | if (!crtc || !vop->is_enabled) |
2148 | return -ENODEV; |
2149 | |
2150 | mutex_lock(&vop->vop_lock); |
2151 | if (mstimeout <= 0) { |
2152 | ret = -EINVAL; |
2153 | goto out; |
2154 | } |
2155 | |
2156 | if (vop_line_flag_irq_is_enabled(vop)) { |
2157 | ret = -EBUSY; |
2158 | goto out; |
2159 | } |
2160 | |
2161 | reinit_completion(x: &vop->line_flag_completion); |
2162 | vop_line_flag_irq_enable(vop); |
2163 | |
2164 | jiffies_left = wait_for_completion_timeout(x: &vop->line_flag_completion, |
2165 | timeout: msecs_to_jiffies(m: mstimeout)); |
2166 | vop_line_flag_irq_disable(vop); |
2167 | |
2168 | if (jiffies_left == 0) { |
2169 | DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n" ); |
2170 | ret = -ETIMEDOUT; |
2171 | goto out; |
2172 | } |
2173 | |
2174 | out: |
2175 | mutex_unlock(lock: &vop->vop_lock); |
2176 | return ret; |
2177 | } |
2178 | EXPORT_SYMBOL(rockchip_drm_wait_vact_end); |
2179 | |
2180 | static int vop_bind(struct device *dev, struct device *master, void *data) |
2181 | { |
2182 | struct platform_device *pdev = to_platform_device(dev); |
2183 | const struct vop_data *vop_data; |
2184 | struct drm_device *drm_dev = data; |
2185 | struct vop *vop; |
2186 | struct resource *res; |
2187 | int ret, irq; |
2188 | |
2189 | vop_data = of_device_get_match_data(dev); |
2190 | if (!vop_data) |
2191 | return -ENODEV; |
2192 | |
2193 | /* Allocate vop struct and its vop_win array */ |
2194 | vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), |
2195 | GFP_KERNEL); |
2196 | if (!vop) |
2197 | return -ENOMEM; |
2198 | |
2199 | vop->dev = dev; |
2200 | vop->data = vop_data; |
2201 | vop->drm_dev = drm_dev; |
2202 | dev_set_drvdata(dev, data: vop); |
2203 | |
2204 | vop_win_init(vop); |
2205 | |
2206 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2207 | vop->regs = devm_ioremap_resource(dev, res); |
2208 | if (IS_ERR(ptr: vop->regs)) |
2209 | return PTR_ERR(ptr: vop->regs); |
2210 | vop->len = resource_size(res); |
2211 | |
2212 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
2213 | if (res) { |
2214 | if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) { |
2215 | DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n" , vop_data->lut_size); |
2216 | return -EINVAL; |
2217 | } |
2218 | vop->lut_regs = devm_ioremap_resource(dev, res); |
2219 | if (IS_ERR(ptr: vop->lut_regs)) |
2220 | return PTR_ERR(ptr: vop->lut_regs); |
2221 | } |
2222 | |
2223 | vop->regsbak = devm_kzalloc(dev, size: vop->len, GFP_KERNEL); |
2224 | if (!vop->regsbak) |
2225 | return -ENOMEM; |
2226 | |
2227 | irq = platform_get_irq(pdev, 0); |
2228 | if (irq < 0) { |
2229 | DRM_DEV_ERROR(dev, "cannot find irq for vop\n" ); |
2230 | return irq; |
2231 | } |
2232 | vop->irq = (unsigned int)irq; |
2233 | |
2234 | spin_lock_init(&vop->reg_lock); |
2235 | spin_lock_init(&vop->irq_lock); |
2236 | mutex_init(&vop->vop_lock); |
2237 | |
2238 | ret = vop_create_crtc(vop); |
2239 | if (ret) |
2240 | return ret; |
2241 | |
2242 | pm_runtime_enable(dev: &pdev->dev); |
2243 | |
2244 | ret = vop_initial(vop); |
2245 | if (ret < 0) { |
2246 | DRM_DEV_ERROR(&pdev->dev, |
2247 | "cannot initial vop dev - err %d\n" , ret); |
2248 | goto err_disable_pm_runtime; |
2249 | } |
2250 | |
2251 | ret = devm_request_irq(dev, irq: vop->irq, handler: vop_isr, |
2252 | IRQF_SHARED, devname: dev_name(dev), dev_id: vop); |
2253 | if (ret) |
2254 | goto err_disable_pm_runtime; |
2255 | |
2256 | if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { |
2257 | vop->rgb = rockchip_rgb_init(dev, crtc: &vop->crtc, drm_dev: vop->drm_dev, video_port: 0); |
2258 | if (IS_ERR(ptr: vop->rgb)) { |
2259 | ret = PTR_ERR(ptr: vop->rgb); |
2260 | goto err_disable_pm_runtime; |
2261 | } |
2262 | } |
2263 | |
2264 | rockchip_drm_dma_init_device(drm_dev, dev); |
2265 | |
2266 | return 0; |
2267 | |
2268 | err_disable_pm_runtime: |
2269 | pm_runtime_disable(dev: &pdev->dev); |
2270 | vop_destroy_crtc(vop); |
2271 | return ret; |
2272 | } |
2273 | |
2274 | static void vop_unbind(struct device *dev, struct device *master, void *data) |
2275 | { |
2276 | struct vop *vop = dev_get_drvdata(dev); |
2277 | |
2278 | if (vop->rgb) |
2279 | rockchip_rgb_fini(rgb: vop->rgb); |
2280 | |
2281 | pm_runtime_disable(dev); |
2282 | vop_destroy_crtc(vop); |
2283 | |
2284 | clk_unprepare(clk: vop->aclk); |
2285 | clk_unprepare(clk: vop->hclk); |
2286 | clk_unprepare(clk: vop->dclk); |
2287 | } |
2288 | |
2289 | const struct component_ops vop_component_ops = { |
2290 | .bind = vop_bind, |
2291 | .unbind = vop_unbind, |
2292 | }; |
2293 | EXPORT_SYMBOL_GPL(vop_component_ops); |
2294 | |