1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (C) 2012 Texas Instruments |
4 | * Author: Rob Clark <robdclark@gmail.com> |
5 | */ |
6 | |
7 | #ifndef __TILCDC_DRV_H__ |
8 | #define __TILCDC_DRV_H__ |
9 | |
10 | #include <linux/cpufreq.h> |
11 | #include <linux/irqreturn.h> |
12 | |
13 | #include <drm/drm_print.h> |
14 | |
15 | struct clk; |
16 | struct workqueue_struct; |
17 | |
18 | struct drm_connector; |
19 | struct drm_connector_helper_funcs; |
20 | struct drm_crtc; |
21 | struct drm_device; |
22 | struct drm_display_mode; |
23 | struct drm_encoder; |
24 | struct drm_framebuffer; |
25 | struct drm_minor; |
26 | struct drm_pending_vblank_event; |
27 | struct drm_plane; |
28 | |
29 | /* Defaulting to pixel clock defined on AM335x */ |
30 | #define TILCDC_DEFAULT_MAX_PIXELCLOCK 126000 |
31 | /* Maximum display width for LCDC V1 */ |
32 | #define TILCDC_DEFAULT_MAX_WIDTH_V1 1024 |
33 | /* ... and for LCDC V2 found on AM335x: */ |
34 | #define TILCDC_DEFAULT_MAX_WIDTH_V2 2048 |
35 | /* |
36 | * This may need some tweaking, but want to allow at least 1280x1024@60 |
37 | * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to |
38 | * be supportable |
39 | */ |
40 | #define TILCDC_DEFAULT_MAX_BANDWIDTH (1280*1024*60) |
41 | |
42 | |
43 | struct tilcdc_drm_private { |
44 | void __iomem *mmio; |
45 | |
46 | struct clk *clk; /* functional clock */ |
47 | int rev; /* IP revision */ |
48 | |
49 | unsigned int irq; |
50 | |
51 | /* don't attempt resolutions w/ higher W * H * Hz: */ |
52 | uint32_t max_bandwidth; |
53 | /* |
54 | * Pixel Clock will be restricted to some value as |
55 | * defined in the device datasheet measured in KHz |
56 | */ |
57 | uint32_t max_pixelclock; |
58 | /* |
59 | * Max allowable width is limited on a per device basis |
60 | * measured in pixels |
61 | */ |
62 | uint32_t max_width; |
63 | |
64 | /* Supported pixel formats */ |
65 | const uint32_t *pixelformats; |
66 | uint32_t num_pixelformats; |
67 | |
68 | #ifdef CONFIG_CPU_FREQ |
69 | struct notifier_block freq_transition; |
70 | #endif |
71 | |
72 | struct workqueue_struct *wq; |
73 | |
74 | struct drm_crtc *crtc; |
75 | |
76 | unsigned int num_encoders; |
77 | struct drm_encoder *encoders[8]; |
78 | |
79 | unsigned int num_connectors; |
80 | struct drm_connector *connectors[8]; |
81 | |
82 | struct drm_encoder *external_encoder; |
83 | struct drm_connector *external_connector; |
84 | |
85 | bool is_registered; |
86 | bool is_componentized; |
87 | bool irq_enabled; |
88 | }; |
89 | |
90 | /* Sub-module for display. Since we don't know at compile time what panels |
91 | * or display adapter(s) might be present (for ex, off chip dvi/tfp410, |
92 | * hdmi encoder, various lcd panels), the connector/encoder(s) are split into |
93 | * separate drivers. If they are probed and found to be present, they |
94 | * register themselves with tilcdc_register_module(). |
95 | */ |
96 | struct tilcdc_module; |
97 | |
98 | struct tilcdc_module_ops { |
99 | /* create appropriate encoders/connectors: */ |
100 | int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev); |
101 | #ifdef CONFIG_DEBUG_FS |
102 | /* create debugfs nodes (can be NULL): */ |
103 | int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor); |
104 | #endif |
105 | }; |
106 | |
107 | struct tilcdc_module { |
108 | const char *name; |
109 | struct list_head list; |
110 | const struct tilcdc_module_ops *funcs; |
111 | }; |
112 | |
113 | void tilcdc_module_init(struct tilcdc_module *mod, const char *name, |
114 | const struct tilcdc_module_ops *funcs); |
115 | void tilcdc_module_cleanup(struct tilcdc_module *mod); |
116 | |
117 | /* Panel config that needs to be set in the crtc, but is not coming from |
118 | * the mode timings. The display module is expected to call |
119 | * tilcdc_crtc_set_panel_info() to set this during modeset. |
120 | */ |
121 | struct tilcdc_panel_info { |
122 | |
123 | /* AC Bias Pin Frequency */ |
124 | uint32_t ac_bias; |
125 | |
126 | /* AC Bias Pin Transitions per Interrupt */ |
127 | uint32_t ac_bias_intrpt; |
128 | |
129 | /* DMA burst size */ |
130 | uint32_t dma_burst_sz; |
131 | |
132 | /* Bits per pixel */ |
133 | uint32_t bpp; |
134 | |
135 | /* FIFO DMA Request Delay */ |
136 | uint32_t fdd; |
137 | |
138 | /* TFT Alternative Signal Mapping (Only for active) */ |
139 | bool tft_alt_mode; |
140 | |
141 | /* Invert pixel clock */ |
142 | bool invert_pxl_clk; |
143 | |
144 | /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ |
145 | uint32_t sync_edge; |
146 | |
147 | /* Horizontal and Vertical Sync: Control: 0=ignore */ |
148 | uint32_t sync_ctrl; |
149 | |
150 | /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ |
151 | uint32_t raster_order; |
152 | |
153 | /* DMA FIFO threshold */ |
154 | uint32_t fifo_th; |
155 | }; |
156 | |
157 | #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) |
158 | |
159 | int tilcdc_crtc_create(struct drm_device *dev); |
160 | irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc); |
161 | void tilcdc_crtc_update_clk(struct drm_crtc *crtc); |
162 | void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, |
163 | const struct tilcdc_panel_info *info); |
164 | void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, |
165 | bool simulate_vesa_sync); |
166 | void tilcdc_crtc_shutdown(struct drm_crtc *crtc); |
167 | int tilcdc_crtc_update_fb(struct drm_crtc *crtc, |
168 | struct drm_framebuffer *fb, |
169 | struct drm_pending_vblank_event *event); |
170 | |
171 | int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane); |
172 | |
173 | #endif /* __TILCDC_DRV_H__ */ |
174 | |