| 1 | /* |
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| 2 | * Copyright © 2014 Broadcom |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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| 21 | * IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef VC4_PACKET_H |
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| 25 | #define VC4_PACKET_H |
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| 26 | |
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| 27 | #include "vc4_regs.h" /* for VC4_MASK, VC4_GET_FIELD, VC4_SET_FIELD */ |
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| 28 | |
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| 29 | enum vc4_packet { |
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| 30 | VC4_PACKET_HALT = 0, |
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| 31 | VC4_PACKET_NOP = 1, |
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| 32 | |
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| 33 | VC4_PACKET_FLUSH = 4, |
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| 34 | VC4_PACKET_FLUSH_ALL = 5, |
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| 35 | VC4_PACKET_START_TILE_BINNING = 6, |
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| 36 | VC4_PACKET_INCREMENT_SEMAPHORE = 7, |
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| 37 | VC4_PACKET_WAIT_ON_SEMAPHORE = 8, |
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| 38 | |
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| 39 | VC4_PACKET_BRANCH = 16, |
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| 40 | VC4_PACKET_BRANCH_TO_SUB_LIST = 17, |
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| 41 | |
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| 42 | VC4_PACKET_STORE_MS_TILE_BUFFER = 24, |
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| 43 | VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25, |
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| 44 | VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26, |
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| 45 | VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27, |
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| 46 | VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28, |
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| 47 | VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29, |
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| 48 | |
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| 49 | VC4_PACKET_GL_INDEXED_PRIMITIVE = 32, |
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| 50 | VC4_PACKET_GL_ARRAY_PRIMITIVE = 33, |
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| 51 | |
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| 52 | VC4_PACKET_COMPRESSED_PRIMITIVE = 48, |
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| 53 | VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49, |
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| 54 | |
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| 55 | VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56, |
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| 56 | |
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| 57 | VC4_PACKET_GL_SHADER_STATE = 64, |
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| 58 | VC4_PACKET_NV_SHADER_STATE = 65, |
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| 59 | VC4_PACKET_VG_SHADER_STATE = 66, |
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| 60 | |
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| 61 | VC4_PACKET_CONFIGURATION_BITS = 96, |
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| 62 | VC4_PACKET_FLAT_SHADE_FLAGS = 97, |
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| 63 | VC4_PACKET_POINT_SIZE = 98, |
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| 64 | VC4_PACKET_LINE_WIDTH = 99, |
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| 65 | VC4_PACKET_RHT_X_BOUNDARY = 100, |
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| 66 | VC4_PACKET_DEPTH_OFFSET = 101, |
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| 67 | VC4_PACKET_CLIP_WINDOW = 102, |
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| 68 | VC4_PACKET_VIEWPORT_OFFSET = 103, |
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| 69 | VC4_PACKET_Z_CLIPPING = 104, |
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| 70 | VC4_PACKET_CLIPPER_XY_SCALING = 105, |
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| 71 | VC4_PACKET_CLIPPER_Z_SCALING = 106, |
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| 72 | |
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| 73 | VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112, |
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| 74 | VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113, |
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| 75 | VC4_PACKET_CLEAR_COLORS = 114, |
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| 76 | VC4_PACKET_TILE_COORDINATES = 115, |
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| 77 | |
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| 78 | /* Not an actual hardware packet -- this is what we use to put |
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| 79 | * references to GEM bos in the command stream, since we need the u32 |
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| 80 | * int the actual address packet in order to store the offset from the |
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| 81 | * start of the BO. |
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| 82 | */ |
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| 83 | VC4_PACKET_GEM_HANDLES = 254, |
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| 84 | } __attribute__ ((__packed__)); |
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| 85 | |
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| 86 | #define VC4_PACKET_HALT_SIZE 1 |
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| 87 | #define VC4_PACKET_NOP_SIZE 1 |
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| 88 | #define VC4_PACKET_FLUSH_SIZE 1 |
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| 89 | #define VC4_PACKET_FLUSH_ALL_SIZE 1 |
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| 90 | #define VC4_PACKET_START_TILE_BINNING_SIZE 1 |
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| 91 | #define VC4_PACKET_INCREMENT_SEMAPHORE_SIZE 1 |
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| 92 | #define VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE 1 |
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| 93 | #define VC4_PACKET_BRANCH_SIZE 5 |
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| 94 | #define VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE 5 |
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| 95 | #define VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE 1 |
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| 96 | #define VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF_SIZE 1 |
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| 97 | #define VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE 5 |
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| 98 | #define VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE 5 |
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| 99 | #define VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE 7 |
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| 100 | #define VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE 7 |
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| 101 | #define VC4_PACKET_GL_INDEXED_PRIMITIVE_SIZE 14 |
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| 102 | #define VC4_PACKET_GL_ARRAY_PRIMITIVE_SIZE 10 |
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| 103 | #define VC4_PACKET_COMPRESSED_PRIMITIVE_SIZE 1 |
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| 104 | #define VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE_SIZE 1 |
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| 105 | #define VC4_PACKET_PRIMITIVE_LIST_FORMAT_SIZE 2 |
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| 106 | #define VC4_PACKET_GL_SHADER_STATE_SIZE 5 |
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| 107 | #define VC4_PACKET_NV_SHADER_STATE_SIZE 5 |
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| 108 | #define VC4_PACKET_VG_SHADER_STATE_SIZE 5 |
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| 109 | #define VC4_PACKET_CONFIGURATION_BITS_SIZE 4 |
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| 110 | #define VC4_PACKET_FLAT_SHADE_FLAGS_SIZE 5 |
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| 111 | #define VC4_PACKET_POINT_SIZE_SIZE 5 |
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| 112 | #define VC4_PACKET_LINE_WIDTH_SIZE 5 |
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| 113 | #define VC4_PACKET_RHT_X_BOUNDARY_SIZE 3 |
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| 114 | #define VC4_PACKET_DEPTH_OFFSET_SIZE 5 |
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| 115 | #define VC4_PACKET_CLIP_WINDOW_SIZE 9 |
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| 116 | #define VC4_PACKET_VIEWPORT_OFFSET_SIZE 5 |
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| 117 | #define VC4_PACKET_Z_CLIPPING_SIZE 9 |
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| 118 | #define VC4_PACKET_CLIPPER_XY_SCALING_SIZE 9 |
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| 119 | #define VC4_PACKET_CLIPPER_Z_SCALING_SIZE 9 |
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| 120 | #define VC4_PACKET_TILE_BINNING_MODE_CONFIG_SIZE 16 |
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| 121 | #define VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE 11 |
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| 122 | #define VC4_PACKET_CLEAR_COLORS_SIZE 14 |
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| 123 | #define VC4_PACKET_TILE_COORDINATES_SIZE 3 |
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| 124 | #define VC4_PACKET_GEM_HANDLES_SIZE 9 |
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| 125 | |
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| 126 | /* Number of multisamples supported. */ |
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| 127 | #define VC4_MAX_SAMPLES 4 |
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| 128 | /* Size of a full resolution color or Z tile buffer load/store. */ |
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| 129 | #define VC4_TILE_BUFFER_SIZE (64 * 64 * 4) |
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| 130 | |
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| 131 | /** @{ |
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| 132 | * Bits used by packets like VC4_PACKET_STORE_TILE_BUFFER_GENERAL and |
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| 133 | * VC4_PACKET_TILE_RENDERING_MODE_CONFIG. |
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| 134 | */ |
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| 135 | #define VC4_TILING_FORMAT_LINEAR 0 |
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| 136 | #define VC4_TILING_FORMAT_T 1 |
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| 137 | #define VC4_TILING_FORMAT_LT 2 |
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| 138 | /** @} */ |
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| 139 | |
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| 140 | /** @{ |
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| 141 | * |
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| 142 | * low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and |
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| 143 | * VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER. |
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| 144 | */ |
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| 145 | #define VC4_LOADSTORE_FULL_RES_EOF BIT(3) |
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| 146 | #define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL BIT(2) |
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| 147 | #define VC4_LOADSTORE_FULL_RES_DISABLE_ZS BIT(1) |
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| 148 | #define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR BIT(0) |
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| 149 | |
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| 150 | /** @{ |
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| 151 | * |
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| 152 | * low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and |
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| 153 | * VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER. |
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| 154 | */ |
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| 155 | #define VC4_LOADSTORE_FULL_RES_EOF BIT(3) |
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| 156 | #define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL BIT(2) |
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| 157 | #define VC4_LOADSTORE_FULL_RES_DISABLE_ZS BIT(1) |
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| 158 | #define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR BIT(0) |
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| 159 | |
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| 160 | /** @{ |
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| 161 | * |
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| 162 | * byte 2 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and |
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| 163 | * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL (low bits of the address) |
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| 164 | */ |
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| 165 | |
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| 166 | #define VC4_LOADSTORE_TILE_BUFFER_EOF BIT(3) |
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| 167 | #define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK BIT(2) |
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| 168 | #define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS BIT(1) |
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| 169 | #define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR BIT(0) |
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| 170 | |
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| 171 | /** @} */ |
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| 172 | |
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| 173 | /** @{ |
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| 174 | * |
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| 175 | * byte 0-1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and |
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| 176 | * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL |
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| 177 | */ |
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| 178 | #define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR BIT(15) |
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| 179 | #define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR BIT(14) |
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| 180 | #define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR BIT(13) |
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| 181 | #define VC4_STORE_TILE_BUFFER_DISABLE_SWAP BIT(12) |
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| 182 | |
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| 183 | #define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK VC4_MASK(9, 8) |
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| 184 | #define VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT 8 |
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| 185 | #define VC4_LOADSTORE_TILE_BUFFER_RGBA8888 0 |
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| 186 | #define VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER 1 |
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| 187 | #define VC4_LOADSTORE_TILE_BUFFER_BGR565 2 |
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| 188 | /** @} */ |
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| 189 | |
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| 190 | /** @{ |
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| 191 | * |
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| 192 | * byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and |
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| 193 | * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL |
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| 194 | */ |
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| 195 | #define VC4_STORE_TILE_BUFFER_MODE_MASK VC4_MASK(7, 6) |
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| 196 | #define VC4_STORE_TILE_BUFFER_MODE_SHIFT 6 |
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| 197 | #define VC4_STORE_TILE_BUFFER_MODE_SAMPLE0 (0 << 6) |
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| 198 | #define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X4 (1 << 6) |
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| 199 | #define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X16 (2 << 6) |
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| 200 | |
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| 201 | /** The values of the field are VC4_TILING_FORMAT_* */ |
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| 202 | #define VC4_LOADSTORE_TILE_BUFFER_TILING_MASK VC4_MASK(5, 4) |
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| 203 | #define VC4_LOADSTORE_TILE_BUFFER_TILING_SHIFT 4 |
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| 204 | |
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| 205 | #define VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK VC4_MASK(2, 0) |
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| 206 | #define VC4_LOADSTORE_TILE_BUFFER_BUFFER_SHIFT 0 |
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| 207 | #define VC4_LOADSTORE_TILE_BUFFER_NONE 0 |
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| 208 | #define VC4_LOADSTORE_TILE_BUFFER_COLOR 1 |
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| 209 | #define VC4_LOADSTORE_TILE_BUFFER_ZS 2 |
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| 210 | #define VC4_LOADSTORE_TILE_BUFFER_Z 3 |
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| 211 | #define VC4_LOADSTORE_TILE_BUFFER_VG_MASK 4 |
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| 212 | #define VC4_LOADSTORE_TILE_BUFFER_FULL 5 |
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| 213 | /** @} */ |
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| 214 | |
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| 215 | #define VC4_INDEX_BUFFER_U8 (0 << 4) |
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| 216 | #define VC4_INDEX_BUFFER_U16 (1 << 4) |
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| 217 | |
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| 218 | /* This flag is only present in NV shader state. */ |
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| 219 | #define VC4_SHADER_FLAG_SHADED_CLIP_COORDS BIT(3) |
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| 220 | #define VC4_SHADER_FLAG_ENABLE_CLIPPING BIT(2) |
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| 221 | #define VC4_SHADER_FLAG_VS_POINT_SIZE BIT(1) |
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| 222 | #define VC4_SHADER_FLAG_FS_SINGLE_THREAD BIT(0) |
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| 223 | |
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| 224 | /** @{ byte 2 of config bits. */ |
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| 225 | #define VC4_CONFIG_BITS_EARLY_Z_UPDATE BIT(1) |
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| 226 | #define VC4_CONFIG_BITS_EARLY_Z BIT(0) |
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| 227 | /** @} */ |
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| 228 | |
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| 229 | /** @{ byte 1 of config bits. */ |
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| 230 | #define VC4_CONFIG_BITS_Z_UPDATE BIT(7) |
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| 231 | /** same values in this 3-bit field as PIPE_FUNC_* */ |
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| 232 | #define VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT 4 |
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| 233 | #define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE BIT(3) |
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| 234 | |
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| 235 | #define VC4_CONFIG_BITS_COVERAGE_UPDATE_NONZERO (0 << 1) |
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| 236 | #define VC4_CONFIG_BITS_COVERAGE_UPDATE_ODD (1 << 1) |
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| 237 | #define VC4_CONFIG_BITS_COVERAGE_UPDATE_OR (2 << 1) |
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| 238 | #define VC4_CONFIG_BITS_COVERAGE_UPDATE_ZERO (3 << 1) |
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| 239 | |
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| 240 | #define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT BIT(0) |
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| 241 | /** @} */ |
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| 242 | |
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| 243 | /** @{ byte 0 of config bits. */ |
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| 244 | #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_NONE (0 << 6) |
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| 245 | #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X (1 << 6) |
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| 246 | #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_16X (2 << 6) |
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| 247 | |
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| 248 | #define VC4_CONFIG_BITS_AA_POINTS_AND_LINES BIT(4) |
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| 249 | #define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET BIT(3) |
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| 250 | #define VC4_CONFIG_BITS_CW_PRIMITIVES BIT(2) |
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| 251 | #define VC4_CONFIG_BITS_ENABLE_PRIM_BACK BIT(1) |
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| 252 | #define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT BIT(0) |
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| 253 | /** @} */ |
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| 254 | |
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| 255 | /** @{ bits in the last u8 of VC4_PACKET_TILE_BINNING_MODE_CONFIG */ |
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| 256 | #define VC4_BIN_CONFIG_DB_NON_MS BIT(7) |
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| 257 | |
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| 258 | #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK VC4_MASK(6, 5) |
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| 259 | #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_SHIFT 5 |
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| 260 | #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32 0 |
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| 261 | #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_64 1 |
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| 262 | #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128 2 |
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| 263 | #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_256 3 |
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| 264 | |
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| 265 | #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK VC4_MASK(4, 3) |
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| 266 | #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_SHIFT 3 |
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| 267 | #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32 0 |
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| 268 | #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_64 1 |
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| 269 | #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_128 2 |
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| 270 | #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_256 3 |
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| 271 | |
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| 272 | #define VC4_BIN_CONFIG_AUTO_INIT_TSDA BIT(2) |
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| 273 | #define VC4_BIN_CONFIG_TILE_BUFFER_64BIT BIT(1) |
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| 274 | #define VC4_BIN_CONFIG_MS_MODE_4X BIT(0) |
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| 275 | /** @} */ |
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| 276 | |
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| 277 | /** @{ bits in the last u16 of VC4_PACKET_TILE_RENDERING_MODE_CONFIG */ |
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| 278 | #define VC4_RENDER_CONFIG_DB_NON_MS BIT(12) |
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| 279 | #define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE BIT(11) |
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| 280 | #define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G BIT(10) |
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| 281 | #define VC4_RENDER_CONFIG_COVERAGE_MODE BIT(9) |
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| 282 | #define VC4_RENDER_CONFIG_ENABLE_VG_MASK BIT(8) |
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| 283 | |
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| 284 | /** The values of the field are VC4_TILING_FORMAT_* */ |
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| 285 | #define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK VC4_MASK(7, 6) |
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| 286 | #define VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT 6 |
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| 287 | |
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| 288 | #define VC4_RENDER_CONFIG_DECIMATE_MODE_1X (0 << 4) |
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| 289 | #define VC4_RENDER_CONFIG_DECIMATE_MODE_4X (1 << 4) |
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| 290 | #define VC4_RENDER_CONFIG_DECIMATE_MODE_16X (2 << 4) |
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| 291 | |
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| 292 | #define VC4_RENDER_CONFIG_FORMAT_MASK VC4_MASK(3, 2) |
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| 293 | #define VC4_RENDER_CONFIG_FORMAT_SHIFT 2 |
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| 294 | #define VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED 0 |
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| 295 | #define VC4_RENDER_CONFIG_FORMAT_RGBA8888 1 |
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| 296 | #define VC4_RENDER_CONFIG_FORMAT_BGR565 2 |
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| 297 | |
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| 298 | #define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT BIT(1) |
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| 299 | #define VC4_RENDER_CONFIG_MS_MODE_4X BIT(0) |
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| 300 | |
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| 301 | #define VC4_PRIMITIVE_LIST_FORMAT_16_INDEX (1 << 4) |
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| 302 | #define VC4_PRIMITIVE_LIST_FORMAT_32_XY (3 << 4) |
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| 303 | #define VC4_PRIMITIVE_LIST_FORMAT_TYPE_POINTS (0 << 0) |
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| 304 | #define VC4_PRIMITIVE_LIST_FORMAT_TYPE_LINES (1 << 0) |
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| 305 | #define VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES (2 << 0) |
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| 306 | #define VC4_PRIMITIVE_LIST_FORMAT_TYPE_RHT (3 << 0) |
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| 307 | |
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| 308 | enum vc4_texture_data_type { |
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| 309 | VC4_TEXTURE_TYPE_RGBA8888 = 0, |
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| 310 | VC4_TEXTURE_TYPE_RGBX8888 = 1, |
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| 311 | VC4_TEXTURE_TYPE_RGBA4444 = 2, |
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| 312 | VC4_TEXTURE_TYPE_RGBA5551 = 3, |
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| 313 | VC4_TEXTURE_TYPE_RGB565 = 4, |
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| 314 | VC4_TEXTURE_TYPE_LUMINANCE = 5, |
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| 315 | VC4_TEXTURE_TYPE_ALPHA = 6, |
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| 316 | VC4_TEXTURE_TYPE_LUMALPHA = 7, |
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| 317 | VC4_TEXTURE_TYPE_ETC1 = 8, |
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| 318 | VC4_TEXTURE_TYPE_S16F = 9, |
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| 319 | VC4_TEXTURE_TYPE_S8 = 10, |
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| 320 | VC4_TEXTURE_TYPE_S16 = 11, |
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| 321 | VC4_TEXTURE_TYPE_BW1 = 12, |
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| 322 | VC4_TEXTURE_TYPE_A4 = 13, |
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| 323 | VC4_TEXTURE_TYPE_A1 = 14, |
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| 324 | VC4_TEXTURE_TYPE_RGBA64 = 15, |
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| 325 | VC4_TEXTURE_TYPE_RGBA32R = 16, |
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| 326 | VC4_TEXTURE_TYPE_YUV422R = 17, |
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| 327 | }; |
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| 328 | |
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| 329 | #define VC4_TEX_P0_OFFSET_MASK VC4_MASK(31, 12) |
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| 330 | #define VC4_TEX_P0_OFFSET_SHIFT 12 |
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| 331 | #define VC4_TEX_P0_CSWIZ_MASK VC4_MASK(11, 10) |
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| 332 | #define VC4_TEX_P0_CSWIZ_SHIFT 10 |
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| 333 | #define VC4_TEX_P0_CMMODE_MASK VC4_MASK(9, 9) |
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| 334 | #define VC4_TEX_P0_CMMODE_SHIFT 9 |
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| 335 | #define VC4_TEX_P0_FLIPY_MASK VC4_MASK(8, 8) |
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| 336 | #define VC4_TEX_P0_FLIPY_SHIFT 8 |
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| 337 | #define VC4_TEX_P0_TYPE_MASK VC4_MASK(7, 4) |
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| 338 | #define VC4_TEX_P0_TYPE_SHIFT 4 |
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| 339 | #define VC4_TEX_P0_MIPLVLS_MASK VC4_MASK(3, 0) |
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| 340 | #define VC4_TEX_P0_MIPLVLS_SHIFT 0 |
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| 341 | |
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| 342 | #define VC4_TEX_P1_TYPE4_MASK VC4_MASK(31, 31) |
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| 343 | #define VC4_TEX_P1_TYPE4_SHIFT 31 |
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| 344 | #define VC4_TEX_P1_HEIGHT_MASK VC4_MASK(30, 20) |
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| 345 | #define VC4_TEX_P1_HEIGHT_SHIFT 20 |
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| 346 | #define VC4_TEX_P1_ETCFLIP_MASK VC4_MASK(19, 19) |
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| 347 | #define VC4_TEX_P1_ETCFLIP_SHIFT 19 |
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| 348 | #define VC4_TEX_P1_WIDTH_MASK VC4_MASK(18, 8) |
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| 349 | #define VC4_TEX_P1_WIDTH_SHIFT 8 |
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| 350 | |
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| 351 | #define VC4_TEX_P1_MAGFILT_MASK VC4_MASK(7, 7) |
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| 352 | #define VC4_TEX_P1_MAGFILT_SHIFT 7 |
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| 353 | # define VC4_TEX_P1_MAGFILT_LINEAR 0 |
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| 354 | # define VC4_TEX_P1_MAGFILT_NEAREST 1 |
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| 355 | |
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| 356 | #define VC4_TEX_P1_MINFILT_MASK VC4_MASK(6, 4) |
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| 357 | #define VC4_TEX_P1_MINFILT_SHIFT 4 |
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| 358 | # define VC4_TEX_P1_MINFILT_LINEAR 0 |
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| 359 | # define VC4_TEX_P1_MINFILT_NEAREST 1 |
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| 360 | # define VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR 2 |
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| 361 | # define VC4_TEX_P1_MINFILT_NEAR_MIP_LIN 3 |
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| 362 | # define VC4_TEX_P1_MINFILT_LIN_MIP_NEAR 4 |
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| 363 | # define VC4_TEX_P1_MINFILT_LIN_MIP_LIN 5 |
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| 364 | |
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| 365 | #define VC4_TEX_P1_WRAP_T_MASK VC4_MASK(3, 2) |
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| 366 | #define VC4_TEX_P1_WRAP_T_SHIFT 2 |
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| 367 | #define VC4_TEX_P1_WRAP_S_MASK VC4_MASK(1, 0) |
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| 368 | #define VC4_TEX_P1_WRAP_S_SHIFT 0 |
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| 369 | # define VC4_TEX_P1_WRAP_REPEAT 0 |
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| 370 | # define VC4_TEX_P1_WRAP_CLAMP 1 |
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| 371 | # define VC4_TEX_P1_WRAP_MIRROR 2 |
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| 372 | # define VC4_TEX_P1_WRAP_BORDER 3 |
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| 373 | |
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| 374 | #define VC4_TEX_P2_PTYPE_MASK VC4_MASK(31, 30) |
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| 375 | #define VC4_TEX_P2_PTYPE_SHIFT 30 |
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| 376 | # define VC4_TEX_P2_PTYPE_IGNORED 0 |
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| 377 | # define VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE 1 |
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| 378 | # define VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS 2 |
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| 379 | # define VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS 3 |
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| 380 | |
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| 381 | /* VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE bits */ |
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| 382 | #define VC4_TEX_P2_CMST_MASK VC4_MASK(29, 12) |
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| 383 | #define VC4_TEX_P2_CMST_SHIFT 12 |
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| 384 | #define VC4_TEX_P2_BSLOD_MASK VC4_MASK(0, 0) |
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| 385 | #define VC4_TEX_P2_BSLOD_SHIFT 0 |
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| 386 | |
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| 387 | /* VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS */ |
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| 388 | #define VC4_TEX_P2_CHEIGHT_MASK VC4_MASK(22, 12) |
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| 389 | #define VC4_TEX_P2_CHEIGHT_SHIFT 12 |
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| 390 | #define VC4_TEX_P2_CWIDTH_MASK VC4_MASK(10, 0) |
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| 391 | #define VC4_TEX_P2_CWIDTH_SHIFT 0 |
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| 392 | |
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| 393 | /* VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS */ |
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| 394 | #define VC4_TEX_P2_CYOFF_MASK VC4_MASK(22, 12) |
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| 395 | #define VC4_TEX_P2_CYOFF_SHIFT 12 |
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| 396 | #define VC4_TEX_P2_CXOFF_MASK VC4_MASK(10, 0) |
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| 397 | #define VC4_TEX_P2_CXOFF_SHIFT 0 |
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| 398 | |
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| 399 | #endif /* VC4_PACKET_H */ |
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| 400 | |
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