1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) 2020 MaxLinear, Inc. |
4 | * |
5 | * This driver is a hardware monitoring driver for PVT controller |
6 | * (MR75203) which is used to configure & control Moortec embedded |
7 | * analog IP to enable multiple embedded temperature sensor(TS), |
8 | * voltage monitor(VM) & process detector(PD) modules. |
9 | */ |
10 | #include <linux/bits.h> |
11 | #include <linux/clk.h> |
12 | #include <linux/debugfs.h> |
13 | #include <linux/hwmon.h> |
14 | #include <linux/kstrtox.h> |
15 | #include <linux/module.h> |
16 | #include <linux/mod_devicetable.h> |
17 | #include <linux/mutex.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/property.h> |
20 | #include <linux/regmap.h> |
21 | #include <linux/reset.h> |
22 | #include <linux/slab.h> |
23 | #include <linux/units.h> |
24 | |
25 | /* PVT Common register */ |
26 | #define PVT_IP_CONFIG 0x04 |
27 | #define TS_NUM_MSK GENMASK(4, 0) |
28 | #define TS_NUM_SFT 0 |
29 | #define PD_NUM_MSK GENMASK(12, 8) |
30 | #define PD_NUM_SFT 8 |
31 | #define VM_NUM_MSK GENMASK(20, 16) |
32 | #define VM_NUM_SFT 16 |
33 | #define CH_NUM_MSK GENMASK(31, 24) |
34 | #define CH_NUM_SFT 24 |
35 | |
36 | #define VM_NUM_MAX (VM_NUM_MSK >> VM_NUM_SFT) |
37 | |
38 | /* Macro Common Register */ |
39 | #define CLK_SYNTH 0x00 |
40 | #define CLK_SYNTH_LO_SFT 0 |
41 | #define CLK_SYNTH_HI_SFT 8 |
42 | #define CLK_SYNTH_HOLD_SFT 16 |
43 | #define CLK_SYNTH_EN BIT(24) |
44 | #define CLK_SYS_CYCLES_MAX 514 |
45 | #define CLK_SYS_CYCLES_MIN 2 |
46 | |
47 | #define SDIF_DISABLE 0x04 |
48 | |
49 | #define SDIF_STAT 0x08 |
50 | #define SDIF_BUSY BIT(0) |
51 | #define SDIF_LOCK BIT(1) |
52 | |
53 | #define SDIF_W 0x0c |
54 | #define SDIF_PROG BIT(31) |
55 | #define SDIF_WRN_W BIT(27) |
56 | #define SDIF_WRN_R 0x00 |
57 | #define SDIF_ADDR_SFT 24 |
58 | |
59 | #define SDIF_HALT 0x10 |
60 | #define SDIF_CTRL 0x14 |
61 | #define SDIF_SMPL_CTRL 0x20 |
62 | |
63 | /* TS & PD Individual Macro Register */ |
64 | #define COM_REG_SIZE 0x40 |
65 | |
66 | #define SDIF_DONE(n) (COM_REG_SIZE + 0x14 + 0x40 * (n)) |
67 | #define SDIF_SMPL_DONE BIT(0) |
68 | |
69 | #define SDIF_DATA(n) (COM_REG_SIZE + 0x18 + 0x40 * (n)) |
70 | #define SAMPLE_DATA_MSK GENMASK(15, 0) |
71 | |
72 | #define HILO_RESET(n) (COM_REG_SIZE + 0x2c + 0x40 * (n)) |
73 | |
74 | /* VM Individual Macro Register */ |
75 | #define VM_COM_REG_SIZE 0x200 |
76 | #define VM_SDIF_DONE(vm) (VM_COM_REG_SIZE + 0x34 + 0x200 * (vm)) |
77 | #define VM_SDIF_DATA(vm, ch) \ |
78 | (VM_COM_REG_SIZE + 0x40 + 0x200 * (vm) + 0x4 * (ch)) |
79 | |
80 | /* SDA Slave Register */ |
81 | #define IP_CTRL 0x00 |
82 | #define IP_RST_REL BIT(1) |
83 | #define IP_RUN_CONT BIT(3) |
84 | #define IP_AUTO BIT(8) |
85 | #define IP_VM_MODE BIT(10) |
86 | |
87 | #define IP_CFG 0x01 |
88 | #define CFG0_MODE_2 BIT(0) |
89 | #define CFG0_PARALLEL_OUT 0 |
90 | #define CFG0_12_BIT 0 |
91 | #define CFG1_VOL_MEAS_MODE 0 |
92 | #define CFG1_PARALLEL_OUT 0 |
93 | #define CFG1_14_BIT 0 |
94 | |
95 | #define IP_DATA 0x03 |
96 | |
97 | #define IP_POLL 0x04 |
98 | #define VM_CH_INIT BIT(20) |
99 | #define VM_CH_REQ BIT(21) |
100 | |
101 | #define IP_TMR 0x05 |
102 | #define POWER_DELAY_CYCLE_256 0x100 |
103 | #define POWER_DELAY_CYCLE_64 0x40 |
104 | |
105 | #define PVT_POLL_DELAY_US 20 |
106 | #define PVT_POLL_TIMEOUT_US 20000 |
107 | #define PVT_CONV_BITS 10 |
108 | #define PVT_N_CONST 90 |
109 | #define PVT_R_CONST 245805 |
110 | |
111 | #define PVT_TEMP_MIN_mC -40000 |
112 | #define PVT_TEMP_MAX_mC 125000 |
113 | |
114 | /* Temperature coefficients for series 5 */ |
115 | #define PVT_SERIES5_H_CONST 200000 |
116 | #define PVT_SERIES5_G_CONST 60000 |
117 | #define PVT_SERIES5_J_CONST -100 |
118 | #define PVT_SERIES5_CAL5_CONST 4094 |
119 | |
120 | /* Temperature coefficients for series 6 */ |
121 | #define PVT_SERIES6_H_CONST 249400 |
122 | #define PVT_SERIES6_G_CONST 57400 |
123 | #define PVT_SERIES6_J_CONST 0 |
124 | #define PVT_SERIES6_CAL5_CONST 4096 |
125 | |
126 | #define TEMPERATURE_SENSOR_SERIES_5 5 |
127 | #define TEMPERATURE_SENSOR_SERIES_6 6 |
128 | |
129 | #define PRE_SCALER_X1 1 |
130 | #define PRE_SCALER_X2 2 |
131 | |
132 | /** |
133 | * struct voltage_device - VM single input parameters. |
134 | * @vm_map: Map channel number to VM index. |
135 | * @ch_map: Map channel number to channel index. |
136 | * @pre_scaler: Pre scaler value (1 or 2) used to normalize the voltage output |
137 | * result. |
138 | * |
139 | * The structure provides mapping between channel-number (0..N-1) to VM-index |
140 | * (0..num_vm-1) and channel-index (0..ch_num-1) where N = num_vm * ch_num. |
141 | * It also provides normalization factor for the VM equation. |
142 | */ |
143 | struct voltage_device { |
144 | u32 vm_map; |
145 | u32 ch_map; |
146 | u32 pre_scaler; |
147 | }; |
148 | |
149 | /** |
150 | * struct voltage_channels - VM channel count. |
151 | * @total: Total number of channels in all VMs. |
152 | * @max: Maximum number of channels among all VMs. |
153 | * |
154 | * The structure provides channel count information across all VMs. |
155 | */ |
156 | struct voltage_channels { |
157 | u32 total; |
158 | u8 max; |
159 | }; |
160 | |
161 | struct temp_coeff { |
162 | u32 h; |
163 | u32 g; |
164 | u32 cal5; |
165 | s32 j; |
166 | }; |
167 | |
168 | struct pvt_device { |
169 | struct regmap *c_map; |
170 | struct regmap *t_map; |
171 | struct regmap *p_map; |
172 | struct regmap *v_map; |
173 | struct clk *clk; |
174 | struct reset_control *rst; |
175 | struct dentry *dbgfs_dir; |
176 | struct voltage_device *vd; |
177 | struct voltage_channels vm_channels; |
178 | struct temp_coeff ts_coeff; |
179 | u32 t_num; |
180 | u32 p_num; |
181 | u32 v_num; |
182 | u32 ip_freq; |
183 | }; |
184 | |
185 | static ssize_t pvt_ts_coeff_j_read(struct file *file, char __user *user_buf, |
186 | size_t count, loff_t *ppos) |
187 | { |
188 | struct pvt_device *pvt = file->private_data; |
189 | unsigned int len; |
190 | char buf[13]; |
191 | |
192 | len = scnprintf(buf, size: sizeof(buf), fmt: "%d\n" , pvt->ts_coeff.j); |
193 | |
194 | return simple_read_from_buffer(to: user_buf, count, ppos, from: buf, available: len); |
195 | } |
196 | |
197 | static ssize_t pvt_ts_coeff_j_write(struct file *file, |
198 | const char __user *user_buf, |
199 | size_t count, loff_t *ppos) |
200 | { |
201 | struct pvt_device *pvt = file->private_data; |
202 | int ret; |
203 | |
204 | ret = kstrtos32_from_user(s: user_buf, count, base: 0, res: &pvt->ts_coeff.j); |
205 | if (ret) |
206 | return ret; |
207 | |
208 | return count; |
209 | } |
210 | |
211 | static const struct file_operations pvt_ts_coeff_j_fops = { |
212 | .read = pvt_ts_coeff_j_read, |
213 | .write = pvt_ts_coeff_j_write, |
214 | .open = simple_open, |
215 | .owner = THIS_MODULE, |
216 | .llseek = default_llseek, |
217 | }; |
218 | |
219 | static void devm_pvt_ts_dbgfs_remove(void *data) |
220 | { |
221 | struct pvt_device *pvt = (struct pvt_device *)data; |
222 | |
223 | debugfs_remove_recursive(dentry: pvt->dbgfs_dir); |
224 | pvt->dbgfs_dir = NULL; |
225 | } |
226 | |
227 | static int pvt_ts_dbgfs_create(struct pvt_device *pvt, struct device *dev) |
228 | { |
229 | pvt->dbgfs_dir = debugfs_create_dir(name: dev_name(dev), NULL); |
230 | |
231 | debugfs_create_u32(name: "ts_coeff_h" , mode: 0644, parent: pvt->dbgfs_dir, |
232 | value: &pvt->ts_coeff.h); |
233 | debugfs_create_u32(name: "ts_coeff_g" , mode: 0644, parent: pvt->dbgfs_dir, |
234 | value: &pvt->ts_coeff.g); |
235 | debugfs_create_u32(name: "ts_coeff_cal5" , mode: 0644, parent: pvt->dbgfs_dir, |
236 | value: &pvt->ts_coeff.cal5); |
237 | debugfs_create_file(name: "ts_coeff_j" , mode: 0644, parent: pvt->dbgfs_dir, data: pvt, |
238 | fops: &pvt_ts_coeff_j_fops); |
239 | |
240 | return devm_add_action_or_reset(dev, devm_pvt_ts_dbgfs_remove, pvt); |
241 | } |
242 | |
243 | static umode_t pvt_is_visible(const void *data, enum hwmon_sensor_types type, |
244 | u32 attr, int channel) |
245 | { |
246 | switch (type) { |
247 | case hwmon_temp: |
248 | if (attr == hwmon_temp_input) |
249 | return 0444; |
250 | break; |
251 | case hwmon_in: |
252 | if (attr == hwmon_in_input) |
253 | return 0444; |
254 | break; |
255 | default: |
256 | break; |
257 | } |
258 | return 0; |
259 | } |
260 | |
261 | static long pvt_calc_temp(struct pvt_device *pvt, u32 nbs) |
262 | { |
263 | /* |
264 | * Convert the register value to degrees centigrade temperature: |
265 | * T = G + H * (n / cal5 - 0.5) + J * F |
266 | */ |
267 | struct temp_coeff *ts_coeff = &pvt->ts_coeff; |
268 | |
269 | s64 tmp = ts_coeff->g + |
270 | div_s64(dividend: ts_coeff->h * (s64)nbs, divisor: ts_coeff->cal5) - |
271 | ts_coeff->h / 2 + |
272 | div_s64(dividend: ts_coeff->j * (s64)pvt->ip_freq, HZ_PER_MHZ); |
273 | |
274 | return clamp_val(tmp, PVT_TEMP_MIN_mC, PVT_TEMP_MAX_mC); |
275 | } |
276 | |
277 | static int pvt_read_temp(struct device *dev, u32 attr, int channel, long *val) |
278 | { |
279 | struct pvt_device *pvt = dev_get_drvdata(dev); |
280 | struct regmap *t_map = pvt->t_map; |
281 | u32 stat, nbs; |
282 | int ret; |
283 | |
284 | switch (attr) { |
285 | case hwmon_temp_input: |
286 | ret = regmap_read_poll_timeout(t_map, SDIF_DONE(channel), |
287 | stat, stat & SDIF_SMPL_DONE, |
288 | PVT_POLL_DELAY_US, |
289 | PVT_POLL_TIMEOUT_US); |
290 | if (ret) |
291 | return ret; |
292 | |
293 | ret = regmap_read(map: t_map, SDIF_DATA(channel), val: &nbs); |
294 | if (ret < 0) |
295 | return ret; |
296 | |
297 | nbs &= SAMPLE_DATA_MSK; |
298 | |
299 | /* |
300 | * Convert the register value to |
301 | * degrees centigrade temperature |
302 | */ |
303 | *val = pvt_calc_temp(pvt, nbs); |
304 | |
305 | return 0; |
306 | default: |
307 | return -EOPNOTSUPP; |
308 | } |
309 | } |
310 | |
311 | static int pvt_read_in(struct device *dev, u32 attr, int channel, long *val) |
312 | { |
313 | struct pvt_device *pvt = dev_get_drvdata(dev); |
314 | struct regmap *v_map = pvt->v_map; |
315 | u32 n, stat, pre_scaler; |
316 | u8 vm_idx, ch_idx; |
317 | int ret; |
318 | |
319 | if (channel >= pvt->vm_channels.total) |
320 | return -EINVAL; |
321 | |
322 | vm_idx = pvt->vd[channel].vm_map; |
323 | ch_idx = pvt->vd[channel].ch_map; |
324 | |
325 | switch (attr) { |
326 | case hwmon_in_input: |
327 | ret = regmap_read_poll_timeout(v_map, VM_SDIF_DONE(vm_idx), |
328 | stat, stat & SDIF_SMPL_DONE, |
329 | PVT_POLL_DELAY_US, |
330 | PVT_POLL_TIMEOUT_US); |
331 | if (ret) |
332 | return ret; |
333 | |
334 | ret = regmap_read(map: v_map, VM_SDIF_DATA(vm_idx, ch_idx), val: &n); |
335 | if (ret < 0) |
336 | return ret; |
337 | |
338 | n &= SAMPLE_DATA_MSK; |
339 | pre_scaler = pvt->vd[channel].pre_scaler; |
340 | /* |
341 | * Convert the N bitstream count into voltage. |
342 | * To support negative voltage calculation for 64bit machines |
343 | * n must be cast to long, since n and *val differ both in |
344 | * signedness and in size. |
345 | * Division is used instead of right shift, because for signed |
346 | * numbers, the sign bit is used to fill the vacated bit |
347 | * positions, and if the number is negative, 1 is used. |
348 | * BIT(x) may not be used instead of (1 << x) because it's |
349 | * unsigned. |
350 | */ |
351 | *val = pre_scaler * (PVT_N_CONST * (long)n - PVT_R_CONST) / |
352 | (1 << PVT_CONV_BITS); |
353 | |
354 | return 0; |
355 | default: |
356 | return -EOPNOTSUPP; |
357 | } |
358 | } |
359 | |
360 | static int pvt_read(struct device *dev, enum hwmon_sensor_types type, |
361 | u32 attr, int channel, long *val) |
362 | { |
363 | switch (type) { |
364 | case hwmon_temp: |
365 | return pvt_read_temp(dev, attr, channel, val); |
366 | case hwmon_in: |
367 | return pvt_read_in(dev, attr, channel, val); |
368 | default: |
369 | return -EOPNOTSUPP; |
370 | } |
371 | } |
372 | |
373 | static struct hwmon_channel_info pvt_temp = { |
374 | .type = hwmon_temp, |
375 | }; |
376 | |
377 | static struct hwmon_channel_info pvt_in = { |
378 | .type = hwmon_in, |
379 | }; |
380 | |
381 | static const struct hwmon_ops pvt_hwmon_ops = { |
382 | .is_visible = pvt_is_visible, |
383 | .read = pvt_read, |
384 | }; |
385 | |
386 | static struct hwmon_chip_info pvt_chip_info = { |
387 | .ops = &pvt_hwmon_ops, |
388 | }; |
389 | |
390 | static int pvt_init(struct pvt_device *pvt) |
391 | { |
392 | u16 sys_freq, key, middle, low = 4, high = 8; |
393 | struct regmap *t_map = pvt->t_map; |
394 | struct regmap *p_map = pvt->p_map; |
395 | struct regmap *v_map = pvt->v_map; |
396 | u32 t_num = pvt->t_num; |
397 | u32 p_num = pvt->p_num; |
398 | u32 v_num = pvt->v_num; |
399 | u32 clk_synth, val; |
400 | int ret; |
401 | |
402 | sys_freq = clk_get_rate(clk: pvt->clk) / HZ_PER_MHZ; |
403 | while (high >= low) { |
404 | middle = (low + high + 1) / 2; |
405 | key = DIV_ROUND_CLOSEST(sys_freq, middle); |
406 | if (key > CLK_SYS_CYCLES_MAX) { |
407 | low = middle + 1; |
408 | continue; |
409 | } else if (key < CLK_SYS_CYCLES_MIN) { |
410 | high = middle - 1; |
411 | continue; |
412 | } else { |
413 | break; |
414 | } |
415 | } |
416 | |
417 | /* |
418 | * The system supports 'clk_sys' to 'clk_ip' frequency ratios |
419 | * from 2:1 to 512:1 |
420 | */ |
421 | key = clamp_val(key, CLK_SYS_CYCLES_MIN, CLK_SYS_CYCLES_MAX) - 2; |
422 | |
423 | clk_synth = ((key + 1) >> 1) << CLK_SYNTH_LO_SFT | |
424 | (key >> 1) << CLK_SYNTH_HI_SFT | |
425 | (key >> 1) << CLK_SYNTH_HOLD_SFT | CLK_SYNTH_EN; |
426 | |
427 | pvt->ip_freq = clk_get_rate(clk: pvt->clk) / (key + 2); |
428 | |
429 | if (t_num) { |
430 | ret = regmap_write(map: t_map, SDIF_SMPL_CTRL, val: 0x0); |
431 | if (ret < 0) |
432 | return ret; |
433 | |
434 | ret = regmap_write(map: t_map, SDIF_HALT, val: 0x0); |
435 | if (ret < 0) |
436 | return ret; |
437 | |
438 | ret = regmap_write(map: t_map, CLK_SYNTH, val: clk_synth); |
439 | if (ret < 0) |
440 | return ret; |
441 | |
442 | ret = regmap_write(map: t_map, SDIF_DISABLE, val: 0x0); |
443 | if (ret < 0) |
444 | return ret; |
445 | |
446 | ret = regmap_read_poll_timeout(t_map, SDIF_STAT, |
447 | val, !(val & SDIF_BUSY), |
448 | PVT_POLL_DELAY_US, |
449 | PVT_POLL_TIMEOUT_US); |
450 | if (ret) |
451 | return ret; |
452 | |
453 | val = CFG0_MODE_2 | CFG0_PARALLEL_OUT | CFG0_12_BIT | |
454 | IP_CFG << SDIF_ADDR_SFT | SDIF_WRN_W | SDIF_PROG; |
455 | ret = regmap_write(map: t_map, SDIF_W, val); |
456 | if (ret < 0) |
457 | return ret; |
458 | |
459 | ret = regmap_read_poll_timeout(t_map, SDIF_STAT, |
460 | val, !(val & SDIF_BUSY), |
461 | PVT_POLL_DELAY_US, |
462 | PVT_POLL_TIMEOUT_US); |
463 | if (ret) |
464 | return ret; |
465 | |
466 | val = POWER_DELAY_CYCLE_256 | IP_TMR << SDIF_ADDR_SFT | |
467 | SDIF_WRN_W | SDIF_PROG; |
468 | ret = regmap_write(map: t_map, SDIF_W, val); |
469 | if (ret < 0) |
470 | return ret; |
471 | |
472 | ret = regmap_read_poll_timeout(t_map, SDIF_STAT, |
473 | val, !(val & SDIF_BUSY), |
474 | PVT_POLL_DELAY_US, |
475 | PVT_POLL_TIMEOUT_US); |
476 | if (ret) |
477 | return ret; |
478 | |
479 | val = IP_RST_REL | IP_RUN_CONT | IP_AUTO | |
480 | IP_CTRL << SDIF_ADDR_SFT | |
481 | SDIF_WRN_W | SDIF_PROG; |
482 | ret = regmap_write(map: t_map, SDIF_W, val); |
483 | if (ret < 0) |
484 | return ret; |
485 | } |
486 | |
487 | if (p_num) { |
488 | ret = regmap_write(map: p_map, SDIF_HALT, val: 0x0); |
489 | if (ret < 0) |
490 | return ret; |
491 | |
492 | ret = regmap_write(map: p_map, SDIF_DISABLE, BIT(p_num) - 1); |
493 | if (ret < 0) |
494 | return ret; |
495 | |
496 | ret = regmap_write(map: p_map, CLK_SYNTH, val: clk_synth); |
497 | if (ret < 0) |
498 | return ret; |
499 | } |
500 | |
501 | if (v_num) { |
502 | ret = regmap_write(map: v_map, SDIF_SMPL_CTRL, val: 0x0); |
503 | if (ret < 0) |
504 | return ret; |
505 | |
506 | ret = regmap_write(map: v_map, SDIF_HALT, val: 0x0); |
507 | if (ret < 0) |
508 | return ret; |
509 | |
510 | ret = regmap_write(map: v_map, CLK_SYNTH, val: clk_synth); |
511 | if (ret < 0) |
512 | return ret; |
513 | |
514 | ret = regmap_write(map: v_map, SDIF_DISABLE, val: 0x0); |
515 | if (ret < 0) |
516 | return ret; |
517 | |
518 | ret = regmap_read_poll_timeout(v_map, SDIF_STAT, |
519 | val, !(val & SDIF_BUSY), |
520 | PVT_POLL_DELAY_US, |
521 | PVT_POLL_TIMEOUT_US); |
522 | if (ret) |
523 | return ret; |
524 | |
525 | val = (BIT(pvt->vm_channels.max) - 1) | VM_CH_INIT | |
526 | IP_POLL << SDIF_ADDR_SFT | SDIF_WRN_W | SDIF_PROG; |
527 | ret = regmap_write(map: v_map, SDIF_W, val); |
528 | if (ret < 0) |
529 | return ret; |
530 | |
531 | ret = regmap_read_poll_timeout(v_map, SDIF_STAT, |
532 | val, !(val & SDIF_BUSY), |
533 | PVT_POLL_DELAY_US, |
534 | PVT_POLL_TIMEOUT_US); |
535 | if (ret) |
536 | return ret; |
537 | |
538 | val = CFG1_VOL_MEAS_MODE | CFG1_PARALLEL_OUT | |
539 | CFG1_14_BIT | IP_CFG << SDIF_ADDR_SFT | |
540 | SDIF_WRN_W | SDIF_PROG; |
541 | ret = regmap_write(map: v_map, SDIF_W, val); |
542 | if (ret < 0) |
543 | return ret; |
544 | |
545 | ret = regmap_read_poll_timeout(v_map, SDIF_STAT, |
546 | val, !(val & SDIF_BUSY), |
547 | PVT_POLL_DELAY_US, |
548 | PVT_POLL_TIMEOUT_US); |
549 | if (ret) |
550 | return ret; |
551 | |
552 | val = POWER_DELAY_CYCLE_64 | IP_TMR << SDIF_ADDR_SFT | |
553 | SDIF_WRN_W | SDIF_PROG; |
554 | ret = regmap_write(map: v_map, SDIF_W, val); |
555 | if (ret < 0) |
556 | return ret; |
557 | |
558 | ret = regmap_read_poll_timeout(v_map, SDIF_STAT, |
559 | val, !(val & SDIF_BUSY), |
560 | PVT_POLL_DELAY_US, |
561 | PVT_POLL_TIMEOUT_US); |
562 | if (ret) |
563 | return ret; |
564 | |
565 | val = IP_RST_REL | IP_RUN_CONT | IP_AUTO | IP_VM_MODE | |
566 | IP_CTRL << SDIF_ADDR_SFT | |
567 | SDIF_WRN_W | SDIF_PROG; |
568 | ret = regmap_write(map: v_map, SDIF_W, val); |
569 | if (ret < 0) |
570 | return ret; |
571 | } |
572 | |
573 | return 0; |
574 | } |
575 | |
576 | static struct regmap_config pvt_regmap_config = { |
577 | .reg_bits = 32, |
578 | .reg_stride = 4, |
579 | .val_bits = 32, |
580 | }; |
581 | |
582 | static int pvt_get_regmap(struct platform_device *pdev, char *reg_name, |
583 | struct pvt_device *pvt) |
584 | { |
585 | struct device *dev = &pdev->dev; |
586 | struct regmap **reg_map; |
587 | void __iomem *io_base; |
588 | |
589 | if (!strcmp(reg_name, "common" )) |
590 | reg_map = &pvt->c_map; |
591 | else if (!strcmp(reg_name, "ts" )) |
592 | reg_map = &pvt->t_map; |
593 | else if (!strcmp(reg_name, "pd" )) |
594 | reg_map = &pvt->p_map; |
595 | else if (!strcmp(reg_name, "vm" )) |
596 | reg_map = &pvt->v_map; |
597 | else |
598 | return -EINVAL; |
599 | |
600 | io_base = devm_platform_ioremap_resource_byname(pdev, name: reg_name); |
601 | if (IS_ERR(ptr: io_base)) |
602 | return PTR_ERR(ptr: io_base); |
603 | |
604 | pvt_regmap_config.name = reg_name; |
605 | *reg_map = devm_regmap_init_mmio(dev, io_base, &pvt_regmap_config); |
606 | if (IS_ERR(ptr: *reg_map)) { |
607 | dev_err(dev, "failed to init register map\n" ); |
608 | return PTR_ERR(ptr: *reg_map); |
609 | } |
610 | |
611 | return 0; |
612 | } |
613 | |
614 | static void pvt_reset_control_assert(void *data) |
615 | { |
616 | struct pvt_device *pvt = data; |
617 | |
618 | reset_control_assert(rstc: pvt->rst); |
619 | } |
620 | |
621 | static int pvt_reset_control_deassert(struct device *dev, struct pvt_device *pvt) |
622 | { |
623 | int ret; |
624 | |
625 | ret = reset_control_deassert(rstc: pvt->rst); |
626 | if (ret) |
627 | return ret; |
628 | |
629 | return devm_add_action_or_reset(dev, pvt_reset_control_assert, pvt); |
630 | } |
631 | |
632 | static int pvt_get_active_channel(struct device *dev, struct pvt_device *pvt, |
633 | u32 vm_num, u32 ch_num, u8 *vm_idx) |
634 | { |
635 | u8 vm_active_ch[VM_NUM_MAX]; |
636 | int ret, i, j, k; |
637 | |
638 | ret = device_property_read_u8_array(dev, propname: "moortec,vm-active-channels" , |
639 | val: vm_active_ch, nval: vm_num); |
640 | if (ret) { |
641 | /* |
642 | * Incase "moortec,vm-active-channels" property is not defined, |
643 | * we assume each VM sensor has all of its channels active. |
644 | */ |
645 | memset(vm_active_ch, ch_num, vm_num); |
646 | pvt->vm_channels.max = ch_num; |
647 | pvt->vm_channels.total = ch_num * vm_num; |
648 | } else { |
649 | for (i = 0; i < vm_num; i++) { |
650 | if (vm_active_ch[i] > ch_num) { |
651 | dev_err(dev, "invalid active channels: %u\n" , |
652 | vm_active_ch[i]); |
653 | return -EINVAL; |
654 | } |
655 | |
656 | pvt->vm_channels.total += vm_active_ch[i]; |
657 | |
658 | if (vm_active_ch[i] > pvt->vm_channels.max) |
659 | pvt->vm_channels.max = vm_active_ch[i]; |
660 | } |
661 | } |
662 | |
663 | /* |
664 | * Map between the channel-number to VM-index and channel-index. |
665 | * Example - 3 VMs, "moortec,vm_active_ch" = <5 2 4>: |
666 | * vm_map = [0 0 0 0 0 1 1 2 2 2 2] |
667 | * ch_map = [0 1 2 3 4 0 1 0 1 2 3] |
668 | */ |
669 | pvt->vd = devm_kcalloc(dev, n: pvt->vm_channels.total, size: sizeof(*pvt->vd), |
670 | GFP_KERNEL); |
671 | if (!pvt->vd) |
672 | return -ENOMEM; |
673 | |
674 | k = 0; |
675 | for (i = 0; i < vm_num; i++) { |
676 | for (j = 0; j < vm_active_ch[i]; j++) { |
677 | pvt->vd[k].vm_map = vm_idx[i]; |
678 | pvt->vd[k].ch_map = j; |
679 | k++; |
680 | } |
681 | } |
682 | |
683 | return 0; |
684 | } |
685 | |
686 | static int pvt_get_pre_scaler(struct device *dev, struct pvt_device *pvt) |
687 | { |
688 | u8 *pre_scaler_ch_list; |
689 | int i, ret, num_ch; |
690 | u32 channel; |
691 | |
692 | /* Set default pre-scaler value to be 1. */ |
693 | for (i = 0; i < pvt->vm_channels.total; i++) |
694 | pvt->vd[i].pre_scaler = PRE_SCALER_X1; |
695 | |
696 | /* Get number of channels configured in "moortec,vm-pre-scaler-x2". */ |
697 | num_ch = device_property_count_u8(dev, propname: "moortec,vm-pre-scaler-x2" ); |
698 | if (num_ch <= 0) |
699 | return 0; |
700 | |
701 | pre_scaler_ch_list = kcalloc(n: num_ch, size: sizeof(*pre_scaler_ch_list), |
702 | GFP_KERNEL); |
703 | if (!pre_scaler_ch_list) |
704 | return -ENOMEM; |
705 | |
706 | /* Get list of all channels that have pre-scaler of 2. */ |
707 | ret = device_property_read_u8_array(dev, propname: "moortec,vm-pre-scaler-x2" , |
708 | val: pre_scaler_ch_list, nval: num_ch); |
709 | if (ret) |
710 | goto out; |
711 | |
712 | for (i = 0; i < num_ch; i++) { |
713 | channel = pre_scaler_ch_list[i]; |
714 | pvt->vd[channel].pre_scaler = PRE_SCALER_X2; |
715 | } |
716 | |
717 | out: |
718 | kfree(objp: pre_scaler_ch_list); |
719 | |
720 | return ret; |
721 | } |
722 | |
723 | static int pvt_set_temp_coeff(struct device *dev, struct pvt_device *pvt) |
724 | { |
725 | struct temp_coeff *ts_coeff = &pvt->ts_coeff; |
726 | u32 series; |
727 | int ret; |
728 | |
729 | /* Incase ts-series property is not defined, use default 5. */ |
730 | ret = device_property_read_u32(dev, propname: "moortec,ts-series" , val: &series); |
731 | if (ret) |
732 | series = TEMPERATURE_SENSOR_SERIES_5; |
733 | |
734 | switch (series) { |
735 | case TEMPERATURE_SENSOR_SERIES_5: |
736 | ts_coeff->h = PVT_SERIES5_H_CONST; |
737 | ts_coeff->g = PVT_SERIES5_G_CONST; |
738 | ts_coeff->j = PVT_SERIES5_J_CONST; |
739 | ts_coeff->cal5 = PVT_SERIES5_CAL5_CONST; |
740 | break; |
741 | case TEMPERATURE_SENSOR_SERIES_6: |
742 | ts_coeff->h = PVT_SERIES6_H_CONST; |
743 | ts_coeff->g = PVT_SERIES6_G_CONST; |
744 | ts_coeff->j = PVT_SERIES6_J_CONST; |
745 | ts_coeff->cal5 = PVT_SERIES6_CAL5_CONST; |
746 | break; |
747 | default: |
748 | dev_err(dev, "invalid temperature sensor series (%u)\n" , |
749 | series); |
750 | return -EINVAL; |
751 | } |
752 | |
753 | dev_dbg(dev, "temperature sensor series = %u\n" , series); |
754 | |
755 | /* Override ts-coeff-h/g/j/cal5 if they are defined. */ |
756 | device_property_read_u32(dev, propname: "moortec,ts-coeff-h" , val: &ts_coeff->h); |
757 | device_property_read_u32(dev, propname: "moortec,ts-coeff-g" , val: &ts_coeff->g); |
758 | device_property_read_u32(dev, propname: "moortec,ts-coeff-j" , val: &ts_coeff->j); |
759 | device_property_read_u32(dev, propname: "moortec,ts-coeff-cal5" , val: &ts_coeff->cal5); |
760 | |
761 | dev_dbg(dev, "ts-coeff: h = %u, g = %u, j = %d, cal5 = %u\n" , |
762 | ts_coeff->h, ts_coeff->g, ts_coeff->j, ts_coeff->cal5); |
763 | |
764 | return 0; |
765 | } |
766 | |
767 | static int mr75203_probe(struct platform_device *pdev) |
768 | { |
769 | u32 ts_num, vm_num, pd_num, ch_num, val, index, i; |
770 | const struct hwmon_channel_info **pvt_info; |
771 | struct device *dev = &pdev->dev; |
772 | u32 *temp_config, *in_config; |
773 | struct device *hwmon_dev; |
774 | struct pvt_device *pvt; |
775 | int ret; |
776 | |
777 | pvt = devm_kzalloc(dev, size: sizeof(*pvt), GFP_KERNEL); |
778 | if (!pvt) |
779 | return -ENOMEM; |
780 | |
781 | ret = pvt_get_regmap(pdev, reg_name: "common" , pvt); |
782 | if (ret) |
783 | return ret; |
784 | |
785 | pvt->clk = devm_clk_get_enabled(dev, NULL); |
786 | if (IS_ERR(ptr: pvt->clk)) |
787 | return dev_err_probe(dev, err: PTR_ERR(ptr: pvt->clk), fmt: "failed to get clock\n" ); |
788 | |
789 | pvt->rst = devm_reset_control_get_optional_exclusive(dev, NULL); |
790 | if (IS_ERR(ptr: pvt->rst)) |
791 | return dev_err_probe(dev, err: PTR_ERR(ptr: pvt->rst), |
792 | fmt: "failed to get reset control\n" ); |
793 | |
794 | if (pvt->rst) { |
795 | ret = pvt_reset_control_deassert(dev, pvt); |
796 | if (ret) |
797 | return dev_err_probe(dev, err: ret, |
798 | fmt: "cannot deassert reset control\n" ); |
799 | } |
800 | |
801 | ret = regmap_read(map: pvt->c_map, PVT_IP_CONFIG, val: &val); |
802 | if (ret < 0) |
803 | return ret; |
804 | |
805 | ts_num = (val & TS_NUM_MSK) >> TS_NUM_SFT; |
806 | pd_num = (val & PD_NUM_MSK) >> PD_NUM_SFT; |
807 | vm_num = (val & VM_NUM_MSK) >> VM_NUM_SFT; |
808 | ch_num = (val & CH_NUM_MSK) >> CH_NUM_SFT; |
809 | pvt->t_num = ts_num; |
810 | pvt->p_num = pd_num; |
811 | pvt->v_num = vm_num; |
812 | val = 0; |
813 | if (ts_num) |
814 | val++; |
815 | if (vm_num) |
816 | val++; |
817 | if (!val) |
818 | return -ENODEV; |
819 | |
820 | pvt_info = devm_kcalloc(dev, n: val + 2, size: sizeof(*pvt_info), GFP_KERNEL); |
821 | if (!pvt_info) |
822 | return -ENOMEM; |
823 | pvt_info[0] = HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ); |
824 | index = 1; |
825 | |
826 | if (ts_num) { |
827 | ret = pvt_get_regmap(pdev, reg_name: "ts" , pvt); |
828 | if (ret) |
829 | return ret; |
830 | |
831 | ret = pvt_set_temp_coeff(dev, pvt); |
832 | if (ret) |
833 | return ret; |
834 | |
835 | temp_config = devm_kcalloc(dev, n: ts_num + 1, |
836 | size: sizeof(*temp_config), GFP_KERNEL); |
837 | if (!temp_config) |
838 | return -ENOMEM; |
839 | |
840 | memset32(s: temp_config, HWMON_T_INPUT, n: ts_num); |
841 | pvt_temp.config = temp_config; |
842 | pvt_info[index++] = &pvt_temp; |
843 | |
844 | pvt_ts_dbgfs_create(pvt, dev); |
845 | } |
846 | |
847 | if (pd_num) { |
848 | ret = pvt_get_regmap(pdev, reg_name: "pd" , pvt); |
849 | if (ret) |
850 | return ret; |
851 | } |
852 | |
853 | if (vm_num) { |
854 | u8 vm_idx[VM_NUM_MAX]; |
855 | |
856 | ret = pvt_get_regmap(pdev, reg_name: "vm" , pvt); |
857 | if (ret) |
858 | return ret; |
859 | |
860 | ret = device_property_read_u8_array(dev, propname: "intel,vm-map" , val: vm_idx, |
861 | nval: vm_num); |
862 | if (ret) { |
863 | /* |
864 | * Incase intel,vm-map property is not defined, we |
865 | * assume incremental channel numbers. |
866 | */ |
867 | for (i = 0; i < vm_num; i++) |
868 | vm_idx[i] = i; |
869 | } else { |
870 | for (i = 0; i < vm_num; i++) |
871 | if (vm_idx[i] >= vm_num || vm_idx[i] == 0xff) { |
872 | pvt->v_num = i; |
873 | vm_num = i; |
874 | break; |
875 | } |
876 | } |
877 | |
878 | ret = pvt_get_active_channel(dev, pvt, vm_num, ch_num, vm_idx); |
879 | if (ret) |
880 | return ret; |
881 | |
882 | ret = pvt_get_pre_scaler(dev, pvt); |
883 | if (ret) |
884 | return ret; |
885 | |
886 | in_config = devm_kcalloc(dev, n: pvt->vm_channels.total + 1, |
887 | size: sizeof(*in_config), GFP_KERNEL); |
888 | if (!in_config) |
889 | return -ENOMEM; |
890 | |
891 | memset32(s: in_config, HWMON_I_INPUT, n: pvt->vm_channels.total); |
892 | in_config[pvt->vm_channels.total] = 0; |
893 | pvt_in.config = in_config; |
894 | |
895 | pvt_info[index++] = &pvt_in; |
896 | } |
897 | |
898 | ret = pvt_init(pvt); |
899 | if (ret) { |
900 | dev_err(dev, "failed to init pvt: %d\n" , ret); |
901 | return ret; |
902 | } |
903 | |
904 | pvt_chip_info.info = pvt_info; |
905 | hwmon_dev = devm_hwmon_device_register_with_info(dev, name: "pvt" , |
906 | drvdata: pvt, |
907 | info: &pvt_chip_info, |
908 | NULL); |
909 | |
910 | return PTR_ERR_OR_ZERO(ptr: hwmon_dev); |
911 | } |
912 | |
913 | static const struct of_device_id moortec_pvt_of_match[] = { |
914 | { .compatible = "moortec,mr75203" }, |
915 | { } |
916 | }; |
917 | MODULE_DEVICE_TABLE(of, moortec_pvt_of_match); |
918 | |
919 | static struct platform_driver moortec_pvt_driver = { |
920 | .driver = { |
921 | .name = "moortec-pvt" , |
922 | .of_match_table = moortec_pvt_of_match, |
923 | }, |
924 | .probe = mr75203_probe, |
925 | }; |
926 | module_platform_driver(moortec_pvt_driver); |
927 | |
928 | MODULE_LICENSE("GPL v2" ); |
929 | |