1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* iio/adc/max1363.c
4	* Copyright (C) 2008-2010 Jonathan Cameron
5	*
6	* based on linux/drivers/i2c/chips/max123x
7	* Copyright (C) 2002-2004 Stefan Eletzhofer
8	*
9	* based on linux/drivers/acron/char/pcf8583.c
10	* Copyright (C) 2000 Russell King
11	*
12	* Driver for max1363 and similar chips.
13	*/
14
15	#include <linux/interrupt.h>
16	#include <linux/device.h>
17	#include <linux/kernel.h>
18	#include <linux/sysfs.h>
19	#include <linux/list.h>
20	#include <linux/i2c.h>
21	#include <linux/regulator/consumer.h>
22	#include <linux/slab.h>
23	#include <linux/err.h>
24	#include <linux/module.h>
25	#include <linux/mod_devicetable.h>
26	#include <linux/property.h>
27
28	#include <linux/iio/iio.h>
29	#include <linux/iio/sysfs.h>
30	#include <linux/iio/events.h>
31	#include <linux/iio/buffer.h>
32	#include <linux/iio/kfifo_buf.h>
33	#include <linux/iio/trigger_consumer.h>
34	#include <linux/iio/triggered_buffer.h>
35
36	#define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
37
38	/* There is a fair bit more defined here than currently
39	* used, but the intention is to support everything these
40	* chips do in the long run */
41
42	/* see data sheets */
43	/* max1363 and max1236, max1237, max1238, max1239 */
44	#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00
45	#define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20
46	#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40
47	#define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60
48	#define MAX1363_SETUP_POWER_UP_INT_REF 0x10
49	#define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00
50
51	/* think about including max11600 etc - more settings */
52	#define MAX1363_SETUP_EXT_CLOCK 0x08
53	#define MAX1363_SETUP_INT_CLOCK 0x00
54	#define MAX1363_SETUP_UNIPOLAR 0x00
55	#define MAX1363_SETUP_BIPOLAR 0x04
56	#define MAX1363_SETUP_RESET 0x00
57	#define MAX1363_SETUP_NORESET 0x02
58	/* max1363 only - though don't care on others.
59	* For now monitor modes are not implemented as the relevant
60	* line is not connected on my test board.
61	* The definitions are here as I intend to add this soon.
62	*/
63	#define MAX1363_SETUP_MONITOR_SETUP 0x01
64
65	/* Specific to the max1363 */
66	#define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
67	#define MAX1363_MON_INT_ENABLE 0x01
68
69	/* defined for readability reasons */
70	/* All chips */
71	#define MAX1363_CONFIG_BYTE(a) ((a))
72
73	#define MAX1363_CONFIG_SE 0x01
74	#define MAX1363_CONFIG_DE 0x00
75	#define MAX1363_CONFIG_SCAN_TO_CS 0x00
76	#define MAX1363_CONFIG_SCAN_SINGLE_8 0x20
77	#define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40
78	#define MAX1363_CONFIG_SCAN_SINGLE_1 0x60
79	/* max123{6-9} only */
80	#define MAX1236_SCAN_MID_TO_CHANNEL 0x40
81
82	/* max1363 only - merely part of channel selects or don't care for others */
83	#define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
84
85	#define MAX1363_CHANNEL_SEL(a) ((a) << 1)
86
87	/* max1363 strictly 0x06 - but doesn't matter */
88	#define MAX1363_CHANNEL_SEL_MASK 0x1E
89	#define MAX1363_SCAN_MASK 0x60
90	#define MAX1363_SE_DE_MASK 0x01
91
92	#define MAX1363_MAX_CHANNELS 25
93	/**
94	* struct max1363_mode - scan mode information
95	* @conf: The corresponding value of the configuration register
96	* @modemask: Bit mask corresponding to channels enabled in this mode
97	*/
98	struct max1363_mode {
99	int8_t conf;
100	DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
101	};
102
103	/* This must be maintained along side the max1363_mode_table in max1363_core */
104	enum max1363_modes {
105	/* Single read of a single channel */
106	_s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
107	/* Differential single read */
108	d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
109	d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
110	/* Scan to channel and mid to channel where overlapping */
111	s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
112	s6to7, s0to7, s6to8, s0to8, s6to9,
113	s0to9, s6to10, s0to10, s6to11, s0to11,
114	/* Differential scan to channel and mid to channel where overlapping */
115	d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
116	d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
117	d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
118	d7m6to11m10, d1m0to11m10,
119	};
120
121	/**
122	* struct max1363_chip_info - chip specifc information
123	* @info: iio core function callbacks structure
124	* @channels: channel specification
125	* @num_channels: number of channels
126	* @mode_list: array of available scan modes
127	* @default_mode: the scan mode in which the chip starts up
128	* @int_vref_mv: the internal reference voltage
129	* @num_modes: number of modes
130	* @bits: accuracy of the adc in bits
131	*/
132	struct max1363_chip_info {
133	const struct iio_info *info;
134	const struct iio_chan_spec *channels;
135	int num_channels;
136	const enum max1363_modes *mode_list;
137	enum max1363_modes default_mode;
138	u16 int_vref_mv;
139	u8 num_modes;
140	u8 bits;
141	};
142
143	/**
144	* struct max1363_state - driver instance specific data
145	* @client: i2c_client
146	* @setupbyte: cache of current device setup byte
147	* @configbyte: cache of current device config byte
148	* @chip_info: chip model specific constants, available modes, etc.
149	* @current_mode: the scan mode of this chip
150	* @requestedmask: a valid requested set of channels
151	* @lock: lock to ensure state is consistent
152	* @monitor_on: whether monitor mode is enabled
153	* @monitor_speed: parameter corresponding to device monitor speed setting
154	* @mask_high: bitmask for enabled high thresholds
155	* @mask_low: bitmask for enabled low thresholds
156	* @thresh_high: high threshold values
157	* @thresh_low: low threshold values
158	* @vref: Reference voltage regulator
159	* @vref_uv: Actual (external or internal) reference voltage
160	* @send: function used to send data to the chip
161	* @recv: function used to receive data from the chip
162	*/
163	struct max1363_state {
164	struct i2c_client *client;
165	u8 setupbyte;
166	u8 configbyte;
167	const struct max1363_chip_info *chip_info;
168	const struct max1363_mode *current_mode;
169	u32 requestedmask;
170	struct mutex lock;
171
172	/* Using monitor modes and buffer at the same time is
173	currently not supported */
174	bool monitor_on;
175	unsigned int monitor_speed:3;
176	u8 mask_high;
177	u8 mask_low;
178	/* 4x unipolar first then the fours bipolar ones */
179	s16 thresh_high[8];
180	s16 thresh_low[8];
181	struct regulator *vref;
182	u32 vref_uv;
183	int (*send)(const struct i2c_client *client,
184	const char *buf, int count);
185	int (*recv)(const struct i2c_client *client,
186	char *buf, int count);
187	};
188
189	#define MAX1363_MODE_SINGLE(_num, _mask) { \
190	.conf = MAX1363_CHANNEL_SEL(_num) \
191	| MAX1363_CONFIG_SCAN_SINGLE_1 \
192	| MAX1363_CONFIG_SE, \
193	.modemask[0] = _mask, \
194	}
195
196	#define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
197	.conf = MAX1363_CHANNEL_SEL(_num) \
198	| MAX1363_CONFIG_SCAN_TO_CS \
199	| MAX1363_CONFIG_SE, \
200	.modemask[0] = _mask, \
201	}
202
203	/* note not available for max1363 hence naming */
204	#define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
205	.conf = MAX1363_CHANNEL_SEL(_num) \
206	| MAX1236_SCAN_MID_TO_CHANNEL \
207	| MAX1363_CONFIG_SE, \
208	.modemask[0] = _mask \
209	}
210
211	#define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
212	.conf = MAX1363_CHANNEL_SEL(_nump) \
213	| MAX1363_CONFIG_SCAN_SINGLE_1 \
214	| MAX1363_CONFIG_DE, \
215	.modemask[0] = _mask \
216	}
217
218	/* Can't think how to automate naming so specify for now */
219	#define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
220	.conf = MAX1363_CHANNEL_SEL(_num) \
221	| MAX1363_CONFIG_SCAN_TO_CS \
222	| MAX1363_CONFIG_DE, \
223	.modemask[0] = _mask \
224	}
225
226	/* note only available for max1363 hence naming */
227	#define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
228	.conf = MAX1363_CHANNEL_SEL(_num) \
229	| MAX1236_SCAN_MID_TO_CHANNEL \
230	| MAX1363_CONFIG_SE, \
231	.modemask[0] = _mask \
232	}
233
234	static const struct max1363_mode max1363_mode_table[] = {
235	/* All of the single channel options first */
236	MAX1363_MODE_SINGLE(0, 1 << 0),
237	MAX1363_MODE_SINGLE(1, 1 << 1),
238	MAX1363_MODE_SINGLE(2, 1 << 2),
239	MAX1363_MODE_SINGLE(3, 1 << 3),
240	MAX1363_MODE_SINGLE(4, 1 << 4),
241	MAX1363_MODE_SINGLE(5, 1 << 5),
242	MAX1363_MODE_SINGLE(6, 1 << 6),
243	MAX1363_MODE_SINGLE(7, 1 << 7),
244	MAX1363_MODE_SINGLE(8, 1 << 8),
245	MAX1363_MODE_SINGLE(9, 1 << 9),
246	MAX1363_MODE_SINGLE(10, 1 << 10),
247	MAX1363_MODE_SINGLE(11, 1 << 11),
248
249	MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
250	MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
251	MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
252	MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
253	MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
254	MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
255	MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
256	MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
257	MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
258	MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
259	MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
260	MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
261
262	/* The multichannel scans next */
263	MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
264	MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
265	MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
266	MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
267	MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
268	MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
269	MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
270	MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
271	MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
272	MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
273	MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
274	MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
275	MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
276	MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
277	MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
278	MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
279	MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
280
281	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
282	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
283	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
284	MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
285	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
286	MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
287	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
288	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
289	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
290	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
291	MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
292	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
293	MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
294	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
295	};
296
297	static const struct max1363_mode
298	*max1363_match_mode(const unsigned long *mask,
299	const struct max1363_chip_info *ci)
300	{
301	int i;
302	if (mask)
303	for (i = 0; i < ci->num_modes; i++)
304	if (bitmap_subset(src1: mask,
305	src2: max1363_mode_table[ci->mode_list[i]].
306	modemask,
307	MAX1363_MAX_CHANNELS))
308	return &max1363_mode_table[ci->mode_list[i]];
309	return NULL;
310	}
311
312	static int max1363_smbus_send(const struct i2c_client *client, const char *buf,
313	int count)
314	{
315	int i, err;
316
317	for (i = err = 0; err == 0 && i < count; ++i)
318	err = i2c_smbus_write_byte(client, value: buf[i]);
319
320	return err ? err : count;
321	}
322
323	static int max1363_smbus_recv(const struct i2c_client *client, char *buf,
324	int count)
325	{
326	int i, ret;
327
328	for (i = 0; i < count; ++i) {
329	ret = i2c_smbus_read_byte(client);
330	if (ret < 0)
331	return ret;
332	buf[i] = ret;
333	}
334
335	return count;
336	}
337
338	static int max1363_write_basic_config(struct max1363_state *st)
339	{
340	u8 tx_buf[2] = { st->setupbyte, st->configbyte };
341
342	return st->send(st->client, tx_buf, 2);
343	}
344
345	static int max1363_set_scan_mode(struct max1363_state *st)
346	{
347	st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
348	| MAX1363_SCAN_MASK
349	| MAX1363_SE_DE_MASK);
350	st->configbyte |= st->current_mode->conf;
351
352	return max1363_write_basic_config(st);
353	}
354
355	static int max1363_read_single_chan(struct iio_dev *indio_dev,
356	struct iio_chan_spec const *chan,
357	int *val,
358	long m)
359	{
360	iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
361	s32 data;
362	u8 rxbuf[2];
363	struct max1363_state *st = iio_priv(indio_dev);
364	struct i2c_client *client = st->client;
365
366	guard(mutex)(T: &st->lock);
367
368	/*
369	* If monitor mode is enabled, the method for reading a single
370	* channel will have to be rather different and has not yet
371	* been implemented.
372	*
373	* Also, cannot read directly if buffered capture enabled.
374	*/
375	if (st->monitor_on)
376	return -EBUSY;
377
378	/* Check to see if current scan mode is correct */
379	if (st->current_mode != &max1363_mode_table[chan->address]) {
380	int ret;
381
382	/* Update scan mode if needed */
383	st->current_mode = &max1363_mode_table[chan->address];
384	ret = max1363_set_scan_mode(st);
385	if (ret < 0)
386	return ret;
387	}
388	if (st->chip_info->bits != 8) {
389	/* Get reading */
390	data = st->recv(client, rxbuf, 2);
391	if (data < 0)
392	return data;
393
394	data = (rxbuf[1] | rxbuf[0] << 8) &
395	((1 << st->chip_info->bits) - 1);
396	} else {
397	/* Get reading */
398	data = st->recv(client, rxbuf, 1);
399	if (data < 0)
400	return data;
401
402	data = rxbuf[0];
403	}
404	*val = data;
405
406	return 0;
407	}
408	unreachable();
409	}
410
411	static int max1363_read_raw(struct iio_dev *indio_dev,
412	struct iio_chan_spec const *chan,
413	int *val,
414	int *val2,
415	long m)
416	{
417	struct max1363_state *st = iio_priv(indio_dev);
418	int ret;
419
420	switch (m) {
421	case IIO_CHAN_INFO_RAW:
422	ret = max1363_read_single_chan(indio_dev, chan, val, m);
423	if (ret < 0)
424	return ret;
425	return IIO_VAL_INT;
426	case IIO_CHAN_INFO_SCALE:
427	*val = st->vref_uv / 1000;
428	*val2 = st->chip_info->bits;
429	return IIO_VAL_FRACTIONAL_LOG2;
430	default:
431	return -EINVAL;
432	}
433	return 0;
434	}
435
436	/* Applies to max1363 */
437	static const enum max1363_modes max1363_mode_list[] = {
438	_s0, _s1, _s2, _s3,
439	s0to1, s0to2, s0to3,
440	d0m1, d2m3, d1m0, d3m2,
441	d0m1to2m3, d1m0to3m2,
442	};
443
444	static const struct iio_event_spec max1363_events[] = {
445	{
446	.type = IIO_EV_TYPE_THRESH,
447	.dir = IIO_EV_DIR_RISING,
448	.mask_separate = BIT(IIO_EV_INFO_VALUE) |
449	BIT(IIO_EV_INFO_ENABLE),
450	}, {
451	.type = IIO_EV_TYPE_THRESH,
452	.dir = IIO_EV_DIR_FALLING,
453	.mask_separate = BIT(IIO_EV_INFO_VALUE) |
454	BIT(IIO_EV_INFO_ENABLE),
455	},
456	};
457
458	#define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \
459	{ \
460	.type = IIO_VOLTAGE, \
461	.indexed = 1, \
462	.channel = num, \
463	.address = addr, \
464	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
465	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
466	.datasheet_name = "AIN"#num, \
467	.scan_type = { \
468	.sign = 'u', \
469	.realbits = bits, \
470	.storagebits = (bits > 8) ? 16 : 8, \
471	.endianness = IIO_BE, \
472	}, \
473	.scan_index = si, \
474	.event_spec = ev_spec, \
475	.num_event_specs = num_ev_spec, \
476	}
477
478	/* bipolar channel */
479	#define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \
480	{ \
481	.type = IIO_VOLTAGE, \
482	.differential = 1, \
483	.indexed = 1, \
484	.channel = num, \
485	.channel2 = num2, \
486	.address = addr, \
487	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
488	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
489	.datasheet_name = "AIN"#num"-AIN"#num2, \
490	.scan_type = { \
491	.sign = 's', \
492	.realbits = bits, \
493	.storagebits = (bits > 8) ? 16 : 8, \
494	.endianness = IIO_BE, \
495	}, \
496	.scan_index = si, \
497	.event_spec = ev_spec, \
498	.num_event_specs = num_ev_spec, \
499	}
500
501	#define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \
502	MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \
503	MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \
504	MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \
505	MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \
506	MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec), \
507	MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec), \
508	MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec), \
509	MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec), \
510	IIO_CHAN_SOFT_TIMESTAMP(8) \
511	}
512
513	static const struct iio_chan_spec max1036_channels[] =
514	MAX1363_4X_CHANS(8, NULL, 0);
515	static const struct iio_chan_spec max1136_channels[] =
516	MAX1363_4X_CHANS(10, NULL, 0);
517	static const struct iio_chan_spec max1236_channels[] =
518	MAX1363_4X_CHANS(12, NULL, 0);
519	static const struct iio_chan_spec max1361_channels[] =
520	MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events));
521	static const struct iio_chan_spec max1363_channels[] =
522	MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events));
523
524	/* Applies to max1236, max1237 */
525	static const enum max1363_modes max1236_mode_list[] = {
526	_s0, _s1, _s2, _s3,
527	s0to1, s0to2, s0to3,
528	d0m1, d2m3, d1m0, d3m2,
529	d0m1to2m3, d1m0to3m2,
530	s2to3,
531	};
532
533	/* Applies to max1238, max1239 */
534	static const enum max1363_modes max1238_mode_list[] = {
535	_s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
536	s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
537	s0to7, s0to8, s0to9, s0to10, s0to11,
538	d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
539	d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
540	d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
541	d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
542	s6to7, s6to8, s6to9, s6to10, s6to11,
543	d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
544	};
545
546	#define MAX1363_12X_CHANS(bits) { \
547	MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
548	MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
549	MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
550	MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
551	MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
552	MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
553	MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
554	MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
555	MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \
556	MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \
557	MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \
558	MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \
559	MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \
560	MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \
561	MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \
562	MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \
563	MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \
564	MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \
565	MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \
566	MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \
567	MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \
568	MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \
569	MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \
570	MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \
571	IIO_CHAN_SOFT_TIMESTAMP(24) \
572	}
573	static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
574	static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
575	static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
576
577	static const enum max1363_modes max11607_mode_list[] = {
578	_s0, _s1, _s2, _s3,
579	s0to1, s0to2, s0to3,
580	s2to3,
581	d0m1, d2m3, d1m0, d3m2,
582	d0m1to2m3, d1m0to3m2,
583	};
584
585	static const enum max1363_modes max11608_mode_list[] = {
586	_s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
587	s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
588	s6to7,
589	d0m1, d2m3, d4m5, d6m7,
590	d1m0, d3m2, d5m4, d7m6,
591	d0m1to2m3, d0m1to4m5, d0m1to6m7,
592	d1m0to3m2, d1m0to5m4, d1m0to7m6,
593	};
594
595	#define MAX1363_8X_CHANS(bits) { \
596	MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
597	MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
598	MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
599	MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
600	MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
601	MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
602	MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
603	MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
604	MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0), \
605	MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0), \
606	MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0), \
607	MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0), \
608	MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0), \
609	MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0), \
610	MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0), \
611	MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0), \
612	IIO_CHAN_SOFT_TIMESTAMP(16) \
613	}
614	static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
615	static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
616	static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
617
618	static const enum max1363_modes max11644_mode_list[] = {
619	_s0, _s1, s0to1, d0m1, d1m0,
620	};
621
622	#define MAX1363_2X_CHANS(bits) { \
623	MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
624	MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
625	MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \
626	MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \
627	IIO_CHAN_SOFT_TIMESTAMP(4) \
628	}
629
630	static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
631	static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
632
633	enum { max1361,
634	max1362,
635	max1363,
636	max1364,
637	max1036,
638	max1037,
639	max1038,
640	max1039,
641	max1136,
642	max1137,
643	max1138,
644	max1139,
645	max1236,
646	max1237,
647	max1238,
648	max1239,
649	max11600,
650	max11601,
651	max11602,
652	max11603,
653	max11604,
654	max11605,
655	max11606,
656	max11607,
657	max11608,
658	max11609,
659	max11610,
660	max11611,
661	max11612,
662	max11613,
663	max11614,
664	max11615,
665	max11616,
666	max11617,
667	max11644,
668	max11645,
669	max11646,
670	max11647
671	};
672
673	static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
674	8300, 4200, 2000, 1000 };
675
676	static ssize_t max1363_monitor_show_freq(struct device *dev,
677	struct device_attribute *attr,
678	char *buf)
679	{
680	struct max1363_state *st = iio_priv(indio_dev: dev_to_iio_dev(dev));
681	return sprintf(buf, fmt: "%d\n", max1363_monitor_speeds[st->monitor_speed]);
682	}
683
684	static ssize_t max1363_monitor_store_freq(struct device *dev,
685	struct device_attribute *attr,
686	const char *buf,
687	size_t len)
688	{
689	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
690	struct max1363_state *st = iio_priv(indio_dev);
691	int i, ret;
692	unsigned long val;
693	bool found = false;
694
695	ret = kstrtoul(s: buf, base: 10, res: &val);
696	if (ret)
697	return -EINVAL;
698	for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
699	if (val == max1363_monitor_speeds[i]) {
700	found = true;
701	break;
702	}
703	if (!found)
704	return -EINVAL;
705
706	scoped_guard(mutex, &st->lock)
707	st->monitor_speed = i;
708
709	return 0;
710	}
711
712	static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
713	max1363_monitor_show_freq,
714	max1363_monitor_store_freq);
715
716	static IIO_CONST_ATTR(sampling_frequency_available,
717	"133000 665000 33300 16600 8300 4200 2000 1000");
718
719	static int max1363_read_thresh(struct iio_dev *indio_dev,
720	const struct iio_chan_spec *chan, enum iio_event_type type,
721	enum iio_event_direction dir, enum iio_event_info info, int *val,
722	int *val2)
723	{
724	struct max1363_state *st = iio_priv(indio_dev);
725	if (dir == IIO_EV_DIR_FALLING)
726	*val = st->thresh_low[chan->channel];
727	else
728	*val = st->thresh_high[chan->channel];
729	return IIO_VAL_INT;
730	}
731
732	static int max1363_write_thresh(struct iio_dev *indio_dev,
733	const struct iio_chan_spec *chan, enum iio_event_type type,
734	enum iio_event_direction dir, enum iio_event_info info, int val,
735	int val2)
736	{
737	struct max1363_state *st = iio_priv(indio_dev);
738	/* make it handle signed correctly as well */
739	switch (st->chip_info->bits) {
740	case 10:
741	if (val > 0x3FF)
742	return -EINVAL;
743	break;
744	case 12:
745	if (val > 0xFFF)
746	return -EINVAL;
747	break;
748	}
749
750	switch (dir) {
751	case IIO_EV_DIR_FALLING:
752	st->thresh_low[chan->channel] = val;
753	break;
754	case IIO_EV_DIR_RISING:
755	st->thresh_high[chan->channel] = val;
756	break;
757	default:
758	return -EINVAL;
759	}
760
761	return 0;
762	}
763
764	static const u64 max1363_event_codes[] = {
765	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
766	IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
767	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
768	IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
769	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
770	IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
771	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
772	IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
773	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
774	IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
775	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
776	IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
777	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
778	IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
779	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
780	IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
781	};
782
783	static irqreturn_t max1363_event_handler(int irq, void *private)
784	{
785	struct iio_dev *indio_dev = private;
786	struct max1363_state *st = iio_priv(indio_dev);
787	s64 timestamp = iio_get_time_ns(indio_dev);
788	unsigned long mask, loc;
789	u8 rx;
790	u8 tx[2] = { st->setupbyte,
791	MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
792
793	st->recv(st->client, &rx, 1);
794	mask = rx;
795	for_each_set_bit(loc, &mask, 8)
796	iio_push_event(indio_dev, ev_code: max1363_event_codes[loc], timestamp);
797	st->send(st->client, tx, 2);
798
799	return IRQ_HANDLED;
800	}
801
802	static int max1363_read_event_config(struct iio_dev *indio_dev,
803	const struct iio_chan_spec *chan, enum iio_event_type type,
804	enum iio_event_direction dir)
805	{
806	struct max1363_state *st = iio_priv(indio_dev);
807	int val;
808	int number = chan->channel;
809
810	guard(mutex)(T: &st->lock);
811	if (dir == IIO_EV_DIR_FALLING)
812	val = (1 << number) & st->mask_low;
813	else
814	val = (1 << number) & st->mask_high;
815
816	return val;
817	}
818
819	static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
820	{
821	u8 *tx_buf;
822	int ret, i = 3, j;
823	unsigned long numelements;
824	int len;
825	const long *modemask;
826
827	if (!enabled) {
828	/* transition to buffered capture is not currently supported */
829	st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
830	st->configbyte &= ~MAX1363_SCAN_MASK;
831	st->monitor_on = false;
832	return max1363_write_basic_config(st);
833	}
834
835	/* Ensure we are in the relevant mode */
836	st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
837	st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
838	| MAX1363_SCAN_MASK
839	| MAX1363_SE_DE_MASK);
840	st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
841	if ((st->mask_low | st->mask_high) & 0x0F) {
842	st->configbyte |= max1363_mode_table[s0to3].conf;
843	modemask = max1363_mode_table[s0to3].modemask;
844	} else if ((st->mask_low | st->mask_high) & 0x30) {
845	st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
846	modemask = max1363_mode_table[d0m1to2m3].modemask;
847	} else {
848	st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
849	modemask = max1363_mode_table[d1m0to3m2].modemask;
850	}
851	numelements = bitmap_weight(src: modemask, MAX1363_MAX_CHANNELS);
852	len = 3 * numelements + 3;
853	tx_buf = kmalloc(size: len, GFP_KERNEL);
854	if (!tx_buf) {
855	ret = -ENOMEM;
856	goto error_ret;
857	}
858	tx_buf[0] = st->configbyte;
859	tx_buf[1] = st->setupbyte;
860	tx_buf[2] = (st->monitor_speed << 1);
861
862	/*
863	* So we need to do yet another bit of nefarious scan mode
864	* setup to match what we need.
865	*/
866	for (j = 0; j < 8; j++)
867	if (test_bit(j, modemask)) {
868	/* Establish the mode is in the scan */
869	if (st->mask_low & (1 << j)) {
870	tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
871	tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
872	} else if (j < 4) {
873	tx_buf[i] = 0;
874	tx_buf[i + 1] = 0;
875	} else {
876	tx_buf[i] = 0x80;
877	tx_buf[i + 1] = 0;
878	}
879	if (st->mask_high & (1 << j)) {
880	tx_buf[i + 1] |=
881	(st->thresh_high[j] >> 8) & 0x0F;
882	tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
883	} else if (j < 4) {
884	tx_buf[i + 1] |= 0x0F;
885	tx_buf[i + 2] = 0xFF;
886	} else {
887	tx_buf[i + 1] |= 0x07;
888	tx_buf[i + 2] = 0xFF;
889	}
890	i += 3;
891	}
892
893
894	ret = st->send(st->client, tx_buf, len);
895	if (ret < 0)
896	goto error_ret;
897	if (ret != len) {
898	ret = -EIO;
899	goto error_ret;
900	}
901
902	/*
903	* Now that we hopefully have sensible thresholds in place it is
904	* time to turn the interrupts on.
905	* It is unclear from the data sheet if this should be necessary
906	* (i.e. whether monitor mode setup is atomic) but it appears to
907	* be in practice.
908	*/
909	tx_buf[0] = st->setupbyte;
910	tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
911	ret = st->send(st->client, tx_buf, 2);
912	if (ret < 0)
913	goto error_ret;
914	if (ret != 2) {
915	ret = -EIO;
916	goto error_ret;
917	}
918	ret = 0;
919	st->monitor_on = true;
920	error_ret:
921
922	kfree(objp: tx_buf);
923
924	return ret;
925	}
926
927	/*
928	* To keep this manageable we always use one of 3 scan modes.
929	* Scan 0...3, 0-1,2-3 and 1-0,3-2
930	*/
931
932	static inline int __max1363_check_event_mask(int thismask, int checkmask)
933	{
934	int ret = 0;
935	/* Is it unipolar */
936	if (thismask < 4) {
937	if (checkmask & ~0x0F) {
938	ret = -EBUSY;
939	goto error_ret;
940	}
941	} else if (thismask < 6) {
942	if (checkmask & ~0x30) {
943	ret = -EBUSY;
944	goto error_ret;
945	}
946	} else if (checkmask & ~0xC0)
947	ret = -EBUSY;
948	error_ret:
949	return ret;
950	}
951
952	static int max1363_write_event_config(struct iio_dev *indio_dev,
953	const struct iio_chan_spec *chan, enum iio_event_type type,
954	enum iio_event_direction dir, int state)
955	{
956	struct max1363_state *st = iio_priv(indio_dev);
957
958	iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
959	int number = chan->channel;
960	u16 unifiedmask;
961	int ret;
962
963	guard(mutex)(T: &st->lock);
964
965	unifiedmask = st->mask_low | st->mask_high;
966	if (dir == IIO_EV_DIR_FALLING) {
967
968	if (state == 0)
969	st->mask_low &= ~(1 << number);
970	else {
971	ret = __max1363_check_event_mask(thismask: (1 << number),
972	checkmask: unifiedmask);
973	if (ret)
974	return ret;
975	st->mask_low |= (1 << number);
976	}
977	} else {
978	if (state == 0)
979	st->mask_high &= ~(1 << number);
980	else {
981	ret = __max1363_check_event_mask(thismask: (1 << number),
982	checkmask: unifiedmask);
983	if (ret)
984	return ret;
985	st->mask_high |= (1 << number);
986	}
987	}
988	}
989	max1363_monitor_mode_update(st, enabled: !!(st->mask_high | st->mask_low));
990
991	return 0;
992	}
993
994	/*
995	* As with scan_elements, only certain sets of these can
996	* be combined.
997	*/
998	static struct attribute *max1363_event_attributes[] = {
999	&iio_dev_attr_sampling_frequency.dev_attr.attr,
1000	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
1001	NULL,
1002	};
1003
1004	static const struct attribute_group max1363_event_attribute_group = {
1005	.attrs = max1363_event_attributes,
1006	};
1007
1008	static int max1363_update_scan_mode(struct iio_dev *indio_dev,
1009	const unsigned long *scan_mask)
1010	{
1011	struct max1363_state *st = iio_priv(indio_dev);
1012
1013	/*
1014	* Need to figure out the current mode based upon the requested
1015	* scan mask in iio_dev
1016	*/
1017	st->current_mode = max1363_match_mode(mask: scan_mask, ci: st->chip_info);
1018	if (!st->current_mode)
1019	return -EINVAL;
1020	max1363_set_scan_mode(st);
1021	return 0;
1022	}
1023
1024	static const struct iio_info max1238_info = {
1025	.read_raw = &max1363_read_raw,
1026	.update_scan_mode = &max1363_update_scan_mode,
1027	};
1028
1029	static const struct iio_info max1363_info = {
1030	.read_event_value = &max1363_read_thresh,
1031	.write_event_value = &max1363_write_thresh,
1032	.read_event_config = &max1363_read_event_config,
1033	.write_event_config = &max1363_write_event_config,
1034	.read_raw = &max1363_read_raw,
1035	.update_scan_mode = &max1363_update_scan_mode,
1036	.event_attrs = &max1363_event_attribute_group,
1037	};
1038
1039	/* max1363 and max1368 tested - rest from data sheet */
1040	static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1041	[max1361] = {
1042	.bits = 10,
1043	.int_vref_mv = 2048,
1044	.mode_list = max1363_mode_list,
1045	.num_modes = ARRAY_SIZE(max1363_mode_list),
1046	.default_mode = s0to3,
1047	.channels = max1361_channels,
1048	.num_channels = ARRAY_SIZE(max1361_channels),
1049	.info = &max1363_info,
1050	},
1051	[max1362] = {
1052	.bits = 10,
1053	.int_vref_mv = 4096,
1054	.mode_list = max1363_mode_list,
1055	.num_modes = ARRAY_SIZE(max1363_mode_list),
1056	.default_mode = s0to3,
1057	.channels = max1361_channels,
1058	.num_channels = ARRAY_SIZE(max1361_channels),
1059	.info = &max1363_info,
1060	},
1061	[max1363] = {
1062	.bits = 12,
1063	.int_vref_mv = 2048,
1064	.mode_list = max1363_mode_list,
1065	.num_modes = ARRAY_SIZE(max1363_mode_list),
1066	.default_mode = s0to3,
1067	.channels = max1363_channels,
1068	.num_channels = ARRAY_SIZE(max1363_channels),
1069	.info = &max1363_info,
1070	},
1071	[max1364] = {
1072	.bits = 12,
1073	.int_vref_mv = 4096,
1074	.mode_list = max1363_mode_list,
1075	.num_modes = ARRAY_SIZE(max1363_mode_list),
1076	.default_mode = s0to3,
1077	.channels = max1363_channels,
1078	.num_channels = ARRAY_SIZE(max1363_channels),
1079	.info = &max1363_info,
1080	},
1081	[max1036] = {
1082	.bits = 8,
1083	.int_vref_mv = 4096,
1084	.mode_list = max1236_mode_list,
1085	.num_modes = ARRAY_SIZE(max1236_mode_list),
1086	.default_mode = s0to3,
1087	.info = &max1238_info,
1088	.channels = max1036_channels,
1089	.num_channels = ARRAY_SIZE(max1036_channels),
1090	},
1091	[max1037] = {
1092	.bits = 8,
1093	.int_vref_mv = 2048,
1094	.mode_list = max1236_mode_list,
1095	.num_modes = ARRAY_SIZE(max1236_mode_list),
1096	.default_mode = s0to3,
1097	.info = &max1238_info,
1098	.channels = max1036_channels,
1099	.num_channels = ARRAY_SIZE(max1036_channels),
1100	},
1101	[max1038] = {
1102	.bits = 8,
1103	.int_vref_mv = 4096,
1104	.mode_list = max1238_mode_list,
1105	.num_modes = ARRAY_SIZE(max1238_mode_list),
1106	.default_mode = s0to11,
1107	.info = &max1238_info,
1108	.channels = max1038_channels,
1109	.num_channels = ARRAY_SIZE(max1038_channels),
1110	},
1111	[max1039] = {
1112	.bits = 8,
1113	.int_vref_mv = 2048,
1114	.mode_list = max1238_mode_list,
1115	.num_modes = ARRAY_SIZE(max1238_mode_list),
1116	.default_mode = s0to11,
1117	.info = &max1238_info,
1118	.channels = max1038_channels,
1119	.num_channels = ARRAY_SIZE(max1038_channels),
1120	},
1121	[max1136] = {
1122	.bits = 10,
1123	.int_vref_mv = 4096,
1124	.mode_list = max1236_mode_list,
1125	.num_modes = ARRAY_SIZE(max1236_mode_list),
1126	.default_mode = s0to3,
1127	.info = &max1238_info,
1128	.channels = max1136_channels,
1129	.num_channels = ARRAY_SIZE(max1136_channels),
1130	},
1131	[max1137] = {
1132	.bits = 10,
1133	.int_vref_mv = 2048,
1134	.mode_list = max1236_mode_list,
1135	.num_modes = ARRAY_SIZE(max1236_mode_list),
1136	.default_mode = s0to3,
1137	.info = &max1238_info,
1138	.channels = max1136_channels,
1139	.num_channels = ARRAY_SIZE(max1136_channels),
1140	},
1141	[max1138] = {
1142	.bits = 10,
1143	.int_vref_mv = 4096,
1144	.mode_list = max1238_mode_list,
1145	.num_modes = ARRAY_SIZE(max1238_mode_list),
1146	.default_mode = s0to11,
1147	.info = &max1238_info,
1148	.channels = max1138_channels,
1149	.num_channels = ARRAY_SIZE(max1138_channels),
1150	},
1151	[max1139] = {
1152	.bits = 10,
1153	.int_vref_mv = 2048,
1154	.mode_list = max1238_mode_list,
1155	.num_modes = ARRAY_SIZE(max1238_mode_list),
1156	.default_mode = s0to11,
1157	.info = &max1238_info,
1158	.channels = max1138_channels,
1159	.num_channels = ARRAY_SIZE(max1138_channels),
1160	},
1161	[max1236] = {
1162	.bits = 12,
1163	.int_vref_mv = 4096,
1164	.mode_list = max1236_mode_list,
1165	.num_modes = ARRAY_SIZE(max1236_mode_list),
1166	.default_mode = s0to3,
1167	.info = &max1238_info,
1168	.channels = max1236_channels,
1169	.num_channels = ARRAY_SIZE(max1236_channels),
1170	},
1171	[max1237] = {
1172	.bits = 12,
1173	.int_vref_mv = 2048,
1174	.mode_list = max1236_mode_list,
1175	.num_modes = ARRAY_SIZE(max1236_mode_list),
1176	.default_mode = s0to3,
1177	.info = &max1238_info,
1178	.channels = max1236_channels,
1179	.num_channels = ARRAY_SIZE(max1236_channels),
1180	},
1181	[max1238] = {
1182	.bits = 12,
1183	.int_vref_mv = 4096,
1184	.mode_list = max1238_mode_list,
1185	.num_modes = ARRAY_SIZE(max1238_mode_list),
1186	.default_mode = s0to11,
1187	.info = &max1238_info,
1188	.channels = max1238_channels,
1189	.num_channels = ARRAY_SIZE(max1238_channels),
1190	},
1191	[max1239] = {
1192	.bits = 12,
1193	.int_vref_mv = 2048,
1194	.mode_list = max1238_mode_list,
1195	.num_modes = ARRAY_SIZE(max1238_mode_list),
1196	.default_mode = s0to11,
1197	.info = &max1238_info,
1198	.channels = max1238_channels,
1199	.num_channels = ARRAY_SIZE(max1238_channels),
1200	},
1201	[max11600] = {
1202	.bits = 8,
1203	.int_vref_mv = 4096,
1204	.mode_list = max11607_mode_list,
1205	.num_modes = ARRAY_SIZE(max11607_mode_list),
1206	.default_mode = s0to3,
1207	.info = &max1238_info,
1208	.channels = max1036_channels,
1209	.num_channels = ARRAY_SIZE(max1036_channels),
1210	},
1211	[max11601] = {
1212	.bits = 8,
1213	.int_vref_mv = 2048,
1214	.mode_list = max11607_mode_list,
1215	.num_modes = ARRAY_SIZE(max11607_mode_list),
1216	.default_mode = s0to3,
1217	.info = &max1238_info,
1218	.channels = max1036_channels,
1219	.num_channels = ARRAY_SIZE(max1036_channels),
1220	},
1221	[max11602] = {
1222	.bits = 8,
1223	.int_vref_mv = 4096,
1224	.mode_list = max11608_mode_list,
1225	.num_modes = ARRAY_SIZE(max11608_mode_list),
1226	.default_mode = s0to7,
1227	.info = &max1238_info,
1228	.channels = max11602_channels,
1229	.num_channels = ARRAY_SIZE(max11602_channels),
1230	},
1231	[max11603] = {
1232	.bits = 8,
1233	.int_vref_mv = 2048,
1234	.mode_list = max11608_mode_list,
1235	.num_modes = ARRAY_SIZE(max11608_mode_list),
1236	.default_mode = s0to7,
1237	.info = &max1238_info,
1238	.channels = max11602_channels,
1239	.num_channels = ARRAY_SIZE(max11602_channels),
1240	},
1241	[max11604] = {
1242	.bits = 8,
1243	.int_vref_mv = 4096,
1244	.mode_list = max1238_mode_list,
1245	.num_modes = ARRAY_SIZE(max1238_mode_list),
1246	.default_mode = s0to11,
1247	.info = &max1238_info,
1248	.channels = max1038_channels,
1249	.num_channels = ARRAY_SIZE(max1038_channels),
1250	},
1251	[max11605] = {
1252	.bits = 8,
1253	.int_vref_mv = 2048,
1254	.mode_list = max1238_mode_list,
1255	.num_modes = ARRAY_SIZE(max1238_mode_list),
1256	.default_mode = s0to11,
1257	.info = &max1238_info,
1258	.channels = max1038_channels,
1259	.num_channels = ARRAY_SIZE(max1038_channels),
1260	},
1261	[max11606] = {
1262	.bits = 10,
1263	.int_vref_mv = 4096,
1264	.mode_list = max11607_mode_list,
1265	.num_modes = ARRAY_SIZE(max11607_mode_list),
1266	.default_mode = s0to3,
1267	.info = &max1238_info,
1268	.channels = max1136_channels,
1269	.num_channels = ARRAY_SIZE(max1136_channels),
1270	},
1271	[max11607] = {
1272	.bits = 10,
1273	.int_vref_mv = 2048,
1274	.mode_list = max11607_mode_list,
1275	.num_modes = ARRAY_SIZE(max11607_mode_list),
1276	.default_mode = s0to3,
1277	.info = &max1238_info,
1278	.channels = max1136_channels,
1279	.num_channels = ARRAY_SIZE(max1136_channels),
1280	},
1281	[max11608] = {
1282	.bits = 10,
1283	.int_vref_mv = 4096,
1284	.mode_list = max11608_mode_list,
1285	.num_modes = ARRAY_SIZE(max11608_mode_list),
1286	.default_mode = s0to7,
1287	.info = &max1238_info,
1288	.channels = max11608_channels,
1289	.num_channels = ARRAY_SIZE(max11608_channels),
1290	},
1291	[max11609] = {
1292	.bits = 10,
1293	.int_vref_mv = 2048,
1294	.mode_list = max11608_mode_list,
1295	.num_modes = ARRAY_SIZE(max11608_mode_list),
1296	.default_mode = s0to7,
1297	.info = &max1238_info,
1298	.channels = max11608_channels,
1299	.num_channels = ARRAY_SIZE(max11608_channels),
1300	},
1301	[max11610] = {
1302	.bits = 10,
1303	.int_vref_mv = 4096,
1304	.mode_list = max1238_mode_list,
1305	.num_modes = ARRAY_SIZE(max1238_mode_list),
1306	.default_mode = s0to11,
1307	.info = &max1238_info,
1308	.channels = max1138_channels,
1309	.num_channels = ARRAY_SIZE(max1138_channels),
1310	},
1311	[max11611] = {
1312	.bits = 10,
1313	.int_vref_mv = 2048,
1314	.mode_list = max1238_mode_list,
1315	.num_modes = ARRAY_SIZE(max1238_mode_list),
1316	.default_mode = s0to11,
1317	.info = &max1238_info,
1318	.channels = max1138_channels,
1319	.num_channels = ARRAY_SIZE(max1138_channels),
1320	},
1321	[max11612] = {
1322	.bits = 12,
1323	.int_vref_mv = 4096,
1324	.mode_list = max11607_mode_list,
1325	.num_modes = ARRAY_SIZE(max11607_mode_list),
1326	.default_mode = s0to3,
1327	.info = &max1238_info,
1328	.channels = max1363_channels,
1329	.num_channels = ARRAY_SIZE(max1363_channels),
1330	},
1331	[max11613] = {
1332	.bits = 12,
1333	.int_vref_mv = 2048,
1334	.mode_list = max11607_mode_list,
1335	.num_modes = ARRAY_SIZE(max11607_mode_list),
1336	.default_mode = s0to3,
1337	.info = &max1238_info,
1338	.channels = max1363_channels,
1339	.num_channels = ARRAY_SIZE(max1363_channels),
1340	},
1341	[max11614] = {
1342	.bits = 12,
1343	.int_vref_mv = 4096,
1344	.mode_list = max11608_mode_list,
1345	.num_modes = ARRAY_SIZE(max11608_mode_list),
1346	.default_mode = s0to7,
1347	.info = &max1238_info,
1348	.channels = max11614_channels,
1349	.num_channels = ARRAY_SIZE(max11614_channels),
1350	},
1351	[max11615] = {
1352	.bits = 12,
1353	.int_vref_mv = 2048,
1354	.mode_list = max11608_mode_list,
1355	.num_modes = ARRAY_SIZE(max11608_mode_list),
1356	.default_mode = s0to7,
1357	.info = &max1238_info,
1358	.channels = max11614_channels,
1359	.num_channels = ARRAY_SIZE(max11614_channels),
1360	},
1361	[max11616] = {
1362	.bits = 12,
1363	.int_vref_mv = 4096,
1364	.mode_list = max1238_mode_list,
1365	.num_modes = ARRAY_SIZE(max1238_mode_list),
1366	.default_mode = s0to11,
1367	.info = &max1238_info,
1368	.channels = max1238_channels,
1369	.num_channels = ARRAY_SIZE(max1238_channels),
1370	},
1371	[max11617] = {
1372	.bits = 12,
1373	.int_vref_mv = 2048,
1374	.mode_list = max1238_mode_list,
1375	.num_modes = ARRAY_SIZE(max1238_mode_list),
1376	.default_mode = s0to11,
1377	.info = &max1238_info,
1378	.channels = max1238_channels,
1379	.num_channels = ARRAY_SIZE(max1238_channels),
1380	},
1381	[max11644] = {
1382	.bits = 12,
1383	.int_vref_mv = 4096,
1384	.mode_list = max11644_mode_list,
1385	.num_modes = ARRAY_SIZE(max11644_mode_list),
1386	.default_mode = s0to1,
1387	.info = &max1238_info,
1388	.channels = max11644_channels,
1389	.num_channels = ARRAY_SIZE(max11644_channels),
1390	},
1391	[max11645] = {
1392	.bits = 12,
1393	.int_vref_mv = 2048,
1394	.mode_list = max11644_mode_list,
1395	.num_modes = ARRAY_SIZE(max11644_mode_list),
1396	.default_mode = s0to1,
1397	.info = &max1238_info,
1398	.channels = max11644_channels,
1399	.num_channels = ARRAY_SIZE(max11644_channels),
1400	},
1401	[max11646] = {
1402	.bits = 10,
1403	.int_vref_mv = 4096,
1404	.mode_list = max11644_mode_list,
1405	.num_modes = ARRAY_SIZE(max11644_mode_list),
1406	.default_mode = s0to1,
1407	.info = &max1238_info,
1408	.channels = max11646_channels,
1409	.num_channels = ARRAY_SIZE(max11646_channels),
1410	},
1411	[max11647] = {
1412	.bits = 10,
1413	.int_vref_mv = 2048,
1414	.mode_list = max11644_mode_list,
1415	.num_modes = ARRAY_SIZE(max11644_mode_list),
1416	.default_mode = s0to1,
1417	.info = &max1238_info,
1418	.channels = max11646_channels,
1419	.num_channels = ARRAY_SIZE(max11646_channels),
1420	},
1421	};
1422
1423	static int max1363_initial_setup(struct max1363_state *st)
1424	{
1425	st->setupbyte = MAX1363_SETUP_INT_CLOCK
1426	| MAX1363_SETUP_UNIPOLAR
1427	| MAX1363_SETUP_NORESET;
1428
1429	if (st->vref)
1430	st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
1431	else
1432	st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
1433	| MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
1434
1435	/* Set scan mode writes the config anyway so wait until then */
1436	st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1437	st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1438	st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1439
1440	return max1363_set_scan_mode(st);
1441	}
1442
1443	static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
1444	{
1445	struct max1363_state *st = iio_priv(indio_dev);
1446	unsigned long *masks;
1447	int i;
1448
1449	masks = devm_kzalloc(dev: &indio_dev->dev,
1450	array3_size(BITS_TO_LONGS(MAX1363_MAX_CHANNELS),
1451	sizeof(long),
1452	st->chip_info->num_modes + 1),
1453	GFP_KERNEL);
1454	if (!masks)
1455	return -ENOMEM;
1456
1457	for (i = 0; i < st->chip_info->num_modes; i++)
1458	bitmap_copy(dst: masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1459	src: max1363_mode_table[st->chip_info->mode_list[i]]
1460	.modemask, MAX1363_MAX_CHANNELS);
1461
1462	indio_dev->available_scan_masks = masks;
1463
1464	return 0;
1465	}
1466
1467	static irqreturn_t max1363_trigger_handler(int irq, void *p)
1468	{
1469	struct iio_poll_func *pf = p;
1470	struct iio_dev *indio_dev = pf->indio_dev;
1471	struct max1363_state *st = iio_priv(indio_dev);
1472	__u8 *rxbuf;
1473	int b_sent;
1474	size_t d_size;
1475	unsigned long numvals = bitmap_weight(src: st->current_mode->modemask,
1476	MAX1363_MAX_CHANNELS);
1477
1478	/* Ensure the timestamp is 8 byte aligned */
1479	if (st->chip_info->bits != 8)
1480	d_size = numvals*2;
1481	else
1482	d_size = numvals;
1483	if (indio_dev->scan_timestamp) {
1484	d_size += sizeof(s64);
1485	if (d_size % sizeof(s64))
1486	d_size += sizeof(s64) - (d_size % sizeof(s64));
1487	}
1488	/* Monitor mode prevents reading. Whilst not currently implemented
1489	* might as well have this test in here in the meantime as it does
1490	* no harm.
1491	*/
1492	if (numvals == 0)
1493	goto done;
1494
1495	rxbuf = kmalloc(size: d_size, GFP_KERNEL);
1496	if (rxbuf == NULL)
1497	goto done;
1498	if (st->chip_info->bits != 8)
1499	b_sent = st->recv(st->client, rxbuf, numvals * 2);
1500	else
1501	b_sent = st->recv(st->client, rxbuf, numvals);
1502	if (b_sent < 0)
1503	goto done_free;
1504
1505	iio_push_to_buffers_with_timestamp(indio_dev, data: rxbuf,
1506	timestamp: iio_get_time_ns(indio_dev));
1507
1508	done_free:
1509	kfree(objp: rxbuf);
1510	done:
1511	iio_trigger_notify_done(trig: indio_dev->trig);
1512
1513	return IRQ_HANDLED;
1514	}
1515
1516	#define MAX1363_COMPATIBLE(of_compatible, cfg) { \
1517	.compatible = of_compatible, \
1518	.data = &max1363_chip_info_tbl[cfg], \
1519	}
1520
1521	static const struct of_device_id max1363_of_match[] = {
1522	MAX1363_COMPATIBLE("maxim,max1361", max1361),
1523	MAX1363_COMPATIBLE("maxim,max1362", max1362),
1524	MAX1363_COMPATIBLE("maxim,max1363", max1363),
1525	MAX1363_COMPATIBLE("maxim,max1364", max1364),
1526	MAX1363_COMPATIBLE("maxim,max1036", max1036),
1527	MAX1363_COMPATIBLE("maxim,max1037", max1037),
1528	MAX1363_COMPATIBLE("maxim,max1038", max1038),
1529	MAX1363_COMPATIBLE("maxim,max1039", max1039),
1530	MAX1363_COMPATIBLE("maxim,max1136", max1136),
1531	MAX1363_COMPATIBLE("maxim,max1137", max1137),
1532	MAX1363_COMPATIBLE("maxim,max1138", max1138),
1533	MAX1363_COMPATIBLE("maxim,max1139", max1139),
1534	MAX1363_COMPATIBLE("maxim,max1236", max1236),
1535	MAX1363_COMPATIBLE("maxim,max1237", max1237),
1536	MAX1363_COMPATIBLE("maxim,max1238", max1238),
1537	MAX1363_COMPATIBLE("maxim,max1239", max1239),
1538	MAX1363_COMPATIBLE("maxim,max11600", max11600),
1539	MAX1363_COMPATIBLE("maxim,max11601", max11601),
1540	MAX1363_COMPATIBLE("maxim,max11602", max11602),
1541	MAX1363_COMPATIBLE("maxim,max11603", max11603),
1542	MAX1363_COMPATIBLE("maxim,max11604", max11604),
1543	MAX1363_COMPATIBLE("maxim,max11605", max11605),
1544	MAX1363_COMPATIBLE("maxim,max11606", max11606),
1545	MAX1363_COMPATIBLE("maxim,max11607", max11607),
1546	MAX1363_COMPATIBLE("maxim,max11608", max11608),
1547	MAX1363_COMPATIBLE("maxim,max11609", max11609),
1548	MAX1363_COMPATIBLE("maxim,max11610", max11610),
1549	MAX1363_COMPATIBLE("maxim,max11611", max11611),
1550	MAX1363_COMPATIBLE("maxim,max11612", max11612),
1551	MAX1363_COMPATIBLE("maxim,max11613", max11613),
1552	MAX1363_COMPATIBLE("maxim,max11614", max11614),
1553	MAX1363_COMPATIBLE("maxim,max11615", max11615),
1554	MAX1363_COMPATIBLE("maxim,max11616", max11616),
1555	MAX1363_COMPATIBLE("maxim,max11617", max11617),
1556	MAX1363_COMPATIBLE("maxim,max11644", max11644),
1557	MAX1363_COMPATIBLE("maxim,max11645", max11645),
1558	MAX1363_COMPATIBLE("maxim,max11646", max11646),
1559	MAX1363_COMPATIBLE("maxim,max11647", max11647),
1560	{ /* sentinel */ }
1561	};
1562	MODULE_DEVICE_TABLE(of, max1363_of_match);
1563
1564	static void max1363_reg_disable(void *reg)
1565	{
1566	regulator_disable(regulator: reg);
1567	}
1568
1569	static int max1363_probe(struct i2c_client *client)
1570	{
1571	const struct i2c_device_id *id = i2c_client_get_device_id(client);
1572	int ret;
1573	struct max1363_state *st;
1574	struct iio_dev *indio_dev;
1575	struct regulator *vref;
1576
1577	indio_dev = devm_iio_device_alloc(parent: &client->dev,
1578	sizeof_priv: sizeof(struct max1363_state));
1579	if (!indio_dev)
1580	return -ENOMEM;
1581
1582	st = iio_priv(indio_dev);
1583
1584	mutex_init(&st->lock);
1585	ret = devm_regulator_get_enable(dev: &client->dev, id: "vcc");
1586	if (ret)
1587	return ret;
1588
1589	st->chip_info = i2c_get_match_data(client);
1590	st->client = client;
1591
1592	st->vref_uv = st->chip_info->int_vref_mv * 1000;
1593	vref = devm_regulator_get_optional(dev: &client->dev, id: "vref");
1594	if (!IS_ERR(ptr: vref)) {
1595	int vref_uv;
1596
1597	ret = regulator_enable(regulator: vref);
1598	if (ret)
1599	return ret;
1600
1601	ret = devm_add_action_or_reset(&client->dev, max1363_reg_disable, vref);
1602	if (ret)
1603	return ret;
1604
1605	st->vref = vref;
1606	vref_uv = regulator_get_voltage(regulator: vref);
1607	if (vref_uv <= 0)
1608	return -EINVAL;
1609
1610	st->vref_uv = vref_uv;
1611	}
1612
1613	if (i2c_check_functionality(adap: client->adapter, I2C_FUNC_I2C)) {
1614	st->send = i2c_master_send;
1615	st->recv = i2c_master_recv;
1616	} else if (i2c_check_functionality(adap: client->adapter, I2C_FUNC_SMBUS_BYTE)
1617	&& st->chip_info->bits == 8) {
1618	st->send = max1363_smbus_send;
1619	st->recv = max1363_smbus_recv;
1620	} else {
1621	return -EOPNOTSUPP;
1622	}
1623
1624	ret = max1363_alloc_scan_masks(indio_dev);
1625	if (ret)
1626	return ret;
1627
1628	indio_dev->name = id->name;
1629	indio_dev->channels = st->chip_info->channels;
1630	indio_dev->num_channels = st->chip_info->num_channels;
1631	indio_dev->info = st->chip_info->info;
1632	indio_dev->modes = INDIO_DIRECT_MODE;
1633	ret = max1363_initial_setup(st);
1634	if (ret < 0)
1635	return ret;
1636
1637	ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
1638	&max1363_trigger_handler, NULL);
1639	if (ret)
1640	return ret;
1641
1642	if (client->irq) {
1643	ret = devm_request_threaded_irq(dev: &client->dev, irq: st->client->irq,
1644	NULL,
1645	thread_fn: &max1363_event_handler,
1646	IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1647	devname: "max1363_event",
1648	dev_id: indio_dev);
1649
1650	if (ret)
1651	return ret;
1652	}
1653
1654	return devm_iio_device_register(&client->dev, indio_dev);
1655	}
1656
1657	#define MAX1363_ID_TABLE(_name, cfg) { \
1658	.name = _name, \
1659	.driver_data = (kernel_ulong_t)&max1363_chip_info_tbl[cfg], \
1660	}
1661
1662	static const struct i2c_device_id max1363_id[] = {
1663	MAX1363_ID_TABLE("max1361", max1361),
1664	MAX1363_ID_TABLE("max1362", max1362),
1665	MAX1363_ID_TABLE("max1363", max1363),
1666	MAX1363_ID_TABLE("max1364", max1364),
1667	MAX1363_ID_TABLE("max1036", max1036),
1668	MAX1363_ID_TABLE("max1037", max1037),
1669	MAX1363_ID_TABLE("max1038", max1038),
1670	MAX1363_ID_TABLE("max1039", max1039),
1671	MAX1363_ID_TABLE("max1136", max1136),
1672	MAX1363_ID_TABLE("max1137", max1137),
1673	MAX1363_ID_TABLE("max1138", max1138),
1674	MAX1363_ID_TABLE("max1139", max1139),
1675	MAX1363_ID_TABLE("max1236", max1236),
1676	MAX1363_ID_TABLE("max1237", max1237),
1677	MAX1363_ID_TABLE("max1238", max1238),
1678	MAX1363_ID_TABLE("max1239", max1239),
1679	MAX1363_ID_TABLE("max11600", max11600),
1680	MAX1363_ID_TABLE("max11601", max11601),
1681	MAX1363_ID_TABLE("max11602", max11602),
1682	MAX1363_ID_TABLE("max11603", max11603),
1683	MAX1363_ID_TABLE("max11604", max11604),
1684	MAX1363_ID_TABLE("max11605", max11605),
1685	MAX1363_ID_TABLE("max11606", max11606),
1686	MAX1363_ID_TABLE("max11607", max11607),
1687	MAX1363_ID_TABLE("max11608", max11608),
1688	MAX1363_ID_TABLE("max11609", max11609),
1689	MAX1363_ID_TABLE("max11610", max11610),
1690	MAX1363_ID_TABLE("max11611", max11611),
1691	MAX1363_ID_TABLE("max11612", max11612),
1692	MAX1363_ID_TABLE("max11613", max11613),
1693	MAX1363_ID_TABLE("max11614", max11614),
1694	MAX1363_ID_TABLE("max11615", max11615),
1695	MAX1363_ID_TABLE("max11616", max11616),
1696	MAX1363_ID_TABLE("max11617", max11617),
1697	MAX1363_ID_TABLE("max11644", max11644),
1698	MAX1363_ID_TABLE("max11645", max11645),
1699	MAX1363_ID_TABLE("max11646", max11646),
1700	MAX1363_ID_TABLE("max11647", max11647),
1701	{ /* sentinel */ }
1702	};
1703
1704	MODULE_DEVICE_TABLE(i2c, max1363_id);
1705
1706	static struct i2c_driver max1363_driver = {
1707	.driver = {
1708	.name = "max1363",
1709	.of_match_table = max1363_of_match,
1710	},
1711	.probe = max1363_probe,
1712	.id_table = max1363_id,
1713	};
1714	module_i2c_driver(max1363_driver);
1715
1716	MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1717	MODULE_DESCRIPTION("Maxim 1363 ADC");
1718	MODULE_LICENSE("GPL v2");
1719