1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2021 Google LLC.
4 *
5 * Driver for Semtech's SX9324 capacitive proximity/button solution.
6 * Based on SX9324 driver and copy of datasheet at:
7 * https://edit.wpgdadawant.com/uploads/news_file/program/2019/30184/tech_files/program_30184_suggest_other_file.pdf
8 */
9
10#include <linux/acpi.h>
11#include <linux/bits.h>
12#include <linux/bitfield.h>
13#include <linux/delay.h>
14#include <linux/i2c.h>
15#include <linux/interrupt.h>
16#include <linux/kernel.h>
17#include <linux/log2.h>
18#include <linux/mod_devicetable.h>
19#include <linux/module.h>
20#include <linux/pm.h>
21#include <linux/property.h>
22#include <linux/regmap.h>
23
24#include <linux/iio/iio.h>
25
26#include "sx_common.h"
27
28/* Register definitions. */
29#define SX9324_REG_IRQ_SRC SX_COMMON_REG_IRQ_SRC
30#define SX9324_REG_STAT0 0x01
31#define SX9324_REG_STAT1 0x02
32#define SX9324_REG_STAT2 0x03
33#define SX9324_REG_STAT2_COMPSTAT_MASK GENMASK(3, 0)
34#define SX9324_REG_STAT3 0x04
35#define SX9324_REG_IRQ_MSK 0x05
36#define SX9324_CONVDONE_IRQ BIT(3)
37#define SX9324_FAR_IRQ BIT(5)
38#define SX9324_CLOSE_IRQ BIT(6)
39#define SX9324_REG_IRQ_CFG0 0x06
40#define SX9324_REG_IRQ_CFG1 0x07
41#define SX9324_REG_IRQ_CFG1_FAILCOND 0x80
42#define SX9324_REG_IRQ_CFG2 0x08
43
44#define SX9324_REG_GNRL_CTRL0 0x10
45#define SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK GENMASK(4, 0)
46#define SX9324_REG_GNRL_CTRL0_SCANPERIOD_100MS 0x16
47#define SX9324_REG_GNRL_CTRL1 0x11
48#define SX9324_REG_GNRL_CTRL1_PHEN_MASK GENMASK(3, 0)
49#define SX9324_REG_GNRL_CTRL1_PAUSECTRL 0x20
50
51#define SX9324_REG_I2C_ADDR 0x14
52#define SX9324_REG_CLK_SPRD 0x15
53
54#define SX9324_REG_AFE_CTRL0 0x20
55#define SX9324_REG_AFE_CTRL0_RINT_SHIFT 6
56#define SX9324_REG_AFE_CTRL0_RINT_MASK \
57 GENMASK(SX9324_REG_AFE_CTRL0_RINT_SHIFT + 1, \
58 SX9324_REG_AFE_CTRL0_RINT_SHIFT)
59#define SX9324_REG_AFE_CTRL0_RINT_LOWEST 0x00
60#define SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT 4
61#define SX9324_REG_AFE_CTRL0_CSIDLE_MASK \
62 GENMASK(SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT + 1, \
63 SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT)
64#define SX9324_REG_AFE_CTRL0_RINT_LOWEST 0x00
65#define SX9324_REG_AFE_CTRL1 0x21
66#define SX9324_REG_AFE_CTRL2 0x22
67#define SX9324_REG_AFE_CTRL3 0x23
68#define SX9324_REG_AFE_CTRL4 0x24
69#define SX9324_REG_AFE_CTRL4_FREQ_83_33HZ 0x40
70#define SX9324_REG_AFE_CTRL4_RESOLUTION_MASK GENMASK(2, 0)
71#define SX9324_REG_AFE_CTRL4_RES_100 0x04
72#define SX9324_REG_AFE_CTRL5 0x25
73#define SX9324_REG_AFE_CTRL6 0x26
74#define SX9324_REG_AFE_CTRL7 0x27
75#define SX9324_REG_AFE_PH0 0x28
76#define SX9324_REG_AFE_PH0_PIN_MASK(_pin) \
77 GENMASK(2 * (_pin) + 1, 2 * (_pin))
78
79#define SX9324_REG_AFE_PH1 0x29
80#define SX9324_REG_AFE_PH2 0x2a
81#define SX9324_REG_AFE_PH3 0x2b
82#define SX9324_REG_AFE_CTRL8 0x2c
83#define SX9324_REG_AFE_CTRL8_RESERVED 0x10
84#define SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM 0x02
85#define SX9324_REG_AFE_CTRL8_RESFILTIN_MASK GENMASK(3, 0)
86#define SX9324_REG_AFE_CTRL9 0x2d
87#define SX9324_REG_AFE_CTRL9_AGAIN_MASK GENMASK(3, 0)
88#define SX9324_REG_AFE_CTRL9_AGAIN_1 0x08
89
90#define SX9324_REG_PROX_CTRL0 0x30
91#define SX9324_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3)
92#define SX9324_REG_PROX_CTRL0_GAIN_SHIFT 3
93#define SX9324_REG_PROX_CTRL0_GAIN_RSVD 0x0
94#define SX9324_REG_PROX_CTRL0_GAIN_1 0x1
95#define SX9324_REG_PROX_CTRL0_GAIN_8 0x4
96#define SX9324_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0)
97#define SX9324_REG_PROX_CTRL0_RAWFILT_1P50 0x01
98#define SX9324_REG_PROX_CTRL1 0x31
99#define SX9324_REG_PROX_CTRL2 0x32
100#define SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K 0x20
101#define SX9324_REG_PROX_CTRL3 0x33
102#define SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES 0x40
103#define SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K 0x20
104#define SX9324_REG_PROX_CTRL4 0x34
105#define SX9324_REG_PROX_CTRL4_AVGNEGFILT_MASK GENMASK(5, 3)
106#define SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 0x08
107#define SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK GENMASK(2, 0)
108#define SX9324_REG_PROX_CTRL4_AVGPOS_FILT_256 0x04
109#define SX9324_REG_PROX_CTRL5 0x35
110#define SX9324_REG_PROX_CTRL5_HYST_MASK GENMASK(5, 4)
111#define SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK GENMASK(3, 2)
112#define SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK GENMASK(1, 0)
113#define SX9324_REG_PROX_CTRL6 0x36
114#define SX9324_REG_PROX_CTRL6_PROXTHRESH_32 0x08
115#define SX9324_REG_PROX_CTRL7 0x37
116
117#define SX9324_REG_ADV_CTRL0 0x40
118#define SX9324_REG_ADV_CTRL1 0x41
119#define SX9324_REG_ADV_CTRL2 0x42
120#define SX9324_REG_ADV_CTRL3 0x43
121#define SX9324_REG_ADV_CTRL4 0x44
122#define SX9324_REG_ADV_CTRL5 0x45
123#define SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK GENMASK(3, 2)
124#define SX9324_REG_ADV_CTRL5_STARTUP_SENSOR_1 0x04
125#define SX9324_REG_ADV_CTRL5_STARTUP_METHOD_1 0x01
126#define SX9324_REG_ADV_CTRL6 0x46
127#define SX9324_REG_ADV_CTRL7 0x47
128#define SX9324_REG_ADV_CTRL8 0x48
129#define SX9324_REG_ADV_CTRL9 0x49
130#define SX9324_REG_ADV_CTRL10 0x4a
131#define SX9324_REG_ADV_CTRL11 0x4b
132#define SX9324_REG_ADV_CTRL12 0x4c
133#define SX9324_REG_ADV_CTRL13 0x4d
134#define SX9324_REG_ADV_CTRL14 0x4e
135#define SX9324_REG_ADV_CTRL15 0x4f
136#define SX9324_REG_ADV_CTRL16 0x50
137#define SX9324_REG_ADV_CTRL17 0x51
138#define SX9324_REG_ADV_CTRL18 0x52
139#define SX9324_REG_ADV_CTRL19 0x53
140#define SX9324_REG_ADV_CTRL20 0x54
141#define SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION 0xf0
142
143#define SX9324_REG_PHASE_SEL 0x60
144
145#define SX9324_REG_USEFUL_MSB 0x61
146#define SX9324_REG_USEFUL_LSB 0x62
147
148#define SX9324_REG_AVG_MSB 0x63
149#define SX9324_REG_AVG_LSB 0x64
150
151#define SX9324_REG_DIFF_MSB 0x65
152#define SX9324_REG_DIFF_LSB 0x66
153
154#define SX9324_REG_OFFSET_MSB 0x67
155#define SX9324_REG_OFFSET_LSB 0x68
156
157#define SX9324_REG_SAR_MSB 0x69
158#define SX9324_REG_SAR_LSB 0x6a
159
160#define SX9324_REG_RESET 0x9f
161/* Write this to REG_RESET to do a soft reset. */
162#define SX9324_SOFT_RESET 0xde
163
164#define SX9324_REG_WHOAMI 0xfa
165#define SX9324_WHOAMI_VALUE 0x23
166
167#define SX9324_REG_REVISION 0xfe
168
169/* 4 channels, as defined in STAT0: PH0, PH1, PH2 and PH3. */
170#define SX9324_NUM_CHANNELS 4
171/* 3 CS pins: CS0, CS1, CS2. */
172#define SX9324_NUM_PINS 3
173
174static const char * const sx9324_cs_pin_usage[] = { "HZ", "MI", "DS", "GD" };
175
176static ssize_t sx9324_phase_configuration_show(struct iio_dev *indio_dev,
177 uintptr_t private,
178 const struct iio_chan_spec *chan,
179 char *buf)
180{
181 struct sx_common_data *data = iio_priv(indio_dev);
182 unsigned int val;
183 int i, ret, pin_idx;
184 size_t len = 0;
185
186 ret = regmap_read(map: data->regmap, SX9324_REG_AFE_PH0 + chan->channel, val: &val);
187 if (ret < 0)
188 return ret;
189
190 for (i = 0; i < SX9324_NUM_PINS; i++) {
191 pin_idx = (val & SX9324_REG_AFE_PH0_PIN_MASK(i)) >> (2 * i);
192 len += sysfs_emit_at(buf, at: len, fmt: "%s,",
193 sx9324_cs_pin_usage[pin_idx]);
194 }
195 buf[len - 1] = '\n';
196 return len;
197}
198
199static const struct iio_chan_spec_ext_info sx9324_channel_ext_info[] = {
200 {
201 .name = "setup",
202 .shared = IIO_SEPARATE,
203 .read = sx9324_phase_configuration_show,
204 },
205 {}
206};
207
208#define SX9324_CHANNEL(idx) \
209{ \
210 .type = IIO_PROXIMITY, \
211 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
212 BIT(IIO_CHAN_INFO_HARDWAREGAIN), \
213 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
214 .info_mask_separate_available = \
215 BIT(IIO_CHAN_INFO_HARDWAREGAIN), \
216 .info_mask_shared_by_all_available = \
217 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
218 .indexed = 1, \
219 .channel = idx, \
220 .address = SX9324_REG_DIFF_MSB, \
221 .event_spec = sx_common_events, \
222 .num_event_specs = ARRAY_SIZE(sx_common_events), \
223 .scan_index = idx, \
224 .scan_type = { \
225 .sign = 's', \
226 .realbits = 12, \
227 .storagebits = 16, \
228 .endianness = IIO_BE, \
229 }, \
230 .ext_info = sx9324_channel_ext_info, \
231}
232
233static const struct iio_chan_spec sx9324_channels[] = {
234 SX9324_CHANNEL(0), /* Phase 0 */
235 SX9324_CHANNEL(1), /* Phase 1 */
236 SX9324_CHANNEL(2), /* Phase 2 */
237 SX9324_CHANNEL(3), /* Phase 3 */
238 IIO_CHAN_SOFT_TIMESTAMP(4),
239};
240
241/*
242 * Each entry contains the integer part (val) and the fractional part, in micro
243 * seconds. It conforms to the IIO output IIO_VAL_INT_PLUS_MICRO.
244 */
245static const struct {
246 int val;
247 int val2;
248} sx9324_samp_freq_table[] = {
249 { 1000, 0 }, /* 00000: Min (no idle time) */
250 { 500, 0 }, /* 00001: 2 ms */
251 { 250, 0 }, /* 00010: 4 ms */
252 { 166, 666666 }, /* 00011: 6 ms */
253 { 125, 0 }, /* 00100: 8 ms */
254 { 100, 0 }, /* 00101: 10 ms */
255 { 71, 428571 }, /* 00110: 14 ms */
256 { 55, 555556 }, /* 00111: 18 ms */
257 { 45, 454545 }, /* 01000: 22 ms */
258 { 38, 461538 }, /* 01001: 26 ms */
259 { 33, 333333 }, /* 01010: 30 ms */
260 { 29, 411765 }, /* 01011: 34 ms */
261 { 26, 315789 }, /* 01100: 38 ms */
262 { 23, 809524 }, /* 01101: 42 ms */
263 { 21, 739130 }, /* 01110: 46 ms */
264 { 20, 0 }, /* 01111: 50 ms */
265 { 17, 857143 }, /* 10000: 56 ms */
266 { 16, 129032 }, /* 10001: 62 ms */
267 { 14, 705882 }, /* 10010: 68 ms */
268 { 13, 513514 }, /* 10011: 74 ms */
269 { 12, 500000 }, /* 10100: 80 ms */
270 { 11, 111111 }, /* 10101: 90 ms */
271 { 10, 0 }, /* 10110: 100 ms (Typ.) */
272 { 5, 0 }, /* 10111: 200 ms */
273 { 3, 333333 }, /* 11000: 300 ms */
274 { 2, 500000 }, /* 11001: 400 ms */
275 { 1, 666667 }, /* 11010: 600 ms */
276 { 1, 250000 }, /* 11011: 800 ms */
277 { 1, 0 }, /* 11100: 1 s */
278 { 0, 500000 }, /* 11101: 2 s */
279 { 0, 333333 }, /* 11110: 3 s */
280 { 0, 250000 }, /* 11111: 4 s */
281};
282
283static const unsigned int sx9324_scan_period_table[] = {
284 2, 15, 30, 45, 60, 90, 120, 200,
285 400, 600, 800, 1000, 2000, 3000, 4000, 5000,
286};
287
288static const struct regmap_range sx9324_writable_reg_ranges[] = {
289 /*
290 * To set COMPSTAT for compensation, even if datasheet says register is
291 * RO.
292 */
293 regmap_reg_range(SX9324_REG_STAT2, SX9324_REG_STAT2),
294 regmap_reg_range(SX9324_REG_IRQ_MSK, SX9324_REG_IRQ_CFG2),
295 regmap_reg_range(SX9324_REG_GNRL_CTRL0, SX9324_REG_GNRL_CTRL1),
296 /* Leave i2c and clock spreading as unavailable */
297 regmap_reg_range(SX9324_REG_AFE_CTRL0, SX9324_REG_AFE_CTRL9),
298 regmap_reg_range(SX9324_REG_PROX_CTRL0, SX9324_REG_PROX_CTRL7),
299 regmap_reg_range(SX9324_REG_ADV_CTRL0, SX9324_REG_ADV_CTRL20),
300 regmap_reg_range(SX9324_REG_PHASE_SEL, SX9324_REG_PHASE_SEL),
301 regmap_reg_range(SX9324_REG_OFFSET_MSB, SX9324_REG_OFFSET_LSB),
302 regmap_reg_range(SX9324_REG_RESET, SX9324_REG_RESET),
303};
304
305static const struct regmap_access_table sx9324_writeable_regs = {
306 .yes_ranges = sx9324_writable_reg_ranges,
307 .n_yes_ranges = ARRAY_SIZE(sx9324_writable_reg_ranges),
308};
309
310/*
311 * All allocated registers are readable, so we just list unallocated
312 * ones.
313 */
314static const struct regmap_range sx9324_non_readable_reg_ranges[] = {
315 regmap_reg_range(SX9324_REG_IRQ_CFG2 + 1, SX9324_REG_GNRL_CTRL0 - 1),
316 regmap_reg_range(SX9324_REG_GNRL_CTRL1 + 1, SX9324_REG_AFE_CTRL0 - 1),
317 regmap_reg_range(SX9324_REG_AFE_CTRL9 + 1, SX9324_REG_PROX_CTRL0 - 1),
318 regmap_reg_range(SX9324_REG_PROX_CTRL7 + 1, SX9324_REG_ADV_CTRL0 - 1),
319 regmap_reg_range(SX9324_REG_ADV_CTRL20 + 1, SX9324_REG_PHASE_SEL - 1),
320 regmap_reg_range(SX9324_REG_SAR_LSB + 1, SX9324_REG_RESET - 1),
321 regmap_reg_range(SX9324_REG_RESET + 1, SX9324_REG_WHOAMI - 1),
322 regmap_reg_range(SX9324_REG_WHOAMI + 1, SX9324_REG_REVISION - 1),
323};
324
325static const struct regmap_access_table sx9324_readable_regs = {
326 .no_ranges = sx9324_non_readable_reg_ranges,
327 .n_no_ranges = ARRAY_SIZE(sx9324_non_readable_reg_ranges),
328};
329
330static const struct regmap_range sx9324_volatile_reg_ranges[] = {
331 regmap_reg_range(SX9324_REG_IRQ_SRC, SX9324_REG_STAT3),
332 regmap_reg_range(SX9324_REG_USEFUL_MSB, SX9324_REG_DIFF_LSB),
333 regmap_reg_range(SX9324_REG_SAR_MSB, SX9324_REG_SAR_LSB),
334 regmap_reg_range(SX9324_REG_WHOAMI, SX9324_REG_WHOAMI),
335 regmap_reg_range(SX9324_REG_REVISION, SX9324_REG_REVISION),
336};
337
338static const struct regmap_access_table sx9324_volatile_regs = {
339 .yes_ranges = sx9324_volatile_reg_ranges,
340 .n_yes_ranges = ARRAY_SIZE(sx9324_volatile_reg_ranges),
341};
342
343static const struct regmap_config sx9324_regmap_config = {
344 .reg_bits = 8,
345 .val_bits = 8,
346
347 .max_register = SX9324_REG_REVISION,
348 .cache_type = REGCACHE_RBTREE,
349
350 .wr_table = &sx9324_writeable_regs,
351 .rd_table = &sx9324_readable_regs,
352 .volatile_table = &sx9324_volatile_regs,
353};
354
355static int sx9324_read_prox_data(struct sx_common_data *data,
356 const struct iio_chan_spec *chan,
357 __be16 *val)
358{
359 int ret;
360
361 ret = regmap_write(map: data->regmap, SX9324_REG_PHASE_SEL, val: chan->channel);
362 if (ret < 0)
363 return ret;
364
365 return regmap_bulk_read(map: data->regmap, reg: chan->address, val, val_count: sizeof(*val));
366}
367
368/*
369 * If we have no interrupt support, we have to wait for a scan period
370 * after enabling a channel to get a result.
371 */
372static int sx9324_wait_for_sample(struct sx_common_data *data)
373{
374 int ret;
375 unsigned int val;
376
377 ret = regmap_read(map: data->regmap, SX9324_REG_GNRL_CTRL0, val: &val);
378 if (ret < 0)
379 return ret;
380 val = FIELD_GET(SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, val);
381
382 msleep(msecs: sx9324_scan_period_table[val]);
383
384 return 0;
385}
386
387static int sx9324_read_gain(struct sx_common_data *data,
388 const struct iio_chan_spec *chan, int *val)
389{
390 unsigned int reg, regval;
391 int ret;
392
393 reg = SX9324_REG_PROX_CTRL0 + chan->channel / 2;
394 ret = regmap_read(map: data->regmap, reg, val: &regval);
395 if (ret)
396 return ret;
397
398 regval = FIELD_GET(SX9324_REG_PROX_CTRL0_GAIN_MASK, regval);
399 if (regval)
400 regval--;
401 else if (regval == SX9324_REG_PROX_CTRL0_GAIN_RSVD ||
402 regval > SX9324_REG_PROX_CTRL0_GAIN_8)
403 return -EINVAL;
404
405 *val = 1 << regval;
406
407 return IIO_VAL_INT;
408}
409
410static int sx9324_read_samp_freq(struct sx_common_data *data,
411 int *val, int *val2)
412{
413 int ret;
414 unsigned int regval;
415
416 ret = regmap_read(map: data->regmap, SX9324_REG_GNRL_CTRL0, val: &regval);
417 if (ret)
418 return ret;
419
420 regval = FIELD_GET(SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, regval);
421 *val = sx9324_samp_freq_table[regval].val;
422 *val2 = sx9324_samp_freq_table[regval].val2;
423
424 return IIO_VAL_INT_PLUS_MICRO;
425}
426
427static int sx9324_read_raw(struct iio_dev *indio_dev,
428 const struct iio_chan_spec *chan,
429 int *val, int *val2, long mask)
430{
431 struct sx_common_data *data = iio_priv(indio_dev);
432
433 switch (mask) {
434 case IIO_CHAN_INFO_RAW:
435 iio_device_claim_direct_scoped(return -EBUSY, indio_dev)
436 return sx_common_read_proximity(data, chan, val);
437 unreachable();
438 case IIO_CHAN_INFO_HARDWAREGAIN:
439 iio_device_claim_direct_scoped(return -EBUSY, indio_dev)
440 return sx9324_read_gain(data, chan, val);
441 unreachable();
442 case IIO_CHAN_INFO_SAMP_FREQ:
443 return sx9324_read_samp_freq(data, val, val2);
444 default:
445 return -EINVAL;
446 }
447}
448
449static const int sx9324_gain_vals[] = { 1, 2, 4, 8 };
450
451static int sx9324_read_avail(struct iio_dev *indio_dev,
452 struct iio_chan_spec const *chan,
453 const int **vals, int *type, int *length,
454 long mask)
455{
456 if (chan->type != IIO_PROXIMITY)
457 return -EINVAL;
458
459 switch (mask) {
460 case IIO_CHAN_INFO_HARDWAREGAIN:
461 *type = IIO_VAL_INT;
462 *length = ARRAY_SIZE(sx9324_gain_vals);
463 *vals = sx9324_gain_vals;
464 return IIO_AVAIL_LIST;
465 case IIO_CHAN_INFO_SAMP_FREQ:
466 *type = IIO_VAL_INT_PLUS_MICRO;
467 *length = ARRAY_SIZE(sx9324_samp_freq_table) * 2;
468 *vals = (int *)sx9324_samp_freq_table;
469 return IIO_AVAIL_LIST;
470 default:
471 return -EINVAL;
472 }
473}
474
475static int sx9324_set_samp_freq(struct sx_common_data *data,
476 int val, int val2)
477{
478 int i;
479
480 for (i = 0; i < ARRAY_SIZE(sx9324_samp_freq_table); i++)
481 if (val == sx9324_samp_freq_table[i].val &&
482 val2 == sx9324_samp_freq_table[i].val2)
483 break;
484
485 if (i == ARRAY_SIZE(sx9324_samp_freq_table))
486 return -EINVAL;
487
488 guard(mutex)(T: &data->mutex);
489
490 return regmap_update_bits(map: data->regmap,
491 SX9324_REG_GNRL_CTRL0,
492 SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, val: i);
493}
494
495static int sx9324_read_thresh(struct sx_common_data *data,
496 const struct iio_chan_spec *chan, int *val)
497{
498 unsigned int regval;
499 unsigned int reg;
500 int ret;
501
502 /*
503 * TODO(gwendal): Depending on the phase function
504 * (proximity/table/body), retrieve the right threshold.
505 * For now, return the proximity threshold.
506 */
507 reg = SX9324_REG_PROX_CTRL6 + chan->channel / 2;
508 ret = regmap_read(map: data->regmap, reg, val: &regval);
509 if (ret)
510 return ret;
511
512 if (regval <= 1)
513 *val = regval;
514 else
515 *val = (regval * regval) / 2;
516
517 return IIO_VAL_INT;
518}
519
520static int sx9324_read_hysteresis(struct sx_common_data *data,
521 const struct iio_chan_spec *chan, int *val)
522{
523 unsigned int regval, pthresh;
524 int ret;
525
526 ret = sx9324_read_thresh(data, chan, val: &pthresh);
527 if (ret < 0)
528 return ret;
529
530 ret = regmap_read(map: data->regmap, SX9324_REG_PROX_CTRL5, val: &regval);
531 if (ret)
532 return ret;
533
534 regval = FIELD_GET(SX9324_REG_PROX_CTRL5_HYST_MASK, regval);
535 if (!regval)
536 *val = 0;
537 else
538 *val = pthresh >> (5 - regval);
539
540 return IIO_VAL_INT;
541}
542
543static int sx9324_read_far_debounce(struct sx_common_data *data, int *val)
544{
545 unsigned int regval;
546 int ret;
547
548 ret = regmap_read(map: data->regmap, SX9324_REG_PROX_CTRL5, val: &regval);
549 if (ret)
550 return ret;
551
552 regval = FIELD_GET(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, regval);
553 if (regval)
554 *val = 1 << regval;
555 else
556 *val = 0;
557
558 return IIO_VAL_INT;
559}
560
561static int sx9324_read_close_debounce(struct sx_common_data *data, int *val)
562{
563 unsigned int regval;
564 int ret;
565
566 ret = regmap_read(map: data->regmap, SX9324_REG_PROX_CTRL5, val: &regval);
567 if (ret)
568 return ret;
569
570 regval = FIELD_GET(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, regval);
571 if (regval)
572 *val = 1 << regval;
573 else
574 *val = 0;
575
576 return IIO_VAL_INT;
577}
578
579static int sx9324_read_event_val(struct iio_dev *indio_dev,
580 const struct iio_chan_spec *chan,
581 enum iio_event_type type,
582 enum iio_event_direction dir,
583 enum iio_event_info info, int *val, int *val2)
584{
585 struct sx_common_data *data = iio_priv(indio_dev);
586
587 if (chan->type != IIO_PROXIMITY)
588 return -EINVAL;
589
590 switch (info) {
591 case IIO_EV_INFO_VALUE:
592 return sx9324_read_thresh(data, chan, val);
593 case IIO_EV_INFO_PERIOD:
594 switch (dir) {
595 case IIO_EV_DIR_RISING:
596 return sx9324_read_far_debounce(data, val);
597 case IIO_EV_DIR_FALLING:
598 return sx9324_read_close_debounce(data, val);
599 default:
600 return -EINVAL;
601 }
602 case IIO_EV_INFO_HYSTERESIS:
603 return sx9324_read_hysteresis(data, chan, val);
604 default:
605 return -EINVAL;
606 }
607}
608
609static int sx9324_write_thresh(struct sx_common_data *data,
610 const struct iio_chan_spec *chan, int _val)
611{
612 unsigned int reg, val = _val;
613
614 reg = SX9324_REG_PROX_CTRL6 + chan->channel / 2;
615
616 if (val >= 1)
617 val = int_sqrt(2 * val);
618
619 if (val > 0xff)
620 return -EINVAL;
621
622 guard(mutex)(T: &data->mutex);
623
624 return regmap_write(map: data->regmap, reg, val);
625}
626
627static int sx9324_write_hysteresis(struct sx_common_data *data,
628 const struct iio_chan_spec *chan, int _val)
629{
630 unsigned int hyst, val = _val;
631 int ret, pthresh;
632
633 ret = sx9324_read_thresh(data, chan, val: &pthresh);
634 if (ret < 0)
635 return ret;
636
637 if (val == 0)
638 hyst = 0;
639 else if (val >= pthresh >> 2)
640 hyst = 3;
641 else if (val >= pthresh >> 3)
642 hyst = 2;
643 else if (val >= pthresh >> 4)
644 hyst = 1;
645 else
646 return -EINVAL;
647
648 hyst = FIELD_PREP(SX9324_REG_PROX_CTRL5_HYST_MASK, hyst);
649 guard(mutex)(T: &data->mutex);
650
651 return regmap_update_bits(map: data->regmap, SX9324_REG_PROX_CTRL5,
652 SX9324_REG_PROX_CTRL5_HYST_MASK, val: hyst);
653}
654
655static int sx9324_write_far_debounce(struct sx_common_data *data, int _val)
656{
657 unsigned int regval, val = _val;
658
659 if (val > 0)
660 val = ilog2(val);
661 if (!FIELD_FIT(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, val))
662 return -EINVAL;
663
664 regval = FIELD_PREP(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, val);
665
666 guard(mutex)(T: &data->mutex);
667
668 return regmap_update_bits(map: data->regmap, SX9324_REG_PROX_CTRL5,
669 SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK,
670 val: regval);
671}
672
673static int sx9324_write_close_debounce(struct sx_common_data *data, int _val)
674{
675 unsigned int regval, val = _val;
676
677 if (val > 0)
678 val = ilog2(val);
679 if (!FIELD_FIT(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, val))
680 return -EINVAL;
681
682 regval = FIELD_PREP(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, val);
683
684 guard(mutex)(T: &data->mutex);
685
686 return regmap_update_bits(map: data->regmap, SX9324_REG_PROX_CTRL5,
687 SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK,
688 val: regval);
689}
690
691static int sx9324_write_event_val(struct iio_dev *indio_dev,
692 const struct iio_chan_spec *chan,
693 enum iio_event_type type,
694 enum iio_event_direction dir,
695 enum iio_event_info info, int val, int val2)
696{
697 struct sx_common_data *data = iio_priv(indio_dev);
698
699 if (chan->type != IIO_PROXIMITY)
700 return -EINVAL;
701
702 switch (info) {
703 case IIO_EV_INFO_VALUE:
704 return sx9324_write_thresh(data, chan, val: val);
705 case IIO_EV_INFO_PERIOD:
706 switch (dir) {
707 case IIO_EV_DIR_RISING:
708 return sx9324_write_far_debounce(data, val: val);
709 case IIO_EV_DIR_FALLING:
710 return sx9324_write_close_debounce(data, val: val);
711 default:
712 return -EINVAL;
713 }
714 case IIO_EV_INFO_HYSTERESIS:
715 return sx9324_write_hysteresis(data, chan, val: val);
716 default:
717 return -EINVAL;
718 }
719}
720
721static int sx9324_write_gain(struct sx_common_data *data,
722 const struct iio_chan_spec *chan, int val)
723{
724 unsigned int gain, reg;
725
726 reg = SX9324_REG_PROX_CTRL0 + chan->channel / 2;
727
728 gain = ilog2(val) + 1;
729 if (val <= 0 || gain > SX9324_REG_PROX_CTRL0_GAIN_8)
730 return -EINVAL;
731
732 gain = FIELD_PREP(SX9324_REG_PROX_CTRL0_GAIN_MASK, gain);
733
734 guard(mutex)(T: &data->mutex);
735
736 return regmap_update_bits(map: data->regmap, reg,
737 SX9324_REG_PROX_CTRL0_GAIN_MASK,
738 val: gain);
739}
740
741static int sx9324_write_raw(struct iio_dev *indio_dev,
742 const struct iio_chan_spec *chan, int val, int val2,
743 long mask)
744{
745 struct sx_common_data *data = iio_priv(indio_dev);
746
747 switch (mask) {
748 case IIO_CHAN_INFO_SAMP_FREQ:
749 return sx9324_set_samp_freq(data, val, val2);
750 case IIO_CHAN_INFO_HARDWAREGAIN:
751 return sx9324_write_gain(data, chan, val);
752 default:
753 return -EINVAL;
754 }
755}
756
757static const struct sx_common_reg_default sx9324_default_regs[] = {
758 { SX9324_REG_IRQ_MSK, 0x00 },
759 { SX9324_REG_IRQ_CFG0, 0x00, "irq_cfg0" },
760 { SX9324_REG_IRQ_CFG1, SX9324_REG_IRQ_CFG1_FAILCOND, "irq_cfg1" },
761 { SX9324_REG_IRQ_CFG2, 0x00, "irq_cfg2" },
762 { SX9324_REG_GNRL_CTRL0, SX9324_REG_GNRL_CTRL0_SCANPERIOD_100MS, "gnrl_ctrl0" },
763 /*
764 * The lower 4 bits should not be set as it enable sensors measurements.
765 * Turning the detection on before the configuration values are set to
766 * good values can cause the device to return erroneous readings.
767 */
768 { SX9324_REG_GNRL_CTRL1, SX9324_REG_GNRL_CTRL1_PAUSECTRL, "gnrl_ctrl1" },
769
770 { SX9324_REG_AFE_CTRL0, SX9324_REG_AFE_CTRL0_RINT_LOWEST, "afe_ctrl0" },
771 { SX9324_REG_AFE_CTRL3, 0x00, "afe_ctrl3" },
772 { SX9324_REG_AFE_CTRL4, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ |
773 SX9324_REG_AFE_CTRL4_RES_100, "afe_ctrl4" },
774 { SX9324_REG_AFE_CTRL6, 0x00, "afe_ctrl6" },
775 { SX9324_REG_AFE_CTRL7, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ |
776 SX9324_REG_AFE_CTRL4_RES_100, "afe_ctrl7" },
777
778 /* TODO(gwendal): PHx use chip default or all grounded? */
779 { SX9324_REG_AFE_PH0, 0x29, "afe_ph0" },
780 { SX9324_REG_AFE_PH1, 0x26, "afe_ph1" },
781 { SX9324_REG_AFE_PH2, 0x1a, "afe_ph2" },
782 { SX9324_REG_AFE_PH3, 0x16, "afe_ph3" },
783
784 { SX9324_REG_AFE_CTRL8, SX9324_REG_AFE_CTRL8_RESERVED |
785 SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM, "afe_ctrl8" },
786 { SX9324_REG_AFE_CTRL9, SX9324_REG_AFE_CTRL9_AGAIN_1, "afe_ctrl9" },
787
788 { SX9324_REG_PROX_CTRL0,
789 SX9324_REG_PROX_CTRL0_GAIN_1 << SX9324_REG_PROX_CTRL0_GAIN_SHIFT |
790 SX9324_REG_PROX_CTRL0_RAWFILT_1P50, "prox_ctrl0" },
791 { SX9324_REG_PROX_CTRL1,
792 SX9324_REG_PROX_CTRL0_GAIN_1 << SX9324_REG_PROX_CTRL0_GAIN_SHIFT |
793 SX9324_REG_PROX_CTRL0_RAWFILT_1P50, "prox_ctrl1" },
794 { SX9324_REG_PROX_CTRL2, SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K, "prox_ctrl2" },
795 { SX9324_REG_PROX_CTRL3, SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES |
796 SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K, "prox_ctrl3" },
797 { SX9324_REG_PROX_CTRL4, SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 |
798 SX9324_REG_PROX_CTRL4_AVGPOS_FILT_256, "prox_ctrl4" },
799 { SX9324_REG_PROX_CTRL5, 0x00, "prox_ctrl5" },
800 { SX9324_REG_PROX_CTRL6, SX9324_REG_PROX_CTRL6_PROXTHRESH_32, "prox_ctrl6" },
801 { SX9324_REG_PROX_CTRL7, SX9324_REG_PROX_CTRL6_PROXTHRESH_32, "prox_ctrl7" },
802 { SX9324_REG_ADV_CTRL0, 0x00, "adv_ctrl0" },
803 { SX9324_REG_ADV_CTRL1, 0x00, "adv_ctrl1" },
804 { SX9324_REG_ADV_CTRL2, 0x00, "adv_ctrl2" },
805 { SX9324_REG_ADV_CTRL3, 0x00, "adv_ctrl3" },
806 { SX9324_REG_ADV_CTRL4, 0x00, "adv_ctrl4" },
807 { SX9324_REG_ADV_CTRL5, SX9324_REG_ADV_CTRL5_STARTUP_SENSOR_1 |
808 SX9324_REG_ADV_CTRL5_STARTUP_METHOD_1, "adv_ctrl5" },
809 { SX9324_REG_ADV_CTRL6, 0x00, "adv_ctrl6" },
810 { SX9324_REG_ADV_CTRL7, 0x00, "adv_ctrl7" },
811 { SX9324_REG_ADV_CTRL8, 0x00, "adv_ctrl8" },
812 { SX9324_REG_ADV_CTRL9, 0x00, "adv_ctrl9" },
813 /* Body/Table threshold */
814 { SX9324_REG_ADV_CTRL10, 0x00, "adv_ctrl10" },
815 { SX9324_REG_ADV_CTRL11, 0x00, "adv_ctrl11" },
816 { SX9324_REG_ADV_CTRL12, 0x00, "adv_ctrl12" },
817 /* TODO(gwendal): SAR currenly disabled */
818 { SX9324_REG_ADV_CTRL13, 0x00, "adv_ctrl13" },
819 { SX9324_REG_ADV_CTRL14, 0x00, "adv_ctrl14" },
820 { SX9324_REG_ADV_CTRL15, 0x00, "adv_ctrl15" },
821 { SX9324_REG_ADV_CTRL16, 0x00, "adv_ctrl16" },
822 { SX9324_REG_ADV_CTRL17, 0x00, "adv_ctrl17" },
823 { SX9324_REG_ADV_CTRL18, 0x00, "adv_ctrl18" },
824 { SX9324_REG_ADV_CTRL19,
825 SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION, "adv_ctrl19" },
826 { SX9324_REG_ADV_CTRL20,
827 SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION, "adv_ctrl20" },
828};
829
830/* Activate all channels and perform an initial compensation. */
831static int sx9324_init_compensation(struct iio_dev *indio_dev)
832{
833 struct sx_common_data *data = iio_priv(indio_dev);
834 unsigned int val;
835 int ret;
836
837 /* run the compensation phase on all channels */
838 ret = regmap_update_bits(map: data->regmap, SX9324_REG_STAT2,
839 SX9324_REG_STAT2_COMPSTAT_MASK,
840 SX9324_REG_STAT2_COMPSTAT_MASK);
841 if (ret)
842 return ret;
843
844 return regmap_read_poll_timeout(data->regmap, SX9324_REG_STAT2, val,
845 !(val & SX9324_REG_STAT2_COMPSTAT_MASK),
846 20000, 2000000);
847}
848
849static u8 sx9324_parse_phase_prop(struct device *dev,
850 struct sx_common_reg_default *reg_def,
851 const char *prop)
852{
853 unsigned int pin_defs[SX9324_NUM_PINS];
854 int count, ret, pin;
855 u32 raw = 0;
856
857 count = device_property_count_u32(dev, propname: prop);
858 if (count != ARRAY_SIZE(pin_defs))
859 return reg_def->def;
860 ret = device_property_read_u32_array(dev, propname: prop, val: pin_defs,
861 ARRAY_SIZE(pin_defs));
862 if (ret)
863 return reg_def->def;
864
865 for (pin = 0; pin < SX9324_NUM_PINS; pin++)
866 raw |= (pin_defs[pin] << (2 * pin)) &
867 SX9324_REG_AFE_PH0_PIN_MASK(pin);
868
869 return raw;
870}
871
872static const struct sx_common_reg_default *
873sx9324_get_default_reg(struct device *dev, int idx,
874 struct sx_common_reg_default *reg_def)
875{
876 static const char * const sx9324_rints[] = { "lowest", "low", "high",
877 "highest" };
878 static const char * const sx9324_csidle[] = { "hi-z", "hi-z", "gnd",
879 "vdd" };
880 u32 start = 0, raw = 0, pos = 0;
881 const char *prop;
882 int ret;
883
884 memcpy(reg_def, &sx9324_default_regs[idx], sizeof(*reg_def));
885
886 sx_common_get_raw_register_config(dev, reg_def);
887 switch (reg_def->reg) {
888 case SX9324_REG_AFE_PH0:
889 reg_def->def = sx9324_parse_phase_prop(dev, reg_def,
890 prop: "semtech,ph0-pin");
891 break;
892 case SX9324_REG_AFE_PH1:
893 reg_def->def = sx9324_parse_phase_prop(dev, reg_def,
894 prop: "semtech,ph1-pin");
895 break;
896 case SX9324_REG_AFE_PH2:
897 reg_def->def = sx9324_parse_phase_prop(dev, reg_def,
898 prop: "semtech,ph2-pin");
899 break;
900 case SX9324_REG_AFE_PH3:
901 reg_def->def = sx9324_parse_phase_prop(dev, reg_def,
902 prop: "semtech,ph3-pin");
903 break;
904 case SX9324_REG_AFE_CTRL0:
905 ret = device_property_match_property_string(dev, propname: "semtech,cs-idle-sleep",
906 array: sx9324_csidle,
907 ARRAY_SIZE(sx9324_csidle));
908 if (ret >= 0) {
909 reg_def->def &= ~SX9324_REG_AFE_CTRL0_CSIDLE_MASK;
910 reg_def->def |= ret << SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT;
911 }
912
913 ret = device_property_match_property_string(dev, propname: "semtech,int-comp-resistor",
914 array: sx9324_rints,
915 ARRAY_SIZE(sx9324_rints));
916 if (ret >= 0) {
917 reg_def->def &= ~SX9324_REG_AFE_CTRL0_RINT_MASK;
918 reg_def->def |= ret << SX9324_REG_AFE_CTRL0_RINT_SHIFT;
919 }
920 break;
921 case SX9324_REG_AFE_CTRL4:
922 case SX9324_REG_AFE_CTRL7:
923 if (reg_def->reg == SX9324_REG_AFE_CTRL4)
924 prop = "semtech,ph01-resolution";
925 else
926 prop = "semtech,ph23-resolution";
927
928 ret = device_property_read_u32(dev, propname: prop, val: &raw);
929 if (ret)
930 break;
931
932 raw = ilog2(raw) - 3;
933
934 reg_def->def &= ~SX9324_REG_AFE_CTRL4_RESOLUTION_MASK;
935 reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL4_RESOLUTION_MASK,
936 raw);
937 break;
938 case SX9324_REG_AFE_CTRL8:
939 ret = device_property_read_u32(dev,
940 propname: "semtech,input-precharge-resistor-ohms",
941 val: &raw);
942 if (ret)
943 break;
944
945 reg_def->def &= ~SX9324_REG_AFE_CTRL8_RESFILTIN_MASK;
946 reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL8_RESFILTIN_MASK,
947 raw / 2000);
948 break;
949
950 case SX9324_REG_AFE_CTRL9:
951 ret = device_property_read_u32(dev,
952 propname: "semtech,input-analog-gain", val: &raw);
953 if (ret)
954 break;
955 /*
956 * The analog gain has the following setting:
957 * +---------+----------------+----------------+
958 * | dt(raw) | physical value | register value |
959 * +---------+----------------+----------------+
960 * | 0 | x1.247 | 6 |
961 * | 1 | x1 | 8 |
962 * | 2 | x0.768 | 11 |
963 * | 3 | x0.552 | 15 |
964 * +---------+----------------+----------------+
965 */
966 reg_def->def &= ~SX9324_REG_AFE_CTRL9_AGAIN_MASK;
967 reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL9_AGAIN_MASK,
968 6 + raw * (raw + 3) / 2);
969 break;
970
971 case SX9324_REG_ADV_CTRL5:
972 ret = device_property_read_u32(dev, propname: "semtech,startup-sensor",
973 val: &start);
974 if (ret)
975 break;
976
977 reg_def->def &= ~SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK;
978 reg_def->def |= FIELD_PREP(SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK,
979 start);
980 break;
981 case SX9324_REG_PROX_CTRL4:
982 ret = device_property_read_u32(dev, propname: "semtech,avg-pos-strength",
983 val: &pos);
984 if (ret)
985 break;
986
987 /* Powers of 2, except for a gap between 16 and 64 */
988 raw = clamp(ilog2(pos), 3, 11) - (pos >= 32 ? 4 : 3);
989
990 reg_def->def &= ~SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK;
991 reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK,
992 raw);
993 break;
994 case SX9324_REG_PROX_CTRL0:
995 case SX9324_REG_PROX_CTRL1:
996 if (reg_def->reg == SX9324_REG_PROX_CTRL0)
997 prop = "semtech,ph01-proxraw-strength";
998 else
999 prop = "semtech,ph23-proxraw-strength";
1000 ret = device_property_read_u32(dev, propname: prop, val: &raw);
1001 if (ret)
1002 break;
1003
1004 reg_def->def &= ~SX9324_REG_PROX_CTRL0_RAWFILT_MASK;
1005 reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL0_RAWFILT_MASK,
1006 raw);
1007 break;
1008 }
1009 return reg_def;
1010}
1011
1012static int sx9324_check_whoami(struct device *dev,
1013 struct iio_dev *indio_dev)
1014{
1015 /*
1016 * Only one sensor for this driver. Assuming the device tree
1017 * is correct, just set the sensor name.
1018 */
1019 indio_dev->name = "sx9324";
1020 return 0;
1021}
1022
1023static const struct sx_common_chip_info sx9324_chip_info = {
1024 .reg_stat = SX9324_REG_STAT0,
1025 .reg_irq_msk = SX9324_REG_IRQ_MSK,
1026 .reg_enable_chan = SX9324_REG_GNRL_CTRL1,
1027 .reg_reset = SX9324_REG_RESET,
1028
1029 .mask_enable_chan = SX9324_REG_GNRL_CTRL1_PHEN_MASK,
1030 .irq_msk_offset = 3,
1031 .num_channels = SX9324_NUM_CHANNELS,
1032 .num_default_regs = ARRAY_SIZE(sx9324_default_regs),
1033
1034 .ops = {
1035 .read_prox_data = sx9324_read_prox_data,
1036 .check_whoami = sx9324_check_whoami,
1037 .init_compensation = sx9324_init_compensation,
1038 .wait_for_sample = sx9324_wait_for_sample,
1039 .get_default_reg = sx9324_get_default_reg,
1040 },
1041
1042 .iio_channels = sx9324_channels,
1043 .num_iio_channels = ARRAY_SIZE(sx9324_channels),
1044 .iio_info = {
1045 .read_raw = sx9324_read_raw,
1046 .read_avail = sx9324_read_avail,
1047 .read_event_value = sx9324_read_event_val,
1048 .write_event_value = sx9324_write_event_val,
1049 .write_raw = sx9324_write_raw,
1050 .read_event_config = sx_common_read_event_config,
1051 .write_event_config = sx_common_write_event_config,
1052 },
1053};
1054
1055static int sx9324_probe(struct i2c_client *client)
1056{
1057 return sx_common_probe(client, chip_info: &sx9324_chip_info, regmap_config: &sx9324_regmap_config);
1058}
1059
1060static int sx9324_suspend(struct device *dev)
1061{
1062 struct sx_common_data *data = iio_priv(indio_dev: dev_get_drvdata(dev));
1063 unsigned int regval;
1064 int ret;
1065
1066 disable_irq_nosync(irq: data->client->irq);
1067
1068 guard(mutex)(T: &data->mutex);
1069 ret = regmap_read(map: data->regmap, SX9324_REG_GNRL_CTRL1, val: &regval);
1070 if (ret < 0)
1071 return ret;
1072
1073 data->suspend_ctrl =
1074 FIELD_GET(SX9324_REG_GNRL_CTRL1_PHEN_MASK, regval);
1075
1076
1077 /* Disable all phases, send the device to sleep. */
1078 return regmap_write(map: data->regmap, SX9324_REG_GNRL_CTRL1, val: 0);
1079}
1080
1081static int sx9324_resume(struct device *dev)
1082{
1083 struct sx_common_data *data = iio_priv(indio_dev: dev_get_drvdata(dev));
1084
1085 scoped_guard(mutex, &data->mutex) {
1086 int ret = regmap_write(map: data->regmap, SX9324_REG_GNRL_CTRL1,
1087 val: data->suspend_ctrl |
1088 SX9324_REG_GNRL_CTRL1_PAUSECTRL);
1089 if (ret)
1090 return ret;
1091 }
1092
1093 enable_irq(irq: data->client->irq);
1094 return 0;
1095}
1096
1097static DEFINE_SIMPLE_DEV_PM_OPS(sx9324_pm_ops, sx9324_suspend, sx9324_resume);
1098
1099static const struct acpi_device_id sx9324_acpi_match[] = {
1100 { "STH9324", SX9324_WHOAMI_VALUE },
1101 { }
1102};
1103MODULE_DEVICE_TABLE(acpi, sx9324_acpi_match);
1104
1105static const struct of_device_id sx9324_of_match[] = {
1106 { .compatible = "semtech,sx9324", (void *)SX9324_WHOAMI_VALUE },
1107 { }
1108};
1109MODULE_DEVICE_TABLE(of, sx9324_of_match);
1110
1111static const struct i2c_device_id sx9324_id[] = {
1112 { "sx9324", SX9324_WHOAMI_VALUE },
1113 { }
1114};
1115MODULE_DEVICE_TABLE(i2c, sx9324_id);
1116
1117static struct i2c_driver sx9324_driver = {
1118 .driver = {
1119 .name = "sx9324",
1120 .acpi_match_table = sx9324_acpi_match,
1121 .of_match_table = sx9324_of_match,
1122 .pm = pm_sleep_ptr(&sx9324_pm_ops),
1123
1124 /*
1125 * Lots of i2c transfers in probe + over 200 ms waiting in
1126 * sx9324_init_compensation() mean a slow probe; prefer async
1127 * so we don't delay boot if we're builtin to the kernel.
1128 */
1129 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1130 },
1131 .probe = sx9324_probe,
1132 .id_table = sx9324_id,
1133};
1134module_i2c_driver(sx9324_driver);
1135
1136MODULE_AUTHOR("Gwendal Grignou <gwendal@chromium.org>");
1137MODULE_DESCRIPTION("Driver for Semtech SX9324 proximity sensor");
1138MODULE_LICENSE("GPL v2");
1139MODULE_IMPORT_NS(SEMTECH_PROX);
1140

source code of linux/drivers/iio/proximity/sx9324.c