1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2021 Google LLC.
4 *
5 * Driver for Semtech's SX9324 capacitive proximity/button solution.
6 * Based on SX9324 driver and copy of datasheet at:
7 * https://edit.wpgdadawant.com/uploads/news_file/program/2019/30184/tech_files/program_30184_suggest_other_file.pdf
8 */
9
10#include <linux/acpi.h>
11#include <linux/bits.h>
12#include <linux/bitfield.h>
13#include <linux/delay.h>
14#include <linux/i2c.h>
15#include <linux/interrupt.h>
16#include <linux/kernel.h>
17#include <linux/log2.h>
18#include <linux/mod_devicetable.h>
19#include <linux/module.h>
20#include <linux/pm.h>
21#include <linux/property.h>
22#include <linux/regmap.h>
23
24#include <linux/iio/iio.h>
25
26#include "sx_common.h"
27
28/* Register definitions. */
29#define SX9324_REG_IRQ_SRC SX_COMMON_REG_IRQ_SRC
30#define SX9324_REG_STAT0 0x01
31#define SX9324_REG_STAT1 0x02
32#define SX9324_REG_STAT2 0x03
33#define SX9324_REG_STAT2_COMPSTAT_MASK GENMASK(3, 0)
34#define SX9324_REG_STAT3 0x04
35#define SX9324_REG_IRQ_MSK 0x05
36#define SX9324_CONVDONE_IRQ BIT(3)
37#define SX9324_FAR_IRQ BIT(5)
38#define SX9324_CLOSE_IRQ BIT(6)
39#define SX9324_REG_IRQ_CFG0 0x06
40#define SX9324_REG_IRQ_CFG1 0x07
41#define SX9324_REG_IRQ_CFG1_FAILCOND 0x80
42#define SX9324_REG_IRQ_CFG2 0x08
43
44#define SX9324_REG_GNRL_CTRL0 0x10
45#define SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK GENMASK(4, 0)
46#define SX9324_REG_GNRL_CTRL0_SCANPERIOD_100MS 0x16
47#define SX9324_REG_GNRL_CTRL1 0x11
48#define SX9324_REG_GNRL_CTRL1_PHEN_MASK GENMASK(3, 0)
49#define SX9324_REG_GNRL_CTRL1_PAUSECTRL 0x20
50
51#define SX9324_REG_I2C_ADDR 0x14
52#define SX9324_REG_CLK_SPRD 0x15
53
54#define SX9324_REG_AFE_CTRL0 0x20
55#define SX9324_REG_AFE_CTRL0_RINT_SHIFT 6
56#define SX9324_REG_AFE_CTRL0_RINT_MASK \
57 GENMASK(SX9324_REG_AFE_CTRL0_RINT_SHIFT + 1, \
58 SX9324_REG_AFE_CTRL0_RINT_SHIFT)
59#define SX9324_REG_AFE_CTRL0_RINT_LOWEST 0x00
60#define SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT 4
61#define SX9324_REG_AFE_CTRL0_CSIDLE_MASK \
62 GENMASK(SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT + 1, \
63 SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT)
64#define SX9324_REG_AFE_CTRL0_RINT_LOWEST 0x00
65#define SX9324_REG_AFE_CTRL1 0x21
66#define SX9324_REG_AFE_CTRL2 0x22
67#define SX9324_REG_AFE_CTRL3 0x23
68#define SX9324_REG_AFE_CTRL4 0x24
69#define SX9324_REG_AFE_CTRL4_FREQ_83_33HZ 0x40
70#define SX9324_REG_AFE_CTRL4_RESOLUTION_MASK GENMASK(2, 0)
71#define SX9324_REG_AFE_CTRL4_RES_100 0x04
72#define SX9324_REG_AFE_CTRL5 0x25
73#define SX9324_REG_AFE_CTRL6 0x26
74#define SX9324_REG_AFE_CTRL7 0x27
75#define SX9324_REG_AFE_PH0 0x28
76#define SX9324_REG_AFE_PH0_PIN_MASK(_pin) \
77 GENMASK(2 * (_pin) + 1, 2 * (_pin))
78
79#define SX9324_REG_AFE_PH1 0x29
80#define SX9324_REG_AFE_PH2 0x2a
81#define SX9324_REG_AFE_PH3 0x2b
82#define SX9324_REG_AFE_CTRL8 0x2c
83#define SX9324_REG_AFE_CTRL8_RESERVED 0x10
84#define SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM 0x02
85#define SX9324_REG_AFE_CTRL8_RESFILTIN_MASK GENMASK(3, 0)
86#define SX9324_REG_AFE_CTRL9 0x2d
87#define SX9324_REG_AFE_CTRL9_AGAIN_MASK GENMASK(3, 0)
88#define SX9324_REG_AFE_CTRL9_AGAIN_1 0x08
89
90#define SX9324_REG_PROX_CTRL0 0x30
91#define SX9324_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3)
92#define SX9324_REG_PROX_CTRL0_GAIN_SHIFT 3
93#define SX9324_REG_PROX_CTRL0_GAIN_RSVD 0x0
94#define SX9324_REG_PROX_CTRL0_GAIN_1 0x1
95#define SX9324_REG_PROX_CTRL0_GAIN_8 0x4
96#define SX9324_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0)
97#define SX9324_REG_PROX_CTRL0_RAWFILT_1P50 0x01
98#define SX9324_REG_PROX_CTRL1 0x31
99#define SX9324_REG_PROX_CTRL2 0x32
100#define SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K 0x20
101#define SX9324_REG_PROX_CTRL3 0x33
102#define SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES 0x40
103#define SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K 0x20
104#define SX9324_REG_PROX_CTRL4 0x34
105#define SX9324_REG_PROX_CTRL4_AVGNEGFILT_MASK GENMASK(5, 3)
106#define SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 0x08
107#define SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK GENMASK(2, 0)
108#define SX9324_REG_PROX_CTRL4_AVGPOS_FILT_256 0x04
109#define SX9324_REG_PROX_CTRL5 0x35
110#define SX9324_REG_PROX_CTRL5_HYST_MASK GENMASK(5, 4)
111#define SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK GENMASK(3, 2)
112#define SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK GENMASK(1, 0)
113#define SX9324_REG_PROX_CTRL6 0x36
114#define SX9324_REG_PROX_CTRL6_PROXTHRESH_32 0x08
115#define SX9324_REG_PROX_CTRL7 0x37
116
117#define SX9324_REG_ADV_CTRL0 0x40
118#define SX9324_REG_ADV_CTRL1 0x41
119#define SX9324_REG_ADV_CTRL2 0x42
120#define SX9324_REG_ADV_CTRL3 0x43
121#define SX9324_REG_ADV_CTRL4 0x44
122#define SX9324_REG_ADV_CTRL5 0x45
123#define SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK GENMASK(3, 2)
124#define SX9324_REG_ADV_CTRL5_STARTUP_SENSOR_1 0x04
125#define SX9324_REG_ADV_CTRL5_STARTUP_METHOD_1 0x01
126#define SX9324_REG_ADV_CTRL6 0x46
127#define SX9324_REG_ADV_CTRL7 0x47
128#define SX9324_REG_ADV_CTRL8 0x48
129#define SX9324_REG_ADV_CTRL9 0x49
130#define SX9324_REG_ADV_CTRL10 0x4a
131#define SX9324_REG_ADV_CTRL11 0x4b
132#define SX9324_REG_ADV_CTRL12 0x4c
133#define SX9324_REG_ADV_CTRL13 0x4d
134#define SX9324_REG_ADV_CTRL14 0x4e
135#define SX9324_REG_ADV_CTRL15 0x4f
136#define SX9324_REG_ADV_CTRL16 0x50
137#define SX9324_REG_ADV_CTRL17 0x51
138#define SX9324_REG_ADV_CTRL18 0x52
139#define SX9324_REG_ADV_CTRL19 0x53
140#define SX9324_REG_ADV_CTRL20 0x54
141#define SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION 0xf0
142
143#define SX9324_REG_PHASE_SEL 0x60
144
145#define SX9324_REG_USEFUL_MSB 0x61
146#define SX9324_REG_USEFUL_LSB 0x62
147
148#define SX9324_REG_AVG_MSB 0x63
149#define SX9324_REG_AVG_LSB 0x64
150
151#define SX9324_REG_DIFF_MSB 0x65
152#define SX9324_REG_DIFF_LSB 0x66
153
154#define SX9324_REG_OFFSET_MSB 0x67
155#define SX9324_REG_OFFSET_LSB 0x68
156
157#define SX9324_REG_SAR_MSB 0x69
158#define SX9324_REG_SAR_LSB 0x6a
159
160#define SX9324_REG_RESET 0x9f
161/* Write this to REG_RESET to do a soft reset. */
162#define SX9324_SOFT_RESET 0xde
163
164#define SX9324_REG_WHOAMI 0xfa
165#define SX9324_WHOAMI_VALUE 0x23
166
167#define SX9324_REG_REVISION 0xfe
168
169/* 4 channels, as defined in STAT0: PH0, PH1, PH2 and PH3. */
170#define SX9324_NUM_CHANNELS 4
171/* 3 CS pins: CS0, CS1, CS2. */
172#define SX9324_NUM_PINS 3
173
174static const char * const sx9324_cs_pin_usage[] = { "HZ", "MI", "DS", "GD" };
175
176static ssize_t sx9324_phase_configuration_show(struct iio_dev *indio_dev,
177 uintptr_t private,
178 const struct iio_chan_spec *chan,
179 char *buf)
180{
181 struct sx_common_data *data = iio_priv(indio_dev);
182 unsigned int val;
183 int i, ret, pin_idx;
184 size_t len = 0;
185
186 ret = regmap_read(map: data->regmap, SX9324_REG_AFE_PH0 + chan->channel, val: &val);
187 if (ret < 0)
188 return ret;
189
190 for (i = 0; i < SX9324_NUM_PINS; i++) {
191 pin_idx = (val & SX9324_REG_AFE_PH0_PIN_MASK(i)) >> (2 * i);
192 len += sysfs_emit_at(buf, at: len, fmt: "%s,",
193 sx9324_cs_pin_usage[pin_idx]);
194 }
195 buf[len - 1] = '\n';
196 return len;
197}
198
199static const struct iio_chan_spec_ext_info sx9324_channel_ext_info[] = {
200 {
201 .name = "setup",
202 .shared = IIO_SEPARATE,
203 .read = sx9324_phase_configuration_show,
204 },
205 { }
206};
207
208#define SX9324_CHANNEL(idx) \
209{ \
210 .type = IIO_PROXIMITY, \
211 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
212 BIT(IIO_CHAN_INFO_HARDWAREGAIN), \
213 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
214 .info_mask_separate_available = \
215 BIT(IIO_CHAN_INFO_HARDWAREGAIN), \
216 .info_mask_shared_by_all_available = \
217 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
218 .indexed = 1, \
219 .channel = idx, \
220 .address = SX9324_REG_DIFF_MSB, \
221 .event_spec = sx_common_events, \
222 .num_event_specs = ARRAY_SIZE(sx_common_events), \
223 .scan_index = idx, \
224 .scan_type = { \
225 .sign = 's', \
226 .realbits = 12, \
227 .storagebits = 16, \
228 .endianness = IIO_BE, \
229 }, \
230 .ext_info = sx9324_channel_ext_info, \
231}
232
233static const struct iio_chan_spec sx9324_channels[] = {
234 SX9324_CHANNEL(0), /* Phase 0 */
235 SX9324_CHANNEL(1), /* Phase 1 */
236 SX9324_CHANNEL(2), /* Phase 2 */
237 SX9324_CHANNEL(3), /* Phase 3 */
238 IIO_CHAN_SOFT_TIMESTAMP(4),
239};
240
241/*
242 * Each entry contains the integer part (val) and the fractional part, in micro
243 * seconds. It conforms to the IIO output IIO_VAL_INT_PLUS_MICRO.
244 */
245static const struct {
246 int val;
247 int val2;
248} sx9324_samp_freq_table[] = {
249 { 1000, 0 }, /* 00000: Min (no idle time) */
250 { 500, 0 }, /* 00001: 2 ms */
251 { 250, 0 }, /* 00010: 4 ms */
252 { 166, 666666 }, /* 00011: 6 ms */
253 { 125, 0 }, /* 00100: 8 ms */
254 { 100, 0 }, /* 00101: 10 ms */
255 { 71, 428571 }, /* 00110: 14 ms */
256 { 55, 555556 }, /* 00111: 18 ms */
257 { 45, 454545 }, /* 01000: 22 ms */
258 { 38, 461538 }, /* 01001: 26 ms */
259 { 33, 333333 }, /* 01010: 30 ms */
260 { 29, 411765 }, /* 01011: 34 ms */
261 { 26, 315789 }, /* 01100: 38 ms */
262 { 23, 809524 }, /* 01101: 42 ms */
263 { 21, 739130 }, /* 01110: 46 ms */
264 { 20, 0 }, /* 01111: 50 ms */
265 { 17, 857143 }, /* 10000: 56 ms */
266 { 16, 129032 }, /* 10001: 62 ms */
267 { 14, 705882 }, /* 10010: 68 ms */
268 { 13, 513514 }, /* 10011: 74 ms */
269 { 12, 500000 }, /* 10100: 80 ms */
270 { 11, 111111 }, /* 10101: 90 ms */
271 { 10, 0 }, /* 10110: 100 ms (Typ.) */
272 { 5, 0 }, /* 10111: 200 ms */
273 { 3, 333333 }, /* 11000: 300 ms */
274 { 2, 500000 }, /* 11001: 400 ms */
275 { 1, 666667 }, /* 11010: 600 ms */
276 { 1, 250000 }, /* 11011: 800 ms */
277 { 1, 0 }, /* 11100: 1 s */
278 { 0, 500000 }, /* 11101: 2 s */
279 { 0, 333333 }, /* 11110: 3 s */
280 { 0, 250000 }, /* 11111: 4 s */
281};
282
283static const unsigned int sx9324_scan_period_table[] = {
284 2, 15, 30, 45, 60, 90, 120, 200,
285 400, 600, 800, 1000, 2000, 3000, 4000, 5000,
286};
287
288static const struct regmap_range sx9324_writable_reg_ranges[] = {
289 /*
290 * To set COMPSTAT for compensation, even if datasheet says register is
291 * RO.
292 */
293 regmap_reg_range(SX9324_REG_STAT2, SX9324_REG_STAT2),
294 regmap_reg_range(SX9324_REG_IRQ_MSK, SX9324_REG_IRQ_CFG2),
295 regmap_reg_range(SX9324_REG_GNRL_CTRL0, SX9324_REG_GNRL_CTRL1),
296 /* Leave i2c and clock spreading as unavailable */
297 regmap_reg_range(SX9324_REG_AFE_CTRL0, SX9324_REG_AFE_CTRL9),
298 regmap_reg_range(SX9324_REG_PROX_CTRL0, SX9324_REG_PROX_CTRL7),
299 regmap_reg_range(SX9324_REG_ADV_CTRL0, SX9324_REG_ADV_CTRL20),
300 regmap_reg_range(SX9324_REG_PHASE_SEL, SX9324_REG_PHASE_SEL),
301 regmap_reg_range(SX9324_REG_OFFSET_MSB, SX9324_REG_OFFSET_LSB),
302 regmap_reg_range(SX9324_REG_RESET, SX9324_REG_RESET),
303};
304
305static const struct regmap_access_table sx9324_writeable_regs = {
306 .yes_ranges = sx9324_writable_reg_ranges,
307 .n_yes_ranges = ARRAY_SIZE(sx9324_writable_reg_ranges),
308};
309
310/*
311 * All allocated registers are readable, so we just list unallocated
312 * ones.
313 */
314static const struct regmap_range sx9324_non_readable_reg_ranges[] = {
315 regmap_reg_range(SX9324_REG_IRQ_CFG2 + 1, SX9324_REG_GNRL_CTRL0 - 1),
316 regmap_reg_range(SX9324_REG_GNRL_CTRL1 + 1, SX9324_REG_AFE_CTRL0 - 1),
317 regmap_reg_range(SX9324_REG_AFE_CTRL9 + 1, SX9324_REG_PROX_CTRL0 - 1),
318 regmap_reg_range(SX9324_REG_PROX_CTRL7 + 1, SX9324_REG_ADV_CTRL0 - 1),
319 regmap_reg_range(SX9324_REG_ADV_CTRL20 + 1, SX9324_REG_PHASE_SEL - 1),
320 regmap_reg_range(SX9324_REG_SAR_LSB + 1, SX9324_REG_RESET - 1),
321 regmap_reg_range(SX9324_REG_RESET + 1, SX9324_REG_WHOAMI - 1),
322 regmap_reg_range(SX9324_REG_WHOAMI + 1, SX9324_REG_REVISION - 1),
323};
324
325static const struct regmap_access_table sx9324_readable_regs = {
326 .no_ranges = sx9324_non_readable_reg_ranges,
327 .n_no_ranges = ARRAY_SIZE(sx9324_non_readable_reg_ranges),
328};
329
330static const struct regmap_range sx9324_volatile_reg_ranges[] = {
331 regmap_reg_range(SX9324_REG_IRQ_SRC, SX9324_REG_STAT3),
332 regmap_reg_range(SX9324_REG_USEFUL_MSB, SX9324_REG_DIFF_LSB),
333 regmap_reg_range(SX9324_REG_SAR_MSB, SX9324_REG_SAR_LSB),
334 regmap_reg_range(SX9324_REG_WHOAMI, SX9324_REG_WHOAMI),
335 regmap_reg_range(SX9324_REG_REVISION, SX9324_REG_REVISION),
336};
337
338static const struct regmap_access_table sx9324_volatile_regs = {
339 .yes_ranges = sx9324_volatile_reg_ranges,
340 .n_yes_ranges = ARRAY_SIZE(sx9324_volatile_reg_ranges),
341};
342
343static const struct regmap_config sx9324_regmap_config = {
344 .reg_bits = 8,
345 .val_bits = 8,
346
347 .max_register = SX9324_REG_REVISION,
348 .cache_type = REGCACHE_RBTREE,
349
350 .wr_table = &sx9324_writeable_regs,
351 .rd_table = &sx9324_readable_regs,
352 .volatile_table = &sx9324_volatile_regs,
353};
354
355static int sx9324_read_prox_data(struct sx_common_data *data,
356 const struct iio_chan_spec *chan,
357 __be16 *val)
358{
359 int ret;
360
361 ret = regmap_write(map: data->regmap, SX9324_REG_PHASE_SEL, val: chan->channel);
362 if (ret < 0)
363 return ret;
364
365 return regmap_bulk_read(map: data->regmap, reg: chan->address, val, val_count: sizeof(*val));
366}
367
368/*
369 * If we have no interrupt support, we have to wait for a scan period
370 * after enabling a channel to get a result.
371 */
372static int sx9324_wait_for_sample(struct sx_common_data *data)
373{
374 int ret;
375 unsigned int val;
376
377 ret = regmap_read(map: data->regmap, SX9324_REG_GNRL_CTRL0, val: &val);
378 if (ret < 0)
379 return ret;
380 val = FIELD_GET(SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, val);
381
382 msleep(msecs: sx9324_scan_period_table[val]);
383
384 return 0;
385}
386
387static int sx9324_read_gain(struct sx_common_data *data,
388 const struct iio_chan_spec *chan, int *val)
389{
390 unsigned int reg, regval;
391 int ret;
392
393 reg = SX9324_REG_PROX_CTRL0 + chan->channel / 2;
394 ret = regmap_read(map: data->regmap, reg, val: &regval);
395 if (ret)
396 return ret;
397
398 regval = FIELD_GET(SX9324_REG_PROX_CTRL0_GAIN_MASK, regval);
399 if (regval)
400 regval--;
401 else if (regval == SX9324_REG_PROX_CTRL0_GAIN_RSVD ||
402 regval > SX9324_REG_PROX_CTRL0_GAIN_8)
403 return -EINVAL;
404
405 *val = 1 << regval;
406
407 return IIO_VAL_INT;
408}
409
410static int sx9324_read_samp_freq(struct sx_common_data *data,
411 int *val, int *val2)
412{
413 int ret;
414 unsigned int regval;
415
416 ret = regmap_read(map: data->regmap, SX9324_REG_GNRL_CTRL0, val: &regval);
417 if (ret)
418 return ret;
419
420 regval = FIELD_GET(SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, regval);
421 *val = sx9324_samp_freq_table[regval].val;
422 *val2 = sx9324_samp_freq_table[regval].val2;
423
424 return IIO_VAL_INT_PLUS_MICRO;
425}
426
427static int sx9324_read_raw(struct iio_dev *indio_dev,
428 const struct iio_chan_spec *chan,
429 int *val, int *val2, long mask)
430{
431 struct sx_common_data *data = iio_priv(indio_dev);
432 int ret;
433
434 switch (mask) {
435 case IIO_CHAN_INFO_RAW:
436 if (!iio_device_claim_direct(indio_dev))
437 return -EBUSY;
438
439 ret = sx_common_read_proximity(data, chan, val);
440 iio_device_release_direct(indio_dev);
441 return ret;
442 case IIO_CHAN_INFO_HARDWAREGAIN:
443 if (!iio_device_claim_direct(indio_dev))
444 return -EBUSY;
445
446 ret = sx9324_read_gain(data, chan, val);
447 iio_device_release_direct(indio_dev);
448 return ret;
449 case IIO_CHAN_INFO_SAMP_FREQ:
450 return sx9324_read_samp_freq(data, val, val2);
451 default:
452 return -EINVAL;
453 }
454}
455
456static const int sx9324_gain_vals[] = { 1, 2, 4, 8 };
457
458static int sx9324_read_avail(struct iio_dev *indio_dev,
459 struct iio_chan_spec const *chan,
460 const int **vals, int *type, int *length,
461 long mask)
462{
463 if (chan->type != IIO_PROXIMITY)
464 return -EINVAL;
465
466 switch (mask) {
467 case IIO_CHAN_INFO_HARDWAREGAIN:
468 *type = IIO_VAL_INT;
469 *length = ARRAY_SIZE(sx9324_gain_vals);
470 *vals = sx9324_gain_vals;
471 return IIO_AVAIL_LIST;
472 case IIO_CHAN_INFO_SAMP_FREQ:
473 *type = IIO_VAL_INT_PLUS_MICRO;
474 *length = ARRAY_SIZE(sx9324_samp_freq_table) * 2;
475 *vals = (int *)sx9324_samp_freq_table;
476 return IIO_AVAIL_LIST;
477 default:
478 return -EINVAL;
479 }
480}
481
482static int sx9324_set_samp_freq(struct sx_common_data *data,
483 int val, int val2)
484{
485 int i;
486
487 for (i = 0; i < ARRAY_SIZE(sx9324_samp_freq_table); i++)
488 if (val == sx9324_samp_freq_table[i].val &&
489 val2 == sx9324_samp_freq_table[i].val2)
490 break;
491
492 if (i == ARRAY_SIZE(sx9324_samp_freq_table))
493 return -EINVAL;
494
495 guard(mutex)(T: &data->mutex);
496
497 return regmap_update_bits(map: data->regmap,
498 SX9324_REG_GNRL_CTRL0,
499 SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, val: i);
500}
501
502static int sx9324_read_thresh(struct sx_common_data *data,
503 const struct iio_chan_spec *chan, int *val)
504{
505 unsigned int regval;
506 unsigned int reg;
507 int ret;
508
509 /*
510 * TODO(gwendal): Depending on the phase function
511 * (proximity/table/body), retrieve the right threshold.
512 * For now, return the proximity threshold.
513 */
514 reg = SX9324_REG_PROX_CTRL6 + chan->channel / 2;
515 ret = regmap_read(map: data->regmap, reg, val: &regval);
516 if (ret)
517 return ret;
518
519 if (regval <= 1)
520 *val = regval;
521 else
522 *val = (regval * regval) / 2;
523
524 return IIO_VAL_INT;
525}
526
527static int sx9324_read_hysteresis(struct sx_common_data *data,
528 const struct iio_chan_spec *chan, int *val)
529{
530 unsigned int regval, pthresh;
531 int ret;
532
533 ret = sx9324_read_thresh(data, chan, val: &pthresh);
534 if (ret < 0)
535 return ret;
536
537 ret = regmap_read(map: data->regmap, SX9324_REG_PROX_CTRL5, val: &regval);
538 if (ret)
539 return ret;
540
541 regval = FIELD_GET(SX9324_REG_PROX_CTRL5_HYST_MASK, regval);
542 if (!regval)
543 *val = 0;
544 else
545 *val = pthresh >> (5 - regval);
546
547 return IIO_VAL_INT;
548}
549
550static int sx9324_read_far_debounce(struct sx_common_data *data, int *val)
551{
552 unsigned int regval;
553 int ret;
554
555 ret = regmap_read(map: data->regmap, SX9324_REG_PROX_CTRL5, val: &regval);
556 if (ret)
557 return ret;
558
559 regval = FIELD_GET(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, regval);
560 if (regval)
561 *val = 1 << regval;
562 else
563 *val = 0;
564
565 return IIO_VAL_INT;
566}
567
568static int sx9324_read_close_debounce(struct sx_common_data *data, int *val)
569{
570 unsigned int regval;
571 int ret;
572
573 ret = regmap_read(map: data->regmap, SX9324_REG_PROX_CTRL5, val: &regval);
574 if (ret)
575 return ret;
576
577 regval = FIELD_GET(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, regval);
578 if (regval)
579 *val = 1 << regval;
580 else
581 *val = 0;
582
583 return IIO_VAL_INT;
584}
585
586static int sx9324_read_event_val(struct iio_dev *indio_dev,
587 const struct iio_chan_spec *chan,
588 enum iio_event_type type,
589 enum iio_event_direction dir,
590 enum iio_event_info info, int *val, int *val2)
591{
592 struct sx_common_data *data = iio_priv(indio_dev);
593
594 if (chan->type != IIO_PROXIMITY)
595 return -EINVAL;
596
597 switch (info) {
598 case IIO_EV_INFO_VALUE:
599 return sx9324_read_thresh(data, chan, val);
600 case IIO_EV_INFO_PERIOD:
601 switch (dir) {
602 case IIO_EV_DIR_RISING:
603 return sx9324_read_far_debounce(data, val);
604 case IIO_EV_DIR_FALLING:
605 return sx9324_read_close_debounce(data, val);
606 default:
607 return -EINVAL;
608 }
609 case IIO_EV_INFO_HYSTERESIS:
610 return sx9324_read_hysteresis(data, chan, val);
611 default:
612 return -EINVAL;
613 }
614}
615
616static int sx9324_write_thresh(struct sx_common_data *data,
617 const struct iio_chan_spec *chan, int _val)
618{
619 unsigned int reg, val = _val;
620
621 reg = SX9324_REG_PROX_CTRL6 + chan->channel / 2;
622
623 if (val >= 1)
624 val = int_sqrt(2 * val);
625
626 if (val > 0xff)
627 return -EINVAL;
628
629 guard(mutex)(T: &data->mutex);
630
631 return regmap_write(map: data->regmap, reg, val);
632}
633
634static int sx9324_write_hysteresis(struct sx_common_data *data,
635 const struct iio_chan_spec *chan, int _val)
636{
637 unsigned int hyst, val = _val;
638 int ret, pthresh;
639
640 ret = sx9324_read_thresh(data, chan, val: &pthresh);
641 if (ret < 0)
642 return ret;
643
644 if (val == 0)
645 hyst = 0;
646 else if (val >= pthresh >> 2)
647 hyst = 3;
648 else if (val >= pthresh >> 3)
649 hyst = 2;
650 else if (val >= pthresh >> 4)
651 hyst = 1;
652 else
653 return -EINVAL;
654
655 hyst = FIELD_PREP(SX9324_REG_PROX_CTRL5_HYST_MASK, hyst);
656 guard(mutex)(T: &data->mutex);
657
658 return regmap_update_bits(map: data->regmap, SX9324_REG_PROX_CTRL5,
659 SX9324_REG_PROX_CTRL5_HYST_MASK, val: hyst);
660}
661
662static int sx9324_write_far_debounce(struct sx_common_data *data, int _val)
663{
664 unsigned int regval, val = _val;
665
666 if (val > 0)
667 val = ilog2(val);
668 if (!FIELD_FIT(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, val))
669 return -EINVAL;
670
671 regval = FIELD_PREP(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, val);
672
673 guard(mutex)(T: &data->mutex);
674
675 return regmap_update_bits(map: data->regmap, SX9324_REG_PROX_CTRL5,
676 SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK,
677 val: regval);
678}
679
680static int sx9324_write_close_debounce(struct sx_common_data *data, int _val)
681{
682 unsigned int regval, val = _val;
683
684 if (val > 0)
685 val = ilog2(val);
686 if (!FIELD_FIT(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, val))
687 return -EINVAL;
688
689 regval = FIELD_PREP(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, val);
690
691 guard(mutex)(T: &data->mutex);
692
693 return regmap_update_bits(map: data->regmap, SX9324_REG_PROX_CTRL5,
694 SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK,
695 val: regval);
696}
697
698static int sx9324_write_event_val(struct iio_dev *indio_dev,
699 const struct iio_chan_spec *chan,
700 enum iio_event_type type,
701 enum iio_event_direction dir,
702 enum iio_event_info info, int val, int val2)
703{
704 struct sx_common_data *data = iio_priv(indio_dev);
705
706 if (chan->type != IIO_PROXIMITY)
707 return -EINVAL;
708
709 switch (info) {
710 case IIO_EV_INFO_VALUE:
711 return sx9324_write_thresh(data, chan, val: val);
712 case IIO_EV_INFO_PERIOD:
713 switch (dir) {
714 case IIO_EV_DIR_RISING:
715 return sx9324_write_far_debounce(data, val: val);
716 case IIO_EV_DIR_FALLING:
717 return sx9324_write_close_debounce(data, val: val);
718 default:
719 return -EINVAL;
720 }
721 case IIO_EV_INFO_HYSTERESIS:
722 return sx9324_write_hysteresis(data, chan, val: val);
723 default:
724 return -EINVAL;
725 }
726}
727
728static int sx9324_write_gain(struct sx_common_data *data,
729 const struct iio_chan_spec *chan, int val)
730{
731 unsigned int gain, reg;
732
733 reg = SX9324_REG_PROX_CTRL0 + chan->channel / 2;
734
735 gain = ilog2(val) + 1;
736 if (val <= 0 || gain > SX9324_REG_PROX_CTRL0_GAIN_8)
737 return -EINVAL;
738
739 gain = FIELD_PREP(SX9324_REG_PROX_CTRL0_GAIN_MASK, gain);
740
741 guard(mutex)(T: &data->mutex);
742
743 return regmap_update_bits(map: data->regmap, reg,
744 SX9324_REG_PROX_CTRL0_GAIN_MASK,
745 val: gain);
746}
747
748static int sx9324_write_raw(struct iio_dev *indio_dev,
749 const struct iio_chan_spec *chan, int val, int val2,
750 long mask)
751{
752 struct sx_common_data *data = iio_priv(indio_dev);
753
754 switch (mask) {
755 case IIO_CHAN_INFO_SAMP_FREQ:
756 return sx9324_set_samp_freq(data, val, val2);
757 case IIO_CHAN_INFO_HARDWAREGAIN:
758 return sx9324_write_gain(data, chan, val);
759 default:
760 return -EINVAL;
761 }
762}
763
764static const struct sx_common_reg_default sx9324_default_regs[] = {
765 { SX9324_REG_IRQ_MSK, 0x00 },
766 { SX9324_REG_IRQ_CFG0, 0x00, "irq_cfg0" },
767 { SX9324_REG_IRQ_CFG1, SX9324_REG_IRQ_CFG1_FAILCOND, "irq_cfg1" },
768 { SX9324_REG_IRQ_CFG2, 0x00, "irq_cfg2" },
769 { SX9324_REG_GNRL_CTRL0, SX9324_REG_GNRL_CTRL0_SCANPERIOD_100MS, "gnrl_ctrl0" },
770 /*
771 * The lower 4 bits should not be set as it enable sensors measurements.
772 * Turning the detection on before the configuration values are set to
773 * good values can cause the device to return erroneous readings.
774 */
775 { SX9324_REG_GNRL_CTRL1, SX9324_REG_GNRL_CTRL1_PAUSECTRL, "gnrl_ctrl1" },
776
777 { SX9324_REG_AFE_CTRL0, SX9324_REG_AFE_CTRL0_RINT_LOWEST, "afe_ctrl0" },
778 { SX9324_REG_AFE_CTRL3, 0x00, "afe_ctrl3" },
779 { SX9324_REG_AFE_CTRL4, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ |
780 SX9324_REG_AFE_CTRL4_RES_100, "afe_ctrl4" },
781 { SX9324_REG_AFE_CTRL6, 0x00, "afe_ctrl6" },
782 { SX9324_REG_AFE_CTRL7, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ |
783 SX9324_REG_AFE_CTRL4_RES_100, "afe_ctrl7" },
784
785 /* TODO(gwendal): PHx use chip default or all grounded? */
786 { SX9324_REG_AFE_PH0, 0x29, "afe_ph0" },
787 { SX9324_REG_AFE_PH1, 0x26, "afe_ph1" },
788 { SX9324_REG_AFE_PH2, 0x1a, "afe_ph2" },
789 { SX9324_REG_AFE_PH3, 0x16, "afe_ph3" },
790
791 { SX9324_REG_AFE_CTRL8, SX9324_REG_AFE_CTRL8_RESERVED |
792 SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM, "afe_ctrl8" },
793 { SX9324_REG_AFE_CTRL9, SX9324_REG_AFE_CTRL9_AGAIN_1, "afe_ctrl9" },
794
795 { SX9324_REG_PROX_CTRL0,
796 SX9324_REG_PROX_CTRL0_GAIN_1 << SX9324_REG_PROX_CTRL0_GAIN_SHIFT |
797 SX9324_REG_PROX_CTRL0_RAWFILT_1P50, "prox_ctrl0" },
798 { SX9324_REG_PROX_CTRL1,
799 SX9324_REG_PROX_CTRL0_GAIN_1 << SX9324_REG_PROX_CTRL0_GAIN_SHIFT |
800 SX9324_REG_PROX_CTRL0_RAWFILT_1P50, "prox_ctrl1" },
801 { SX9324_REG_PROX_CTRL2, SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K, "prox_ctrl2" },
802 { SX9324_REG_PROX_CTRL3, SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES |
803 SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K, "prox_ctrl3" },
804 { SX9324_REG_PROX_CTRL4, SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 |
805 SX9324_REG_PROX_CTRL4_AVGPOS_FILT_256, "prox_ctrl4" },
806 { SX9324_REG_PROX_CTRL5, 0x00, "prox_ctrl5" },
807 { SX9324_REG_PROX_CTRL6, SX9324_REG_PROX_CTRL6_PROXTHRESH_32, "prox_ctrl6" },
808 { SX9324_REG_PROX_CTRL7, SX9324_REG_PROX_CTRL6_PROXTHRESH_32, "prox_ctrl7" },
809 { SX9324_REG_ADV_CTRL0, 0x00, "adv_ctrl0" },
810 { SX9324_REG_ADV_CTRL1, 0x00, "adv_ctrl1" },
811 { SX9324_REG_ADV_CTRL2, 0x00, "adv_ctrl2" },
812 { SX9324_REG_ADV_CTRL3, 0x00, "adv_ctrl3" },
813 { SX9324_REG_ADV_CTRL4, 0x00, "adv_ctrl4" },
814 { SX9324_REG_ADV_CTRL5, SX9324_REG_ADV_CTRL5_STARTUP_SENSOR_1 |
815 SX9324_REG_ADV_CTRL5_STARTUP_METHOD_1, "adv_ctrl5" },
816 { SX9324_REG_ADV_CTRL6, 0x00, "adv_ctrl6" },
817 { SX9324_REG_ADV_CTRL7, 0x00, "adv_ctrl7" },
818 { SX9324_REG_ADV_CTRL8, 0x00, "adv_ctrl8" },
819 { SX9324_REG_ADV_CTRL9, 0x00, "adv_ctrl9" },
820 /* Body/Table threshold */
821 { SX9324_REG_ADV_CTRL10, 0x00, "adv_ctrl10" },
822 { SX9324_REG_ADV_CTRL11, 0x00, "adv_ctrl11" },
823 { SX9324_REG_ADV_CTRL12, 0x00, "adv_ctrl12" },
824 /* TODO(gwendal): SAR currenly disabled */
825 { SX9324_REG_ADV_CTRL13, 0x00, "adv_ctrl13" },
826 { SX9324_REG_ADV_CTRL14, 0x00, "adv_ctrl14" },
827 { SX9324_REG_ADV_CTRL15, 0x00, "adv_ctrl15" },
828 { SX9324_REG_ADV_CTRL16, 0x00, "adv_ctrl16" },
829 { SX9324_REG_ADV_CTRL17, 0x00, "adv_ctrl17" },
830 { SX9324_REG_ADV_CTRL18, 0x00, "adv_ctrl18" },
831 { SX9324_REG_ADV_CTRL19,
832 SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION, "adv_ctrl19" },
833 { SX9324_REG_ADV_CTRL20,
834 SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION, "adv_ctrl20" },
835};
836
837/* Activate all channels and perform an initial compensation. */
838static int sx9324_init_compensation(struct iio_dev *indio_dev)
839{
840 struct sx_common_data *data = iio_priv(indio_dev);
841 unsigned int val;
842 int ret;
843
844 /* run the compensation phase on all channels */
845 ret = regmap_set_bits(map: data->regmap, SX9324_REG_STAT2,
846 SX9324_REG_STAT2_COMPSTAT_MASK);
847 if (ret)
848 return ret;
849
850 return regmap_read_poll_timeout(data->regmap, SX9324_REG_STAT2, val,
851 !(val & SX9324_REG_STAT2_COMPSTAT_MASK),
852 20000, 2000000);
853}
854
855static u8 sx9324_parse_phase_prop(struct device *dev,
856 struct sx_common_reg_default *reg_def,
857 const char *prop)
858{
859 unsigned int pin_defs[SX9324_NUM_PINS];
860 int count, ret, pin;
861 u32 raw = 0;
862
863 count = device_property_count_u32(dev, propname: prop);
864 if (count != ARRAY_SIZE(pin_defs))
865 return reg_def->def;
866 ret = device_property_read_u32_array(dev, propname: prop, val: pin_defs,
867 ARRAY_SIZE(pin_defs));
868 if (ret)
869 return reg_def->def;
870
871 for (pin = 0; pin < SX9324_NUM_PINS; pin++)
872 raw |= (pin_defs[pin] << (2 * pin)) &
873 SX9324_REG_AFE_PH0_PIN_MASK(pin);
874
875 return raw;
876}
877
878static void sx_common_get_raw_register_config(struct device *dev,
879 struct sx_common_reg_default *reg_def)
880{
881#ifdef CONFIG_ACPI
882 struct acpi_device *adev = ACPI_COMPANION(dev);
883 u32 raw = 0, ret;
884 char prop[80];
885
886 if (!reg_def->property || !adev)
887 return;
888
889 snprintf(buf: prop, ARRAY_SIZE(prop), fmt: "%s,reg_%s", acpi_device_hid(device: adev), reg_def->property);
890 ret = device_property_read_u32(dev, propname: prop, val: &raw);
891 if (ret)
892 return;
893
894 reg_def->def = raw;
895#endif
896}
897
898static const struct sx_common_reg_default *
899sx9324_get_default_reg(struct device *dev, int idx,
900 struct sx_common_reg_default *reg_def)
901{
902 static const char * const sx9324_rints[] = { "lowest", "low", "high",
903 "highest" };
904 static const char * const sx9324_csidle[] = { "hi-z", "hi-z", "gnd",
905 "vdd" };
906 u32 start = 0, raw = 0, pos = 0;
907 const char *prop;
908 int ret;
909
910 memcpy(reg_def, &sx9324_default_regs[idx], sizeof(*reg_def));
911
912 sx_common_get_raw_register_config(dev, reg_def);
913 switch (reg_def->reg) {
914 case SX9324_REG_AFE_PH0:
915 reg_def->def = sx9324_parse_phase_prop(dev, reg_def,
916 prop: "semtech,ph0-pin");
917 break;
918 case SX9324_REG_AFE_PH1:
919 reg_def->def = sx9324_parse_phase_prop(dev, reg_def,
920 prop: "semtech,ph1-pin");
921 break;
922 case SX9324_REG_AFE_PH2:
923 reg_def->def = sx9324_parse_phase_prop(dev, reg_def,
924 prop: "semtech,ph2-pin");
925 break;
926 case SX9324_REG_AFE_PH3:
927 reg_def->def = sx9324_parse_phase_prop(dev, reg_def,
928 prop: "semtech,ph3-pin");
929 break;
930 case SX9324_REG_AFE_CTRL0:
931 ret = device_property_match_property_string(dev, propname: "semtech,cs-idle-sleep",
932 array: sx9324_csidle,
933 ARRAY_SIZE(sx9324_csidle));
934 if (ret >= 0) {
935 reg_def->def &= ~SX9324_REG_AFE_CTRL0_CSIDLE_MASK;
936 reg_def->def |= ret << SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT;
937 }
938
939 ret = device_property_match_property_string(dev, propname: "semtech,int-comp-resistor",
940 array: sx9324_rints,
941 ARRAY_SIZE(sx9324_rints));
942 if (ret >= 0) {
943 reg_def->def &= ~SX9324_REG_AFE_CTRL0_RINT_MASK;
944 reg_def->def |= ret << SX9324_REG_AFE_CTRL0_RINT_SHIFT;
945 }
946 break;
947 case SX9324_REG_AFE_CTRL4:
948 case SX9324_REG_AFE_CTRL7:
949 if (reg_def->reg == SX9324_REG_AFE_CTRL4)
950 prop = "semtech,ph01-resolution";
951 else
952 prop = "semtech,ph23-resolution";
953
954 ret = device_property_read_u32(dev, propname: prop, val: &raw);
955 if (ret)
956 break;
957
958 raw = ilog2(raw) - 3;
959
960 reg_def->def &= ~SX9324_REG_AFE_CTRL4_RESOLUTION_MASK;
961 reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL4_RESOLUTION_MASK,
962 raw);
963 break;
964 case SX9324_REG_AFE_CTRL8:
965 ret = device_property_read_u32(dev,
966 propname: "semtech,input-precharge-resistor-ohms",
967 val: &raw);
968 if (ret)
969 break;
970
971 reg_def->def &= ~SX9324_REG_AFE_CTRL8_RESFILTIN_MASK;
972 reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL8_RESFILTIN_MASK,
973 raw / 2000);
974 break;
975
976 case SX9324_REG_AFE_CTRL9:
977 ret = device_property_read_u32(dev,
978 propname: "semtech,input-analog-gain", val: &raw);
979 if (ret)
980 break;
981 /*
982 * The analog gain has the following setting:
983 * +---------+----------------+----------------+
984 * | dt(raw) | physical value | register value |
985 * +---------+----------------+----------------+
986 * | 0 | x1.247 | 6 |
987 * | 1 | x1 | 8 |
988 * | 2 | x0.768 | 11 |
989 * | 3 | x0.552 | 15 |
990 * +---------+----------------+----------------+
991 */
992 reg_def->def &= ~SX9324_REG_AFE_CTRL9_AGAIN_MASK;
993 reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL9_AGAIN_MASK,
994 6 + raw * (raw + 3) / 2);
995 break;
996
997 case SX9324_REG_ADV_CTRL5:
998 ret = device_property_read_u32(dev, propname: "semtech,startup-sensor",
999 val: &start);
1000 if (ret)
1001 break;
1002
1003 reg_def->def &= ~SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK;
1004 reg_def->def |= FIELD_PREP(SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK,
1005 start);
1006 break;
1007 case SX9324_REG_PROX_CTRL4:
1008 ret = device_property_read_u32(dev, propname: "semtech,avg-pos-strength",
1009 val: &pos);
1010 if (ret)
1011 break;
1012
1013 /* Powers of 2, except for a gap between 16 and 64 */
1014 raw = clamp(ilog2(pos), 3, 11) - (pos >= 32 ? 4 : 3);
1015
1016 reg_def->def &= ~SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK;
1017 reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK,
1018 raw);
1019 break;
1020 case SX9324_REG_PROX_CTRL0:
1021 case SX9324_REG_PROX_CTRL1:
1022 if (reg_def->reg == SX9324_REG_PROX_CTRL0)
1023 prop = "semtech,ph01-proxraw-strength";
1024 else
1025 prop = "semtech,ph23-proxraw-strength";
1026 ret = device_property_read_u32(dev, propname: prop, val: &raw);
1027 if (ret)
1028 break;
1029
1030 reg_def->def &= ~SX9324_REG_PROX_CTRL0_RAWFILT_MASK;
1031 reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL0_RAWFILT_MASK,
1032 raw);
1033 break;
1034 }
1035 return reg_def;
1036}
1037
1038static int sx9324_check_whoami(struct device *dev,
1039 struct iio_dev *indio_dev)
1040{
1041 /*
1042 * Only one sensor for this driver. Assuming the device tree
1043 * is correct, just set the sensor name.
1044 */
1045 indio_dev->name = "sx9324";
1046 return 0;
1047}
1048
1049static const struct sx_common_chip_info sx9324_chip_info = {
1050 .reg_stat = SX9324_REG_STAT0,
1051 .reg_irq_msk = SX9324_REG_IRQ_MSK,
1052 .reg_enable_chan = SX9324_REG_GNRL_CTRL1,
1053 .reg_reset = SX9324_REG_RESET,
1054
1055 .mask_enable_chan = SX9324_REG_GNRL_CTRL1_PHEN_MASK,
1056 .irq_msk_offset = 3,
1057 .num_channels = SX9324_NUM_CHANNELS,
1058 .num_default_regs = ARRAY_SIZE(sx9324_default_regs),
1059
1060 .ops = {
1061 .read_prox_data = sx9324_read_prox_data,
1062 .check_whoami = sx9324_check_whoami,
1063 .init_compensation = sx9324_init_compensation,
1064 .wait_for_sample = sx9324_wait_for_sample,
1065 .get_default_reg = sx9324_get_default_reg,
1066 },
1067
1068 .iio_channels = sx9324_channels,
1069 .num_iio_channels = ARRAY_SIZE(sx9324_channels),
1070 .iio_info = {
1071 .read_raw = sx9324_read_raw,
1072 .read_avail = sx9324_read_avail,
1073 .read_event_value = sx9324_read_event_val,
1074 .write_event_value = sx9324_write_event_val,
1075 .write_raw = sx9324_write_raw,
1076 .read_event_config = sx_common_read_event_config,
1077 .write_event_config = sx_common_write_event_config,
1078 },
1079};
1080
1081static int sx9324_probe(struct i2c_client *client)
1082{
1083 return sx_common_probe(client, chip_info: &sx9324_chip_info, regmap_config: &sx9324_regmap_config);
1084}
1085
1086static int sx9324_suspend(struct device *dev)
1087{
1088 struct sx_common_data *data = iio_priv(indio_dev: dev_get_drvdata(dev));
1089 unsigned int regval;
1090 int ret;
1091
1092 disable_irq_nosync(irq: data->client->irq);
1093
1094 guard(mutex)(T: &data->mutex);
1095 ret = regmap_read(map: data->regmap, SX9324_REG_GNRL_CTRL1, val: &regval);
1096 if (ret < 0)
1097 return ret;
1098
1099 data->suspend_ctrl =
1100 FIELD_GET(SX9324_REG_GNRL_CTRL1_PHEN_MASK, regval);
1101
1102
1103 /* Disable all phases, send the device to sleep. */
1104 return regmap_write(map: data->regmap, SX9324_REG_GNRL_CTRL1, val: 0);
1105}
1106
1107static int sx9324_resume(struct device *dev)
1108{
1109 struct sx_common_data *data = iio_priv(indio_dev: dev_get_drvdata(dev));
1110
1111 scoped_guard(mutex, &data->mutex) {
1112 int ret = regmap_write(map: data->regmap, SX9324_REG_GNRL_CTRL1,
1113 val: data->suspend_ctrl |
1114 SX9324_REG_GNRL_CTRL1_PAUSECTRL);
1115 if (ret)
1116 return ret;
1117 }
1118
1119 enable_irq(irq: data->client->irq);
1120 return 0;
1121}
1122
1123static DEFINE_SIMPLE_DEV_PM_OPS(sx9324_pm_ops, sx9324_suspend, sx9324_resume);
1124
1125static const struct acpi_device_id sx9324_acpi_match[] = {
1126 { "STH9324", SX9324_WHOAMI_VALUE },
1127 { }
1128};
1129MODULE_DEVICE_TABLE(acpi, sx9324_acpi_match);
1130
1131static const struct of_device_id sx9324_of_match[] = {
1132 { .compatible = "semtech,sx9324", (void *)SX9324_WHOAMI_VALUE },
1133 { }
1134};
1135MODULE_DEVICE_TABLE(of, sx9324_of_match);
1136
1137static const struct i2c_device_id sx9324_id[] = {
1138 { "sx9324", SX9324_WHOAMI_VALUE },
1139 { }
1140};
1141MODULE_DEVICE_TABLE(i2c, sx9324_id);
1142
1143static struct i2c_driver sx9324_driver = {
1144 .driver = {
1145 .name = "sx9324",
1146 .acpi_match_table = sx9324_acpi_match,
1147 .of_match_table = sx9324_of_match,
1148 .pm = pm_sleep_ptr(&sx9324_pm_ops),
1149
1150 /*
1151 * Lots of i2c transfers in probe + over 200 ms waiting in
1152 * sx9324_init_compensation() mean a slow probe; prefer async
1153 * so we don't delay boot if we're builtin to the kernel.
1154 */
1155 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1156 },
1157 .probe = sx9324_probe,
1158 .id_table = sx9324_id,
1159};
1160module_i2c_driver(sx9324_driver);
1161
1162MODULE_AUTHOR("Gwendal Grignou <gwendal@chromium.org>");
1163MODULE_DESCRIPTION("Driver for Semtech SX9324 proximity sensor");
1164MODULE_LICENSE("GPL v2");
1165MODULE_IMPORT_NS("SEMTECH_PROX");
1166

source code of linux/drivers/iio/proximity/sx9324.c