1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com> |
4 | * Loongson PCH MSI support |
5 | */ |
6 | |
7 | #define pr_fmt(fmt) "pch-msi: " fmt |
8 | |
9 | #include <linux/irqchip.h> |
10 | #include <linux/msi.h> |
11 | #include <linux/of.h> |
12 | #include <linux/of_address.h> |
13 | #include <linux/of_irq.h> |
14 | #include <linux/of_pci.h> |
15 | #include <linux/pci.h> |
16 | #include <linux/slab.h> |
17 | |
18 | static int nr_pics; |
19 | |
20 | struct pch_msi_data { |
21 | struct mutex msi_map_lock; |
22 | phys_addr_t doorbell; |
23 | u32 irq_first; /* The vector number that MSIs starts */ |
24 | u32 num_irqs; /* The number of vectors for MSIs */ |
25 | unsigned long *msi_map; |
26 | }; |
27 | |
28 | static struct fwnode_handle *pch_msi_handle[MAX_IO_PICS]; |
29 | |
30 | static void pch_msi_mask_msi_irq(struct irq_data *d) |
31 | { |
32 | pci_msi_mask_irq(data: d); |
33 | irq_chip_mask_parent(data: d); |
34 | } |
35 | |
36 | static void pch_msi_unmask_msi_irq(struct irq_data *d) |
37 | { |
38 | irq_chip_unmask_parent(data: d); |
39 | pci_msi_unmask_irq(data: d); |
40 | } |
41 | |
42 | static struct irq_chip pch_msi_irq_chip = { |
43 | .name = "PCH PCI MSI" , |
44 | .irq_mask = pch_msi_mask_msi_irq, |
45 | .irq_unmask = pch_msi_unmask_msi_irq, |
46 | .irq_ack = irq_chip_ack_parent, |
47 | .irq_set_affinity = irq_chip_set_affinity_parent, |
48 | }; |
49 | |
50 | static int pch_msi_allocate_hwirq(struct pch_msi_data *priv, int num_req) |
51 | { |
52 | int first; |
53 | |
54 | mutex_lock(&priv->msi_map_lock); |
55 | |
56 | first = bitmap_find_free_region(bitmap: priv->msi_map, bits: priv->num_irqs, |
57 | order: get_count_order(count: num_req)); |
58 | if (first < 0) { |
59 | mutex_unlock(lock: &priv->msi_map_lock); |
60 | return -ENOSPC; |
61 | } |
62 | |
63 | mutex_unlock(lock: &priv->msi_map_lock); |
64 | |
65 | return priv->irq_first + first; |
66 | } |
67 | |
68 | static void pch_msi_free_hwirq(struct pch_msi_data *priv, |
69 | int hwirq, int num_req) |
70 | { |
71 | int first = hwirq - priv->irq_first; |
72 | |
73 | mutex_lock(&priv->msi_map_lock); |
74 | bitmap_release_region(bitmap: priv->msi_map, pos: first, order: get_count_order(count: num_req)); |
75 | mutex_unlock(lock: &priv->msi_map_lock); |
76 | } |
77 | |
78 | static void pch_msi_compose_msi_msg(struct irq_data *data, |
79 | struct msi_msg *msg) |
80 | { |
81 | struct pch_msi_data *priv = irq_data_get_irq_chip_data(d: data); |
82 | |
83 | msg->address_hi = upper_32_bits(priv->doorbell); |
84 | msg->address_lo = lower_32_bits(priv->doorbell); |
85 | msg->data = data->hwirq; |
86 | } |
87 | |
88 | static struct msi_domain_info pch_msi_domain_info = { |
89 | .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | |
90 | MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, |
91 | .chip = &pch_msi_irq_chip, |
92 | }; |
93 | |
94 | static struct irq_chip middle_irq_chip = { |
95 | .name = "PCH MSI" , |
96 | .irq_mask = irq_chip_mask_parent, |
97 | .irq_unmask = irq_chip_unmask_parent, |
98 | .irq_ack = irq_chip_ack_parent, |
99 | .irq_set_affinity = irq_chip_set_affinity_parent, |
100 | .irq_compose_msi_msg = pch_msi_compose_msi_msg, |
101 | }; |
102 | |
103 | static int pch_msi_parent_domain_alloc(struct irq_domain *domain, |
104 | unsigned int virq, int hwirq) |
105 | { |
106 | struct irq_fwspec fwspec; |
107 | |
108 | fwspec.fwnode = domain->parent->fwnode; |
109 | fwspec.param_count = 1; |
110 | fwspec.param[0] = hwirq; |
111 | |
112 | return irq_domain_alloc_irqs_parent(domain, irq_base: virq, nr_irqs: 1, arg: &fwspec); |
113 | } |
114 | |
115 | static int pch_msi_middle_domain_alloc(struct irq_domain *domain, |
116 | unsigned int virq, |
117 | unsigned int nr_irqs, void *args) |
118 | { |
119 | struct pch_msi_data *priv = domain->host_data; |
120 | int hwirq, err, i; |
121 | |
122 | hwirq = pch_msi_allocate_hwirq(priv, num_req: nr_irqs); |
123 | if (hwirq < 0) |
124 | return hwirq; |
125 | |
126 | for (i = 0; i < nr_irqs; i++) { |
127 | err = pch_msi_parent_domain_alloc(domain, virq: virq + i, hwirq: hwirq + i); |
128 | if (err) |
129 | goto err_hwirq; |
130 | |
131 | irq_domain_set_hwirq_and_chip(domain, virq: virq + i, hwirq: hwirq + i, |
132 | chip: &middle_irq_chip, chip_data: priv); |
133 | } |
134 | |
135 | return 0; |
136 | |
137 | err_hwirq: |
138 | pch_msi_free_hwirq(priv, hwirq, num_req: nr_irqs); |
139 | irq_domain_free_irqs_parent(domain, irq_base: virq, nr_irqs: i - 1); |
140 | |
141 | return err; |
142 | } |
143 | |
144 | static void pch_msi_middle_domain_free(struct irq_domain *domain, |
145 | unsigned int virq, |
146 | unsigned int nr_irqs) |
147 | { |
148 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); |
149 | struct pch_msi_data *priv = irq_data_get_irq_chip_data(d); |
150 | |
151 | irq_domain_free_irqs_parent(domain, irq_base: virq, nr_irqs); |
152 | pch_msi_free_hwirq(priv, hwirq: d->hwirq, num_req: nr_irqs); |
153 | } |
154 | |
155 | static const struct irq_domain_ops pch_msi_middle_domain_ops = { |
156 | .alloc = pch_msi_middle_domain_alloc, |
157 | .free = pch_msi_middle_domain_free, |
158 | }; |
159 | |
160 | static int pch_msi_init_domains(struct pch_msi_data *priv, |
161 | struct irq_domain *parent, |
162 | struct fwnode_handle *domain_handle) |
163 | { |
164 | struct irq_domain *middle_domain, *msi_domain; |
165 | |
166 | middle_domain = irq_domain_create_hierarchy(parent, flags: 0, size: priv->num_irqs, |
167 | fwnode: domain_handle, |
168 | ops: &pch_msi_middle_domain_ops, |
169 | host_data: priv); |
170 | if (!middle_domain) { |
171 | pr_err("Failed to create the MSI middle domain\n" ); |
172 | return -ENOMEM; |
173 | } |
174 | |
175 | irq_domain_update_bus_token(domain: middle_domain, bus_token: DOMAIN_BUS_NEXUS); |
176 | |
177 | msi_domain = pci_msi_create_irq_domain(fwnode: domain_handle, |
178 | info: &pch_msi_domain_info, |
179 | parent: middle_domain); |
180 | if (!msi_domain) { |
181 | pr_err("Failed to create PCI MSI domain\n" ); |
182 | irq_domain_remove(host: middle_domain); |
183 | return -ENOMEM; |
184 | } |
185 | |
186 | return 0; |
187 | } |
188 | |
189 | static int pch_msi_init(phys_addr_t msg_address, int irq_base, int irq_count, |
190 | struct irq_domain *parent_domain, struct fwnode_handle *domain_handle) |
191 | { |
192 | int ret; |
193 | struct pch_msi_data *priv; |
194 | |
195 | priv = kzalloc(size: sizeof(*priv), GFP_KERNEL); |
196 | if (!priv) |
197 | return -ENOMEM; |
198 | |
199 | mutex_init(&priv->msi_map_lock); |
200 | |
201 | priv->doorbell = msg_address; |
202 | priv->irq_first = irq_base; |
203 | priv->num_irqs = irq_count; |
204 | |
205 | priv->msi_map = bitmap_zalloc(nbits: priv->num_irqs, GFP_KERNEL); |
206 | if (!priv->msi_map) |
207 | goto err_priv; |
208 | |
209 | pr_debug("Registering %d MSIs, starting at %d\n" , |
210 | priv->num_irqs, priv->irq_first); |
211 | |
212 | ret = pch_msi_init_domains(priv, parent: parent_domain, domain_handle); |
213 | if (ret) |
214 | goto err_map; |
215 | |
216 | pch_msi_handle[nr_pics++] = domain_handle; |
217 | return 0; |
218 | |
219 | err_map: |
220 | bitmap_free(bitmap: priv->msi_map); |
221 | err_priv: |
222 | kfree(objp: priv); |
223 | |
224 | return -EINVAL; |
225 | } |
226 | |
227 | #ifdef CONFIG_OF |
228 | static int pch_msi_of_init(struct device_node *node, struct device_node *parent) |
229 | { |
230 | int err; |
231 | int irq_base, irq_count; |
232 | struct resource res; |
233 | struct irq_domain *parent_domain; |
234 | |
235 | parent_domain = irq_find_host(node: parent); |
236 | if (!parent_domain) { |
237 | pr_err("Failed to find the parent domain\n" ); |
238 | return -ENXIO; |
239 | } |
240 | |
241 | if (of_address_to_resource(dev: node, index: 0, r: &res)) { |
242 | pr_err("Failed to allocate resource\n" ); |
243 | return -EINVAL; |
244 | } |
245 | |
246 | if (of_property_read_u32(np: node, propname: "loongson,msi-base-vec" , out_value: &irq_base)) { |
247 | pr_err("Unable to parse MSI vec base\n" ); |
248 | return -EINVAL; |
249 | } |
250 | |
251 | if (of_property_read_u32(np: node, propname: "loongson,msi-num-vecs" , out_value: &irq_count)) { |
252 | pr_err("Unable to parse MSI vec number\n" ); |
253 | return -EINVAL; |
254 | } |
255 | |
256 | err = pch_msi_init(msg_address: res.start, irq_base, irq_count, parent_domain, domain_handle: of_node_to_fwnode(node)); |
257 | if (err < 0) |
258 | return err; |
259 | |
260 | return 0; |
261 | } |
262 | |
263 | IRQCHIP_DECLARE(pch_msi, "loongson,pch-msi-1.0" , pch_msi_of_init); |
264 | #endif |
265 | |
266 | #ifdef CONFIG_ACPI |
267 | struct fwnode_handle *get_pch_msi_handle(int pci_segment) |
268 | { |
269 | int i; |
270 | |
271 | for (i = 0; i < MAX_IO_PICS; i++) { |
272 | if (msi_group[i].pci_segment == pci_segment) |
273 | return pch_msi_handle[i]; |
274 | } |
275 | return NULL; |
276 | } |
277 | |
278 | int __init pch_msi_acpi_init(struct irq_domain *parent, |
279 | struct acpi_madt_msi_pic *acpi_pchmsi) |
280 | { |
281 | int ret; |
282 | struct fwnode_handle *domain_handle; |
283 | |
284 | domain_handle = irq_domain_alloc_fwnode(pa: &acpi_pchmsi->msg_address); |
285 | ret = pch_msi_init(msg_address: acpi_pchmsi->msg_address, irq_base: acpi_pchmsi->start, |
286 | irq_count: acpi_pchmsi->count, parent_domain: parent, domain_handle); |
287 | if (ret < 0) |
288 | irq_domain_free_fwnode(fwnode: domain_handle); |
289 | |
290 | return ret; |
291 | } |
292 | #endif |
293 | |