1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 Conexant cx24120/cx24118 - DVBS/S2 Satellite demod/tuner driver
4
5 Copyright (C) 2008 Patrick Boettcher <pb@linuxtv.org>
6 Copyright (C) 2009 Sergey Tyurin <forum.free-x.de>
7 Updated 2012 by Jannis Achstetter <jannis_achstetter@web.de>
8 Copyright (C) 2015 Jemma Denson <jdenson@gmail.com>
9 April 2015
10 Refactored & simplified driver
11 Updated to work with delivery system supplied by DVBv5
12 Add frequency, fec & pilot to get_frontend
13
14 Cards supported: Technisat Skystar S2
15
16*/
17
18#include <linux/slab.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/init.h>
23#include <linux/firmware.h>
24#include <media/dvb_frontend.h>
25#include "cx24120.h"
26
27#define CX24120_SEARCH_RANGE_KHZ 5000
28#define CX24120_FIRMWARE "dvb-fe-cx24120-1.20.58.2.fw"
29
30/* cx24120 i2c registers */
31#define CX24120_REG_CMD_START 0x00 /* write cmd_id */
32#define CX24120_REG_CMD_ARGS 0x01 /* write command arguments */
33#define CX24120_REG_CMD_END 0x1f /* write 0x01 for end */
34
35#define CX24120_REG_MAILBOX 0x33
36#define CX24120_REG_FREQ3 0x34 /* frequency */
37#define CX24120_REG_FREQ2 0x35
38#define CX24120_REG_FREQ1 0x36
39
40#define CX24120_REG_FECMODE 0x39 /* FEC status */
41#define CX24120_REG_STATUS 0x3a /* Tuner status */
42#define CX24120_REG_SIGSTR_H 0x3a /* Signal strength high */
43#define CX24120_REG_SIGSTR_L 0x3b /* Signal strength low byte */
44#define CX24120_REG_QUALITY_H 0x40 /* SNR high byte */
45#define CX24120_REG_QUALITY_L 0x41 /* SNR low byte */
46
47#define CX24120_REG_BER_HH 0x47 /* BER high byte of high word */
48#define CX24120_REG_BER_HL 0x48 /* BER low byte of high word */
49#define CX24120_REG_BER_LH 0x49 /* BER high byte of low word */
50#define CX24120_REG_BER_LL 0x4a /* BER low byte of low word */
51
52#define CX24120_REG_UCB_H 0x50 /* UCB high byte */
53#define CX24120_REG_UCB_L 0x51 /* UCB low byte */
54
55#define CX24120_REG_CLKDIV 0xe6
56#define CX24120_REG_RATEDIV 0xf0
57
58#define CX24120_REG_REVISION 0xff /* Chip revision (ro) */
59
60/* Command messages */
61enum command_message_id {
62 CMD_VCO_SET = 0x10, /* cmd.len = 12; */
63 CMD_TUNEREQUEST = 0x11, /* cmd.len = 15; */
64
65 CMD_MPEG_ONOFF = 0x13, /* cmd.len = 4; */
66 CMD_MPEG_INIT = 0x14, /* cmd.len = 7; */
67 CMD_BANDWIDTH = 0x15, /* cmd.len = 12; */
68 CMD_CLOCK_READ = 0x16, /* read clock */
69 CMD_CLOCK_SET = 0x17, /* cmd.len = 10; */
70
71 CMD_DISEQC_MSG1 = 0x20, /* cmd.len = 11; */
72 CMD_DISEQC_MSG2 = 0x21, /* cmd.len = d->msg_len + 6; */
73 CMD_SETVOLTAGE = 0x22, /* cmd.len = 2; */
74 CMD_SETTONE = 0x23, /* cmd.len = 4; */
75 CMD_DISEQC_BURST = 0x24, /* cmd.len not used !!! */
76
77 CMD_READ_SNR = 0x1a, /* Read signal strength */
78 CMD_START_TUNER = 0x1b, /* ??? */
79
80 CMD_FWVERSION = 0x35,
81
82 CMD_BER_CTRL = 0x3c, /* cmd.len = 0x03; */
83};
84
85#define CX24120_MAX_CMD_LEN 30
86
87/* pilot mask */
88#define CX24120_PILOT_OFF 0x00
89#define CX24120_PILOT_ON 0x40
90#define CX24120_PILOT_AUTO 0x80
91
92/* signal status */
93#define CX24120_HAS_SIGNAL 0x01
94#define CX24120_HAS_CARRIER 0x02
95#define CX24120_HAS_VITERBI 0x04
96#define CX24120_HAS_LOCK 0x08
97#define CX24120_HAS_UNK1 0x10
98#define CX24120_HAS_UNK2 0x20
99#define CX24120_STATUS_MASK 0x0f
100#define CX24120_SIGNAL_MASK 0xc0
101
102/* ber window */
103#define CX24120_BER_WINDOW 16
104#define CX24120_BER_WSIZE ((1 << CX24120_BER_WINDOW) * 208 * 8)
105
106#define info(args...) pr_info("cx24120: " args)
107#define err(args...) pr_err("cx24120: ### ERROR: " args)
108
109/* The Demod/Tuner can't easily provide these, we cache them */
110struct cx24120_tuning {
111 u32 frequency;
112 u32 symbol_rate;
113 enum fe_spectral_inversion inversion;
114 enum fe_code_rate fec;
115
116 enum fe_delivery_system delsys;
117 enum fe_modulation modulation;
118 enum fe_pilot pilot;
119
120 /* Demod values */
121 u8 fec_val;
122 u8 fec_mask;
123 u8 clkdiv;
124 u8 ratediv;
125 u8 inversion_val;
126 u8 pilot_val;
127};
128
129/* Private state */
130struct cx24120_state {
131 struct i2c_adapter *i2c;
132 const struct cx24120_config *config;
133 struct dvb_frontend frontend;
134
135 u8 cold_init;
136 u8 mpeg_enabled;
137 u8 need_clock_set;
138
139 /* current and next tuning parameters */
140 struct cx24120_tuning dcur;
141 struct cx24120_tuning dnxt;
142
143 enum fe_status fe_status;
144
145 /* dvbv5 stats calculations */
146 u32 bitrate;
147 u32 berw_usecs;
148 u32 ber_prev;
149 u32 ucb_offset;
150 unsigned long ber_jiffies_stats;
151 unsigned long per_jiffies_stats;
152};
153
154/* Command message to firmware */
155struct cx24120_cmd {
156 u8 id;
157 u8 len;
158 u8 arg[CX24120_MAX_CMD_LEN];
159};
160
161/* Read single register */
162static int cx24120_readreg(struct cx24120_state *state, u8 reg)
163{
164 int ret;
165 u8 buf = 0;
166 struct i2c_msg msg[] = {
167 {
168 .addr = state->config->i2c_addr,
169 .flags = 0,
170 .len = 1,
171 .buf = &reg
172 }, {
173 .addr = state->config->i2c_addr,
174 .flags = I2C_M_RD,
175 .len = 1,
176 .buf = &buf
177 }
178 };
179
180 ret = i2c_transfer(adap: state->i2c, msgs: msg, num: 2);
181 if (ret != 2) {
182 err("Read error: reg=0x%02x, ret=%i)\n", reg, ret);
183 return ret;
184 }
185
186 dev_dbg(&state->i2c->dev, "reg=0x%02x; data=0x%02x\n", reg, buf);
187
188 return buf;
189}
190
191/* Write single register */
192static int cx24120_writereg(struct cx24120_state *state, u8 reg, u8 data)
193{
194 u8 buf[] = { reg, data };
195 struct i2c_msg msg = {
196 .addr = state->config->i2c_addr,
197 .flags = 0,
198 .buf = buf,
199 .len = 2
200 };
201 int ret;
202
203 ret = i2c_transfer(adap: state->i2c, msgs: &msg, num: 1);
204 if (ret != 1) {
205 err("Write error: i2c_write error(err == %i, 0x%02x: 0x%02x)\n",
206 ret, reg, data);
207 return ret;
208 }
209
210 dev_dbg(&state->i2c->dev, "reg=0x%02x; data=0x%02x\n", reg, data);
211
212 return 0;
213}
214
215/* Write multiple registers in chunks of i2c_wr_max-sized buffers */
216static int cx24120_writeregs(struct cx24120_state *state,
217 u8 reg, const u8 *values, u16 len, u8 incr)
218{
219 int ret;
220 u16 max = state->config->i2c_wr_max > 0 ?
221 state->config->i2c_wr_max :
222 len;
223
224 struct i2c_msg msg = {
225 .addr = state->config->i2c_addr,
226 .flags = 0,
227 };
228
229 msg.buf = kmalloc(size: max + 1, GFP_KERNEL);
230 if (!msg.buf)
231 return -ENOMEM;
232
233 while (len) {
234 msg.buf[0] = reg;
235 msg.len = len > max ? max : len;
236 memcpy(&msg.buf[1], values, msg.len);
237
238 len -= msg.len; /* data length revers counter */
239 values += msg.len; /* incr data pointer */
240
241 if (incr)
242 reg += msg.len;
243 msg.len++; /* don't forget the addr byte */
244
245 ret = i2c_transfer(adap: state->i2c, msgs: &msg, num: 1);
246 if (ret != 1) {
247 err("i2c_write error(err == %i, 0x%02x)\n", ret, reg);
248 goto out;
249 }
250
251 dev_dbg(&state->i2c->dev, "reg=0x%02x; data=%*ph\n",
252 reg, msg.len - 1, msg.buf + 1);
253 }
254
255 ret = 0;
256
257out:
258 kfree(objp: msg.buf);
259 return ret;
260}
261
262static const struct dvb_frontend_ops cx24120_ops;
263
264struct dvb_frontend *cx24120_attach(const struct cx24120_config *config,
265 struct i2c_adapter *i2c)
266{
267 struct cx24120_state *state;
268 int demod_rev;
269
270 info("Conexant cx24120/cx24118 - DVBS/S2 Satellite demod/tuner\n");
271 state = kzalloc(size: sizeof(*state), GFP_KERNEL);
272 if (!state) {
273 err("Unable to allocate memory for cx24120_state\n");
274 goto error;
275 }
276
277 /* setup the state */
278 state->config = config;
279 state->i2c = i2c;
280
281 /* check if the demod is present and has proper type */
282 demod_rev = cx24120_readreg(state, CX24120_REG_REVISION);
283 switch (demod_rev) {
284 case 0x07:
285 info("Demod cx24120 rev. 0x07 detected.\n");
286 break;
287 case 0x05:
288 info("Demod cx24120 rev. 0x05 detected.\n");
289 break;
290 default:
291 err("Unsupported demod revision: 0x%x detected.\n", demod_rev);
292 goto error;
293 }
294
295 /* create dvb_frontend */
296 state->cold_init = 0;
297 memcpy(&state->frontend.ops, &cx24120_ops,
298 sizeof(struct dvb_frontend_ops));
299 state->frontend.demodulator_priv = state;
300
301 info("Conexant cx24120/cx24118 attached.\n");
302 return &state->frontend;
303
304error:
305 kfree(objp: state);
306 return NULL;
307}
308EXPORT_SYMBOL_GPL(cx24120_attach);
309
310static int cx24120_test_rom(struct cx24120_state *state)
311{
312 int err, ret;
313
314 err = cx24120_readreg(state, reg: 0xfd);
315 if (err & 4) {
316 ret = cx24120_readreg(state, reg: 0xdf) & 0xfe;
317 err = cx24120_writereg(state, reg: 0xdf, data: ret);
318 }
319 return err;
320}
321
322static int cx24120_read_snr(struct dvb_frontend *fe, u16 *snr)
323{
324 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
325
326 if (c->cnr.stat[0].scale != FE_SCALE_DECIBEL)
327 *snr = 0;
328 else
329 *snr = div_s64(dividend: c->cnr.stat[0].svalue, divisor: 100);
330
331 return 0;
332}
333
334static int cx24120_read_ber(struct dvb_frontend *fe, u32 *ber)
335{
336 struct cx24120_state *state = fe->demodulator_priv;
337 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
338
339 if (c->post_bit_error.stat[0].scale != FE_SCALE_COUNTER) {
340 *ber = 0;
341 return 0;
342 }
343
344 *ber = c->post_bit_error.stat[0].uvalue - state->ber_prev;
345 state->ber_prev = c->post_bit_error.stat[0].uvalue;
346
347 return 0;
348}
349
350static int cx24120_msg_mpeg_output_global_config(struct cx24120_state *state,
351 u8 flag);
352
353/* Check if we're running a command that needs to disable mpeg out */
354static void cx24120_check_cmd(struct cx24120_state *state, u8 id)
355{
356 switch (id) {
357 case CMD_TUNEREQUEST:
358 case CMD_CLOCK_READ:
359 case CMD_DISEQC_MSG1:
360 case CMD_DISEQC_MSG2:
361 case CMD_SETVOLTAGE:
362 case CMD_SETTONE:
363 case CMD_DISEQC_BURST:
364 cx24120_msg_mpeg_output_global_config(state, flag: 0);
365 /* Old driver would do a msleep(100) here */
366 return;
367 default:
368 return;
369 }
370}
371
372/* Send a message to the firmware */
373static int cx24120_message_send(struct cx24120_state *state,
374 struct cx24120_cmd *cmd)
375{
376 int ficus;
377
378 if (state->mpeg_enabled) {
379 /* Disable mpeg out on certain commands */
380 cx24120_check_cmd(state, id: cmd->id);
381 }
382
383 cx24120_writereg(state, CX24120_REG_CMD_START, data: cmd->id);
384 cx24120_writeregs(state, CX24120_REG_CMD_ARGS, values: &cmd->arg[0],
385 len: cmd->len, incr: 1);
386 cx24120_writereg(state, CX24120_REG_CMD_END, data: 0x01);
387
388 ficus = 1000;
389 while (cx24120_readreg(state, CX24120_REG_CMD_END)) {
390 msleep(msecs: 20);
391 ficus -= 20;
392 if (ficus == 0) {
393 err("Error sending message to firmware\n");
394 return -EREMOTEIO;
395 }
396 }
397 dev_dbg(&state->i2c->dev, "sent message 0x%02x\n", cmd->id);
398
399 return 0;
400}
401
402/* Send a message and fill arg[] with the results */
403static int cx24120_message_sendrcv(struct cx24120_state *state,
404 struct cx24120_cmd *cmd, u8 numreg)
405{
406 int ret, i;
407
408 if (numreg > CX24120_MAX_CMD_LEN) {
409 err("Too many registers to read. cmd->reg = %d", numreg);
410 return -EREMOTEIO;
411 }
412
413 ret = cx24120_message_send(state, cmd);
414 if (ret != 0)
415 return ret;
416
417 if (!numreg)
418 return 0;
419
420 /* Read numreg registers starting from register cmd->len */
421 for (i = 0; i < numreg; i++)
422 cmd->arg[i] = cx24120_readreg(state, reg: (cmd->len + i + 1));
423
424 return 0;
425}
426
427static int cx24120_read_signal_strength(struct dvb_frontend *fe,
428 u16 *signal_strength)
429{
430 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
431
432 if (c->strength.stat[0].scale != FE_SCALE_RELATIVE)
433 *signal_strength = 0;
434 else
435 *signal_strength = c->strength.stat[0].uvalue;
436
437 return 0;
438}
439
440static int cx24120_msg_mpeg_output_global_config(struct cx24120_state *state,
441 u8 enable)
442{
443 struct cx24120_cmd cmd;
444 int ret;
445
446 cmd.id = CMD_MPEG_ONOFF;
447 cmd.len = 4;
448 cmd.arg[0] = 0x01;
449 cmd.arg[1] = 0x00;
450 cmd.arg[2] = enable ? 0 : (u8)(-1);
451 cmd.arg[3] = 0x01;
452
453 ret = cx24120_message_send(state, cmd: &cmd);
454 if (ret != 0) {
455 dev_dbg(&state->i2c->dev, "failed to %s MPEG output\n",
456 enable ? "enable" : "disable");
457 return ret;
458 }
459
460 state->mpeg_enabled = enable;
461 dev_dbg(&state->i2c->dev, "MPEG output %s\n",
462 enable ? "enabled" : "disabled");
463
464 return 0;
465}
466
467static int cx24120_msg_mpeg_output_config(struct cx24120_state *state, u8 seq)
468{
469 struct cx24120_cmd cmd;
470 struct cx24120_initial_mpeg_config i =
471 state->config->initial_mpeg_config;
472
473 cmd.id = CMD_MPEG_INIT;
474 cmd.len = 7;
475 cmd.arg[0] = seq; /* sequental number - can be 0,1,2 */
476 cmd.arg[1] = ((i.x1 & 0x01) << 1) | ((i.x1 >> 1) & 0x01);
477 cmd.arg[2] = 0x05;
478 cmd.arg[3] = 0x02;
479 cmd.arg[4] = ((i.x2 >> 1) & 0x01);
480 cmd.arg[5] = (i.x2 & 0xf0) | (i.x3 & 0x0f);
481 cmd.arg[6] = 0x10;
482
483 return cx24120_message_send(state, cmd: &cmd);
484}
485
486static int cx24120_diseqc_send_burst(struct dvb_frontend *fe,
487 enum fe_sec_mini_cmd burst)
488{
489 struct cx24120_state *state = fe->demodulator_priv;
490 struct cx24120_cmd cmd;
491
492 dev_dbg(&state->i2c->dev, "\n");
493
494 /*
495 * Yes, cmd.len is set to zero. The old driver
496 * didn't specify any len, but also had a
497 * memset 0 before every use of the cmd struct
498 * which would have set it to zero.
499 * This quite probably needs looking into.
500 */
501 cmd.id = CMD_DISEQC_BURST;
502 cmd.len = 0;
503 cmd.arg[0] = 0x00;
504 cmd.arg[1] = (burst == SEC_MINI_B) ? 0x01 : 0x00;
505
506 return cx24120_message_send(state, cmd: &cmd);
507}
508
509static int cx24120_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
510{
511 struct cx24120_state *state = fe->demodulator_priv;
512 struct cx24120_cmd cmd;
513
514 dev_dbg(&state->i2c->dev, "(%d)\n", tone);
515
516 if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
517 err("Invalid tone=%d\n", tone);
518 return -EINVAL;
519 }
520
521 cmd.id = CMD_SETTONE;
522 cmd.len = 4;
523 cmd.arg[0] = 0x00;
524 cmd.arg[1] = 0x00;
525 cmd.arg[2] = 0x00;
526 cmd.arg[3] = (tone == SEC_TONE_ON) ? 0x01 : 0x00;
527
528 return cx24120_message_send(state, cmd: &cmd);
529}
530
531static int cx24120_set_voltage(struct dvb_frontend *fe,
532 enum fe_sec_voltage voltage)
533{
534 struct cx24120_state *state = fe->demodulator_priv;
535 struct cx24120_cmd cmd;
536
537 dev_dbg(&state->i2c->dev, "(%d)\n", voltage);
538
539 cmd.id = CMD_SETVOLTAGE;
540 cmd.len = 2;
541 cmd.arg[0] = 0x00;
542 cmd.arg[1] = (voltage == SEC_VOLTAGE_18) ? 0x01 : 0x00;
543
544 return cx24120_message_send(state, cmd: &cmd);
545}
546
547static int cx24120_send_diseqc_msg(struct dvb_frontend *fe,
548 struct dvb_diseqc_master_cmd *d)
549{
550 struct cx24120_state *state = fe->demodulator_priv;
551 struct cx24120_cmd cmd;
552 int back_count;
553
554 dev_dbg(&state->i2c->dev, "\n");
555
556 cmd.id = CMD_DISEQC_MSG1;
557 cmd.len = 11;
558 cmd.arg[0] = 0x00;
559 cmd.arg[1] = 0x00;
560 cmd.arg[2] = 0x03;
561 cmd.arg[3] = 0x16;
562 cmd.arg[4] = 0x28;
563 cmd.arg[5] = 0x01;
564 cmd.arg[6] = 0x01;
565 cmd.arg[7] = 0x14;
566 cmd.arg[8] = 0x19;
567 cmd.arg[9] = 0x14;
568 cmd.arg[10] = 0x1e;
569
570 if (cx24120_message_send(state, cmd: &cmd)) {
571 err("send 1st message(0x%x) failed\n", cmd.id);
572 return -EREMOTEIO;
573 }
574
575 cmd.id = CMD_DISEQC_MSG2;
576 cmd.len = d->msg_len + 6;
577 cmd.arg[0] = 0x00;
578 cmd.arg[1] = 0x01;
579 cmd.arg[2] = 0x02;
580 cmd.arg[3] = 0x00;
581 cmd.arg[4] = 0x00;
582 cmd.arg[5] = d->msg_len;
583
584 memcpy(&cmd.arg[6], &d->msg, d->msg_len);
585
586 if (cx24120_message_send(state, cmd: &cmd)) {
587 err("send 2nd message(0x%x) failed\n", cmd.id);
588 return -EREMOTEIO;
589 }
590
591 back_count = 500;
592 do {
593 if (!(cx24120_readreg(state, reg: 0x93) & 0x01)) {
594 dev_dbg(&state->i2c->dev, "diseqc sequence sent\n");
595 return 0;
596 }
597 msleep(msecs: 20);
598 back_count -= 20;
599 } while (back_count);
600
601 err("Too long waiting for diseqc.\n");
602 return -ETIMEDOUT;
603}
604
605static void cx24120_get_stats(struct cx24120_state *state)
606{
607 struct dvb_frontend *fe = &state->frontend;
608 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
609 struct cx24120_cmd cmd;
610 int ret, cnr, msecs;
611 u16 sig, ucb;
612 u32 ber;
613
614 dev_dbg(&state->i2c->dev, "\n");
615
616 /* signal strength */
617 if (state->fe_status & FE_HAS_SIGNAL) {
618 cmd.id = CMD_READ_SNR;
619 cmd.len = 1;
620 cmd.arg[0] = 0x00;
621
622 ret = cx24120_message_send(state, cmd: &cmd);
623 if (ret != 0) {
624 err("error reading signal strength\n");
625 return;
626 }
627
628 /* raw */
629 sig = cx24120_readreg(state, CX24120_REG_SIGSTR_H) >> 6;
630 sig = sig << 8;
631 sig |= cx24120_readreg(state, CX24120_REG_SIGSTR_L);
632 dev_dbg(&state->i2c->dev,
633 "signal strength from firmware = 0x%x\n", sig);
634
635 /* cooked */
636 sig = -100 * sig + 94324;
637
638 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
639 c->strength.stat[0].uvalue = sig;
640 } else {
641 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
642 }
643
644 /* CNR */
645 if (state->fe_status & FE_HAS_VITERBI) {
646 cnr = cx24120_readreg(state, CX24120_REG_QUALITY_H) << 8;
647 cnr |= cx24120_readreg(state, CX24120_REG_QUALITY_L);
648 dev_dbg(&state->i2c->dev, "read SNR index = %d\n", cnr);
649
650 /* guessed - seems about right */
651 cnr = cnr * 100;
652
653 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
654 c->cnr.stat[0].svalue = cnr;
655 } else {
656 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
657 }
658
659 /* BER & UCB require lock */
660 if (!(state->fe_status & FE_HAS_LOCK)) {
661 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
662 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
663 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
664 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
665 return;
666 }
667
668 /* BER */
669 if (time_after(jiffies, state->ber_jiffies_stats)) {
670 msecs = (state->berw_usecs + 500) / 1000;
671 state->ber_jiffies_stats = jiffies + msecs_to_jiffies(m: msecs);
672
673 ber = cx24120_readreg(state, CX24120_REG_BER_HH) << 24;
674 ber |= cx24120_readreg(state, CX24120_REG_BER_HL) << 16;
675 ber |= cx24120_readreg(state, CX24120_REG_BER_LH) << 8;
676 ber |= cx24120_readreg(state, CX24120_REG_BER_LL);
677 dev_dbg(&state->i2c->dev, "read BER index = %d\n", ber);
678
679 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
680 c->post_bit_error.stat[0].uvalue += ber;
681
682 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
683 c->post_bit_count.stat[0].uvalue += CX24120_BER_WSIZE;
684 }
685
686 /* UCB */
687 if (time_after(jiffies, state->per_jiffies_stats)) {
688 state->per_jiffies_stats = jiffies + msecs_to_jiffies(m: 1000);
689
690 ucb = cx24120_readreg(state, CX24120_REG_UCB_H) << 8;
691 ucb |= cx24120_readreg(state, CX24120_REG_UCB_L);
692 dev_dbg(&state->i2c->dev, "ucblocks = %d\n", ucb);
693
694 /* handle reset */
695 if (ucb < state->ucb_offset)
696 state->ucb_offset = c->block_error.stat[0].uvalue;
697
698 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
699 c->block_error.stat[0].uvalue = ucb + state->ucb_offset;
700
701 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
702 c->block_count.stat[0].uvalue += state->bitrate / 8 / 208;
703 }
704}
705
706static void cx24120_set_clock_ratios(struct dvb_frontend *fe);
707
708/* Read current tuning status */
709static int cx24120_read_status(struct dvb_frontend *fe, enum fe_status *status)
710{
711 struct cx24120_state *state = fe->demodulator_priv;
712 int lock;
713
714 lock = cx24120_readreg(state, CX24120_REG_STATUS);
715
716 dev_dbg(&state->i2c->dev, "status = 0x%02x\n", lock);
717
718 *status = 0;
719
720 if (lock & CX24120_HAS_SIGNAL)
721 *status = FE_HAS_SIGNAL;
722 if (lock & CX24120_HAS_CARRIER)
723 *status |= FE_HAS_CARRIER;
724 if (lock & CX24120_HAS_VITERBI)
725 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
726 if (lock & CX24120_HAS_LOCK)
727 *status |= FE_HAS_LOCK;
728
729 /*
730 * TODO: is FE_HAS_SYNC in the right place?
731 * Other cx241xx drivers have this slightly
732 * different
733 */
734
735 state->fe_status = *status;
736 cx24120_get_stats(state);
737
738 /* Set the clock once tuned in */
739 if (state->need_clock_set && *status & FE_HAS_LOCK) {
740 /* Set clock ratios */
741 cx24120_set_clock_ratios(fe);
742
743 /* Old driver would do a msleep(200) here */
744
745 /* Renable mpeg output */
746 if (!state->mpeg_enabled)
747 cx24120_msg_mpeg_output_global_config(state, enable: 1);
748
749 state->need_clock_set = 0;
750 }
751
752 return 0;
753}
754
755/*
756 * FEC & modulation lookup table
757 * Used for decoding the REG_FECMODE register
758 * once tuned in.
759 */
760struct cx24120_modfec {
761 enum fe_delivery_system delsys;
762 enum fe_modulation mod;
763 enum fe_code_rate fec;
764 u8 val;
765};
766
767static const struct cx24120_modfec modfec_lookup_table[] = {
768 /*delsys mod fec val */
769 { SYS_DVBS, QPSK, FEC_1_2, 0x01 },
770 { SYS_DVBS, QPSK, FEC_2_3, 0x02 },
771 { SYS_DVBS, QPSK, FEC_3_4, 0x03 },
772 { SYS_DVBS, QPSK, FEC_4_5, 0x04 },
773 { SYS_DVBS, QPSK, FEC_5_6, 0x05 },
774 { SYS_DVBS, QPSK, FEC_6_7, 0x06 },
775 { SYS_DVBS, QPSK, FEC_7_8, 0x07 },
776
777 { SYS_DVBS2, QPSK, FEC_1_2, 0x04 },
778 { SYS_DVBS2, QPSK, FEC_3_5, 0x05 },
779 { SYS_DVBS2, QPSK, FEC_2_3, 0x06 },
780 { SYS_DVBS2, QPSK, FEC_3_4, 0x07 },
781 { SYS_DVBS2, QPSK, FEC_4_5, 0x08 },
782 { SYS_DVBS2, QPSK, FEC_5_6, 0x09 },
783 { SYS_DVBS2, QPSK, FEC_8_9, 0x0a },
784 { SYS_DVBS2, QPSK, FEC_9_10, 0x0b },
785
786 { SYS_DVBS2, PSK_8, FEC_3_5, 0x0c },
787 { SYS_DVBS2, PSK_8, FEC_2_3, 0x0d },
788 { SYS_DVBS2, PSK_8, FEC_3_4, 0x0e },
789 { SYS_DVBS2, PSK_8, FEC_5_6, 0x0f },
790 { SYS_DVBS2, PSK_8, FEC_8_9, 0x10 },
791 { SYS_DVBS2, PSK_8, FEC_9_10, 0x11 },
792};
793
794/* Retrieve current fec, modulation & pilot values */
795static int cx24120_get_fec(struct dvb_frontend *fe)
796{
797 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
798 struct cx24120_state *state = fe->demodulator_priv;
799 int idx;
800 int ret;
801 int fec;
802
803 ret = cx24120_readreg(state, CX24120_REG_FECMODE);
804 fec = ret & 0x3f; /* Lower 6 bits */
805
806 dev_dbg(&state->i2c->dev, "raw fec = %d\n", fec);
807
808 for (idx = 0; idx < ARRAY_SIZE(modfec_lookup_table); idx++) {
809 if (modfec_lookup_table[idx].delsys != state->dcur.delsys)
810 continue;
811 if (modfec_lookup_table[idx].val != fec)
812 continue;
813
814 break; /* found */
815 }
816
817 if (idx >= ARRAY_SIZE(modfec_lookup_table)) {
818 dev_dbg(&state->i2c->dev, "couldn't find fec!\n");
819 return -EINVAL;
820 }
821
822 /* save values back to cache */
823 c->modulation = modfec_lookup_table[idx].mod;
824 c->fec_inner = modfec_lookup_table[idx].fec;
825 c->pilot = (ret & 0x80) ? PILOT_ON : PILOT_OFF;
826
827 dev_dbg(&state->i2c->dev, "mod(%d), fec(%d), pilot(%d)\n",
828 c->modulation, c->fec_inner, c->pilot);
829
830 return 0;
831}
832
833/* Calculate ber window time */
834static void cx24120_calculate_ber_window(struct cx24120_state *state, u32 rate)
835{
836 struct dvb_frontend *fe = &state->frontend;
837 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
838 u64 tmp;
839
840 /*
841 * Calculate bitrate from rate in the clock ratios table.
842 * This isn't *exactly* right but close enough.
843 */
844 tmp = (u64)c->symbol_rate * rate;
845 do_div(tmp, 256);
846 state->bitrate = tmp;
847
848 /* usecs per ber window */
849 tmp = 1000000ULL * CX24120_BER_WSIZE;
850 do_div(tmp, state->bitrate);
851 state->berw_usecs = tmp;
852
853 dev_dbg(&state->i2c->dev, "bitrate: %u, berw_usecs: %u\n",
854 state->bitrate, state->berw_usecs);
855}
856
857/*
858 * Clock ratios lookup table
859 *
860 * Values obtained from much larger table in old driver
861 * which had numerous entries which would never match.
862 *
863 * There's probably some way of calculating these but I
864 * can't determine the pattern
865 */
866struct cx24120_clock_ratios_table {
867 enum fe_delivery_system delsys;
868 enum fe_pilot pilot;
869 enum fe_modulation mod;
870 enum fe_code_rate fec;
871 u32 m_rat;
872 u32 n_rat;
873 u32 rate;
874};
875
876static const struct cx24120_clock_ratios_table clock_ratios_table[] = {
877 /*delsys pilot mod fec m_rat n_rat rate */
878 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_1_2, 273088, 254505, 274 },
879 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_3_5, 17272, 13395, 330 },
880 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_2_3, 24344, 16967, 367 },
881 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_3_4, 410788, 254505, 413 },
882 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_4_5, 438328, 254505, 440 },
883 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_5_6, 30464, 16967, 459 },
884 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_8_9, 487832, 254505, 490 },
885 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_9_10, 493952, 254505, 496 },
886 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_3_5, 328168, 169905, 494 },
887 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_2_3, 24344, 11327, 550 },
888 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_3_4, 410788, 169905, 618 },
889 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_5_6, 30464, 11327, 688 },
890 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_8_9, 487832, 169905, 735 },
891 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_9_10, 493952, 169905, 744 },
892 { SYS_DVBS2, PILOT_ON, QPSK, FEC_1_2, 273088, 260709, 268 },
893 { SYS_DVBS2, PILOT_ON, QPSK, FEC_3_5, 328168, 260709, 322 },
894 { SYS_DVBS2, PILOT_ON, QPSK, FEC_2_3, 121720, 86903, 358 },
895 { SYS_DVBS2, PILOT_ON, QPSK, FEC_3_4, 410788, 260709, 403 },
896 { SYS_DVBS2, PILOT_ON, QPSK, FEC_4_5, 438328, 260709, 430 },
897 { SYS_DVBS2, PILOT_ON, QPSK, FEC_5_6, 152320, 86903, 448 },
898 { SYS_DVBS2, PILOT_ON, QPSK, FEC_8_9, 487832, 260709, 479 },
899 { SYS_DVBS2, PILOT_ON, QPSK, FEC_9_10, 493952, 260709, 485 },
900 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_3_5, 328168, 173853, 483 },
901 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_2_3, 121720, 57951, 537 },
902 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_3_4, 410788, 173853, 604 },
903 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_5_6, 152320, 57951, 672 },
904 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_8_9, 487832, 173853, 718 },
905 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_9_10, 493952, 173853, 727 },
906 { SYS_DVBS, PILOT_OFF, QPSK, FEC_1_2, 152592, 152592, 256 },
907 { SYS_DVBS, PILOT_OFF, QPSK, FEC_2_3, 305184, 228888, 341 },
908 { SYS_DVBS, PILOT_OFF, QPSK, FEC_3_4, 457776, 305184, 384 },
909 { SYS_DVBS, PILOT_OFF, QPSK, FEC_5_6, 762960, 457776, 427 },
910 { SYS_DVBS, PILOT_OFF, QPSK, FEC_7_8, 1068144, 610368, 448 },
911};
912
913/* Set clock ratio from lookup table */
914static void cx24120_set_clock_ratios(struct dvb_frontend *fe)
915{
916 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
917 struct cx24120_state *state = fe->demodulator_priv;
918 struct cx24120_cmd cmd;
919 int ret, idx;
920
921 /* Find fec, modulation, pilot */
922 ret = cx24120_get_fec(fe);
923 if (ret != 0)
924 return;
925
926 /* Find the clock ratios in the lookup table */
927 for (idx = 0; idx < ARRAY_SIZE(clock_ratios_table); idx++) {
928 if (clock_ratios_table[idx].delsys != state->dcur.delsys)
929 continue;
930 if (clock_ratios_table[idx].mod != c->modulation)
931 continue;
932 if (clock_ratios_table[idx].fec != c->fec_inner)
933 continue;
934 if (clock_ratios_table[idx].pilot != c->pilot)
935 continue;
936
937 break; /* found */
938 }
939
940 if (idx >= ARRAY_SIZE(clock_ratios_table)) {
941 info("Clock ratio not found - data reception in danger\n");
942 return;
943 }
944
945 /* Read current values? */
946 cmd.id = CMD_CLOCK_READ;
947 cmd.len = 1;
948 cmd.arg[0] = 0x00;
949 ret = cx24120_message_sendrcv(state, cmd: &cmd, numreg: 6);
950 if (ret != 0)
951 return;
952 /* in cmd[0]-[5] - result */
953
954 dev_dbg(&state->i2c->dev, "m=%d, n=%d; idx: %d m=%d, n=%d, rate=%d\n",
955 cmd.arg[2] | (cmd.arg[1] << 8) | (cmd.arg[0] << 16),
956 cmd.arg[5] | (cmd.arg[4] << 8) | (cmd.arg[3] << 16),
957 idx,
958 clock_ratios_table[idx].m_rat,
959 clock_ratios_table[idx].n_rat,
960 clock_ratios_table[idx].rate);
961
962 /* Set the clock */
963 cmd.id = CMD_CLOCK_SET;
964 cmd.len = 10;
965 cmd.arg[0] = 0;
966 cmd.arg[1] = 0x10;
967 cmd.arg[2] = (clock_ratios_table[idx].m_rat >> 16) & 0xff;
968 cmd.arg[3] = (clock_ratios_table[idx].m_rat >> 8) & 0xff;
969 cmd.arg[4] = (clock_ratios_table[idx].m_rat >> 0) & 0xff;
970 cmd.arg[5] = (clock_ratios_table[idx].n_rat >> 16) & 0xff;
971 cmd.arg[6] = (clock_ratios_table[idx].n_rat >> 8) & 0xff;
972 cmd.arg[7] = (clock_ratios_table[idx].n_rat >> 0) & 0xff;
973 cmd.arg[8] = (clock_ratios_table[idx].rate >> 8) & 0xff;
974 cmd.arg[9] = (clock_ratios_table[idx].rate >> 0) & 0xff;
975
976 ret = cx24120_message_send(state, cmd: &cmd);
977 if (ret != 0)
978 return;
979
980 /* Calculate ber window rates for stat work */
981 cx24120_calculate_ber_window(state, rate: clock_ratios_table[idx].rate);
982}
983
984/* Set inversion value */
985static int cx24120_set_inversion(struct cx24120_state *state,
986 enum fe_spectral_inversion inversion)
987{
988 dev_dbg(&state->i2c->dev, "(%d)\n", inversion);
989
990 switch (inversion) {
991 case INVERSION_OFF:
992 state->dnxt.inversion_val = 0x00;
993 break;
994 case INVERSION_ON:
995 state->dnxt.inversion_val = 0x04;
996 break;
997 case INVERSION_AUTO:
998 state->dnxt.inversion_val = 0x0c;
999 break;
1000 default:
1001 return -EINVAL;
1002 }
1003
1004 state->dnxt.inversion = inversion;
1005
1006 return 0;
1007}
1008
1009/* FEC lookup table for tuning */
1010struct cx24120_modfec_table {
1011 enum fe_delivery_system delsys;
1012 enum fe_modulation mod;
1013 enum fe_code_rate fec;
1014 u8 val;
1015};
1016
1017static const struct cx24120_modfec_table modfec_table[] = {
1018 /*delsys mod fec val */
1019 { SYS_DVBS, QPSK, FEC_1_2, 0x2e },
1020 { SYS_DVBS, QPSK, FEC_2_3, 0x2f },
1021 { SYS_DVBS, QPSK, FEC_3_4, 0x30 },
1022 { SYS_DVBS, QPSK, FEC_5_6, 0x31 },
1023 { SYS_DVBS, QPSK, FEC_6_7, 0x32 },
1024 { SYS_DVBS, QPSK, FEC_7_8, 0x33 },
1025
1026 { SYS_DVBS2, QPSK, FEC_1_2, 0x04 },
1027 { SYS_DVBS2, QPSK, FEC_3_5, 0x05 },
1028 { SYS_DVBS2, QPSK, FEC_2_3, 0x06 },
1029 { SYS_DVBS2, QPSK, FEC_3_4, 0x07 },
1030 { SYS_DVBS2, QPSK, FEC_4_5, 0x08 },
1031 { SYS_DVBS2, QPSK, FEC_5_6, 0x09 },
1032 { SYS_DVBS2, QPSK, FEC_8_9, 0x0a },
1033 { SYS_DVBS2, QPSK, FEC_9_10, 0x0b },
1034
1035 { SYS_DVBS2, PSK_8, FEC_3_5, 0x0c },
1036 { SYS_DVBS2, PSK_8, FEC_2_3, 0x0d },
1037 { SYS_DVBS2, PSK_8, FEC_3_4, 0x0e },
1038 { SYS_DVBS2, PSK_8, FEC_5_6, 0x0f },
1039 { SYS_DVBS2, PSK_8, FEC_8_9, 0x10 },
1040 { SYS_DVBS2, PSK_8, FEC_9_10, 0x11 },
1041};
1042
1043/* Set fec_val & fec_mask values from delsys, modulation & fec */
1044static int cx24120_set_fec(struct cx24120_state *state, enum fe_modulation mod,
1045 enum fe_code_rate fec)
1046{
1047 int idx;
1048
1049 dev_dbg(&state->i2c->dev, "(0x%02x,0x%02x)\n", mod, fec);
1050
1051 state->dnxt.fec = fec;
1052
1053 /* Lookup fec_val from modfec table */
1054 for (idx = 0; idx < ARRAY_SIZE(modfec_table); idx++) {
1055 if (modfec_table[idx].delsys != state->dnxt.delsys)
1056 continue;
1057 if (modfec_table[idx].mod != mod)
1058 continue;
1059 if (modfec_table[idx].fec != fec)
1060 continue;
1061
1062 /* found */
1063 state->dnxt.fec_mask = 0x00;
1064 state->dnxt.fec_val = modfec_table[idx].val;
1065 return 0;
1066 }
1067
1068 if (state->dnxt.delsys == SYS_DVBS2) {
1069 /* DVBS2 auto is 0x00/0x00 */
1070 state->dnxt.fec_mask = 0x00;
1071 state->dnxt.fec_val = 0x00;
1072 } else {
1073 /* Set DVB-S to auto */
1074 state->dnxt.fec_val = 0x2e;
1075 state->dnxt.fec_mask = 0xac;
1076 }
1077
1078 return 0;
1079}
1080
1081/* Set pilot */
1082static int cx24120_set_pilot(struct cx24120_state *state, enum fe_pilot pilot)
1083{
1084 dev_dbg(&state->i2c->dev, "(%d)\n", pilot);
1085
1086 /* Pilot only valid in DVBS2 */
1087 if (state->dnxt.delsys != SYS_DVBS2) {
1088 state->dnxt.pilot_val = CX24120_PILOT_OFF;
1089 return 0;
1090 }
1091
1092 switch (pilot) {
1093 case PILOT_OFF:
1094 state->dnxt.pilot_val = CX24120_PILOT_OFF;
1095 break;
1096 case PILOT_ON:
1097 state->dnxt.pilot_val = CX24120_PILOT_ON;
1098 break;
1099 case PILOT_AUTO:
1100 default:
1101 state->dnxt.pilot_val = CX24120_PILOT_AUTO;
1102 }
1103
1104 return 0;
1105}
1106
1107/* Set symbol rate */
1108static int cx24120_set_symbolrate(struct cx24120_state *state, u32 rate)
1109{
1110 dev_dbg(&state->i2c->dev, "(%d)\n", rate);
1111
1112 state->dnxt.symbol_rate = rate;
1113
1114 /* Check symbol rate */
1115 if (rate > 31000000) {
1116 state->dnxt.clkdiv = (-(rate < 31000001) & 3) + 2;
1117 state->dnxt.ratediv = (-(rate < 31000001) & 6) + 4;
1118 } else {
1119 state->dnxt.clkdiv = 3;
1120 state->dnxt.ratediv = 6;
1121 }
1122
1123 return 0;
1124}
1125
1126/* Overwrite the current tuning params, we are about to tune */
1127static void cx24120_clone_params(struct dvb_frontend *fe)
1128{
1129 struct cx24120_state *state = fe->demodulator_priv;
1130
1131 state->dcur = state->dnxt;
1132}
1133
1134static int cx24120_set_frontend(struct dvb_frontend *fe)
1135{
1136 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1137 struct cx24120_state *state = fe->demodulator_priv;
1138 struct cx24120_cmd cmd;
1139 int ret;
1140
1141 switch (c->delivery_system) {
1142 case SYS_DVBS2:
1143 dev_dbg(&state->i2c->dev, "DVB-S2\n");
1144 break;
1145 case SYS_DVBS:
1146 dev_dbg(&state->i2c->dev, "DVB-S\n");
1147 break;
1148 default:
1149 dev_dbg(&state->i2c->dev,
1150 "delivery system(%d) not supported\n",
1151 c->delivery_system);
1152 return -EINVAL;
1153 }
1154
1155 state->dnxt.delsys = c->delivery_system;
1156 state->dnxt.modulation = c->modulation;
1157 state->dnxt.frequency = c->frequency;
1158 state->dnxt.pilot = c->pilot;
1159
1160 ret = cx24120_set_inversion(state, inversion: c->inversion);
1161 if (ret != 0)
1162 return ret;
1163
1164 ret = cx24120_set_fec(state, mod: c->modulation, fec: c->fec_inner);
1165 if (ret != 0)
1166 return ret;
1167
1168 ret = cx24120_set_pilot(state, pilot: c->pilot);
1169 if (ret != 0)
1170 return ret;
1171
1172 ret = cx24120_set_symbolrate(state, rate: c->symbol_rate);
1173 if (ret != 0)
1174 return ret;
1175
1176 /* discard the 'current' tuning parameters and prepare to tune */
1177 cx24120_clone_params(fe);
1178
1179 dev_dbg(&state->i2c->dev,
1180 "delsys = %d\n", state->dcur.delsys);
1181 dev_dbg(&state->i2c->dev,
1182 "modulation = %d\n", state->dcur.modulation);
1183 dev_dbg(&state->i2c->dev,
1184 "frequency = %d\n", state->dcur.frequency);
1185 dev_dbg(&state->i2c->dev,
1186 "pilot = %d (val = 0x%02x)\n",
1187 state->dcur.pilot, state->dcur.pilot_val);
1188 dev_dbg(&state->i2c->dev,
1189 "symbol_rate = %d (clkdiv/ratediv = 0x%02x/0x%02x)\n",
1190 state->dcur.symbol_rate,
1191 state->dcur.clkdiv, state->dcur.ratediv);
1192 dev_dbg(&state->i2c->dev,
1193 "FEC = %d (mask/val = 0x%02x/0x%02x)\n",
1194 state->dcur.fec, state->dcur.fec_mask, state->dcur.fec_val);
1195 dev_dbg(&state->i2c->dev,
1196 "Inversion = %d (val = 0x%02x)\n",
1197 state->dcur.inversion, state->dcur.inversion_val);
1198
1199 /* Flag that clock needs to be set after tune */
1200 state->need_clock_set = 1;
1201
1202 /* Tune in */
1203 cmd.id = CMD_TUNEREQUEST;
1204 cmd.len = 15;
1205 cmd.arg[0] = 0;
1206 cmd.arg[1] = (state->dcur.frequency & 0xff0000) >> 16;
1207 cmd.arg[2] = (state->dcur.frequency & 0x00ff00) >> 8;
1208 cmd.arg[3] = (state->dcur.frequency & 0x0000ff);
1209 cmd.arg[4] = ((state->dcur.symbol_rate / 1000) & 0xff00) >> 8;
1210 cmd.arg[5] = ((state->dcur.symbol_rate / 1000) & 0x00ff);
1211 cmd.arg[6] = state->dcur.inversion;
1212 cmd.arg[7] = state->dcur.fec_val | state->dcur.pilot_val;
1213 cmd.arg[8] = CX24120_SEARCH_RANGE_KHZ >> 8;
1214 cmd.arg[9] = CX24120_SEARCH_RANGE_KHZ & 0xff;
1215 cmd.arg[10] = 0; /* maybe rolloff? */
1216 cmd.arg[11] = state->dcur.fec_mask;
1217 cmd.arg[12] = state->dcur.ratediv;
1218 cmd.arg[13] = state->dcur.clkdiv;
1219 cmd.arg[14] = 0;
1220
1221 /* Send tune command */
1222 ret = cx24120_message_send(state, cmd: &cmd);
1223 if (ret != 0)
1224 return ret;
1225
1226 /* Write symbol rate values */
1227 ret = cx24120_writereg(state, CX24120_REG_CLKDIV, data: state->dcur.clkdiv);
1228 ret = cx24120_readreg(state, CX24120_REG_RATEDIV);
1229 ret &= 0xfffffff0;
1230 ret |= state->dcur.ratediv;
1231 ret = cx24120_writereg(state, CX24120_REG_RATEDIV, data: ret);
1232
1233 return 0;
1234}
1235
1236/* Set vco from config */
1237static int cx24120_set_vco(struct cx24120_state *state)
1238{
1239 struct cx24120_cmd cmd;
1240 u32 nxtal_khz, vco;
1241 u64 inv_vco;
1242 u32 xtal_khz = state->config->xtal_khz;
1243
1244 nxtal_khz = xtal_khz * 4;
1245 vco = nxtal_khz * 10;
1246 inv_vco = DIV_ROUND_CLOSEST_ULL(0x400000000ULL, vco);
1247
1248 dev_dbg(&state->i2c->dev, "xtal=%d, vco=%d, inv_vco=%lld\n",
1249 xtal_khz, vco, inv_vco);
1250
1251 cmd.id = CMD_VCO_SET;
1252 cmd.len = 12;
1253 cmd.arg[0] = (vco >> 16) & 0xff;
1254 cmd.arg[1] = (vco >> 8) & 0xff;
1255 cmd.arg[2] = vco & 0xff;
1256 cmd.arg[3] = (inv_vco >> 8) & 0xff;
1257 cmd.arg[4] = (inv_vco) & 0xff;
1258 cmd.arg[5] = 0x03;
1259 cmd.arg[6] = (nxtal_khz >> 8) & 0xff;
1260 cmd.arg[7] = nxtal_khz & 0xff;
1261 cmd.arg[8] = 0x06;
1262 cmd.arg[9] = 0x03;
1263 cmd.arg[10] = (xtal_khz >> 16) & 0xff;
1264 cmd.arg[11] = xtal_khz & 0xff;
1265
1266 return cx24120_message_send(state, cmd: &cmd);
1267}
1268
1269static int cx24120_init(struct dvb_frontend *fe)
1270{
1271 const struct firmware *fw;
1272 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1273 struct cx24120_state *state = fe->demodulator_priv;
1274 struct cx24120_cmd cmd;
1275 u8 reg;
1276 int ret, i;
1277 unsigned char vers[4];
1278
1279 if (state->cold_init)
1280 return 0;
1281
1282 /* ???? */
1283 cx24120_writereg(state, reg: 0xea, data: 0x00);
1284 cx24120_test_rom(state);
1285 reg = cx24120_readreg(state, reg: 0xfb) & 0xfe;
1286 cx24120_writereg(state, reg: 0xfb, data: reg);
1287 reg = cx24120_readreg(state, reg: 0xfc) & 0xfe;
1288 cx24120_writereg(state, reg: 0xfc, data: reg);
1289 cx24120_writereg(state, reg: 0xc3, data: 0x04);
1290 cx24120_writereg(state, reg: 0xc4, data: 0x04);
1291 cx24120_writereg(state, reg: 0xce, data: 0x00);
1292 cx24120_writereg(state, reg: 0xcf, data: 0x00);
1293 reg = cx24120_readreg(state, reg: 0xea) & 0xfe;
1294 cx24120_writereg(state, reg: 0xea, data: reg);
1295 cx24120_writereg(state, reg: 0xeb, data: 0x0c);
1296 cx24120_writereg(state, reg: 0xec, data: 0x06);
1297 cx24120_writereg(state, reg: 0xed, data: 0x05);
1298 cx24120_writereg(state, reg: 0xee, data: 0x03);
1299 cx24120_writereg(state, reg: 0xef, data: 0x05);
1300 cx24120_writereg(state, reg: 0xf3, data: 0x03);
1301 cx24120_writereg(state, reg: 0xf4, data: 0x44);
1302
1303 for (i = 0; i < 3; i++) {
1304 cx24120_writereg(state, reg: 0xf0 + i, data: 0x04);
1305 cx24120_writereg(state, reg: 0xe6 + i, data: 0x02);
1306 }
1307
1308 cx24120_writereg(state, reg: 0xea, data: (reg | 0x01));
1309 for (i = 0; i < 6; i += 2) {
1310 cx24120_writereg(state, reg: 0xc5 + i, data: 0x00);
1311 cx24120_writereg(state, reg: 0xc6 + i, data: 0x00);
1312 }
1313
1314 cx24120_writereg(state, reg: 0xe4, data: 0x03);
1315 cx24120_writereg(state, reg: 0xeb, data: 0x0a);
1316
1317 dev_dbg(&state->i2c->dev, "requesting firmware (%s) to download...\n",
1318 CX24120_FIRMWARE);
1319
1320 ret = state->config->request_firmware(fe, &fw, CX24120_FIRMWARE);
1321 if (ret) {
1322 err("Could not load firmware (%s): %d\n", CX24120_FIRMWARE,
1323 ret);
1324 return ret;
1325 }
1326
1327 dev_dbg(&state->i2c->dev,
1328 "Firmware found, size %d bytes (%02x %02x .. %02x %02x)\n",
1329 (int)fw->size, /* firmware_size in bytes */
1330 fw->data[0], /* fw 1st byte */
1331 fw->data[1], /* fw 2d byte */
1332 fw->data[fw->size - 2], /* fw before last byte */
1333 fw->data[fw->size - 1]); /* fw last byte */
1334
1335 cx24120_test_rom(state);
1336 reg = cx24120_readreg(state, reg: 0xfb) & 0xfe;
1337 cx24120_writereg(state, reg: 0xfb, data: reg);
1338 cx24120_writereg(state, reg: 0xe0, data: 0x76);
1339 cx24120_writereg(state, reg: 0xf7, data: 0x81);
1340 cx24120_writereg(state, reg: 0xf8, data: 0x00);
1341 cx24120_writereg(state, reg: 0xf9, data: 0x00);
1342 cx24120_writeregs(state, reg: 0xfa, values: fw->data, len: (fw->size - 1), incr: 0x00);
1343 cx24120_writereg(state, reg: 0xf7, data: 0xc0);
1344 cx24120_writereg(state, reg: 0xe0, data: 0x00);
1345 reg = (fw->size - 2) & 0x00ff;
1346 cx24120_writereg(state, reg: 0xf8, data: reg);
1347 reg = ((fw->size - 2) >> 8) & 0x00ff;
1348 cx24120_writereg(state, reg: 0xf9, data: reg);
1349 cx24120_writereg(state, reg: 0xf7, data: 0x00);
1350 cx24120_writereg(state, reg: 0xdc, data: 0x00);
1351 cx24120_writereg(state, reg: 0xdc, data: 0x07);
1352 msleep(msecs: 500);
1353
1354 /* Check final byte matches final byte of firmware */
1355 reg = cx24120_readreg(state, reg: 0xe1);
1356 if (reg == fw->data[fw->size - 1]) {
1357 dev_dbg(&state->i2c->dev, "Firmware uploaded successfully\n");
1358 ret = 0;
1359 } else {
1360 err("Firmware upload failed. Last byte returned=0x%x\n", ret);
1361 ret = -EREMOTEIO;
1362 }
1363 cx24120_writereg(state, reg: 0xdc, data: 0x00);
1364 release_firmware(fw);
1365 if (ret != 0)
1366 return ret;
1367
1368 /* Start tuner */
1369 cmd.id = CMD_START_TUNER;
1370 cmd.len = 3;
1371 cmd.arg[0] = 0x00;
1372 cmd.arg[1] = 0x00;
1373 cmd.arg[2] = 0x00;
1374
1375 if (cx24120_message_send(state, cmd: &cmd) != 0) {
1376 err("Error tuner start! :(\n");
1377 return -EREMOTEIO;
1378 }
1379
1380 /* Set VCO */
1381 ret = cx24120_set_vco(state);
1382 if (ret != 0) {
1383 err("Error set VCO! :(\n");
1384 return ret;
1385 }
1386
1387 /* set bandwidth */
1388 cmd.id = CMD_BANDWIDTH;
1389 cmd.len = 12;
1390 cmd.arg[0] = 0x00;
1391 cmd.arg[1] = 0x00;
1392 cmd.arg[2] = 0x00;
1393 cmd.arg[3] = 0x00;
1394 cmd.arg[4] = 0x05;
1395 cmd.arg[5] = 0x02;
1396 cmd.arg[6] = 0x02;
1397 cmd.arg[7] = 0x00;
1398 cmd.arg[8] = 0x05;
1399 cmd.arg[9] = 0x02;
1400 cmd.arg[10] = 0x02;
1401 cmd.arg[11] = 0x00;
1402
1403 if (cx24120_message_send(state, cmd: &cmd)) {
1404 err("Error set bandwidth!\n");
1405 return -EREMOTEIO;
1406 }
1407
1408 reg = cx24120_readreg(state, reg: 0xba);
1409 if (reg > 3) {
1410 dev_dbg(&state->i2c->dev, "Reset-readreg 0xba: %x\n", ret);
1411 err("Error initialising tuner!\n");
1412 return -EREMOTEIO;
1413 }
1414
1415 dev_dbg(&state->i2c->dev, "Tuner initialised correctly.\n");
1416
1417 /* Initialise mpeg outputs */
1418 cx24120_writereg(state, reg: 0xeb, data: 0x0a);
1419 if (cx24120_msg_mpeg_output_global_config(state, enable: 0) ||
1420 cx24120_msg_mpeg_output_config(state, seq: 0) ||
1421 cx24120_msg_mpeg_output_config(state, seq: 1) ||
1422 cx24120_msg_mpeg_output_config(state, seq: 2)) {
1423 err("Error initialising mpeg output. :(\n");
1424 return -EREMOTEIO;
1425 }
1426
1427 /* Set size of BER window */
1428 cmd.id = CMD_BER_CTRL;
1429 cmd.len = 3;
1430 cmd.arg[0] = 0x00;
1431 cmd.arg[1] = CX24120_BER_WINDOW;
1432 cmd.arg[2] = CX24120_BER_WINDOW;
1433 if (cx24120_message_send(state, cmd: &cmd)) {
1434 err("Error setting ber window\n");
1435 return -EREMOTEIO;
1436 }
1437
1438 /* Firmware CMD 35: Get firmware version */
1439 cmd.id = CMD_FWVERSION;
1440 cmd.len = 1;
1441 for (i = 0; i < 4; i++) {
1442 cmd.arg[0] = i;
1443 ret = cx24120_message_send(state, cmd: &cmd);
1444 if (ret != 0)
1445 return ret;
1446 vers[i] = cx24120_readreg(state, CX24120_REG_MAILBOX);
1447 }
1448 info("FW version %i.%i.%i.%i\n", vers[0], vers[1], vers[2], vers[3]);
1449
1450 /* init stats here in order signal app which stats are supported */
1451 c->strength.len = 1;
1452 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1453 c->cnr.len = 1;
1454 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1455 c->post_bit_error.len = 1;
1456 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1457 c->post_bit_count.len = 1;
1458 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1459 c->block_error.len = 1;
1460 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1461 c->block_count.len = 1;
1462 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1463
1464 state->cold_init = 1;
1465
1466 return 0;
1467}
1468
1469static int cx24120_tune(struct dvb_frontend *fe, bool re_tune,
1470 unsigned int mode_flags, unsigned int *delay,
1471 enum fe_status *status)
1472{
1473 struct cx24120_state *state = fe->demodulator_priv;
1474 int ret;
1475
1476 dev_dbg(&state->i2c->dev, "(%d)\n", re_tune);
1477
1478 /* TODO: Do we need to set delay? */
1479
1480 if (re_tune) {
1481 ret = cx24120_set_frontend(fe);
1482 if (ret)
1483 return ret;
1484 }
1485
1486 return cx24120_read_status(fe, status);
1487}
1488
1489static enum dvbfe_algo cx24120_get_algo(struct dvb_frontend *fe)
1490{
1491 return DVBFE_ALGO_HW;
1492}
1493
1494static int cx24120_sleep(struct dvb_frontend *fe)
1495{
1496 return 0;
1497}
1498
1499static int cx24120_get_frontend(struct dvb_frontend *fe,
1500 struct dtv_frontend_properties *c)
1501{
1502 struct cx24120_state *state = fe->demodulator_priv;
1503 u8 freq1, freq2, freq3;
1504 int status;
1505
1506 dev_dbg(&state->i2c->dev, "\n");
1507
1508 /* don't return empty data if we're not tuned in */
1509 status = cx24120_readreg(state, CX24120_REG_STATUS);
1510 if (!(status & CX24120_HAS_LOCK))
1511 return 0;
1512
1513 /* Get frequency */
1514 freq1 = cx24120_readreg(state, CX24120_REG_FREQ1);
1515 freq2 = cx24120_readreg(state, CX24120_REG_FREQ2);
1516 freq3 = cx24120_readreg(state, CX24120_REG_FREQ3);
1517 c->frequency = (freq3 << 16) | (freq2 << 8) | freq1;
1518 dev_dbg(&state->i2c->dev, "frequency = %d\n", c->frequency);
1519
1520 /* Get modulation, fec, pilot */
1521 cx24120_get_fec(fe);
1522
1523 return 0;
1524}
1525
1526static void cx24120_release(struct dvb_frontend *fe)
1527{
1528 struct cx24120_state *state = fe->demodulator_priv;
1529
1530 dev_dbg(&state->i2c->dev, "Clear state structure\n");
1531 kfree(objp: state);
1532}
1533
1534static int cx24120_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1535{
1536 struct cx24120_state *state = fe->demodulator_priv;
1537 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1538
1539 if (c->block_error.stat[0].scale != FE_SCALE_COUNTER) {
1540 *ucblocks = 0;
1541 return 0;
1542 }
1543
1544 *ucblocks = c->block_error.stat[0].uvalue - state->ucb_offset;
1545
1546 return 0;
1547}
1548
1549static const struct dvb_frontend_ops cx24120_ops = {
1550 .delsys = { SYS_DVBS, SYS_DVBS2 },
1551 .info = {
1552 .name = "Conexant CX24120/CX24118",
1553 .frequency_min_hz = 950 * MHz,
1554 .frequency_max_hz = 2150 * MHz,
1555 .frequency_stepsize_hz = 1011 * kHz,
1556 .frequency_tolerance_hz = 5 * MHz,
1557 .symbol_rate_min = 1000000,
1558 .symbol_rate_max = 45000000,
1559 .caps = FE_CAN_INVERSION_AUTO |
1560 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1561 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1562 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1563 FE_CAN_2G_MODULATION |
1564 FE_CAN_QPSK | FE_CAN_RECOVER
1565 },
1566 .release = cx24120_release,
1567
1568 .init = cx24120_init,
1569 .sleep = cx24120_sleep,
1570
1571 .tune = cx24120_tune,
1572 .get_frontend_algo = cx24120_get_algo,
1573 .set_frontend = cx24120_set_frontend,
1574
1575 .get_frontend = cx24120_get_frontend,
1576 .read_status = cx24120_read_status,
1577 .read_ber = cx24120_read_ber,
1578 .read_signal_strength = cx24120_read_signal_strength,
1579 .read_snr = cx24120_read_snr,
1580 .read_ucblocks = cx24120_read_ucblocks,
1581
1582 .diseqc_send_master_cmd = cx24120_send_diseqc_msg,
1583
1584 .diseqc_send_burst = cx24120_diseqc_send_burst,
1585 .set_tone = cx24120_set_tone,
1586 .set_voltage = cx24120_set_voltage,
1587};
1588
1589MODULE_DESCRIPTION("DVB Frontend module for Conexant CX24120/CX24118 hardware");
1590MODULE_AUTHOR("Jemma Denson");
1591MODULE_LICENSE("GPL");
1592

source code of linux/drivers/media/dvb-frontends/cx24120.c