1/* SPDX-License-Identifier: GPL-2.0 */
2#include "drxk_map.h"
3
4#define DRXK_VERSION_MAJOR 0
5#define DRXK_VERSION_MINOR 9
6#define DRXK_VERSION_PATCH 4300
7
8#define HI_I2C_DELAY 42
9#define HI_I2C_BRIDGE_DELAY 350
10#define DRXK_MAX_RETRIES 100
11
12#define DRIVER_4400 1
13
14#define DRXX_JTAGID 0x039210D9
15#define DRXX_J_JTAGID 0x239310D9
16#define DRXX_K_JTAGID 0x039210D9
17
18#define DRX_UNKNOWN 254
19#define DRX_AUTO 255
20
21#define DRX_SCU_READY 0
22#define DRXK_MAX_WAITTIME (200)
23#define SCU_RESULT_OK 0
24#define SCU_RESULT_SIZE -4
25#define SCU_RESULT_INVPAR -3
26#define SCU_RESULT_UNKSTD -2
27#define SCU_RESULT_UNKCMD -1
28
29#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT
30#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200)
31#endif
32
33#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/
34#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/
35#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/
36#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/
37#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/
38#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/
39#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/
40#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/
41
42#define IQM_CF_OUT_ENA_OFDM__M 0x4
43#define IQM_FS_ADJ_SEL_B_QAM 0x1
44#define IQM_FS_ADJ_SEL_B_OFF 0x0
45#define IQM_FS_ADJ_SEL_B_VSB 0x2
46#define IQM_RC_ADJ_SEL_B_OFF 0x0
47#define IQM_RC_ADJ_SEL_B_QAM 0x1
48#define IQM_RC_ADJ_SEL_B_VSB 0x2
49
50enum operation_mode {
51 OM_NONE,
52 OM_QAM_ITU_A,
53 OM_QAM_ITU_B,
54 OM_QAM_ITU_C,
55 OM_DVBT
56};
57
58enum drx_power_mode {
59 DRX_POWER_UP = 0,
60 DRX_POWER_MODE_1,
61 DRX_POWER_MODE_2,
62 DRX_POWER_MODE_3,
63 DRX_POWER_MODE_4,
64 DRX_POWER_MODE_5,
65 DRX_POWER_MODE_6,
66 DRX_POWER_MODE_7,
67 DRX_POWER_MODE_8,
68
69 DRX_POWER_MODE_9,
70 DRX_POWER_MODE_10,
71 DRX_POWER_MODE_11,
72 DRX_POWER_MODE_12,
73 DRX_POWER_MODE_13,
74 DRX_POWER_MODE_14,
75 DRX_POWER_MODE_15,
76 DRX_POWER_MODE_16,
77 DRX_POWER_DOWN = 255
78};
79
80
81/* Intermediate power mode for DRXK, power down OFDM clock domain */
82#ifndef DRXK_POWER_DOWN_OFDM
83#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1
84#endif
85
86/* Intermediate power mode for DRXK, power down core (sysclk) */
87#ifndef DRXK_POWER_DOWN_CORE
88#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9
89#endif
90
91/* Intermediate power mode for DRXK, power down pll (only osc runs) */
92#ifndef DRXK_POWER_DOWN_PLL
93#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10
94#endif
95
96
97enum agc_ctrl_mode {
98 DRXK_AGC_CTRL_AUTO = 0,
99 DRXK_AGC_CTRL_USER,
100 DRXK_AGC_CTRL_OFF
101};
102
103enum e_drxk_state {
104 DRXK_UNINITIALIZED = 0,
105 DRXK_STOPPED,
106 DRXK_DTV_STARTED,
107 DRXK_ATV_STARTED,
108 DRXK_POWERED_DOWN,
109 DRXK_NO_DEV /* If drxk init failed */
110};
111
112enum e_drxk_coef_array_index {
113 DRXK_COEF_IDX_MN = 0,
114 DRXK_COEF_IDX_FM ,
115 DRXK_COEF_IDX_L ,
116 DRXK_COEF_IDX_LP ,
117 DRXK_COEF_IDX_BG ,
118 DRXK_COEF_IDX_DK ,
119 DRXK_COEF_IDX_I ,
120 DRXK_COEF_IDX_MAX
121};
122enum e_drxk_sif_attenuation {
123 DRXK_SIF_ATTENUATION_0DB,
124 DRXK_SIF_ATTENUATION_3DB,
125 DRXK_SIF_ATTENUATION_6DB,
126 DRXK_SIF_ATTENUATION_9DB
127};
128enum e_drxk_constellation {
129 DRX_CONSTELLATION_BPSK = 0,
130 DRX_CONSTELLATION_QPSK,
131 DRX_CONSTELLATION_PSK8,
132 DRX_CONSTELLATION_QAM16,
133 DRX_CONSTELLATION_QAM32,
134 DRX_CONSTELLATION_QAM64,
135 DRX_CONSTELLATION_QAM128,
136 DRX_CONSTELLATION_QAM256,
137 DRX_CONSTELLATION_QAM512,
138 DRX_CONSTELLATION_QAM1024,
139 DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
140 DRX_CONSTELLATION_AUTO = DRX_AUTO
141};
142enum e_drxk_interleave_mode {
143 DRXK_QAM_I12_J17 = 16,
144 DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN
145};
146enum {
147 DRXK_SPIN_A1 = 0,
148 DRXK_SPIN_A2,
149 DRXK_SPIN_A3,
150 DRXK_SPIN_UNKNOWN
151};
152
153enum drxk_cfg_dvbt_sqi_speed {
154 DRXK_DVBT_SQI_SPEED_FAST = 0,
155 DRXK_DVBT_SQI_SPEED_MEDIUM,
156 DRXK_DVBT_SQI_SPEED_SLOW,
157 DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
158} ;
159
160enum drx_fftmode_t {
161 DRX_FFTMODE_2K = 0,
162 DRX_FFTMODE_4K,
163 DRX_FFTMODE_8K,
164 DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
165 DRX_FFTMODE_AUTO = DRX_AUTO
166};
167
168enum drxmpeg_str_width_t {
169 DRX_MPEG_STR_WIDTH_1,
170 DRX_MPEG_STR_WIDTH_8
171};
172
173enum drx_qam_lock_range_t {
174 DRX_QAM_LOCKRANGE_NORMAL,
175 DRX_QAM_LOCKRANGE_EXTENDED
176};
177
178struct drxk_cfg_dvbt_echo_thres_t {
179 u16 threshold;
180 enum drx_fftmode_t fft_mode;
181} ;
182
183struct s_cfg_agc {
184 enum agc_ctrl_mode ctrl_mode; /* off, user, auto */
185 u16 output_level; /* range dependent on AGC */
186 u16 min_output_level; /* range dependent on AGC */
187 u16 max_output_level; /* range dependent on AGC */
188 u16 speed; /* range dependent on AGC */
189 u16 top; /* rf-agc take over point */
190 u16 cut_off_current; /* rf-agc is accelerated if output current
191 is below cut-off current */
192 u16 ingain_tgt_max;
193 u16 fast_clip_ctrl_delay;
194};
195
196struct s_cfg_pre_saw {
197 u16 reference; /* pre SAW reference value, range 0 .. 31 */
198 bool use_pre_saw; /* TRUE algorithms must use pre SAW sense */
199};
200
201struct drxk_ofdm_sc_cmd_t {
202 u16 cmd; /* Command number */
203 u16 subcmd; /* Sub-command parameter*/
204 u16 param0; /* General purpous param */
205 u16 param1; /* General purpous param */
206 u16 param2; /* General purpous param */
207 u16 param3; /* General purpous param */
208 u16 param4; /* General purpous param */
209};
210
211struct drxk_state {
212 struct dvb_frontend frontend;
213 struct dtv_frontend_properties props;
214 struct device *dev;
215
216 struct i2c_adapter *i2c;
217 u8 demod_address;
218 void *priv;
219
220 struct mutex mutex;
221
222 u32 m_instance; /* Channel 1,2,3 or 4 */
223
224 int m_chunk_size;
225 u8 chunk[256];
226
227 bool m_has_lna;
228 bool m_has_dvbt;
229 bool m_has_dvbc;
230 bool m_has_audio;
231 bool m_has_atv;
232 bool m_has_oob;
233 bool m_has_sawsw; /* TRUE if mat_tx is available */
234 bool m_has_gpio1; /* TRUE if mat_rx is available */
235 bool m_has_gpio2; /* TRUE if GPIO is available */
236 bool m_has_irqn; /* TRUE if IRQN is available */
237 u16 m_osc_clock_freq;
238 u16 m_hi_cfg_timing_div;
239 u16 m_hi_cfg_bridge_delay;
240 u16 m_hi_cfg_wake_up_key;
241 u16 m_hi_cfg_timeout;
242 u16 m_hi_cfg_ctrl;
243 s32 m_sys_clock_freq; /* system clock frequency in kHz */
244
245 enum e_drxk_state m_drxk_state; /* State of Drxk (init,stopped,started) */
246 enum operation_mode m_operation_mode; /* digital standards */
247 struct s_cfg_agc m_vsb_rf_agc_cfg; /* settings for VSB RF-AGC */
248 struct s_cfg_agc m_vsb_if_agc_cfg; /* settings for VSB IF-AGC */
249 u16 m_vsb_pga_cfg; /* settings for VSB PGA */
250 struct s_cfg_pre_saw m_vsb_pre_saw_cfg; /* settings for pre SAW sense */
251 s32 m_Quality83percent; /* MER level (*0.1 dB) for 83% quality indication */
252 s32 m_Quality93percent; /* MER level (*0.1 dB) for 93% quality indication */
253 bool m_smart_ant_inverted;
254 bool m_b_debug_enable_bridge;
255 bool m_b_p_down_open_bridge; /* only open DRXK bridge before power-down once it has been accessed */
256 bool m_b_power_down; /* Power down when not used */
257
258 u32 m_iqm_fs_rate_ofs; /* frequency shift as written to DRXK register (28bit fixpoint) */
259
260 bool m_enable_mpeg_output; /* If TRUE, enable MPEG output */
261 bool m_insert_rs_byte; /* If TRUE, insert RS byte */
262 bool m_enable_parallel; /* If TRUE, parallel out otherwise serial */
263 bool m_invert_data; /* If TRUE, invert DATA signals */
264 bool m_invert_err; /* If TRUE, invert ERR signal */
265 bool m_invert_str; /* If TRUE, invert STR signals */
266 bool m_invert_val; /* If TRUE, invert VAL signals */
267 bool m_invert_clk; /* If TRUE, invert CLK signals */
268 bool m_dvbc_static_clk;
269 bool m_dvbt_static_clk; /* If TRUE, static MPEG clockrate will
270 be used, otherwise clockrate will
271 adapt to the bitrate of the TS */
272 u32 m_dvbt_bitrate;
273 u32 m_dvbc_bitrate;
274
275 u8 m_ts_data_strength;
276 u8 m_ts_clockk_strength;
277
278 bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */
279
280 enum drxmpeg_str_width_t m_width_str; /* MPEG start width */
281 u32 m_mpeg_ts_static_bitrate; /* Maximum bitrate in b/s in case
282 static clockrate is selected */
283
284 /* LARGE_INTEGER m_startTime; */ /* Contains the time of the last demod start */
285 s32 m_mpeg_lock_time_out; /* WaitForLockStatus Timeout (counts from start time) */
286 s32 m_demod_lock_time_out; /* WaitForLockStatus Timeout (counts from start time) */
287
288 bool m_disable_te_ihandling;
289
290 bool m_rf_agc_pol;
291 bool m_if_agc_pol;
292
293 struct s_cfg_agc m_atv_rf_agc_cfg; /* settings for ATV RF-AGC */
294 struct s_cfg_agc m_atv_if_agc_cfg; /* settings for ATV IF-AGC */
295 struct s_cfg_pre_saw m_atv_pre_saw_cfg; /* settings for ATV pre SAW sense */
296 bool m_phase_correction_bypass;
297 s16 m_atv_top_vid_peak;
298 u16 m_atv_top_noise_th;
299 enum e_drxk_sif_attenuation m_sif_attenuation;
300 bool m_enable_cvbs_output;
301 bool m_enable_sif_output;
302 bool m_b_mirror_freq_spect;
303 enum e_drxk_constellation m_constellation; /* constellation type of the channel */
304 u32 m_curr_symbol_rate; /* Current QAM symbol rate */
305 struct s_cfg_agc m_qam_rf_agc_cfg; /* settings for QAM RF-AGC */
306 struct s_cfg_agc m_qam_if_agc_cfg; /* settings for QAM IF-AGC */
307 u16 m_qam_pga_cfg; /* settings for QAM PGA */
308 struct s_cfg_pre_saw m_qam_pre_saw_cfg; /* settings for QAM pre SAW sense */
309 enum e_drxk_interleave_mode m_qam_interleave_mode; /* QAM Interleave mode */
310 u16 m_fec_rs_plen;
311 u16 m_fec_rs_prescale;
312
313 enum drxk_cfg_dvbt_sqi_speed m_sqi_speed;
314
315 u16 m_gpio;
316 u16 m_gpio_cfg;
317
318 struct s_cfg_agc m_dvbt_rf_agc_cfg; /* settings for QAM RF-AGC */
319 struct s_cfg_agc m_dvbt_if_agc_cfg; /* settings for QAM IF-AGC */
320 struct s_cfg_pre_saw m_dvbt_pre_saw_cfg; /* settings for QAM pre SAW sense */
321
322 u16 m_agcfast_clip_ctrl_delay;
323 bool m_adc_comp_passed;
324 u16 m_adcCompCoef[64];
325 u16 m_adc_state;
326
327 u8 *m_microcode;
328 int m_microcode_length;
329 bool m_drxk_a3_rom_code;
330 bool m_drxk_a3_patch_code;
331
332 bool m_rfmirror;
333 u8 m_device_spin;
334 u32 m_iqm_rc_rate;
335
336 enum drx_power_mode m_current_power_mode;
337
338 /* when true, avoids other devices to use the I2C bus */
339 bool drxk_i2c_exclusive_lock;
340
341 /*
342 * Configurable parameters at the driver. They stores the values found
343 * at struct drxk_config.
344 */
345
346 u16 uio_mask; /* Bits used by UIO */
347
348 bool enable_merr_cfg;
349 bool single_master;
350 bool no_i2c_bridge;
351 bool antenna_dvbt;
352 u16 antenna_gpio;
353
354 enum fe_status fe_status;
355
356 /* Firmware */
357 const char *microcode_name;
358 struct completion fw_wait_load;
359 const struct firmware *fw;
360 int qam_demod_parameter_count;
361};
362
363#define NEVER_LOCK 0
364#define NOT_LOCKED 1
365#define DEMOD_LOCK 2
366#define FEC_LOCK 3
367#define MPEG_LOCK 4
368
369

source code of linux/drivers/media/dvb-frontends/drxk_hard.h