1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* drxk_hard: DRX-K DVB-C/T demodulator driver
4	*
5	* Copyright (C) 2010-2011 Digital Devices GmbH
6	*/
7
8	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10	#include <linux/kernel.h>
11	#include <linux/module.h>
12	#include <linux/moduleparam.h>
13	#include <linux/init.h>
14	#include <linux/delay.h>
15	#include <linux/firmware.h>
16	#include <linux/i2c.h>
17	#include <linux/hardirq.h>
18	#include <asm/div64.h>
19
20	#include <media/dvb_frontend.h>
21	#include "drxk.h"
22	#include "drxk_hard.h"
23	#include <linux/int_log.h>
24
25	static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
26	static int power_down_qam(struct drxk_state *state);
27	static int set_dvbt_standard(struct drxk_state *state,
28	enum operation_mode o_mode);
29	static int set_qam_standard(struct drxk_state *state,
30	enum operation_mode o_mode);
31	static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
32	s32 tuner_freq_offset);
33	static int set_dvbt_standard(struct drxk_state *state,
34	enum operation_mode o_mode);
35	static int dvbt_start(struct drxk_state *state);
36	static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
37	s32 tuner_freq_offset);
38	static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
39	static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
40	static int switch_antenna_to_qam(struct drxk_state *state);
41	static int switch_antenna_to_dvbt(struct drxk_state *state);
42
43	static bool is_dvbt(struct drxk_state *state)
44	{
45	return state->m_operation_mode == OM_DVBT;
46	}
47
48	static bool is_qam(struct drxk_state *state)
49	{
50	return state->m_operation_mode == OM_QAM_ITU_A ||
51	state->m_operation_mode == OM_QAM_ITU_B ||
52	state->m_operation_mode == OM_QAM_ITU_C;
53	}
54
55	#define NOA1ROM 0
56
57	#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
58	#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
59
60	#define DEFAULT_MER_83 165
61	#define DEFAULT_MER_93 250
62
63	#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
64	#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
65	#endif
66
67	#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
68	#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
69	#endif
70
71	#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
72	#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
73
74	#ifndef DRXK_KI_RAGC_ATV
75	#define DRXK_KI_RAGC_ATV 4
76	#endif
77	#ifndef DRXK_KI_IAGC_ATV
78	#define DRXK_KI_IAGC_ATV 6
79	#endif
80	#ifndef DRXK_KI_DAGC_ATV
81	#define DRXK_KI_DAGC_ATV 7
82	#endif
83
84	#ifndef DRXK_KI_RAGC_QAM
85	#define DRXK_KI_RAGC_QAM 3
86	#endif
87	#ifndef DRXK_KI_IAGC_QAM
88	#define DRXK_KI_IAGC_QAM 4
89	#endif
90	#ifndef DRXK_KI_DAGC_QAM
91	#define DRXK_KI_DAGC_QAM 7
92	#endif
93	#ifndef DRXK_KI_RAGC_DVBT
94	#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
95	#endif
96	#ifndef DRXK_KI_IAGC_DVBT
97	#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
98	#endif
99	#ifndef DRXK_KI_DAGC_DVBT
100	#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
101	#endif
102
103	#ifndef DRXK_AGC_DAC_OFFSET
104	#define DRXK_AGC_DAC_OFFSET (0x800)
105	#endif
106
107	#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
108	#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
109	#endif
110
111	#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
112	#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
113	#endif
114
115	#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
116	#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
117	#endif
118
119	#ifndef DRXK_QAM_SYMBOLRATE_MAX
120	#define DRXK_QAM_SYMBOLRATE_MAX (7233000)
121	#endif
122
123	#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
124	#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
125	#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
126	#define DRXK_BL_ROM_OFFSET_TAPS_BG 24
127	#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
128	#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
129	#define DRXK_BL_ROM_OFFSET_TAPS_FM 48
130	#define DRXK_BL_ROM_OFFSET_UCODE 0
131
132	#define DRXK_BLC_TIMEOUT 100
133
134	#define DRXK_BLCC_NR_ELEMENTS_TAPS 2
135	#define DRXK_BLCC_NR_ELEMENTS_UCODE 6
136
137	#define DRXK_BLDC_NR_ELEMENTS_TAPS 28
138
139	#ifndef DRXK_OFDM_NE_NOTCH_WIDTH
140	#define DRXK_OFDM_NE_NOTCH_WIDTH (4)
141	#endif
142
143	#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
144	#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
145	#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
146	#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
147	#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
148
149	static unsigned int debug;
150	module_param(debug, int, 0644);
151	MODULE_PARM_DESC(debug, "enable debug messages");
152
153	#define dprintk(level, fmt, arg...) do { \
154	if (debug >= level) \
155	printk(KERN_DEBUG KBUILD_MODNAME ": %s " fmt, __func__, ##arg); \
156	} while (0)
157
158	static inline u32 Frac28a(u32 a, u32 c)
159	{
160	int i = 0;
161	u32 Q1 = 0;
162	u32 R0 = 0;
163
164	R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
165	Q1 = a / c; /*
166	* integer part, only the 4 least significant
167	* bits will be visible in the result
168	*/
169
170	/* division using radix 16, 7 nibbles in the result */
171	for (i = 0; i < 7; i++) {
172	Q1 = (Q1 << 4) | (R0 / c);
173	R0 = (R0 % c) << 4;
174	}
175	/* rounding */
176	if ((R0 >> 3) >= c)
177	Q1++;
178
179	return Q1;
180	}
181
182	static inline u32 log10times100(u32 value)
183	{
184	return (100L * intlog10(value)) >> 24;
185	}
186
187	/***************************************************************************/
188	/* I2C **********************************************************************/
189	/***************************************************************************/
190
191	static int drxk_i2c_lock(struct drxk_state *state)
192	{
193	i2c_lock_bus(adapter: state->i2c, I2C_LOCK_SEGMENT);
194	state->drxk_i2c_exclusive_lock = true;
195
196	return 0;
197	}
198
199	static void drxk_i2c_unlock(struct drxk_state *state)
200	{
201	if (!state->drxk_i2c_exclusive_lock)
202	return;
203
204	i2c_unlock_bus(adapter: state->i2c, I2C_LOCK_SEGMENT);
205	state->drxk_i2c_exclusive_lock = false;
206	}
207
208	static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
209	unsigned len)
210	{
211	if (state->drxk_i2c_exclusive_lock)
212	return __i2c_transfer(adap: state->i2c, msgs, num: len);
213	else
214	return i2c_transfer(adap: state->i2c, msgs, num: len);
215	}
216
217	static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
218	{
219	struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
220	.buf = val, .len = 1}
221	};
222
223	return drxk_i2c_transfer(state, msgs, len: 1);
224	}
225
226	static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
227	{
228	int status;
229	struct i2c_msg msg = {
230	.addr = adr, .flags = 0, .buf = data, .len = len };
231
232	dprintk(3, ": %*ph\n", len, data);
233
234	status = drxk_i2c_transfer(state, msgs: &msg, len: 1);
235	if (status >= 0 && status != 1)
236	status = -EIO;
237
238	if (status < 0)
239	pr_err("i2c write error at addr 0x%02x\n", adr);
240
241	return status;
242	}
243
244	static int i2c_read(struct drxk_state *state,
245	u8 adr, u8 *msg, int len, u8 *answ, int alen)
246	{
247	int status;
248	struct i2c_msg msgs[2] = {
249	{.addr = adr, .flags = 0,
250	.buf = msg, .len = len},
251	{.addr = adr, .flags = I2C_M_RD,
252	.buf = answ, .len = alen}
253	};
254
255	status = drxk_i2c_transfer(state, msgs, len: 2);
256	if (status != 2) {
257	if (debug > 2)
258	pr_cont(": ERROR!\n");
259	if (status >= 0)
260	status = -EIO;
261
262	pr_err("i2c read error at addr 0x%02x\n", adr);
263	return status;
264	}
265	dprintk(3, ": read from %*ph, value = %*ph\n", len, msg, alen, answ);
266	return 0;
267	}
268
269	static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
270	{
271	int status;
272	u8 adr = state->demod_address, mm1[4], mm2[2], len;
273
274	if (state->single_master)
275	flags |= 0xC0;
276
277	if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
278	mm1[0] = (((reg << 1) & 0xFF) | 0x01);
279	mm1[1] = ((reg >> 16) & 0xFF);
280	mm1[2] = ((reg >> 24) & 0xFF) | flags;
281	mm1[3] = ((reg >> 7) & 0xFF);
282	len = 4;
283	} else {
284	mm1[0] = ((reg << 1) & 0xFF);
285	mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
286	len = 2;
287	}
288	dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
289	status = i2c_read(state, adr, msg: mm1, len, answ: mm2, alen: 2);
290	if (status < 0)
291	return status;
292	if (data)
293	*data = mm2[0] | (mm2[1] << 8);
294
295	return 0;
296	}
297
298	static int read16(struct drxk_state *state, u32 reg, u16 *data)
299	{
300	return read16_flags(state, reg, data, flags: 0);
301	}
302
303	static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
304	{
305	int status;
306	u8 adr = state->demod_address, mm1[4], mm2[4], len;
307
308	if (state->single_master)
309	flags |= 0xC0;
310
311	if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
312	mm1[0] = (((reg << 1) & 0xFF) | 0x01);
313	mm1[1] = ((reg >> 16) & 0xFF);
314	mm1[2] = ((reg >> 24) & 0xFF) | flags;
315	mm1[3] = ((reg >> 7) & 0xFF);
316	len = 4;
317	} else {
318	mm1[0] = ((reg << 1) & 0xFF);
319	mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
320	len = 2;
321	}
322	dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
323	status = i2c_read(state, adr, msg: mm1, len, answ: mm2, alen: 4);
324	if (status < 0)
325	return status;
326	if (data)
327	*data = mm2[0] | (mm2[1] << 8) |
328	(mm2[2] << 16) | (mm2[3] << 24);
329
330	return 0;
331	}
332
333	static int read32(struct drxk_state *state, u32 reg, u32 *data)
334	{
335	return read32_flags(state, reg, data, flags: 0);
336	}
337
338	static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
339	{
340	u8 adr = state->demod_address, mm[6], len;
341
342	if (state->single_master)
343	flags |= 0xC0;
344	if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
345	mm[0] = (((reg << 1) & 0xFF) | 0x01);
346	mm[1] = ((reg >> 16) & 0xFF);
347	mm[2] = ((reg >> 24) & 0xFF) | flags;
348	mm[3] = ((reg >> 7) & 0xFF);
349	len = 4;
350	} else {
351	mm[0] = ((reg << 1) & 0xFF);
352	mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
353	len = 2;
354	}
355	mm[len] = data & 0xff;
356	mm[len + 1] = (data >> 8) & 0xff;
357
358	dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
359	return i2c_write(state, adr, data: mm, len: len + 2);
360	}
361
362	static int write16(struct drxk_state *state, u32 reg, u16 data)
363	{
364	return write16_flags(state, reg, data, flags: 0);
365	}
366
367	static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
368	{
369	u8 adr = state->demod_address, mm[8], len;
370
371	if (state->single_master)
372	flags |= 0xC0;
373	if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
374	mm[0] = (((reg << 1) & 0xFF) | 0x01);
375	mm[1] = ((reg >> 16) & 0xFF);
376	mm[2] = ((reg >> 24) & 0xFF) | flags;
377	mm[3] = ((reg >> 7) & 0xFF);
378	len = 4;
379	} else {
380	mm[0] = ((reg << 1) & 0xFF);
381	mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
382	len = 2;
383	}
384	mm[len] = data & 0xff;
385	mm[len + 1] = (data >> 8) & 0xff;
386	mm[len + 2] = (data >> 16) & 0xff;
387	mm[len + 3] = (data >> 24) & 0xff;
388	dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
389
390	return i2c_write(state, adr, data: mm, len: len + 4);
391	}
392
393	static int write32(struct drxk_state *state, u32 reg, u32 data)
394	{
395	return write32_flags(state, reg, data, flags: 0);
396	}
397
398	static int write_block(struct drxk_state *state, u32 address,
399	const int block_size, const u8 p_block[])
400	{
401	int status = 0, blk_size = block_size;
402	u8 flags = 0;
403
404	if (state->single_master)
405	flags |= 0xC0;
406
407	while (blk_size > 0) {
408	int chunk = blk_size > state->m_chunk_size ?
409	state->m_chunk_size : blk_size;
410	u8 *adr_buf = &state->chunk[0];
411	u32 adr_length = 0;
412
413	if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) {
414	adr_buf[0] = (((address << 1) & 0xFF) | 0x01);
415	adr_buf[1] = ((address >> 16) & 0xFF);
416	adr_buf[2] = ((address >> 24) & 0xFF);
417	adr_buf[3] = ((address >> 7) & 0xFF);
418	adr_buf[2] |= flags;
419	adr_length = 4;
420	if (chunk == state->m_chunk_size)
421	chunk -= 2;
422	} else {
423	adr_buf[0] = ((address << 1) & 0xFF);
424	adr_buf[1] = (((address >> 16) & 0x0F) |
425	((address >> 18) & 0xF0));
426	adr_length = 2;
427	}
428	memcpy(&state->chunk[adr_length], p_block, chunk);
429	dprintk(2, "(0x%08x, 0x%02x)\n", address, flags);
430	if (p_block)
431	dprintk(2, "%*ph\n", chunk, p_block);
432	status = i2c_write(state, adr: state->demod_address,
433	data: &state->chunk[0], len: chunk + adr_length);
434	if (status < 0) {
435	pr_err("%s: i2c write error at addr 0x%02x\n",
436	__func__, address);
437	break;
438	}
439	p_block += chunk;
440	address += (chunk >> 1);
441	blk_size -= chunk;
442	}
443	return status;
444	}
445
446	#ifndef DRXK_MAX_RETRIES_POWERUP
447	#define DRXK_MAX_RETRIES_POWERUP 20
448	#endif
449
450	static int power_up_device(struct drxk_state *state)
451	{
452	int status;
453	u8 data = 0;
454	u16 retry_count = 0;
455
456	dprintk(1, "\n");
457
458	status = i2c_read1(state, adr: state->demod_address, val: &data);
459	if (status < 0) {
460	do {
461	data = 0;
462	status = i2c_write(state, adr: state->demod_address,
463	data: &data, len: 1);
464	usleep_range(min: 10000, max: 11000);
465	retry_count++;
466	if (status < 0)
467	continue;
468	status = i2c_read1(state, adr: state->demod_address,
469	val: &data);
470	} while (status < 0 &&
471	(retry_count < DRXK_MAX_RETRIES_POWERUP));
472	if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)
473	goto error;
474	}
475
476	/* Make sure all clk domains are active */
477	status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
478	if (status < 0)
479	goto error;
480	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
481	if (status < 0)
482	goto error;
483	/* Enable pll lock tests */
484	status = write16(state, SIO_CC_PLL_LOCK__A, data: 1);
485	if (status < 0)
486	goto error;
487
488	state->m_current_power_mode = DRX_POWER_UP;
489
490	error:
491	if (status < 0)
492	pr_err("Error %d on %s\n", status, __func__);
493
494	return status;
495	}
496
497
498	static int init_state(struct drxk_state *state)
499	{
500	/*
501	* FIXME: most (all?) of the values below should be moved into
502	* struct drxk_config, as they are probably board-specific
503	*/
504	u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO;
505	u32 ul_vsb_if_agc_output_level = 0;
506	u32 ul_vsb_if_agc_min_level = 0;
507	u32 ul_vsb_if_agc_max_level = 0x7FFF;
508	u32 ul_vsb_if_agc_speed = 3;
509
510	u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO;
511	u32 ul_vsb_rf_agc_output_level = 0;
512	u32 ul_vsb_rf_agc_min_level = 0;
513	u32 ul_vsb_rf_agc_max_level = 0x7FFF;
514	u32 ul_vsb_rf_agc_speed = 3;
515	u32 ul_vsb_rf_agc_top = 9500;
516	u32 ul_vsb_rf_agc_cut_off_current = 4000;
517
518	u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO;
519	u32 ul_atv_if_agc_output_level = 0;
520	u32 ul_atv_if_agc_min_level = 0;
521	u32 ul_atv_if_agc_max_level = 0;
522	u32 ul_atv_if_agc_speed = 3;
523
524	u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF;
525	u32 ul_atv_rf_agc_output_level = 0;
526	u32 ul_atv_rf_agc_min_level = 0;
527	u32 ul_atv_rf_agc_max_level = 0;
528	u32 ul_atv_rf_agc_top = 9500;
529	u32 ul_atv_rf_agc_cut_off_current = 4000;
530	u32 ul_atv_rf_agc_speed = 3;
531
532	u32 ulQual83 = DEFAULT_MER_83;
533	u32 ulQual93 = DEFAULT_MER_93;
534
535	u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
536	u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
537
538	/* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
539	/* io_pad_cfg_mode output mode is drive always */
540	/* io_pad_cfg_drive is set to power 2 (23 mA) */
541	u32 ul_gpio_cfg = 0x0113;
542	u32 ul_invert_ts_clock = 0;
543	u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
544	u32 ul_dvbt_bitrate = 50000000;
545	u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
546
547	u32 ul_insert_rs_byte = 0;
548
549	u32 ul_rf_mirror = 1;
550	u32 ul_power_down = 0;
551
552	dprintk(1, "\n");
553
554	state->m_has_lna = false;
555	state->m_has_dvbt = false;
556	state->m_has_dvbc = false;
557	state->m_has_atv = false;
558	state->m_has_oob = false;
559	state->m_has_audio = false;
560
561	if (!state->m_chunk_size)
562	state->m_chunk_size = 124;
563
564	state->m_osc_clock_freq = 0;
565	state->m_smart_ant_inverted = false;
566	state->m_b_p_down_open_bridge = false;
567
568	/* real system clock frequency in kHz */
569	state->m_sys_clock_freq = 151875;
570	/* Timing div, 250ns/Psys */
571	/* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
572	state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *
573	HI_I2C_DELAY) / 1000;
574	/* Clipping */
575	if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
576	state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
577	state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
578	/* port/bridge/power down ctrl */
579	state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
580
581	state->m_b_power_down = (ul_power_down != 0);
582
583	state->m_drxk_a3_patch_code = false;
584
585	/* Init AGC and PGA parameters */
586	/* VSB IF */
587	state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode;
588	state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level;
589	state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level;
590	state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level;
591	state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed;
592	state->m_vsb_pga_cfg = 140;
593
594	/* VSB RF */
595	state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode;
596	state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level;
597	state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level;
598	state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level;
599	state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed;
600	state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top;
601	state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current;
602	state->m_vsb_pre_saw_cfg.reference = 0x07;
603	state->m_vsb_pre_saw_cfg.use_pre_saw = true;
604
605	state->m_Quality83percent = DEFAULT_MER_83;
606	state->m_Quality93percent = DEFAULT_MER_93;
607	if (ulQual93 <= 500 && ulQual83 < ulQual93) {
608	state->m_Quality83percent = ulQual83;
609	state->m_Quality93percent = ulQual93;
610	}
611
612	/* ATV IF */
613	state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode;
614	state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level;
615	state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level;
616	state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level;
617	state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed;
618
619	/* ATV RF */
620	state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode;
621	state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level;
622	state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level;
623	state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level;
624	state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed;
625	state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top;
626	state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current;
627	state->m_atv_pre_saw_cfg.reference = 0x04;
628	state->m_atv_pre_saw_cfg.use_pre_saw = true;
629
630
631	/* DVBT RF */
632	state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
633	state->m_dvbt_rf_agc_cfg.output_level = 0;
634	state->m_dvbt_rf_agc_cfg.min_output_level = 0;
635	state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;
636	state->m_dvbt_rf_agc_cfg.top = 0x2100;
637	state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;
638	state->m_dvbt_rf_agc_cfg.speed = 1;
639
640
641	/* DVBT IF */
642	state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
643	state->m_dvbt_if_agc_cfg.output_level = 0;
644	state->m_dvbt_if_agc_cfg.min_output_level = 0;
645	state->m_dvbt_if_agc_cfg.max_output_level = 9000;
646	state->m_dvbt_if_agc_cfg.top = 13424;
647	state->m_dvbt_if_agc_cfg.cut_off_current = 0;
648	state->m_dvbt_if_agc_cfg.speed = 3;
649	state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;
650	state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;
651	/* state->m_dvbtPgaCfg = 140; */
652
653	state->m_dvbt_pre_saw_cfg.reference = 4;
654	state->m_dvbt_pre_saw_cfg.use_pre_saw = false;
655
656	/* QAM RF */
657	state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
658	state->m_qam_rf_agc_cfg.output_level = 0;
659	state->m_qam_rf_agc_cfg.min_output_level = 6023;
660	state->m_qam_rf_agc_cfg.max_output_level = 27000;
661	state->m_qam_rf_agc_cfg.top = 0x2380;
662	state->m_qam_rf_agc_cfg.cut_off_current = 4000;
663	state->m_qam_rf_agc_cfg.speed = 3;
664
665	/* QAM IF */
666	state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
667	state->m_qam_if_agc_cfg.output_level = 0;
668	state->m_qam_if_agc_cfg.min_output_level = 0;
669	state->m_qam_if_agc_cfg.max_output_level = 9000;
670	state->m_qam_if_agc_cfg.top = 0x0511;
671	state->m_qam_if_agc_cfg.cut_off_current = 0;
672	state->m_qam_if_agc_cfg.speed = 3;
673	state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;
674	state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;
675
676	state->m_qam_pga_cfg = 140;
677	state->m_qam_pre_saw_cfg.reference = 4;
678	state->m_qam_pre_saw_cfg.use_pre_saw = false;
679
680	state->m_operation_mode = OM_NONE;
681	state->m_drxk_state = DRXK_UNINITIALIZED;
682
683	/* MPEG output configuration */
684	state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG output */
685	state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */
686	state->m_invert_data = false; /* If TRUE; invert DATA signals */
687	state->m_invert_err = false; /* If TRUE; invert ERR signal */
688	state->m_invert_str = false; /* If TRUE; invert STR signals */
689	state->m_invert_val = false; /* If TRUE; invert VAL signals */
690	state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */
691
692	/* If TRUE; static MPEG clockrate will be used;
693	otherwise clockrate will adapt to the bitrate of the TS */
694
695	state->m_dvbt_bitrate = ul_dvbt_bitrate;
696	state->m_dvbc_bitrate = ul_dvbc_bitrate;
697
698	state->m_ts_data_strength = (ul_ts_data_strength & 0x07);
699
700	/* Maximum bitrate in b/s in case static clockrate is selected */
701	state->m_mpeg_ts_static_bitrate = 19392658;
702	state->m_disable_te_ihandling = false;
703
704	if (ul_insert_rs_byte)
705	state->m_insert_rs_byte = true;
706
707	state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
708	if (ul_mpeg_lock_time_out < 10000)
709	state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;
710	state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
711	if (ul_demod_lock_time_out < 10000)
712	state->m_demod_lock_time_out = ul_demod_lock_time_out;
713
714	/* QAM defaults */
715	state->m_constellation = DRX_CONSTELLATION_AUTO;
716	state->m_qam_interleave_mode = DRXK_QAM_I12_J17;
717	state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */
718	state->m_fec_rs_prescale = 1;
719
720	state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;
721	state->m_agcfast_clip_ctrl_delay = 0;
722
723	state->m_gpio_cfg = ul_gpio_cfg;
724
725	state->m_b_power_down = false;
726	state->m_current_power_mode = DRX_POWER_DOWN;
727
728	state->m_rfmirror = (ul_rf_mirror == 0);
729	state->m_if_agc_pol = false;
730	return 0;
731	}
732
733	static int drxx_open(struct drxk_state *state)
734	{
735	int status = 0;
736	u32 jtag = 0;
737	u16 bid = 0;
738	u16 key = 0;
739
740	dprintk(1, "\n");
741	/* stop lock indicator process */
742	status = write16(state, SCU_RAM_GPIO__A,
743	SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
744	if (status < 0)
745	goto error;
746	/* Check device id */
747	status = read16(state, SIO_TOP_COMM_KEY__A, data: &key);
748	if (status < 0)
749	goto error;
750	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
751	if (status < 0)
752	goto error;
753	status = read32(state, SIO_TOP_JTAGID_LO__A, data: &jtag);
754	if (status < 0)
755	goto error;
756	status = read16(state, SIO_PDR_UIO_IN_HI__A, data: &bid);
757	if (status < 0)
758	goto error;
759	status = write16(state, SIO_TOP_COMM_KEY__A, data: key);
760	error:
761	if (status < 0)
762	pr_err("Error %d on %s\n", status, __func__);
763	return status;
764	}
765
766	static int get_device_capabilities(struct drxk_state *state)
767	{
768	u16 sio_pdr_ohw_cfg = 0;
769	u32 sio_top_jtagid_lo = 0;
770	int status;
771	const char *spin = "";
772
773	dprintk(1, "\n");
774
775	/* driver 0.9.0 */
776	/* stop lock indicator process */
777	status = write16(state, SCU_RAM_GPIO__A,
778	SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
779	if (status < 0)
780	goto error;
781	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
782	if (status < 0)
783	goto error;
784	status = read16(state, SIO_PDR_OHW_CFG__A, data: &sio_pdr_ohw_cfg);
785	if (status < 0)
786	goto error;
787	status = write16(state, SIO_TOP_COMM_KEY__A, data: 0x0000);
788	if (status < 0)
789	goto error;
790
791	switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
792	case 0:
793	/* ignore (bypass ?) */
794	break;
795	case 1:
796	/* 27 MHz */
797	state->m_osc_clock_freq = 27000;
798	break;
799	case 2:
800	/* 20.25 MHz */
801	state->m_osc_clock_freq = 20250;
802	break;
803	case 3:
804	/* 4 MHz */
805	state->m_osc_clock_freq = 20250;
806	break;
807	default:
808	pr_err("Clock Frequency is unknown\n");
809	return -EINVAL;
810	}
811	/*
812	Determine device capabilities
813	Based on pinning v14
814	*/
815	status = read32(state, SIO_TOP_JTAGID_LO__A, data: &sio_top_jtagid_lo);
816	if (status < 0)
817	goto error;
818
819	pr_info("status = 0x%08x\n", sio_top_jtagid_lo);
820
821	/* driver 0.9.0 */
822	switch ((sio_top_jtagid_lo >> 29) & 0xF) {
823	case 0:
824	state->m_device_spin = DRXK_SPIN_A1;
825	spin = "A1";
826	break;
827	case 2:
828	state->m_device_spin = DRXK_SPIN_A2;
829	spin = "A2";
830	break;
831	case 3:
832	state->m_device_spin = DRXK_SPIN_A3;
833	spin = "A3";
834	break;
835	default:
836	state->m_device_spin = DRXK_SPIN_UNKNOWN;
837	status = -EINVAL;
838	pr_err("Spin %d unknown\n", (sio_top_jtagid_lo >> 29) & 0xF);
839	goto error2;
840	}
841	switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
842	case 0x13:
843	/* typeId = DRX3913K_TYPE_ID */
844	state->m_has_lna = false;
845	state->m_has_oob = false;
846	state->m_has_atv = false;
847	state->m_has_audio = false;
848	state->m_has_dvbt = true;
849	state->m_has_dvbc = true;
850	state->m_has_sawsw = true;
851	state->m_has_gpio2 = false;
852	state->m_has_gpio1 = false;
853	state->m_has_irqn = false;
854	break;
855	case 0x15:
856	/* typeId = DRX3915K_TYPE_ID */
857	state->m_has_lna = false;
858	state->m_has_oob = false;
859	state->m_has_atv = true;
860	state->m_has_audio = false;
861	state->m_has_dvbt = true;
862	state->m_has_dvbc = false;
863	state->m_has_sawsw = true;
864	state->m_has_gpio2 = true;
865	state->m_has_gpio1 = true;
866	state->m_has_irqn = false;
867	break;
868	case 0x16:
869	/* typeId = DRX3916K_TYPE_ID */
870	state->m_has_lna = false;
871	state->m_has_oob = false;
872	state->m_has_atv = true;
873	state->m_has_audio = false;
874	state->m_has_dvbt = true;
875	state->m_has_dvbc = false;
876	state->m_has_sawsw = true;
877	state->m_has_gpio2 = true;
878	state->m_has_gpio1 = true;
879	state->m_has_irqn = false;
880	break;
881	case 0x18:
882	/* typeId = DRX3918K_TYPE_ID */
883	state->m_has_lna = false;
884	state->m_has_oob = false;
885	state->m_has_atv = true;
886	state->m_has_audio = true;
887	state->m_has_dvbt = true;
888	state->m_has_dvbc = false;
889	state->m_has_sawsw = true;
890	state->m_has_gpio2 = true;
891	state->m_has_gpio1 = true;
892	state->m_has_irqn = false;
893	break;
894	case 0x21:
895	/* typeId = DRX3921K_TYPE_ID */
896	state->m_has_lna = false;
897	state->m_has_oob = false;
898	state->m_has_atv = true;
899	state->m_has_audio = true;
900	state->m_has_dvbt = true;
901	state->m_has_dvbc = true;
902	state->m_has_sawsw = true;
903	state->m_has_gpio2 = true;
904	state->m_has_gpio1 = true;
905	state->m_has_irqn = false;
906	break;
907	case 0x23:
908	/* typeId = DRX3923K_TYPE_ID */
909	state->m_has_lna = false;
910	state->m_has_oob = false;
911	state->m_has_atv = true;
912	state->m_has_audio = true;
913	state->m_has_dvbt = true;
914	state->m_has_dvbc = true;
915	state->m_has_sawsw = true;
916	state->m_has_gpio2 = true;
917	state->m_has_gpio1 = true;
918	state->m_has_irqn = false;
919	break;
920	case 0x25:
921	/* typeId = DRX3925K_TYPE_ID */
922	state->m_has_lna = false;
923	state->m_has_oob = false;
924	state->m_has_atv = true;
925	state->m_has_audio = true;
926	state->m_has_dvbt = true;
927	state->m_has_dvbc = true;
928	state->m_has_sawsw = true;
929	state->m_has_gpio2 = true;
930	state->m_has_gpio1 = true;
931	state->m_has_irqn = false;
932	break;
933	case 0x26:
934	/* typeId = DRX3926K_TYPE_ID */
935	state->m_has_lna = false;
936	state->m_has_oob = false;
937	state->m_has_atv = true;
938	state->m_has_audio = false;
939	state->m_has_dvbt = true;
940	state->m_has_dvbc = true;
941	state->m_has_sawsw = true;
942	state->m_has_gpio2 = true;
943	state->m_has_gpio1 = true;
944	state->m_has_irqn = false;
945	break;
946	default:
947	pr_err("DeviceID 0x%02x not supported\n",
948	((sio_top_jtagid_lo >> 12) & 0xFF));
949	status = -EINVAL;
950	goto error2;
951	}
952
953	pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
954	((sio_top_jtagid_lo >> 12) & 0xFF), spin,
955	state->m_osc_clock_freq / 1000,
956	state->m_osc_clock_freq % 1000);
957
958	error:
959	if (status < 0)
960	pr_err("Error %d on %s\n", status, __func__);
961
962	error2:
963	return status;
964	}
965
966	static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)
967	{
968	int status;
969	bool powerdown_cmd;
970
971	dprintk(1, "\n");
972
973	/* Write command */
974	status = write16(state, SIO_HI_RA_RAM_CMD__A, data: cmd);
975	if (status < 0)
976	goto error;
977	if (cmd == SIO_HI_RA_RAM_CMD_RESET)
978	usleep_range(min: 1000, max: 2000);
979
980	powerdown_cmd =
981	(bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
982	((state->m_hi_cfg_ctrl) &
983	SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
984	SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
985	if (!powerdown_cmd) {
986	/* Wait until command rdy */
987	u32 retry_count = 0;
988	u16 wait_cmd;
989
990	do {
991	usleep_range(min: 1000, max: 2000);
992	retry_count += 1;
993	status = read16(state, SIO_HI_RA_RAM_CMD__A,
994	data: &wait_cmd);
995	} while ((status < 0 || wait_cmd) && (retry_count < DRXK_MAX_RETRIES));
996	if (status < 0)
997	goto error;
998	status = read16(state, SIO_HI_RA_RAM_RES__A, data: p_result);
999	}
1000	error:
1001	if (status < 0)
1002	pr_err("Error %d on %s\n", status, __func__);
1003
1004	return status;
1005	}
1006
1007	static int hi_cfg_command(struct drxk_state *state)
1008	{
1009	int status;
1010
1011	dprintk(1, "\n");
1012
1013	mutex_lock(&state->mutex);
1014
1015	status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
1016	data: state->m_hi_cfg_timeout);
1017	if (status < 0)
1018	goto error;
1019	status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
1020	data: state->m_hi_cfg_ctrl);
1021	if (status < 0)
1022	goto error;
1023	status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
1024	data: state->m_hi_cfg_wake_up_key);
1025	if (status < 0)
1026	goto error;
1027	status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
1028	data: state->m_hi_cfg_bridge_delay);
1029	if (status < 0)
1030	goto error;
1031	status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
1032	data: state->m_hi_cfg_timing_div);
1033	if (status < 0)
1034	goto error;
1035	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
1036	SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1037	if (status < 0)
1038	goto error;
1039	status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);
1040	if (status < 0)
1041	goto error;
1042
1043	state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1044	error:
1045	mutex_unlock(lock: &state->mutex);
1046	if (status < 0)
1047	pr_err("Error %d on %s\n", status, __func__);
1048	return status;
1049	}
1050
1051	static int init_hi(struct drxk_state *state)
1052	{
1053	dprintk(1, "\n");
1054
1055	state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
1056	state->m_hi_cfg_timeout = 0x96FF;
1057	/* port/bridge/power down ctrl */
1058	state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1059
1060	return hi_cfg_command(state);
1061	}
1062
1063	static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
1064	{
1065	int status;
1066	u16 sio_pdr_mclk_cfg = 0;
1067	u16 sio_pdr_mdx_cfg = 0;
1068	u16 err_cfg = 0;
1069
1070	dprintk(1, ": mpeg %s, %s mode\n",
1071	mpeg_enable ? "enable" : "disable",
1072	state->m_enable_parallel ? "parallel" : "serial");
1073
1074	/* stop lock indicator process */
1075	status = write16(state, SCU_RAM_GPIO__A,
1076	SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1077	if (status < 0)
1078	goto error;
1079
1080	/* MPEG TS pad configuration */
1081	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1082	if (status < 0)
1083	goto error;
1084
1085	if (!mpeg_enable) {
1086	/* Set MPEG TS pads to inputmode */
1087	status = write16(state, SIO_PDR_MSTRT_CFG__A, data: 0x0000);
1088	if (status < 0)
1089	goto error;
1090	status = write16(state, SIO_PDR_MERR_CFG__A, data: 0x0000);
1091	if (status < 0)
1092	goto error;
1093	status = write16(state, SIO_PDR_MCLK_CFG__A, data: 0x0000);
1094	if (status < 0)
1095	goto error;
1096	status = write16(state, SIO_PDR_MVAL_CFG__A, data: 0x0000);
1097	if (status < 0)
1098	goto error;
1099	status = write16(state, SIO_PDR_MD0_CFG__A, data: 0x0000);
1100	if (status < 0)
1101	goto error;
1102	status = write16(state, SIO_PDR_MD1_CFG__A, data: 0x0000);
1103	if (status < 0)
1104	goto error;
1105	status = write16(state, SIO_PDR_MD2_CFG__A, data: 0x0000);
1106	if (status < 0)
1107	goto error;
1108	status = write16(state, SIO_PDR_MD3_CFG__A, data: 0x0000);
1109	if (status < 0)
1110	goto error;
1111	status = write16(state, SIO_PDR_MD4_CFG__A, data: 0x0000);
1112	if (status < 0)
1113	goto error;
1114	status = write16(state, SIO_PDR_MD5_CFG__A, data: 0x0000);
1115	if (status < 0)
1116	goto error;
1117	status = write16(state, SIO_PDR_MD6_CFG__A, data: 0x0000);
1118	if (status < 0)
1119	goto error;
1120	status = write16(state, SIO_PDR_MD7_CFG__A, data: 0x0000);
1121	if (status < 0)
1122	goto error;
1123	} else {
1124	/* Enable MPEG output */
1125	sio_pdr_mdx_cfg =
1126	((state->m_ts_data_strength <<
1127	SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1128	sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<
1129	SIO_PDR_MCLK_CFG_DRIVE__B) |
1130	0x0003);
1131
1132	status = write16(state, SIO_PDR_MSTRT_CFG__A, data: sio_pdr_mdx_cfg);
1133	if (status < 0)
1134	goto error;
1135
1136	if (state->enable_merr_cfg)
1137	err_cfg = sio_pdr_mdx_cfg;
1138
1139	status = write16(state, SIO_PDR_MERR_CFG__A, data: err_cfg);
1140	if (status < 0)
1141	goto error;
1142	status = write16(state, SIO_PDR_MVAL_CFG__A, data: err_cfg);
1143	if (status < 0)
1144	goto error;
1145
1146	if (state->m_enable_parallel) {
1147	/* parallel -> enable MD1 to MD7 */
1148	status = write16(state, SIO_PDR_MD1_CFG__A,
1149	data: sio_pdr_mdx_cfg);
1150	if (status < 0)
1151	goto error;
1152	status = write16(state, SIO_PDR_MD2_CFG__A,
1153	data: sio_pdr_mdx_cfg);
1154	if (status < 0)
1155	goto error;
1156	status = write16(state, SIO_PDR_MD3_CFG__A,
1157	data: sio_pdr_mdx_cfg);
1158	if (status < 0)
1159	goto error;
1160	status = write16(state, SIO_PDR_MD4_CFG__A,
1161	data: sio_pdr_mdx_cfg);
1162	if (status < 0)
1163	goto error;
1164	status = write16(state, SIO_PDR_MD5_CFG__A,
1165	data: sio_pdr_mdx_cfg);
1166	if (status < 0)
1167	goto error;
1168	status = write16(state, SIO_PDR_MD6_CFG__A,
1169	data: sio_pdr_mdx_cfg);
1170	if (status < 0)
1171	goto error;
1172	status = write16(state, SIO_PDR_MD7_CFG__A,
1173	data: sio_pdr_mdx_cfg);
1174	if (status < 0)
1175	goto error;
1176	} else {
1177	sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<
1178	SIO_PDR_MD0_CFG_DRIVE__B)
1179	| 0x0003);
1180	/* serial -> disable MD1 to MD7 */
1181	status = write16(state, SIO_PDR_MD1_CFG__A, data: 0x0000);
1182	if (status < 0)
1183	goto error;
1184	status = write16(state, SIO_PDR_MD2_CFG__A, data: 0x0000);
1185	if (status < 0)
1186	goto error;
1187	status = write16(state, SIO_PDR_MD3_CFG__A, data: 0x0000);
1188	if (status < 0)
1189	goto error;
1190	status = write16(state, SIO_PDR_MD4_CFG__A, data: 0x0000);
1191	if (status < 0)
1192	goto error;
1193	status = write16(state, SIO_PDR_MD5_CFG__A, data: 0x0000);
1194	if (status < 0)
1195	goto error;
1196	status = write16(state, SIO_PDR_MD6_CFG__A, data: 0x0000);
1197	if (status < 0)
1198	goto error;
1199	status = write16(state, SIO_PDR_MD7_CFG__A, data: 0x0000);
1200	if (status < 0)
1201	goto error;
1202	}
1203	status = write16(state, SIO_PDR_MCLK_CFG__A, data: sio_pdr_mclk_cfg);
1204	if (status < 0)
1205	goto error;
1206	status = write16(state, SIO_PDR_MD0_CFG__A, data: sio_pdr_mdx_cfg);
1207	if (status < 0)
1208	goto error;
1209	}
1210	/* Enable MB output over MPEG pads and ctl input */
1211	status = write16(state, SIO_PDR_MON_CFG__A, data: 0x0000);
1212	if (status < 0)
1213	goto error;
1214	/* Write nomagic word to enable pdr reg write */
1215	status = write16(state, SIO_TOP_COMM_KEY__A, data: 0x0000);
1216	error:
1217	if (status < 0)
1218	pr_err("Error %d on %s\n", status, __func__);
1219	return status;
1220	}
1221
1222	static int mpegts_disable(struct drxk_state *state)
1223	{
1224	dprintk(1, "\n");
1225
1226	return mpegts_configure_pins(state, mpeg_enable: false);
1227	}
1228
1229	static int bl_chain_cmd(struct drxk_state *state,
1230	u16 rom_offset, u16 nr_of_elements, u32 time_out)
1231	{
1232	u16 bl_status = 0;
1233	int status;
1234	unsigned long end;
1235
1236	dprintk(1, "\n");
1237	mutex_lock(&state->mutex);
1238	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1239	if (status < 0)
1240	goto error;
1241	status = write16(state, SIO_BL_CHAIN_ADDR__A, data: rom_offset);
1242	if (status < 0)
1243	goto error;
1244	status = write16(state, SIO_BL_CHAIN_LEN__A, data: nr_of_elements);
1245	if (status < 0)
1246	goto error;
1247	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1248	if (status < 0)
1249	goto error;
1250
1251	end = jiffies + msecs_to_jiffies(m: time_out);
1252	do {
1253	usleep_range(min: 1000, max: 2000);
1254	status = read16(state, SIO_BL_STATUS__A, data: &bl_status);
1255	if (status < 0)
1256	goto error;
1257	} while ((bl_status == 0x1) &&
1258	((time_is_after_jiffies(end))));
1259
1260	if (bl_status == 0x1) {
1261	pr_err("SIO not ready\n");
1262	status = -EINVAL;
1263	goto error2;
1264	}
1265	error:
1266	if (status < 0)
1267	pr_err("Error %d on %s\n", status, __func__);
1268	error2:
1269	mutex_unlock(lock: &state->mutex);
1270	return status;
1271	}
1272
1273
1274	static int download_microcode(struct drxk_state *state,
1275	const u8 p_mc_image[], u32 length)
1276	{
1277	const u8 *p_src = p_mc_image;
1278	u32 address;
1279	u16 n_blocks;
1280	u16 block_size;
1281	u32 offset = 0;
1282	u32 i;
1283	int status = 0;
1284
1285	dprintk(1, "\n");
1286
1287	/* down the drain (we don't care about MAGIC_WORD) */
1288	#if 0
1289	/* For future reference */
1290	drain = (p_src[0] << 8) | p_src[1];
1291	#endif
1292	p_src += sizeof(u16);
1293	offset += sizeof(u16);
1294	n_blocks = (p_src[0] << 8) | p_src[1];
1295	p_src += sizeof(u16);
1296	offset += sizeof(u16);
1297
1298	for (i = 0; i < n_blocks; i += 1) {
1299	address = (p_src[0] << 24) | (p_src[1] << 16) |
1300	(p_src[2] << 8) | p_src[3];
1301	p_src += sizeof(u32);
1302	offset += sizeof(u32);
1303
1304	block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16);
1305	p_src += sizeof(u16);
1306	offset += sizeof(u16);
1307
1308	#if 0
1309	/* For future reference */
1310	flags = (p_src[0] << 8) | p_src[1];
1311	#endif
1312	p_src += sizeof(u16);
1313	offset += sizeof(u16);
1314
1315	#if 0
1316	/* For future reference */
1317	block_crc = (p_src[0] << 8) | p_src[1];
1318	#endif
1319	p_src += sizeof(u16);
1320	offset += sizeof(u16);
1321
1322	if (offset + block_size > length) {
1323	pr_err("Firmware is corrupted.\n");
1324	return -EINVAL;
1325	}
1326
1327	status = write_block(state, address, block_size, p_block: p_src);
1328	if (status < 0) {
1329	pr_err("Error %d while loading firmware\n", status);
1330	break;
1331	}
1332	p_src += block_size;
1333	offset += block_size;
1334	}
1335	return status;
1336	}
1337
1338	static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
1339	{
1340	int status;
1341	u16 data = 0;
1342	u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1343	u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1344	unsigned long end;
1345
1346	dprintk(1, "\n");
1347
1348	if (!enable) {
1349	desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1350	desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1351	}
1352
1353	status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, data: &data);
1354	if (status >= 0 && data == desired_status) {
1355	/* tokenring already has correct status */
1356	return status;
1357	}
1358	/* Disable/enable dvbt tokenring bridge */
1359	status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, data: desired_ctrl);
1360
1361	end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1362	do {
1363	status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, data: &data);
1364	if ((status >= 0 && data == desired_status)
1365	|| time_is_after_jiffies(end))
1366	break;
1367	usleep_range(min: 1000, max: 2000);
1368	} while (1);
1369	if (data != desired_status) {
1370	pr_err("SIO not ready\n");
1371	return -EINVAL;
1372	}
1373	return status;
1374	}
1375
1376	static int mpegts_stop(struct drxk_state *state)
1377	{
1378	int status = 0;
1379	u16 fec_oc_snc_mode = 0;
1380	u16 fec_oc_ipr_mode = 0;
1381
1382	dprintk(1, "\n");
1383
1384	/* Graceful shutdown (byte boundaries) */
1385	status = read16(state, FEC_OC_SNC_MODE__A, data: &fec_oc_snc_mode);
1386	if (status < 0)
1387	goto error;
1388	fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1389	status = write16(state, FEC_OC_SNC_MODE__A, data: fec_oc_snc_mode);
1390	if (status < 0)
1391	goto error;
1392
1393	/* Suppress MCLK during absence of data */
1394	status = read16(state, FEC_OC_IPR_MODE__A, data: &fec_oc_ipr_mode);
1395	if (status < 0)
1396	goto error;
1397	fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1398	status = write16(state, FEC_OC_IPR_MODE__A, data: fec_oc_ipr_mode);
1399
1400	error:
1401	if (status < 0)
1402	pr_err("Error %d on %s\n", status, __func__);
1403
1404	return status;
1405	}
1406
1407	static int scu_command(struct drxk_state *state,
1408	u16 cmd, u8 parameter_len,
1409	u16 *parameter, u8 result_len, u16 *result)
1410	{
1411	#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1412	#error DRXK register mapping no longer compatible with this routine!
1413	#endif
1414	u16 cur_cmd = 0;
1415	int status = -EINVAL;
1416	unsigned long end;
1417	u8 buffer[34];
1418	int cnt = 0, ii;
1419	const char *p;
1420	char errname[30];
1421
1422	dprintk(1, "\n");
1423
1424	if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) ||
1425	((result_len > 0) && (result == NULL))) {
1426	pr_err("Error %d on %s\n", status, __func__);
1427	return status;
1428	}
1429
1430	mutex_lock(&state->mutex);
1431
1432	/* assume that the command register is ready
1433	since it is checked afterwards */
1434	if (parameter) {
1435	for (ii = parameter_len - 1; ii >= 0; ii -= 1) {
1436	buffer[cnt++] = (parameter[ii] & 0xFF);
1437	buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1438	}
1439	}
1440	buffer[cnt++] = (cmd & 0xFF);
1441	buffer[cnt++] = ((cmd >> 8) & 0xFF);
1442
1443	write_block(state, SCU_RAM_PARAM_0__A -
1444	(parameter_len - 1), block_size: cnt, p_block: buffer);
1445	/* Wait until SCU has processed command */
1446	end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1447	do {
1448	usleep_range(min: 1000, max: 2000);
1449	status = read16(state, SCU_RAM_COMMAND__A, data: &cur_cmd);
1450	if (status < 0)
1451	goto error;
1452	} while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1453	if (cur_cmd != DRX_SCU_READY) {
1454	pr_err("SCU not ready\n");
1455	status = -EIO;
1456	goto error2;
1457	}
1458	/* read results */
1459	if ((result_len > 0) && (result != NULL)) {
1460	s16 err;
1461	int ii;
1462
1463	for (ii = result_len - 1; ii >= 0; ii -= 1) {
1464	status = read16(state, SCU_RAM_PARAM_0__A - ii,
1465	data: &result[ii]);
1466	if (status < 0)
1467	goto error;
1468	}
1469
1470	/* Check if an error was reported by SCU */
1471	err = (s16)result[0];
1472	if (err >= 0)
1473	goto error;
1474
1475	/* check for the known error codes */
1476	switch (err) {
1477	case SCU_RESULT_UNKCMD:
1478	p = "SCU_RESULT_UNKCMD";
1479	break;
1480	case SCU_RESULT_UNKSTD:
1481	p = "SCU_RESULT_UNKSTD";
1482	break;
1483	case SCU_RESULT_SIZE:
1484	p = "SCU_RESULT_SIZE";
1485	break;
1486	case SCU_RESULT_INVPAR:
1487	p = "SCU_RESULT_INVPAR";
1488	break;
1489	default: /* Other negative values are errors */
1490	sprintf(buf: errname, fmt: "ERROR: %d\n", err);
1491	p = errname;
1492	}
1493	pr_err("%s while sending cmd 0x%04x with params:", p, cmd);
1494	print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1495	status = -EINVAL;
1496	goto error2;
1497	}
1498
1499	error:
1500	if (status < 0)
1501	pr_err("Error %d on %s\n", status, __func__);
1502	error2:
1503	mutex_unlock(lock: &state->mutex);
1504	return status;
1505	}
1506
1507	static int set_iqm_af(struct drxk_state *state, bool active)
1508	{
1509	u16 data = 0;
1510	int status;
1511
1512	dprintk(1, "\n");
1513
1514	/* Configure IQM */
1515	status = read16(state, IQM_AF_STDBY__A, data: &data);
1516	if (status < 0)
1517	goto error;
1518
1519	if (!active) {
1520	data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1521	| IQM_AF_STDBY_STDBY_AMP_STANDBY
1522	| IQM_AF_STDBY_STDBY_PD_STANDBY
1523	| IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1524	| IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1525	} else {
1526	data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1527	& (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1528	& (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1529	& (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1530	& (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1531	);
1532	}
1533	status = write16(state, IQM_AF_STDBY__A, data);
1534
1535	error:
1536	if (status < 0)
1537	pr_err("Error %d on %s\n", status, __func__);
1538	return status;
1539	}
1540
1541	static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)
1542	{
1543	int status = 0;
1544	u16 sio_cc_pwd_mode = 0;
1545
1546	dprintk(1, "\n");
1547
1548	/* Check arguments */
1549	if (mode == NULL)
1550	return -EINVAL;
1551
1552	switch (*mode) {
1553	case DRX_POWER_UP:
1554	sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
1555	break;
1556	case DRXK_POWER_DOWN_OFDM:
1557	sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1558	break;
1559	case DRXK_POWER_DOWN_CORE:
1560	sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1561	break;
1562	case DRXK_POWER_DOWN_PLL:
1563	sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
1564	break;
1565	case DRX_POWER_DOWN:
1566	sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
1567	break;
1568	default:
1569	/* Unknown sleep mode */
1570	return -EINVAL;
1571	}
1572
1573	/* If already in requested power mode, do nothing */
1574	if (state->m_current_power_mode == *mode)
1575	return 0;
1576
1577	/* For next steps make sure to start from DRX_POWER_UP mode */
1578	if (state->m_current_power_mode != DRX_POWER_UP) {
1579	status = power_up_device(state);
1580	if (status < 0)
1581	goto error;
1582	status = dvbt_enable_ofdm_token_ring(state, enable: true);
1583	if (status < 0)
1584	goto error;
1585	}
1586
1587	if (*mode == DRX_POWER_UP) {
1588	/* Restore analog & pin configuration */
1589	} else {
1590	/* Power down to requested mode */
1591	/* Backup some register settings */
1592	/* Set pins with possible pull-ups connected
1593	to them in input mode */
1594	/* Analog power down */
1595	/* ADC power down */
1596	/* Power down device */
1597	/* stop all comm_exec */
1598	/* Stop and power down previous standard */
1599	switch (state->m_operation_mode) {
1600	case OM_DVBT:
1601	status = mpegts_stop(state);
1602	if (status < 0)
1603	goto error;
1604	status = power_down_dvbt(state, set_power_mode: false);
1605	if (status < 0)
1606	goto error;
1607	break;
1608	case OM_QAM_ITU_A:
1609	case OM_QAM_ITU_C:
1610	status = mpegts_stop(state);
1611	if (status < 0)
1612	goto error;
1613	status = power_down_qam(state);
1614	if (status < 0)
1615	goto error;
1616	break;
1617	default:
1618	break;
1619	}
1620	status = dvbt_enable_ofdm_token_ring(state, enable: false);
1621	if (status < 0)
1622	goto error;
1623	status = write16(state, SIO_CC_PWD_MODE__A, data: sio_cc_pwd_mode);
1624	if (status < 0)
1625	goto error;
1626	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1627	if (status < 0)
1628	goto error;
1629
1630	if (*mode != DRXK_POWER_DOWN_OFDM) {
1631	state->m_hi_cfg_ctrl |=
1632	SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1633	status = hi_cfg_command(state);
1634	if (status < 0)
1635	goto error;
1636	}
1637	}
1638	state->m_current_power_mode = *mode;
1639
1640	error:
1641	if (status < 0)
1642	pr_err("Error %d on %s\n", status, __func__);
1643
1644	return status;
1645	}
1646
1647	static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)
1648	{
1649	enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
1650	u16 cmd_result = 0;
1651	u16 data = 0;
1652	int status;
1653
1654	dprintk(1, "\n");
1655
1656	status = read16(state, SCU_COMM_EXEC__A, data: &data);
1657	if (status < 0)
1658	goto error;
1659	if (data == SCU_COMM_EXEC_ACTIVE) {
1660	/* Send OFDM stop command */
1661	status = scu_command(state,
1662	SCU_RAM_COMMAND_STANDARD_OFDM
1663	| SCU_RAM_COMMAND_CMD_DEMOD_STOP,
1664	parameter_len: 0, NULL, result_len: 1, result: &cmd_result);
1665	if (status < 0)
1666	goto error;
1667	/* Send OFDM reset command */
1668	status = scu_command(state,
1669	SCU_RAM_COMMAND_STANDARD_OFDM
1670	| SCU_RAM_COMMAND_CMD_DEMOD_RESET,
1671	parameter_len: 0, NULL, result_len: 1, result: &cmd_result);
1672	if (status < 0)
1673	goto error;
1674	}
1675
1676	/* Reset datapath for OFDM, processors first */
1677	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1678	if (status < 0)
1679	goto error;
1680	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1681	if (status < 0)
1682	goto error;
1683	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1684	if (status < 0)
1685	goto error;
1686
1687	/* powerdown AFE */
1688	status = set_iqm_af(state, active: false);
1689	if (status < 0)
1690	goto error;
1691
1692	/* powerdown to OFDM mode */
1693	if (set_power_mode) {
1694	status = ctrl_power_mode(state, mode: &power_mode);
1695	if (status < 0)
1696	goto error;
1697	}
1698	error:
1699	if (status < 0)
1700	pr_err("Error %d on %s\n", status, __func__);
1701	return status;
1702	}
1703
1704	static int setoperation_mode(struct drxk_state *state,
1705	enum operation_mode o_mode)
1706	{
1707	int status = 0;
1708
1709	dprintk(1, "\n");
1710	/*
1711	Stop and power down previous standard
1712	TODO investigate total power down instead of partial
1713	power down depending on "previous" standard.
1714	*/
1715
1716	/* disable HW lock indicator */
1717	status = write16(state, SCU_RAM_GPIO__A,
1718	SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1719	if (status < 0)
1720	goto error;
1721
1722	/* Device is already at the required mode */
1723	if (state->m_operation_mode == o_mode)
1724	return 0;
1725
1726	switch (state->m_operation_mode) {
1727	/* OM_NONE was added for start up */
1728	case OM_NONE:
1729	break;
1730	case OM_DVBT:
1731	status = mpegts_stop(state);
1732	if (status < 0)
1733	goto error;
1734	status = power_down_dvbt(state, set_power_mode: true);
1735	if (status < 0)
1736	goto error;
1737	state->m_operation_mode = OM_NONE;
1738	break;
1739	case OM_QAM_ITU_A:
1740	case OM_QAM_ITU_C:
1741	status = mpegts_stop(state);
1742	if (status < 0)
1743	goto error;
1744	status = power_down_qam(state);
1745	if (status < 0)
1746	goto error;
1747	state->m_operation_mode = OM_NONE;
1748	break;
1749	case OM_QAM_ITU_B:
1750	default:
1751	status = -EINVAL;
1752	goto error;
1753	}
1754
1755	/*
1756	Power up new standard
1757	*/
1758	switch (o_mode) {
1759	case OM_DVBT:
1760	dprintk(1, ": DVB-T\n");
1761	state->m_operation_mode = o_mode;
1762	status = set_dvbt_standard(state, o_mode);
1763	if (status < 0)
1764	goto error;
1765	break;
1766	case OM_QAM_ITU_A:
1767	case OM_QAM_ITU_C:
1768	dprintk(1, ": DVB-C Annex %c\n",
1769	(state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');
1770	state->m_operation_mode = o_mode;
1771	status = set_qam_standard(state, o_mode);
1772	if (status < 0)
1773	goto error;
1774	break;
1775	case OM_QAM_ITU_B:
1776	default:
1777	status = -EINVAL;
1778	}
1779	error:
1780	if (status < 0)
1781	pr_err("Error %d on %s\n", status, __func__);
1782	return status;
1783	}
1784
1785	static int start(struct drxk_state *state, s32 offset_freq,
1786	s32 intermediate_frequency)
1787	{
1788	int status = -EINVAL;
1789
1790	u16 i_freqk_hz;
1791	s32 offsetk_hz = offset_freq / 1000;
1792
1793	dprintk(1, "\n");
1794	if (state->m_drxk_state != DRXK_STOPPED &&
1795	state->m_drxk_state != DRXK_DTV_STARTED)
1796	goto error;
1797
1798	state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);
1799
1800	if (intermediate_frequency < 0) {
1801	state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;
1802	intermediate_frequency = -intermediate_frequency;
1803	}
1804
1805	switch (state->m_operation_mode) {
1806	case OM_QAM_ITU_A:
1807	case OM_QAM_ITU_C:
1808	i_freqk_hz = (intermediate_frequency / 1000);
1809	status = set_qam(state, intermediate_freqk_hz: i_freqk_hz, tuner_freq_offset: offsetk_hz);
1810	if (status < 0)
1811	goto error;
1812	state->m_drxk_state = DRXK_DTV_STARTED;
1813	break;
1814	case OM_DVBT:
1815	i_freqk_hz = (intermediate_frequency / 1000);
1816	status = mpegts_stop(state);
1817	if (status < 0)
1818	goto error;
1819	status = set_dvbt(state, intermediate_freqk_hz: i_freqk_hz, tuner_freq_offset: offsetk_hz);
1820	if (status < 0)
1821	goto error;
1822	status = dvbt_start(state);
1823	if (status < 0)
1824	goto error;
1825	state->m_drxk_state = DRXK_DTV_STARTED;
1826	break;
1827	default:
1828	break;
1829	}
1830	error:
1831	if (status < 0)
1832	pr_err("Error %d on %s\n", status, __func__);
1833	return status;
1834	}
1835
1836	static int shut_down(struct drxk_state *state)
1837	{
1838	dprintk(1, "\n");
1839
1840	mpegts_stop(state);
1841	return 0;
1842	}
1843
1844	static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)
1845	{
1846	int status = -EINVAL;
1847
1848	dprintk(1, "\n");
1849
1850	if (p_lock_status == NULL)
1851	goto error;
1852
1853	*p_lock_status = NOT_LOCKED;
1854
1855	/* define the SCU command code */
1856	switch (state->m_operation_mode) {
1857	case OM_QAM_ITU_A:
1858	case OM_QAM_ITU_B:
1859	case OM_QAM_ITU_C:
1860	status = get_qam_lock_status(state, p_lock_status);
1861	break;
1862	case OM_DVBT:
1863	status = get_dvbt_lock_status(state, p_lock_status);
1864	break;
1865	default:
1866	pr_debug("Unsupported operation mode %d in %s\n",
1867	state->m_operation_mode, __func__);
1868	return 0;
1869	}
1870	error:
1871	if (status < 0)
1872	pr_err("Error %d on %s\n", status, __func__);
1873	return status;
1874	}
1875
1876	static int mpegts_start(struct drxk_state *state)
1877	{
1878	int status;
1879
1880	u16 fec_oc_snc_mode = 0;
1881
1882	/* Allow OC to sync again */
1883	status = read16(state, FEC_OC_SNC_MODE__A, data: &fec_oc_snc_mode);
1884	if (status < 0)
1885	goto error;
1886	fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1887	status = write16(state, FEC_OC_SNC_MODE__A, data: fec_oc_snc_mode);
1888	if (status < 0)
1889	goto error;
1890	status = write16(state, FEC_OC_SNC_UNLOCK__A, data: 1);
1891	error:
1892	if (status < 0)
1893	pr_err("Error %d on %s\n", status, __func__);
1894	return status;
1895	}
1896
1897	static int mpegts_dto_init(struct drxk_state *state)
1898	{
1899	int status;
1900
1901	dprintk(1, "\n");
1902
1903	/* Rate integration settings */
1904	status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, data: 0x0000);
1905	if (status < 0)
1906	goto error;
1907	status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, data: 0x000C);
1908	if (status < 0)
1909	goto error;
1910	status = write16(state, FEC_OC_RCN_GAIN__A, data: 0x000A);
1911	if (status < 0)
1912	goto error;
1913	status = write16(state, FEC_OC_AVR_PARM_A__A, data: 0x0008);
1914	if (status < 0)
1915	goto error;
1916	status = write16(state, FEC_OC_AVR_PARM_B__A, data: 0x0006);
1917	if (status < 0)
1918	goto error;
1919	status = write16(state, FEC_OC_TMD_HI_MARGIN__A, data: 0x0680);
1920	if (status < 0)
1921	goto error;
1922	status = write16(state, FEC_OC_TMD_LO_MARGIN__A, data: 0x0080);
1923	if (status < 0)
1924	goto error;
1925	status = write16(state, FEC_OC_TMD_COUNT__A, data: 0x03F4);
1926	if (status < 0)
1927	goto error;
1928
1929	/* Additional configuration */
1930	status = write16(state, FEC_OC_OCR_INVERT__A, data: 0);
1931	if (status < 0)
1932	goto error;
1933	status = write16(state, FEC_OC_SNC_LWM__A, data: 2);
1934	if (status < 0)
1935	goto error;
1936	status = write16(state, FEC_OC_SNC_HWM__A, data: 12);
1937	error:
1938	if (status < 0)
1939	pr_err("Error %d on %s\n", status, __func__);
1940
1941	return status;
1942	}
1943
1944	static int mpegts_dto_setup(struct drxk_state *state,
1945	enum operation_mode o_mode)
1946	{
1947	int status;
1948
1949	u16 fec_oc_reg_mode = 0; /* FEC_OC_MODE register value */
1950	u16 fec_oc_reg_ipr_mode = 0; /* FEC_OC_IPR_MODE register value */
1951	u16 fec_oc_dto_mode = 0; /* FEC_OC_IPR_INVERT register value */
1952	u16 fec_oc_fct_mode = 0; /* FEC_OC_IPR_INVERT register value */
1953	u16 fec_oc_dto_period = 2; /* FEC_OC_IPR_INVERT register value */
1954	u16 fec_oc_dto_burst_len = 188; /* FEC_OC_IPR_INVERT register value */
1955	u32 fec_oc_rcn_ctl_rate = 0; /* FEC_OC_IPR_INVERT register value */
1956	u16 fec_oc_tmd_mode = 0;
1957	u16 fec_oc_tmd_int_upd_rate = 0;
1958	u32 max_bit_rate = 0;
1959	bool static_clk = false;
1960
1961	dprintk(1, "\n");
1962
1963	/* Check insertion of the Reed-Solomon parity bytes */
1964	status = read16(state, FEC_OC_MODE__A, data: &fec_oc_reg_mode);
1965	if (status < 0)
1966	goto error;
1967	status = read16(state, FEC_OC_IPR_MODE__A, data: &fec_oc_reg_ipr_mode);
1968	if (status < 0)
1969	goto error;
1970	fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
1971	fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
1972	if (state->m_insert_rs_byte) {
1973	/* enable parity symbol forward */
1974	fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
1975	/* MVAL disable during parity bytes */
1976	fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
1977	/* TS burst length to 204 */
1978	fec_oc_dto_burst_len = 204;
1979	}
1980
1981	/* Check serial or parallel output */
1982	fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
1983	if (!state->m_enable_parallel) {
1984	/* MPEG data output is serial -> set ipr_mode[0] */
1985	fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
1986	}
1987
1988	switch (o_mode) {
1989	case OM_DVBT:
1990	max_bit_rate = state->m_dvbt_bitrate;
1991	fec_oc_tmd_mode = 3;
1992	fec_oc_rcn_ctl_rate = 0xC00000;
1993	static_clk = state->m_dvbt_static_clk;
1994	break;
1995	case OM_QAM_ITU_A:
1996	case OM_QAM_ITU_C:
1997	fec_oc_tmd_mode = 0x0004;
1998	fec_oc_rcn_ctl_rate = 0xD2B4EE; /* good for >63 Mb/s */
1999	max_bit_rate = state->m_dvbc_bitrate;
2000	static_clk = state->m_dvbc_static_clk;
2001	break;
2002	default:
2003	status = -EINVAL;
2004	} /* switch (standard) */
2005	if (status < 0)
2006	goto error;
2007
2008	/* Configure DTO's */
2009	if (static_clk) {
2010	u32 bit_rate = 0;
2011
2012	/* Rational DTO for MCLK source (static MCLK rate),
2013	Dynamic DTO for optimal grouping
2014	(avoid intra-packet gaps),
2015	DTO offset enable to sync TS burst with MSTRT */
2016	fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2017	FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2018	fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2019	FEC_OC_FCT_MODE_VIRT_ENA__M);
2020
2021	/* Check user defined bitrate */
2022	bit_rate = max_bit_rate;
2023	if (bit_rate > 75900000UL) { /* max is 75.9 Mb/s */
2024	bit_rate = 75900000UL;
2025	}
2026	/* Rational DTO period:
2027	dto_period = (Fsys / bitrate) - 2
2028
2029	result should be floored,
2030	to make sure >= requested bitrate
2031	*/
2032	fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)
2033	* 1000) / bit_rate);
2034	if (fec_oc_dto_period <= 2)
2035	fec_oc_dto_period = 0;
2036	else
2037	fec_oc_dto_period -= 2;
2038	fec_oc_tmd_int_upd_rate = 8;
2039	} else {
2040	/* (commonAttr->static_clk == false) => dynamic mode */
2041	fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M;
2042	fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE;
2043	fec_oc_tmd_int_upd_rate = 5;
2044	}
2045
2046	/* Write appropriate registers with requested configuration */
2047	status = write16(state, FEC_OC_DTO_BURST_LEN__A, data: fec_oc_dto_burst_len);
2048	if (status < 0)
2049	goto error;
2050	status = write16(state, FEC_OC_DTO_PERIOD__A, data: fec_oc_dto_period);
2051	if (status < 0)
2052	goto error;
2053	status = write16(state, FEC_OC_DTO_MODE__A, data: fec_oc_dto_mode);
2054	if (status < 0)
2055	goto error;
2056	status = write16(state, FEC_OC_FCT_MODE__A, data: fec_oc_fct_mode);
2057	if (status < 0)
2058	goto error;
2059	status = write16(state, FEC_OC_MODE__A, data: fec_oc_reg_mode);
2060	if (status < 0)
2061	goto error;
2062	status = write16(state, FEC_OC_IPR_MODE__A, data: fec_oc_reg_ipr_mode);
2063	if (status < 0)
2064	goto error;
2065
2066	/* Rate integration settings */
2067	status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, data: fec_oc_rcn_ctl_rate);
2068	if (status < 0)
2069	goto error;
2070	status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
2071	data: fec_oc_tmd_int_upd_rate);
2072	if (status < 0)
2073	goto error;
2074	status = write16(state, FEC_OC_TMD_MODE__A, data: fec_oc_tmd_mode);
2075	error:
2076	if (status < 0)
2077	pr_err("Error %d on %s\n", status, __func__);
2078	return status;
2079	}
2080
2081	static int mpegts_configure_polarity(struct drxk_state *state)
2082	{
2083	u16 fec_oc_reg_ipr_invert = 0;
2084
2085	/* Data mask for the output data byte */
2086	u16 invert_data_mask =
2087	FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2088	FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2089	FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2090	FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2091
2092	dprintk(1, "\n");
2093
2094	/* Control selective inversion of output bits */
2095	fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2096	if (state->m_invert_data)
2097	fec_oc_reg_ipr_invert |= invert_data_mask;
2098	fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2099	if (state->m_invert_err)
2100	fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2101	fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2102	if (state->m_invert_str)
2103	fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
2104	fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2105	if (state->m_invert_val)
2106	fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
2107	fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2108	if (state->m_invert_clk)
2109	fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
2110
2111	return write16(state, FEC_OC_IPR_INVERT__A, data: fec_oc_reg_ipr_invert);
2112	}
2113
2114	#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2115
2116	static int set_agc_rf(struct drxk_state *state,
2117	struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2118	{
2119	int status = -EINVAL;
2120	u16 data = 0;
2121	struct s_cfg_agc *p_if_agc_settings;
2122
2123	dprintk(1, "\n");
2124
2125	if (p_agc_cfg == NULL)
2126	goto error;
2127
2128	switch (p_agc_cfg->ctrl_mode) {
2129	case DRXK_AGC_CTRL_AUTO:
2130	/* Enable RF AGC DAC */
2131	status = read16(state, IQM_AF_STDBY__A, data: &data);
2132	if (status < 0)
2133	goto error;
2134	data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2135	status = write16(state, IQM_AF_STDBY__A, data);
2136	if (status < 0)
2137	goto error;
2138	status = read16(state, SCU_RAM_AGC_CONFIG__A, data: &data);
2139	if (status < 0)
2140	goto error;
2141
2142	/* Enable SCU RF AGC loop */
2143	data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2144
2145	/* Polarity */
2146	if (state->m_rf_agc_pol)
2147	data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2148	else
2149	data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2150	status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2151	if (status < 0)
2152	goto error;
2153
2154	/* Set speed (using complementary reduction value) */
2155	status = read16(state, SCU_RAM_AGC_KI_RED__A, data: &data);
2156	if (status < 0)
2157	goto error;
2158
2159	data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2160	data |= (~(p_agc_cfg->speed <<
2161	SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2162	& SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2163
2164	status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2165	if (status < 0)
2166	goto error;
2167
2168	if (is_dvbt(state))
2169	p_if_agc_settings = &state->m_dvbt_if_agc_cfg;
2170	else if (is_qam(state))
2171	p_if_agc_settings = &state->m_qam_if_agc_cfg;
2172	else
2173	p_if_agc_settings = &state->m_atv_if_agc_cfg;
2174	if (p_if_agc_settings == NULL) {
2175	status = -EINVAL;
2176	goto error;
2177	}
2178
2179	/* Set TOP, only if IF-AGC is in AUTO mode */
2180	if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) {
2181	status = write16(state,
2182	SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2183	data: p_agc_cfg->top);
2184	if (status < 0)
2185	goto error;
2186	}
2187
2188	/* Cut-Off current */
2189	status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
2190	data: p_agc_cfg->cut_off_current);
2191	if (status < 0)
2192	goto error;
2193
2194	/* Max. output level */
2195	status = write16(state, SCU_RAM_AGC_RF_MAX__A,
2196	data: p_agc_cfg->max_output_level);
2197	if (status < 0)
2198	goto error;
2199
2200	break;
2201
2202	case DRXK_AGC_CTRL_USER:
2203	/* Enable RF AGC DAC */
2204	status = read16(state, IQM_AF_STDBY__A, data: &data);
2205	if (status < 0)
2206	goto error;
2207	data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2208	status = write16(state, IQM_AF_STDBY__A, data);
2209	if (status < 0)
2210	goto error;
2211
2212	/* Disable SCU RF AGC loop */
2213	status = read16(state, SCU_RAM_AGC_CONFIG__A, data: &data);
2214	if (status < 0)
2215	goto error;
2216	data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2217	if (state->m_rf_agc_pol)
2218	data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2219	else
2220	data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2221	status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2222	if (status < 0)
2223	goto error;
2224
2225	/* SCU c.o.c. to 0, enabling full control range */
2226	status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, data: 0);
2227	if (status < 0)
2228	goto error;
2229
2230	/* Write value to output pin */
2231	status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
2232	data: p_agc_cfg->output_level);
2233	if (status < 0)
2234	goto error;
2235	break;
2236
2237	case DRXK_AGC_CTRL_OFF:
2238	/* Disable RF AGC DAC */
2239	status = read16(state, IQM_AF_STDBY__A, data: &data);
2240	if (status < 0)
2241	goto error;
2242	data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2243	status = write16(state, IQM_AF_STDBY__A, data);
2244	if (status < 0)
2245	goto error;
2246
2247	/* Disable SCU RF AGC loop */
2248	status = read16(state, SCU_RAM_AGC_CONFIG__A, data: &data);
2249	if (status < 0)
2250	goto error;
2251	data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2252	status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2253	if (status < 0)
2254	goto error;
2255	break;
2256
2257	default:
2258	status = -EINVAL;
2259
2260	}
2261	error:
2262	if (status < 0)
2263	pr_err("Error %d on %s\n", status, __func__);
2264	return status;
2265	}
2266
2267	#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2268
2269	static int set_agc_if(struct drxk_state *state,
2270	struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2271	{
2272	u16 data = 0;
2273	int status = 0;
2274	struct s_cfg_agc *p_rf_agc_settings;
2275
2276	dprintk(1, "\n");
2277
2278	switch (p_agc_cfg->ctrl_mode) {
2279	case DRXK_AGC_CTRL_AUTO:
2280
2281	/* Enable IF AGC DAC */
2282	status = read16(state, IQM_AF_STDBY__A, data: &data);
2283	if (status < 0)
2284	goto error;
2285	data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2286	status = write16(state, IQM_AF_STDBY__A, data);
2287	if (status < 0)
2288	goto error;
2289
2290	status = read16(state, SCU_RAM_AGC_CONFIG__A, data: &data);
2291	if (status < 0)
2292	goto error;
2293
2294	/* Enable SCU IF AGC loop */
2295	data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2296
2297	/* Polarity */
2298	if (state->m_if_agc_pol)
2299	data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2300	else
2301	data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2302	status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2303	if (status < 0)
2304	goto error;
2305
2306	/* Set speed (using complementary reduction value) */
2307	status = read16(state, SCU_RAM_AGC_KI_RED__A, data: &data);
2308	if (status < 0)
2309	goto error;
2310	data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2311	data |= (~(p_agc_cfg->speed <<
2312	SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2313	& SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2314
2315	status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2316	if (status < 0)
2317	goto error;
2318
2319	if (is_qam(state))
2320	p_rf_agc_settings = &state->m_qam_rf_agc_cfg;
2321	else
2322	p_rf_agc_settings = &state->m_atv_rf_agc_cfg;
2323	if (p_rf_agc_settings == NULL)
2324	return -1;
2325	/* Restore TOP */
2326	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2327	data: p_rf_agc_settings->top);
2328	if (status < 0)
2329	goto error;
2330	break;
2331
2332	case DRXK_AGC_CTRL_USER:
2333
2334	/* Enable IF AGC DAC */
2335	status = read16(state, IQM_AF_STDBY__A, data: &data);
2336	if (status < 0)
2337	goto error;
2338	data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2339	status = write16(state, IQM_AF_STDBY__A, data);
2340	if (status < 0)
2341	goto error;
2342
2343	status = read16(state, SCU_RAM_AGC_CONFIG__A, data: &data);
2344	if (status < 0)
2345	goto error;
2346
2347	/* Disable SCU IF AGC loop */
2348	data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2349
2350	/* Polarity */
2351	if (state->m_if_agc_pol)
2352	data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2353	else
2354	data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2355	status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2356	if (status < 0)
2357	goto error;
2358
2359	/* Write value to output pin */
2360	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2361	data: p_agc_cfg->output_level);
2362	if (status < 0)
2363	goto error;
2364	break;
2365
2366	case DRXK_AGC_CTRL_OFF:
2367
2368	/* Disable If AGC DAC */
2369	status = read16(state, IQM_AF_STDBY__A, data: &data);
2370	if (status < 0)
2371	goto error;
2372	data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2373	status = write16(state, IQM_AF_STDBY__A, data);
2374	if (status < 0)
2375	goto error;
2376
2377	/* Disable SCU IF AGC loop */
2378	status = read16(state, SCU_RAM_AGC_CONFIG__A, data: &data);
2379	if (status < 0)
2380	goto error;
2381	data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2382	status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2383	if (status < 0)
2384	goto error;
2385	break;
2386	} /* switch (agcSettingsIf->ctrl_mode) */
2387
2388	/* always set the top to support
2389	configurations without if-loop */
2390	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, data: p_agc_cfg->top);
2391	error:
2392	if (status < 0)
2393	pr_err("Error %d on %s\n", status, __func__);
2394	return status;
2395	}
2396
2397	static int get_qam_signal_to_noise(struct drxk_state *state,
2398	s32 *p_signal_to_noise)
2399	{
2400	int status = 0;
2401	u16 qam_sl_err_power = 0; /* accum. error between
2402	raw and sliced symbols */
2403	u32 qam_sl_sig_power = 0; /* used for MER, depends of
2404	QAM modulation */
2405	u32 qam_sl_mer = 0; /* QAM MER */
2406
2407	dprintk(1, "\n");
2408
2409	/* MER calculation */
2410
2411	/* get the register value needed for MER */
2412	status = read16(state, QAM_SL_ERR_POWER__A, data: &qam_sl_err_power);
2413	if (status < 0) {
2414	pr_err("Error %d on %s\n", status, __func__);
2415	return -EINVAL;
2416	}
2417
2418	switch (state->props.modulation) {
2419	case QAM_16:
2420	qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2421	break;
2422	case QAM_32:
2423	qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2424	break;
2425	case QAM_64:
2426	qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2427	break;
2428	case QAM_128:
2429	qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2430	break;
2431	default:
2432	case QAM_256:
2433	qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2434	break;
2435	}
2436
2437	if (qam_sl_err_power > 0) {
2438	qam_sl_mer = log10times100(value: qam_sl_sig_power) -
2439	log10times100(value: (u32) qam_sl_err_power);
2440	}
2441	*p_signal_to_noise = qam_sl_mer;
2442
2443	return status;
2444	}
2445
2446	static int get_dvbt_signal_to_noise(struct drxk_state *state,
2447	s32 *p_signal_to_noise)
2448	{
2449	int status;
2450	u16 reg_data = 0;
2451	u32 eq_reg_td_sqr_err_i = 0;
2452	u32 eq_reg_td_sqr_err_q = 0;
2453	u16 eq_reg_td_sqr_err_exp = 0;
2454	u16 eq_reg_td_tps_pwr_ofs = 0;
2455	u16 eq_reg_td_req_smb_cnt = 0;
2456	u32 tps_cnt = 0;
2457	u32 sqr_err_iq = 0;
2458	u32 a = 0;
2459	u32 b = 0;
2460	u32 c = 0;
2461	u32 i_mer = 0;
2462	u16 transmission_params = 0;
2463
2464	dprintk(1, "\n");
2465
2466	status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
2467	data: &eq_reg_td_tps_pwr_ofs);
2468	if (status < 0)
2469	goto error;
2470	status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
2471	data: &eq_reg_td_req_smb_cnt);
2472	if (status < 0)
2473	goto error;
2474	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
2475	data: &eq_reg_td_sqr_err_exp);
2476	if (status < 0)
2477	goto error;
2478	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
2479	data: &reg_data);
2480	if (status < 0)
2481	goto error;
2482	/* Extend SQR_ERR_I operational range */
2483	eq_reg_td_sqr_err_i = (u32) reg_data;
2484	if ((eq_reg_td_sqr_err_exp > 11) &&
2485	(eq_reg_td_sqr_err_i < 0x00000FFFUL)) {
2486	eq_reg_td_sqr_err_i += 0x00010000UL;
2487	}
2488	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, data: &reg_data);
2489	if (status < 0)
2490	goto error;
2491	/* Extend SQR_ERR_Q operational range */
2492	eq_reg_td_sqr_err_q = (u32) reg_data;
2493	if ((eq_reg_td_sqr_err_exp > 11) &&
2494	(eq_reg_td_sqr_err_q < 0x00000FFFUL))
2495	eq_reg_td_sqr_err_q += 0x00010000UL;
2496
2497	status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
2498	data: &transmission_params);
2499	if (status < 0)
2500	goto error;
2501
2502	/* Check input data for MER */
2503
2504	/* MER calculation (in 0.1 dB) without math.h */
2505	if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0))
2506	i_mer = 0;
2507	else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) {
2508	/* No error at all, this must be the HW reset value
2509	* Apparently no first measurement yet
2510	* Set MER to 0.0 */
2511	i_mer = 0;
2512	} else {
2513	sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) <<
2514	eq_reg_td_sqr_err_exp;
2515	if ((transmission_params &
2516	OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2517	== OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2518	tps_cnt = 17;
2519	else
2520	tps_cnt = 68;
2521
2522	/* IMER = 100 * log10 (x)
2523	where x = (eq_reg_td_tps_pwr_ofs^2 *
2524	eq_reg_td_req_smb_cnt * tps_cnt)/sqr_err_iq
2525
2526	=> IMER = a + b -c
2527	where a = 100 * log10 (eq_reg_td_tps_pwr_ofs^2)
2528	b = 100 * log10 (eq_reg_td_req_smb_cnt * tps_cnt)
2529	c = 100 * log10 (sqr_err_iq)
2530	*/
2531
2532	/* log(x) x = 9bits * 9bits->18 bits */
2533	a = log10times100(value: eq_reg_td_tps_pwr_ofs *
2534	eq_reg_td_tps_pwr_ofs);
2535	/* log(x) x = 16bits * 7bits->23 bits */
2536	b = log10times100(value: eq_reg_td_req_smb_cnt * tps_cnt);
2537	/* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2538	c = log10times100(value: sqr_err_iq);
2539
2540	i_mer = a + b - c;
2541	}
2542	*p_signal_to_noise = i_mer;
2543
2544	error:
2545	if (status < 0)
2546	pr_err("Error %d on %s\n", status, __func__);
2547	return status;
2548	}
2549
2550	static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)
2551	{
2552	dprintk(1, "\n");
2553
2554	*p_signal_to_noise = 0;
2555	switch (state->m_operation_mode) {
2556	case OM_DVBT:
2557	return get_dvbt_signal_to_noise(state, p_signal_to_noise);
2558	case OM_QAM_ITU_A:
2559	case OM_QAM_ITU_C:
2560	return get_qam_signal_to_noise(state, p_signal_to_noise);
2561	default:
2562	break;
2563	}
2564	return 0;
2565	}
2566
2567	#if 0
2568	static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2569	{
2570	/* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2571	int status = 0;
2572
2573	dprintk(1, "\n");
2574
2575	static s32 QE_SN[] = {
2576	51, /* QPSK 1/2 */
2577	69, /* QPSK 2/3 */
2578	79, /* QPSK 3/4 */
2579	89, /* QPSK 5/6 */
2580	97, /* QPSK 7/8 */
2581	108, /* 16-QAM 1/2 */
2582	131, /* 16-QAM 2/3 */
2583	146, /* 16-QAM 3/4 */
2584	156, /* 16-QAM 5/6 */
2585	160, /* 16-QAM 7/8 */
2586	165, /* 64-QAM 1/2 */
2587	187, /* 64-QAM 2/3 */
2588	202, /* 64-QAM 3/4 */
2589	216, /* 64-QAM 5/6 */
2590	225, /* 64-QAM 7/8 */
2591	};
2592
2593	*p_quality = 0;
2594
2595	do {
2596	s32 signal_to_noise = 0;
2597	u16 constellation = 0;
2598	u16 code_rate = 0;
2599	u32 signal_to_noise_rel;
2600	u32 ber_quality;
2601
2602	status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2603	if (status < 0)
2604	break;
2605	status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2606	&constellation);
2607	if (status < 0)
2608	break;
2609	constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2610
2611	status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2612	&code_rate);
2613	if (status < 0)
2614	break;
2615	code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2616
2617	if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2618	code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2619	break;
2620	signal_to_noise_rel = signal_to_noise -
2621	QE_SN[constellation * 5 + code_rate];
2622	ber_quality = 100;
2623
2624	if (signal_to_noise_rel < -70)
2625	*p_quality = 0;
2626	else if (signal_to_noise_rel < 30)
2627	*p_quality = ((signal_to_noise_rel + 70) *
2628	ber_quality) / 100;
2629	else
2630	*p_quality = ber_quality;
2631	} while (0);
2632	return 0;
2633	};
2634
2635	static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2636	{
2637	int status = 0;
2638	*p_quality = 0;
2639
2640	dprintk(1, "\n");
2641
2642	do {
2643	u32 signal_to_noise = 0;
2644	u32 ber_quality = 100;
2645	u32 signal_to_noise_rel = 0;
2646
2647	status = get_qam_signal_to_noise(state, &signal_to_noise);
2648	if (status < 0)
2649	break;
2650
2651	switch (state->props.modulation) {
2652	case QAM_16:
2653	signal_to_noise_rel = signal_to_noise - 200;
2654	break;
2655	case QAM_32:
2656	signal_to_noise_rel = signal_to_noise - 230;
2657	break; /* Not in NorDig */
2658	case QAM_64:
2659	signal_to_noise_rel = signal_to_noise - 260;
2660	break;
2661	case QAM_128:
2662	signal_to_noise_rel = signal_to_noise - 290;
2663	break;
2664	default:
2665	case QAM_256:
2666	signal_to_noise_rel = signal_to_noise - 320;
2667	break;
2668	}
2669
2670	if (signal_to_noise_rel < -70)
2671	*p_quality = 0;
2672	else if (signal_to_noise_rel < 30)
2673	*p_quality = ((signal_to_noise_rel + 70) *
2674	ber_quality) / 100;
2675	else
2676	*p_quality = ber_quality;
2677	} while (0);
2678
2679	return status;
2680	}
2681
2682	static int get_quality(struct drxk_state *state, s32 *p_quality)
2683	{
2684	dprintk(1, "\n");
2685
2686	switch (state->m_operation_mode) {
2687	case OM_DVBT:
2688	return get_dvbt_quality(state, p_quality);
2689	case OM_QAM_ITU_A:
2690	return get_dvbc_quality(state, p_quality);
2691	default:
2692	break;
2693	}
2694
2695	return 0;
2696	}
2697	#endif
2698
2699	/* Free data ram in SIO HI */
2700	#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2701	#define SIO_HI_RA_RAM_USR_END__A 0x420060
2702
2703	#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2704	#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2705	#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2706	#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2707
2708	#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2709	#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2710	#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2711
2712	static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)
2713	{
2714	int status = -EINVAL;
2715
2716	dprintk(1, "\n");
2717
2718	if (state->m_drxk_state == DRXK_UNINITIALIZED)
2719	return 0;
2720	if (state->m_drxk_state == DRXK_POWERED_DOWN)
2721	goto error;
2722
2723	if (state->no_i2c_bridge)
2724	return 0;
2725
2726	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
2727	SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2728	if (status < 0)
2729	goto error;
2730	if (b_enable_bridge) {
2731	status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2732	SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2733	if (status < 0)
2734	goto error;
2735	} else {
2736	status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2737	SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2738	if (status < 0)
2739	goto error;
2740	}
2741
2742	status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);
2743
2744	error:
2745	if (status < 0)
2746	pr_err("Error %d on %s\n", status, __func__);
2747	return status;
2748	}
2749
2750	static int set_pre_saw(struct drxk_state *state,
2751	struct s_cfg_pre_saw *p_pre_saw_cfg)
2752	{
2753	int status = -EINVAL;
2754
2755	dprintk(1, "\n");
2756
2757	if ((p_pre_saw_cfg == NULL)
2758	|| (p_pre_saw_cfg->reference > IQM_AF_PDREF__M))
2759	goto error;
2760
2761	status = write16(state, IQM_AF_PDREF__A, data: p_pre_saw_cfg->reference);
2762	error:
2763	if (status < 0)
2764	pr_err("Error %d on %s\n", status, __func__);
2765	return status;
2766	}
2767
2768	static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,
2769	u16 rom_offset, u16 nr_of_elements, u32 time_out)
2770	{
2771	u16 bl_status = 0;
2772	u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF);
2773	u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF);
2774	int status;
2775	unsigned long end;
2776
2777	dprintk(1, "\n");
2778
2779	mutex_lock(&state->mutex);
2780	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2781	if (status < 0)
2782	goto error;
2783	status = write16(state, SIO_BL_TGT_HDR__A, data: blockbank);
2784	if (status < 0)
2785	goto error;
2786	status = write16(state, SIO_BL_TGT_ADDR__A, data: offset);
2787	if (status < 0)
2788	goto error;
2789	status = write16(state, SIO_BL_SRC_ADDR__A, data: rom_offset);
2790	if (status < 0)
2791	goto error;
2792	status = write16(state, SIO_BL_SRC_LEN__A, data: nr_of_elements);
2793	if (status < 0)
2794	goto error;
2795	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2796	if (status < 0)
2797	goto error;
2798
2799	end = jiffies + msecs_to_jiffies(m: time_out);
2800	do {
2801	status = read16(state, SIO_BL_STATUS__A, data: &bl_status);
2802	if (status < 0)
2803	goto error;
2804	} while ((bl_status == 0x1) && time_is_after_jiffies(end));
2805	if (bl_status == 0x1) {
2806	pr_err("SIO not ready\n");
2807	status = -EINVAL;
2808	goto error2;
2809	}
2810	error:
2811	if (status < 0)
2812	pr_err("Error %d on %s\n", status, __func__);
2813	error2:
2814	mutex_unlock(lock: &state->mutex);
2815	return status;
2816
2817	}
2818
2819	static int adc_sync_measurement(struct drxk_state *state, u16 *count)
2820	{
2821	u16 data = 0;
2822	int status;
2823
2824	dprintk(1, "\n");
2825
2826	/* start measurement */
2827	status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2828	if (status < 0)
2829	goto error;
2830	status = write16(state, IQM_AF_START_LOCK__A, data: 1);
2831	if (status < 0)
2832	goto error;
2833
2834	*count = 0;
2835	status = read16(state, IQM_AF_PHASE0__A, data: &data);
2836	if (status < 0)
2837	goto error;
2838	if (data == 127)
2839	*count = *count + 1;
2840	status = read16(state, IQM_AF_PHASE1__A, data: &data);
2841	if (status < 0)
2842	goto error;
2843	if (data == 127)
2844	*count = *count + 1;
2845	status = read16(state, IQM_AF_PHASE2__A, data: &data);
2846	if (status < 0)
2847	goto error;
2848	if (data == 127)
2849	*count = *count + 1;
2850
2851	error:
2852	if (status < 0)
2853	pr_err("Error %d on %s\n", status, __func__);
2854	return status;
2855	}
2856
2857	static int adc_synchronization(struct drxk_state *state)
2858	{
2859	u16 count = 0;
2860	int status;
2861
2862	dprintk(1, "\n");
2863
2864	status = adc_sync_measurement(state, count: &count);
2865	if (status < 0)
2866	goto error;
2867
2868	if (count == 1) {
2869	/* Try sampling on a different edge */
2870	u16 clk_neg = 0;
2871
2872	status = read16(state, IQM_AF_CLKNEG__A, data: &clk_neg);
2873	if (status < 0)
2874	goto error;
2875	if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2876	IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2877	clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2878	clk_neg |=
2879	IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2880	} else {
2881	clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2882	clk_neg |=
2883	IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2884	}
2885	status = write16(state, IQM_AF_CLKNEG__A, data: clk_neg);
2886	if (status < 0)
2887	goto error;
2888	status = adc_sync_measurement(state, count: &count);
2889	if (status < 0)
2890	goto error;
2891	}
2892
2893	if (count < 2)
2894	status = -EINVAL;
2895	error:
2896	if (status < 0)
2897	pr_err("Error %d on %s\n", status, __func__);
2898	return status;
2899	}
2900
2901	static int set_frequency_shifter(struct drxk_state *state,
2902	u16 intermediate_freqk_hz,
2903	s32 tuner_freq_offset, bool is_dtv)
2904	{
2905	bool select_pos_image = false;
2906	u32 rf_freq_residual = tuner_freq_offset;
2907	u32 fm_frequency_shift = 0;
2908	bool tuner_mirror = !state->m_b_mirror_freq_spect;
2909	u32 adc_freq;
2910	bool adc_flip;
2911	int status;
2912	u32 if_freq_actual;
2913	u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);
2914	u32 frequency_shift;
2915	bool image_to_select;
2916
2917	dprintk(1, "\n");
2918
2919	/*
2920	Program frequency shifter
2921	No need to account for mirroring on RF
2922	*/
2923	if (is_dtv) {
2924	if ((state->m_operation_mode == OM_QAM_ITU_A) ||
2925	(state->m_operation_mode == OM_QAM_ITU_C) ||
2926	(state->m_operation_mode == OM_DVBT))
2927	select_pos_image = true;
2928	else
2929	select_pos_image = false;
2930	}
2931	if (tuner_mirror)
2932	/* tuner doesn't mirror */
2933	if_freq_actual = intermediate_freqk_hz +
2934	rf_freq_residual + fm_frequency_shift;
2935	else
2936	/* tuner mirrors */
2937	if_freq_actual = intermediate_freqk_hz -
2938	rf_freq_residual - fm_frequency_shift;
2939	if (if_freq_actual > sampling_frequency / 2) {
2940	/* adc mirrors */
2941	adc_freq = sampling_frequency - if_freq_actual;
2942	adc_flip = true;
2943	} else {
2944	/* adc doesn't mirror */
2945	adc_freq = if_freq_actual;
2946	adc_flip = false;
2947	}
2948
2949	frequency_shift = adc_freq;
2950	image_to_select = state->m_rfmirror ^ tuner_mirror ^
2951	adc_flip ^ select_pos_image;
2952	state->m_iqm_fs_rate_ofs =
2953	Frac28a(a: (frequency_shift), c: sampling_frequency);
2954
2955	if (image_to_select)
2956	state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;
2957
2958	/* Program frequency shifter with tuner offset compensation */
2959	/* frequency_shift += tuner_freq_offset; TODO */
2960	status = write32(state, IQM_FS_RATE_OFS_LO__A,
2961	data: state->m_iqm_fs_rate_ofs);
2962	if (status < 0)
2963	pr_err("Error %d on %s\n", status, __func__);
2964	return status;
2965	}
2966
2967	static int init_agc(struct drxk_state *state, bool is_dtv)
2968	{
2969	u16 ingain_tgt = 0;
2970	u16 ingain_tgt_min = 0;
2971	u16 ingain_tgt_max = 0;
2972	u16 clp_cyclen = 0;
2973	u16 clp_sum_min = 0;
2974	u16 clp_dir_to = 0;
2975	u16 sns_sum_min = 0;
2976	u16 sns_sum_max = 0;
2977	u16 clp_sum_max = 0;
2978	u16 sns_dir_to = 0;
2979	u16 ki_innergain_min = 0;
2980	u16 if_iaccu_hi_tgt = 0;
2981	u16 if_iaccu_hi_tgt_min = 0;
2982	u16 if_iaccu_hi_tgt_max = 0;
2983	u16 data = 0;
2984	u16 fast_clp_ctrl_delay = 0;
2985	u16 clp_ctrl_mode = 0;
2986	int status = 0;
2987
2988	dprintk(1, "\n");
2989
2990	/* Common settings */
2991	sns_sum_max = 1023;
2992	if_iaccu_hi_tgt_min = 2047;
2993	clp_cyclen = 500;
2994	clp_sum_max = 1023;
2995
2996	/* AGCInit() not available for DVBT; init done in microcode */
2997	if (!is_qam(state)) {
2998	pr_err("%s: mode %d is not DVB-C\n",
2999	__func__, state->m_operation_mode);
3000	return -EINVAL;
3001	}
3002
3003	/* FIXME: Analog TV AGC require different settings */
3004
3005	/* Standard specific settings */
3006	clp_sum_min = 8;
3007	clp_dir_to = (u16) -9;
3008	clp_ctrl_mode = 0;
3009	sns_sum_min = 8;
3010	sns_dir_to = (u16) -9;
3011	ki_innergain_min = (u16) -1030;
3012	if_iaccu_hi_tgt_max = 0x2380;
3013	if_iaccu_hi_tgt = 0x2380;
3014	ingain_tgt_min = 0x0511;
3015	ingain_tgt = 0x0511;
3016	ingain_tgt_max = 5119;
3017	fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
3018
3019	status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3020	data: fast_clp_ctrl_delay);
3021	if (status < 0)
3022	goto error;
3023
3024	status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, data: clp_ctrl_mode);
3025	if (status < 0)
3026	goto error;
3027	status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, data: ingain_tgt);
3028	if (status < 0)
3029	goto error;
3030	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, data: ingain_tgt_min);
3031	if (status < 0)
3032	goto error;
3033	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, data: ingain_tgt_max);
3034	if (status < 0)
3035	goto error;
3036	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
3037	data: if_iaccu_hi_tgt_min);
3038	if (status < 0)
3039	goto error;
3040	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
3041	data: if_iaccu_hi_tgt_max);
3042	if (status < 0)
3043	goto error;
3044	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, data: 0);
3045	if (status < 0)
3046	goto error;
3047	status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, data: 0);
3048	if (status < 0)
3049	goto error;
3050	status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, data: 0);
3051	if (status < 0)
3052	goto error;
3053	status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, data: 0);
3054	if (status < 0)
3055	goto error;
3056	status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, data: clp_sum_max);
3057	if (status < 0)
3058	goto error;
3059	status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, data: sns_sum_max);
3060	if (status < 0)
3061	goto error;
3062
3063	status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
3064	data: ki_innergain_min);
3065	if (status < 0)
3066	goto error;
3067	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
3068	data: if_iaccu_hi_tgt);
3069	if (status < 0)
3070	goto error;
3071	status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, data: clp_cyclen);
3072	if (status < 0)
3073	goto error;
3074
3075	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, data: 1023);
3076	if (status < 0)
3077	goto error;
3078	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, data: (u16) -1023);
3079	if (status < 0)
3080	goto error;
3081	status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, data: 50);
3082	if (status < 0)
3083	goto error;
3084
3085	status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, data: 20);
3086	if (status < 0)
3087	goto error;
3088	status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, data: clp_sum_min);
3089	if (status < 0)
3090	goto error;
3091	status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, data: sns_sum_min);
3092	if (status < 0)
3093	goto error;
3094	status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, data: clp_dir_to);
3095	if (status < 0)
3096	goto error;
3097	status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, data: sns_dir_to);
3098	if (status < 0)
3099	goto error;
3100	status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, data: 0x7fff);
3101	if (status < 0)
3102	goto error;
3103	status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, data: 0x0);
3104	if (status < 0)
3105	goto error;
3106	status = write16(state, SCU_RAM_AGC_KI_MIN__A, data: 0x0117);
3107	if (status < 0)
3108	goto error;
3109	status = write16(state, SCU_RAM_AGC_KI_MAX__A, data: 0x0657);
3110	if (status < 0)
3111	goto error;
3112	status = write16(state, SCU_RAM_AGC_CLP_SUM__A, data: 0);
3113	if (status < 0)
3114	goto error;
3115	status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, data: 0);
3116	if (status < 0)
3117	goto error;
3118	status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, data: 0);
3119	if (status < 0)
3120	goto error;
3121	status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, data: 1);
3122	if (status < 0)
3123	goto error;
3124	status = write16(state, SCU_RAM_AGC_SNS_SUM__A, data: 0);
3125	if (status < 0)
3126	goto error;
3127	status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, data: 0);
3128	if (status < 0)
3129	goto error;
3130	status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, data: 0);
3131	if (status < 0)
3132	goto error;
3133	status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, data: 1);
3134	if (status < 0)
3135	goto error;
3136	status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, data: 500);
3137	if (status < 0)
3138	goto error;
3139	status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, data: 500);
3140	if (status < 0)
3141	goto error;
3142
3143	/* Initialize inner-loop KI gain factors */
3144	status = read16(state, SCU_RAM_AGC_KI__A, data: &data);
3145	if (status < 0)
3146	goto error;
3147
3148	data = 0x0657;
3149	data &= ~SCU_RAM_AGC_KI_RF__M;
3150	data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3151	data &= ~SCU_RAM_AGC_KI_IF__M;
3152	data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3153
3154	status = write16(state, SCU_RAM_AGC_KI__A, data);
3155	error:
3156	if (status < 0)
3157	pr_err("Error %d on %s\n", status, __func__);
3158	return status;
3159	}
3160
3161	static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)
3162	{
3163	int status;
3164
3165	dprintk(1, "\n");
3166	if (packet_err == NULL)
3167	status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, data: 0);
3168	else
3169	status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
3170	data: packet_err);
3171	if (status < 0)
3172	pr_err("Error %d on %s\n", status, __func__);
3173	return status;
3174	}
3175
3176	static int dvbt_sc_command(struct drxk_state *state,
3177	u16 cmd, u16 subcmd,
3178	u16 param0, u16 param1, u16 param2,
3179	u16 param3, u16 param4)
3180	{
3181	u16 cur_cmd = 0;
3182	u16 err_code = 0;
3183	u16 retry_cnt = 0;
3184	u16 sc_exec = 0;
3185	int status;
3186
3187	dprintk(1, "\n");
3188	status = read16(state, OFDM_SC_COMM_EXEC__A, data: &sc_exec);
3189	if (sc_exec != 1) {
3190	/* SC is not running */
3191	status = -EINVAL;
3192	}
3193	if (status < 0)
3194	goto error;
3195
3196	/* Wait until sc is ready to receive command */
3197	retry_cnt = 0;
3198	do {
3199	usleep_range(min: 1000, max: 2000);
3200	status = read16(state, OFDM_SC_RA_RAM_CMD__A, data: &cur_cmd);
3201	retry_cnt++;
3202	} while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3203	if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3204	goto error;
3205
3206	/* Write sub-command */
3207	switch (cmd) {
3208	/* All commands using sub-cmd */
3209	case OFDM_SC_RA_RAM_CMD_PROC_START:
3210	case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3211	case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3212	status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, data: subcmd);
3213	if (status < 0)
3214	goto error;
3215	break;
3216	default:
3217	/* Do nothing */
3218	break;
3219	}
3220
3221	/* Write needed parameters and the command */
3222	status = 0;
3223	switch (cmd) {
3224	/* All commands using 5 parameters */
3225	/* All commands using 4 parameters */
3226	/* All commands using 3 parameters */
3227	/* All commands using 2 parameters */
3228	case OFDM_SC_RA_RAM_CMD_PROC_START:
3229	case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3230	case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3231	status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, data: param1);
3232	fallthrough; /* All commands using 1 parameters */
3233	case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3234	case OFDM_SC_RA_RAM_CMD_USER_IO:
3235	status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, data: param0);
3236	fallthrough; /* All commands using 0 parameters */
3237	case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3238	case OFDM_SC_RA_RAM_CMD_NULL:
3239	/* Write command */
3240	status |= write16(state, OFDM_SC_RA_RAM_CMD__A, data: cmd);
3241	break;
3242	default:
3243	/* Unknown command */
3244	status = -EINVAL;
3245	}
3246	if (status < 0)
3247	goto error;
3248
3249	/* Wait until sc is ready processing command */
3250	retry_cnt = 0;
3251	do {
3252	usleep_range(min: 1000, max: 2000);
3253	status = read16(state, OFDM_SC_RA_RAM_CMD__A, data: &cur_cmd);
3254	retry_cnt++;
3255	} while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3256	if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3257	goto error;
3258
3259	/* Check for illegal cmd */
3260	status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, data: &err_code);
3261	if (err_code == 0xFFFF) {
3262	/* illegal command */
3263	status = -EINVAL;
3264	}
3265	if (status < 0)
3266	goto error;
3267
3268	/* Retrieve results parameters from SC */
3269	switch (cmd) {
3270	/* All commands yielding 5 results */
3271	/* All commands yielding 4 results */
3272	/* All commands yielding 3 results */
3273	/* All commands yielding 2 results */
3274	/* All commands yielding 1 result */
3275	case OFDM_SC_RA_RAM_CMD_USER_IO:
3276	case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3277	status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, data: &(param0));
3278	break;
3279	/* All commands yielding 0 results */
3280	case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3281	case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3282	case OFDM_SC_RA_RAM_CMD_PROC_START:
3283	case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3284	case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3285	case OFDM_SC_RA_RAM_CMD_NULL:
3286	break;
3287	default:
3288	/* Unknown command */
3289	status = -EINVAL;
3290	break;
3291	} /* switch (cmd->cmd) */
3292	error:
3293	if (status < 0)
3294	pr_err("Error %d on %s\n", status, __func__);
3295	return status;
3296	}
3297
3298	static int power_up_dvbt(struct drxk_state *state)
3299	{
3300	enum drx_power_mode power_mode = DRX_POWER_UP;
3301	int status;
3302
3303	dprintk(1, "\n");
3304	status = ctrl_power_mode(state, mode: &power_mode);
3305	if (status < 0)
3306	pr_err("Error %d on %s\n", status, __func__);
3307	return status;
3308	}
3309
3310	static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)
3311	{
3312	int status;
3313
3314	dprintk(1, "\n");
3315	if (*enabled)
3316	status = write16(state, IQM_CF_BYPASSDET__A, data: 0);
3317	else
3318	status = write16(state, IQM_CF_BYPASSDET__A, data: 1);
3319	if (status < 0)
3320	pr_err("Error %d on %s\n", status, __func__);
3321	return status;
3322	}
3323
3324	#define DEFAULT_FR_THRES_8K 4000
3325	static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
3326	{
3327
3328	int status;
3329
3330	dprintk(1, "\n");
3331	if (*enabled) {
3332	/* write mask to 1 */
3333	status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3334	DEFAULT_FR_THRES_8K);
3335	} else {
3336	/* write mask to 0 */
3337	status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, data: 0);
3338	}
3339	if (status < 0)
3340	pr_err("Error %d on %s\n", status, __func__);
3341
3342	return status;
3343	}
3344
3345	static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
3346	struct drxk_cfg_dvbt_echo_thres_t *echo_thres)
3347	{
3348	u16 data = 0;
3349	int status;
3350
3351	dprintk(1, "\n");
3352	status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data: &data);
3353	if (status < 0)
3354	goto error;
3355
3356	switch (echo_thres->fft_mode) {
3357	case DRX_FFTMODE_2K:
3358	data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3359	data |= ((echo_thres->threshold <<
3360	OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3361	& (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3362	break;
3363	case DRX_FFTMODE_8K:
3364	data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3365	data |= ((echo_thres->threshold <<
3366	OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3367	& (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3368	break;
3369	default:
3370	return -EINVAL;
3371	}
3372
3373	status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3374	error:
3375	if (status < 0)
3376	pr_err("Error %d on %s\n", status, __func__);
3377	return status;
3378	}
3379
3380	static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,
3381	enum drxk_cfg_dvbt_sqi_speed *speed)
3382	{
3383	int status = -EINVAL;
3384
3385	dprintk(1, "\n");
3386
3387	switch (*speed) {
3388	case DRXK_DVBT_SQI_SPEED_FAST:
3389	case DRXK_DVBT_SQI_SPEED_MEDIUM:
3390	case DRXK_DVBT_SQI_SPEED_SLOW:
3391	break;
3392	default:
3393	goto error;
3394	}
3395	status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3396	data: (u16) *speed);
3397	error:
3398	if (status < 0)
3399	pr_err("Error %d on %s\n", status, __func__);
3400	return status;
3401	}
3402
3403	/*============================================================================*/
3404
3405	/*
3406	* \brief Activate DVBT specific presets
3407	* \param demod instance of demodulator.
3408	* \return DRXStatus_t.
3409	*
3410	* Called in DVBTSetStandard
3411	*
3412	*/
3413	static int dvbt_activate_presets(struct drxk_state *state)
3414	{
3415	int status;
3416	bool setincenable = false;
3417	bool setfrenable = true;
3418
3419	struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K };
3420	struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K };
3421
3422	dprintk(1, "\n");
3423	status = dvbt_ctrl_set_inc_enable(state, enabled: &setincenable);
3424	if (status < 0)
3425	goto error;
3426	status = dvbt_ctrl_set_fr_enable(state, enabled: &setfrenable);
3427	if (status < 0)
3428	goto error;
3429	status = dvbt_ctrl_set_echo_threshold(state, echo_thres: &echo_thres2k);
3430	if (status < 0)
3431	goto error;
3432	status = dvbt_ctrl_set_echo_threshold(state, echo_thres: &echo_thres8k);
3433	if (status < 0)
3434	goto error;
3435	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
3436	data: state->m_dvbt_if_agc_cfg.ingain_tgt_max);
3437	error:
3438	if (status < 0)
3439	pr_err("Error %d on %s\n", status, __func__);
3440	return status;
3441	}
3442
3443	/*============================================================================*/
3444
3445	/*
3446	* \brief Initialize channelswitch-independent settings for DVBT.
3447	* \param demod instance of demodulator.
3448	* \return DRXStatus_t.
3449	*
3450	* For ROM code channel filter taps are loaded from the bootloader. For microcode
3451	* the DVB-T taps from the drxk_filters.h are used.
3452	*/
3453	static int set_dvbt_standard(struct drxk_state *state,
3454	enum operation_mode o_mode)
3455	{
3456	u16 cmd_result = 0;
3457	u16 data = 0;
3458	int status;
3459
3460	dprintk(1, "\n");
3461
3462	power_up_dvbt(state);
3463	/* added antenna switch */
3464	switch_antenna_to_dvbt(state);
3465	/* send OFDM reset command */
3466	status = scu_command(state,
3467	SCU_RAM_COMMAND_STANDARD_OFDM
3468	| SCU_RAM_COMMAND_CMD_DEMOD_RESET,
3469	parameter_len: 0, NULL, result_len: 1, result: &cmd_result);
3470	if (status < 0)
3471	goto error;
3472
3473	/* send OFDM setenv command */
3474	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3475	| SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
3476	parameter_len: 0, NULL, result_len: 1, result: &cmd_result);
3477	if (status < 0)
3478	goto error;
3479
3480	/* reset datapath for OFDM, processors first */
3481	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3482	if (status < 0)
3483	goto error;
3484	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3485	if (status < 0)
3486	goto error;
3487	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3488	if (status < 0)
3489	goto error;
3490
3491	/* IQM setup */
3492	/* synchronize on ofdstate->m_festart */
3493	status = write16(state, IQM_AF_UPD_SEL__A, data: 1);
3494	if (status < 0)
3495	goto error;
3496	/* window size for clipping ADC detection */
3497	status = write16(state, IQM_AF_CLP_LEN__A, data: 0);
3498	if (status < 0)
3499	goto error;
3500	/* window size for sense pre-SAW detection */
3501	status = write16(state, IQM_AF_SNS_LEN__A, data: 0);
3502	if (status < 0)
3503	goto error;
3504	/* sense threshold for sense pre-SAW detection */
3505	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3506	if (status < 0)
3507	goto error;
3508	status = set_iqm_af(state, active: true);
3509	if (status < 0)
3510	goto error;
3511
3512	status = write16(state, IQM_AF_AGC_RF__A, data: 0);
3513	if (status < 0)
3514	goto error;
3515
3516	/* Impulse noise cruncher setup */
3517	status = write16(state, IQM_AF_INC_LCT__A, data: 0); /* crunch in IQM_CF */
3518	if (status < 0)
3519	goto error;
3520	status = write16(state, IQM_CF_DET_LCT__A, data: 0); /* detect in IQM_CF */
3521	if (status < 0)
3522	goto error;
3523	status = write16(state, IQM_CF_WND_LEN__A, data: 3); /* peak detector window length */
3524	if (status < 0)
3525	goto error;
3526
3527	status = write16(state, IQM_RC_STRETCH__A, data: 16);
3528	if (status < 0)
3529	goto error;
3530	status = write16(state, IQM_CF_OUT_ENA__A, data: 0x4); /* enable output 2 */
3531	if (status < 0)
3532	goto error;
3533	status = write16(state, IQM_CF_DS_ENA__A, data: 0x4); /* decimate output 2 */
3534	if (status < 0)
3535	goto error;
3536	status = write16(state, IQM_CF_SCALE__A, data: 1600);
3537	if (status < 0)
3538	goto error;
3539	status = write16(state, IQM_CF_SCALE_SH__A, data: 0);
3540	if (status < 0)
3541	goto error;
3542
3543	/* virtual clipping threshold for clipping ADC detection */
3544	status = write16(state, IQM_AF_CLP_TH__A, data: 448);
3545	if (status < 0)
3546	goto error;
3547	status = write16(state, IQM_CF_DATATH__A, data: 495); /* crunching threshold */
3548	if (status < 0)
3549	goto error;
3550
3551	status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
3552	DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3553	if (status < 0)
3554	goto error;
3555
3556	status = write16(state, IQM_CF_PKDTH__A, data: 2); /* peak detector threshold */
3557	if (status < 0)
3558	goto error;
3559	status = write16(state, IQM_CF_POW_MEAS_LEN__A, data: 2);
3560	if (status < 0)
3561	goto error;
3562	/* enable power measurement interrupt */
3563	status = write16(state, IQM_CF_COMM_INT_MSK__A, data: 1);
3564	if (status < 0)
3565	goto error;
3566	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3567	if (status < 0)
3568	goto error;
3569
3570	/* IQM will not be reset from here, sync ADC and update/init AGC */
3571	status = adc_synchronization(state);
3572	if (status < 0)
3573	goto error;
3574	status = set_pre_saw(state, p_pre_saw_cfg: &state->m_dvbt_pre_saw_cfg);
3575	if (status < 0)
3576	goto error;
3577
3578	/* Halt SCU to enable safe non-atomic accesses */
3579	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3580	if (status < 0)
3581	goto error;
3582
3583	status = set_agc_rf(state, p_agc_cfg: &state->m_dvbt_rf_agc_cfg, is_dtv: true);
3584	if (status < 0)
3585	goto error;
3586	status = set_agc_if(state, p_agc_cfg: &state->m_dvbt_if_agc_cfg, is_dtv: true);
3587	if (status < 0)
3588	goto error;
3589
3590	/* Set Noise Estimation notch width and enable DC fix */
3591	status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, data: &data);
3592	if (status < 0)
3593	goto error;
3594	data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3595	status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3596	if (status < 0)
3597	goto error;
3598
3599	/* Activate SCU to enable SCU commands */
3600	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3601	if (status < 0)
3602	goto error;
3603
3604	if (!state->m_drxk_a3_rom_code) {
3605	/* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay */
3606	status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3607	data: state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
3608	if (status < 0)
3609	goto error;
3610	}
3611
3612	/* OFDM_SC setup */
3613	#ifdef COMPILE_FOR_NONRT
3614	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3615	if (status < 0)
3616	goto error;
3617	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3618	if (status < 0)
3619	goto error;
3620	#endif
3621
3622	/* FEC setup */
3623	status = write16(state, FEC_DI_INPUT_CTL__A, data: 1); /* OFDM input */
3624	if (status < 0)
3625	goto error;
3626
3627
3628	#ifdef COMPILE_FOR_NONRT
3629	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3630	if (status < 0)
3631	goto error;
3632	#else
3633	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, data: 0x1000);
3634	if (status < 0)
3635	goto error;
3636	#endif
3637	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, data: 0x0001);
3638	if (status < 0)
3639	goto error;
3640
3641	/* Setup MPEG bus */
3642	status = mpegts_dto_setup(state, o_mode: OM_DVBT);
3643	if (status < 0)
3644	goto error;
3645	/* Set DVBT Presets */
3646	status = dvbt_activate_presets(state);
3647	if (status < 0)
3648	goto error;
3649
3650	error:
3651	if (status < 0)
3652	pr_err("Error %d on %s\n", status, __func__);
3653	return status;
3654	}
3655
3656	/*============================================================================*/
3657	/*
3658	* \brief start dvbt demodulating for channel.
3659	* \param demod instance of demodulator.
3660	* \return DRXStatus_t.
3661	*/
3662	static int dvbt_start(struct drxk_state *state)
3663	{
3664	u16 param1;
3665	int status;
3666	/* drxk_ofdm_sc_cmd_t scCmd; */
3667
3668	dprintk(1, "\n");
3669	/* start correct processes to get in lock */
3670	/* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3671	param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3672	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, subcmd: 0,
3673	OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1,
3674	param2: 0, param3: 0, param4: 0);
3675	if (status < 0)
3676	goto error;
3677	/* start FEC OC */
3678	status = mpegts_start(state);
3679	if (status < 0)
3680	goto error;
3681	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3682	if (status < 0)
3683	goto error;
3684	error:
3685	if (status < 0)
3686	pr_err("Error %d on %s\n", status, __func__);
3687	return status;
3688	}
3689
3690
3691	/*============================================================================*/
3692
3693	/*
3694	* \brief Set up dvbt demodulator for channel.
3695	* \param demod instance of demodulator.
3696	* \return DRXStatus_t.
3697	* // original DVBTSetChannel()
3698	*/
3699	static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3700	s32 tuner_freq_offset)
3701	{
3702	u16 cmd_result = 0;
3703	u16 transmission_params = 0;
3704	u32 iqm_rc_rate_ofs = 0;
3705	u32 bandwidth = 0;
3706	u16 param1;
3707	int status;
3708
3709	dprintk(1, "IF =%d, TFO = %d\n",
3710	intermediate_freqk_hz, tuner_freq_offset);
3711
3712	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3713	| SCU_RAM_COMMAND_CMD_DEMOD_STOP,
3714	parameter_len: 0, NULL, result_len: 1, result: &cmd_result);
3715	if (status < 0)
3716	goto error;
3717
3718	/* Halt SCU to enable safe non-atomic accesses */
3719	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3720	if (status < 0)
3721	goto error;
3722
3723	/* Stop processors */
3724	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3725	if (status < 0)
3726	goto error;
3727	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3728	if (status < 0)
3729	goto error;
3730
3731	/* Mandatory fix, always stop CP, required to set spl offset back to
3732	hardware default (is set to 0 by ucode during pilot detection */
3733	status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3734	if (status < 0)
3735	goto error;
3736
3737	/*== Write channel settings to device ================================*/
3738
3739	/* mode */
3740	switch (state->props.transmission_mode) {
3741	case TRANSMISSION_MODE_AUTO:
3742	case TRANSMISSION_MODE_8K:
3743	default:
3744	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3745	break;
3746	case TRANSMISSION_MODE_2K:
3747	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3748	break;
3749	}
3750
3751	/* guard */
3752	switch (state->props.guard_interval) {
3753	default:
3754	case GUARD_INTERVAL_AUTO: /* try first guess DRX_GUARD_1DIV4 */
3755	case GUARD_INTERVAL_1_4:
3756	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3757	break;
3758	case GUARD_INTERVAL_1_32:
3759	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3760	break;
3761	case GUARD_INTERVAL_1_16:
3762	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3763	break;
3764	case GUARD_INTERVAL_1_8:
3765	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3766	break;
3767	}
3768
3769	/* hierarchy */
3770	switch (state->props.hierarchy) {
3771	case HIERARCHY_AUTO:
3772	case HIERARCHY_NONE:
3773	default: /* try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3774	case HIERARCHY_1:
3775	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3776	break;
3777	case HIERARCHY_2:
3778	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3779	break;
3780	case HIERARCHY_4:
3781	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3782	break;
3783	}
3784
3785
3786	/* modulation */
3787	switch (state->props.modulation) {
3788	case QAM_AUTO:
3789	default: /* try first guess DRX_CONSTELLATION_QAM64 */
3790	case QAM_64:
3791	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3792	break;
3793	case QPSK:
3794	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3795	break;
3796	case QAM_16:
3797	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3798	break;
3799	}
3800	#if 0
3801	/* No hierarchical channels support in BDA */
3802	/* Priority (only for hierarchical channels) */
3803	switch (channel->priority) {
3804	case DRX_PRIORITY_LOW:
3805	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3806	WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3807	OFDM_EC_SB_PRIOR_LO);
3808	break;
3809	case DRX_PRIORITY_HIGH:
3810	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3811	WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3812	OFDM_EC_SB_PRIOR_HI));
3813	break;
3814	case DRX_PRIORITY_UNKNOWN:
3815	default:
3816	status = -EINVAL;
3817	goto error;
3818	}
3819	#else
3820	/* Set Priority high */
3821	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3822	status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3823	if (status < 0)
3824	goto error;
3825	#endif
3826
3827	/* coderate */
3828	switch (state->props.code_rate_HP) {
3829	case FEC_AUTO:
3830	default: /* try first guess DRX_CODERATE_2DIV3 */
3831	case FEC_2_3:
3832	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3833	break;
3834	case FEC_1_2:
3835	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3836	break;
3837	case FEC_3_4:
3838	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3839	break;
3840	case FEC_5_6:
3841	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3842	break;
3843	case FEC_7_8:
3844	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3845	break;
3846	}
3847
3848	/*
3849	* SAW filter selection: normally not necessary, but if wanted
3850	* the application can select a SAW filter via the driver by
3851	* using UIOs
3852	*/
3853
3854	/* First determine real bandwidth (Hz) */
3855	/* Also set delay for impulse noise cruncher */
3856	/*
3857	* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is
3858	* changed by SC for fix for some 8K,1/8 guard but is restored by
3859	* InitEC and ResetEC functions
3860	*/
3861	switch (state->props.bandwidth_hz) {
3862	case 0:
3863	state->props.bandwidth_hz = 8000000;
3864	fallthrough;
3865	case 8000000:
3866	bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3867	status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3868	data: 3052);
3869	if (status < 0)
3870	goto error;
3871	/* cochannel protection for PAL 8 MHz */
3872	status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3873	data: 7);
3874	if (status < 0)
3875	goto error;
3876	status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3877	data: 7);
3878	if (status < 0)
3879	goto error;
3880	status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3881	data: 7);
3882	if (status < 0)
3883	goto error;
3884	status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3885	data: 1);
3886	if (status < 0)
3887	goto error;
3888	break;
3889	case 7000000:
3890	bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3891	status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3892	data: 3491);
3893	if (status < 0)
3894	goto error;
3895	/* cochannel protection for PAL 7 MHz */
3896	status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3897	data: 8);
3898	if (status < 0)
3899	goto error;
3900	status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3901	data: 8);
3902	if (status < 0)
3903	goto error;
3904	status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3905	data: 4);
3906	if (status < 0)
3907	goto error;
3908	status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3909	data: 1);
3910	if (status < 0)
3911	goto error;
3912	break;
3913	case 6000000:
3914	bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3915	status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3916	data: 4073);
3917	if (status < 0)
3918	goto error;
3919	/* cochannel protection for NTSC 6 MHz */
3920	status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3921	data: 19);
3922	if (status < 0)
3923	goto error;
3924	status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3925	data: 19);
3926	if (status < 0)
3927	goto error;
3928	status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3929	data: 14);
3930	if (status < 0)
3931	goto error;
3932	status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3933	data: 1);
3934	if (status < 0)
3935	goto error;
3936	break;
3937	default:
3938	status = -EINVAL;
3939	goto error;
3940	}
3941
3942	if (iqm_rc_rate_ofs == 0) {
3943	/* Now compute IQM_RC_RATE_OFS
3944	(((SysFreq/BandWidth)/2)/2) -1) * 2^23)
3945	=>
3946	((SysFreq / BandWidth) * (2^21)) - (2^23)
3947	*/
3948	/* (SysFreq / BandWidth) * (2^28) */
3949	/*
3950	* assert (MAX(sysClk)/MIN(bandwidth) < 16)
3951	* => assert(MAX(sysClk) < 16*MIN(bandwidth))
3952	* => assert(109714272 > 48000000) = true
3953	* so Frac 28 can be used
3954	*/
3955	iqm_rc_rate_ofs = Frac28a(a: (u32)
3956	((state->m_sys_clock_freq *
3957	1000) / 3), c: bandwidth);
3958	/* (SysFreq / BandWidth) * (2^21), rounding before truncating */
3959	if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40)
3960	iqm_rc_rate_ofs += 0x80L;
3961	iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7;
3962	/* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
3963	iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23);
3964	}
3965
3966	iqm_rc_rate_ofs &=
3967	((((u32) IQM_RC_RATE_OFS_HI__M) <<
3968	IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
3969	status = write32(state, IQM_RC_RATE_OFS_LO__A, data: iqm_rc_rate_ofs);
3970	if (status < 0)
3971	goto error;
3972
3973	/* Bandwidth setting done */
3974
3975	#if 0
3976	status = dvbt_set_frequency_shift(demod, channel, tuner_offset);
3977	if (status < 0)
3978	goto error;
3979	#endif
3980	status = set_frequency_shifter(state, intermediate_freqk_hz,
3981	tuner_freq_offset, is_dtv: true);
3982	if (status < 0)
3983	goto error;
3984
3985	/*== start SC, write channel settings to SC ==========================*/
3986
3987	/* Activate SCU to enable SCU commands */
3988	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3989	if (status < 0)
3990	goto error;
3991
3992	/* Enable SC after setting all other parameters */
3993	status = write16(state, OFDM_SC_COMM_STATE__A, data: 0);
3994	if (status < 0)
3995	goto error;
3996	status = write16(state, OFDM_SC_COMM_EXEC__A, data: 1);
3997	if (status < 0)
3998	goto error;
3999
4000
4001	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
4002	| SCU_RAM_COMMAND_CMD_DEMOD_START,
4003	parameter_len: 0, NULL, result_len: 1, result: &cmd_result);
4004	if (status < 0)
4005	goto error;
4006
4007	/* Write SC parameter registers, set all AUTO flags in operation mode */
4008	param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4009	OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4010	OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4011	OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4012	OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4013	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4014	subcmd: 0, param0: transmission_params, param1, param2: 0, param3: 0, param4: 0);
4015	if (status < 0)
4016	goto error;
4017
4018	if (!state->m_drxk_a3_rom_code)
4019	status = dvbt_ctrl_set_sqi_speed(state, speed: &state->m_sqi_speed);
4020	error:
4021	if (status < 0)
4022	pr_err("Error %d on %s\n", status, __func__);
4023
4024	return status;
4025	}
4026
4027
4028	/*============================================================================*/
4029
4030	/*
4031	* \brief Retrieve lock status .
4032	* \param demod Pointer to demodulator instance.
4033	* \param lockStat Pointer to lock status structure.
4034	* \return DRXStatus_t.
4035	*
4036	*/
4037	static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)
4038	{
4039	int status;
4040	const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4041	OFDM_SC_RA_RAM_LOCK_FEC__M);
4042	const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4043	const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4044
4045	u16 sc_ra_ram_lock = 0;
4046	u16 sc_comm_exec = 0;
4047
4048	dprintk(1, "\n");
4049
4050	*p_lock_status = NOT_LOCKED;
4051	/* driver 0.9.0 */
4052	/* Check if SC is running */
4053	status = read16(state, OFDM_SC_COMM_EXEC__A, data: &sc_comm_exec);
4054	if (status < 0)
4055	goto end;
4056	if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP)
4057	goto end;
4058
4059	status = read16(state, OFDM_SC_RA_RAM_LOCK__A, data: &sc_ra_ram_lock);
4060	if (status < 0)
4061	goto end;
4062
4063	if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask)
4064	*p_lock_status = MPEG_LOCK;
4065	else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask)
4066	*p_lock_status = FEC_LOCK;
4067	else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask)
4068	*p_lock_status = DEMOD_LOCK;
4069	else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4070	*p_lock_status = NEVER_LOCK;
4071	end:
4072	if (status < 0)
4073	pr_err("Error %d on %s\n", status, __func__);
4074
4075	return status;
4076	}
4077
4078	static int power_up_qam(struct drxk_state *state)
4079	{
4080	enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
4081	int status;
4082
4083	dprintk(1, "\n");
4084	status = ctrl_power_mode(state, mode: &power_mode);
4085	if (status < 0)
4086	pr_err("Error %d on %s\n", status, __func__);
4087
4088	return status;
4089	}
4090
4091
4092	/* Power Down QAM */
4093	static int power_down_qam(struct drxk_state *state)
4094	{
4095	u16 data = 0;
4096	u16 cmd_result;
4097	int status = 0;
4098
4099	dprintk(1, "\n");
4100	status = read16(state, SCU_COMM_EXEC__A, data: &data);
4101	if (status < 0)
4102	goto error;
4103	if (data == SCU_COMM_EXEC_ACTIVE) {
4104	/*
4105	STOP demodulator
4106	QAM and HW blocks
4107	*/
4108	/* stop all comstate->m_exec */
4109	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4110	if (status < 0)
4111	goto error;
4112	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
4113	| SCU_RAM_COMMAND_CMD_DEMOD_STOP,
4114	parameter_len: 0, NULL, result_len: 1, result: &cmd_result);
4115	if (status < 0)
4116	goto error;
4117	}
4118	/* powerdown AFE */
4119	status = set_iqm_af(state, active: false);
4120
4121	error:
4122	if (status < 0)
4123	pr_err("Error %d on %s\n", status, __func__);
4124
4125	return status;
4126	}
4127
4128	/*============================================================================*/
4129
4130	/*
4131	* \brief Setup of the QAM Measurement intervals for signal quality
4132	* \param demod instance of demod.
4133	* \param modulation current modulation.
4134	* \return DRXStatus_t.
4135	*
4136	* NOTE:
4137	* Take into account that for certain settings the errorcounters can overflow.
4138	* The implementation does not check this.
4139	*
4140	*/
4141	static int set_qam_measurement(struct drxk_state *state,
4142	enum e_drxk_constellation modulation,
4143	u32 symbol_rate)
4144	{
4145	u32 fec_bits_desired = 0; /* BER accounting period */
4146	u32 fec_rs_period_total = 0; /* Total period */
4147	u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */
4148	u16 fec_rs_period = 0; /* Value for corresponding I2C register */
4149	int status = 0;
4150
4151	dprintk(1, "\n");
4152
4153	fec_rs_prescale = 1;
4154	/* fec_bits_desired = symbol_rate [kHz] *
4155	FrameLenght [ms] *
4156	(modulation + 1) *
4157	SyncLoss (== 1) *
4158	ViterbiLoss (==1)
4159	*/
4160	switch (modulation) {
4161	case DRX_CONSTELLATION_QAM16:
4162	fec_bits_desired = 4 * symbol_rate;
4163	break;
4164	case DRX_CONSTELLATION_QAM32:
4165	fec_bits_desired = 5 * symbol_rate;
4166	break;
4167	case DRX_CONSTELLATION_QAM64:
4168	fec_bits_desired = 6 * symbol_rate;
4169	break;
4170	case DRX_CONSTELLATION_QAM128:
4171	fec_bits_desired = 7 * symbol_rate;
4172	break;
4173	case DRX_CONSTELLATION_QAM256:
4174	fec_bits_desired = 8 * symbol_rate;
4175	break;
4176	default:
4177	status = -EINVAL;
4178	}
4179	if (status < 0)
4180	goto error;
4181
4182	fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */
4183	fec_bits_desired *= 500; /* meas. period [ms] */
4184
4185	/* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4186	/* fec_rs_period_total = fec_bits_desired / 1632 */
4187	fec_rs_period_total = (fec_bits_desired / 1632UL) + 1; /* roughly ceil */
4188
4189	/* fec_rs_period_total = fec_rs_prescale * fec_rs_period */
4190	fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16);
4191	if (fec_rs_prescale == 0) {
4192	/* Divide by zero (though impossible) */
4193	status = -EINVAL;
4194	if (status < 0)
4195	goto error;
4196	}
4197	fec_rs_period =
4198	((u16) fec_rs_period_total +
4199	(fec_rs_prescale >> 1)) / fec_rs_prescale;
4200
4201	/* write corresponding registers */
4202	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, data: fec_rs_period);
4203	if (status < 0)
4204	goto error;
4205	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
4206	data: fec_rs_prescale);
4207	if (status < 0)
4208	goto error;
4209	status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, data: fec_rs_period);
4210	error:
4211	if (status < 0)
4212	pr_err("Error %d on %s\n", status, __func__);
4213	return status;
4214	}
4215
4216	static int set_qam16(struct drxk_state *state)
4217	{
4218	int status = 0;
4219
4220	dprintk(1, "\n");
4221	/* QAM Equalizer Setup */
4222	/* Equalizer */
4223	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, data: 13517);
4224	if (status < 0)
4225	goto error;
4226	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, data: 13517);
4227	if (status < 0)
4228	goto error;
4229	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, data: 13517);
4230	if (status < 0)
4231	goto error;
4232	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, data: 13517);
4233	if (status < 0)
4234	goto error;
4235	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, data: 13517);
4236	if (status < 0)
4237	goto error;
4238	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, data: 13517);
4239	if (status < 0)
4240	goto error;
4241	/* Decision Feedback Equalizer */
4242	status = write16(state, QAM_DQ_QUAL_FUN0__A, data: 2);
4243	if (status < 0)
4244	goto error;
4245	status = write16(state, QAM_DQ_QUAL_FUN1__A, data: 2);
4246	if (status < 0)
4247	goto error;
4248	status = write16(state, QAM_DQ_QUAL_FUN2__A, data: 2);
4249	if (status < 0)
4250	goto error;
4251	status = write16(state, QAM_DQ_QUAL_FUN3__A, data: 2);
4252	if (status < 0)
4253	goto error;
4254	status = write16(state, QAM_DQ_QUAL_FUN4__A, data: 2);
4255	if (status < 0)
4256	goto error;
4257	status = write16(state, QAM_DQ_QUAL_FUN5__A, data: 0);
4258	if (status < 0)
4259	goto error;
4260
4261	status = write16(state, QAM_SY_SYNC_HWM__A, data: 5);
4262	if (status < 0)
4263	goto error;
4264	status = write16(state, QAM_SY_SYNC_AWM__A, data: 4);
4265	if (status < 0)
4266	goto error;
4267	status = write16(state, QAM_SY_SYNC_LWM__A, data: 3);
4268	if (status < 0)
4269	goto error;
4270
4271	/* QAM Slicer Settings */
4272	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4273	DRXK_QAM_SL_SIG_POWER_QAM16);
4274	if (status < 0)
4275	goto error;
4276
4277	/* QAM Loop Controller Coeficients */
4278	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, data: 15);
4279	if (status < 0)
4280	goto error;
4281	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, data: 40);
4282	if (status < 0)
4283	goto error;
4284	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, data: 12);
4285	if (status < 0)
4286	goto error;
4287	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, data: 24);
4288	if (status < 0)
4289	goto error;
4290	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, data: 24);
4291	if (status < 0)
4292	goto error;
4293	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, data: 12);
4294	if (status < 0)
4295	goto error;
4296	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, data: 16);
4297	if (status < 0)
4298	goto error;
4299	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, data: 16);
4300	if (status < 0)
4301	goto error;
4302
4303	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, data: 5);
4304	if (status < 0)
4305	goto error;
4306	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, data: 20);
4307	if (status < 0)
4308	goto error;
4309	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, data: 80);
4310	if (status < 0)
4311	goto error;
4312	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, data: 5);
4313	if (status < 0)
4314	goto error;
4315	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, data: 20);
4316	if (status < 0)
4317	goto error;
4318	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, data: 50);
4319	if (status < 0)
4320	goto error;
4321	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, data: 16);
4322	if (status < 0)
4323	goto error;
4324	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, data: 16);
4325	if (status < 0)
4326	goto error;
4327	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, data: 32);
4328	if (status < 0)
4329	goto error;
4330	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, data: 5);
4331	if (status < 0)
4332	goto error;
4333	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, data: 10);
4334	if (status < 0)
4335	goto error;
4336	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, data: 10);
4337	if (status < 0)
4338	goto error;
4339
4340
4341	/* QAM State Machine (FSM) Thresholds */
4342
4343	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, data: 140);
4344	if (status < 0)
4345	goto error;
4346	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, data: 50);
4347	if (status < 0)
4348	goto error;
4349	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, data: 95);
4350	if (status < 0)
4351	goto error;
4352	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, data: 120);
4353	if (status < 0)
4354	goto error;
4355	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, data: 230);
4356	if (status < 0)
4357	goto error;
4358	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, data: 105);
4359	if (status < 0)
4360	goto error;
4361
4362	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, data: 40);
4363	if (status < 0)
4364	goto error;
4365	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, data: 4);
4366	if (status < 0)
4367	goto error;
4368	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, data: 24);
4369	if (status < 0)
4370	goto error;
4371
4372
4373	/* QAM FSM Tracking Parameters */
4374
4375	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, data: (u16) 16);
4376	if (status < 0)
4377	goto error;
4378	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, data: (u16) 220);
4379	if (status < 0)
4380	goto error;
4381	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, data: (u16) 25);
4382	if (status < 0)
4383	goto error;
4384	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, data: (u16) 6);
4385	if (status < 0)
4386	goto error;
4387	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, data: (u16) -24);
4388	if (status < 0)
4389	goto error;
4390	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, data: (u16) -65);
4391	if (status < 0)
4392	goto error;
4393	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, data: (u16) -127);
4394	if (status < 0)
4395	goto error;
4396
4397	error:
4398	if (status < 0)
4399	pr_err("Error %d on %s\n", status, __func__);
4400	return status;
4401	}
4402
4403	/*============================================================================*/
4404
4405	/*
4406	* \brief QAM32 specific setup
4407	* \param demod instance of demod.
4408	* \return DRXStatus_t.
4409	*/
4410	static int set_qam32(struct drxk_state *state)
4411	{
4412	int status = 0;
4413
4414	dprintk(1, "\n");
4415
4416	/* QAM Equalizer Setup */
4417	/* Equalizer */
4418	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, data: 6707);
4419	if (status < 0)
4420	goto error;
4421	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, data: 6707);
4422	if (status < 0)
4423	goto error;
4424	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, data: 6707);
4425	if (status < 0)
4426	goto error;
4427	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, data: 6707);
4428	if (status < 0)
4429	goto error;
4430	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, data: 6707);
4431	if (status < 0)
4432	goto error;
4433	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, data: 6707);
4434	if (status < 0)
4435	goto error;
4436
4437	/* Decision Feedback Equalizer */
4438	status = write16(state, QAM_DQ_QUAL_FUN0__A, data: 3);
4439	if (status < 0)
4440	goto error;
4441	status = write16(state, QAM_DQ_QUAL_FUN1__A, data: 3);
4442	if (status < 0)
4443	goto error;
4444	status = write16(state, QAM_DQ_QUAL_FUN2__A, data: 3);
4445	if (status < 0)
4446	goto error;
4447	status = write16(state, QAM_DQ_QUAL_FUN3__A, data: 3);
4448	if (status < 0)
4449	goto error;
4450	status = write16(state, QAM_DQ_QUAL_FUN4__A, data: 3);
4451	if (status < 0)
4452	goto error;
4453	status = write16(state, QAM_DQ_QUAL_FUN5__A, data: 0);
4454	if (status < 0)
4455	goto error;
4456
4457	status = write16(state, QAM_SY_SYNC_HWM__A, data: 6);
4458	if (status < 0)
4459	goto error;
4460	status = write16(state, QAM_SY_SYNC_AWM__A, data: 5);
4461	if (status < 0)
4462	goto error;
4463	status = write16(state, QAM_SY_SYNC_LWM__A, data: 3);
4464	if (status < 0)
4465	goto error;
4466
4467	/* QAM Slicer Settings */
4468
4469	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4470	DRXK_QAM_SL_SIG_POWER_QAM32);
4471	if (status < 0)
4472	goto error;
4473
4474
4475	/* QAM Loop Controller Coeficients */
4476
4477	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, data: 15);
4478	if (status < 0)
4479	goto error;
4480	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, data: 40);
4481	if (status < 0)
4482	goto error;
4483	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, data: 12);
4484	if (status < 0)
4485	goto error;
4486	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, data: 24);
4487	if (status < 0)
4488	goto error;
4489	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, data: 24);
4490	if (status < 0)
4491	goto error;
4492	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, data: 12);
4493	if (status < 0)
4494	goto error;
4495	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, data: 16);
4496	if (status < 0)
4497	goto error;
4498	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, data: 16);
4499	if (status < 0)
4500	goto error;
4501
4502	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, data: 5);
4503	if (status < 0)
4504	goto error;
4505	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, data: 20);
4506	if (status < 0)
4507	goto error;
4508	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, data: 80);
4509	if (status < 0)
4510	goto error;
4511	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, data: 5);
4512	if (status < 0)
4513	goto error;
4514	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, data: 20);
4515	if (status < 0)
4516	goto error;
4517	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, data: 50);
4518	if (status < 0)
4519	goto error;
4520	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, data: 16);
4521	if (status < 0)
4522	goto error;
4523	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, data: 16);
4524	if (status < 0)
4525	goto error;
4526	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, data: 16);
4527	if (status < 0)
4528	goto error;
4529	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, data: 5);
4530	if (status < 0)
4531	goto error;
4532	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, data: 10);
4533	if (status < 0)
4534	goto error;
4535	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, data: 0);
4536	if (status < 0)
4537	goto error;
4538
4539
4540	/* QAM State Machine (FSM) Thresholds */
4541
4542	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, data: 90);
4543	if (status < 0)
4544	goto error;
4545	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, data: 50);
4546	if (status < 0)
4547	goto error;
4548	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, data: 80);
4549	if (status < 0)
4550	goto error;
4551	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, data: 100);
4552	if (status < 0)
4553	goto error;
4554	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, data: 170);
4555	if (status < 0)
4556	goto error;
4557	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, data: 100);
4558	if (status < 0)
4559	goto error;
4560
4561	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, data: 40);
4562	if (status < 0)
4563	goto error;
4564	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, data: 4);
4565	if (status < 0)
4566	goto error;
4567	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, data: 10);
4568	if (status < 0)
4569	goto error;
4570
4571
4572	/* QAM FSM Tracking Parameters */
4573
4574	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, data: (u16) 12);
4575	if (status < 0)
4576	goto error;
4577	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, data: (u16) 140);
4578	if (status < 0)
4579	goto error;
4580	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, data: (u16) -8);
4581	if (status < 0)
4582	goto error;
4583	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, data: (u16) -16);
4584	if (status < 0)
4585	goto error;
4586	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, data: (u16) -26);
4587	if (status < 0)
4588	goto error;
4589	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, data: (u16) -56);
4590	if (status < 0)
4591	goto error;
4592	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, data: (u16) -86);
4593	error:
4594	if (status < 0)
4595	pr_err("Error %d on %s\n", status, __func__);
4596	return status;
4597	}
4598
4599	/*============================================================================*/
4600
4601	/*
4602	* \brief QAM64 specific setup
4603	* \param demod instance of demod.
4604	* \return DRXStatus_t.
4605	*/
4606	static int set_qam64(struct drxk_state *state)
4607	{
4608	int status = 0;
4609
4610	dprintk(1, "\n");
4611	/* QAM Equalizer Setup */
4612	/* Equalizer */
4613	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, data: 13336);
4614	if (status < 0)
4615	goto error;
4616	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, data: 12618);
4617	if (status < 0)
4618	goto error;
4619	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, data: 11988);
4620	if (status < 0)
4621	goto error;
4622	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, data: 13809);
4623	if (status < 0)
4624	goto error;
4625	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, data: 13809);
4626	if (status < 0)
4627	goto error;
4628	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, data: 15609);
4629	if (status < 0)
4630	goto error;
4631
4632	/* Decision Feedback Equalizer */
4633	status = write16(state, QAM_DQ_QUAL_FUN0__A, data: 4);
4634	if (status < 0)
4635	goto error;
4636	status = write16(state, QAM_DQ_QUAL_FUN1__A, data: 4);
4637	if (status < 0)
4638	goto error;
4639	status = write16(state, QAM_DQ_QUAL_FUN2__A, data: 4);
4640	if (status < 0)
4641	goto error;
4642	status = write16(state, QAM_DQ_QUAL_FUN3__A, data: 4);
4643	if (status < 0)
4644	goto error;
4645	status = write16(state, QAM_DQ_QUAL_FUN4__A, data: 3);
4646	if (status < 0)
4647	goto error;
4648	status = write16(state, QAM_DQ_QUAL_FUN5__A, data: 0);
4649	if (status < 0)
4650	goto error;
4651
4652	status = write16(state, QAM_SY_SYNC_HWM__A, data: 5);
4653	if (status < 0)
4654	goto error;
4655	status = write16(state, QAM_SY_SYNC_AWM__A, data: 4);
4656	if (status < 0)
4657	goto error;
4658	status = write16(state, QAM_SY_SYNC_LWM__A, data: 3);
4659	if (status < 0)
4660	goto error;
4661
4662	/* QAM Slicer Settings */
4663	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4664	DRXK_QAM_SL_SIG_POWER_QAM64);
4665	if (status < 0)
4666	goto error;
4667
4668
4669	/* QAM Loop Controller Coeficients */
4670
4671	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, data: 15);
4672	if (status < 0)
4673	goto error;
4674	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, data: 40);
4675	if (status < 0)
4676	goto error;
4677	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, data: 12);
4678	if (status < 0)
4679	goto error;
4680	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, data: 24);
4681	if (status < 0)
4682	goto error;
4683	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, data: 24);
4684	if (status < 0)
4685	goto error;
4686	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, data: 12);
4687	if (status < 0)
4688	goto error;
4689	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, data: 16);
4690	if (status < 0)
4691	goto error;
4692	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, data: 16);
4693	if (status < 0)
4694	goto error;
4695
4696	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, data: 5);
4697	if (status < 0)
4698	goto error;
4699	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, data: 30);
4700	if (status < 0)
4701	goto error;
4702	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, data: 100);
4703	if (status < 0)
4704	goto error;
4705	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, data: 5);
4706	if (status < 0)
4707	goto error;
4708	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, data: 30);
4709	if (status < 0)
4710	goto error;
4711	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, data: 50);
4712	if (status < 0)
4713	goto error;
4714	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, data: 16);
4715	if (status < 0)
4716	goto error;
4717	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, data: 25);
4718	if (status < 0)
4719	goto error;
4720	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, data: 48);
4721	if (status < 0)
4722	goto error;
4723	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, data: 5);
4724	if (status < 0)
4725	goto error;
4726	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, data: 10);
4727	if (status < 0)
4728	goto error;
4729	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, data: 10);
4730	if (status < 0)
4731	goto error;
4732
4733
4734	/* QAM State Machine (FSM) Thresholds */
4735
4736	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, data: 100);
4737	if (status < 0)
4738	goto error;
4739	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, data: 60);
4740	if (status < 0)
4741	goto error;
4742	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, data: 80);
4743	if (status < 0)
4744	goto error;
4745	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, data: 110);
4746	if (status < 0)
4747	goto error;
4748	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, data: 200);
4749	if (status < 0)
4750	goto error;
4751	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, data: 95);
4752	if (status < 0)
4753	goto error;
4754
4755	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, data: 40);
4756	if (status < 0)
4757	goto error;
4758	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, data: 4);
4759	if (status < 0)
4760	goto error;
4761	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, data: 15);
4762	if (status < 0)
4763	goto error;
4764
4765
4766	/* QAM FSM Tracking Parameters */
4767
4768	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, data: (u16) 12);
4769	if (status < 0)
4770	goto error;
4771	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, data: (u16) 141);
4772	if (status < 0)
4773	goto error;
4774	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, data: (u16) 7);
4775	if (status < 0)
4776	goto error;
4777	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, data: (u16) 0);
4778	if (status < 0)
4779	goto error;
4780	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, data: (u16) -15);
4781	if (status < 0)
4782	goto error;
4783	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, data: (u16) -45);
4784	if (status < 0)
4785	goto error;
4786	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, data: (u16) -80);
4787	error:
4788	if (status < 0)
4789	pr_err("Error %d on %s\n", status, __func__);
4790
4791	return status;
4792	}
4793
4794	/*============================================================================*/
4795
4796	/*
4797	* \brief QAM128 specific setup
4798	* \param demod: instance of demod.
4799	* \return DRXStatus_t.
4800	*/
4801	static int set_qam128(struct drxk_state *state)
4802	{
4803	int status = 0;
4804
4805	dprintk(1, "\n");
4806	/* QAM Equalizer Setup */
4807	/* Equalizer */
4808	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, data: 6564);
4809	if (status < 0)
4810	goto error;
4811	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, data: 6598);
4812	if (status < 0)
4813	goto error;
4814	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, data: 6394);
4815	if (status < 0)
4816	goto error;
4817	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, data: 6409);
4818	if (status < 0)
4819	goto error;
4820	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, data: 6656);
4821	if (status < 0)
4822	goto error;
4823	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, data: 7238);
4824	if (status < 0)
4825	goto error;
4826
4827	/* Decision Feedback Equalizer */
4828	status = write16(state, QAM_DQ_QUAL_FUN0__A, data: 6);
4829	if (status < 0)
4830	goto error;
4831	status = write16(state, QAM_DQ_QUAL_FUN1__A, data: 6);
4832	if (status < 0)
4833	goto error;
4834	status = write16(state, QAM_DQ_QUAL_FUN2__A, data: 6);
4835	if (status < 0)
4836	goto error;
4837	status = write16(state, QAM_DQ_QUAL_FUN3__A, data: 6);
4838	if (status < 0)
4839	goto error;
4840	status = write16(state, QAM_DQ_QUAL_FUN4__A, data: 5);
4841	if (status < 0)
4842	goto error;
4843	status = write16(state, QAM_DQ_QUAL_FUN5__A, data: 0);
4844	if (status < 0)
4845	goto error;
4846
4847	status = write16(state, QAM_SY_SYNC_HWM__A, data: 6);
4848	if (status < 0)
4849	goto error;
4850	status = write16(state, QAM_SY_SYNC_AWM__A, data: 5);
4851	if (status < 0)
4852	goto error;
4853	status = write16(state, QAM_SY_SYNC_LWM__A, data: 3);
4854	if (status < 0)
4855	goto error;
4856
4857
4858	/* QAM Slicer Settings */
4859
4860	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4861	DRXK_QAM_SL_SIG_POWER_QAM128);
4862	if (status < 0)
4863	goto error;
4864
4865
4866	/* QAM Loop Controller Coeficients */
4867
4868	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, data: 15);
4869	if (status < 0)
4870	goto error;
4871	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, data: 40);
4872	if (status < 0)
4873	goto error;
4874	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, data: 12);
4875	if (status < 0)
4876	goto error;
4877	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, data: 24);
4878	if (status < 0)
4879	goto error;
4880	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, data: 24);
4881	if (status < 0)
4882	goto error;
4883	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, data: 12);
4884	if (status < 0)
4885	goto error;
4886	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, data: 16);
4887	if (status < 0)
4888	goto error;
4889	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, data: 16);
4890	if (status < 0)
4891	goto error;
4892
4893	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, data: 5);
4894	if (status < 0)
4895	goto error;
4896	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, data: 40);
4897	if (status < 0)
4898	goto error;
4899	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, data: 120);
4900	if (status < 0)
4901	goto error;
4902	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, data: 5);
4903	if (status < 0)
4904	goto error;
4905	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, data: 40);
4906	if (status < 0)
4907	goto error;
4908	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, data: 60);
4909	if (status < 0)
4910	goto error;
4911	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, data: 16);
4912	if (status < 0)
4913	goto error;
4914	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, data: 25);
4915	if (status < 0)
4916	goto error;
4917	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, data: 64);
4918	if (status < 0)
4919	goto error;
4920	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, data: 5);
4921	if (status < 0)
4922	goto error;
4923	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, data: 10);
4924	if (status < 0)
4925	goto error;
4926	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, data: 0);
4927	if (status < 0)
4928	goto error;
4929
4930
4931	/* QAM State Machine (FSM) Thresholds */
4932
4933	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, data: 50);
4934	if (status < 0)
4935	goto error;
4936	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, data: 60);
4937	if (status < 0)
4938	goto error;
4939	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, data: 80);
4940	if (status < 0)
4941	goto error;
4942	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, data: 100);
4943	if (status < 0)
4944	goto error;
4945	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, data: 140);
4946	if (status < 0)
4947	goto error;
4948	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, data: 100);
4949	if (status < 0)
4950	goto error;
4951
4952	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, data: 40);
4953	if (status < 0)
4954	goto error;
4955	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, data: 5);
4956	if (status < 0)
4957	goto error;
4958
4959	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, data: 12);
4960	if (status < 0)
4961	goto error;
4962
4963	/* QAM FSM Tracking Parameters */
4964
4965	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, data: (u16) 8);
4966	if (status < 0)
4967	goto error;
4968	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, data: (u16) 65);
4969	if (status < 0)
4970	goto error;
4971	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, data: (u16) 5);
4972	if (status < 0)
4973	goto error;
4974	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, data: (u16) 3);
4975	if (status < 0)
4976	goto error;
4977	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, data: (u16) -1);
4978	if (status < 0)
4979	goto error;
4980	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, data: (u16) -12);
4981	if (status < 0)
4982	goto error;
4983	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, data: (u16) -23);
4984	error:
4985	if (status < 0)
4986	pr_err("Error %d on %s\n", status, __func__);
4987
4988	return status;
4989	}
4990
4991	/*============================================================================*/
4992
4993	/*
4994	* \brief QAM256 specific setup
4995	* \param demod: instance of demod.
4996	* \return DRXStatus_t.
4997	*/
4998	static int set_qam256(struct drxk_state *state)
4999	{
5000	int status = 0;
5001
5002	dprintk(1, "\n");
5003	/* QAM Equalizer Setup */
5004	/* Equalizer */
5005	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, data: 11502);
5006	if (status < 0)
5007	goto error;
5008	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, data: 12084);
5009	if (status < 0)
5010	goto error;
5011	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, data: 12543);
5012	if (status < 0)
5013	goto error;
5014	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, data: 12931);
5015	if (status < 0)
5016	goto error;
5017	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, data: 13629);
5018	if (status < 0)
5019	goto error;
5020	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, data: 15385);
5021	if (status < 0)
5022	goto error;
5023
5024	/* Decision Feedback Equalizer */
5025	status = write16(state, QAM_DQ_QUAL_FUN0__A, data: 8);
5026	if (status < 0)
5027	goto error;
5028	status = write16(state, QAM_DQ_QUAL_FUN1__A, data: 8);
5029	if (status < 0)
5030	goto error;
5031	status = write16(state, QAM_DQ_QUAL_FUN2__A, data: 8);
5032	if (status < 0)
5033	goto error;
5034	status = write16(state, QAM_DQ_QUAL_FUN3__A, data: 8);
5035	if (status < 0)
5036	goto error;
5037	status = write16(state, QAM_DQ_QUAL_FUN4__A, data: 6);
5038	if (status < 0)
5039	goto error;
5040	status = write16(state, QAM_DQ_QUAL_FUN5__A, data: 0);
5041	if (status < 0)
5042	goto error;
5043
5044	status = write16(state, QAM_SY_SYNC_HWM__A, data: 5);
5045	if (status < 0)
5046	goto error;
5047	status = write16(state, QAM_SY_SYNC_AWM__A, data: 4);
5048	if (status < 0)
5049	goto error;
5050	status = write16(state, QAM_SY_SYNC_LWM__A, data: 3);
5051	if (status < 0)
5052	goto error;
5053
5054	/* QAM Slicer Settings */
5055
5056	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
5057	DRXK_QAM_SL_SIG_POWER_QAM256);
5058	if (status < 0)
5059	goto error;
5060
5061
5062	/* QAM Loop Controller Coeficients */
5063
5064	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, data: 15);
5065	if (status < 0)
5066	goto error;
5067	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, data: 40);
5068	if (status < 0)
5069	goto error;
5070	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, data: 12);
5071	if (status < 0)
5072	goto error;
5073	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, data: 24);
5074	if (status < 0)
5075	goto error;
5076	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, data: 24);
5077	if (status < 0)
5078	goto error;
5079	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, data: 12);
5080	if (status < 0)
5081	goto error;
5082	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, data: 16);
5083	if (status < 0)
5084	goto error;
5085	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, data: 16);
5086	if (status < 0)
5087	goto error;
5088
5089	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, data: 5);
5090	if (status < 0)
5091	goto error;
5092	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, data: 50);
5093	if (status < 0)
5094	goto error;
5095	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, data: 250);
5096	if (status < 0)
5097	goto error;
5098	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, data: 5);
5099	if (status < 0)
5100	goto error;
5101	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, data: 50);
5102	if (status < 0)
5103	goto error;
5104	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, data: 125);
5105	if (status < 0)
5106	goto error;
5107	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, data: 16);
5108	if (status < 0)
5109	goto error;
5110	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, data: 25);
5111	if (status < 0)
5112	goto error;
5113	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, data: 48);
5114	if (status < 0)
5115	goto error;
5116	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, data: 5);
5117	if (status < 0)
5118	goto error;
5119	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, data: 10);
5120	if (status < 0)
5121	goto error;
5122	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, data: 10);
5123	if (status < 0)
5124	goto error;
5125
5126
5127	/* QAM State Machine (FSM) Thresholds */
5128
5129	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, data: 50);
5130	if (status < 0)
5131	goto error;
5132	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, data: 60);
5133	if (status < 0)
5134	goto error;
5135	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, data: 80);
5136	if (status < 0)
5137	goto error;
5138	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, data: 100);
5139	if (status < 0)
5140	goto error;
5141	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, data: 150);
5142	if (status < 0)
5143	goto error;
5144	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, data: 110);
5145	if (status < 0)
5146	goto error;
5147
5148	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, data: 40);
5149	if (status < 0)
5150	goto error;
5151	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, data: 4);
5152	if (status < 0)
5153	goto error;
5154	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, data: 12);
5155	if (status < 0)
5156	goto error;
5157
5158
5159	/* QAM FSM Tracking Parameters */
5160
5161	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, data: (u16) 8);
5162	if (status < 0)
5163	goto error;
5164	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, data: (u16) 74);
5165	if (status < 0)
5166	goto error;
5167	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, data: (u16) 18);
5168	if (status < 0)
5169	goto error;
5170	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, data: (u16) 13);
5171	if (status < 0)
5172	goto error;
5173	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, data: (u16) 7);
5174	if (status < 0)
5175	goto error;
5176	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, data: (u16) 0);
5177	if (status < 0)
5178	goto error;
5179	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, data: (u16) -8);
5180	error:
5181	if (status < 0)
5182	pr_err("Error %d on %s\n", status, __func__);
5183	return status;
5184	}
5185
5186
5187	/*============================================================================*/
5188	/*
5189	* \brief Reset QAM block.
5190	* \param demod: instance of demod.
5191	* \param channel: pointer to channel data.
5192	* \return DRXStatus_t.
5193	*/
5194	static int qam_reset_qam(struct drxk_state *state)
5195	{
5196	int status;
5197	u16 cmd_result;
5198
5199	dprintk(1, "\n");
5200	/* Stop QAM comstate->m_exec */
5201	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5202	if (status < 0)
5203	goto error;
5204
5205	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5206	| SCU_RAM_COMMAND_CMD_DEMOD_RESET,
5207	parameter_len: 0, NULL, result_len: 1, result: &cmd_result);
5208	error:
5209	if (status < 0)
5210	pr_err("Error %d on %s\n", status, __func__);
5211	return status;
5212	}
5213
5214	/*============================================================================*/
5215
5216	/*
5217	* \brief Set QAM symbolrate.
5218	* \param demod: instance of demod.
5219	* \param channel: pointer to channel data.
5220	* \return DRXStatus_t.
5221	*/
5222	static int qam_set_symbolrate(struct drxk_state *state)
5223	{
5224	u32 adc_frequency = 0;
5225	u32 symb_freq = 0;
5226	u32 iqm_rc_rate = 0;
5227	u16 ratesel = 0;
5228	u32 lc_symb_rate = 0;
5229	int status;
5230
5231	dprintk(1, "\n");
5232	/* Select & calculate correct IQM rate */
5233	adc_frequency = (state->m_sys_clock_freq * 1000) / 3;
5234	ratesel = 0;
5235	if (state->props.symbol_rate <= 1188750)
5236	ratesel = 3;
5237	else if (state->props.symbol_rate <= 2377500)
5238	ratesel = 2;
5239	else if (state->props.symbol_rate <= 4755000)
5240	ratesel = 1;
5241	status = write16(state, IQM_FD_RATESEL__A, data: ratesel);
5242	if (status < 0)
5243	goto error;
5244
5245	/*
5246	IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5247	*/
5248	symb_freq = state->props.symbol_rate * (1 << ratesel);
5249	if (symb_freq == 0) {
5250	/* Divide by zero */
5251	status = -EINVAL;
5252	goto error;
5253	}
5254	iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) +
5255	(Frac28a(a: (adc_frequency % symb_freq), c: symb_freq) >> 7) -
5256	(1 << 23);
5257	status = write32(state, IQM_RC_RATE_OFS_LO__A, data: iqm_rc_rate);
5258	if (status < 0)
5259	goto error;
5260	state->m_iqm_rc_rate = iqm_rc_rate;
5261	/*
5262	LcSymbFreq = round (.125 * symbolrate / adc_freq * (1<<15))
5263	*/
5264	symb_freq = state->props.symbol_rate;
5265	if (adc_frequency == 0) {
5266	/* Divide by zero */
5267	status = -EINVAL;
5268	goto error;
5269	}
5270	lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) +
5271	(Frac28a(a: (symb_freq % adc_frequency), c: adc_frequency) >>
5272	16);
5273	if (lc_symb_rate > 511)
5274	lc_symb_rate = 511;
5275	status = write16(state, QAM_LC_SYMBOL_FREQ__A, data: (u16) lc_symb_rate);
5276
5277	error:
5278	if (status < 0)
5279	pr_err("Error %d on %s\n", status, __func__);
5280	return status;
5281	}
5282
5283	/*============================================================================*/
5284
5285	/*
5286	* \brief Get QAM lock status.
5287	* \param demod: instance of demod.
5288	* \param channel: pointer to channel data.
5289	* \return DRXStatus_t.
5290	*/
5291
5292	static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)
5293	{
5294	int status;
5295	u16 result[2] = { 0, 0 };
5296
5297	dprintk(1, "\n");
5298	*p_lock_status = NOT_LOCKED;
5299	status = scu_command(state,
5300	SCU_RAM_COMMAND_STANDARD_QAM |
5301	SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, parameter_len: 0, NULL, result_len: 2,
5302	result);
5303	if (status < 0)
5304	pr_err("Error %d on %s\n", status, __func__);
5305
5306	if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5307	/* 0x0000 NOT LOCKED */
5308	} else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5309	/* 0x4000 DEMOD LOCKED */
5310	*p_lock_status = DEMOD_LOCK;
5311	} else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5312	/* 0x8000 DEMOD + FEC LOCKED (system lock) */
5313	*p_lock_status = MPEG_LOCK;
5314	} else {
5315	/* 0xC000 NEVER LOCKED */
5316	/* (system will never be able to lock to the signal) */
5317	/*
5318	* TODO: check this, intermediate & standard specific lock
5319	* states are not taken into account here
5320	*/
5321	*p_lock_status = NEVER_LOCK;
5322	}
5323	return status;
5324	}
5325
5326	#define QAM_MIRROR__M 0x03
5327	#define QAM_MIRROR_NORMAL 0x00
5328	#define QAM_MIRRORED 0x01
5329	#define QAM_MIRROR_AUTO_ON 0x02
5330	#define QAM_LOCKRANGE__M 0x10
5331	#define QAM_LOCKRANGE_NORMAL 0x10
5332
5333	static int qam_demodulator_command(struct drxk_state *state,
5334	int number_of_parameters)
5335	{
5336	int status;
5337	u16 cmd_result;
5338	u16 set_param_parameters[4] = { 0, 0, 0, 0 };
5339
5340	set_param_parameters[0] = state->m_constellation; /* modulation */
5341	set_param_parameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5342
5343	if (number_of_parameters == 2) {
5344	u16 set_env_parameters[1] = { 0 };
5345
5346	if (state->m_operation_mode == OM_QAM_ITU_C)
5347	set_env_parameters[0] = QAM_TOP_ANNEX_C;
5348	else
5349	set_env_parameters[0] = QAM_TOP_ANNEX_A;
5350
5351	status = scu_command(state,
5352	SCU_RAM_COMMAND_STANDARD_QAM
5353	| SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
5354	parameter_len: 1, parameter: set_env_parameters, result_len: 1, result: &cmd_result);
5355	if (status < 0)
5356	goto error;
5357
5358	status = scu_command(state,
5359	SCU_RAM_COMMAND_STANDARD_QAM
5360	| SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5361	parameter_len: number_of_parameters, parameter: set_param_parameters,
5362	result_len: 1, result: &cmd_result);
5363	} else if (number_of_parameters == 4) {
5364	if (state->m_operation_mode == OM_QAM_ITU_C)
5365	set_param_parameters[2] = QAM_TOP_ANNEX_C;
5366	else
5367	set_param_parameters[2] = QAM_TOP_ANNEX_A;
5368
5369	set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON);
5370	/* Env parameters */
5371	/* check for LOCKRANGE Extended */
5372	/* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */
5373
5374	status = scu_command(state,
5375	SCU_RAM_COMMAND_STANDARD_QAM
5376	| SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5377	parameter_len: number_of_parameters, parameter: set_param_parameters,
5378	result_len: 1, result: &cmd_result);
5379	} else {
5380	pr_warn("Unknown QAM demodulator parameter count %d\n",
5381	number_of_parameters);
5382	status = -EINVAL;
5383	}
5384
5385	error:
5386	if (status < 0)
5387	pr_warn("Warning %d on %s\n", status, __func__);
5388	return status;
5389	}
5390
5391	static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5392	s32 tuner_freq_offset)
5393	{
5394	int status;
5395	u16 cmd_result;
5396	int qam_demod_param_count = state->qam_demod_parameter_count;
5397
5398	dprintk(1, "\n");
5399	/*
5400	* STEP 1: reset demodulator
5401	* resets FEC DI and FEC RS
5402	* resets QAM block
5403	* resets SCU variables
5404	*/
5405	status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5406	if (status < 0)
5407	goto error;
5408	status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5409	if (status < 0)
5410	goto error;
5411	status = qam_reset_qam(state);
5412	if (status < 0)
5413	goto error;
5414
5415	/*
5416	* STEP 2: configure demodulator
5417	* -set params; resets IQM,QAM,FEC HW; initializes some
5418	* SCU variables
5419	*/
5420	status = qam_set_symbolrate(state);
5421	if (status < 0)
5422	goto error;
5423
5424	/* Set params */
5425	switch (state->props.modulation) {
5426	case QAM_256:
5427	state->m_constellation = DRX_CONSTELLATION_QAM256;
5428	break;
5429	case QAM_AUTO:
5430	case QAM_64:
5431	state->m_constellation = DRX_CONSTELLATION_QAM64;
5432	break;
5433	case QAM_16:
5434	state->m_constellation = DRX_CONSTELLATION_QAM16;
5435	break;
5436	case QAM_32:
5437	state->m_constellation = DRX_CONSTELLATION_QAM32;
5438	break;
5439	case QAM_128:
5440	state->m_constellation = DRX_CONSTELLATION_QAM128;
5441	break;
5442	default:
5443	status = -EINVAL;
5444	break;
5445	}
5446	if (status < 0)
5447	goto error;
5448
5449	/* Use the 4-parameter if it's requested or we're probing for
5450	* the correct command. */
5451	if (state->qam_demod_parameter_count == 4
5452	|| !state->qam_demod_parameter_count) {
5453	qam_demod_param_count = 4;
5454	status = qam_demodulator_command(state, number_of_parameters: qam_demod_param_count);
5455	}
5456
5457	/* Use the 2-parameter command if it was requested or if we're
5458	* probing for the correct command and the 4-parameter command
5459	* failed. */
5460	if (state->qam_demod_parameter_count == 2
5461	|| (!state->qam_demod_parameter_count && status < 0)) {
5462	qam_demod_param_count = 2;
5463	status = qam_demodulator_command(state, number_of_parameters: qam_demod_param_count);
5464	}
5465
5466	if (status < 0) {
5467	dprintk(1, "Could not set demodulator parameters.\n");
5468	dprintk(1,
5469	"Make sure qam_demod_parameter_count (%d) is correct for your firmware (%s).\n",
5470	state->qam_demod_parameter_count,
5471	state->microcode_name);
5472	goto error;
5473	} else if (!state->qam_demod_parameter_count) {
5474	dprintk(1,
5475	"Auto-probing the QAM command parameters was successful - using %d parameters.\n",
5476	qam_demod_param_count);
5477
5478	/*
5479	* One of our commands was successful. We don't need to
5480	* auto-probe anymore, now that we got the correct command.
5481	*/
5482	state->qam_demod_parameter_count = qam_demod_param_count;
5483	}
5484
5485	/*
5486	* STEP 3: enable the system in a mode where the ADC provides valid
5487	* signal setup modulation independent registers
5488	*/
5489	#if 0
5490	status = set_frequency(channel, tuner_freq_offset));
5491	if (status < 0)
5492	goto error;
5493	#endif
5494	status = set_frequency_shifter(state, intermediate_freqk_hz,
5495	tuner_freq_offset, is_dtv: true);
5496	if (status < 0)
5497	goto error;
5498
5499	/* Setup BER measurement */
5500	status = set_qam_measurement(state, modulation: state->m_constellation,
5501	symbol_rate: state->props.symbol_rate);
5502	if (status < 0)
5503	goto error;
5504
5505	/* Reset default values */
5506	status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5507	if (status < 0)
5508	goto error;
5509	status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5510	if (status < 0)
5511	goto error;
5512
5513	/* Reset default LC values */
5514	status = write16(state, QAM_LC_RATE_LIMIT__A, data: 3);
5515	if (status < 0)
5516	goto error;
5517	status = write16(state, QAM_LC_LPF_FACTORP__A, data: 4);
5518	if (status < 0)
5519	goto error;
5520	status = write16(state, QAM_LC_LPF_FACTORI__A, data: 4);
5521	if (status < 0)
5522	goto error;
5523	status = write16(state, QAM_LC_MODE__A, data: 7);
5524	if (status < 0)
5525	goto error;
5526
5527	status = write16(state, QAM_LC_QUAL_TAB0__A, data: 1);
5528	if (status < 0)
5529	goto error;
5530	status = write16(state, QAM_LC_QUAL_TAB1__A, data: 1);
5531	if (status < 0)
5532	goto error;
5533	status = write16(state, QAM_LC_QUAL_TAB2__A, data: 1);
5534	if (status < 0)
5535	goto error;
5536	status = write16(state, QAM_LC_QUAL_TAB3__A, data: 1);
5537	if (status < 0)
5538	goto error;
5539	status = write16(state, QAM_LC_QUAL_TAB4__A, data: 2);
5540	if (status < 0)
5541	goto error;
5542	status = write16(state, QAM_LC_QUAL_TAB5__A, data: 2);
5543	if (status < 0)
5544	goto error;
5545	status = write16(state, QAM_LC_QUAL_TAB6__A, data: 2);
5546	if (status < 0)
5547	goto error;
5548	status = write16(state, QAM_LC_QUAL_TAB8__A, data: 2);
5549	if (status < 0)
5550	goto error;
5551	status = write16(state, QAM_LC_QUAL_TAB9__A, data: 2);
5552	if (status < 0)
5553	goto error;
5554	status = write16(state, QAM_LC_QUAL_TAB10__A, data: 2);
5555	if (status < 0)
5556	goto error;
5557	status = write16(state, QAM_LC_QUAL_TAB12__A, data: 2);
5558	if (status < 0)
5559	goto error;
5560	status = write16(state, QAM_LC_QUAL_TAB15__A, data: 3);
5561	if (status < 0)
5562	goto error;
5563	status = write16(state, QAM_LC_QUAL_TAB16__A, data: 3);
5564	if (status < 0)
5565	goto error;
5566	status = write16(state, QAM_LC_QUAL_TAB20__A, data: 4);
5567	if (status < 0)
5568	goto error;
5569	status = write16(state, QAM_LC_QUAL_TAB25__A, data: 4);
5570	if (status < 0)
5571	goto error;
5572
5573	/* Mirroring, QAM-block starting point not inverted */
5574	status = write16(state, QAM_SY_SP_INV__A,
5575	QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5576	if (status < 0)
5577	goto error;
5578
5579	/* Halt SCU to enable safe non-atomic accesses */
5580	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5581	if (status < 0)
5582	goto error;
5583
5584	/* STEP 4: modulation specific setup */
5585	switch (state->props.modulation) {
5586	case QAM_16:
5587	status = set_qam16(state);
5588	break;
5589	case QAM_32:
5590	status = set_qam32(state);
5591	break;
5592	case QAM_AUTO:
5593	case QAM_64:
5594	status = set_qam64(state);
5595	break;
5596	case QAM_128:
5597	status = set_qam128(state);
5598	break;
5599	case QAM_256:
5600	status = set_qam256(state);
5601	break;
5602	default:
5603	status = -EINVAL;
5604	break;
5605	}
5606	if (status < 0)
5607	goto error;
5608
5609	/* Activate SCU to enable SCU commands */
5610	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5611	if (status < 0)
5612	goto error;
5613
5614	/* Re-configure MPEG output, requires knowledge of channel bitrate */
5615	/* extAttr->currentChannel.modulation = channel->modulation; */
5616	/* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5617	status = mpegts_dto_setup(state, o_mode: state->m_operation_mode);
5618	if (status < 0)
5619	goto error;
5620
5621	/* start processes */
5622	status = mpegts_start(state);
5623	if (status < 0)
5624	goto error;
5625	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5626	if (status < 0)
5627	goto error;
5628	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5629	if (status < 0)
5630	goto error;
5631	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5632	if (status < 0)
5633	goto error;
5634
5635	/* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5636	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5637	| SCU_RAM_COMMAND_CMD_DEMOD_START,
5638	parameter_len: 0, NULL, result_len: 1, result: &cmd_result);
5639	if (status < 0)
5640	goto error;
5641
5642	/* update global DRXK data container */
5643	/*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5644
5645	error:
5646	if (status < 0)
5647	pr_err("Error %d on %s\n", status, __func__);
5648	return status;
5649	}
5650
5651	static int set_qam_standard(struct drxk_state *state,
5652	enum operation_mode o_mode)
5653	{
5654	int status;
5655	#ifdef DRXK_QAM_TAPS
5656	#define DRXK_QAMA_TAPS_SELECT
5657	#include "drxk_filters.h"
5658	#undef DRXK_QAMA_TAPS_SELECT
5659	#endif
5660
5661	dprintk(1, "\n");
5662
5663	/* added antenna switch */
5664	switch_antenna_to_qam(state);
5665
5666	/* Ensure correct power-up mode */
5667	status = power_up_qam(state);
5668	if (status < 0)
5669	goto error;
5670	/* Reset QAM block */
5671	status = qam_reset_qam(state);
5672	if (status < 0)
5673	goto error;
5674
5675	/* Setup IQM */
5676
5677	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5678	if (status < 0)
5679	goto error;
5680	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5681	if (status < 0)
5682	goto error;
5683
5684	/* Upload IQM Channel Filter settings by
5685	boot loader from ROM table */
5686	switch (o_mode) {
5687	case OM_QAM_ITU_A:
5688	status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
5689	DRXK_BLCC_NR_ELEMENTS_TAPS,
5690	DRXK_BLC_TIMEOUT);
5691	break;
5692	case OM_QAM_ITU_C:
5693	status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
5694	DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5695	DRXK_BLDC_NR_ELEMENTS_TAPS,
5696	DRXK_BLC_TIMEOUT);
5697	if (status < 0)
5698	goto error;
5699	status = bl_direct_cmd(state,
5700	IQM_CF_TAP_IM0__A,
5701	DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5702	DRXK_BLDC_NR_ELEMENTS_TAPS,
5703	DRXK_BLC_TIMEOUT);
5704	break;
5705	default:
5706	status = -EINVAL;
5707	}
5708	if (status < 0)
5709	goto error;
5710
5711	status = write16(state, IQM_CF_OUT_ENA__A, data: 1 << IQM_CF_OUT_ENA_QAM__B);
5712	if (status < 0)
5713	goto error;
5714	status = write16(state, IQM_CF_SYMMETRIC__A, data: 0);
5715	if (status < 0)
5716	goto error;
5717	status = write16(state, IQM_CF_MIDTAP__A,
5718	data: ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5719	if (status < 0)
5720	goto error;
5721
5722	status = write16(state, IQM_RC_STRETCH__A, data: 21);
5723	if (status < 0)
5724	goto error;
5725	status = write16(state, IQM_AF_CLP_LEN__A, data: 0);
5726	if (status < 0)
5727	goto error;
5728	status = write16(state, IQM_AF_CLP_TH__A, data: 448);
5729	if (status < 0)
5730	goto error;
5731	status = write16(state, IQM_AF_SNS_LEN__A, data: 0);
5732	if (status < 0)
5733	goto error;
5734	status = write16(state, IQM_CF_POW_MEAS_LEN__A, data: 0);
5735	if (status < 0)
5736	goto error;
5737
5738	status = write16(state, IQM_FS_ADJ_SEL__A, data: 1);
5739	if (status < 0)
5740	goto error;
5741	status = write16(state, IQM_RC_ADJ_SEL__A, data: 1);
5742	if (status < 0)
5743	goto error;
5744	status = write16(state, IQM_CF_ADJ_SEL__A, data: 1);
5745	if (status < 0)
5746	goto error;
5747	status = write16(state, IQM_AF_UPD_SEL__A, data: 0);
5748	if (status < 0)
5749	goto error;
5750
5751	/* IQM Impulse Noise Processing Unit */
5752	status = write16(state, IQM_CF_CLP_VAL__A, data: 500);
5753	if (status < 0)
5754	goto error;
5755	status = write16(state, IQM_CF_DATATH__A, data: 1000);
5756	if (status < 0)
5757	goto error;
5758	status = write16(state, IQM_CF_BYPASSDET__A, data: 1);
5759	if (status < 0)
5760	goto error;
5761	status = write16(state, IQM_CF_DET_LCT__A, data: 0);
5762	if (status < 0)
5763	goto error;
5764	status = write16(state, IQM_CF_WND_LEN__A, data: 1);
5765	if (status < 0)
5766	goto error;
5767	status = write16(state, IQM_CF_PKDTH__A, data: 1);
5768	if (status < 0)
5769	goto error;
5770	status = write16(state, IQM_AF_INC_BYPASS__A, data: 1);
5771	if (status < 0)
5772	goto error;
5773
5774	/* turn on IQMAF. Must be done before setAgc**() */
5775	status = set_iqm_af(state, active: true);
5776	if (status < 0)
5777	goto error;
5778	status = write16(state, IQM_AF_START_LOCK__A, data: 0x01);
5779	if (status < 0)
5780	goto error;
5781
5782	/* IQM will not be reset from here, sync ADC and update/init AGC */
5783	status = adc_synchronization(state);
5784	if (status < 0)
5785	goto error;
5786
5787	/* Set the FSM step period */
5788	status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, data: 2000);
5789	if (status < 0)
5790	goto error;
5791
5792	/* Halt SCU to enable safe non-atomic accesses */
5793	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5794	if (status < 0)
5795	goto error;
5796
5797	/* No more resets of the IQM, current standard correctly set =>
5798	now AGCs can be configured. */
5799
5800	status = init_agc(state, is_dtv: true);
5801	if (status < 0)
5802	goto error;
5803	status = set_pre_saw(state, p_pre_saw_cfg: &(state->m_qam_pre_saw_cfg));
5804	if (status < 0)
5805	goto error;
5806
5807	/* Configure AGC's */
5808	status = set_agc_rf(state, p_agc_cfg: &(state->m_qam_rf_agc_cfg), is_dtv: true);
5809	if (status < 0)
5810	goto error;
5811	status = set_agc_if(state, p_agc_cfg: &(state->m_qam_if_agc_cfg), is_dtv: true);
5812	if (status < 0)
5813	goto error;
5814
5815	/* Activate SCU to enable SCU commands */
5816	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5817	error:
5818	if (status < 0)
5819	pr_err("Error %d on %s\n", status, __func__);
5820	return status;
5821	}
5822
5823	static int write_gpio(struct drxk_state *state)
5824	{
5825	int status;
5826	u16 value = 0;
5827
5828	dprintk(1, "\n");
5829	/* stop lock indicator process */
5830	status = write16(state, SCU_RAM_GPIO__A,
5831	SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5832	if (status < 0)
5833	goto error;
5834
5835	/* Write magic word to enable pdr reg write */
5836	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5837	if (status < 0)
5838	goto error;
5839
5840	if (state->m_has_sawsw) {
5841	if (state->uio_mask & 0x0001) { /* UIO-1 */
5842	/* write to io pad configuration register - output mode */
5843	status = write16(state, SIO_PDR_SMA_TX_CFG__A,
5844	data: state->m_gpio_cfg);
5845	if (status < 0)
5846	goto error;
5847
5848	/* use corresponding bit in io data output registar */
5849	status = read16(state, SIO_PDR_UIO_OUT_LO__A, data: &value);
5850	if (status < 0)
5851	goto error;
5852	if ((state->m_gpio & 0x0001) == 0)
5853	value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5854	else
5855	value |= 0x8000; /* write one to 15th bit - 1st UIO */
5856	/* write back to io data output register */
5857	status = write16(state, SIO_PDR_UIO_OUT_LO__A, data: value);
5858	if (status < 0)
5859	goto error;
5860	}
5861	if (state->uio_mask & 0x0002) { /* UIO-2 */
5862	/* write to io pad configuration register - output mode */
5863	status = write16(state, SIO_PDR_SMA_RX_CFG__A,
5864	data: state->m_gpio_cfg);
5865	if (status < 0)
5866	goto error;
5867
5868	/* use corresponding bit in io data output registar */
5869	status = read16(state, SIO_PDR_UIO_OUT_LO__A, data: &value);
5870	if (status < 0)
5871	goto error;
5872	if ((state->m_gpio & 0x0002) == 0)
5873	value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5874	else
5875	value |= 0x4000; /* write one to 14th bit - 2st UIO */
5876	/* write back to io data output register */
5877	status = write16(state, SIO_PDR_UIO_OUT_LO__A, data: value);
5878	if (status < 0)
5879	goto error;
5880	}
5881	if (state->uio_mask & 0x0004) { /* UIO-3 */
5882	/* write to io pad configuration register - output mode */
5883	status = write16(state, SIO_PDR_GPIO_CFG__A,
5884	data: state->m_gpio_cfg);
5885	if (status < 0)
5886	goto error;
5887
5888	/* use corresponding bit in io data output registar */
5889	status = read16(state, SIO_PDR_UIO_OUT_LO__A, data: &value);
5890	if (status < 0)
5891	goto error;
5892	if ((state->m_gpio & 0x0004) == 0)
5893	value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5894	else
5895	value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
5896	/* write back to io data output register */
5897	status = write16(state, SIO_PDR_UIO_OUT_LO__A, data: value);
5898	if (status < 0)
5899	goto error;
5900	}
5901	}
5902	/* Write magic word to disable pdr reg write */
5903	status = write16(state, SIO_TOP_COMM_KEY__A, data: 0x0000);
5904	error:
5905	if (status < 0)
5906	pr_err("Error %d on %s\n", status, __func__);
5907	return status;
5908	}
5909
5910	static int switch_antenna_to_qam(struct drxk_state *state)
5911	{
5912	int status = 0;
5913	bool gpio_state;
5914
5915	dprintk(1, "\n");
5916
5917	if (!state->antenna_gpio)
5918	return 0;
5919
5920	gpio_state = state->m_gpio & state->antenna_gpio;
5921
5922	if (state->antenna_dvbt ^ gpio_state) {
5923	/* Antenna is on DVB-T mode. Switch */
5924	if (state->antenna_dvbt)
5925	state->m_gpio &= ~state->antenna_gpio;
5926	else
5927	state->m_gpio |= state->antenna_gpio;
5928	status = write_gpio(state);
5929	}
5930	if (status < 0)
5931	pr_err("Error %d on %s\n", status, __func__);
5932	return status;
5933	}
5934
5935	static int switch_antenna_to_dvbt(struct drxk_state *state)
5936	{
5937	int status = 0;
5938	bool gpio_state;
5939
5940	dprintk(1, "\n");
5941
5942	if (!state->antenna_gpio)
5943	return 0;
5944
5945	gpio_state = state->m_gpio & state->antenna_gpio;
5946
5947	if (!(state->antenna_dvbt ^ gpio_state)) {
5948	/* Antenna is on DVB-C mode. Switch */
5949	if (state->antenna_dvbt)
5950	state->m_gpio |= state->antenna_gpio;
5951	else
5952	state->m_gpio &= ~state->antenna_gpio;
5953	status = write_gpio(state);
5954	}
5955	if (status < 0)
5956	pr_err("Error %d on %s\n", status, __func__);
5957	return status;
5958	}
5959
5960
5961	static int power_down_device(struct drxk_state *state)
5962	{
5963	/* Power down to requested mode */
5964	/* Backup some register settings */
5965	/* Set pins with possible pull-ups connected to them in input mode */
5966	/* Analog power down */
5967	/* ADC power down */
5968	/* Power down device */
5969	int status;
5970
5971	dprintk(1, "\n");
5972	if (state->m_b_p_down_open_bridge) {
5973	/* Open I2C bridge before power down of DRXK */
5974	status = ConfigureI2CBridge(state, b_enable_bridge: true);
5975	if (status < 0)
5976	goto error;
5977	}
5978	/* driver 0.9.0 */
5979	status = dvbt_enable_ofdm_token_ring(state, enable: false);
5980	if (status < 0)
5981	goto error;
5982
5983	status = write16(state, SIO_CC_PWD_MODE__A,
5984	SIO_CC_PWD_MODE_LEVEL_CLOCK);
5985	if (status < 0)
5986	goto error;
5987	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5988	if (status < 0)
5989	goto error;
5990	state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5991	status = hi_cfg_command(state);
5992	error:
5993	if (status < 0)
5994	pr_err("Error %d on %s\n", status, __func__);
5995
5996	return status;
5997	}
5998
5999	static int init_drxk(struct drxk_state *state)
6000	{
6001	int status = 0, n = 0;
6002	enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
6003	u16 driver_version;
6004
6005	dprintk(1, "\n");
6006	if (state->m_drxk_state == DRXK_UNINITIALIZED) {
6007	drxk_i2c_lock(state);
6008	status = power_up_device(state);
6009	if (status < 0)
6010	goto error;
6011	status = drxx_open(state);
6012	if (status < 0)
6013	goto error;
6014	/* Soft reset of OFDM-, sys- and osc-clockdomain */
6015	status = write16(state, SIO_CC_SOFT_RST__A,
6016	SIO_CC_SOFT_RST_OFDM__M
6017	| SIO_CC_SOFT_RST_SYS__M
6018	| SIO_CC_SOFT_RST_OSC__M);
6019	if (status < 0)
6020	goto error;
6021	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6022	if (status < 0)
6023	goto error;
6024	/*
6025	* TODO is this needed? If yes, how much delay in
6026	* worst case scenario
6027	*/
6028	usleep_range(min: 1000, max: 2000);
6029	state->m_drxk_a3_patch_code = true;
6030	status = get_device_capabilities(state);
6031	if (status < 0)
6032	goto error;
6033
6034	/* Bridge delay, uses oscilator clock */
6035	/* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6036	/* SDA brdige delay */
6037	state->m_hi_cfg_bridge_delay =
6038	(u16) ((state->m_osc_clock_freq / 1000) *
6039	HI_I2C_BRIDGE_DELAY) / 1000;
6040	/* Clipping */
6041	if (state->m_hi_cfg_bridge_delay >
6042	SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6043	state->m_hi_cfg_bridge_delay =
6044	SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6045	}
6046	/* SCL bridge delay, same as SDA for now */
6047	state->m_hi_cfg_bridge_delay +=
6048	state->m_hi_cfg_bridge_delay <<
6049	SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6050
6051	status = init_hi(state);
6052	if (status < 0)
6053	goto error;
6054	/* disable various processes */
6055	#if NOA1ROM
6056	if (!(state->m_DRXK_A1_ROM_CODE)
6057	&& !(state->m_DRXK_A2_ROM_CODE))
6058	#endif
6059	{
6060	status = write16(state, SCU_RAM_GPIO__A,
6061	SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6062	if (status < 0)
6063	goto error;
6064	}
6065
6066	/* disable MPEG port */
6067	status = mpegts_disable(state);
6068	if (status < 0)
6069	goto error;
6070
6071	/* Stop AUD and SCU */
6072	status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6073	if (status < 0)
6074	goto error;
6075	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6076	if (status < 0)
6077	goto error;
6078
6079	/* enable token-ring bus through OFDM block for possible ucode upload */
6080	status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6081	SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6082	if (status < 0)
6083	goto error;
6084
6085	/* include boot loader section */
6086	status = write16(state, SIO_BL_COMM_EXEC__A,
6087	SIO_BL_COMM_EXEC_ACTIVE);
6088	if (status < 0)
6089	goto error;
6090	status = bl_chain_cmd(state, rom_offset: 0, nr_of_elements: 6, time_out: 100);
6091	if (status < 0)
6092	goto error;
6093
6094	if (state->fw) {
6095	status = download_microcode(state, p_mc_image: state->fw->data,
6096	length: state->fw->size);
6097	if (status < 0)
6098	goto error;
6099	}
6100
6101	/* disable token-ring bus through OFDM block for possible ucode upload */
6102	status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6103	SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6104	if (status < 0)
6105	goto error;
6106
6107	/* Run SCU for a little while to initialize microcode version numbers */
6108	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6109	if (status < 0)
6110	goto error;
6111	status = drxx_open(state);
6112	if (status < 0)
6113	goto error;
6114	/* added for test */
6115	msleep(msecs: 30);
6116
6117	power_mode = DRXK_POWER_DOWN_OFDM;
6118	status = ctrl_power_mode(state, mode: &power_mode);
6119	if (status < 0)
6120	goto error;
6121
6122	/* Stamp driver version number in SCU data RAM in BCD code
6123	Done to enable field application engineers to retrieve drxdriver version
6124	via I2C from SCU RAM.
6125	Not using SCU command interface for SCU register access since no
6126	microcode may be present.
6127	*/
6128	driver_version =
6129	(((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6130	(((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6131	((DRXK_VERSION_MAJOR % 10) << 4) +
6132	(DRXK_VERSION_MINOR % 10);
6133	status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
6134	data: driver_version);
6135	if (status < 0)
6136	goto error;
6137	driver_version =
6138	(((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6139	(((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6140	(((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6141	(DRXK_VERSION_PATCH % 10);
6142	status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
6143	data: driver_version);
6144	if (status < 0)
6145	goto error;
6146
6147	pr_info("DRXK driver version %d.%d.%d\n",
6148	DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6149	DRXK_VERSION_PATCH);
6150
6151	/*
6152	* Dirty fix of default values for ROM/PATCH microcode
6153	* Dirty because this fix makes it impossible to setup
6154	* suitable values before calling DRX_Open. This solution
6155	* requires changes to RF AGC speed to be done via the CTRL
6156	* function after calling DRX_Open
6157	*/
6158
6159	/* m_dvbt_rf_agc_cfg.speed = 3; */
6160
6161	/* Reset driver debug flags to 0 */
6162	status = write16(state, SCU_RAM_DRIVER_DEBUG__A, data: 0);
6163	if (status < 0)
6164	goto error;
6165	/* driver 0.9.0 */
6166	/* Setup FEC OC:
6167	NOTE: No more full FEC resets allowed afterwards!! */
6168	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6169	if (status < 0)
6170	goto error;
6171	/* MPEGTS functions are still the same */
6172	status = mpegts_dto_init(state);
6173	if (status < 0)
6174	goto error;
6175	status = mpegts_stop(state);
6176	if (status < 0)
6177	goto error;
6178	status = mpegts_configure_polarity(state);
6179	if (status < 0)
6180	goto error;
6181	status = mpegts_configure_pins(state, mpeg_enable: state->m_enable_mpeg_output);
6182	if (status < 0)
6183	goto error;
6184	/* added: configure GPIO */
6185	status = write_gpio(state);
6186	if (status < 0)
6187	goto error;
6188
6189	state->m_drxk_state = DRXK_STOPPED;
6190
6191	if (state->m_b_power_down) {
6192	status = power_down_device(state);
6193	if (status < 0)
6194	goto error;
6195	state->m_drxk_state = DRXK_POWERED_DOWN;
6196	} else
6197	state->m_drxk_state = DRXK_STOPPED;
6198
6199	/* Initialize the supported delivery systems */
6200	n = 0;
6201	if (state->m_has_dvbc) {
6202	state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6203	state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6204	strlcat(p: state->frontend.ops.info.name, q: " DVB-C",
6205	avail: sizeof(state->frontend.ops.info.name));
6206	}
6207	if (state->m_has_dvbt) {
6208	state->frontend.ops.delsys[n++] = SYS_DVBT;
6209	strlcat(p: state->frontend.ops.info.name, q: " DVB-T",
6210	avail: sizeof(state->frontend.ops.info.name));
6211	}
6212	drxk_i2c_unlock(state);
6213	}
6214	error:
6215	if (status < 0) {
6216	state->m_drxk_state = DRXK_NO_DEV;
6217	drxk_i2c_unlock(state);
6218	pr_err("Error %d on %s\n", status, __func__);
6219	}
6220
6221	return status;
6222	}
6223
6224	static void load_firmware_cb(const struct firmware *fw,
6225	void *context)
6226	{
6227	struct drxk_state *state = context;
6228
6229	dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded");
6230	if (!fw) {
6231	pr_err("Could not load firmware file %s.\n",
6232	state->microcode_name);
6233	pr_info("Copy %s to your hotplug directory!\n",
6234	state->microcode_name);
6235	state->microcode_name = NULL;
6236
6237	/*
6238	* As firmware is now load asynchronous, it is not possible
6239	* anymore to fail at frontend attach. We might silently
6240	* return here, and hope that the driver won't crash.
6241	* We might also change all DVB callbacks to return -ENODEV
6242	* if the device is not initialized.
6243	* As the DRX-K devices have their own internal firmware,
6244	* let's just hope that it will match a firmware revision
6245	* compatible with this driver and proceed.
6246	*/
6247	}
6248	state->fw = fw;
6249
6250	init_drxk(state);
6251	}
6252
6253	static void drxk_release(struct dvb_frontend *fe)
6254	{
6255	struct drxk_state *state = fe->demodulator_priv;
6256
6257	dprintk(1, "\n");
6258	release_firmware(fw: state->fw);
6259
6260	kfree(objp: state);
6261	}
6262
6263	static int drxk_sleep(struct dvb_frontend *fe)
6264	{
6265	struct drxk_state *state = fe->demodulator_priv;
6266
6267	dprintk(1, "\n");
6268
6269	if (state->m_drxk_state == DRXK_NO_DEV)
6270	return -ENODEV;
6271	if (state->m_drxk_state == DRXK_UNINITIALIZED)
6272	return 0;
6273
6274	shut_down(state);
6275	return 0;
6276	}
6277
6278	static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6279	{
6280	struct drxk_state *state = fe->demodulator_priv;
6281
6282	dprintk(1, ": %s\n", enable ? "enable" : "disable");
6283
6284	if (state->m_drxk_state == DRXK_NO_DEV)
6285	return -ENODEV;
6286
6287	return ConfigureI2CBridge(state, b_enable_bridge: enable ? true : false);
6288	}
6289
6290	static int drxk_set_parameters(struct dvb_frontend *fe)
6291	{
6292	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6293	u32 delsys = p->delivery_system, old_delsys;
6294	struct drxk_state *state = fe->demodulator_priv;
6295	u32 IF;
6296
6297	dprintk(1, "\n");
6298
6299	if (state->m_drxk_state == DRXK_NO_DEV)
6300	return -ENODEV;
6301
6302	if (state->m_drxk_state == DRXK_UNINITIALIZED)
6303	return -EAGAIN;
6304
6305	if (!fe->ops.tuner_ops.get_if_frequency) {
6306	pr_err("Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6307	return -EINVAL;
6308	}
6309
6310	if (fe->ops.i2c_gate_ctrl)
6311	fe->ops.i2c_gate_ctrl(fe, 1);
6312	if (fe->ops.tuner_ops.set_params)
6313	fe->ops.tuner_ops.set_params(fe);
6314	if (fe->ops.i2c_gate_ctrl)
6315	fe->ops.i2c_gate_ctrl(fe, 0);
6316
6317	old_delsys = state->props.delivery_system;
6318	state->props = *p;
6319
6320	if (old_delsys != delsys) {
6321	shut_down(state);
6322	switch (delsys) {
6323	case SYS_DVBC_ANNEX_A:
6324	case SYS_DVBC_ANNEX_C:
6325	if (!state->m_has_dvbc)
6326	return -EINVAL;
6327	state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?
6328	true : false;
6329	if (state->m_itut_annex_c)
6330	setoperation_mode(state, o_mode: OM_QAM_ITU_C);
6331	else
6332	setoperation_mode(state, o_mode: OM_QAM_ITU_A);
6333	break;
6334	case SYS_DVBT:
6335	if (!state->m_has_dvbt)
6336	return -EINVAL;
6337	setoperation_mode(state, o_mode: OM_DVBT);
6338	break;
6339	default:
6340	return -EINVAL;
6341	}
6342	}
6343
6344	fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6345	start(state, offset_freq: 0, intermediate_frequency: IF);
6346
6347	/* After set_frontend, stats aren't available */
6348	p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6349	p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6350	p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6351	p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6352	p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6353	p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6354	p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6355	p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6356
6357	/* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6358
6359	return 0;
6360	}
6361
6362	static int get_strength(struct drxk_state *state, u64 *strength)
6363	{
6364	int status;
6365	struct s_cfg_agc rf_agc, if_agc;
6366	u32 total_gain = 0;
6367	u32 atten = 0;
6368	u32 agc_range = 0;
6369	u16 scu_lvl = 0;
6370	u16 scu_coc = 0;
6371	/* FIXME: those are part of the tuner presets */
6372	u16 tuner_rf_gain = 50; /* Default value on az6007 driver */
6373	u16 tuner_if_gain = 40; /* Default value on az6007 driver */
6374
6375	*strength = 0;
6376
6377	if (is_dvbt(state)) {
6378	rf_agc = state->m_dvbt_rf_agc_cfg;
6379	if_agc = state->m_dvbt_if_agc_cfg;
6380	} else if (is_qam(state)) {
6381	rf_agc = state->m_qam_rf_agc_cfg;
6382	if_agc = state->m_qam_if_agc_cfg;
6383	} else {
6384	rf_agc = state->m_atv_rf_agc_cfg;
6385	if_agc = state->m_atv_if_agc_cfg;
6386	}
6387
6388	if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6389	/* SCU output_level */
6390	status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, data: &scu_lvl);
6391	if (status < 0)
6392	return status;
6393
6394	/* SCU c.o.c. */
6395	status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, data: &scu_coc);
6396	if (status < 0)
6397	return status;
6398
6399	if (((u32) scu_lvl + (u32) scu_coc) < 0xffff)
6400	rf_agc.output_level = scu_lvl + scu_coc;
6401	else
6402	rf_agc.output_level = 0xffff;
6403
6404	/* Take RF gain into account */
6405	total_gain += tuner_rf_gain;
6406
6407	/* clip output value */
6408	if (rf_agc.output_level < rf_agc.min_output_level)
6409	rf_agc.output_level = rf_agc.min_output_level;
6410	if (rf_agc.output_level > rf_agc.max_output_level)
6411	rf_agc.output_level = rf_agc.max_output_level;
6412
6413	agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level);
6414	if (agc_range > 0) {
6415	atten += 100UL *
6416	((u32)(tuner_rf_gain)) *
6417	((u32)(rf_agc.output_level - rf_agc.min_output_level))
6418	/ agc_range;
6419	}
6420	}
6421
6422	if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6423	status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6424	data: &if_agc.output_level);
6425	if (status < 0)
6426	return status;
6427
6428	status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6429	data: &if_agc.top);
6430	if (status < 0)
6431	return status;
6432
6433	/* Take IF gain into account */
6434	total_gain += (u32) tuner_if_gain;
6435
6436	/* clip output value */
6437	if (if_agc.output_level < if_agc.min_output_level)
6438	if_agc.output_level = if_agc.min_output_level;
6439	if (if_agc.output_level > if_agc.max_output_level)
6440	if_agc.output_level = if_agc.max_output_level;
6441
6442	agc_range = (u32)(if_agc.max_output_level - if_agc.min_output_level);
6443	if (agc_range > 0) {
6444	atten += 100UL *
6445	((u32)(tuner_if_gain)) *
6446	((u32)(if_agc.output_level - if_agc.min_output_level))
6447	/ agc_range;
6448	}
6449	}
6450
6451	/*
6452	* Convert to 0..65535 scale.
6453	* If it can't be measured (AGC is disabled), just show 100%.
6454	*/
6455	if (total_gain > 0)
6456	*strength = (65535UL * atten / total_gain / 100);
6457	else
6458	*strength = 65535;
6459
6460	return 0;
6461	}
6462
6463	static int drxk_get_stats(struct dvb_frontend *fe)
6464	{
6465	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6466	struct drxk_state *state = fe->demodulator_priv;
6467	int status;
6468	u32 stat;
6469	u16 reg16;
6470	u32 post_bit_count;
6471	u32 post_bit_err_count;
6472	u32 post_bit_error_scale;
6473	u32 pre_bit_err_count;
6474	u32 pre_bit_count;
6475	u32 pkt_count;
6476	u32 pkt_error_count;
6477	s32 cnr;
6478
6479	if (state->m_drxk_state == DRXK_NO_DEV)
6480	return -ENODEV;
6481	if (state->m_drxk_state == DRXK_UNINITIALIZED)
6482	return -EAGAIN;
6483
6484	/* get status */
6485	state->fe_status = 0;
6486	get_lock_status(state, p_lock_status: &stat);
6487	if (stat == MPEG_LOCK)
6488	state->fe_status |= 0x1f;
6489	if (stat == FEC_LOCK)
6490	state->fe_status |= 0x0f;
6491	if (stat == DEMOD_LOCK)
6492	state->fe_status |= 0x07;
6493
6494	/*
6495	* Estimate signal strength from AGC
6496	*/
6497	get_strength(state, strength: &c->strength.stat[0].uvalue);
6498	c->strength.stat[0].scale = FE_SCALE_RELATIVE;
6499
6500
6501	if (stat >= DEMOD_LOCK) {
6502	get_signal_to_noise(state, p_signal_to_noise: &cnr);
6503	c->cnr.stat[0].svalue = cnr * 100;
6504	c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
6505	} else {
6506	c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6507	}
6508
6509	if (stat < FEC_LOCK) {
6510	c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6511	c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6512	c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6513	c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6514	c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6515	c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6516	return 0;
6517	}
6518
6519	/* Get post BER */
6520
6521	/* BER measurement is valid if at least FEC lock is achieved */
6522
6523	/*
6524	* OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be
6525	* written to set nr of symbols or bits over which to measure
6526	* EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg().
6527	*/
6528
6529	/* Read registers for post/preViterbi BER calculation */
6530	status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, data: &reg16);
6531	if (status < 0)
6532	goto error;
6533	pre_bit_err_count = reg16;
6534
6535	status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , data: &reg16);
6536	if (status < 0)
6537	goto error;
6538	pre_bit_count = reg16;
6539
6540	/* Number of bit-errors */
6541	status = read16(state, FEC_RS_NR_BIT_ERRORS__A, data: &reg16);
6542	if (status < 0)
6543	goto error;
6544	post_bit_err_count = reg16;
6545
6546	status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, data: &reg16);
6547	if (status < 0)
6548	goto error;
6549	post_bit_error_scale = reg16;
6550
6551	status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, data: &reg16);
6552	if (status < 0)
6553	goto error;
6554	pkt_count = reg16;
6555
6556	status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, data: &reg16);
6557	if (status < 0)
6558	goto error;
6559	pkt_error_count = reg16;
6560	write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, data: 0);
6561
6562	post_bit_err_count *= post_bit_error_scale;
6563
6564	post_bit_count = pkt_count * 204 * 8;
6565
6566	/* Store the results */
6567	c->block_error.stat[0].scale = FE_SCALE_COUNTER;
6568	c->block_error.stat[0].uvalue += pkt_error_count;
6569	c->block_count.stat[0].scale = FE_SCALE_COUNTER;
6570	c->block_count.stat[0].uvalue += pkt_count;
6571
6572	c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6573	c->pre_bit_error.stat[0].uvalue += pre_bit_err_count;
6574	c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6575	c->pre_bit_count.stat[0].uvalue += pre_bit_count;
6576
6577	c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6578	c->post_bit_error.stat[0].uvalue += post_bit_err_count;
6579	c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6580	c->post_bit_count.stat[0].uvalue += post_bit_count;
6581
6582	error:
6583	return status;
6584	}
6585
6586
6587	static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status)
6588	{
6589	struct drxk_state *state = fe->demodulator_priv;
6590	int rc;
6591
6592	dprintk(1, "\n");
6593
6594	rc = drxk_get_stats(fe);
6595	if (rc < 0)
6596	return rc;
6597
6598	*status = state->fe_status;
6599
6600	return 0;
6601	}
6602
6603	static int drxk_read_signal_strength(struct dvb_frontend *fe,
6604	u16 *strength)
6605	{
6606	struct drxk_state *state = fe->demodulator_priv;
6607	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6608
6609	dprintk(1, "\n");
6610
6611	if (state->m_drxk_state == DRXK_NO_DEV)
6612	return -ENODEV;
6613	if (state->m_drxk_state == DRXK_UNINITIALIZED)
6614	return -EAGAIN;
6615
6616	*strength = c->strength.stat[0].uvalue;
6617	return 0;
6618	}
6619
6620	static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6621	{
6622	struct drxk_state *state = fe->demodulator_priv;
6623	s32 snr2;
6624
6625	dprintk(1, "\n");
6626
6627	if (state->m_drxk_state == DRXK_NO_DEV)
6628	return -ENODEV;
6629	if (state->m_drxk_state == DRXK_UNINITIALIZED)
6630	return -EAGAIN;
6631
6632	get_signal_to_noise(state, p_signal_to_noise: &snr2);
6633
6634	/* No negative SNR, clip to zero */
6635	if (snr2 < 0)
6636	snr2 = 0;
6637	*snr = snr2 & 0xffff;
6638	return 0;
6639	}
6640
6641	static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6642	{
6643	struct drxk_state *state = fe->demodulator_priv;
6644	u16 err = 0;
6645
6646	dprintk(1, "\n");
6647
6648	if (state->m_drxk_state == DRXK_NO_DEV)
6649	return -ENODEV;
6650	if (state->m_drxk_state == DRXK_UNINITIALIZED)
6651	return -EAGAIN;
6652
6653	dvbtqam_get_acc_pkt_err(state, packet_err: &err);
6654	*ucblocks = (u32) err;
6655	return 0;
6656	}
6657
6658	static int drxk_get_tune_settings(struct dvb_frontend *fe,
6659	struct dvb_frontend_tune_settings *sets)
6660	{
6661	struct drxk_state *state = fe->demodulator_priv;
6662	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6663
6664	dprintk(1, "\n");
6665
6666	if (state->m_drxk_state == DRXK_NO_DEV)
6667	return -ENODEV;
6668	if (state->m_drxk_state == DRXK_UNINITIALIZED)
6669	return -EAGAIN;
6670
6671	switch (p->delivery_system) {
6672	case SYS_DVBC_ANNEX_A:
6673	case SYS_DVBC_ANNEX_C:
6674	case SYS_DVBT:
6675	sets->min_delay_ms = 3000;
6676	sets->max_drift = 0;
6677	sets->step_size = 0;
6678	return 0;
6679	default:
6680	return -EINVAL;
6681	}
6682	}
6683
6684	static const struct dvb_frontend_ops drxk_ops = {
6685	/* .delsys will be filled dynamically */
6686	.info = {
6687	.name = "DRXK",
6688	.frequency_min_hz = 47 * MHz,
6689	.frequency_max_hz = 865 * MHz,
6690	/* For DVB-C */
6691	.symbol_rate_min = 870000,
6692	.symbol_rate_max = 11700000,
6693	/* For DVB-T */
6694	.frequency_stepsize_hz = 166667,
6695
6696	.caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6697	FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6698	FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6699	FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6700	FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6701	FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6702	},
6703
6704	.release = drxk_release,
6705	.sleep = drxk_sleep,
6706	.i2c_gate_ctrl = drxk_gate_ctrl,
6707
6708	.set_frontend = drxk_set_parameters,
6709	.get_tune_settings = drxk_get_tune_settings,
6710
6711	.read_status = drxk_read_status,
6712	.read_signal_strength = drxk_read_signal_strength,
6713	.read_snr = drxk_read_snr,
6714	.read_ucblocks = drxk_read_ucblocks,
6715	};
6716
6717	struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6718	struct i2c_adapter *i2c)
6719	{
6720	struct dtv_frontend_properties *p;
6721	struct drxk_state *state = NULL;
6722	u8 adr = config->adr;
6723	int status;
6724
6725	dprintk(1, "\n");
6726	state = kzalloc(size: sizeof(struct drxk_state), GFP_KERNEL);
6727	if (!state)
6728	return NULL;
6729
6730	state->i2c = i2c;
6731	state->demod_address = adr;
6732	state->single_master = config->single_master;
6733	state->microcode_name = config->microcode_name;
6734	state->qam_demod_parameter_count = config->qam_demod_parameter_count;
6735	state->no_i2c_bridge = config->no_i2c_bridge;
6736	state->antenna_gpio = config->antenna_gpio;
6737	state->antenna_dvbt = config->antenna_dvbt;
6738	state->m_chunk_size = config->chunk_size;
6739	state->enable_merr_cfg = config->enable_merr_cfg;
6740
6741	if (config->dynamic_clk) {
6742	state->m_dvbt_static_clk = false;
6743	state->m_dvbc_static_clk = false;
6744	} else {
6745	state->m_dvbt_static_clk = true;
6746	state->m_dvbc_static_clk = true;
6747	}
6748
6749
6750	if (config->mpeg_out_clk_strength)
6751	state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;
6752	else
6753	state->m_ts_clockk_strength = 0x06;
6754
6755	if (config->parallel_ts)
6756	state->m_enable_parallel = true;
6757	else
6758	state->m_enable_parallel = false;
6759
6760	/* NOTE: as more UIO bits will be used, add them to the mask */
6761	state->uio_mask = config->antenna_gpio;
6762
6763	/* Default gpio to DVB-C */
6764	if (!state->antenna_dvbt && state->antenna_gpio)
6765	state->m_gpio |= state->antenna_gpio;
6766	else
6767	state->m_gpio &= ~state->antenna_gpio;
6768
6769	mutex_init(&state->mutex);
6770
6771	memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6772	state->frontend.demodulator_priv = state;
6773
6774	init_state(state);
6775
6776	/* Load firmware and initialize DRX-K */
6777	if (state->microcode_name) {
6778	const struct firmware *fw = NULL;
6779
6780	status = request_firmware(fw: &fw, name: state->microcode_name,
6781	device: state->i2c->dev.parent);
6782	if (status < 0)
6783	fw = NULL;
6784	load_firmware_cb(fw, context: state);
6785	} else if (init_drxk(state) < 0)
6786	goto error;
6787
6788
6789	/* Initialize stats */
6790	p = &state->frontend.dtv_property_cache;
6791	p->strength.len = 1;
6792	p->cnr.len = 1;
6793	p->block_error.len = 1;
6794	p->block_count.len = 1;
6795	p->pre_bit_error.len = 1;
6796	p->pre_bit_count.len = 1;
6797	p->post_bit_error.len = 1;
6798	p->post_bit_count.len = 1;
6799
6800	p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6801	p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6802	p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6803	p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6804	p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6805	p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6806	p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6807	p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6808
6809	pr_info("frontend initialized.\n");
6810	return &state->frontend;
6811
6812	error:
6813	pr_err("not found\n");
6814	kfree(objp: state);
6815	return NULL;
6816	}
6817	EXPORT_SYMBOL_GPL(drxk_attach);
6818
6819	MODULE_DESCRIPTION("DRX-K driver");
6820	MODULE_AUTHOR("Ralph Metzler");
6821	MODULE_LICENSE("GPL");
6822