1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Driver for the ST STV0910 DVB-S/S2 demodulator. |
4 | * |
5 | * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de> |
6 | * Marcus Metzler <mocm@metzlerbros.de> |
7 | * developed for Digital Devices GmbH |
8 | */ |
9 | |
10 | #include <linux/kernel.h> |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> |
13 | #include <linux/init.h> |
14 | #include <linux/delay.h> |
15 | #include <linux/firmware.h> |
16 | #include <linux/i2c.h> |
17 | #include <asm/div64.h> |
18 | |
19 | #include <media/dvb_frontend.h> |
20 | #include "stv0910.h" |
21 | #include "stv0910_regs.h" |
22 | |
23 | #define EXT_CLOCK 30000000 |
24 | #define TUNING_DELAY 200 |
25 | #define BER_SRC_S 0x20 |
26 | #define BER_SRC_S2 0x20 |
27 | |
28 | static LIST_HEAD(stvlist); |
29 | |
30 | enum receive_mode { RCVMODE_NONE, RCVMODE_DVBS, RCVMODE_DVBS2, RCVMODE_AUTO }; |
31 | |
32 | enum dvbs2_fectype { DVBS2_64K, DVBS2_16K }; |
33 | |
34 | enum dvbs2_mod_cod { |
35 | DVBS2_DUMMY_PLF, DVBS2_QPSK_1_4, DVBS2_QPSK_1_3, DVBS2_QPSK_2_5, |
36 | DVBS2_QPSK_1_2, DVBS2_QPSK_3_5, DVBS2_QPSK_2_3, DVBS2_QPSK_3_4, |
37 | DVBS2_QPSK_4_5, DVBS2_QPSK_5_6, DVBS2_QPSK_8_9, DVBS2_QPSK_9_10, |
38 | DVBS2_8PSK_3_5, DVBS2_8PSK_2_3, DVBS2_8PSK_3_4, DVBS2_8PSK_5_6, |
39 | DVBS2_8PSK_8_9, DVBS2_8PSK_9_10, DVBS2_16APSK_2_3, DVBS2_16APSK_3_4, |
40 | DVBS2_16APSK_4_5, DVBS2_16APSK_5_6, DVBS2_16APSK_8_9, DVBS2_16APSK_9_10, |
41 | DVBS2_32APSK_3_4, DVBS2_32APSK_4_5, DVBS2_32APSK_5_6, DVBS2_32APSK_8_9, |
42 | DVBS2_32APSK_9_10 |
43 | }; |
44 | |
45 | enum fe_stv0910_mod_cod { |
46 | FE_DUMMY_PLF, FE_QPSK_14, FE_QPSK_13, FE_QPSK_25, |
47 | FE_QPSK_12, FE_QPSK_35, FE_QPSK_23, FE_QPSK_34, |
48 | FE_QPSK_45, FE_QPSK_56, FE_QPSK_89, FE_QPSK_910, |
49 | FE_8PSK_35, FE_8PSK_23, FE_8PSK_34, FE_8PSK_56, |
50 | FE_8PSK_89, FE_8PSK_910, FE_16APSK_23, FE_16APSK_34, |
51 | FE_16APSK_45, FE_16APSK_56, FE_16APSK_89, FE_16APSK_910, |
52 | FE_32APSK_34, FE_32APSK_45, FE_32APSK_56, FE_32APSK_89, |
53 | FE_32APSK_910 |
54 | }; |
55 | |
56 | enum fe_stv0910_roll_off { FE_SAT_35, FE_SAT_25, FE_SAT_20, FE_SAT_15 }; |
57 | |
58 | static inline u32 muldiv32(u32 a, u32 b, u32 c) |
59 | { |
60 | u64 tmp64; |
61 | |
62 | tmp64 = (u64)a * (u64)b; |
63 | do_div(tmp64, c); |
64 | |
65 | return (u32)tmp64; |
66 | } |
67 | |
68 | struct stv_base { |
69 | struct list_head stvlist; |
70 | |
71 | u8 adr; |
72 | struct i2c_adapter *i2c; |
73 | struct mutex i2c_lock; /* shared I2C access protect */ |
74 | struct mutex reg_lock; /* shared register write protect */ |
75 | int count; |
76 | |
77 | u32 extclk; |
78 | u32 mclk; |
79 | }; |
80 | |
81 | struct stv { |
82 | struct stv_base *base; |
83 | struct dvb_frontend fe; |
84 | int nr; |
85 | u16 regoff; |
86 | u8 i2crpt; |
87 | u8 tscfgh; |
88 | u8 tsgeneral; |
89 | u8 tsspeed; |
90 | u8 single; |
91 | unsigned long tune_time; |
92 | |
93 | s32 search_range; |
94 | u32 started; |
95 | u32 demod_lock_time; |
96 | enum receive_mode receive_mode; |
97 | u32 demod_timeout; |
98 | u32 fec_timeout; |
99 | u32 first_time_lock; |
100 | u8 demod_bits; |
101 | u32 symbol_rate; |
102 | |
103 | u8 last_viterbi_rate; |
104 | enum fe_code_rate puncture_rate; |
105 | enum fe_stv0910_mod_cod mod_cod; |
106 | enum dvbs2_fectype fectype; |
107 | u32 pilots; |
108 | enum fe_stv0910_roll_off feroll_off; |
109 | |
110 | int is_standard_broadcast; |
111 | int is_vcm; |
112 | |
113 | u32 cur_scrambling_code; |
114 | |
115 | u32 last_bernumerator; |
116 | u32 last_berdenominator; |
117 | u8 berscale; |
118 | |
119 | u8 vth[6]; |
120 | }; |
121 | |
122 | struct sinit_table { |
123 | u16 address; |
124 | u8 data; |
125 | }; |
126 | |
127 | struct slookup { |
128 | s16 value; |
129 | u32 reg_value; |
130 | }; |
131 | |
132 | static int write_reg(struct stv *state, u16 reg, u8 val) |
133 | { |
134 | struct i2c_adapter *adap = state->base->i2c; |
135 | u8 data[3] = {reg >> 8, reg & 0xff, val}; |
136 | struct i2c_msg msg = {.addr = state->base->adr, .flags = 0, |
137 | .buf = data, .len = 3}; |
138 | |
139 | if (i2c_transfer(adap, msgs: &msg, num: 1) != 1) { |
140 | dev_warn(&adap->dev, "i2c write error ([%02x] %04x: %02x)\n" , |
141 | state->base->adr, reg, val); |
142 | return -EIO; |
143 | } |
144 | return 0; |
145 | } |
146 | |
147 | static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr, |
148 | u16 reg, u8 *val, int count) |
149 | { |
150 | u8 msg[2] = {reg >> 8, reg & 0xff}; |
151 | struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, |
152 | .buf = msg, .len = 2}, |
153 | {.addr = adr, .flags = I2C_M_RD, |
154 | .buf = val, .len = count } }; |
155 | |
156 | if (i2c_transfer(adap: adapter, msgs, num: 2) != 2) { |
157 | dev_warn(&adapter->dev, "i2c read error ([%02x] %04x)\n" , |
158 | adr, reg); |
159 | return -EIO; |
160 | } |
161 | return 0; |
162 | } |
163 | |
164 | static int read_reg(struct stv *state, u16 reg, u8 *val) |
165 | { |
166 | return i2c_read_regs16(adapter: state->base->i2c, adr: state->base->adr, |
167 | reg, val, count: 1); |
168 | } |
169 | |
170 | static int read_regs(struct stv *state, u16 reg, u8 *val, int len) |
171 | { |
172 | return i2c_read_regs16(adapter: state->base->i2c, adr: state->base->adr, |
173 | reg, val, count: len); |
174 | } |
175 | |
176 | static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val) |
177 | { |
178 | int status; |
179 | u8 tmp; |
180 | |
181 | mutex_lock(&state->base->reg_lock); |
182 | status = read_reg(state, reg, val: &tmp); |
183 | if (!status) |
184 | status = write_reg(state, reg, val: (tmp & ~mask) | (val & mask)); |
185 | mutex_unlock(lock: &state->base->reg_lock); |
186 | return status; |
187 | } |
188 | |
189 | static int write_field(struct stv *state, u32 field, u8 val) |
190 | { |
191 | int status; |
192 | u8 shift, mask, old, new; |
193 | |
194 | status = read_reg(state, reg: field >> 16, val: &old); |
195 | if (status) |
196 | return status; |
197 | mask = field & 0xff; |
198 | shift = (field >> 12) & 0xf; |
199 | new = ((val << shift) & mask) | (old & ~mask); |
200 | if (new == old) |
201 | return 0; |
202 | return write_reg(state, reg: field >> 16, val: new); |
203 | } |
204 | |
205 | #define SET_FIELD(_reg, _val) \ |
206 | write_field(state, state->nr ? FSTV0910_P2_##_reg : \ |
207 | FSTV0910_P1_##_reg, _val) |
208 | |
209 | #define SET_REG(_reg, _val) \ |
210 | write_reg(state, state->nr ? RSTV0910_P2_##_reg : \ |
211 | RSTV0910_P1_##_reg, _val) |
212 | |
213 | #define GET_REG(_reg, _val) \ |
214 | read_reg(state, state->nr ? RSTV0910_P2_##_reg : \ |
215 | RSTV0910_P1_##_reg, _val) |
216 | |
217 | static const struct slookup s1_sn_lookup[] = { |
218 | { 0, 9242 }, /* C/N= 0dB */ |
219 | { 5, 9105 }, /* C/N= 0.5dB */ |
220 | { 10, 8950 }, /* C/N= 1.0dB */ |
221 | { 15, 8780 }, /* C/N= 1.5dB */ |
222 | { 20, 8566 }, /* C/N= 2.0dB */ |
223 | { 25, 8366 }, /* C/N= 2.5dB */ |
224 | { 30, 8146 }, /* C/N= 3.0dB */ |
225 | { 35, 7908 }, /* C/N= 3.5dB */ |
226 | { 40, 7666 }, /* C/N= 4.0dB */ |
227 | { 45, 7405 }, /* C/N= 4.5dB */ |
228 | { 50, 7136 }, /* C/N= 5.0dB */ |
229 | { 55, 6861 }, /* C/N= 5.5dB */ |
230 | { 60, 6576 }, /* C/N= 6.0dB */ |
231 | { 65, 6330 }, /* C/N= 6.5dB */ |
232 | { 70, 6048 }, /* C/N= 7.0dB */ |
233 | { 75, 5768 }, /* C/N= 7.5dB */ |
234 | { 80, 5492 }, /* C/N= 8.0dB */ |
235 | { 85, 5224 }, /* C/N= 8.5dB */ |
236 | { 90, 4959 }, /* C/N= 9.0dB */ |
237 | { 95, 4709 }, /* C/N= 9.5dB */ |
238 | { 100, 4467 }, /* C/N=10.0dB */ |
239 | { 105, 4236 }, /* C/N=10.5dB */ |
240 | { 110, 4013 }, /* C/N=11.0dB */ |
241 | { 115, 3800 }, /* C/N=11.5dB */ |
242 | { 120, 3598 }, /* C/N=12.0dB */ |
243 | { 125, 3406 }, /* C/N=12.5dB */ |
244 | { 130, 3225 }, /* C/N=13.0dB */ |
245 | { 135, 3052 }, /* C/N=13.5dB */ |
246 | { 140, 2889 }, /* C/N=14.0dB */ |
247 | { 145, 2733 }, /* C/N=14.5dB */ |
248 | { 150, 2587 }, /* C/N=15.0dB */ |
249 | { 160, 2318 }, /* C/N=16.0dB */ |
250 | { 170, 2077 }, /* C/N=17.0dB */ |
251 | { 180, 1862 }, /* C/N=18.0dB */ |
252 | { 190, 1670 }, /* C/N=19.0dB */ |
253 | { 200, 1499 }, /* C/N=20.0dB */ |
254 | { 210, 1347 }, /* C/N=21.0dB */ |
255 | { 220, 1213 }, /* C/N=22.0dB */ |
256 | { 230, 1095 }, /* C/N=23.0dB */ |
257 | { 240, 992 }, /* C/N=24.0dB */ |
258 | { 250, 900 }, /* C/N=25.0dB */ |
259 | { 260, 826 }, /* C/N=26.0dB */ |
260 | { 270, 758 }, /* C/N=27.0dB */ |
261 | { 280, 702 }, /* C/N=28.0dB */ |
262 | { 290, 653 }, /* C/N=29.0dB */ |
263 | { 300, 613 }, /* C/N=30.0dB */ |
264 | { 310, 579 }, /* C/N=31.0dB */ |
265 | { 320, 550 }, /* C/N=32.0dB */ |
266 | { 330, 526 }, /* C/N=33.0dB */ |
267 | { 350, 490 }, /* C/N=33.0dB */ |
268 | { 400, 445 }, /* C/N=40.0dB */ |
269 | { 450, 430 }, /* C/N=45.0dB */ |
270 | { 500, 426 }, /* C/N=50.0dB */ |
271 | { 510, 425 } /* C/N=51.0dB */ |
272 | }; |
273 | |
274 | static const struct slookup s2_sn_lookup[] = { |
275 | { -30, 13950 }, /* C/N=-2.5dB */ |
276 | { -25, 13580 }, /* C/N=-2.5dB */ |
277 | { -20, 13150 }, /* C/N=-2.0dB */ |
278 | { -15, 12760 }, /* C/N=-1.5dB */ |
279 | { -10, 12345 }, /* C/N=-1.0dB */ |
280 | { -5, 11900 }, /* C/N=-0.5dB */ |
281 | { 0, 11520 }, /* C/N= 0dB */ |
282 | { 5, 11080 }, /* C/N= 0.5dB */ |
283 | { 10, 10630 }, /* C/N= 1.0dB */ |
284 | { 15, 10210 }, /* C/N= 1.5dB */ |
285 | { 20, 9790 }, /* C/N= 2.0dB */ |
286 | { 25, 9390 }, /* C/N= 2.5dB */ |
287 | { 30, 8970 }, /* C/N= 3.0dB */ |
288 | { 35, 8575 }, /* C/N= 3.5dB */ |
289 | { 40, 8180 }, /* C/N= 4.0dB */ |
290 | { 45, 7800 }, /* C/N= 4.5dB */ |
291 | { 50, 7430 }, /* C/N= 5.0dB */ |
292 | { 55, 7080 }, /* C/N= 5.5dB */ |
293 | { 60, 6720 }, /* C/N= 6.0dB */ |
294 | { 65, 6320 }, /* C/N= 6.5dB */ |
295 | { 70, 6060 }, /* C/N= 7.0dB */ |
296 | { 75, 5760 }, /* C/N= 7.5dB */ |
297 | { 80, 5480 }, /* C/N= 8.0dB */ |
298 | { 85, 5200 }, /* C/N= 8.5dB */ |
299 | { 90, 4930 }, /* C/N= 9.0dB */ |
300 | { 95, 4680 }, /* C/N= 9.5dB */ |
301 | { 100, 4425 }, /* C/N=10.0dB */ |
302 | { 105, 4210 }, /* C/N=10.5dB */ |
303 | { 110, 3980 }, /* C/N=11.0dB */ |
304 | { 115, 3765 }, /* C/N=11.5dB */ |
305 | { 120, 3570 }, /* C/N=12.0dB */ |
306 | { 125, 3315 }, /* C/N=12.5dB */ |
307 | { 130, 3140 }, /* C/N=13.0dB */ |
308 | { 135, 2980 }, /* C/N=13.5dB */ |
309 | { 140, 2820 }, /* C/N=14.0dB */ |
310 | { 145, 2670 }, /* C/N=14.5dB */ |
311 | { 150, 2535 }, /* C/N=15.0dB */ |
312 | { 160, 2270 }, /* C/N=16.0dB */ |
313 | { 170, 2035 }, /* C/N=17.0dB */ |
314 | { 180, 1825 }, /* C/N=18.0dB */ |
315 | { 190, 1650 }, /* C/N=19.0dB */ |
316 | { 200, 1485 }, /* C/N=20.0dB */ |
317 | { 210, 1340 }, /* C/N=21.0dB */ |
318 | { 220, 1212 }, /* C/N=22.0dB */ |
319 | { 230, 1100 }, /* C/N=23.0dB */ |
320 | { 240, 1000 }, /* C/N=24.0dB */ |
321 | { 250, 910 }, /* C/N=25.0dB */ |
322 | { 260, 836 }, /* C/N=26.0dB */ |
323 | { 270, 772 }, /* C/N=27.0dB */ |
324 | { 280, 718 }, /* C/N=28.0dB */ |
325 | { 290, 671 }, /* C/N=29.0dB */ |
326 | { 300, 635 }, /* C/N=30.0dB */ |
327 | { 310, 602 }, /* C/N=31.0dB */ |
328 | { 320, 575 }, /* C/N=32.0dB */ |
329 | { 330, 550 }, /* C/N=33.0dB */ |
330 | { 350, 517 }, /* C/N=35.0dB */ |
331 | { 400, 480 }, /* C/N=40.0dB */ |
332 | { 450, 466 }, /* C/N=45.0dB */ |
333 | { 500, 464 }, /* C/N=50.0dB */ |
334 | { 510, 463 }, /* C/N=51.0dB */ |
335 | }; |
336 | |
337 | static const struct slookup padc_lookup[] = { |
338 | { 0, 118000 }, /* PADC= +0dBm */ |
339 | { -100, 93600 }, /* PADC= -1dBm */ |
340 | { -200, 74500 }, /* PADC= -2dBm */ |
341 | { -300, 59100 }, /* PADC= -3dBm */ |
342 | { -400, 47000 }, /* PADC= -4dBm */ |
343 | { -500, 37300 }, /* PADC= -5dBm */ |
344 | { -600, 29650 }, /* PADC= -6dBm */ |
345 | { -700, 23520 }, /* PADC= -7dBm */ |
346 | { -900, 14850 }, /* PADC= -9dBm */ |
347 | { -1100, 9380 }, /* PADC=-11dBm */ |
348 | { -1300, 5910 }, /* PADC=-13dBm */ |
349 | { -1500, 3730 }, /* PADC=-15dBm */ |
350 | { -1700, 2354 }, /* PADC=-17dBm */ |
351 | { -1900, 1485 }, /* PADC=-19dBm */ |
352 | { -2000, 1179 }, /* PADC=-20dBm */ |
353 | { -2100, 1000 }, /* PADC=-21dBm */ |
354 | }; |
355 | |
356 | /********************************************************************* |
357 | * Tracking carrier loop carrier QPSK 1/4 to 8PSK 9/10 long Frame |
358 | *********************************************************************/ |
359 | static const u8 s2car_loop[] = { |
360 | /* |
361 | * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff |
362 | * 20MPon 20MPoff 30MPon 30MPoff |
363 | */ |
364 | |
365 | /* FE_QPSK_14 */ |
366 | 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x2A, 0x1C, 0x3A, 0x3B, |
367 | /* FE_QPSK_13 */ |
368 | 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x3A, 0x0C, 0x3A, 0x2B, |
369 | /* FE_QPSK_25 */ |
370 | 0x1C, 0x3C, 0x1B, 0x3C, 0x3A, 0x1C, 0x3A, 0x3B, 0x3A, 0x2B, |
371 | /* FE_QPSK_12 */ |
372 | 0x0C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B, |
373 | /* FE_QPSK_35 */ |
374 | 0x1C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B, |
375 | /* FE_QPSK_23 */ |
376 | 0x2C, 0x2C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B, |
377 | /* FE_QPSK_34 */ |
378 | 0x3C, 0x2C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B, |
379 | /* FE_QPSK_45 */ |
380 | 0x0D, 0x3C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B, |
381 | /* FE_QPSK_56 */ |
382 | 0x1D, 0x3C, 0x0C, 0x2C, 0x2B, 0x1C, 0x1B, 0x3B, 0x0B, 0x1B, |
383 | /* FE_QPSK_89 */ |
384 | 0x3D, 0x0D, 0x0C, 0x2C, 0x2B, 0x0C, 0x2B, 0x2B, 0x0B, 0x0B, |
385 | /* FE_QPSK_910 */ |
386 | 0x1E, 0x0D, 0x1C, 0x2C, 0x3B, 0x0C, 0x2B, 0x2B, 0x1B, 0x0B, |
387 | /* FE_8PSK_35 */ |
388 | 0x28, 0x09, 0x28, 0x09, 0x28, 0x09, 0x28, 0x08, 0x28, 0x27, |
389 | /* FE_8PSK_23 */ |
390 | 0x19, 0x29, 0x19, 0x29, 0x19, 0x29, 0x38, 0x19, 0x28, 0x09, |
391 | /* FE_8PSK_34 */ |
392 | 0x1A, 0x0B, 0x1A, 0x3A, 0x0A, 0x2A, 0x39, 0x2A, 0x39, 0x1A, |
393 | /* FE_8PSK_56 */ |
394 | 0x2B, 0x2B, 0x1B, 0x1B, 0x0B, 0x1B, 0x1A, 0x0B, 0x1A, 0x1A, |
395 | /* FE_8PSK_89 */ |
396 | 0x0C, 0x0C, 0x3B, 0x3B, 0x1B, 0x1B, 0x2A, 0x0B, 0x2A, 0x2A, |
397 | /* FE_8PSK_910 */ |
398 | 0x0C, 0x1C, 0x0C, 0x3B, 0x2B, 0x1B, 0x3A, 0x0B, 0x2A, 0x2A, |
399 | |
400 | /********************************************************************** |
401 | * Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame |
402 | **********************************************************************/ |
403 | |
404 | /* |
405 | * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon |
406 | * 20MPoff 30MPon 30MPoff |
407 | */ |
408 | |
409 | /* FE_16APSK_23 */ |
410 | 0x0A, 0x0A, 0x0A, 0x0A, 0x1A, 0x0A, 0x39, 0x0A, 0x29, 0x0A, |
411 | /* FE_16APSK_34 */ |
412 | 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0A, 0x2A, 0x0A, 0x1A, 0x0A, |
413 | /* FE_16APSK_45 */ |
414 | 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A, |
415 | /* FE_16APSK_56 */ |
416 | 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A, |
417 | /* FE_16APSK_89 */ |
418 | 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A, |
419 | /* FE_16APSK_910 */ |
420 | 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A, |
421 | /* FE_32APSK_34 */ |
422 | 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, |
423 | /* FE_32APSK_45 */ |
424 | 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, |
425 | /* FE_32APSK_56 */ |
426 | 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, |
427 | /* FE_32APSK_89 */ |
428 | 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, |
429 | /* FE_32APSK_910 */ |
430 | 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, |
431 | }; |
432 | |
433 | static u8 get_optim_cloop(struct stv *state, |
434 | enum fe_stv0910_mod_cod mod_cod, u32 pilots) |
435 | { |
436 | int i = 0; |
437 | |
438 | if (mod_cod >= FE_32APSK_910) |
439 | i = ((int)FE_32APSK_910 - (int)FE_QPSK_14) * 10; |
440 | else if (mod_cod >= FE_QPSK_14) |
441 | i = ((int)mod_cod - (int)FE_QPSK_14) * 10; |
442 | |
443 | if (state->symbol_rate <= 3000000) |
444 | i += 0; |
445 | else if (state->symbol_rate <= 7000000) |
446 | i += 2; |
447 | else if (state->symbol_rate <= 15000000) |
448 | i += 4; |
449 | else if (state->symbol_rate <= 25000000) |
450 | i += 6; |
451 | else |
452 | i += 8; |
453 | |
454 | if (!pilots) |
455 | i += 1; |
456 | |
457 | return s2car_loop[i]; |
458 | } |
459 | |
460 | static int get_cur_symbol_rate(struct stv *state, u32 *p_symbol_rate) |
461 | { |
462 | int status = 0; |
463 | u8 symb_freq0; |
464 | u8 symb_freq1; |
465 | u8 symb_freq2; |
466 | u8 symb_freq3; |
467 | u8 tim_offs0; |
468 | u8 tim_offs1; |
469 | u8 tim_offs2; |
470 | u32 symbol_rate; |
471 | s32 timing_offset; |
472 | |
473 | *p_symbol_rate = 0; |
474 | if (!state->started) |
475 | return status; |
476 | |
477 | read_reg(state, RSTV0910_P2_SFR3 + state->regoff, val: &symb_freq3); |
478 | read_reg(state, RSTV0910_P2_SFR2 + state->regoff, val: &symb_freq2); |
479 | read_reg(state, RSTV0910_P2_SFR1 + state->regoff, val: &symb_freq1); |
480 | read_reg(state, RSTV0910_P2_SFR0 + state->regoff, val: &symb_freq0); |
481 | read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, val: &tim_offs2); |
482 | read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, val: &tim_offs1); |
483 | read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, val: &tim_offs0); |
484 | |
485 | symbol_rate = ((u32)symb_freq3 << 24) | ((u32)symb_freq2 << 16) | |
486 | ((u32)symb_freq1 << 8) | (u32)symb_freq0; |
487 | timing_offset = ((u32)tim_offs2 << 16) | ((u32)tim_offs1 << 8) | |
488 | (u32)tim_offs0; |
489 | |
490 | if ((timing_offset & (1 << 23)) != 0) |
491 | timing_offset |= 0xFF000000; /* Sign extent */ |
492 | |
493 | symbol_rate = (u32)(((u64)symbol_rate * state->base->mclk) >> 32); |
494 | timing_offset = (s32)(((s64)symbol_rate * (s64)timing_offset) >> 29); |
495 | |
496 | *p_symbol_rate = symbol_rate + timing_offset; |
497 | |
498 | return 0; |
499 | } |
500 | |
501 | static int get_signal_parameters(struct stv *state) |
502 | { |
503 | u8 tmp; |
504 | |
505 | if (!state->started) |
506 | return -EINVAL; |
507 | |
508 | if (state->receive_mode == RCVMODE_DVBS2) { |
509 | read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, val: &tmp); |
510 | state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2); |
511 | state->pilots = (tmp & 0x01) != 0; |
512 | state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1); |
513 | |
514 | } else if (state->receive_mode == RCVMODE_DVBS) { |
515 | read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, val: &tmp); |
516 | state->puncture_rate = FEC_NONE; |
517 | switch (tmp & 0x1F) { |
518 | case 0x0d: |
519 | state->puncture_rate = FEC_1_2; |
520 | break; |
521 | case 0x12: |
522 | state->puncture_rate = FEC_2_3; |
523 | break; |
524 | case 0x15: |
525 | state->puncture_rate = FEC_3_4; |
526 | break; |
527 | case 0x18: |
528 | state->puncture_rate = FEC_5_6; |
529 | break; |
530 | case 0x1a: |
531 | state->puncture_rate = FEC_7_8; |
532 | break; |
533 | } |
534 | state->is_vcm = 0; |
535 | state->is_standard_broadcast = 1; |
536 | state->feroll_off = FE_SAT_35; |
537 | } |
538 | return 0; |
539 | } |
540 | |
541 | static int tracking_optimization(struct stv *state) |
542 | { |
543 | u8 tmp; |
544 | |
545 | read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, val: &tmp); |
546 | tmp &= ~0xC0; |
547 | |
548 | switch (state->receive_mode) { |
549 | case RCVMODE_DVBS: |
550 | tmp |= 0x40; |
551 | break; |
552 | case RCVMODE_DVBS2: |
553 | tmp |= 0x80; |
554 | break; |
555 | default: |
556 | tmp |= 0xC0; |
557 | break; |
558 | } |
559 | write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, val: tmp); |
560 | |
561 | if (state->receive_mode == RCVMODE_DVBS2) { |
562 | /* Disable Reed-Solomon */ |
563 | write_shared_reg(state, |
564 | RSTV0910_TSTTSRS, mask: state->nr ? 0x02 : 0x01, |
565 | val: 0x03); |
566 | |
567 | if (state->fectype == DVBS2_64K) { |
568 | u8 aclc = get_optim_cloop(state, mod_cod: state->mod_cod, |
569 | pilots: state->pilots); |
570 | |
571 | if (state->mod_cod <= FE_QPSK_910) { |
572 | write_reg(state, RSTV0910_P2_ACLC2S2Q + |
573 | state->regoff, val: aclc); |
574 | } else if (state->mod_cod <= FE_8PSK_910) { |
575 | write_reg(state, RSTV0910_P2_ACLC2S2Q + |
576 | state->regoff, val: 0x2a); |
577 | write_reg(state, RSTV0910_P2_ACLC2S28 + |
578 | state->regoff, val: aclc); |
579 | } else if (state->mod_cod <= FE_16APSK_910) { |
580 | write_reg(state, RSTV0910_P2_ACLC2S2Q + |
581 | state->regoff, val: 0x2a); |
582 | write_reg(state, RSTV0910_P2_ACLC2S216A + |
583 | state->regoff, val: aclc); |
584 | } else if (state->mod_cod <= FE_32APSK_910) { |
585 | write_reg(state, RSTV0910_P2_ACLC2S2Q + |
586 | state->regoff, val: 0x2a); |
587 | write_reg(state, RSTV0910_P2_ACLC2S232A + |
588 | state->regoff, val: aclc); |
589 | } |
590 | } |
591 | } |
592 | return 0; |
593 | } |
594 | |
595 | static s32 table_lookup(const struct slookup *table, |
596 | int table_size, u32 reg_value) |
597 | { |
598 | s32 value; |
599 | int imin = 0; |
600 | int imax = table_size - 1; |
601 | int i; |
602 | s32 reg_diff; |
603 | |
604 | /* Assumes Table[0].RegValue > Table[imax].RegValue */ |
605 | if (reg_value >= table[0].reg_value) { |
606 | value = table[0].value; |
607 | } else if (reg_value <= table[imax].reg_value) { |
608 | value = table[imax].value; |
609 | } else { |
610 | while ((imax - imin) > 1) { |
611 | i = (imax + imin) / 2; |
612 | if ((table[imin].reg_value >= reg_value) && |
613 | (reg_value >= table[i].reg_value)) |
614 | imax = i; |
615 | else |
616 | imin = i; |
617 | } |
618 | |
619 | reg_diff = table[imax].reg_value - table[imin].reg_value; |
620 | value = table[imin].value; |
621 | if (reg_diff != 0) |
622 | value += ((s32)(reg_value - table[imin].reg_value) * |
623 | (s32)(table[imax].value |
624 | - table[imin].value)) |
625 | / (reg_diff); |
626 | } |
627 | |
628 | return value; |
629 | } |
630 | |
631 | static int get_signal_to_noise(struct stv *state, s32 *signal_to_noise) |
632 | { |
633 | u8 data0; |
634 | u8 data1; |
635 | u16 data; |
636 | int n_lookup; |
637 | const struct slookup *lookup; |
638 | |
639 | *signal_to_noise = 0; |
640 | |
641 | if (!state->started) |
642 | return -EINVAL; |
643 | |
644 | if (state->receive_mode == RCVMODE_DVBS2) { |
645 | read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff, |
646 | val: &data1); |
647 | read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff, |
648 | val: &data0); |
649 | n_lookup = ARRAY_SIZE(s2_sn_lookup); |
650 | lookup = s2_sn_lookup; |
651 | } else { |
652 | read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff, |
653 | val: &data1); |
654 | read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff, |
655 | val: &data0); |
656 | n_lookup = ARRAY_SIZE(s1_sn_lookup); |
657 | lookup = s1_sn_lookup; |
658 | } |
659 | data = (((u16)data1) << 8) | (u16)data0; |
660 | *signal_to_noise = table_lookup(table: lookup, table_size: n_lookup, reg_value: data); |
661 | return 0; |
662 | } |
663 | |
664 | static int get_bit_error_rate_s(struct stv *state, u32 *bernumerator, |
665 | u32 *berdenominator) |
666 | { |
667 | u8 regs[3]; |
668 | |
669 | int status = read_regs(state, |
670 | RSTV0910_P2_ERRCNT12 + state->regoff, |
671 | val: regs, len: 3); |
672 | |
673 | if (status) |
674 | return -EINVAL; |
675 | |
676 | if ((regs[0] & 0x80) == 0) { |
677 | state->last_berdenominator = 1ULL << ((state->berscale * 2) + |
678 | 10 + 3); |
679 | state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) | |
680 | ((u32)regs[1] << 8) | regs[2]; |
681 | if (state->last_bernumerator < 256 && state->berscale < 6) { |
682 | state->berscale += 1; |
683 | status = write_reg(state, RSTV0910_P2_ERRCTRL1 + |
684 | state->regoff, |
685 | val: 0x20 | state->berscale); |
686 | } else if (state->last_bernumerator > 1024 && |
687 | state->berscale > 2) { |
688 | state->berscale -= 1; |
689 | status = write_reg(state, RSTV0910_P2_ERRCTRL1 + |
690 | state->regoff, val: 0x20 | |
691 | state->berscale); |
692 | } |
693 | } |
694 | *bernumerator = state->last_bernumerator; |
695 | *berdenominator = state->last_berdenominator; |
696 | return 0; |
697 | } |
698 | |
699 | static u32 dvbs2_nbch(enum dvbs2_mod_cod mod_cod, enum dvbs2_fectype fectype) |
700 | { |
701 | static const u32 nbch[][2] = { |
702 | { 0, 0}, /* DUMMY_PLF */ |
703 | {16200, 3240}, /* QPSK_1_4, */ |
704 | {21600, 5400}, /* QPSK_1_3, */ |
705 | {25920, 6480}, /* QPSK_2_5, */ |
706 | {32400, 7200}, /* QPSK_1_2, */ |
707 | {38880, 9720}, /* QPSK_3_5, */ |
708 | {43200, 10800}, /* QPSK_2_3, */ |
709 | {48600, 11880}, /* QPSK_3_4, */ |
710 | {51840, 12600}, /* QPSK_4_5, */ |
711 | {54000, 13320}, /* QPSK_5_6, */ |
712 | {57600, 14400}, /* QPSK_8_9, */ |
713 | {58320, 16000}, /* QPSK_9_10, */ |
714 | {43200, 9720}, /* 8PSK_3_5, */ |
715 | {48600, 10800}, /* 8PSK_2_3, */ |
716 | {51840, 11880}, /* 8PSK_3_4, */ |
717 | {54000, 13320}, /* 8PSK_5_6, */ |
718 | {57600, 14400}, /* 8PSK_8_9, */ |
719 | {58320, 16000}, /* 8PSK_9_10, */ |
720 | {43200, 10800}, /* 16APSK_2_3, */ |
721 | {48600, 11880}, /* 16APSK_3_4, */ |
722 | {51840, 12600}, /* 16APSK_4_5, */ |
723 | {54000, 13320}, /* 16APSK_5_6, */ |
724 | {57600, 14400}, /* 16APSK_8_9, */ |
725 | {58320, 16000}, /* 16APSK_9_10 */ |
726 | {48600, 11880}, /* 32APSK_3_4, */ |
727 | {51840, 12600}, /* 32APSK_4_5, */ |
728 | {54000, 13320}, /* 32APSK_5_6, */ |
729 | {57600, 14400}, /* 32APSK_8_9, */ |
730 | {58320, 16000}, /* 32APSK_9_10 */ |
731 | }; |
732 | |
733 | if (mod_cod >= DVBS2_QPSK_1_4 && |
734 | mod_cod <= DVBS2_32APSK_9_10 && fectype <= DVBS2_16K) |
735 | return nbch[mod_cod][fectype]; |
736 | return 64800; |
737 | } |
738 | |
739 | static int get_bit_error_rate_s2(struct stv *state, u32 *bernumerator, |
740 | u32 *berdenominator) |
741 | { |
742 | u8 regs[3]; |
743 | |
744 | int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff, |
745 | val: regs, len: 3); |
746 | |
747 | if (status) |
748 | return -EINVAL; |
749 | |
750 | if ((regs[0] & 0x80) == 0) { |
751 | state->last_berdenominator = |
752 | dvbs2_nbch(mod_cod: (enum dvbs2_mod_cod)state->mod_cod, |
753 | fectype: state->fectype) << |
754 | (state->berscale * 2); |
755 | state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) | |
756 | ((u32)regs[1] << 8) | regs[2]; |
757 | if (state->last_bernumerator < 256 && state->berscale < 6) { |
758 | state->berscale += 1; |
759 | write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, |
760 | val: 0x20 | state->berscale); |
761 | } else if (state->last_bernumerator > 1024 && |
762 | state->berscale > 2) { |
763 | state->berscale -= 1; |
764 | write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, |
765 | val: 0x20 | state->berscale); |
766 | } |
767 | } |
768 | *bernumerator = state->last_bernumerator; |
769 | *berdenominator = state->last_berdenominator; |
770 | return status; |
771 | } |
772 | |
773 | static int get_bit_error_rate(struct stv *state, u32 *bernumerator, |
774 | u32 *berdenominator) |
775 | { |
776 | *bernumerator = 0; |
777 | *berdenominator = 1; |
778 | |
779 | switch (state->receive_mode) { |
780 | case RCVMODE_DVBS: |
781 | return get_bit_error_rate_s(state, |
782 | bernumerator, berdenominator); |
783 | case RCVMODE_DVBS2: |
784 | return get_bit_error_rate_s2(state, |
785 | bernumerator, berdenominator); |
786 | default: |
787 | break; |
788 | } |
789 | return 0; |
790 | } |
791 | |
792 | static int set_mclock(struct stv *state, u32 master_clock) |
793 | { |
794 | u32 idf = 1; |
795 | u32 odf = 4; |
796 | u32 quartz = state->base->extclk / 1000000; |
797 | u32 fphi = master_clock / 1000000; |
798 | u32 ndiv = (fphi * odf * idf) / quartz; |
799 | u32 cp = 7; |
800 | u32 fvco; |
801 | |
802 | if (ndiv >= 7 && ndiv <= 71) |
803 | cp = 7; |
804 | else if (ndiv >= 72 && ndiv <= 79) |
805 | cp = 8; |
806 | else if (ndiv >= 80 && ndiv <= 87) |
807 | cp = 9; |
808 | else if (ndiv >= 88 && ndiv <= 95) |
809 | cp = 10; |
810 | else if (ndiv >= 96 && ndiv <= 103) |
811 | cp = 11; |
812 | else if (ndiv >= 104 && ndiv <= 111) |
813 | cp = 12; |
814 | else if (ndiv >= 112 && ndiv <= 119) |
815 | cp = 13; |
816 | else if (ndiv >= 120 && ndiv <= 127) |
817 | cp = 14; |
818 | else if (ndiv >= 128 && ndiv <= 135) |
819 | cp = 15; |
820 | else if (ndiv >= 136 && ndiv <= 143) |
821 | cp = 16; |
822 | else if (ndiv >= 144 && ndiv <= 151) |
823 | cp = 17; |
824 | else if (ndiv >= 152 && ndiv <= 159) |
825 | cp = 18; |
826 | else if (ndiv >= 160 && ndiv <= 167) |
827 | cp = 19; |
828 | else if (ndiv >= 168 && ndiv <= 175) |
829 | cp = 20; |
830 | else if (ndiv >= 176 && ndiv <= 183) |
831 | cp = 21; |
832 | else if (ndiv >= 184 && ndiv <= 191) |
833 | cp = 22; |
834 | else if (ndiv >= 192 && ndiv <= 199) |
835 | cp = 23; |
836 | else if (ndiv >= 200 && ndiv <= 207) |
837 | cp = 24; |
838 | else if (ndiv >= 208 && ndiv <= 215) |
839 | cp = 25; |
840 | else if (ndiv >= 216 && ndiv <= 223) |
841 | cp = 26; |
842 | else if (ndiv >= 224 && ndiv <= 225) |
843 | cp = 27; |
844 | |
845 | write_reg(state, RSTV0910_NCOARSE, val: (cp << 3) | idf); |
846 | write_reg(state, RSTV0910_NCOARSE2, val: odf); |
847 | write_reg(state, RSTV0910_NCOARSE1, val: ndiv); |
848 | |
849 | fvco = (quartz * 2 * ndiv) / idf; |
850 | state->base->mclk = fvco / (2 * odf) * 1000000; |
851 | |
852 | return 0; |
853 | } |
854 | |
855 | static int stop(struct stv *state) |
856 | { |
857 | if (state->started) { |
858 | u8 tmp; |
859 | |
860 | write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, |
861 | val: state->tscfgh | 0x01); |
862 | read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, val: &tmp); |
863 | tmp &= ~0x01; /* release reset DVBS2 packet delin */ |
864 | write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, val: tmp); |
865 | /* Blind optim*/ |
866 | write_reg(state, RSTV0910_P2_AGC2O + state->regoff, val: 0x5B); |
867 | /* Stop the demod */ |
868 | write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, val: 0x5c); |
869 | state->started = 0; |
870 | } |
871 | state->receive_mode = RCVMODE_NONE; |
872 | return 0; |
873 | } |
874 | |
875 | static void set_pls(struct stv *state, u32 pls_code) |
876 | { |
877 | if (pls_code == state->cur_scrambling_code) |
878 | return; |
879 | |
880 | /* PLROOT2 bit 2 = gold code */ |
881 | write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff, |
882 | val: pls_code & 0xff); |
883 | write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff, |
884 | val: (pls_code >> 8) & 0xff); |
885 | write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff, |
886 | val: 0x04 | ((pls_code >> 16) & 0x03)); |
887 | state->cur_scrambling_code = pls_code; |
888 | } |
889 | |
890 | static void set_isi(struct stv *state, u32 isi) |
891 | { |
892 | if (isi == NO_STREAM_ID_FILTER) |
893 | return; |
894 | if (isi == 0x80000000) { |
895 | SET_FIELD(FORCE_CONTINUOUS, 1); |
896 | SET_FIELD(TSOUT_NOSYNC, 1); |
897 | } else { |
898 | SET_FIELD(FILTER_EN, 1); |
899 | write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff, |
900 | val: isi & 0xff); |
901 | write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, val: 0xff); |
902 | } |
903 | SET_FIELD(ALGOSWRST, 1); |
904 | SET_FIELD(ALGOSWRST, 0); |
905 | } |
906 | |
907 | static void set_stream_modes(struct stv *state, |
908 | struct dtv_frontend_properties *p) |
909 | { |
910 | set_isi(state, isi: p->stream_id); |
911 | set_pls(state, pls_code: p->scrambling_sequence_index); |
912 | } |
913 | |
914 | static int init_search_param(struct stv *state, |
915 | struct dtv_frontend_properties *p) |
916 | { |
917 | SET_FIELD(FORCE_CONTINUOUS, 0); |
918 | SET_FIELD(FRAME_MODE, 0); |
919 | SET_FIELD(FILTER_EN, 0); |
920 | SET_FIELD(TSOUT_NOSYNC, 0); |
921 | SET_FIELD(TSFIFO_EMBINDVB, 0); |
922 | SET_FIELD(TSDEL_SYNCBYTE, 0); |
923 | SET_REG(UPLCCST0, 0xe0); |
924 | SET_FIELD(TSINS_TOKEN, 0); |
925 | SET_FIELD(HYSTERESIS_THRESHOLD, 0); |
926 | SET_FIELD(ISIOBS_MODE, 1); |
927 | |
928 | set_stream_modes(state, p); |
929 | return 0; |
930 | } |
931 | |
932 | static int enable_puncture_rate(struct stv *state, enum fe_code_rate rate) |
933 | { |
934 | u8 val; |
935 | |
936 | switch (rate) { |
937 | case FEC_1_2: |
938 | val = 0x01; |
939 | break; |
940 | case FEC_2_3: |
941 | val = 0x02; |
942 | break; |
943 | case FEC_3_4: |
944 | val = 0x04; |
945 | break; |
946 | case FEC_5_6: |
947 | val = 0x08; |
948 | break; |
949 | case FEC_7_8: |
950 | val = 0x20; |
951 | break; |
952 | case FEC_NONE: |
953 | default: |
954 | val = 0x2f; |
955 | break; |
956 | } |
957 | |
958 | return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val); |
959 | } |
960 | |
961 | static int set_vth_default(struct stv *state) |
962 | { |
963 | state->vth[0] = 0xd7; |
964 | state->vth[1] = 0x85; |
965 | state->vth[2] = 0x58; |
966 | state->vth[3] = 0x3a; |
967 | state->vth[4] = 0x34; |
968 | state->vth[5] = 0x28; |
969 | write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, val: state->vth[0]); |
970 | write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, val: state->vth[1]); |
971 | write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, val: state->vth[2]); |
972 | write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, val: state->vth[3]); |
973 | write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, val: state->vth[4]); |
974 | write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, val: state->vth[5]); |
975 | return 0; |
976 | } |
977 | |
978 | static int set_vth(struct stv *state) |
979 | { |
980 | static const struct slookup vthlookup_table[] = { |
981 | {250, 8780}, /* C/N= 1.5dB */ |
982 | {100, 7405}, /* C/N= 4.5dB */ |
983 | {40, 6330}, /* C/N= 6.5dB */ |
984 | {12, 5224}, /* C/N= 8.5dB */ |
985 | {5, 4236} /* C/N=10.5dB */ |
986 | }; |
987 | |
988 | int i; |
989 | u8 tmp[2]; |
990 | int status = read_regs(state, |
991 | RSTV0910_P2_NNOSDATAT1 + state->regoff, |
992 | val: tmp, len: 2); |
993 | u16 reg_value = (tmp[0] << 8) | tmp[1]; |
994 | s32 vth = table_lookup(table: vthlookup_table, ARRAY_SIZE(vthlookup_table), |
995 | reg_value); |
996 | |
997 | for (i = 0; i < 6; i += 1) |
998 | if (state->vth[i] > vth) |
999 | state->vth[i] = vth; |
1000 | |
1001 | write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, val: state->vth[0]); |
1002 | write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, val: state->vth[1]); |
1003 | write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, val: state->vth[2]); |
1004 | write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, val: state->vth[3]); |
1005 | write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, val: state->vth[4]); |
1006 | write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, val: state->vth[5]); |
1007 | return status; |
1008 | } |
1009 | |
1010 | static int start(struct stv *state, struct dtv_frontend_properties *p) |
1011 | { |
1012 | s32 freq; |
1013 | u8 reg_dmdcfgmd; |
1014 | u16 symb; |
1015 | |
1016 | if (p->symbol_rate < 100000 || p->symbol_rate > 70000000) |
1017 | return -EINVAL; |
1018 | |
1019 | state->receive_mode = RCVMODE_NONE; |
1020 | state->demod_lock_time = 0; |
1021 | |
1022 | /* Demod Stop */ |
1023 | if (state->started) |
1024 | write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, val: 0x5C); |
1025 | |
1026 | init_search_param(state, p); |
1027 | |
1028 | if (p->symbol_rate <= 1000000) { /* SR <=1Msps */ |
1029 | state->demod_timeout = 3000; |
1030 | state->fec_timeout = 2000; |
1031 | } else if (p->symbol_rate <= 2000000) { /* 1Msps < SR <=2Msps */ |
1032 | state->demod_timeout = 2500; |
1033 | state->fec_timeout = 1300; |
1034 | } else if (p->symbol_rate <= 5000000) { /* 2Msps< SR <=5Msps */ |
1035 | state->demod_timeout = 1000; |
1036 | state->fec_timeout = 650; |
1037 | } else if (p->symbol_rate <= 10000000) { /* 5Msps< SR <=10Msps */ |
1038 | state->demod_timeout = 700; |
1039 | state->fec_timeout = 350; |
1040 | } else if (p->symbol_rate < 20000000) { /* 10Msps< SR <=20Msps */ |
1041 | state->demod_timeout = 400; |
1042 | state->fec_timeout = 200; |
1043 | } else { /* SR >=20Msps */ |
1044 | state->demod_timeout = 300; |
1045 | state->fec_timeout = 200; |
1046 | } |
1047 | |
1048 | /* Set the Init Symbol rate */ |
1049 | symb = muldiv32(a: p->symbol_rate, b: 65536, c: state->base->mclk); |
1050 | write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff, |
1051 | val: ((symb >> 8) & 0x7F)); |
1052 | write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, val: (symb & 0xFF)); |
1053 | |
1054 | state->demod_bits |= 0x80; |
1055 | write_reg(state, RSTV0910_P2_DEMOD + state->regoff, val: state->demod_bits); |
1056 | |
1057 | /* FE_STV0910_SetSearchStandard */ |
1058 | read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, val: ®_dmdcfgmd); |
1059 | write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, |
1060 | val: reg_dmdcfgmd |= 0xC0); |
1061 | |
1062 | write_shared_reg(state, |
1063 | RSTV0910_TSTTSRS, mask: state->nr ? 0x02 : 0x01, val: 0x00); |
1064 | |
1065 | /* Disable DSS */ |
1066 | write_reg(state, RSTV0910_P2_FECM + state->regoff, val: 0x00); |
1067 | write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val: 0x2F); |
1068 | |
1069 | enable_puncture_rate(state, rate: FEC_NONE); |
1070 | |
1071 | /* 8PSK 3/5, 8PSK 2/3 Poff tracking optimization WA */ |
1072 | write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, val: 0x0B); |
1073 | write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, val: 0x0A); |
1074 | write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, val: 0x84); |
1075 | write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, val: 0x84); |
1076 | write_reg(state, RSTV0910_P2_CARHDR + state->regoff, val: 0x1C); |
1077 | write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, val: 0x79); |
1078 | |
1079 | write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, val: 0x29); |
1080 | write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, val: 0x09); |
1081 | write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, val: 0x84); |
1082 | write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, val: 0x84); |
1083 | |
1084 | /* |
1085 | * Reset CAR3, bug DVBS2->DVBS1 lock |
1086 | * Note: The bit is only pulsed -> no lock on shared register needed |
1087 | */ |
1088 | write_reg(state, RSTV0910_TSTRES0, val: state->nr ? 0x04 : 0x08); |
1089 | write_reg(state, RSTV0910_TSTRES0, val: 0); |
1090 | |
1091 | set_vth_default(state); |
1092 | /* Reset demod */ |
1093 | write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, val: 0x1F); |
1094 | |
1095 | write_reg(state, RSTV0910_P2_CARCFG + state->regoff, val: 0x46); |
1096 | |
1097 | if (p->symbol_rate <= 5000000) |
1098 | freq = (state->search_range / 2000) + 80; |
1099 | else |
1100 | freq = (state->search_range / 2000) + 1600; |
1101 | freq = (freq << 16) / (state->base->mclk / 1000); |
1102 | |
1103 | write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff, |
1104 | val: (freq >> 8) & 0xff); |
1105 | write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, val: (freq & 0xff)); |
1106 | /* CFR Low Setting */ |
1107 | freq = -freq; |
1108 | write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff, |
1109 | val: (freq >> 8) & 0xff); |
1110 | write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, val: (freq & 0xff)); |
1111 | |
1112 | /* init the demod frequency offset to 0 */ |
1113 | write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, val: 0); |
1114 | write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, val: 0); |
1115 | |
1116 | write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, val: 0x1F); |
1117 | /* Trigger acq */ |
1118 | write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, val: 0x15); |
1119 | |
1120 | state->demod_lock_time += TUNING_DELAY; |
1121 | state->started = 1; |
1122 | |
1123 | return 0; |
1124 | } |
1125 | |
1126 | static int init_diseqc(struct stv *state) |
1127 | { |
1128 | u16 offs = state->nr ? 0x40 : 0; /* Address offset */ |
1129 | u8 freq = ((state->base->mclk + 11000 * 32) / (22000 * 32)); |
1130 | |
1131 | /* Disable receiver */ |
1132 | write_reg(state, RSTV0910_P1_DISRXCFG + offs, val: 0x00); |
1133 | write_reg(state, RSTV0910_P1_DISTXCFG + offs, val: 0xBA); /* Reset = 1 */ |
1134 | write_reg(state, RSTV0910_P1_DISTXCFG + offs, val: 0x3A); /* Reset = 0 */ |
1135 | write_reg(state, RSTV0910_P1_DISTXF22 + offs, val: freq); |
1136 | return 0; |
1137 | } |
1138 | |
1139 | static int probe(struct stv *state) |
1140 | { |
1141 | u8 id; |
1142 | |
1143 | state->receive_mode = RCVMODE_NONE; |
1144 | state->started = 0; |
1145 | |
1146 | if (read_reg(state, RSTV0910_MID, val: &id) < 0) |
1147 | return -ENODEV; |
1148 | |
1149 | if (id != 0x51) |
1150 | return -EINVAL; |
1151 | |
1152 | /* Configure the I2C repeater to off */ |
1153 | write_reg(state, RSTV0910_P1_I2CRPT, val: 0x24); |
1154 | /* Configure the I2C repeater to off */ |
1155 | write_reg(state, RSTV0910_P2_I2CRPT, val: 0x24); |
1156 | /* Set the I2C to oversampling ratio */ |
1157 | write_reg(state, RSTV0910_I2CCFG, val: 0x88); /* state->i2ccfg */ |
1158 | |
1159 | write_reg(state, RSTV0910_OUTCFG, val: 0x00); /* OUTCFG */ |
1160 | write_reg(state, RSTV0910_PADCFG, val: 0x05); /* RFAGC Pads Dev = 05 */ |
1161 | write_reg(state, RSTV0910_SYNTCTRL, val: 0x02); /* SYNTCTRL */ |
1162 | write_reg(state, RSTV0910_TSGENERAL, val: state->tsgeneral); /* TSGENERAL */ |
1163 | write_reg(state, RSTV0910_CFGEXT, val: 0x02); /* CFGEXT */ |
1164 | |
1165 | if (state->single) |
1166 | write_reg(state, RSTV0910_GENCFG, val: 0x14); /* GENCFG */ |
1167 | else |
1168 | write_reg(state, RSTV0910_GENCFG, val: 0x15); /* GENCFG */ |
1169 | |
1170 | write_reg(state, RSTV0910_P1_TNRCFG2, val: 0x02); /* IQSWAP = 0 */ |
1171 | write_reg(state, RSTV0910_P2_TNRCFG2, val: 0x82); /* IQSWAP = 1 */ |
1172 | |
1173 | write_reg(state, RSTV0910_P1_CAR3CFG, val: 0x02); |
1174 | write_reg(state, RSTV0910_P2_CAR3CFG, val: 0x02); |
1175 | write_reg(state, RSTV0910_P1_DMDCFG4, val: 0x04); |
1176 | write_reg(state, RSTV0910_P2_DMDCFG4, val: 0x04); |
1177 | |
1178 | write_reg(state, RSTV0910_TSTRES0, val: 0x80); /* LDPC Reset */ |
1179 | write_reg(state, RSTV0910_TSTRES0, val: 0x00); |
1180 | |
1181 | write_reg(state, RSTV0910_P1_TSPIDFLT1, val: 0x00); |
1182 | write_reg(state, RSTV0910_P2_TSPIDFLT1, val: 0x00); |
1183 | |
1184 | write_reg(state, RSTV0910_P1_TMGCFG2, val: 0x80); |
1185 | write_reg(state, RSTV0910_P2_TMGCFG2, val: 0x80); |
1186 | |
1187 | set_mclock(state, master_clock: 135000000); |
1188 | |
1189 | /* TS output */ |
1190 | write_reg(state, RSTV0910_P1_TSCFGH, val: state->tscfgh | 0x01); |
1191 | write_reg(state, RSTV0910_P1_TSCFGH, val: state->tscfgh); |
1192 | write_reg(state, RSTV0910_P1_TSCFGM, val: 0xC0); /* Manual speed */ |
1193 | write_reg(state, RSTV0910_P1_TSCFGL, val: 0x20); |
1194 | |
1195 | write_reg(state, RSTV0910_P1_TSSPEED, val: state->tsspeed); |
1196 | |
1197 | write_reg(state, RSTV0910_P2_TSCFGH, val: state->tscfgh | 0x01); |
1198 | write_reg(state, RSTV0910_P2_TSCFGH, val: state->tscfgh); |
1199 | write_reg(state, RSTV0910_P2_TSCFGM, val: 0xC0); /* Manual speed */ |
1200 | write_reg(state, RSTV0910_P2_TSCFGL, val: 0x20); |
1201 | |
1202 | write_reg(state, RSTV0910_P2_TSSPEED, val: state->tsspeed); |
1203 | |
1204 | /* Reset stream merger */ |
1205 | write_reg(state, RSTV0910_P1_TSCFGH, val: state->tscfgh | 0x01); |
1206 | write_reg(state, RSTV0910_P2_TSCFGH, val: state->tscfgh | 0x01); |
1207 | write_reg(state, RSTV0910_P1_TSCFGH, val: state->tscfgh); |
1208 | write_reg(state, RSTV0910_P2_TSCFGH, val: state->tscfgh); |
1209 | |
1210 | write_reg(state, RSTV0910_P1_I2CRPT, val: state->i2crpt); |
1211 | write_reg(state, RSTV0910_P2_I2CRPT, val: state->i2crpt); |
1212 | |
1213 | write_reg(state, RSTV0910_P1_TSINSDELM, val: 0x17); |
1214 | write_reg(state, RSTV0910_P1_TSINSDELL, val: 0xff); |
1215 | |
1216 | write_reg(state, RSTV0910_P2_TSINSDELM, val: 0x17); |
1217 | write_reg(state, RSTV0910_P2_TSINSDELL, val: 0xff); |
1218 | |
1219 | init_diseqc(state); |
1220 | return 0; |
1221 | } |
1222 | |
1223 | static int gate_ctrl(struct dvb_frontend *fe, int enable) |
1224 | { |
1225 | struct stv *state = fe->demodulator_priv; |
1226 | u8 i2crpt = state->i2crpt & ~0x86; |
1227 | |
1228 | /* |
1229 | * mutex_lock note: Concurrent I2C gate bus accesses must be |
1230 | * prevented (STV0910 = dual demod on a single IC with a single I2C |
1231 | * gate/bus, and two tuners attached), similar to most (if not all) |
1232 | * other I2C host interfaces/buses. |
1233 | * |
1234 | * enable=1 (open I2C gate) will grab the lock |
1235 | * enable=0 (close I2C gate) releases the lock |
1236 | */ |
1237 | |
1238 | if (enable) { |
1239 | mutex_lock(&state->base->i2c_lock); |
1240 | i2crpt |= 0x80; |
1241 | } else { |
1242 | i2crpt |= 0x02; |
1243 | } |
1244 | |
1245 | if (write_reg(state, reg: state->nr ? RSTV0910_P2_I2CRPT : |
1246 | RSTV0910_P1_I2CRPT, val: i2crpt) < 0) { |
1247 | /* don't hold the I2C bus lock on failure */ |
1248 | if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock))) |
1249 | mutex_unlock(lock: &state->base->i2c_lock); |
1250 | dev_err(&state->base->i2c->dev, |
1251 | "%s() write_reg failure (enable=%d)\n" , |
1252 | __func__, enable); |
1253 | return -EIO; |
1254 | } |
1255 | |
1256 | state->i2crpt = i2crpt; |
1257 | |
1258 | if (!enable) |
1259 | if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock))) |
1260 | mutex_unlock(lock: &state->base->i2c_lock); |
1261 | return 0; |
1262 | } |
1263 | |
1264 | static void release(struct dvb_frontend *fe) |
1265 | { |
1266 | struct stv *state = fe->demodulator_priv; |
1267 | |
1268 | state->base->count--; |
1269 | if (state->base->count == 0) { |
1270 | list_del(entry: &state->base->stvlist); |
1271 | kfree(objp: state->base); |
1272 | } |
1273 | kfree(objp: state); |
1274 | } |
1275 | |
1276 | static int set_parameters(struct dvb_frontend *fe) |
1277 | { |
1278 | int stat = 0; |
1279 | struct stv *state = fe->demodulator_priv; |
1280 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
1281 | |
1282 | stop(state); |
1283 | if (fe->ops.tuner_ops.set_params) |
1284 | fe->ops.tuner_ops.set_params(fe); |
1285 | state->symbol_rate = p->symbol_rate; |
1286 | stat = start(state, p); |
1287 | return stat; |
1288 | } |
1289 | |
1290 | static int manage_matype_info(struct stv *state) |
1291 | { |
1292 | if (!state->started) |
1293 | return -EINVAL; |
1294 | if (state->receive_mode == RCVMODE_DVBS2) { |
1295 | u8 [2]; |
1296 | |
1297 | read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff, |
1298 | val: bbheader, len: 2); |
1299 | state->feroll_off = |
1300 | (enum fe_stv0910_roll_off)(bbheader[0] & 0x03); |
1301 | state->is_vcm = (bbheader[0] & 0x10) == 0; |
1302 | state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0; |
1303 | } else if (state->receive_mode == RCVMODE_DVBS) { |
1304 | state->is_vcm = 0; |
1305 | state->is_standard_broadcast = 1; |
1306 | state->feroll_off = FE_SAT_35; |
1307 | } |
1308 | return 0; |
1309 | } |
1310 | |
1311 | static int read_snr(struct dvb_frontend *fe) |
1312 | { |
1313 | struct stv *state = fe->demodulator_priv; |
1314 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
1315 | s32 snrval; |
1316 | |
1317 | if (!get_signal_to_noise(state, signal_to_noise: &snrval)) { |
1318 | p->cnr.stat[0].scale = FE_SCALE_DECIBEL; |
1319 | p->cnr.stat[0].svalue = 100 * snrval; /* fix scale */ |
1320 | } else { |
1321 | p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
1322 | } |
1323 | |
1324 | return 0; |
1325 | } |
1326 | |
1327 | static int read_ber(struct dvb_frontend *fe) |
1328 | { |
1329 | struct stv *state = fe->demodulator_priv; |
1330 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
1331 | u32 n, d; |
1332 | |
1333 | get_bit_error_rate(state, bernumerator: &n, berdenominator: &d); |
1334 | |
1335 | p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; |
1336 | p->pre_bit_error.stat[0].uvalue = n; |
1337 | p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; |
1338 | p->pre_bit_count.stat[0].uvalue = d; |
1339 | |
1340 | return 0; |
1341 | } |
1342 | |
1343 | static void read_signal_strength(struct dvb_frontend *fe) |
1344 | { |
1345 | struct stv *state = fe->demodulator_priv; |
1346 | struct dtv_frontend_properties *p = &state->fe.dtv_property_cache; |
1347 | u8 reg[2]; |
1348 | u16 agc; |
1349 | s32 padc, power = 0; |
1350 | int i; |
1351 | |
1352 | read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, val: reg, len: 2); |
1353 | |
1354 | agc = (((u32)reg[0]) << 8) | reg[1]; |
1355 | |
1356 | for (i = 0; i < 5; i += 1) { |
1357 | read_regs(state, RSTV0910_P2_POWERI + state->regoff, val: reg, len: 2); |
1358 | power += (u32)reg[0] * (u32)reg[0] |
1359 | + (u32)reg[1] * (u32)reg[1]; |
1360 | usleep_range(min: 3000, max: 4000); |
1361 | } |
1362 | power /= 5; |
1363 | |
1364 | padc = table_lookup(table: padc_lookup, ARRAY_SIZE(padc_lookup), reg_value: power) + 352; |
1365 | |
1366 | p->strength.stat[0].scale = FE_SCALE_DECIBEL; |
1367 | p->strength.stat[0].svalue = (padc - agc); |
1368 | } |
1369 | |
1370 | static int read_status(struct dvb_frontend *fe, enum fe_status *status) |
1371 | { |
1372 | struct stv *state = fe->demodulator_priv; |
1373 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
1374 | u8 dmd_state = 0; |
1375 | u8 dstatus = 0; |
1376 | enum receive_mode cur_receive_mode = RCVMODE_NONE; |
1377 | u32 feclock = 0; |
1378 | |
1379 | *status = 0; |
1380 | |
1381 | read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, val: &dmd_state); |
1382 | |
1383 | if (dmd_state & 0x40) { |
1384 | read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, val: &dstatus); |
1385 | if (dstatus & 0x08) |
1386 | cur_receive_mode = (dmd_state & 0x20) ? |
1387 | RCVMODE_DVBS : RCVMODE_DVBS2; |
1388 | } |
1389 | if (cur_receive_mode == RCVMODE_NONE) { |
1390 | set_vth(state); |
1391 | |
1392 | /* reset signal statistics */ |
1393 | p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
1394 | p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
1395 | p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
1396 | p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
1397 | |
1398 | return 0; |
1399 | } |
1400 | |
1401 | *status |= (FE_HAS_SIGNAL |
1402 | | FE_HAS_CARRIER |
1403 | | FE_HAS_VITERBI |
1404 | | FE_HAS_SYNC); |
1405 | |
1406 | if (state->receive_mode == RCVMODE_NONE) { |
1407 | state->receive_mode = cur_receive_mode; |
1408 | state->demod_lock_time = jiffies; |
1409 | state->first_time_lock = 1; |
1410 | |
1411 | get_signal_parameters(state); |
1412 | tracking_optimization(state); |
1413 | |
1414 | write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, |
1415 | val: state->tscfgh); |
1416 | usleep_range(min: 3000, max: 4000); |
1417 | write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, |
1418 | val: state->tscfgh | 0x01); |
1419 | write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, |
1420 | val: state->tscfgh); |
1421 | } |
1422 | if (dmd_state & 0x40) { |
1423 | if (state->receive_mode == RCVMODE_DVBS2) { |
1424 | u8 pdelstatus; |
1425 | |
1426 | read_reg(state, |
1427 | RSTV0910_P2_PDELSTATUS1 + state->regoff, |
1428 | val: &pdelstatus); |
1429 | feclock = (pdelstatus & 0x02) != 0; |
1430 | } else { |
1431 | u8 vstatus; |
1432 | |
1433 | read_reg(state, |
1434 | RSTV0910_P2_VSTATUSVIT + state->regoff, |
1435 | val: &vstatus); |
1436 | feclock = (vstatus & 0x08) != 0; |
1437 | } |
1438 | } |
1439 | |
1440 | if (feclock) { |
1441 | *status |= FE_HAS_LOCK; |
1442 | |
1443 | if (state->first_time_lock) { |
1444 | u8 tmp; |
1445 | |
1446 | state->first_time_lock = 0; |
1447 | |
1448 | manage_matype_info(state); |
1449 | |
1450 | if (state->receive_mode == RCVMODE_DVBS2) { |
1451 | /* |
1452 | * FSTV0910_P2_MANUALSX_ROLLOFF, |
1453 | * FSTV0910_P2_MANUALS2_ROLLOFF = 0 |
1454 | */ |
1455 | state->demod_bits &= ~0x84; |
1456 | write_reg(state, |
1457 | RSTV0910_P2_DEMOD + state->regoff, |
1458 | val: state->demod_bits); |
1459 | read_reg(state, |
1460 | RSTV0910_P2_PDELCTRL2 + state->regoff, |
1461 | val: &tmp); |
1462 | /* reset DVBS2 packet delinator error counter */ |
1463 | tmp |= 0x40; |
1464 | write_reg(state, |
1465 | RSTV0910_P2_PDELCTRL2 + state->regoff, |
1466 | val: tmp); |
1467 | /* reset DVBS2 packet delinator error counter */ |
1468 | tmp &= ~0x40; |
1469 | write_reg(state, |
1470 | RSTV0910_P2_PDELCTRL2 + state->regoff, |
1471 | val: tmp); |
1472 | |
1473 | state->berscale = 2; |
1474 | state->last_bernumerator = 0; |
1475 | state->last_berdenominator = 1; |
1476 | /* force to PRE BCH Rate */ |
1477 | write_reg(state, |
1478 | RSTV0910_P2_ERRCTRL1 + state->regoff, |
1479 | BER_SRC_S2 | state->berscale); |
1480 | } else { |
1481 | state->berscale = 2; |
1482 | state->last_bernumerator = 0; |
1483 | state->last_berdenominator = 1; |
1484 | /* force to PRE RS Rate */ |
1485 | write_reg(state, |
1486 | RSTV0910_P2_ERRCTRL1 + state->regoff, |
1487 | BER_SRC_S | state->berscale); |
1488 | } |
1489 | /* Reset the Total packet counter */ |
1490 | write_reg(state, |
1491 | RSTV0910_P2_FBERCPT4 + state->regoff, val: 0x00); |
1492 | /* |
1493 | * Reset the packet Error counter2 (and Set it to |
1494 | * infinite error count mode) |
1495 | */ |
1496 | write_reg(state, |
1497 | RSTV0910_P2_ERRCTRL2 + state->regoff, val: 0xc1); |
1498 | |
1499 | set_vth_default(state); |
1500 | if (state->receive_mode == RCVMODE_DVBS) |
1501 | enable_puncture_rate(state, |
1502 | rate: state->puncture_rate); |
1503 | } |
1504 | |
1505 | /* Use highest signaled ModCod for quality */ |
1506 | if (state->is_vcm) { |
1507 | u8 tmp; |
1508 | enum fe_stv0910_mod_cod mod_cod; |
1509 | |
1510 | read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, |
1511 | val: &tmp); |
1512 | mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2); |
1513 | |
1514 | if (mod_cod > state->mod_cod) |
1515 | state->mod_cod = mod_cod; |
1516 | } |
1517 | } |
1518 | |
1519 | /* read signal statistics */ |
1520 | |
1521 | /* read signal strength */ |
1522 | read_signal_strength(fe); |
1523 | |
1524 | /* read carrier/noise on FE_HAS_CARRIER */ |
1525 | if (*status & FE_HAS_CARRIER) |
1526 | read_snr(fe); |
1527 | else |
1528 | p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
1529 | |
1530 | /* read ber */ |
1531 | if (*status & FE_HAS_VITERBI) { |
1532 | read_ber(fe); |
1533 | } else { |
1534 | p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
1535 | p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
1536 | } |
1537 | |
1538 | return 0; |
1539 | } |
1540 | |
1541 | static int get_frontend(struct dvb_frontend *fe, |
1542 | struct dtv_frontend_properties *p) |
1543 | { |
1544 | struct stv *state = fe->demodulator_priv; |
1545 | u8 tmp; |
1546 | u32 symbolrate; |
1547 | |
1548 | if (state->receive_mode == RCVMODE_DVBS2) { |
1549 | u32 mc; |
1550 | const enum fe_modulation modcod2mod[0x20] = { |
1551 | QPSK, QPSK, QPSK, QPSK, |
1552 | QPSK, QPSK, QPSK, QPSK, |
1553 | QPSK, QPSK, QPSK, QPSK, |
1554 | PSK_8, PSK_8, PSK_8, PSK_8, |
1555 | PSK_8, PSK_8, APSK_16, APSK_16, |
1556 | APSK_16, APSK_16, APSK_16, APSK_16, |
1557 | APSK_32, APSK_32, APSK_32, APSK_32, |
1558 | APSK_32, |
1559 | }; |
1560 | const enum fe_code_rate modcod2fec[0x20] = { |
1561 | FEC_NONE, FEC_NONE, FEC_NONE, FEC_2_5, |
1562 | FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4, |
1563 | FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10, |
1564 | FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6, |
1565 | FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4, |
1566 | FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10, |
1567 | FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9, |
1568 | FEC_9_10 |
1569 | }; |
1570 | read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, val: &tmp); |
1571 | mc = ((tmp & 0x7c) >> 2); |
1572 | p->pilot = (tmp & 0x01) ? PILOT_ON : PILOT_OFF; |
1573 | p->modulation = modcod2mod[mc]; |
1574 | p->fec_inner = modcod2fec[mc]; |
1575 | } else if (state->receive_mode == RCVMODE_DVBS) { |
1576 | read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, val: &tmp); |
1577 | switch (tmp & 0x1F) { |
1578 | case 0x0d: |
1579 | p->fec_inner = FEC_1_2; |
1580 | break; |
1581 | case 0x12: |
1582 | p->fec_inner = FEC_2_3; |
1583 | break; |
1584 | case 0x15: |
1585 | p->fec_inner = FEC_3_4; |
1586 | break; |
1587 | case 0x18: |
1588 | p->fec_inner = FEC_5_6; |
1589 | break; |
1590 | case 0x1a: |
1591 | p->fec_inner = FEC_7_8; |
1592 | break; |
1593 | default: |
1594 | p->fec_inner = FEC_NONE; |
1595 | break; |
1596 | } |
1597 | p->rolloff = ROLLOFF_35; |
1598 | } |
1599 | |
1600 | if (state->receive_mode != RCVMODE_NONE) { |
1601 | get_cur_symbol_rate(state, p_symbol_rate: &symbolrate); |
1602 | p->symbol_rate = symbolrate; |
1603 | } |
1604 | return 0; |
1605 | } |
1606 | |
1607 | static int tune(struct dvb_frontend *fe, bool re_tune, |
1608 | unsigned int mode_flags, |
1609 | unsigned int *delay, enum fe_status *status) |
1610 | { |
1611 | struct stv *state = fe->demodulator_priv; |
1612 | int r; |
1613 | |
1614 | if (re_tune) { |
1615 | r = set_parameters(fe); |
1616 | if (r) |
1617 | return r; |
1618 | state->tune_time = jiffies; |
1619 | } |
1620 | |
1621 | r = read_status(fe, status); |
1622 | if (r) |
1623 | return r; |
1624 | |
1625 | if (*status & FE_HAS_LOCK) |
1626 | return 0; |
1627 | *delay = HZ; |
1628 | |
1629 | return 0; |
1630 | } |
1631 | |
1632 | static enum dvbfe_algo get_algo(struct dvb_frontend *fe) |
1633 | { |
1634 | return DVBFE_ALGO_HW; |
1635 | } |
1636 | |
1637 | static int set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone) |
1638 | { |
1639 | struct stv *state = fe->demodulator_priv; |
1640 | u16 offs = state->nr ? 0x40 : 0; |
1641 | |
1642 | switch (tone) { |
1643 | case SEC_TONE_ON: |
1644 | return write_reg(state, RSTV0910_P1_DISTXCFG + offs, val: 0x38); |
1645 | case SEC_TONE_OFF: |
1646 | return write_reg(state, RSTV0910_P1_DISTXCFG + offs, val: 0x3a); |
1647 | default: |
1648 | break; |
1649 | } |
1650 | return -EINVAL; |
1651 | } |
1652 | |
1653 | static int wait_dis(struct stv *state, u8 flag, u8 val) |
1654 | { |
1655 | int i; |
1656 | u8 stat; |
1657 | u16 offs = state->nr ? 0x40 : 0; |
1658 | |
1659 | for (i = 0; i < 10; i++) { |
1660 | read_reg(state, RSTV0910_P1_DISTXSTATUS + offs, val: &stat); |
1661 | if ((stat & flag) == val) |
1662 | return 0; |
1663 | usleep_range(min: 10000, max: 11000); |
1664 | } |
1665 | return -ETIMEDOUT; |
1666 | } |
1667 | |
1668 | static int send_master_cmd(struct dvb_frontend *fe, |
1669 | struct dvb_diseqc_master_cmd *cmd) |
1670 | { |
1671 | struct stv *state = fe->demodulator_priv; |
1672 | int i; |
1673 | |
1674 | SET_FIELD(DISEQC_MODE, 2); |
1675 | SET_FIELD(DIS_PRECHARGE, 1); |
1676 | for (i = 0; i < cmd->msg_len; i++) { |
1677 | wait_dis(state, flag: 0x40, val: 0x00); |
1678 | SET_REG(DISTXFIFO, cmd->msg[i]); |
1679 | } |
1680 | SET_FIELD(DIS_PRECHARGE, 0); |
1681 | wait_dis(state, flag: 0x20, val: 0x20); |
1682 | return 0; |
1683 | } |
1684 | |
1685 | static int send_burst(struct dvb_frontend *fe, enum fe_sec_mini_cmd burst) |
1686 | { |
1687 | struct stv *state = fe->demodulator_priv; |
1688 | u8 value; |
1689 | |
1690 | if (burst == SEC_MINI_A) { |
1691 | SET_FIELD(DISEQC_MODE, 3); |
1692 | value = 0x00; |
1693 | } else { |
1694 | SET_FIELD(DISEQC_MODE, 2); |
1695 | value = 0xFF; |
1696 | } |
1697 | |
1698 | SET_FIELD(DIS_PRECHARGE, 1); |
1699 | wait_dis(state, flag: 0x40, val: 0x00); |
1700 | SET_REG(DISTXFIFO, value); |
1701 | SET_FIELD(DIS_PRECHARGE, 0); |
1702 | wait_dis(state, flag: 0x20, val: 0x20); |
1703 | |
1704 | return 0; |
1705 | } |
1706 | |
1707 | static int sleep(struct dvb_frontend *fe) |
1708 | { |
1709 | struct stv *state = fe->demodulator_priv; |
1710 | |
1711 | stop(state); |
1712 | return 0; |
1713 | } |
1714 | |
1715 | static const struct dvb_frontend_ops stv0910_ops = { |
1716 | .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, |
1717 | .info = { |
1718 | .name = "ST STV0910" , |
1719 | .frequency_min_hz = 950 * MHz, |
1720 | .frequency_max_hz = 2150 * MHz, |
1721 | .symbol_rate_min = 100000, |
1722 | .symbol_rate_max = 70000000, |
1723 | .caps = FE_CAN_INVERSION_AUTO | |
1724 | FE_CAN_FEC_AUTO | |
1725 | FE_CAN_QPSK | |
1726 | FE_CAN_2G_MODULATION | |
1727 | FE_CAN_MULTISTREAM |
1728 | }, |
1729 | .sleep = sleep, |
1730 | .release = release, |
1731 | .i2c_gate_ctrl = gate_ctrl, |
1732 | .set_frontend = set_parameters, |
1733 | .get_frontend_algo = get_algo, |
1734 | .get_frontend = get_frontend, |
1735 | .tune = tune, |
1736 | .read_status = read_status, |
1737 | .set_tone = set_tone, |
1738 | |
1739 | .diseqc_send_master_cmd = send_master_cmd, |
1740 | .diseqc_send_burst = send_burst, |
1741 | }; |
1742 | |
1743 | static struct stv_base *match_base(struct i2c_adapter *i2c, u8 adr) |
1744 | { |
1745 | struct stv_base *p; |
1746 | |
1747 | list_for_each_entry(p, &stvlist, stvlist) |
1748 | if (p->i2c == i2c && p->adr == adr) |
1749 | return p; |
1750 | return NULL; |
1751 | } |
1752 | |
1753 | static void stv0910_init_stats(struct stv *state) |
1754 | { |
1755 | struct dtv_frontend_properties *p = &state->fe.dtv_property_cache; |
1756 | |
1757 | p->strength.len = 1; |
1758 | p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
1759 | p->cnr.len = 1; |
1760 | p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
1761 | p->pre_bit_error.len = 1; |
1762 | p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
1763 | p->pre_bit_count.len = 1; |
1764 | p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
1765 | } |
1766 | |
1767 | struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c, |
1768 | struct stv0910_cfg *cfg, |
1769 | int nr) |
1770 | { |
1771 | struct stv *state; |
1772 | struct stv_base *base; |
1773 | |
1774 | state = kzalloc(size: sizeof(*state), GFP_KERNEL); |
1775 | if (!state) |
1776 | return NULL; |
1777 | |
1778 | state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40); |
1779 | state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00; |
1780 | state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4); |
1781 | /* use safe tsspeed value if unspecified through stv0910_cfg */ |
1782 | state->tsspeed = (cfg->tsspeed ? cfg->tsspeed : 0x28); |
1783 | state->nr = nr; |
1784 | state->regoff = state->nr ? 0 : 0x200; |
1785 | state->search_range = 16000000; |
1786 | state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */ |
1787 | state->receive_mode = RCVMODE_NONE; |
1788 | state->cur_scrambling_code = (~0U); |
1789 | state->single = cfg->single ? 1 : 0; |
1790 | |
1791 | base = match_base(i2c, adr: cfg->adr); |
1792 | if (base) { |
1793 | base->count++; |
1794 | state->base = base; |
1795 | } else { |
1796 | base = kzalloc(size: sizeof(*base), GFP_KERNEL); |
1797 | if (!base) |
1798 | goto fail; |
1799 | base->i2c = i2c; |
1800 | base->adr = cfg->adr; |
1801 | base->count = 1; |
1802 | base->extclk = cfg->clk ? cfg->clk : 30000000; |
1803 | |
1804 | mutex_init(&base->i2c_lock); |
1805 | mutex_init(&base->reg_lock); |
1806 | state->base = base; |
1807 | if (probe(state) < 0) { |
1808 | dev_info(&i2c->dev, "No demod found at adr %02X on %s\n" , |
1809 | cfg->adr, dev_name(&i2c->dev)); |
1810 | kfree(objp: base); |
1811 | goto fail; |
1812 | } |
1813 | list_add(new: &base->stvlist, head: &stvlist); |
1814 | } |
1815 | state->fe.ops = stv0910_ops; |
1816 | state->fe.demodulator_priv = state; |
1817 | state->nr = nr; |
1818 | |
1819 | dev_info(&i2c->dev, "%s demod found at adr %02X on %s\n" , |
1820 | state->fe.ops.info.name, cfg->adr, dev_name(&i2c->dev)); |
1821 | |
1822 | stv0910_init_stats(state); |
1823 | |
1824 | return &state->fe; |
1825 | |
1826 | fail: |
1827 | kfree(objp: state); |
1828 | return NULL; |
1829 | } |
1830 | EXPORT_SYMBOL_GPL(stv0910_attach); |
1831 | |
1832 | MODULE_DESCRIPTION("ST STV0910 multistandard frontend driver" ); |
1833 | MODULE_AUTHOR("Ralph and Marcus Metzler, Manfred Voelkel" ); |
1834 | MODULE_LICENSE("GPL v2" ); |
1835 | |