1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | Driver for Philips tda1004xh OFDM Demodulator |
4 | |
5 | (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach |
6 | |
7 | |
8 | */ |
9 | /* |
10 | * This driver needs external firmware. Please use the commands |
11 | * "<kerneldir>/scripts/get_dvb_firmware tda10045", |
12 | * "<kerneldir>/scripts/get_dvb_firmware tda10046" to |
13 | * download/extract them, and then copy them to /usr/lib/hotplug/firmware |
14 | * or /lib/firmware (depending on configuration of firmware hotplug). |
15 | */ |
16 | #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw" |
17 | #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw" |
18 | |
19 | #include <linux/init.h> |
20 | #include <linux/module.h> |
21 | #include <linux/device.h> |
22 | #include <linux/jiffies.h> |
23 | #include <linux/string.h> |
24 | #include <linux/slab.h> |
25 | |
26 | #include <media/dvb_frontend.h> |
27 | #include "tda1004x.h" |
28 | |
29 | static int debug; |
30 | #define dprintk(args...) \ |
31 | do { \ |
32 | if (debug) printk(KERN_DEBUG "tda1004x: " args); \ |
33 | } while (0) |
34 | |
35 | #define TDA1004X_CHIPID 0x00 |
36 | #define TDA1004X_AUTO 0x01 |
37 | #define TDA1004X_IN_CONF1 0x02 |
38 | #define TDA1004X_IN_CONF2 0x03 |
39 | #define TDA1004X_OUT_CONF1 0x04 |
40 | #define TDA1004X_OUT_CONF2 0x05 |
41 | #define TDA1004X_STATUS_CD 0x06 |
42 | #define TDA1004X_CONFC4 0x07 |
43 | #define TDA1004X_DSSPARE2 0x0C |
44 | #define TDA10045H_CODE_IN 0x0D |
45 | #define TDA10045H_FWPAGE 0x0E |
46 | #define TDA1004X_SCAN_CPT 0x10 |
47 | #define TDA1004X_DSP_CMD 0x11 |
48 | #define TDA1004X_DSP_ARG 0x12 |
49 | #define TDA1004X_DSP_DATA1 0x13 |
50 | #define TDA1004X_DSP_DATA2 0x14 |
51 | #define TDA1004X_CONFADC1 0x15 |
52 | #define TDA1004X_CONFC1 0x16 |
53 | #define TDA10045H_S_AGC 0x1a |
54 | #define TDA10046H_AGC_TUN_LEVEL 0x1a |
55 | #define TDA1004X_SNR 0x1c |
56 | #define TDA1004X_CONF_TS1 0x1e |
57 | #define TDA1004X_CONF_TS2 0x1f |
58 | #define TDA1004X_CBER_RESET 0x20 |
59 | #define TDA1004X_CBER_MSB 0x21 |
60 | #define TDA1004X_CBER_LSB 0x22 |
61 | #define TDA1004X_CVBER_LUT 0x23 |
62 | #define TDA1004X_VBER_MSB 0x24 |
63 | #define TDA1004X_VBER_MID 0x25 |
64 | #define TDA1004X_VBER_LSB 0x26 |
65 | #define TDA1004X_UNCOR 0x27 |
66 | |
67 | #define TDA10045H_CONFPLL_P 0x2D |
68 | #define TDA10045H_CONFPLL_M_MSB 0x2E |
69 | #define TDA10045H_CONFPLL_M_LSB 0x2F |
70 | #define TDA10045H_CONFPLL_N 0x30 |
71 | |
72 | #define TDA10046H_CONFPLL1 0x2D |
73 | #define TDA10046H_CONFPLL2 0x2F |
74 | #define TDA10046H_CONFPLL3 0x30 |
75 | #define TDA10046H_TIME_WREF1 0x31 |
76 | #define TDA10046H_TIME_WREF2 0x32 |
77 | #define TDA10046H_TIME_WREF3 0x33 |
78 | #define TDA10046H_TIME_WREF4 0x34 |
79 | #define TDA10046H_TIME_WREF5 0x35 |
80 | |
81 | #define TDA10045H_UNSURW_MSB 0x31 |
82 | #define TDA10045H_UNSURW_LSB 0x32 |
83 | #define TDA10045H_WREF_MSB 0x33 |
84 | #define TDA10045H_WREF_MID 0x34 |
85 | #define TDA10045H_WREF_LSB 0x35 |
86 | #define TDA10045H_MUXOUT 0x36 |
87 | #define TDA1004X_CONFADC2 0x37 |
88 | |
89 | #define TDA10045H_IOFFSET 0x38 |
90 | |
91 | #define TDA10046H_CONF_TRISTATE1 0x3B |
92 | #define TDA10046H_CONF_TRISTATE2 0x3C |
93 | #define TDA10046H_CONF_POLARITY 0x3D |
94 | #define TDA10046H_FREQ_OFFSET 0x3E |
95 | #define TDA10046H_GPIO_OUT_SEL 0x41 |
96 | #define TDA10046H_GPIO_SELECT 0x42 |
97 | #define TDA10046H_AGC_CONF 0x43 |
98 | #define TDA10046H_AGC_THR 0x44 |
99 | #define TDA10046H_AGC_RENORM 0x45 |
100 | #define TDA10046H_AGC_GAINS 0x46 |
101 | #define TDA10046H_AGC_TUN_MIN 0x47 |
102 | #define TDA10046H_AGC_TUN_MAX 0x48 |
103 | #define TDA10046H_AGC_IF_MIN 0x49 |
104 | #define TDA10046H_AGC_IF_MAX 0x4A |
105 | |
106 | #define TDA10046H_FREQ_PHY2_MSB 0x4D |
107 | #define TDA10046H_FREQ_PHY2_LSB 0x4E |
108 | |
109 | #define TDA10046H_CVBER_CTRL 0x4F |
110 | #define TDA10046H_AGC_IF_LEVEL 0x52 |
111 | #define TDA10046H_CODE_CPT 0x57 |
112 | #define TDA10046H_CODE_IN 0x58 |
113 | |
114 | |
115 | static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data) |
116 | { |
117 | int ret; |
118 | u8 buf[] = { reg, data }; |
119 | struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 }; |
120 | |
121 | dprintk("%s: reg=0x%x, data=0x%x\n" , __func__, reg, data); |
122 | |
123 | msg.addr = state->config->demod_address; |
124 | ret = i2c_transfer(adap: state->i2c, msgs: &msg, num: 1); |
125 | |
126 | if (ret != 1) |
127 | dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n" , |
128 | __func__, reg, data, ret); |
129 | |
130 | dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n" , __func__, |
131 | reg, data, ret); |
132 | return (ret != 1) ? -1 : 0; |
133 | } |
134 | |
135 | static int tda1004x_read_byte(struct tda1004x_state *state, int reg) |
136 | { |
137 | int ret; |
138 | u8 b0[] = { reg }; |
139 | u8 b1[] = { 0 }; |
140 | struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 }, |
141 | { .flags = I2C_M_RD, .buf = b1, .len = 1 }}; |
142 | |
143 | dprintk("%s: reg=0x%x\n" , __func__, reg); |
144 | |
145 | msg[0].addr = state->config->demod_address; |
146 | msg[1].addr = state->config->demod_address; |
147 | ret = i2c_transfer(adap: state->i2c, msgs: msg, num: 2); |
148 | |
149 | if (ret != 2) { |
150 | dprintk("%s: error reg=0x%x, ret=%i\n" , __func__, reg, |
151 | ret); |
152 | return -EINVAL; |
153 | } |
154 | |
155 | dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n" , __func__, |
156 | reg, b1[0], ret); |
157 | return b1[0]; |
158 | } |
159 | |
160 | static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data) |
161 | { |
162 | int val; |
163 | dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n" , __func__, reg, |
164 | mask, data); |
165 | |
166 | // read a byte and check |
167 | val = tda1004x_read_byte(state, reg); |
168 | if (val < 0) |
169 | return val; |
170 | |
171 | // mask if off |
172 | val = val & ~mask; |
173 | val |= data & 0xff; |
174 | |
175 | // write it out again |
176 | return tda1004x_write_byteI(state, reg, data: val); |
177 | } |
178 | |
179 | static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len) |
180 | { |
181 | int i; |
182 | int result; |
183 | |
184 | dprintk("%s: reg=0x%x, len=0x%x\n" , __func__, reg, len); |
185 | |
186 | result = 0; |
187 | for (i = 0; i < len; i++) { |
188 | result = tda1004x_write_byteI(state, reg: reg + i, data: buf[i]); |
189 | if (result != 0) |
190 | break; |
191 | } |
192 | |
193 | return result; |
194 | } |
195 | |
196 | static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state) |
197 | { |
198 | int result; |
199 | dprintk("%s\n" , __func__); |
200 | |
201 | result = tda1004x_write_mask(state, TDA1004X_CONFC4, mask: 2, data: 2); |
202 | msleep(msecs: 20); |
203 | return result; |
204 | } |
205 | |
206 | static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state) |
207 | { |
208 | dprintk("%s\n" , __func__); |
209 | |
210 | return tda1004x_write_mask(state, TDA1004X_CONFC4, mask: 2, data: 0); |
211 | } |
212 | |
213 | static int tda10045h_set_bandwidth(struct tda1004x_state *state, |
214 | u32 bandwidth) |
215 | { |
216 | static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f }; |
217 | static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb }; |
218 | static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 }; |
219 | |
220 | switch (bandwidth) { |
221 | case 6000000: |
222 | tda1004x_write_buf(state, TDA10045H_CONFPLL_P, buf: bandwidth_6mhz, len: sizeof(bandwidth_6mhz)); |
223 | break; |
224 | |
225 | case 7000000: |
226 | tda1004x_write_buf(state, TDA10045H_CONFPLL_P, buf: bandwidth_7mhz, len: sizeof(bandwidth_7mhz)); |
227 | break; |
228 | |
229 | case 8000000: |
230 | tda1004x_write_buf(state, TDA10045H_CONFPLL_P, buf: bandwidth_8mhz, len: sizeof(bandwidth_8mhz)); |
231 | break; |
232 | |
233 | default: |
234 | return -EINVAL; |
235 | } |
236 | |
237 | tda1004x_write_byteI(state, TDA10045H_IOFFSET, data: 0); |
238 | |
239 | return 0; |
240 | } |
241 | |
242 | static int tda10046h_set_bandwidth(struct tda1004x_state *state, |
243 | u32 bandwidth) |
244 | { |
245 | static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 }; |
246 | static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f }; |
247 | static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d }; |
248 | |
249 | static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 }; |
250 | static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab }; |
251 | static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 }; |
252 | int tda10046_clk53m; |
253 | |
254 | if ((state->config->if_freq == TDA10046_FREQ_045) || |
255 | (state->config->if_freq == TDA10046_FREQ_052)) |
256 | tda10046_clk53m = 0; |
257 | else |
258 | tda10046_clk53m = 1; |
259 | switch (bandwidth) { |
260 | case 6000000: |
261 | if (tda10046_clk53m) |
262 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, buf: bandwidth_6mhz_53M, |
263 | len: sizeof(bandwidth_6mhz_53M)); |
264 | else |
265 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, buf: bandwidth_6mhz_48M, |
266 | len: sizeof(bandwidth_6mhz_48M)); |
267 | if (state->config->if_freq == TDA10046_FREQ_045) { |
268 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, data: 0x0a); |
269 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, data: 0xab); |
270 | } |
271 | break; |
272 | |
273 | case 7000000: |
274 | if (tda10046_clk53m) |
275 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, buf: bandwidth_7mhz_53M, |
276 | len: sizeof(bandwidth_7mhz_53M)); |
277 | else |
278 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, buf: bandwidth_7mhz_48M, |
279 | len: sizeof(bandwidth_7mhz_48M)); |
280 | if (state->config->if_freq == TDA10046_FREQ_045) { |
281 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, data: 0x0c); |
282 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, data: 0x00); |
283 | } |
284 | break; |
285 | |
286 | case 8000000: |
287 | if (tda10046_clk53m) |
288 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, buf: bandwidth_8mhz_53M, |
289 | len: sizeof(bandwidth_8mhz_53M)); |
290 | else |
291 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, buf: bandwidth_8mhz_48M, |
292 | len: sizeof(bandwidth_8mhz_48M)); |
293 | if (state->config->if_freq == TDA10046_FREQ_045) { |
294 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, data: 0x0d); |
295 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, data: 0x55); |
296 | } |
297 | break; |
298 | |
299 | default: |
300 | return -EINVAL; |
301 | } |
302 | |
303 | return 0; |
304 | } |
305 | |
306 | static int tda1004x_do_upload(struct tda1004x_state *state, |
307 | const unsigned char *mem, unsigned int len, |
308 | u8 dspCodeCounterReg, u8 dspCodeInReg) |
309 | { |
310 | u8 buf[65]; |
311 | struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 }; |
312 | int tx_size; |
313 | int pos = 0; |
314 | |
315 | /* clear code counter */ |
316 | tda1004x_write_byteI(state, reg: dspCodeCounterReg, data: 0); |
317 | fw_msg.addr = state->config->demod_address; |
318 | |
319 | i2c_lock_bus(adapter: state->i2c, I2C_LOCK_SEGMENT); |
320 | buf[0] = dspCodeInReg; |
321 | while (pos != len) { |
322 | // work out how much to send this time |
323 | tx_size = len - pos; |
324 | if (tx_size > 0x10) |
325 | tx_size = 0x10; |
326 | |
327 | // send the chunk |
328 | memcpy(buf + 1, mem + pos, tx_size); |
329 | fw_msg.len = tx_size + 1; |
330 | if (__i2c_transfer(adap: state->i2c, msgs: &fw_msg, num: 1) != 1) { |
331 | printk(KERN_ERR "tda1004x: Error during firmware upload\n" ); |
332 | i2c_unlock_bus(adapter: state->i2c, I2C_LOCK_SEGMENT); |
333 | return -EIO; |
334 | } |
335 | pos += tx_size; |
336 | |
337 | dprintk("%s: fw_pos=0x%x\n" , __func__, pos); |
338 | } |
339 | i2c_unlock_bus(adapter: state->i2c, I2C_LOCK_SEGMENT); |
340 | |
341 | /* give the DSP a chance to settle 03/10/05 Hac */ |
342 | msleep(msecs: 100); |
343 | |
344 | return 0; |
345 | } |
346 | |
347 | static int tda1004x_check_upload_ok(struct tda1004x_state *state) |
348 | { |
349 | u8 data1, data2; |
350 | unsigned long timeout; |
351 | |
352 | if (state->demod_type == TDA1004X_DEMOD_TDA10046) { |
353 | timeout = jiffies + 2 * HZ; |
354 | while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) { |
355 | if (time_after(jiffies, timeout)) { |
356 | printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n" ); |
357 | break; |
358 | } |
359 | msleep(msecs: 1); |
360 | } |
361 | } else |
362 | msleep(msecs: 100); |
363 | |
364 | // check upload was OK |
365 | tda1004x_write_mask(state, TDA1004X_CONFC4, mask: 0x10, data: 0); // we want to read from the DSP |
366 | tda1004x_write_byteI(state, TDA1004X_DSP_CMD, data: 0x67); |
367 | |
368 | data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1); |
369 | data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2); |
370 | if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) { |
371 | printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n" , data2); |
372 | return -EIO; |
373 | } |
374 | printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n" , data2); |
375 | return 0; |
376 | } |
377 | |
378 | static int tda10045_fwupload(struct dvb_frontend* fe) |
379 | { |
380 | struct tda1004x_state* state = fe->demodulator_priv; |
381 | int ret; |
382 | const struct firmware *fw; |
383 | |
384 | /* don't re-upload unless necessary */ |
385 | if (tda1004x_check_upload_ok(state) == 0) |
386 | return 0; |
387 | |
388 | /* request the firmware, this will block until someone uploads it */ |
389 | printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n" , TDA10045_DEFAULT_FIRMWARE); |
390 | ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); |
391 | if (ret) { |
392 | printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n" ); |
393 | return ret; |
394 | } |
395 | |
396 | /* reset chip */ |
397 | tda1004x_write_mask(state, TDA1004X_CONFC4, mask: 0x10, data: 0); |
398 | tda1004x_write_mask(state, TDA1004X_CONFC4, mask: 8, data: 8); |
399 | tda1004x_write_mask(state, TDA1004X_CONFC4, mask: 8, data: 0); |
400 | msleep(msecs: 10); |
401 | |
402 | /* set parameters */ |
403 | tda10045h_set_bandwidth(state, bandwidth: 8000000); |
404 | |
405 | ret = tda1004x_do_upload(state, mem: fw->data, len: fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN); |
406 | release_firmware(fw); |
407 | if (ret) |
408 | return ret; |
409 | printk(KERN_INFO "tda1004x: firmware upload complete\n" ); |
410 | |
411 | /* wait for DSP to initialise */ |
412 | /* DSPREADY doesn't seem to work on the TDA10045H */ |
413 | msleep(msecs: 100); |
414 | |
415 | return tda1004x_check_upload_ok(state); |
416 | } |
417 | |
418 | static void tda10046_init_plls(struct dvb_frontend* fe) |
419 | { |
420 | struct tda1004x_state* state = fe->demodulator_priv; |
421 | int tda10046_clk53m; |
422 | |
423 | if ((state->config->if_freq == TDA10046_FREQ_045) || |
424 | (state->config->if_freq == TDA10046_FREQ_052)) |
425 | tda10046_clk53m = 0; |
426 | else |
427 | tda10046_clk53m = 1; |
428 | |
429 | tda1004x_write_byteI(state, TDA10046H_CONFPLL1, data: 0xf0); |
430 | if(tda10046_clk53m) { |
431 | printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n" ); |
432 | tda1004x_write_byteI(state, TDA10046H_CONFPLL2, data: 0x08); // PLL M = 8 |
433 | } else { |
434 | printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n" ); |
435 | tda1004x_write_byteI(state, TDA10046H_CONFPLL2, data: 0x03); // PLL M = 3 |
436 | } |
437 | if (state->config->xtal_freq == TDA10046_XTAL_4M ) { |
438 | dprintk("%s: setting up PLLs for a 4 MHz Xtal\n" , __func__); |
439 | tda1004x_write_byteI(state, TDA10046H_CONFPLL3, data: 0); // PLL P = N = 0 |
440 | } else { |
441 | dprintk("%s: setting up PLLs for a 16 MHz Xtal\n" , __func__); |
442 | tda1004x_write_byteI(state, TDA10046H_CONFPLL3, data: 3); // PLL P = 0, N = 3 |
443 | } |
444 | if(tda10046_clk53m) |
445 | tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, data: 0x67); |
446 | else |
447 | tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, data: 0x72); |
448 | /* Note clock frequency is handled implicitly */ |
449 | switch (state->config->if_freq) { |
450 | case TDA10046_FREQ_045: |
451 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, data: 0x0c); |
452 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, data: 0x00); |
453 | break; |
454 | case TDA10046_FREQ_052: |
455 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, data: 0x0d); |
456 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, data: 0xc7); |
457 | break; |
458 | case TDA10046_FREQ_3617: |
459 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, data: 0xd7); |
460 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, data: 0x59); |
461 | break; |
462 | case TDA10046_FREQ_3613: |
463 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, data: 0xd7); |
464 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, data: 0x3f); |
465 | break; |
466 | } |
467 | tda10046h_set_bandwidth(state, bandwidth: 8000000); /* default bandwidth 8 MHz */ |
468 | /* let the PLLs settle */ |
469 | msleep(msecs: 120); |
470 | } |
471 | |
472 | static int tda10046_fwupload(struct dvb_frontend* fe) |
473 | { |
474 | struct tda1004x_state* state = fe->demodulator_priv; |
475 | int ret, confc4; |
476 | const struct firmware *fw; |
477 | |
478 | /* reset + wake up chip */ |
479 | if (state->config->xtal_freq == TDA10046_XTAL_4M) { |
480 | confc4 = 0; |
481 | } else { |
482 | dprintk("%s: 16MHz Xtal, reducing I2C speed\n" , __func__); |
483 | confc4 = 0x80; |
484 | } |
485 | tda1004x_write_byteI(state, TDA1004X_CONFC4, data: confc4); |
486 | |
487 | tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, mask: 1, data: 0); |
488 | /* set GPIO 1 and 3 */ |
489 | if (state->config->gpio_config != TDA10046_GPTRI) { |
490 | tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, data: 0x33); |
491 | tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, mask: 0x0f, data: state->config->gpio_config &0x0f); |
492 | } |
493 | /* let the clocks recover from sleep */ |
494 | msleep(msecs: 10); |
495 | |
496 | /* The PLLs need to be reprogrammed after sleep */ |
497 | tda10046_init_plls(fe); |
498 | tda1004x_write_mask(state, TDA1004X_CONFADC2, mask: 0xc0, data: 0); |
499 | |
500 | /* don't re-upload unless necessary */ |
501 | if (tda1004x_check_upload_ok(state) == 0) |
502 | return 0; |
503 | |
504 | /* |
505 | For i2c normal work, we need to slow down the bus speed. |
506 | However, the slow down breaks the eeprom firmware load. |
507 | So, use normal speed for eeprom booting and then restore the |
508 | i2c speed after that. Tested with MSI TV @nyware A/D board, |
509 | that comes with firmware version 29 inside their eeprom. |
510 | |
511 | It should also be noticed that no other I2C transfer should |
512 | be in course while booting from eeprom, otherwise, tda10046 |
513 | goes into an instable state. So, proper locking are needed |
514 | at the i2c bus master. |
515 | */ |
516 | printk(KERN_INFO "tda1004x: trying to boot from eeprom\n" ); |
517 | tda1004x_write_byteI(state, TDA1004X_CONFC4, data: 4); |
518 | msleep(msecs: 300); |
519 | tda1004x_write_byteI(state, TDA1004X_CONFC4, data: confc4); |
520 | |
521 | /* Checks if eeprom firmware went without troubles */ |
522 | if (tda1004x_check_upload_ok(state) == 0) |
523 | return 0; |
524 | |
525 | /* eeprom firmware didn't work. Load one manually. */ |
526 | |
527 | if (state->config->request_firmware != NULL) { |
528 | /* request the firmware, this will block until someone uploads it */ |
529 | printk(KERN_INFO "tda1004x: waiting for firmware upload...\n" ); |
530 | ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE); |
531 | if (ret) { |
532 | /* remain compatible to old bug: try to load with tda10045 image name */ |
533 | ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); |
534 | if (ret) { |
535 | printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n" ); |
536 | return ret; |
537 | } else { |
538 | printk(KERN_INFO "tda1004x: please rename the firmware file to %s\n" , |
539 | TDA10046_DEFAULT_FIRMWARE); |
540 | } |
541 | } |
542 | } else { |
543 | printk(KERN_ERR "tda1004x: no request function defined, can't upload from file\n" ); |
544 | return -EIO; |
545 | } |
546 | tda1004x_write_mask(state, TDA1004X_CONFC4, mask: 8, data: 8); // going to boot from HOST |
547 | ret = tda1004x_do_upload(state, mem: fw->data, len: fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN); |
548 | release_firmware(fw); |
549 | return tda1004x_check_upload_ok(state); |
550 | } |
551 | |
552 | static int tda1004x_encode_fec(int fec) |
553 | { |
554 | // convert known FEC values |
555 | switch (fec) { |
556 | case FEC_1_2: |
557 | return 0; |
558 | case FEC_2_3: |
559 | return 1; |
560 | case FEC_3_4: |
561 | return 2; |
562 | case FEC_5_6: |
563 | return 3; |
564 | case FEC_7_8: |
565 | return 4; |
566 | } |
567 | |
568 | // unsupported |
569 | return -EINVAL; |
570 | } |
571 | |
572 | static int tda1004x_decode_fec(int tdafec) |
573 | { |
574 | // convert known FEC values |
575 | switch (tdafec) { |
576 | case 0: |
577 | return FEC_1_2; |
578 | case 1: |
579 | return FEC_2_3; |
580 | case 2: |
581 | return FEC_3_4; |
582 | case 3: |
583 | return FEC_5_6; |
584 | case 4: |
585 | return FEC_7_8; |
586 | } |
587 | |
588 | // unsupported |
589 | return -1; |
590 | } |
591 | |
592 | static int tda1004x_write(struct dvb_frontend* fe, const u8 buf[], int len) |
593 | { |
594 | struct tda1004x_state* state = fe->demodulator_priv; |
595 | |
596 | if (len != 2) |
597 | return -EINVAL; |
598 | |
599 | return tda1004x_write_byteI(state, reg: buf[0], data: buf[1]); |
600 | } |
601 | |
602 | static int tda10045_init(struct dvb_frontend* fe) |
603 | { |
604 | struct tda1004x_state* state = fe->demodulator_priv; |
605 | |
606 | dprintk("%s\n" , __func__); |
607 | |
608 | if (tda10045_fwupload(fe)) { |
609 | printk("tda1004x: firmware upload failed\n" ); |
610 | return -EIO; |
611 | } |
612 | |
613 | tda1004x_write_mask(state, TDA1004X_CONFADC1, mask: 0x10, data: 0); // wake up the ADC |
614 | |
615 | // tda setup |
616 | tda1004x_write_mask(state, TDA1004X_CONFC4, mask: 0x20, data: 0); // disable DSP watchdog timer |
617 | tda1004x_write_mask(state, TDA1004X_AUTO, mask: 8, data: 0); // select HP stream |
618 | tda1004x_write_mask(state, TDA1004X_CONFC1, mask: 0x40, data: 0); // set polarity of VAGC signal |
619 | tda1004x_write_mask(state, TDA1004X_CONFC1, mask: 0x80, data: 0x80); // enable pulse killer |
620 | tda1004x_write_mask(state, TDA1004X_AUTO, mask: 0x10, data: 0x10); // enable auto offset |
621 | tda1004x_write_mask(state, TDA1004X_IN_CONF2, mask: 0xC0, data: 0x0); // no frequency offset |
622 | tda1004x_write_byteI(state, TDA1004X_CONF_TS1, data: 0); // setup MPEG2 TS interface |
623 | tda1004x_write_byteI(state, TDA1004X_CONF_TS2, data: 0); // setup MPEG2 TS interface |
624 | tda1004x_write_mask(state, TDA1004X_VBER_MSB, mask: 0xe0, data: 0xa0); // 10^6 VBER measurement bits |
625 | tda1004x_write_mask(state, TDA1004X_CONFC1, mask: 0x10, data: 0); // VAGC polarity |
626 | tda1004x_write_byteI(state, TDA1004X_CONFADC1, data: 0x2e); |
627 | |
628 | tda1004x_write_mask(state, reg: 0x1f, mask: 0x01, data: state->config->invert_oclk); |
629 | |
630 | return 0; |
631 | } |
632 | |
633 | static int tda10046_init(struct dvb_frontend* fe) |
634 | { |
635 | struct tda1004x_state* state = fe->demodulator_priv; |
636 | dprintk("%s\n" , __func__); |
637 | |
638 | if (tda10046_fwupload(fe)) { |
639 | printk("tda1004x: firmware upload failed\n" ); |
640 | return -EIO; |
641 | } |
642 | |
643 | // tda setup |
644 | tda1004x_write_mask(state, TDA1004X_CONFC4, mask: 0x20, data: 0); // disable DSP watchdog timer |
645 | tda1004x_write_byteI(state, TDA1004X_AUTO, data: 0x87); // 100 ppm crystal, select HP stream |
646 | tda1004x_write_byteI(state, TDA1004X_CONFC1, data: 0x88); // enable pulse killer |
647 | |
648 | switch (state->config->agc_config) { |
649 | case TDA10046_AGC_DEFAULT: |
650 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, data: 0x00); // AGC setup |
651 | tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, mask: 0xf0, data: 0x60); // set AGC polarities |
652 | break; |
653 | case TDA10046_AGC_IFO_AUTO_NEG: |
654 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, data: 0x0a); // AGC setup |
655 | tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, mask: 0xf0, data: 0x60); // set AGC polarities |
656 | break; |
657 | case TDA10046_AGC_IFO_AUTO_POS: |
658 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, data: 0x0a); // AGC setup |
659 | tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, mask: 0xf0, data: 0x00); // set AGC polarities |
660 | break; |
661 | case TDA10046_AGC_TDA827X: |
662 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, data: 0x02); // AGC setup |
663 | tda1004x_write_byteI(state, TDA10046H_AGC_THR, data: 0x70); // AGC Threshold |
664 | tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, data: 0x08); // Gain Renormalize |
665 | tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, mask: 0xf0, data: 0x60); // set AGC polarities |
666 | break; |
667 | } |
668 | if (state->config->ts_mode == 0) { |
669 | tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, mask: 0xc0, data: 0x40); |
670 | tda1004x_write_mask(state, reg: 0x3a, mask: 0x80, data: state->config->invert_oclk << 7); |
671 | } else { |
672 | tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, mask: 0xc0, data: 0x80); |
673 | tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, mask: 0x10, |
674 | data: state->config->invert_oclk << 4); |
675 | } |
676 | tda1004x_write_byteI(state, TDA1004X_CONFADC2, data: 0x38); |
677 | tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, mask: 0x3e, data: 0x38); // Turn IF AGC output on |
678 | tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, data: 0); // } |
679 | tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, data: 0xff); // } AGC min/max values |
680 | tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, data: 0); // } |
681 | tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, data: 0xff); // } |
682 | tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, data: 0x12); // IF gain 2, TUN gain 1 |
683 | tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, data: 0x1a); // 10^6 VBER measurement bits |
684 | tda1004x_write_byteI(state, TDA1004X_CONF_TS1, data: 7); // MPEG2 interface config |
685 | tda1004x_write_byteI(state, TDA1004X_CONF_TS2, data: 0xc0); // MPEG2 interface config |
686 | // tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes |
687 | |
688 | return 0; |
689 | } |
690 | |
691 | static int tda1004x_set_fe(struct dvb_frontend *fe) |
692 | { |
693 | struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache; |
694 | struct tda1004x_state* state = fe->demodulator_priv; |
695 | int tmp; |
696 | int inversion; |
697 | |
698 | dprintk("%s\n" , __func__); |
699 | |
700 | if (state->demod_type == TDA1004X_DEMOD_TDA10046) { |
701 | // setup auto offset |
702 | tda1004x_write_mask(state, TDA1004X_AUTO, mask: 0x10, data: 0x10); |
703 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 0x80, data: 0); |
704 | tda1004x_write_mask(state, TDA1004X_IN_CONF2, mask: 0xC0, data: 0); |
705 | |
706 | // disable agc_conf[2] |
707 | tda1004x_write_mask(state, TDA10046H_AGC_CONF, mask: 4, data: 0); |
708 | } |
709 | |
710 | // set frequency |
711 | if (fe->ops.tuner_ops.set_params) { |
712 | fe->ops.tuner_ops.set_params(fe); |
713 | if (fe->ops.i2c_gate_ctrl) |
714 | fe->ops.i2c_gate_ctrl(fe, 0); |
715 | } |
716 | |
717 | // Hardcoded to use auto as much as possible on the TDA10045 as it |
718 | // is very unreliable if AUTO mode is _not_ used. |
719 | if (state->demod_type == TDA1004X_DEMOD_TDA10045) { |
720 | fe_params->code_rate_HP = FEC_AUTO; |
721 | fe_params->guard_interval = GUARD_INTERVAL_AUTO; |
722 | fe_params->transmission_mode = TRANSMISSION_MODE_AUTO; |
723 | } |
724 | |
725 | // Set standard params.. or put them to auto |
726 | if ((fe_params->code_rate_HP == FEC_AUTO) || |
727 | (fe_params->code_rate_LP == FEC_AUTO) || |
728 | (fe_params->modulation == QAM_AUTO) || |
729 | (fe_params->hierarchy == HIERARCHY_AUTO)) { |
730 | tda1004x_write_mask(state, TDA1004X_AUTO, mask: 1, data: 1); // enable auto |
731 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 0x03, data: 0); /* turn off modulation bits */ |
732 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 0x60, data: 0); // turn off hierarchy bits |
733 | tda1004x_write_mask(state, TDA1004X_IN_CONF2, mask: 0x3f, data: 0); // turn off FEC bits |
734 | } else { |
735 | tda1004x_write_mask(state, TDA1004X_AUTO, mask: 1, data: 0); // disable auto |
736 | |
737 | // set HP FEC |
738 | tmp = tda1004x_encode_fec(fec: fe_params->code_rate_HP); |
739 | if (tmp < 0) |
740 | return tmp; |
741 | tda1004x_write_mask(state, TDA1004X_IN_CONF2, mask: 7, data: tmp); |
742 | |
743 | // set LP FEC |
744 | tmp = tda1004x_encode_fec(fec: fe_params->code_rate_LP); |
745 | if (tmp < 0) |
746 | return tmp; |
747 | tda1004x_write_mask(state, TDA1004X_IN_CONF2, mask: 0x38, data: tmp << 3); |
748 | |
749 | /* set modulation */ |
750 | switch (fe_params->modulation) { |
751 | case QPSK: |
752 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 3, data: 0); |
753 | break; |
754 | |
755 | case QAM_16: |
756 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 3, data: 1); |
757 | break; |
758 | |
759 | case QAM_64: |
760 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 3, data: 2); |
761 | break; |
762 | |
763 | default: |
764 | return -EINVAL; |
765 | } |
766 | |
767 | // set hierarchy |
768 | switch (fe_params->hierarchy) { |
769 | case HIERARCHY_NONE: |
770 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 0x60, data: 0 << 5); |
771 | break; |
772 | |
773 | case HIERARCHY_1: |
774 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 0x60, data: 1 << 5); |
775 | break; |
776 | |
777 | case HIERARCHY_2: |
778 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 0x60, data: 2 << 5); |
779 | break; |
780 | |
781 | case HIERARCHY_4: |
782 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 0x60, data: 3 << 5); |
783 | break; |
784 | |
785 | default: |
786 | return -EINVAL; |
787 | } |
788 | } |
789 | |
790 | // set bandwidth |
791 | switch (state->demod_type) { |
792 | case TDA1004X_DEMOD_TDA10045: |
793 | tda10045h_set_bandwidth(state, bandwidth: fe_params->bandwidth_hz); |
794 | break; |
795 | |
796 | case TDA1004X_DEMOD_TDA10046: |
797 | tda10046h_set_bandwidth(state, bandwidth: fe_params->bandwidth_hz); |
798 | break; |
799 | } |
800 | |
801 | // set inversion |
802 | inversion = fe_params->inversion; |
803 | if (state->config->invert) |
804 | inversion = inversion ? INVERSION_OFF : INVERSION_ON; |
805 | switch (inversion) { |
806 | case INVERSION_OFF: |
807 | tda1004x_write_mask(state, TDA1004X_CONFC1, mask: 0x20, data: 0); |
808 | break; |
809 | |
810 | case INVERSION_ON: |
811 | tda1004x_write_mask(state, TDA1004X_CONFC1, mask: 0x20, data: 0x20); |
812 | break; |
813 | |
814 | default: |
815 | return -EINVAL; |
816 | } |
817 | |
818 | // set guard interval |
819 | switch (fe_params->guard_interval) { |
820 | case GUARD_INTERVAL_1_32: |
821 | tda1004x_write_mask(state, TDA1004X_AUTO, mask: 2, data: 0); |
822 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 0x0c, data: 0 << 2); |
823 | break; |
824 | |
825 | case GUARD_INTERVAL_1_16: |
826 | tda1004x_write_mask(state, TDA1004X_AUTO, mask: 2, data: 0); |
827 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 0x0c, data: 1 << 2); |
828 | break; |
829 | |
830 | case GUARD_INTERVAL_1_8: |
831 | tda1004x_write_mask(state, TDA1004X_AUTO, mask: 2, data: 0); |
832 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 0x0c, data: 2 << 2); |
833 | break; |
834 | |
835 | case GUARD_INTERVAL_1_4: |
836 | tda1004x_write_mask(state, TDA1004X_AUTO, mask: 2, data: 0); |
837 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 0x0c, data: 3 << 2); |
838 | break; |
839 | |
840 | case GUARD_INTERVAL_AUTO: |
841 | tda1004x_write_mask(state, TDA1004X_AUTO, mask: 2, data: 2); |
842 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 0x0c, data: 0 << 2); |
843 | break; |
844 | |
845 | default: |
846 | return -EINVAL; |
847 | } |
848 | |
849 | // set transmission mode |
850 | switch (fe_params->transmission_mode) { |
851 | case TRANSMISSION_MODE_2K: |
852 | tda1004x_write_mask(state, TDA1004X_AUTO, mask: 4, data: 0); |
853 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 0x10, data: 0 << 4); |
854 | break; |
855 | |
856 | case TRANSMISSION_MODE_8K: |
857 | tda1004x_write_mask(state, TDA1004X_AUTO, mask: 4, data: 0); |
858 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 0x10, data: 1 << 4); |
859 | break; |
860 | |
861 | case TRANSMISSION_MODE_AUTO: |
862 | tda1004x_write_mask(state, TDA1004X_AUTO, mask: 4, data: 4); |
863 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, mask: 0x10, data: 0); |
864 | break; |
865 | |
866 | default: |
867 | return -EINVAL; |
868 | } |
869 | |
870 | // start the lock |
871 | switch (state->demod_type) { |
872 | case TDA1004X_DEMOD_TDA10045: |
873 | tda1004x_write_mask(state, TDA1004X_CONFC4, mask: 8, data: 8); |
874 | tda1004x_write_mask(state, TDA1004X_CONFC4, mask: 8, data: 0); |
875 | break; |
876 | |
877 | case TDA1004X_DEMOD_TDA10046: |
878 | tda1004x_write_mask(state, TDA1004X_AUTO, mask: 0x40, data: 0x40); |
879 | msleep(msecs: 1); |
880 | tda1004x_write_mask(state, TDA10046H_AGC_CONF, mask: 4, data: 1); |
881 | break; |
882 | } |
883 | |
884 | msleep(msecs: 10); |
885 | |
886 | return 0; |
887 | } |
888 | |
889 | static int tda1004x_get_fe(struct dvb_frontend *fe, |
890 | struct dtv_frontend_properties *fe_params) |
891 | { |
892 | struct tda1004x_state* state = fe->demodulator_priv; |
893 | int status; |
894 | |
895 | dprintk("%s\n" , __func__); |
896 | |
897 | status = tda1004x_read_byte(state, TDA1004X_STATUS_CD); |
898 | if (status == -1) |
899 | return -EIO; |
900 | |
901 | /* Only update the properties cache if device is locked */ |
902 | if (!(status & 8)) |
903 | return 0; |
904 | |
905 | // inversion status |
906 | fe_params->inversion = INVERSION_OFF; |
907 | if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20) |
908 | fe_params->inversion = INVERSION_ON; |
909 | if (state->config->invert) |
910 | fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON; |
911 | |
912 | // bandwidth |
913 | switch (state->demod_type) { |
914 | case TDA1004X_DEMOD_TDA10045: |
915 | switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) { |
916 | case 0x14: |
917 | fe_params->bandwidth_hz = 8000000; |
918 | break; |
919 | case 0xdb: |
920 | fe_params->bandwidth_hz = 7000000; |
921 | break; |
922 | case 0x4f: |
923 | fe_params->bandwidth_hz = 6000000; |
924 | break; |
925 | } |
926 | break; |
927 | case TDA1004X_DEMOD_TDA10046: |
928 | switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) { |
929 | case 0x5c: |
930 | case 0x54: |
931 | fe_params->bandwidth_hz = 8000000; |
932 | break; |
933 | case 0x6a: |
934 | case 0x60: |
935 | fe_params->bandwidth_hz = 7000000; |
936 | break; |
937 | case 0x7b: |
938 | case 0x70: |
939 | fe_params->bandwidth_hz = 6000000; |
940 | break; |
941 | } |
942 | break; |
943 | } |
944 | |
945 | // FEC |
946 | fe_params->code_rate_HP = |
947 | tda1004x_decode_fec(tdafec: tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7); |
948 | fe_params->code_rate_LP = |
949 | tda1004x_decode_fec(tdafec: (tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7); |
950 | |
951 | /* modulation */ |
952 | switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) { |
953 | case 0: |
954 | fe_params->modulation = QPSK; |
955 | break; |
956 | case 1: |
957 | fe_params->modulation = QAM_16; |
958 | break; |
959 | case 2: |
960 | fe_params->modulation = QAM_64; |
961 | break; |
962 | } |
963 | |
964 | // transmission mode |
965 | fe_params->transmission_mode = TRANSMISSION_MODE_2K; |
966 | if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10) |
967 | fe_params->transmission_mode = TRANSMISSION_MODE_8K; |
968 | |
969 | // guard interval |
970 | switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) { |
971 | case 0: |
972 | fe_params->guard_interval = GUARD_INTERVAL_1_32; |
973 | break; |
974 | case 1: |
975 | fe_params->guard_interval = GUARD_INTERVAL_1_16; |
976 | break; |
977 | case 2: |
978 | fe_params->guard_interval = GUARD_INTERVAL_1_8; |
979 | break; |
980 | case 3: |
981 | fe_params->guard_interval = GUARD_INTERVAL_1_4; |
982 | break; |
983 | } |
984 | |
985 | // hierarchy |
986 | switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) { |
987 | case 0: |
988 | fe_params->hierarchy = HIERARCHY_NONE; |
989 | break; |
990 | case 1: |
991 | fe_params->hierarchy = HIERARCHY_1; |
992 | break; |
993 | case 2: |
994 | fe_params->hierarchy = HIERARCHY_2; |
995 | break; |
996 | case 3: |
997 | fe_params->hierarchy = HIERARCHY_4; |
998 | break; |
999 | } |
1000 | |
1001 | return 0; |
1002 | } |
1003 | |
1004 | static int tda1004x_read_status(struct dvb_frontend *fe, |
1005 | enum fe_status *fe_status) |
1006 | { |
1007 | struct tda1004x_state* state = fe->demodulator_priv; |
1008 | int status; |
1009 | int cber; |
1010 | int vber; |
1011 | |
1012 | dprintk("%s\n" , __func__); |
1013 | |
1014 | // read status |
1015 | status = tda1004x_read_byte(state, TDA1004X_STATUS_CD); |
1016 | if (status == -1) |
1017 | return -EIO; |
1018 | |
1019 | // decode |
1020 | *fe_status = 0; |
1021 | if (status & 4) |
1022 | *fe_status |= FE_HAS_SIGNAL; |
1023 | if (status & 2) |
1024 | *fe_status |= FE_HAS_CARRIER; |
1025 | if (status & 8) |
1026 | *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; |
1027 | |
1028 | // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi |
1029 | // is getting anything valid |
1030 | if (!(*fe_status & FE_HAS_VITERBI)) { |
1031 | // read the CBER |
1032 | cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB); |
1033 | if (cber == -1) |
1034 | return -EIO; |
1035 | status = tda1004x_read_byte(state, TDA1004X_CBER_MSB); |
1036 | if (status == -1) |
1037 | return -EIO; |
1038 | cber |= (status << 8); |
1039 | // The address 0x20 should be read to cope with a TDA10046 bug |
1040 | tda1004x_read_byte(state, TDA1004X_CBER_RESET); |
1041 | |
1042 | if (cber != 65535) |
1043 | *fe_status |= FE_HAS_VITERBI; |
1044 | } |
1045 | |
1046 | // if we DO have some valid VITERBI output, but don't already have SYNC |
1047 | // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid. |
1048 | if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) { |
1049 | // read the VBER |
1050 | vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB); |
1051 | if (vber == -1) |
1052 | return -EIO; |
1053 | status = tda1004x_read_byte(state, TDA1004X_VBER_MID); |
1054 | if (status == -1) |
1055 | return -EIO; |
1056 | vber |= (status << 8); |
1057 | status = tda1004x_read_byte(state, TDA1004X_VBER_MSB); |
1058 | if (status == -1) |
1059 | return -EIO; |
1060 | vber |= (status & 0x0f) << 16; |
1061 | // The CVBER_LUT should be read to cope with TDA10046 hardware bug |
1062 | tda1004x_read_byte(state, TDA1004X_CVBER_LUT); |
1063 | |
1064 | // if RS has passed some valid TS packets, then we must be |
1065 | // getting some SYNC bytes |
1066 | if (vber < 16632) |
1067 | *fe_status |= FE_HAS_SYNC; |
1068 | } |
1069 | |
1070 | // success |
1071 | dprintk("%s: fe_status=0x%x\n" , __func__, *fe_status); |
1072 | return 0; |
1073 | } |
1074 | |
1075 | static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal) |
1076 | { |
1077 | struct tda1004x_state* state = fe->demodulator_priv; |
1078 | int tmp; |
1079 | int reg = 0; |
1080 | |
1081 | dprintk("%s\n" , __func__); |
1082 | |
1083 | // determine the register to use |
1084 | switch (state->demod_type) { |
1085 | case TDA1004X_DEMOD_TDA10045: |
1086 | reg = TDA10045H_S_AGC; |
1087 | break; |
1088 | |
1089 | case TDA1004X_DEMOD_TDA10046: |
1090 | reg = TDA10046H_AGC_IF_LEVEL; |
1091 | break; |
1092 | } |
1093 | |
1094 | // read it |
1095 | tmp = tda1004x_read_byte(state, reg); |
1096 | if (tmp < 0) |
1097 | return -EIO; |
1098 | |
1099 | *signal = (tmp << 8) | tmp; |
1100 | dprintk("%s: signal=0x%x\n" , __func__, *signal); |
1101 | return 0; |
1102 | } |
1103 | |
1104 | static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr) |
1105 | { |
1106 | struct tda1004x_state* state = fe->demodulator_priv; |
1107 | int tmp; |
1108 | |
1109 | dprintk("%s\n" , __func__); |
1110 | |
1111 | // read it |
1112 | tmp = tda1004x_read_byte(state, TDA1004X_SNR); |
1113 | if (tmp < 0) |
1114 | return -EIO; |
1115 | tmp = 255 - tmp; |
1116 | |
1117 | *snr = ((tmp << 8) | tmp); |
1118 | dprintk("%s: snr=0x%x\n" , __func__, *snr); |
1119 | return 0; |
1120 | } |
1121 | |
1122 | static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) |
1123 | { |
1124 | struct tda1004x_state* state = fe->demodulator_priv; |
1125 | int tmp; |
1126 | int tmp2; |
1127 | int counter; |
1128 | |
1129 | dprintk("%s\n" , __func__); |
1130 | |
1131 | // read the UCBLOCKS and reset |
1132 | counter = 0; |
1133 | tmp = tda1004x_read_byte(state, TDA1004X_UNCOR); |
1134 | if (tmp < 0) |
1135 | return -EIO; |
1136 | tmp &= 0x7f; |
1137 | while (counter++ < 5) { |
1138 | tda1004x_write_mask(state, TDA1004X_UNCOR, mask: 0x80, data: 0); |
1139 | tda1004x_write_mask(state, TDA1004X_UNCOR, mask: 0x80, data: 0); |
1140 | tda1004x_write_mask(state, TDA1004X_UNCOR, mask: 0x80, data: 0); |
1141 | |
1142 | tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR); |
1143 | if (tmp2 < 0) |
1144 | return -EIO; |
1145 | tmp2 &= 0x7f; |
1146 | if ((tmp2 < tmp) || (tmp2 == 0)) |
1147 | break; |
1148 | } |
1149 | |
1150 | if (tmp != 0x7f) |
1151 | *ucblocks = tmp; |
1152 | else |
1153 | *ucblocks = 0xffffffff; |
1154 | |
1155 | dprintk("%s: ucblocks=0x%x\n" , __func__, *ucblocks); |
1156 | return 0; |
1157 | } |
1158 | |
1159 | static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber) |
1160 | { |
1161 | struct tda1004x_state* state = fe->demodulator_priv; |
1162 | int tmp; |
1163 | |
1164 | dprintk("%s\n" , __func__); |
1165 | |
1166 | // read it in |
1167 | tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB); |
1168 | if (tmp < 0) |
1169 | return -EIO; |
1170 | *ber = tmp << 1; |
1171 | tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB); |
1172 | if (tmp < 0) |
1173 | return -EIO; |
1174 | *ber |= (tmp << 9); |
1175 | // The address 0x20 should be read to cope with a TDA10046 bug |
1176 | tda1004x_read_byte(state, TDA1004X_CBER_RESET); |
1177 | |
1178 | dprintk("%s: ber=0x%x\n" , __func__, *ber); |
1179 | return 0; |
1180 | } |
1181 | |
1182 | static int tda1004x_sleep(struct dvb_frontend* fe) |
1183 | { |
1184 | struct tda1004x_state* state = fe->demodulator_priv; |
1185 | int gpio_conf; |
1186 | |
1187 | switch (state->demod_type) { |
1188 | case TDA1004X_DEMOD_TDA10045: |
1189 | tda1004x_write_mask(state, TDA1004X_CONFADC1, mask: 0x10, data: 0x10); |
1190 | break; |
1191 | |
1192 | case TDA1004X_DEMOD_TDA10046: |
1193 | /* set outputs to tristate */ |
1194 | tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, data: 0xff); |
1195 | /* invert GPIO 1 and 3 if desired*/ |
1196 | gpio_conf = state->config->gpio_config; |
1197 | if (gpio_conf >= TDA10046_GP00_I) |
1198 | tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, mask: 0x0f, |
1199 | data: (gpio_conf & 0x0f) ^ 0x0a); |
1200 | |
1201 | tda1004x_write_mask(state, TDA1004X_CONFADC2, mask: 0xc0, data: 0xc0); |
1202 | tda1004x_write_mask(state, TDA1004X_CONFC4, mask: 1, data: 1); |
1203 | break; |
1204 | } |
1205 | |
1206 | return 0; |
1207 | } |
1208 | |
1209 | static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) |
1210 | { |
1211 | struct tda1004x_state* state = fe->demodulator_priv; |
1212 | |
1213 | if (enable) { |
1214 | return tda1004x_enable_tuner_i2c(state); |
1215 | } else { |
1216 | return tda1004x_disable_tuner_i2c(state); |
1217 | } |
1218 | } |
1219 | |
1220 | static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings) |
1221 | { |
1222 | fesettings->min_delay_ms = 800; |
1223 | /* Drift compensation makes no sense for DVB-T */ |
1224 | fesettings->step_size = 0; |
1225 | fesettings->max_drift = 0; |
1226 | return 0; |
1227 | } |
1228 | |
1229 | static void tda1004x_release(struct dvb_frontend* fe) |
1230 | { |
1231 | struct tda1004x_state *state = fe->demodulator_priv; |
1232 | kfree(objp: state); |
1233 | } |
1234 | |
1235 | static const struct dvb_frontend_ops tda10045_ops = { |
1236 | .delsys = { SYS_DVBT }, |
1237 | .info = { |
1238 | .name = "Philips TDA10045H DVB-T" , |
1239 | .frequency_min_hz = 51 * MHz, |
1240 | .frequency_max_hz = 858 * MHz, |
1241 | .frequency_stepsize_hz = 166667, |
1242 | .caps = |
1243 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | |
1244 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | |
1245 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | |
1246 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
1247 | }, |
1248 | |
1249 | .release = tda1004x_release, |
1250 | |
1251 | .init = tda10045_init, |
1252 | .sleep = tda1004x_sleep, |
1253 | .write = tda1004x_write, |
1254 | .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl, |
1255 | |
1256 | .set_frontend = tda1004x_set_fe, |
1257 | .get_frontend = tda1004x_get_fe, |
1258 | .get_tune_settings = tda1004x_get_tune_settings, |
1259 | |
1260 | .read_status = tda1004x_read_status, |
1261 | .read_ber = tda1004x_read_ber, |
1262 | .read_signal_strength = tda1004x_read_signal_strength, |
1263 | .read_snr = tda1004x_read_snr, |
1264 | .read_ucblocks = tda1004x_read_ucblocks, |
1265 | }; |
1266 | |
1267 | struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config, |
1268 | struct i2c_adapter* i2c) |
1269 | { |
1270 | struct tda1004x_state *state; |
1271 | int id; |
1272 | |
1273 | /* allocate memory for the internal state */ |
1274 | state = kzalloc(size: sizeof(struct tda1004x_state), GFP_KERNEL); |
1275 | if (!state) { |
1276 | printk(KERN_ERR "Can't allocate memory for tda10045 state\n" ); |
1277 | return NULL; |
1278 | } |
1279 | |
1280 | /* setup the state */ |
1281 | state->config = config; |
1282 | state->i2c = i2c; |
1283 | state->demod_type = TDA1004X_DEMOD_TDA10045; |
1284 | |
1285 | /* check if the demod is there */ |
1286 | id = tda1004x_read_byte(state, TDA1004X_CHIPID); |
1287 | if (id < 0) { |
1288 | printk(KERN_ERR "tda10045: chip is not answering. Giving up.\n" ); |
1289 | kfree(objp: state); |
1290 | return NULL; |
1291 | } |
1292 | |
1293 | if (id != 0x25) { |
1294 | printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n" , id); |
1295 | kfree(objp: state); |
1296 | return NULL; |
1297 | } |
1298 | |
1299 | /* create dvb_frontend */ |
1300 | memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops)); |
1301 | state->frontend.demodulator_priv = state; |
1302 | return &state->frontend; |
1303 | } |
1304 | |
1305 | static const struct dvb_frontend_ops tda10046_ops = { |
1306 | .delsys = { SYS_DVBT }, |
1307 | .info = { |
1308 | .name = "Philips TDA10046H DVB-T" , |
1309 | .frequency_min_hz = 51 * MHz, |
1310 | .frequency_max_hz = 858 * MHz, |
1311 | .frequency_stepsize_hz = 166667, |
1312 | .caps = |
1313 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | |
1314 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | |
1315 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | |
1316 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
1317 | }, |
1318 | |
1319 | .release = tda1004x_release, |
1320 | |
1321 | .init = tda10046_init, |
1322 | .sleep = tda1004x_sleep, |
1323 | .write = tda1004x_write, |
1324 | .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl, |
1325 | |
1326 | .set_frontend = tda1004x_set_fe, |
1327 | .get_frontend = tda1004x_get_fe, |
1328 | .get_tune_settings = tda1004x_get_tune_settings, |
1329 | |
1330 | .read_status = tda1004x_read_status, |
1331 | .read_ber = tda1004x_read_ber, |
1332 | .read_signal_strength = tda1004x_read_signal_strength, |
1333 | .read_snr = tda1004x_read_snr, |
1334 | .read_ucblocks = tda1004x_read_ucblocks, |
1335 | }; |
1336 | |
1337 | struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config, |
1338 | struct i2c_adapter* i2c) |
1339 | { |
1340 | struct tda1004x_state *state; |
1341 | int id; |
1342 | |
1343 | /* allocate memory for the internal state */ |
1344 | state = kzalloc(size: sizeof(struct tda1004x_state), GFP_KERNEL); |
1345 | if (!state) { |
1346 | printk(KERN_ERR "Can't allocate memory for tda10046 state\n" ); |
1347 | return NULL; |
1348 | } |
1349 | |
1350 | /* setup the state */ |
1351 | state->config = config; |
1352 | state->i2c = i2c; |
1353 | state->demod_type = TDA1004X_DEMOD_TDA10046; |
1354 | |
1355 | /* check if the demod is there */ |
1356 | id = tda1004x_read_byte(state, TDA1004X_CHIPID); |
1357 | if (id < 0) { |
1358 | printk(KERN_ERR "tda10046: chip is not answering. Giving up.\n" ); |
1359 | kfree(objp: state); |
1360 | return NULL; |
1361 | } |
1362 | if (id != 0x46) { |
1363 | printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n" , id); |
1364 | kfree(objp: state); |
1365 | return NULL; |
1366 | } |
1367 | |
1368 | /* create dvb_frontend */ |
1369 | memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops)); |
1370 | state->frontend.demodulator_priv = state; |
1371 | return &state->frontend; |
1372 | } |
1373 | |
1374 | module_param(debug, int, 0644); |
1375 | MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)." ); |
1376 | |
1377 | MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator" ); |
1378 | MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach" ); |
1379 | MODULE_LICENSE("GPL" ); |
1380 | |
1381 | EXPORT_SYMBOL_GPL(tda10045_attach); |
1382 | EXPORT_SYMBOL_GPL(tda10046_attach); |
1383 | |