1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * mt9t112 Camera Driver |
4 | * |
5 | * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> |
6 | * |
7 | * Copyright (C) 2009 Renesas Solutions Corp. |
8 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> |
9 | * |
10 | * Based on ov772x driver, mt9m111 driver, |
11 | * |
12 | * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com> |
13 | * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr> |
14 | * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> |
15 | * Copyright (C) 2008 Magnus Damm |
16 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> |
17 | * |
18 | * TODO: This driver lacks support for frame rate control due to missing |
19 | * register level documentation and suitable hardware for testing. |
20 | * v4l-utils compliance tools will report errors. |
21 | */ |
22 | |
23 | #include <linux/clk.h> |
24 | #include <linux/delay.h> |
25 | #include <linux/gpio/consumer.h> |
26 | #include <linux/i2c.h> |
27 | #include <linux/init.h> |
28 | #include <linux/module.h> |
29 | #include <linux/slab.h> |
30 | #include <linux/v4l2-mediabus.h> |
31 | #include <linux/videodev2.h> |
32 | |
33 | #include <media/i2c/mt9t112.h> |
34 | #include <media/v4l2-common.h> |
35 | #include <media/v4l2-image-sizes.h> |
36 | #include <media/v4l2-subdev.h> |
37 | |
38 | /* you can check PLL/clock info */ |
39 | /* #define EXT_CLOCK 24000000 */ |
40 | |
41 | /************************************************************************ |
42 | * macro |
43 | ***********************************************************************/ |
44 | /* |
45 | * frame size |
46 | */ |
47 | #define MAX_WIDTH 2048 |
48 | #define MAX_HEIGHT 1536 |
49 | |
50 | /* |
51 | * macro of read/write |
52 | */ |
53 | #define ECHECKER(ret, x) \ |
54 | do { \ |
55 | (ret) = (x); \ |
56 | if ((ret) < 0) \ |
57 | return (ret); \ |
58 | } while (0) |
59 | |
60 | #define mt9t112_reg_write(ret, client, a, b) \ |
61 | ECHECKER(ret, __mt9t112_reg_write(client, a, b)) |
62 | #define mt9t112_mcu_write(ret, client, a, b) \ |
63 | ECHECKER(ret, __mt9t112_mcu_write(client, a, b)) |
64 | |
65 | #define mt9t112_reg_mask_set(ret, client, a, b, c) \ |
66 | ECHECKER(ret, __mt9t112_reg_mask_set(client, a, b, c)) |
67 | #define mt9t112_mcu_mask_set(ret, client, a, b, c) \ |
68 | ECHECKER(ret, __mt9t112_mcu_mask_set(client, a, b, c)) |
69 | |
70 | #define mt9t112_reg_read(ret, client, a) \ |
71 | ECHECKER(ret, __mt9t112_reg_read(client, a)) |
72 | |
73 | /* |
74 | * Logical address |
75 | */ |
76 | #define _VAR(id, offset, base) (base | (id & 0x1f) << 10 | (offset & 0x3ff)) |
77 | #define VAR(id, offset) _VAR(id, offset, 0x0000) |
78 | #define VAR8(id, offset) _VAR(id, offset, 0x8000) |
79 | |
80 | /************************************************************************ |
81 | * struct |
82 | ***********************************************************************/ |
83 | struct mt9t112_format { |
84 | u32 code; |
85 | enum v4l2_colorspace colorspace; |
86 | u16 fmt; |
87 | u16 order; |
88 | }; |
89 | |
90 | struct mt9t112_priv { |
91 | struct v4l2_subdev subdev; |
92 | struct mt9t112_platform_data *info; |
93 | struct i2c_client *client; |
94 | struct v4l2_rect frame; |
95 | struct clk *clk; |
96 | struct gpio_desc *standby_gpio; |
97 | const struct mt9t112_format *format; |
98 | int num_formats; |
99 | bool init_done; |
100 | }; |
101 | |
102 | /************************************************************************ |
103 | * supported format |
104 | ***********************************************************************/ |
105 | |
106 | static const struct mt9t112_format mt9t112_cfmts[] = { |
107 | { |
108 | .code = MEDIA_BUS_FMT_UYVY8_2X8, |
109 | .colorspace = V4L2_COLORSPACE_SRGB, |
110 | .fmt = 1, |
111 | .order = 0, |
112 | }, { |
113 | .code = MEDIA_BUS_FMT_VYUY8_2X8, |
114 | .colorspace = V4L2_COLORSPACE_SRGB, |
115 | .fmt = 1, |
116 | .order = 1, |
117 | }, { |
118 | .code = MEDIA_BUS_FMT_YUYV8_2X8, |
119 | .colorspace = V4L2_COLORSPACE_SRGB, |
120 | .fmt = 1, |
121 | .order = 2, |
122 | }, { |
123 | .code = MEDIA_BUS_FMT_YVYU8_2X8, |
124 | .colorspace = V4L2_COLORSPACE_SRGB, |
125 | .fmt = 1, |
126 | .order = 3, |
127 | }, { |
128 | .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, |
129 | .colorspace = V4L2_COLORSPACE_SRGB, |
130 | .fmt = 8, |
131 | .order = 2, |
132 | }, { |
133 | .code = MEDIA_BUS_FMT_RGB565_2X8_LE, |
134 | .colorspace = V4L2_COLORSPACE_SRGB, |
135 | .fmt = 4, |
136 | .order = 2, |
137 | }, |
138 | }; |
139 | |
140 | /************************************************************************ |
141 | * general function |
142 | ***********************************************************************/ |
143 | static struct mt9t112_priv *to_mt9t112(const struct i2c_client *client) |
144 | { |
145 | return container_of(i2c_get_clientdata(client), |
146 | struct mt9t112_priv, |
147 | subdev); |
148 | } |
149 | |
150 | static int __mt9t112_reg_read(const struct i2c_client *client, u16 command) |
151 | { |
152 | struct i2c_msg msg[2]; |
153 | u8 buf[2]; |
154 | int ret; |
155 | |
156 | command = swab16(command); |
157 | |
158 | msg[0].addr = client->addr; |
159 | msg[0].flags = 0; |
160 | msg[0].len = 2; |
161 | msg[0].buf = (u8 *)&command; |
162 | |
163 | msg[1].addr = client->addr; |
164 | msg[1].flags = I2C_M_RD; |
165 | msg[1].len = 2; |
166 | msg[1].buf = buf; |
167 | |
168 | /* |
169 | * If return value of this function is < 0, it means error, else, |
170 | * below 16bit is valid data. |
171 | */ |
172 | ret = i2c_transfer(adap: client->adapter, msgs: msg, num: 2); |
173 | if (ret < 0) |
174 | return ret; |
175 | |
176 | memcpy(&ret, buf, 2); |
177 | |
178 | return swab16(ret); |
179 | } |
180 | |
181 | static int __mt9t112_reg_write(const struct i2c_client *client, |
182 | u16 command, u16 data) |
183 | { |
184 | struct i2c_msg msg; |
185 | u8 buf[4]; |
186 | int ret; |
187 | |
188 | command = swab16(command); |
189 | data = swab16(data); |
190 | |
191 | memcpy(buf + 0, &command, 2); |
192 | memcpy(buf + 2, &data, 2); |
193 | |
194 | msg.addr = client->addr; |
195 | msg.flags = 0; |
196 | msg.len = 4; |
197 | msg.buf = buf; |
198 | |
199 | /* |
200 | * i2c_transfer return message length, but this function should |
201 | * return 0 if correct case. |
202 | */ |
203 | ret = i2c_transfer(adap: client->adapter, msgs: &msg, num: 1); |
204 | |
205 | return ret >= 0 ? 0 : ret; |
206 | } |
207 | |
208 | static int __mt9t112_reg_mask_set(const struct i2c_client *client, |
209 | u16 command, u16 mask, u16 set) |
210 | { |
211 | int val = __mt9t112_reg_read(client, command); |
212 | |
213 | if (val < 0) |
214 | return val; |
215 | |
216 | val &= ~mask; |
217 | val |= set & mask; |
218 | |
219 | return __mt9t112_reg_write(client, command, data: val); |
220 | } |
221 | |
222 | /* mcu access */ |
223 | static int __mt9t112_mcu_read(const struct i2c_client *client, u16 command) |
224 | { |
225 | int ret; |
226 | |
227 | ret = __mt9t112_reg_write(client, command: 0x098E, data: command); |
228 | if (ret < 0) |
229 | return ret; |
230 | |
231 | return __mt9t112_reg_read(client, command: 0x0990); |
232 | } |
233 | |
234 | static int __mt9t112_mcu_write(const struct i2c_client *client, |
235 | u16 command, u16 data) |
236 | { |
237 | int ret; |
238 | |
239 | ret = __mt9t112_reg_write(client, command: 0x098E, data: command); |
240 | if (ret < 0) |
241 | return ret; |
242 | |
243 | return __mt9t112_reg_write(client, command: 0x0990, data); |
244 | } |
245 | |
246 | static int __mt9t112_mcu_mask_set(const struct i2c_client *client, |
247 | u16 command, u16 mask, u16 set) |
248 | { |
249 | int val = __mt9t112_mcu_read(client, command); |
250 | |
251 | if (val < 0) |
252 | return val; |
253 | |
254 | val &= ~mask; |
255 | val |= set & mask; |
256 | |
257 | return __mt9t112_mcu_write(client, command, data: val); |
258 | } |
259 | |
260 | static int mt9t112_reset(const struct i2c_client *client) |
261 | { |
262 | int ret; |
263 | |
264 | mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0001); |
265 | usleep_range(min: 1000, max: 5000); |
266 | mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0000); |
267 | |
268 | return ret; |
269 | } |
270 | |
271 | #ifndef EXT_CLOCK |
272 | #define CLOCK_INFO(a, b) |
273 | #else |
274 | #define CLOCK_INFO(a, b) mt9t112_clock_info(a, b) |
275 | static int mt9t112_clock_info(const struct i2c_client *client, u32 ext) |
276 | { |
277 | int m, n, p1, p2, p3, p4, p5, p6, p7; |
278 | u32 vco, clk; |
279 | char *enable; |
280 | |
281 | ext /= 1000; /* kbyte order */ |
282 | |
283 | mt9t112_reg_read(n, client, 0x0012); |
284 | p1 = n & 0x000f; |
285 | n = n >> 4; |
286 | p2 = n & 0x000f; |
287 | n = n >> 4; |
288 | p3 = n & 0x000f; |
289 | |
290 | mt9t112_reg_read(n, client, 0x002a); |
291 | p4 = n & 0x000f; |
292 | n = n >> 4; |
293 | p5 = n & 0x000f; |
294 | n = n >> 4; |
295 | p6 = n & 0x000f; |
296 | |
297 | mt9t112_reg_read(n, client, 0x002c); |
298 | p7 = n & 0x000f; |
299 | |
300 | mt9t112_reg_read(n, client, 0x0010); |
301 | m = n & 0x00ff; |
302 | n = (n >> 8) & 0x003f; |
303 | |
304 | enable = ((ext < 6000) || (ext > 54000)) ? "X" : "" ; |
305 | dev_dbg(&client->dev, "EXTCLK : %10u K %s\n" , ext, enable); |
306 | |
307 | vco = 2 * m * ext / (n + 1); |
308 | enable = ((vco < 384000) || (vco > 768000)) ? "X" : "" ; |
309 | dev_dbg(&client->dev, "VCO : %10u K %s\n" , vco, enable); |
310 | |
311 | clk = vco / (p1 + 1) / (p2 + 1); |
312 | enable = (clk > 96000) ? "X" : "" ; |
313 | dev_dbg(&client->dev, "PIXCLK : %10u K %s\n" , clk, enable); |
314 | |
315 | clk = vco / (p3 + 1); |
316 | enable = (clk > 768000) ? "X" : "" ; |
317 | dev_dbg(&client->dev, "MIPICLK : %10u K %s\n" , clk, enable); |
318 | |
319 | clk = vco / (p6 + 1); |
320 | enable = (clk > 96000) ? "X" : "" ; |
321 | dev_dbg(&client->dev, "MCU CLK : %10u K %s\n" , clk, enable); |
322 | |
323 | clk = vco / (p5 + 1); |
324 | enable = (clk > 54000) ? "X" : "" ; |
325 | dev_dbg(&client->dev, "SOC CLK : %10u K %s\n" , clk, enable); |
326 | |
327 | clk = vco / (p4 + 1); |
328 | enable = (clk > 70000) ? "X" : "" ; |
329 | dev_dbg(&client->dev, "Sensor CLK : %10u K %s\n" , clk, enable); |
330 | |
331 | clk = vco / (p7 + 1); |
332 | dev_dbg(&client->dev, "External sensor : %10u K\n" , clk); |
333 | |
334 | clk = ext / (n + 1); |
335 | enable = ((clk < 2000) || (clk > 24000)) ? "X" : "" ; |
336 | dev_dbg(&client->dev, "PFD : %10u K %s\n" , clk, enable); |
337 | |
338 | return 0; |
339 | } |
340 | #endif |
341 | |
342 | static int mt9t112_set_a_frame_size(const struct i2c_client *client, |
343 | u16 width, u16 height) |
344 | { |
345 | int ret; |
346 | u16 wstart = (MAX_WIDTH - width) / 2; |
347 | u16 hstart = (MAX_HEIGHT - height) / 2; |
348 | |
349 | /* (Context A) Image Width/Height. */ |
350 | mt9t112_mcu_write(ret, client, VAR(26, 0), width); |
351 | mt9t112_mcu_write(ret, client, VAR(26, 2), height); |
352 | |
353 | /* (Context A) Output Width/Height. */ |
354 | mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width); |
355 | mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + height); |
356 | |
357 | /* (Context A) Start Row/Column. */ |
358 | mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart); |
359 | mt9t112_mcu_write(ret, client, VAR(18, 4), 4 + wstart); |
360 | |
361 | /* (Context A) End Row/Column. */ |
362 | mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart); |
363 | mt9t112_mcu_write(ret, client, VAR(18, 8), 11 + width + wstart); |
364 | |
365 | mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); |
366 | |
367 | return ret; |
368 | } |
369 | |
370 | static int mt9t112_set_pll_dividers(const struct i2c_client *client, |
371 | u8 m, u8 n, u8 p1, u8 p2, u8 p3, u8 p4, |
372 | u8 p5, u8 p6, u8 p7) |
373 | { |
374 | int ret; |
375 | u16 val; |
376 | |
377 | /* N/M */ |
378 | val = (n << 8) | (m << 0); |
379 | mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val); |
380 | |
381 | /* P1/P2/P3 */ |
382 | val = ((p3 & 0x0F) << 8) | ((p2 & 0x0F) << 4) | ((p1 & 0x0F) << 0); |
383 | mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val); |
384 | |
385 | /* P4/P5/P6 */ |
386 | val = (0x7 << 12) | ((p6 & 0x0F) << 8) | ((p5 & 0x0F) << 4) | |
387 | ((p4 & 0x0F) << 0); |
388 | mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val); |
389 | |
390 | /* P7 */ |
391 | val = (0x1 << 12) | ((p7 & 0x0F) << 0); |
392 | mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val); |
393 | |
394 | return ret; |
395 | } |
396 | |
397 | static int mt9t112_init_pll(const struct i2c_client *client) |
398 | { |
399 | struct mt9t112_priv *priv = to_mt9t112(client); |
400 | int data, i, ret; |
401 | |
402 | mt9t112_reg_mask_set(ret, client, 0x0014, 0x003, 0x0001); |
403 | |
404 | /* PLL control: BYPASS PLL = 8517. */ |
405 | mt9t112_reg_write(ret, client, 0x0014, 0x2145); |
406 | |
407 | /* Replace these registers when new timing parameters are generated. */ |
408 | mt9t112_set_pll_dividers(client, |
409 | m: priv->info->divider.m, n: priv->info->divider.n, |
410 | p1: priv->info->divider.p1, p2: priv->info->divider.p2, |
411 | p3: priv->info->divider.p3, p4: priv->info->divider.p4, |
412 | p5: priv->info->divider.p5, p6: priv->info->divider.p6, |
413 | p7: priv->info->divider.p7); |
414 | |
415 | /* |
416 | * TEST_BYPASS on |
417 | * PLL_ENABLE on |
418 | * SEL_LOCK_DET on |
419 | * TEST_BYPASS off |
420 | */ |
421 | mt9t112_reg_write(ret, client, 0x0014, 0x2525); |
422 | mt9t112_reg_write(ret, client, 0x0014, 0x2527); |
423 | mt9t112_reg_write(ret, client, 0x0014, 0x3427); |
424 | mt9t112_reg_write(ret, client, 0x0014, 0x3027); |
425 | |
426 | mdelay(10); |
427 | |
428 | /* |
429 | * PLL_BYPASS off |
430 | * Reference clock count |
431 | * I2C Master Clock Divider |
432 | */ |
433 | mt9t112_reg_write(ret, client, 0x0014, 0x3046); |
434 | /* JPEG initialization workaround */ |
435 | mt9t112_reg_write(ret, client, 0x0016, 0x0400); |
436 | mt9t112_reg_write(ret, client, 0x0022, 0x0190); |
437 | mt9t112_reg_write(ret, client, 0x3B84, 0x0212); |
438 | |
439 | /* External sensor clock is PLL bypass. */ |
440 | mt9t112_reg_write(ret, client, 0x002E, 0x0500); |
441 | |
442 | mt9t112_reg_mask_set(ret, client, 0x0018, 0x0002, 0x0002); |
443 | mt9t112_reg_mask_set(ret, client, 0x3B82, 0x0004, 0x0004); |
444 | |
445 | /* MCU disabled. */ |
446 | mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0x0004); |
447 | |
448 | /* Out of standby. */ |
449 | mt9t112_reg_mask_set(ret, client, 0x0018, 0x0001, 0); |
450 | |
451 | mdelay(50); |
452 | |
453 | /* |
454 | * Standby Workaround |
455 | * Disable Secondary I2C Pads |
456 | */ |
457 | mt9t112_reg_write(ret, client, 0x0614, 0x0001); |
458 | mdelay(1); |
459 | mt9t112_reg_write(ret, client, 0x0614, 0x0001); |
460 | mdelay(1); |
461 | mt9t112_reg_write(ret, client, 0x0614, 0x0001); |
462 | mdelay(1); |
463 | mt9t112_reg_write(ret, client, 0x0614, 0x0001); |
464 | mdelay(1); |
465 | mt9t112_reg_write(ret, client, 0x0614, 0x0001); |
466 | mdelay(1); |
467 | mt9t112_reg_write(ret, client, 0x0614, 0x0001); |
468 | mdelay(1); |
469 | |
470 | /* Poll to verify out of standby. Must Poll this bit. */ |
471 | for (i = 0; i < 100; i++) { |
472 | mt9t112_reg_read(data, client, 0x0018); |
473 | if (!(data & 0x4000)) |
474 | break; |
475 | |
476 | mdelay(10); |
477 | } |
478 | |
479 | return ret; |
480 | } |
481 | |
482 | static int mt9t112_init_setting(const struct i2c_client *client) |
483 | { |
484 | int ret; |
485 | |
486 | /* Adaptive Output Clock (A) */ |
487 | mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000); |
488 | |
489 | /* Read Mode (A) */ |
490 | mt9t112_mcu_write(ret, client, VAR(18, 12), 0x0024); |
491 | |
492 | /* Fine Correction (A) */ |
493 | mt9t112_mcu_write(ret, client, VAR(18, 15), 0x00CC); |
494 | |
495 | /* Fine IT Min (A) */ |
496 | mt9t112_mcu_write(ret, client, VAR(18, 17), 0x01f1); |
497 | |
498 | /* Fine IT Max Margin (A) */ |
499 | mt9t112_mcu_write(ret, client, VAR(18, 19), 0x00fF); |
500 | |
501 | /* Base Frame Lines (A) */ |
502 | mt9t112_mcu_write(ret, client, VAR(18, 29), 0x032D); |
503 | |
504 | /* Min Line Length (A) */ |
505 | mt9t112_mcu_write(ret, client, VAR(18, 31), 0x073a); |
506 | |
507 | /* Line Length (A) */ |
508 | mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07d0); |
509 | |
510 | /* Adaptive Output Clock (B) */ |
511 | mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000); |
512 | |
513 | /* Row Start (B) */ |
514 | mt9t112_mcu_write(ret, client, VAR(18, 74), 0x004); |
515 | |
516 | /* Column Start (B) */ |
517 | mt9t112_mcu_write(ret, client, VAR(18, 76), 0x004); |
518 | |
519 | /* Row End (B) */ |
520 | mt9t112_mcu_write(ret, client, VAR(18, 78), 0x60B); |
521 | |
522 | /* Column End (B) */ |
523 | mt9t112_mcu_write(ret, client, VAR(18, 80), 0x80B); |
524 | |
525 | /* Fine Correction (B) */ |
526 | mt9t112_mcu_write(ret, client, VAR(18, 87), 0x008C); |
527 | |
528 | /* Fine IT Min (B) */ |
529 | mt9t112_mcu_write(ret, client, VAR(18, 89), 0x01F1); |
530 | |
531 | /* Fine IT Max Margin (B) */ |
532 | mt9t112_mcu_write(ret, client, VAR(18, 91), 0x00FF); |
533 | |
534 | /* Base Frame Lines (B) */ |
535 | mt9t112_mcu_write(ret, client, VAR(18, 101), 0x0668); |
536 | |
537 | /* Min Line Length (B) */ |
538 | mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0AF0); |
539 | |
540 | /* Line Length (B) */ |
541 | mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0); |
542 | |
543 | /* |
544 | * Flicker Detection registers. |
545 | * This section should be replaced whenever new timing file is |
546 | * generated. All the following registers need to be replaced. |
547 | * Following registers are generated from Register Wizard but user can |
548 | * modify them. For detail see auto flicker detection tuning. |
549 | */ |
550 | |
551 | /* FD_FDPERIOD_SELECT */ |
552 | mt9t112_mcu_write(ret, client, VAR8(8, 5), 0x01); |
553 | |
554 | /* PRI_B_CONFIG_FD_ALGO_RUN */ |
555 | mt9t112_mcu_write(ret, client, VAR(27, 17), 0x0003); |
556 | |
557 | /* PRI_A_CONFIG_FD_ALGO_RUN */ |
558 | mt9t112_mcu_write(ret, client, VAR(26, 17), 0x0003); |
559 | |
560 | /* |
561 | * AFD range detection tuning registers. |
562 | */ |
563 | |
564 | /* Search_f1_50 */ |
565 | mt9t112_mcu_write(ret, client, VAR8(18, 165), 0x25); |
566 | |
567 | /* Search_f2_50 */ |
568 | mt9t112_mcu_write(ret, client, VAR8(18, 166), 0x28); |
569 | |
570 | /* Search_f1_60 */ |
571 | mt9t112_mcu_write(ret, client, VAR8(18, 167), 0x2C); |
572 | |
573 | /* Search_f2_60 */ |
574 | mt9t112_mcu_write(ret, client, VAR8(18, 168), 0x2F); |
575 | |
576 | /* Period_50Hz (A) */ |
577 | mt9t112_mcu_write(ret, client, VAR8(18, 68), 0xBA); |
578 | |
579 | /* Secret register by Aptina. */ |
580 | /* Period_50Hz (A MSB) */ |
581 | mt9t112_mcu_write(ret, client, VAR8(18, 303), 0x00); |
582 | |
583 | /* Period_60Hz (A) */ |
584 | mt9t112_mcu_write(ret, client, VAR8(18, 69), 0x9B); |
585 | |
586 | /* Secret register by Aptina. */ |
587 | /* Period_60Hz (A MSB) */ |
588 | mt9t112_mcu_write(ret, client, VAR8(18, 301), 0x00); |
589 | |
590 | /* Period_50Hz (B) */ |
591 | mt9t112_mcu_write(ret, client, VAR8(18, 140), 0x82); |
592 | |
593 | /* Secret register by Aptina. */ |
594 | /* Period_50Hz (B) MSB */ |
595 | mt9t112_mcu_write(ret, client, VAR8(18, 304), 0x00); |
596 | |
597 | /* Period_60Hz (B) */ |
598 | mt9t112_mcu_write(ret, client, VAR8(18, 141), 0x6D); |
599 | |
600 | /* Secret register by Aptina. */ |
601 | /* Period_60Hz (B) MSB */ |
602 | mt9t112_mcu_write(ret, client, VAR8(18, 302), 0x00); |
603 | |
604 | /* FD Mode */ |
605 | mt9t112_mcu_write(ret, client, VAR8(8, 2), 0x10); |
606 | |
607 | /* Stat_min */ |
608 | mt9t112_mcu_write(ret, client, VAR8(8, 9), 0x02); |
609 | |
610 | /* Stat_max */ |
611 | mt9t112_mcu_write(ret, client, VAR8(8, 10), 0x03); |
612 | |
613 | /* Min_amplitude */ |
614 | mt9t112_mcu_write(ret, client, VAR8(8, 12), 0x0A); |
615 | |
616 | /* RX FIFO Watermark (A) */ |
617 | mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0014); |
618 | |
619 | /* RX FIFO Watermark (B) */ |
620 | mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0014); |
621 | |
622 | /* MCLK: 16MHz |
623 | * PCLK: 73MHz |
624 | * CorePixCLK: 36.5 MHz |
625 | */ |
626 | mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 133); |
627 | mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 110); |
628 | mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 130); |
629 | mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 108); |
630 | |
631 | mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 27); |
632 | mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 30); |
633 | mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 32); |
634 | mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 35); |
635 | |
636 | return ret; |
637 | } |
638 | |
639 | static int mt9t112_auto_focus_setting(const struct i2c_client *client) |
640 | { |
641 | int ret; |
642 | |
643 | mt9t112_mcu_write(ret, client, VAR(12, 13), 0x000F); |
644 | mt9t112_mcu_write(ret, client, VAR(12, 23), 0x0F0F); |
645 | mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); |
646 | |
647 | mt9t112_reg_write(ret, client, 0x0614, 0x0000); |
648 | |
649 | mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05); |
650 | mt9t112_mcu_write(ret, client, VAR8(12, 2), 0x02); |
651 | mt9t112_mcu_write(ret, client, VAR(12, 3), 0x0002); |
652 | mt9t112_mcu_write(ret, client, VAR(17, 3), 0x8001); |
653 | mt9t112_mcu_write(ret, client, VAR(17, 11), 0x0025); |
654 | mt9t112_mcu_write(ret, client, VAR(17, 13), 0x0193); |
655 | mt9t112_mcu_write(ret, client, VAR8(17, 33), 0x18); |
656 | mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05); |
657 | |
658 | return ret; |
659 | } |
660 | |
661 | static int mt9t112_auto_focus_trigger(const struct i2c_client *client) |
662 | { |
663 | int ret; |
664 | |
665 | mt9t112_mcu_write(ret, client, VAR8(12, 25), 0x01); |
666 | |
667 | return ret; |
668 | } |
669 | |
670 | static int mt9t112_init_camera(const struct i2c_client *client) |
671 | { |
672 | int ret; |
673 | |
674 | ECHECKER(ret, mt9t112_reset(client)); |
675 | ECHECKER(ret, mt9t112_init_pll(client)); |
676 | ECHECKER(ret, mt9t112_init_setting(client)); |
677 | ECHECKER(ret, mt9t112_auto_focus_setting(client)); |
678 | |
679 | mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0); |
680 | |
681 | /* Analog setting B.*/ |
682 | mt9t112_reg_write(ret, client, 0x3084, 0x2409); |
683 | mt9t112_reg_write(ret, client, 0x3092, 0x0A49); |
684 | mt9t112_reg_write(ret, client, 0x3094, 0x4949); |
685 | mt9t112_reg_write(ret, client, 0x3096, 0x4950); |
686 | |
687 | /* |
688 | * Disable adaptive clock. |
689 | * PRI_A_CONFIG_JPEG_OB_TX_CONTROL_VAR |
690 | * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR |
691 | */ |
692 | mt9t112_mcu_write(ret, client, VAR(26, 160), 0x0A2E); |
693 | mt9t112_mcu_write(ret, client, VAR(27, 160), 0x0A2E); |
694 | |
695 | /* |
696 | * Configure Status in Status_before_length Format and enable header. |
697 | * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR |
698 | */ |
699 | mt9t112_mcu_write(ret, client, VAR(27, 144), 0x0CB4); |
700 | |
701 | /* |
702 | * Enable JPEG in context B. |
703 | * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR |
704 | */ |
705 | mt9t112_mcu_write(ret, client, VAR8(27, 142), 0x01); |
706 | |
707 | /* Disable Dac_TXLO. */ |
708 | mt9t112_reg_write(ret, client, 0x316C, 0x350F); |
709 | |
710 | /* Set max slew rates. */ |
711 | mt9t112_reg_write(ret, client, 0x1E, 0x777); |
712 | |
713 | return ret; |
714 | } |
715 | |
716 | /************************************************************************ |
717 | * v4l2_subdev_core_ops |
718 | ***********************************************************************/ |
719 | |
720 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
721 | static int mt9t112_g_register(struct v4l2_subdev *sd, |
722 | struct v4l2_dbg_register *reg) |
723 | { |
724 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
725 | int ret; |
726 | |
727 | reg->size = 2; |
728 | mt9t112_reg_read(ret, client, reg->reg); |
729 | |
730 | reg->val = (__u64)ret; |
731 | |
732 | return 0; |
733 | } |
734 | |
735 | static int mt9t112_s_register(struct v4l2_subdev *sd, |
736 | const struct v4l2_dbg_register *reg) |
737 | { |
738 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
739 | int ret; |
740 | |
741 | mt9t112_reg_write(ret, client, reg->reg, reg->val); |
742 | |
743 | return ret; |
744 | } |
745 | #endif |
746 | |
747 | static int mt9t112_power_on(struct mt9t112_priv *priv) |
748 | { |
749 | int ret; |
750 | |
751 | ret = clk_prepare_enable(clk: priv->clk); |
752 | if (ret) |
753 | return ret; |
754 | |
755 | if (priv->standby_gpio) { |
756 | gpiod_set_value(desc: priv->standby_gpio, value: 0); |
757 | msleep(msecs: 100); |
758 | } |
759 | |
760 | return 0; |
761 | } |
762 | |
763 | static int mt9t112_power_off(struct mt9t112_priv *priv) |
764 | { |
765 | clk_disable_unprepare(clk: priv->clk); |
766 | if (priv->standby_gpio) { |
767 | gpiod_set_value(desc: priv->standby_gpio, value: 1); |
768 | msleep(msecs: 100); |
769 | } |
770 | |
771 | return 0; |
772 | } |
773 | |
774 | static int mt9t112_s_power(struct v4l2_subdev *sd, int on) |
775 | { |
776 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
777 | struct mt9t112_priv *priv = to_mt9t112(client); |
778 | |
779 | return on ? mt9t112_power_on(priv) : |
780 | mt9t112_power_off(priv); |
781 | } |
782 | |
783 | static const struct v4l2_subdev_core_ops mt9t112_subdev_core_ops = { |
784 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
785 | .g_register = mt9t112_g_register, |
786 | .s_register = mt9t112_s_register, |
787 | #endif |
788 | .s_power = mt9t112_s_power, |
789 | }; |
790 | |
791 | /************************************************************************ |
792 | * v4l2_subdev_video_ops |
793 | **********************************************************************/ |
794 | static int mt9t112_s_stream(struct v4l2_subdev *sd, int enable) |
795 | { |
796 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
797 | struct mt9t112_priv *priv = to_mt9t112(client); |
798 | int ret = 0; |
799 | |
800 | if (!enable) { |
801 | /* FIXME |
802 | * |
803 | * If user selected large output size, and used it long time, |
804 | * mt9t112 camera will be very warm. |
805 | * |
806 | * But current driver can not stop mt9t112 camera. |
807 | * So, set small size here to solve this problem. |
808 | */ |
809 | mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT); |
810 | return ret; |
811 | } |
812 | |
813 | if (!priv->init_done) { |
814 | u16 param = MT9T112_FLAG_PCLK_RISING_EDGE & priv->info->flags ? |
815 | 0x0001 : 0x0000; |
816 | |
817 | ECHECKER(ret, mt9t112_init_camera(client)); |
818 | |
819 | /* Invert PCLK (Data sampled on falling edge of pixclk). */ |
820 | mt9t112_reg_write(ret, client, 0x3C20, param); |
821 | |
822 | mdelay(5); |
823 | |
824 | priv->init_done = true; |
825 | } |
826 | |
827 | mt9t112_mcu_write(ret, client, VAR(26, 7), priv->format->fmt); |
828 | mt9t112_mcu_write(ret, client, VAR(26, 9), priv->format->order); |
829 | mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); |
830 | |
831 | mt9t112_set_a_frame_size(client, width: priv->frame.width, height: priv->frame.height); |
832 | |
833 | ECHECKER(ret, mt9t112_auto_focus_trigger(client)); |
834 | |
835 | dev_dbg(&client->dev, "format : %d\n" , priv->format->code); |
836 | dev_dbg(&client->dev, "size : %d x %d\n" , |
837 | priv->frame.width, |
838 | priv->frame.height); |
839 | |
840 | CLOCK_INFO(client, EXT_CLOCK); |
841 | |
842 | return ret; |
843 | } |
844 | |
845 | static int mt9t112_set_params(struct mt9t112_priv *priv, |
846 | const struct v4l2_rect *rect, |
847 | u32 code) |
848 | { |
849 | int i; |
850 | |
851 | /* |
852 | * get color format |
853 | */ |
854 | for (i = 0; i < priv->num_formats; i++) |
855 | if (mt9t112_cfmts[i].code == code) |
856 | break; |
857 | |
858 | if (i == priv->num_formats) |
859 | return -EINVAL; |
860 | |
861 | priv->frame = *rect; |
862 | |
863 | /* |
864 | * frame size check |
865 | */ |
866 | v4l_bound_align_image(width: &priv->frame.width, wmin: 0, MAX_WIDTH, walign: 0, |
867 | height: &priv->frame.height, hmin: 0, MAX_HEIGHT, halign: 0, salign: 0); |
868 | |
869 | priv->format = mt9t112_cfmts + i; |
870 | |
871 | return 0; |
872 | } |
873 | |
874 | static int mt9t112_get_selection(struct v4l2_subdev *sd, |
875 | struct v4l2_subdev_state *sd_state, |
876 | struct v4l2_subdev_selection *sel) |
877 | { |
878 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
879 | struct mt9t112_priv *priv = to_mt9t112(client); |
880 | |
881 | if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) |
882 | return -EINVAL; |
883 | |
884 | switch (sel->target) { |
885 | case V4L2_SEL_TGT_CROP_BOUNDS: |
886 | sel->r.left = 0; |
887 | sel->r.top = 0; |
888 | sel->r.width = MAX_WIDTH; |
889 | sel->r.height = MAX_HEIGHT; |
890 | return 0; |
891 | case V4L2_SEL_TGT_CROP: |
892 | sel->r = priv->frame; |
893 | return 0; |
894 | default: |
895 | return -EINVAL; |
896 | } |
897 | } |
898 | |
899 | static int mt9t112_set_selection(struct v4l2_subdev *sd, |
900 | struct v4l2_subdev_state *sd_state, |
901 | struct v4l2_subdev_selection *sel) |
902 | { |
903 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
904 | struct mt9t112_priv *priv = to_mt9t112(client); |
905 | const struct v4l2_rect *rect = &sel->r; |
906 | |
907 | if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE || |
908 | sel->target != V4L2_SEL_TGT_CROP) |
909 | return -EINVAL; |
910 | |
911 | return mt9t112_set_params(priv, rect, code: priv->format->code); |
912 | } |
913 | |
914 | static int mt9t112_get_fmt(struct v4l2_subdev *sd, |
915 | struct v4l2_subdev_state *sd_state, |
916 | struct v4l2_subdev_format *format) |
917 | { |
918 | struct v4l2_mbus_framefmt *mf = &format->format; |
919 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
920 | struct mt9t112_priv *priv = to_mt9t112(client); |
921 | |
922 | if (format->pad) |
923 | return -EINVAL; |
924 | |
925 | mf->width = priv->frame.width; |
926 | mf->height = priv->frame.height; |
927 | mf->colorspace = priv->format->colorspace; |
928 | mf->code = priv->format->code; |
929 | mf->field = V4L2_FIELD_NONE; |
930 | |
931 | return 0; |
932 | } |
933 | |
934 | static int mt9t112_s_fmt(struct v4l2_subdev *sd, |
935 | struct v4l2_mbus_framefmt *mf) |
936 | { |
937 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
938 | struct mt9t112_priv *priv = to_mt9t112(client); |
939 | struct v4l2_rect rect = { |
940 | .width = mf->width, |
941 | .height = mf->height, |
942 | .left = priv->frame.left, |
943 | .top = priv->frame.top, |
944 | }; |
945 | int ret; |
946 | |
947 | ret = mt9t112_set_params(priv, rect: &rect, code: mf->code); |
948 | |
949 | if (!ret) |
950 | mf->colorspace = priv->format->colorspace; |
951 | |
952 | return ret; |
953 | } |
954 | |
955 | static int mt9t112_set_fmt(struct v4l2_subdev *sd, |
956 | struct v4l2_subdev_state *sd_state, |
957 | struct v4l2_subdev_format *format) |
958 | { |
959 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
960 | struct v4l2_mbus_framefmt *mf = &format->format; |
961 | struct mt9t112_priv *priv = to_mt9t112(client); |
962 | int i; |
963 | |
964 | if (format->pad) |
965 | return -EINVAL; |
966 | |
967 | for (i = 0; i < priv->num_formats; i++) |
968 | if (mt9t112_cfmts[i].code == mf->code) |
969 | break; |
970 | |
971 | if (i == priv->num_formats) { |
972 | mf->code = MEDIA_BUS_FMT_UYVY8_2X8; |
973 | mf->colorspace = V4L2_COLORSPACE_JPEG; |
974 | } else { |
975 | mf->colorspace = mt9t112_cfmts[i].colorspace; |
976 | } |
977 | |
978 | v4l_bound_align_image(width: &mf->width, wmin: 0, MAX_WIDTH, walign: 0, |
979 | height: &mf->height, hmin: 0, MAX_HEIGHT, halign: 0, salign: 0); |
980 | |
981 | mf->field = V4L2_FIELD_NONE; |
982 | |
983 | if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) |
984 | return mt9t112_s_fmt(sd, mf); |
985 | |
986 | return 0; |
987 | } |
988 | |
989 | static int mt9t112_enum_mbus_code(struct v4l2_subdev *sd, |
990 | struct v4l2_subdev_state *sd_state, |
991 | struct v4l2_subdev_mbus_code_enum *code) |
992 | { |
993 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
994 | struct mt9t112_priv *priv = to_mt9t112(client); |
995 | |
996 | if (code->pad || code->index >= priv->num_formats) |
997 | return -EINVAL; |
998 | |
999 | code->code = mt9t112_cfmts[code->index].code; |
1000 | |
1001 | return 0; |
1002 | } |
1003 | |
1004 | static const struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = { |
1005 | .s_stream = mt9t112_s_stream, |
1006 | }; |
1007 | |
1008 | static const struct v4l2_subdev_pad_ops mt9t112_subdev_pad_ops = { |
1009 | .enum_mbus_code = mt9t112_enum_mbus_code, |
1010 | .get_selection = mt9t112_get_selection, |
1011 | .set_selection = mt9t112_set_selection, |
1012 | .get_fmt = mt9t112_get_fmt, |
1013 | .set_fmt = mt9t112_set_fmt, |
1014 | }; |
1015 | |
1016 | /************************************************************************ |
1017 | * i2c driver |
1018 | ***********************************************************************/ |
1019 | static const struct v4l2_subdev_ops mt9t112_subdev_ops = { |
1020 | .core = &mt9t112_subdev_core_ops, |
1021 | .video = &mt9t112_subdev_video_ops, |
1022 | .pad = &mt9t112_subdev_pad_ops, |
1023 | }; |
1024 | |
1025 | static int mt9t112_camera_probe(struct i2c_client *client) |
1026 | { |
1027 | struct mt9t112_priv *priv = to_mt9t112(client); |
1028 | const char *devname; |
1029 | int chipid; |
1030 | int ret; |
1031 | |
1032 | ret = mt9t112_s_power(sd: &priv->subdev, on: 1); |
1033 | if (ret < 0) |
1034 | return ret; |
1035 | |
1036 | /* Check and show chip ID. */ |
1037 | mt9t112_reg_read(chipid, client, 0x0000); |
1038 | |
1039 | switch (chipid) { |
1040 | case 0x2680: |
1041 | devname = "mt9t111" ; |
1042 | priv->num_formats = 1; |
1043 | break; |
1044 | case 0x2682: |
1045 | devname = "mt9t112" ; |
1046 | priv->num_formats = ARRAY_SIZE(mt9t112_cfmts); |
1047 | break; |
1048 | default: |
1049 | dev_err(&client->dev, "Product ID error %04x\n" , chipid); |
1050 | ret = -ENODEV; |
1051 | goto done; |
1052 | } |
1053 | |
1054 | dev_info(&client->dev, "%s chip ID %04x\n" , devname, chipid); |
1055 | |
1056 | done: |
1057 | mt9t112_s_power(sd: &priv->subdev, on: 0); |
1058 | |
1059 | return ret; |
1060 | } |
1061 | |
1062 | static int mt9t112_probe(struct i2c_client *client) |
1063 | { |
1064 | struct mt9t112_priv *priv; |
1065 | int ret; |
1066 | |
1067 | if (!client->dev.platform_data) { |
1068 | dev_err(&client->dev, "mt9t112: missing platform data!\n" ); |
1069 | return -EINVAL; |
1070 | } |
1071 | |
1072 | priv = devm_kzalloc(dev: &client->dev, size: sizeof(*priv), GFP_KERNEL); |
1073 | if (!priv) |
1074 | return -ENOMEM; |
1075 | |
1076 | priv->info = client->dev.platform_data; |
1077 | priv->init_done = false; |
1078 | |
1079 | v4l2_i2c_subdev_init(sd: &priv->subdev, client, ops: &mt9t112_subdev_ops); |
1080 | |
1081 | priv->clk = devm_clk_get(dev: &client->dev, id: "extclk" ); |
1082 | if (PTR_ERR(ptr: priv->clk) == -ENOENT) { |
1083 | priv->clk = NULL; |
1084 | } else if (IS_ERR(ptr: priv->clk)) { |
1085 | dev_err(&client->dev, "Unable to get clock \"extclk\"\n" ); |
1086 | return PTR_ERR(ptr: priv->clk); |
1087 | } |
1088 | |
1089 | priv->standby_gpio = devm_gpiod_get_optional(dev: &client->dev, con_id: "standby" , |
1090 | flags: GPIOD_OUT_HIGH); |
1091 | if (IS_ERR(ptr: priv->standby_gpio)) { |
1092 | dev_err(&client->dev, "Unable to get gpio \"standby\"\n" ); |
1093 | return PTR_ERR(ptr: priv->standby_gpio); |
1094 | } |
1095 | |
1096 | ret = mt9t112_camera_probe(client); |
1097 | if (ret) |
1098 | return ret; |
1099 | |
1100 | return v4l2_async_register_subdev(sd: &priv->subdev); |
1101 | } |
1102 | |
1103 | static void mt9t112_remove(struct i2c_client *client) |
1104 | { |
1105 | struct mt9t112_priv *priv = to_mt9t112(client); |
1106 | |
1107 | clk_disable_unprepare(clk: priv->clk); |
1108 | v4l2_async_unregister_subdev(sd: &priv->subdev); |
1109 | } |
1110 | |
1111 | static const struct i2c_device_id mt9t112_id[] = { |
1112 | { "mt9t112" , 0 }, |
1113 | { } |
1114 | }; |
1115 | MODULE_DEVICE_TABLE(i2c, mt9t112_id); |
1116 | |
1117 | static struct i2c_driver mt9t112_i2c_driver = { |
1118 | .driver = { |
1119 | .name = "mt9t112" , |
1120 | }, |
1121 | .probe = mt9t112_probe, |
1122 | .remove = mt9t112_remove, |
1123 | .id_table = mt9t112_id, |
1124 | }; |
1125 | |
1126 | module_i2c_driver(mt9t112_i2c_driver); |
1127 | |
1128 | MODULE_DESCRIPTION("V4L2 driver for MT9T111/MT9T112 camera sensor" ); |
1129 | MODULE_AUTHOR("Kuninori Morimoto" ); |
1130 | MODULE_LICENSE("GPL v2" ); |
1131 | |