1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * tc358743 - Toshiba HDMI to CSI-2 bridge |
4 | * |
5 | * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights |
6 | * reserved. |
7 | */ |
8 | |
9 | /* |
10 | * References (c = chapter, p = page): |
11 | * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 |
12 | * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls |
13 | */ |
14 | |
15 | #include <linux/kernel.h> |
16 | #include <linux/module.h> |
17 | #include <linux/slab.h> |
18 | #include <linux/i2c.h> |
19 | #include <linux/clk.h> |
20 | #include <linux/delay.h> |
21 | #include <linux/gpio/consumer.h> |
22 | #include <linux/interrupt.h> |
23 | #include <linux/timer.h> |
24 | #include <linux/of_graph.h> |
25 | #include <linux/videodev2.h> |
26 | #include <linux/workqueue.h> |
27 | #include <linux/v4l2-dv-timings.h> |
28 | #include <linux/hdmi.h> |
29 | #include <media/cec.h> |
30 | #include <media/v4l2-dv-timings.h> |
31 | #include <media/v4l2-device.h> |
32 | #include <media/v4l2-ctrls.h> |
33 | #include <media/v4l2-event.h> |
34 | #include <media/v4l2-fwnode.h> |
35 | #include <media/i2c/tc358743.h> |
36 | |
37 | #include "tc358743_regs.h" |
38 | |
39 | static int debug; |
40 | module_param(debug, int, 0644); |
41 | MODULE_PARM_DESC(debug, "debug level (0-3)" ); |
42 | |
43 | MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver" ); |
44 | MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>" ); |
45 | MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>" ); |
46 | MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>" ); |
47 | MODULE_LICENSE("GPL" ); |
48 | |
49 | #define EDID_NUM_BLOCKS_MAX 8 |
50 | #define EDID_BLOCK_SIZE 128 |
51 | |
52 | #define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2) |
53 | |
54 | #define POLL_INTERVAL_CEC_MS 10 |
55 | #define POLL_INTERVAL_MS 1000 |
56 | |
57 | static const struct v4l2_dv_timings_cap tc358743_timings_cap = { |
58 | .type = V4L2_DV_BT_656_1120, |
59 | /* keep this initialization for compatibility with GCC < 4.4.6 */ |
60 | .reserved = { 0 }, |
61 | /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */ |
62 | V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 13000000, 165000000, |
63 | V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | |
64 | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, |
65 | V4L2_DV_BT_CAP_PROGRESSIVE | |
66 | V4L2_DV_BT_CAP_REDUCED_BLANKING | |
67 | V4L2_DV_BT_CAP_CUSTOM) |
68 | }; |
69 | |
70 | struct tc358743_state { |
71 | struct tc358743_platform_data pdata; |
72 | struct v4l2_mbus_config_mipi_csi2 bus; |
73 | struct v4l2_subdev sd; |
74 | struct media_pad pad; |
75 | struct v4l2_ctrl_handler hdl; |
76 | struct i2c_client *i2c_client; |
77 | /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */ |
78 | struct mutex confctl_mutex; |
79 | |
80 | /* controls */ |
81 | struct v4l2_ctrl *detect_tx_5v_ctrl; |
82 | struct v4l2_ctrl *audio_sampling_rate_ctrl; |
83 | struct v4l2_ctrl *audio_present_ctrl; |
84 | |
85 | struct delayed_work delayed_work_enable_hotplug; |
86 | |
87 | struct timer_list timer; |
88 | struct work_struct work_i2c_poll; |
89 | |
90 | /* edid */ |
91 | u8 edid_blocks_written; |
92 | |
93 | struct v4l2_dv_timings timings; |
94 | u32 mbus_fmt_code; |
95 | u8 csi_lanes_in_use; |
96 | |
97 | struct gpio_desc *reset_gpio; |
98 | |
99 | struct cec_adapter *cec_adap; |
100 | }; |
101 | |
102 | static void tc358743_enable_interrupts(struct v4l2_subdev *sd, |
103 | bool cable_connected); |
104 | static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd); |
105 | |
106 | static inline struct tc358743_state *to_state(struct v4l2_subdev *sd) |
107 | { |
108 | return container_of(sd, struct tc358743_state, sd); |
109 | } |
110 | |
111 | /* --------------- I2C --------------- */ |
112 | |
113 | static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) |
114 | { |
115 | struct tc358743_state *state = to_state(sd); |
116 | struct i2c_client *client = state->i2c_client; |
117 | int err; |
118 | u8 buf[2] = { reg >> 8, reg & 0xff }; |
119 | struct i2c_msg msgs[] = { |
120 | { |
121 | .addr = client->addr, |
122 | .flags = 0, |
123 | .len = 2, |
124 | .buf = buf, |
125 | }, |
126 | { |
127 | .addr = client->addr, |
128 | .flags = I2C_M_RD, |
129 | .len = n, |
130 | .buf = values, |
131 | }, |
132 | }; |
133 | |
134 | err = i2c_transfer(adap: client->adapter, msgs, ARRAY_SIZE(msgs)); |
135 | if (err != ARRAY_SIZE(msgs)) { |
136 | v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed: %d\n" , |
137 | __func__, reg, client->addr, err); |
138 | } |
139 | } |
140 | |
141 | static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) |
142 | { |
143 | struct tc358743_state *state = to_state(sd); |
144 | struct i2c_client *client = state->i2c_client; |
145 | int err, i; |
146 | struct i2c_msg msg; |
147 | u8 data[I2C_MAX_XFER_SIZE]; |
148 | |
149 | if ((2 + n) > I2C_MAX_XFER_SIZE) { |
150 | n = I2C_MAX_XFER_SIZE - 2; |
151 | v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n" , |
152 | reg, 2 + n); |
153 | } |
154 | |
155 | msg.addr = client->addr; |
156 | msg.buf = data; |
157 | msg.len = 2 + n; |
158 | msg.flags = 0; |
159 | |
160 | data[0] = reg >> 8; |
161 | data[1] = reg & 0xff; |
162 | |
163 | for (i = 0; i < n; i++) |
164 | data[2 + i] = values[i]; |
165 | |
166 | err = i2c_transfer(adap: client->adapter, msgs: &msg, num: 1); |
167 | if (err != 1) { |
168 | v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed: %d\n" , |
169 | __func__, reg, client->addr, err); |
170 | return; |
171 | } |
172 | |
173 | if (debug < 3) |
174 | return; |
175 | |
176 | switch (n) { |
177 | case 1: |
178 | v4l2_info(sd, "I2C write 0x%04x = 0x%02x" , |
179 | reg, data[2]); |
180 | break; |
181 | case 2: |
182 | v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x" , |
183 | reg, data[3], data[2]); |
184 | break; |
185 | case 4: |
186 | v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x" , |
187 | reg, data[5], data[4], data[3], data[2]); |
188 | break; |
189 | default: |
190 | v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n" , |
191 | n, reg); |
192 | } |
193 | } |
194 | |
195 | static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n) |
196 | { |
197 | __le32 val = 0; |
198 | |
199 | i2c_rd(sd, reg, values: (u8 __force *)&val, n); |
200 | |
201 | return le32_to_cpu(val); |
202 | } |
203 | |
204 | static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n) |
205 | { |
206 | __le32 raw = cpu_to_le32(val); |
207 | |
208 | i2c_wr(sd, reg, values: (u8 __force *)&raw, n); |
209 | } |
210 | |
211 | static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg) |
212 | { |
213 | return i2c_rdreg(sd, reg, n: 1); |
214 | } |
215 | |
216 | static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val) |
217 | { |
218 | i2c_wrreg(sd, reg, val, n: 1); |
219 | } |
220 | |
221 | static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg, |
222 | u8 mask, u8 val) |
223 | { |
224 | i2c_wrreg(sd, reg, val: (i2c_rdreg(sd, reg, n: 1) & mask) | val, n: 1); |
225 | } |
226 | |
227 | static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg) |
228 | { |
229 | return i2c_rdreg(sd, reg, n: 2); |
230 | } |
231 | |
232 | static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val) |
233 | { |
234 | i2c_wrreg(sd, reg, val, n: 2); |
235 | } |
236 | |
237 | static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val) |
238 | { |
239 | i2c_wrreg(sd, reg, val: (i2c_rdreg(sd, reg, n: 2) & mask) | val, n: 2); |
240 | } |
241 | |
242 | static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg) |
243 | { |
244 | return i2c_rdreg(sd, reg, n: 4); |
245 | } |
246 | |
247 | static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val) |
248 | { |
249 | i2c_wrreg(sd, reg, val, n: 4); |
250 | } |
251 | |
252 | /* --------------- STATUS --------------- */ |
253 | |
254 | static inline bool is_hdmi(struct v4l2_subdev *sd) |
255 | { |
256 | return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI; |
257 | } |
258 | |
259 | static inline bool tx_5v_power_present(struct v4l2_subdev *sd) |
260 | { |
261 | return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V; |
262 | } |
263 | |
264 | static inline bool no_signal(struct v4l2_subdev *sd) |
265 | { |
266 | return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS); |
267 | } |
268 | |
269 | static inline bool no_sync(struct v4l2_subdev *sd) |
270 | { |
271 | return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC); |
272 | } |
273 | |
274 | static inline bool audio_present(struct v4l2_subdev *sd) |
275 | { |
276 | return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE; |
277 | } |
278 | |
279 | static int get_audio_sampling_rate(struct v4l2_subdev *sd) |
280 | { |
281 | static const int code_to_rate[] = { |
282 | 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800, |
283 | 88200, 768000, 96000, 705600, 176400, 0, 192000, 0 |
284 | }; |
285 | |
286 | /* Register FS_SET is not cleared when the cable is disconnected */ |
287 | if (no_signal(sd)) |
288 | return 0; |
289 | |
290 | return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS]; |
291 | } |
292 | |
293 | /* --------------- TIMINGS --------------- */ |
294 | |
295 | static inline unsigned fps(const struct v4l2_bt_timings *t) |
296 | { |
297 | if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t)) |
298 | return 0; |
299 | |
300 | return DIV_ROUND_CLOSEST((unsigned)t->pixelclock, |
301 | V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t)); |
302 | } |
303 | |
304 | static int tc358743_get_detected_timings(struct v4l2_subdev *sd, |
305 | struct v4l2_dv_timings *timings) |
306 | { |
307 | struct v4l2_bt_timings *bt = &timings->bt; |
308 | unsigned width, height, frame_width, frame_height, frame_interval, fps; |
309 | |
310 | memset(timings, 0, sizeof(struct v4l2_dv_timings)); |
311 | |
312 | if (no_signal(sd)) { |
313 | v4l2_dbg(1, debug, sd, "%s: no valid signal\n" , __func__); |
314 | return -ENOLINK; |
315 | } |
316 | if (no_sync(sd)) { |
317 | v4l2_dbg(1, debug, sd, "%s: no sync on signal\n" , __func__); |
318 | return -ENOLCK; |
319 | } |
320 | |
321 | timings->type = V4L2_DV_BT_656_1120; |
322 | bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ? |
323 | V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; |
324 | |
325 | width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) + |
326 | i2c_rd8(sd, DE_WIDTH_H_LO); |
327 | height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) + |
328 | i2c_rd8(sd, DE_WIDTH_V_LO); |
329 | frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) + |
330 | i2c_rd8(sd, H_SIZE_LO); |
331 | frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) + |
332 | i2c_rd8(sd, V_SIZE_LO)) / 2; |
333 | /* frame interval in milliseconds * 10 |
334 | * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */ |
335 | frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) + |
336 | i2c_rd8(sd, FV_CNT_LO); |
337 | fps = (frame_interval > 0) ? |
338 | DIV_ROUND_CLOSEST(10000, frame_interval) : 0; |
339 | |
340 | bt->width = width; |
341 | bt->height = height; |
342 | bt->vsync = frame_height - height; |
343 | bt->hsync = frame_width - width; |
344 | bt->pixelclock = frame_width * frame_height * fps; |
345 | if (bt->interlaced == V4L2_DV_INTERLACED) { |
346 | bt->height *= 2; |
347 | bt->il_vsync = bt->vsync + 1; |
348 | bt->pixelclock /= 2; |
349 | } |
350 | |
351 | return 0; |
352 | } |
353 | |
354 | /* --------------- HOTPLUG / HDCP / EDID --------------- */ |
355 | |
356 | static void tc358743_delayed_work_enable_hotplug(struct work_struct *work) |
357 | { |
358 | struct delayed_work *dwork = to_delayed_work(work); |
359 | struct tc358743_state *state = container_of(dwork, |
360 | struct tc358743_state, delayed_work_enable_hotplug); |
361 | struct v4l2_subdev *sd = &state->sd; |
362 | |
363 | v4l2_dbg(2, debug, sd, "%s:\n" , __func__); |
364 | |
365 | i2c_wr8_and_or(sd, HPD_CTL, mask: ~MASK_HPD_OUT0, MASK_HPD_OUT0); |
366 | } |
367 | |
368 | static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable) |
369 | { |
370 | v4l2_dbg(2, debug, sd, "%s: %s\n" , __func__, enable ? |
371 | "enable" : "disable" ); |
372 | |
373 | if (enable) { |
374 | i2c_wr8_and_or(sd, HDCP_REG3, mask: ~KEY_RD_CMD, KEY_RD_CMD); |
375 | |
376 | i2c_wr8_and_or(sd, HDCP_MODE, mask: ~MASK_MANUAL_AUTHENTICATION, val: 0); |
377 | |
378 | i2c_wr8_and_or(sd, HDCP_REG1, mask: 0xff, |
379 | MASK_AUTH_UNAUTH_SEL_16_FRAMES | |
380 | MASK_AUTH_UNAUTH_AUTO); |
381 | |
382 | i2c_wr8_and_or(sd, HDCP_REG2, mask: ~MASK_AUTO_P3_RESET, |
383 | SET_AUTO_P3_RESET_FRAMES(0x0f)); |
384 | } else { |
385 | i2c_wr8_and_or(sd, HDCP_MODE, mask: ~MASK_MANUAL_AUTHENTICATION, |
386 | MASK_MANUAL_AUTHENTICATION); |
387 | } |
388 | } |
389 | |
390 | static void tc358743_disable_edid(struct v4l2_subdev *sd) |
391 | { |
392 | struct tc358743_state *state = to_state(sd); |
393 | |
394 | v4l2_dbg(2, debug, sd, "%s:\n" , __func__); |
395 | |
396 | cancel_delayed_work_sync(dwork: &state->delayed_work_enable_hotplug); |
397 | |
398 | /* DDC access to EDID is also disabled when hotplug is disabled. See |
399 | * register DDC_CTL */ |
400 | i2c_wr8_and_or(sd, HPD_CTL, mask: ~MASK_HPD_OUT0, val: 0x0); |
401 | } |
402 | |
403 | static void tc358743_enable_edid(struct v4l2_subdev *sd) |
404 | { |
405 | struct tc358743_state *state = to_state(sd); |
406 | |
407 | if (state->edid_blocks_written == 0) { |
408 | v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n" , __func__); |
409 | tc358743_s_ctrl_detect_tx_5v(sd); |
410 | return; |
411 | } |
412 | |
413 | v4l2_dbg(2, debug, sd, "%s:\n" , __func__); |
414 | |
415 | /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when |
416 | * hotplug is enabled. See register DDC_CTL */ |
417 | schedule_delayed_work(dwork: &state->delayed_work_enable_hotplug, HZ / 10); |
418 | |
419 | tc358743_enable_interrupts(sd, cable_connected: true); |
420 | tc358743_s_ctrl_detect_tx_5v(sd); |
421 | } |
422 | |
423 | static void tc358743_erase_bksv(struct v4l2_subdev *sd) |
424 | { |
425 | int i; |
426 | |
427 | for (i = 0; i < 5; i++) |
428 | i2c_wr8(sd, BKSV + i, val: 0); |
429 | } |
430 | |
431 | /* --------------- AVI infoframe --------------- */ |
432 | |
433 | static void print_avi_infoframe(struct v4l2_subdev *sd) |
434 | { |
435 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
436 | struct device *dev = &client->dev; |
437 | union hdmi_infoframe frame; |
438 | u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; |
439 | |
440 | if (!is_hdmi(sd)) { |
441 | v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n" ); |
442 | return; |
443 | } |
444 | |
445 | i2c_rd(sd, PK_AVI_0HEAD, values: buffer, HDMI_INFOFRAME_SIZE(AVI)); |
446 | |
447 | if (hdmi_infoframe_unpack(frame: &frame, buffer, size: sizeof(buffer)) < 0) { |
448 | v4l2_err(sd, "%s: unpack of AVI infoframe failed\n" , __func__); |
449 | return; |
450 | } |
451 | |
452 | hdmi_infoframe_log(KERN_INFO, dev, frame: &frame); |
453 | } |
454 | |
455 | /* --------------- CTRLS --------------- */ |
456 | |
457 | static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd) |
458 | { |
459 | struct tc358743_state *state = to_state(sd); |
460 | |
461 | return v4l2_ctrl_s_ctrl(ctrl: state->detect_tx_5v_ctrl, |
462 | val: tx_5v_power_present(sd)); |
463 | } |
464 | |
465 | static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd) |
466 | { |
467 | struct tc358743_state *state = to_state(sd); |
468 | |
469 | return v4l2_ctrl_s_ctrl(ctrl: state->audio_sampling_rate_ctrl, |
470 | val: get_audio_sampling_rate(sd)); |
471 | } |
472 | |
473 | static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd) |
474 | { |
475 | struct tc358743_state *state = to_state(sd); |
476 | |
477 | return v4l2_ctrl_s_ctrl(ctrl: state->audio_present_ctrl, |
478 | val: audio_present(sd)); |
479 | } |
480 | |
481 | static int tc358743_update_controls(struct v4l2_subdev *sd) |
482 | { |
483 | int ret = 0; |
484 | |
485 | ret |= tc358743_s_ctrl_detect_tx_5v(sd); |
486 | ret |= tc358743_s_ctrl_audio_sampling_rate(sd); |
487 | ret |= tc358743_s_ctrl_audio_present(sd); |
488 | |
489 | return ret; |
490 | } |
491 | |
492 | /* --------------- INIT --------------- */ |
493 | |
494 | static void tc358743_reset_phy(struct v4l2_subdev *sd) |
495 | { |
496 | v4l2_dbg(1, debug, sd, "%s:\n" , __func__); |
497 | |
498 | i2c_wr8_and_or(sd, PHY_RST, mask: ~MASK_RESET_CTRL, val: 0); |
499 | i2c_wr8_and_or(sd, PHY_RST, mask: ~MASK_RESET_CTRL, MASK_RESET_CTRL); |
500 | } |
501 | |
502 | static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask) |
503 | { |
504 | u16 sysctl = i2c_rd16(sd, SYSCTL); |
505 | |
506 | i2c_wr16(sd, SYSCTL, val: sysctl | mask); |
507 | i2c_wr16(sd, SYSCTL, val: sysctl & ~mask); |
508 | } |
509 | |
510 | static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable) |
511 | { |
512 | i2c_wr16_and_or(sd, SYSCTL, mask: ~MASK_SLEEP, |
513 | val: enable ? MASK_SLEEP : 0); |
514 | } |
515 | |
516 | static inline void enable_stream(struct v4l2_subdev *sd, bool enable) |
517 | { |
518 | struct tc358743_state *state = to_state(sd); |
519 | |
520 | v4l2_dbg(3, debug, sd, "%s: %sable\n" , |
521 | __func__, enable ? "en" : "dis" ); |
522 | |
523 | if (enable) { |
524 | /* It is critical for CSI receiver to see lane transition |
525 | * LP11->HS. Set to non-continuous mode to enable clock lane |
526 | * LP11 state. */ |
527 | i2c_wr32(sd, TXOPTIONCNTRL, val: 0); |
528 | /* Set to continuous mode to trigger LP11->HS transition */ |
529 | i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE); |
530 | /* Unmute video */ |
531 | i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE); |
532 | } else { |
533 | /* Mute video so that all data lanes go to LSP11 state. |
534 | * No data is output to CSI Tx block. */ |
535 | i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE); |
536 | } |
537 | |
538 | mutex_lock(&state->confctl_mutex); |
539 | i2c_wr16_and_or(sd, CONFCTL, mask: ~(MASK_VBUFEN | MASK_ABUFEN), |
540 | val: enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0); |
541 | mutex_unlock(lock: &state->confctl_mutex); |
542 | } |
543 | |
544 | static void tc358743_set_pll(struct v4l2_subdev *sd) |
545 | { |
546 | struct tc358743_state *state = to_state(sd); |
547 | struct tc358743_platform_data *pdata = &state->pdata; |
548 | u16 pllctl0 = i2c_rd16(sd, PLLCTL0); |
549 | u16 pllctl1 = i2c_rd16(sd, PLLCTL1); |
550 | u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) | |
551 | SET_PLL_FBD(pdata->pll_fbd); |
552 | u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; |
553 | |
554 | v4l2_dbg(2, debug, sd, "%s:\n" , __func__); |
555 | |
556 | /* Only rewrite when needed (new value or disabled), since rewriting |
557 | * triggers another format change event. */ |
558 | if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) { |
559 | u16 pll_frs; |
560 | |
561 | if (hsck > 500000000) |
562 | pll_frs = 0x0; |
563 | else if (hsck > 250000000) |
564 | pll_frs = 0x1; |
565 | else if (hsck > 125000000) |
566 | pll_frs = 0x2; |
567 | else |
568 | pll_frs = 0x3; |
569 | |
570 | v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n" , __func__); |
571 | tc358743_sleep_mode(sd, enable: true); |
572 | i2c_wr16(sd, PLLCTL0, val: pllctl0_new); |
573 | i2c_wr16_and_or(sd, PLLCTL1, |
574 | mask: ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN), |
575 | val: (SET_PLL_FRS(pll_frs) | MASK_RESETB | |
576 | MASK_PLL_EN)); |
577 | udelay(10); /* REF_02, Sheet "Source HDMI" */ |
578 | i2c_wr16_and_or(sd, PLLCTL1, mask: ~MASK_CKEN, MASK_CKEN); |
579 | tc358743_sleep_mode(sd, enable: false); |
580 | } |
581 | } |
582 | |
583 | static void tc358743_set_ref_clk(struct v4l2_subdev *sd) |
584 | { |
585 | struct tc358743_state *state = to_state(sd); |
586 | struct tc358743_platform_data *pdata = &state->pdata; |
587 | u32 sys_freq; |
588 | u32 lockdet_ref; |
589 | u32 cec_freq; |
590 | u16 fh_min; |
591 | u16 fh_max; |
592 | |
593 | BUG_ON(!(pdata->refclk_hz == 26000000 || |
594 | pdata->refclk_hz == 27000000 || |
595 | pdata->refclk_hz == 42000000)); |
596 | |
597 | sys_freq = pdata->refclk_hz / 10000; |
598 | i2c_wr8(sd, SYS_FREQ0, val: sys_freq & 0x00ff); |
599 | i2c_wr8(sd, SYS_FREQ1, val: (sys_freq & 0xff00) >> 8); |
600 | |
601 | i2c_wr8_and_or(sd, PHY_CTL0, mask: ~MASK_PHY_SYSCLK_IND, |
602 | val: (pdata->refclk_hz == 42000000) ? |
603 | MASK_PHY_SYSCLK_IND : 0x0); |
604 | |
605 | fh_min = pdata->refclk_hz / 100000; |
606 | i2c_wr8(sd, FH_MIN0, val: fh_min & 0x00ff); |
607 | i2c_wr8(sd, FH_MIN1, val: (fh_min & 0xff00) >> 8); |
608 | |
609 | fh_max = (fh_min * 66) / 10; |
610 | i2c_wr8(sd, FH_MAX0, val: fh_max & 0x00ff); |
611 | i2c_wr8(sd, FH_MAX1, val: (fh_max & 0xff00) >> 8); |
612 | |
613 | lockdet_ref = pdata->refclk_hz / 100; |
614 | i2c_wr8(sd, LOCKDET_REF0, val: lockdet_ref & 0x0000ff); |
615 | i2c_wr8(sd, LOCKDET_REF1, val: (lockdet_ref & 0x00ff00) >> 8); |
616 | i2c_wr8(sd, LOCKDET_REF2, val: (lockdet_ref & 0x0f0000) >> 16); |
617 | |
618 | i2c_wr8_and_or(sd, NCO_F0_MOD, mask: ~MASK_NCO_F0_MOD, |
619 | val: (pdata->refclk_hz == 27000000) ? |
620 | MASK_NCO_F0_MOD_27MHZ : 0x0); |
621 | |
622 | /* |
623 | * Trial and error suggests that the default register value |
624 | * of 656 is for a 42 MHz reference clock. Use that to derive |
625 | * a new value based on the actual reference clock. |
626 | */ |
627 | cec_freq = (656 * sys_freq) / 4200; |
628 | i2c_wr16(sd, CECHCLK, val: cec_freq); |
629 | i2c_wr16(sd, CECLCLK, val: cec_freq); |
630 | } |
631 | |
632 | static void tc358743_set_csi_color_space(struct v4l2_subdev *sd) |
633 | { |
634 | struct tc358743_state *state = to_state(sd); |
635 | |
636 | switch (state->mbus_fmt_code) { |
637 | case MEDIA_BUS_FMT_UYVY8_1X16: |
638 | v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n" , __func__); |
639 | i2c_wr8_and_or(sd, VOUT_SET2, |
640 | mask: ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, |
641 | MASK_SEL422 | MASK_VOUT_422FIL_100); |
642 | i2c_wr8_and_or(sd, VI_REP, mask: ~MASK_VOUT_COLOR_SEL & 0xff, |
643 | MASK_VOUT_COLOR_601_YCBCR_LIMITED); |
644 | mutex_lock(&state->confctl_mutex); |
645 | i2c_wr16_and_or(sd, CONFCTL, mask: ~MASK_YCBCRFMT, |
646 | MASK_YCBCRFMT_422_8_BIT); |
647 | mutex_unlock(lock: &state->confctl_mutex); |
648 | break; |
649 | case MEDIA_BUS_FMT_RGB888_1X24: |
650 | v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n" , __func__); |
651 | i2c_wr8_and_or(sd, VOUT_SET2, |
652 | mask: ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, |
653 | val: 0x00); |
654 | i2c_wr8_and_or(sd, VI_REP, mask: ~MASK_VOUT_COLOR_SEL & 0xff, |
655 | MASK_VOUT_COLOR_RGB_FULL); |
656 | mutex_lock(&state->confctl_mutex); |
657 | i2c_wr16_and_or(sd, CONFCTL, mask: ~MASK_YCBCRFMT, val: 0); |
658 | mutex_unlock(lock: &state->confctl_mutex); |
659 | break; |
660 | default: |
661 | v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n" , |
662 | __func__, state->mbus_fmt_code); |
663 | } |
664 | } |
665 | |
666 | static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd) |
667 | { |
668 | struct tc358743_state *state = to_state(sd); |
669 | struct v4l2_bt_timings *bt = &state->timings.bt; |
670 | struct tc358743_platform_data *pdata = &state->pdata; |
671 | u32 bits_pr_pixel = |
672 | (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24; |
673 | u32 bps = bt->width * bt->height * fps(t: bt) * bits_pr_pixel; |
674 | u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; |
675 | |
676 | return DIV_ROUND_UP(bps, bps_pr_lane); |
677 | } |
678 | |
679 | static void tc358743_set_csi(struct v4l2_subdev *sd) |
680 | { |
681 | struct tc358743_state *state = to_state(sd); |
682 | struct tc358743_platform_data *pdata = &state->pdata; |
683 | unsigned lanes = tc358743_num_csi_lanes_needed(sd); |
684 | |
685 | v4l2_dbg(3, debug, sd, "%s:\n" , __func__); |
686 | |
687 | state->csi_lanes_in_use = lanes; |
688 | |
689 | tc358743_reset(sd, MASK_CTXRST); |
690 | |
691 | if (lanes < 1) |
692 | i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE); |
693 | if (lanes < 1) |
694 | i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE); |
695 | if (lanes < 2) |
696 | i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE); |
697 | if (lanes < 3) |
698 | i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE); |
699 | if (lanes < 4) |
700 | i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE); |
701 | |
702 | i2c_wr32(sd, LINEINITCNT, val: pdata->lineinitcnt); |
703 | i2c_wr32(sd, LPTXTIMECNT, val: pdata->lptxtimecnt); |
704 | i2c_wr32(sd, TCLK_HEADERCNT, val: pdata->tclk_headercnt); |
705 | i2c_wr32(sd, TCLK_TRAILCNT, val: pdata->tclk_trailcnt); |
706 | i2c_wr32(sd, THS_HEADERCNT, val: pdata->ths_headercnt); |
707 | i2c_wr32(sd, TWAKEUP, val: pdata->twakeup); |
708 | i2c_wr32(sd, TCLK_POSTCNT, val: pdata->tclk_postcnt); |
709 | i2c_wr32(sd, THS_TRAILCNT, val: pdata->ths_trailcnt); |
710 | i2c_wr32(sd, HSTXVREGCNT, val: pdata->hstxvregcnt); |
711 | |
712 | i2c_wr32(sd, HSTXVREGEN, |
713 | val: ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) | |
714 | ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) | |
715 | ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) | |
716 | ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) | |
717 | ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0)); |
718 | |
719 | i2c_wr32(sd, TXOPTIONCNTRL, val: (state->bus.flags & |
720 | V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK) ? 0 : MASK_CONTCLKMODE); |
721 | i2c_wr32(sd, STARTCNTRL, MASK_START); |
722 | i2c_wr32(sd, CSI_START, MASK_STRT); |
723 | |
724 | i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | |
725 | MASK_ADDRESS_CSI_CONTROL | |
726 | MASK_CSI_MODE | |
727 | MASK_TXHSMD | |
728 | ((lanes == 4) ? MASK_NOL_4 : |
729 | (lanes == 3) ? MASK_NOL_3 : |
730 | (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1)); |
731 | |
732 | i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | |
733 | MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK | |
734 | MASK_WCER | MASK_INER); |
735 | |
736 | i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR | |
737 | MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK); |
738 | |
739 | i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | |
740 | MASK_ADDRESS_CSI_INT_ENA | MASK_INTER); |
741 | } |
742 | |
743 | static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd) |
744 | { |
745 | struct tc358743_state *state = to_state(sd); |
746 | struct tc358743_platform_data *pdata = &state->pdata; |
747 | |
748 | /* Default settings from REF_02, sheet "Source HDMI" |
749 | * and custom settings as platform data */ |
750 | i2c_wr8_and_or(sd, PHY_EN, mask: ~MASK_ENABLE_PHY, val: 0x0); |
751 | i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) | |
752 | SET_FREQ_RANGE_MODE_CYCLES(1)); |
753 | i2c_wr8_and_or(sd, PHY_CTL2, mask: ~MASK_PHY_AUTO_RSTn, |
754 | val: (pdata->hdmi_phy_auto_reset_tmds_detected ? |
755 | MASK_PHY_AUTO_RST2 : 0) | |
756 | (pdata->hdmi_phy_auto_reset_tmds_in_range ? |
757 | MASK_PHY_AUTO_RST3 : 0) | |
758 | (pdata->hdmi_phy_auto_reset_tmds_valid ? |
759 | MASK_PHY_AUTO_RST4 : 0)); |
760 | i2c_wr8(sd, PHY_BIAS, val: 0x40); |
761 | i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a)); |
762 | i2c_wr8(sd, AVM_CTL, val: 45); |
763 | i2c_wr8_and_or(sd, HDMI_DET, mask: ~MASK_HDMI_DET_V, |
764 | val: pdata->hdmi_detection_delay << 4); |
765 | i2c_wr8_and_or(sd, HV_RST, mask: ~(MASK_H_PI_RST | MASK_V_PI_RST), |
766 | val: (pdata->hdmi_phy_auto_reset_hsync_out_of_range ? |
767 | MASK_H_PI_RST : 0) | |
768 | (pdata->hdmi_phy_auto_reset_vsync_out_of_range ? |
769 | MASK_V_PI_RST : 0)); |
770 | i2c_wr8_and_or(sd, PHY_EN, mask: ~MASK_ENABLE_PHY, MASK_ENABLE_PHY); |
771 | } |
772 | |
773 | static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd) |
774 | { |
775 | struct tc358743_state *state = to_state(sd); |
776 | |
777 | /* Default settings from REF_02, sheet "Source HDMI" */ |
778 | i2c_wr8(sd, FORCE_MUTE, val: 0x00); |
779 | i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 | |
780 | MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 | |
781 | MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0); |
782 | i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9); |
783 | i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2); |
784 | i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500)); |
785 | i2c_wr8(sd, FS_MUTE, val: 0x00); |
786 | i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE); |
787 | i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE); |
788 | i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM); |
789 | i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM); |
790 | i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S); |
791 | i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100)); |
792 | |
793 | mutex_lock(&state->confctl_mutex); |
794 | i2c_wr16_and_or(sd, CONFCTL, mask: 0xffff, MASK_AUDCHNUM_2 | |
795 | MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX); |
796 | mutex_unlock(lock: &state->confctl_mutex); |
797 | } |
798 | |
799 | static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd) |
800 | { |
801 | /* Default settings from REF_02, sheet "Source HDMI" */ |
802 | i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE | |
803 | MASK_ACP_INT_MODE | MASK_VS_INT_MODE | |
804 | MASK_SPD_INT_MODE | MASK_MS_INT_MODE | |
805 | MASK_AUD_INT_MODE | MASK_AVI_INT_MODE); |
806 | i2c_wr8(sd, NO_PKT_LIMIT, val: 0x2c); |
807 | i2c_wr8(sd, NO_PKT_CLR, val: 0x53); |
808 | i2c_wr8(sd, ERR_PK_LIMIT, val: 0x01); |
809 | i2c_wr8(sd, NO_PKT_LIMIT2, val: 0x30); |
810 | i2c_wr8(sd, NO_GDB_LIMIT, val: 0x10); |
811 | } |
812 | |
813 | static void tc358743_initial_setup(struct v4l2_subdev *sd) |
814 | { |
815 | struct tc358743_state *state = to_state(sd); |
816 | struct tc358743_platform_data *pdata = &state->pdata; |
817 | |
818 | /* |
819 | * IR is not supported by this driver. |
820 | * CEC is only enabled if needed. |
821 | */ |
822 | i2c_wr16_and_or(sd, SYSCTL, mask: ~(MASK_IRRST | MASK_CECRST), |
823 | val: (MASK_IRRST | MASK_CECRST)); |
824 | |
825 | tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST); |
826 | #ifdef CONFIG_VIDEO_TC358743_CEC |
827 | tc358743_reset(sd, MASK_CECRST); |
828 | #endif |
829 | tc358743_sleep_mode(sd, enable: false); |
830 | |
831 | i2c_wr16(sd, FIFOCTL, val: pdata->fifo_level); |
832 | |
833 | tc358743_set_ref_clk(sd); |
834 | |
835 | i2c_wr8_and_or(sd, DDC_CTL, mask: ~MASK_DDC5V_MODE, |
836 | val: pdata->ddc5v_delay & MASK_DDC5V_MODE); |
837 | i2c_wr8_and_or(sd, EDID_MODE, mask: ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC); |
838 | |
839 | tc358743_set_hdmi_phy(sd); |
840 | tc358743_set_hdmi_hdcp(sd, enable: pdata->enable_hdcp); |
841 | tc358743_set_hdmi_audio(sd); |
842 | tc358743_set_hdmi_info_frame_mode(sd); |
843 | |
844 | /* All CE and IT formats are detected as RGB full range in DVI mode */ |
845 | i2c_wr8_and_or(sd, VI_MODE, mask: ~MASK_RGB_DVI, val: 0); |
846 | |
847 | i2c_wr8_and_or(sd, VOUT_SET2, mask: ~MASK_VOUTCOLORMODE, |
848 | MASK_VOUTCOLORMODE_AUTO); |
849 | i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT); |
850 | } |
851 | |
852 | /* --------------- CEC --------------- */ |
853 | |
854 | #ifdef CONFIG_VIDEO_TC358743_CEC |
855 | static int tc358743_cec_adap_enable(struct cec_adapter *adap, bool enable) |
856 | { |
857 | struct tc358743_state *state = adap->priv; |
858 | struct v4l2_subdev *sd = &state->sd; |
859 | |
860 | i2c_wr32(sd, CECIMSK, val: enable ? MASK_CECTIM | MASK_CECRIM : 0); |
861 | i2c_wr32(sd, CECICLR, MASK_CECTICLR | MASK_CECRICLR); |
862 | i2c_wr32(sd, CECEN, val: enable); |
863 | if (enable) |
864 | i2c_wr32(sd, CECREN, MASK_CECREN); |
865 | return 0; |
866 | } |
867 | |
868 | static int tc358743_cec_adap_monitor_all_enable(struct cec_adapter *adap, |
869 | bool enable) |
870 | { |
871 | struct tc358743_state *state = adap->priv; |
872 | struct v4l2_subdev *sd = &state->sd; |
873 | u32 reg; |
874 | |
875 | reg = i2c_rd32(sd, CECRCTL1); |
876 | if (enable) |
877 | reg |= MASK_CECOTH; |
878 | else |
879 | reg &= ~MASK_CECOTH; |
880 | i2c_wr32(sd, CECRCTL1, val: reg); |
881 | return 0; |
882 | } |
883 | |
884 | static int tc358743_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) |
885 | { |
886 | struct tc358743_state *state = adap->priv; |
887 | struct v4l2_subdev *sd = &state->sd; |
888 | unsigned int la = 0; |
889 | |
890 | if (log_addr != CEC_LOG_ADDR_INVALID) { |
891 | la = i2c_rd32(sd, CECADD); |
892 | la |= 1 << log_addr; |
893 | } |
894 | i2c_wr32(sd, CECADD, val: la); |
895 | return 0; |
896 | } |
897 | |
898 | static int tc358743_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, |
899 | u32 signal_free_time, struct cec_msg *msg) |
900 | { |
901 | struct tc358743_state *state = adap->priv; |
902 | struct v4l2_subdev *sd = &state->sd; |
903 | unsigned int i; |
904 | |
905 | i2c_wr32(sd, CECTCTL, |
906 | val: (cec_msg_is_broadcast(msg) ? MASK_CECBRD : 0) | |
907 | (signal_free_time - 1)); |
908 | for (i = 0; i < msg->len; i++) |
909 | i2c_wr32(sd, CECTBUF1 + i * 4, |
910 | val: msg->msg[i] | ((i == msg->len - 1) ? MASK_CECTEOM : 0)); |
911 | i2c_wr32(sd, CECTEN, MASK_CECTEN); |
912 | return 0; |
913 | } |
914 | |
915 | static const struct cec_adap_ops tc358743_cec_adap_ops = { |
916 | .adap_enable = tc358743_cec_adap_enable, |
917 | .adap_log_addr = tc358743_cec_adap_log_addr, |
918 | .adap_transmit = tc358743_cec_adap_transmit, |
919 | .adap_monitor_all_enable = tc358743_cec_adap_monitor_all_enable, |
920 | }; |
921 | |
922 | static void tc358743_cec_handler(struct v4l2_subdev *sd, u16 intstatus, |
923 | bool *handled) |
924 | { |
925 | struct tc358743_state *state = to_state(sd); |
926 | unsigned int cec_rxint, cec_txint; |
927 | unsigned int clr = 0; |
928 | |
929 | cec_rxint = i2c_rd32(sd, CECRSTAT); |
930 | cec_txint = i2c_rd32(sd, CECTSTAT); |
931 | |
932 | if (intstatus & MASK_CEC_RINT) |
933 | clr |= MASK_CECRICLR; |
934 | if (intstatus & MASK_CEC_TINT) |
935 | clr |= MASK_CECTICLR; |
936 | i2c_wr32(sd, CECICLR, val: clr); |
937 | |
938 | if ((intstatus & MASK_CEC_TINT) && cec_txint) { |
939 | if (cec_txint & MASK_CECTIEND) |
940 | cec_transmit_attempt_done(adap: state->cec_adap, |
941 | CEC_TX_STATUS_OK); |
942 | else if (cec_txint & MASK_CECTIAL) |
943 | cec_transmit_attempt_done(adap: state->cec_adap, |
944 | CEC_TX_STATUS_ARB_LOST); |
945 | else if (cec_txint & MASK_CECTIACK) |
946 | cec_transmit_attempt_done(adap: state->cec_adap, |
947 | CEC_TX_STATUS_NACK); |
948 | else if (cec_txint & MASK_CECTIUR) { |
949 | /* |
950 | * Not sure when this bit is set. Treat |
951 | * it as an error for now. |
952 | */ |
953 | cec_transmit_attempt_done(adap: state->cec_adap, |
954 | CEC_TX_STATUS_ERROR); |
955 | } |
956 | if (handled) |
957 | *handled = true; |
958 | } |
959 | if ((intstatus & MASK_CEC_RINT) && |
960 | (cec_rxint & MASK_CECRIEND)) { |
961 | struct cec_msg msg = {}; |
962 | unsigned int i; |
963 | unsigned int v; |
964 | |
965 | v = i2c_rd32(sd, CECRCTR); |
966 | msg.len = v & 0x1f; |
967 | if (msg.len > CEC_MAX_MSG_SIZE) |
968 | msg.len = CEC_MAX_MSG_SIZE; |
969 | for (i = 0; i < msg.len; i++) { |
970 | v = i2c_rd32(sd, CECRBUF1 + i * 4); |
971 | msg.msg[i] = v & 0xff; |
972 | } |
973 | cec_received_msg(adap: state->cec_adap, msg: &msg); |
974 | if (handled) |
975 | *handled = true; |
976 | } |
977 | i2c_wr16(sd, INTSTATUS, |
978 | val: intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)); |
979 | } |
980 | |
981 | #endif |
982 | |
983 | /* --------------- IRQ --------------- */ |
984 | |
985 | static void tc358743_format_change(struct v4l2_subdev *sd) |
986 | { |
987 | struct tc358743_state *state = to_state(sd); |
988 | struct v4l2_dv_timings timings; |
989 | const struct v4l2_event tc358743_ev_fmt = { |
990 | .type = V4L2_EVENT_SOURCE_CHANGE, |
991 | .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, |
992 | }; |
993 | |
994 | if (tc358743_get_detected_timings(sd, timings: &timings)) { |
995 | enable_stream(sd, enable: false); |
996 | |
997 | v4l2_dbg(1, debug, sd, "%s: No signal\n" , |
998 | __func__); |
999 | } else { |
1000 | if (!v4l2_match_dv_timings(measured: &state->timings, standard: &timings, pclock_delta: 0, match_reduced_fps: false)) |
1001 | enable_stream(sd, enable: false); |
1002 | |
1003 | if (debug) |
1004 | v4l2_print_dv_timings(dev_prefix: sd->name, |
1005 | prefix: "tc358743_format_change: New format: " , |
1006 | t: &timings, detailed: false); |
1007 | } |
1008 | |
1009 | if (sd->devnode) |
1010 | v4l2_subdev_notify_event(sd, ev: &tc358743_ev_fmt); |
1011 | } |
1012 | |
1013 | static void tc358743_init_interrupts(struct v4l2_subdev *sd) |
1014 | { |
1015 | u16 i; |
1016 | |
1017 | /* clear interrupt status registers */ |
1018 | for (i = SYS_INT; i <= KEY_INT; i++) |
1019 | i2c_wr8(sd, reg: i, val: 0xff); |
1020 | |
1021 | i2c_wr16(sd, INTSTATUS, val: 0xffff); |
1022 | } |
1023 | |
1024 | static void tc358743_enable_interrupts(struct v4l2_subdev *sd, |
1025 | bool cable_connected) |
1026 | { |
1027 | v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n" , __func__, |
1028 | cable_connected); |
1029 | |
1030 | if (cable_connected) { |
1031 | i2c_wr8(sd, SYS_INTM, val: ~(MASK_M_DDC | MASK_M_DVI_DET | |
1032 | MASK_M_HDMI_DET) & 0xff); |
1033 | i2c_wr8(sd, CLK_INTM, val: ~MASK_M_IN_DE_CHG); |
1034 | i2c_wr8(sd, CBIT_INTM, val: ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK | |
1035 | MASK_M_AF_UNLOCK) & 0xff); |
1036 | i2c_wr8(sd, AUDIO_INTM, val: ~MASK_M_BUFINIT_END); |
1037 | i2c_wr8(sd, MISC_INTM, val: ~MASK_M_SYNC_CHG); |
1038 | } else { |
1039 | i2c_wr8(sd, SYS_INTM, val: ~MASK_M_DDC & 0xff); |
1040 | i2c_wr8(sd, CLK_INTM, val: 0xff); |
1041 | i2c_wr8(sd, CBIT_INTM, val: 0xff); |
1042 | i2c_wr8(sd, AUDIO_INTM, val: 0xff); |
1043 | i2c_wr8(sd, MISC_INTM, val: 0xff); |
1044 | } |
1045 | } |
1046 | |
1047 | static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd, |
1048 | bool *handled) |
1049 | { |
1050 | u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM); |
1051 | u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask; |
1052 | |
1053 | i2c_wr8(sd, AUDIO_INT, val: audio_int); |
1054 | |
1055 | v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n" , __func__, audio_int); |
1056 | |
1057 | tc358743_s_ctrl_audio_sampling_rate(sd); |
1058 | tc358743_s_ctrl_audio_present(sd); |
1059 | } |
1060 | |
1061 | static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled) |
1062 | { |
1063 | v4l2_err(sd, "%s: CSI_ERR = 0x%x\n" , __func__, i2c_rd32(sd, CSI_ERR)); |
1064 | |
1065 | i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER); |
1066 | } |
1067 | |
1068 | static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd, |
1069 | bool *handled) |
1070 | { |
1071 | u8 misc_int_mask = i2c_rd8(sd, MISC_INTM); |
1072 | u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask; |
1073 | |
1074 | i2c_wr8(sd, MISC_INT, val: misc_int); |
1075 | |
1076 | v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n" , __func__, misc_int); |
1077 | |
1078 | if (misc_int & MASK_I_SYNC_CHG) { |
1079 | /* Reset the HDMI PHY to try to trigger proper lock on the |
1080 | * incoming video format. Erase BKSV to prevent that old keys |
1081 | * are used when a new source is connected. */ |
1082 | if (no_sync(sd) || no_signal(sd)) { |
1083 | tc358743_reset_phy(sd); |
1084 | tc358743_erase_bksv(sd); |
1085 | } |
1086 | |
1087 | tc358743_format_change(sd); |
1088 | |
1089 | misc_int &= ~MASK_I_SYNC_CHG; |
1090 | if (handled) |
1091 | *handled = true; |
1092 | } |
1093 | |
1094 | if (misc_int) { |
1095 | v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n" , |
1096 | __func__, misc_int); |
1097 | } |
1098 | } |
1099 | |
1100 | static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd, |
1101 | bool *handled) |
1102 | { |
1103 | u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM); |
1104 | u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask; |
1105 | |
1106 | i2c_wr8(sd, CBIT_INT, val: cbit_int); |
1107 | |
1108 | v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n" , __func__, cbit_int); |
1109 | |
1110 | if (cbit_int & MASK_I_CBIT_FS) { |
1111 | |
1112 | v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n" , |
1113 | __func__); |
1114 | tc358743_s_ctrl_audio_sampling_rate(sd); |
1115 | |
1116 | cbit_int &= ~MASK_I_CBIT_FS; |
1117 | if (handled) |
1118 | *handled = true; |
1119 | } |
1120 | |
1121 | if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) { |
1122 | |
1123 | v4l2_dbg(1, debug, sd, "%s: Audio present changed\n" , |
1124 | __func__); |
1125 | tc358743_s_ctrl_audio_present(sd); |
1126 | |
1127 | cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK); |
1128 | if (handled) |
1129 | *handled = true; |
1130 | } |
1131 | |
1132 | if (cbit_int) { |
1133 | v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n" , |
1134 | __func__, cbit_int); |
1135 | } |
1136 | } |
1137 | |
1138 | static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled) |
1139 | { |
1140 | u8 clk_int_mask = i2c_rd8(sd, CLK_INTM); |
1141 | u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask; |
1142 | |
1143 | /* Bit 7 and bit 6 are set even when they are masked */ |
1144 | i2c_wr8(sd, CLK_INT, val: clk_int | 0x80 | MASK_I_OUT_H_CHG); |
1145 | |
1146 | v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n" , __func__, clk_int); |
1147 | |
1148 | if (clk_int & (MASK_I_IN_DE_CHG)) { |
1149 | |
1150 | v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n" , |
1151 | __func__); |
1152 | |
1153 | /* If the source switch to a new resolution with the same pixel |
1154 | * frequency as the existing (e.g. 1080p25 -> 720p50), the |
1155 | * I_SYNC_CHG interrupt is not always triggered, while the |
1156 | * I_IN_DE_CHG interrupt seems to work fine. Format change |
1157 | * notifications are only sent when the signal is stable to |
1158 | * reduce the number of notifications. */ |
1159 | if (!no_signal(sd) && !no_sync(sd)) |
1160 | tc358743_format_change(sd); |
1161 | |
1162 | clk_int &= ~(MASK_I_IN_DE_CHG); |
1163 | if (handled) |
1164 | *handled = true; |
1165 | } |
1166 | |
1167 | if (clk_int) { |
1168 | v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n" , |
1169 | __func__, clk_int); |
1170 | } |
1171 | } |
1172 | |
1173 | static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled) |
1174 | { |
1175 | struct tc358743_state *state = to_state(sd); |
1176 | u8 sys_int_mask = i2c_rd8(sd, SYS_INTM); |
1177 | u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask; |
1178 | |
1179 | i2c_wr8(sd, SYS_INT, val: sys_int); |
1180 | |
1181 | v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n" , __func__, sys_int); |
1182 | |
1183 | if (sys_int & MASK_I_DDC) { |
1184 | bool tx_5v = tx_5v_power_present(sd); |
1185 | |
1186 | v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n" , |
1187 | __func__, tx_5v ? "yes" : "no" ); |
1188 | |
1189 | if (tx_5v) { |
1190 | tc358743_enable_edid(sd); |
1191 | } else { |
1192 | tc358743_enable_interrupts(sd, cable_connected: false); |
1193 | tc358743_disable_edid(sd); |
1194 | memset(&state->timings, 0, sizeof(state->timings)); |
1195 | tc358743_erase_bksv(sd); |
1196 | tc358743_update_controls(sd); |
1197 | } |
1198 | |
1199 | sys_int &= ~MASK_I_DDC; |
1200 | if (handled) |
1201 | *handled = true; |
1202 | } |
1203 | |
1204 | if (sys_int & MASK_I_DVI) { |
1205 | v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n" , |
1206 | __func__); |
1207 | |
1208 | /* Reset the HDMI PHY to try to trigger proper lock on the |
1209 | * incoming video format. Erase BKSV to prevent that old keys |
1210 | * are used when a new source is connected. */ |
1211 | if (no_sync(sd) || no_signal(sd)) { |
1212 | tc358743_reset_phy(sd); |
1213 | tc358743_erase_bksv(sd); |
1214 | } |
1215 | |
1216 | sys_int &= ~MASK_I_DVI; |
1217 | if (handled) |
1218 | *handled = true; |
1219 | } |
1220 | |
1221 | if (sys_int & MASK_I_HDMI) { |
1222 | v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n" , |
1223 | __func__); |
1224 | |
1225 | /* Register is reset in DVI mode (REF_01, c. 6.6.41) */ |
1226 | i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON); |
1227 | |
1228 | sys_int &= ~MASK_I_HDMI; |
1229 | if (handled) |
1230 | *handled = true; |
1231 | } |
1232 | |
1233 | if (sys_int) { |
1234 | v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n" , |
1235 | __func__, sys_int); |
1236 | } |
1237 | } |
1238 | |
1239 | /* --------------- CORE OPS --------------- */ |
1240 | |
1241 | static int tc358743_log_status(struct v4l2_subdev *sd) |
1242 | { |
1243 | struct tc358743_state *state = to_state(sd); |
1244 | struct v4l2_dv_timings timings; |
1245 | uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS); |
1246 | uint16_t sysctl = i2c_rd16(sd, SYSCTL); |
1247 | u8 vi_status3 = i2c_rd8(sd, VI_STATUS3); |
1248 | const int deep_color_mode[4] = { 8, 10, 12, 16 }; |
1249 | static const char * const input_color_space[] = { |
1250 | "RGB" , "YCbCr 601" , "opRGB" , "YCbCr 709" , "NA (4)" , |
1251 | "xvYCC 601" , "NA(6)" , "xvYCC 709" , "NA(8)" , "sYCC601" , |
1252 | "NA(10)" , "NA(11)" , "NA(12)" , "opYCC 601" }; |
1253 | |
1254 | v4l2_info(sd, "-----Chip status-----\n" ); |
1255 | v4l2_info(sd, "Chip ID: 0x%02x\n" , |
1256 | (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8); |
1257 | v4l2_info(sd, "Chip revision: 0x%02x\n" , |
1258 | i2c_rd16(sd, CHIPID) & MASK_REVID); |
1259 | v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n" , |
1260 | !!(sysctl & MASK_IRRST), |
1261 | !!(sysctl & MASK_CECRST), |
1262 | !!(sysctl & MASK_CTXRST), |
1263 | !!(sysctl & MASK_HDMIRST)); |
1264 | v4l2_info(sd, "Sleep mode: %s\n" , sysctl & MASK_SLEEP ? "on" : "off" ); |
1265 | v4l2_info(sd, "Cable detected (+5V power): %s\n" , |
1266 | hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no" ); |
1267 | v4l2_info(sd, "DDC lines enabled: %s\n" , |
1268 | (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ? |
1269 | "yes" : "no" ); |
1270 | v4l2_info(sd, "Hotplug enabled: %s\n" , |
1271 | (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ? |
1272 | "yes" : "no" ); |
1273 | v4l2_info(sd, "CEC enabled: %s\n" , |
1274 | (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no" ); |
1275 | v4l2_info(sd, "-----Signal status-----\n" ); |
1276 | v4l2_info(sd, "TMDS signal detected: %s\n" , |
1277 | hdmi_sys_status & MASK_S_TMDS ? "yes" : "no" ); |
1278 | v4l2_info(sd, "Stable sync signal: %s\n" , |
1279 | hdmi_sys_status & MASK_S_SYNC ? "yes" : "no" ); |
1280 | v4l2_info(sd, "PHY PLL locked: %s\n" , |
1281 | hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no" ); |
1282 | v4l2_info(sd, "PHY DE detected: %s\n" , |
1283 | hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no" ); |
1284 | |
1285 | if (tc358743_get_detected_timings(sd, timings: &timings)) { |
1286 | v4l2_info(sd, "No video detected\n" ); |
1287 | } else { |
1288 | v4l2_print_dv_timings(dev_prefix: sd->name, prefix: "Detected format: " , t: &timings, |
1289 | detailed: true); |
1290 | } |
1291 | v4l2_print_dv_timings(dev_prefix: sd->name, prefix: "Configured format: " , t: &state->timings, |
1292 | detailed: true); |
1293 | |
1294 | v4l2_info(sd, "-----CSI-TX status-----\n" ); |
1295 | v4l2_info(sd, "Lanes needed: %d\n" , |
1296 | tc358743_num_csi_lanes_needed(sd)); |
1297 | v4l2_info(sd, "Lanes in use: %d\n" , |
1298 | state->csi_lanes_in_use); |
1299 | v4l2_info(sd, "Waiting for particular sync signal: %s\n" , |
1300 | (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ? |
1301 | "yes" : "no" ); |
1302 | v4l2_info(sd, "Transmit mode: %s\n" , |
1303 | (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ? |
1304 | "yes" : "no" ); |
1305 | v4l2_info(sd, "Receive mode: %s\n" , |
1306 | (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ? |
1307 | "yes" : "no" ); |
1308 | v4l2_info(sd, "Stopped: %s\n" , |
1309 | (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ? |
1310 | "yes" : "no" ); |
1311 | v4l2_info(sd, "Color space: %s\n" , |
1312 | state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ? |
1313 | "YCbCr 422 16-bit" : |
1314 | state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ? |
1315 | "RGB 888 24-bit" : "Unsupported" ); |
1316 | |
1317 | v4l2_info(sd, "-----%s status-----\n" , is_hdmi(sd) ? "HDMI" : "DVI-D" ); |
1318 | v4l2_info(sd, "HDCP encrypted content: %s\n" , |
1319 | hdmi_sys_status & MASK_S_HDCP ? "yes" : "no" ); |
1320 | v4l2_info(sd, "Input color space: %s %s range\n" , |
1321 | input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1], |
1322 | (vi_status3 & MASK_LIMITED) ? "limited" : "full" ); |
1323 | if (!is_hdmi(sd)) |
1324 | return 0; |
1325 | v4l2_info(sd, "AV Mute: %s\n" , hdmi_sys_status & MASK_S_AVMUTE ? "on" : |
1326 | "off" ); |
1327 | v4l2_info(sd, "Deep color mode: %d-bits per channel\n" , |
1328 | deep_color_mode[(i2c_rd8(sd, VI_STATUS1) & |
1329 | MASK_S_DEEPCOLOR) >> 2]); |
1330 | print_avi_infoframe(sd); |
1331 | |
1332 | return 0; |
1333 | } |
1334 | |
1335 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1336 | static void tc358743_print_register_map(struct v4l2_subdev *sd) |
1337 | { |
1338 | v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n" ); |
1339 | v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n" ); |
1340 | v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n" ); |
1341 | v4l2_info(sd, "0x0400-0x05FF: Reserved\n" ); |
1342 | v4l2_info(sd, "0x0600-0x06FF: CEC Register\n" ); |
1343 | v4l2_info(sd, "0x0700-0x84FF: Reserved\n" ); |
1344 | v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n" ); |
1345 | v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n" ); |
1346 | v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n" ); |
1347 | v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n" ); |
1348 | v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n" ); |
1349 | v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n" ); |
1350 | v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n" ); |
1351 | v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n" ); |
1352 | v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n" ); |
1353 | v4l2_info(sd, "0x9300- : Reserved\n" ); |
1354 | } |
1355 | |
1356 | static int tc358743_get_reg_size(u16 address) |
1357 | { |
1358 | /* REF_01 p. 66-72 */ |
1359 | if (address <= 0x00ff) |
1360 | return 2; |
1361 | else if ((address >= 0x0100) && (address <= 0x06FF)) |
1362 | return 4; |
1363 | else if ((address >= 0x0700) && (address <= 0x84ff)) |
1364 | return 2; |
1365 | else |
1366 | return 1; |
1367 | } |
1368 | |
1369 | static int tc358743_g_register(struct v4l2_subdev *sd, |
1370 | struct v4l2_dbg_register *reg) |
1371 | { |
1372 | if (reg->reg > 0xffff) { |
1373 | tc358743_print_register_map(sd); |
1374 | return -EINVAL; |
1375 | } |
1376 | |
1377 | reg->size = tc358743_get_reg_size(address: reg->reg); |
1378 | |
1379 | reg->val = i2c_rdreg(sd, reg: reg->reg, n: reg->size); |
1380 | |
1381 | return 0; |
1382 | } |
1383 | |
1384 | static int tc358743_s_register(struct v4l2_subdev *sd, |
1385 | const struct v4l2_dbg_register *reg) |
1386 | { |
1387 | if (reg->reg > 0xffff) { |
1388 | tc358743_print_register_map(sd); |
1389 | return -EINVAL; |
1390 | } |
1391 | |
1392 | /* It should not be possible for the user to enable HDCP with a simple |
1393 | * v4l2-dbg command. |
1394 | * |
1395 | * DO NOT REMOVE THIS unless all other issues with HDCP have been |
1396 | * resolved. |
1397 | */ |
1398 | if (reg->reg == HDCP_MODE || |
1399 | reg->reg == HDCP_REG1 || |
1400 | reg->reg == HDCP_REG2 || |
1401 | reg->reg == HDCP_REG3 || |
1402 | reg->reg == BCAPS) |
1403 | return 0; |
1404 | |
1405 | i2c_wrreg(sd, reg: (u16)reg->reg, val: reg->val, |
1406 | n: tc358743_get_reg_size(address: reg->reg)); |
1407 | |
1408 | return 0; |
1409 | } |
1410 | #endif |
1411 | |
1412 | static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled) |
1413 | { |
1414 | u16 intstatus = i2c_rd16(sd, INTSTATUS); |
1415 | |
1416 | v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n" , __func__, intstatus); |
1417 | |
1418 | if (intstatus & MASK_HDMI_INT) { |
1419 | u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0); |
1420 | u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1); |
1421 | |
1422 | if (hdmi_int0 & MASK_I_MISC) |
1423 | tc358743_hdmi_misc_int_handler(sd, handled); |
1424 | if (hdmi_int1 & MASK_I_CBIT) |
1425 | tc358743_hdmi_cbit_int_handler(sd, handled); |
1426 | if (hdmi_int1 & MASK_I_CLK) |
1427 | tc358743_hdmi_clk_int_handler(sd, handled); |
1428 | if (hdmi_int1 & MASK_I_SYS) |
1429 | tc358743_hdmi_sys_int_handler(sd, handled); |
1430 | if (hdmi_int1 & MASK_I_AUD) |
1431 | tc358743_hdmi_audio_int_handler(sd, handled); |
1432 | |
1433 | i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT); |
1434 | intstatus &= ~MASK_HDMI_INT; |
1435 | } |
1436 | |
1437 | #ifdef CONFIG_VIDEO_TC358743_CEC |
1438 | if (intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)) { |
1439 | tc358743_cec_handler(sd, intstatus, handled); |
1440 | i2c_wr16(sd, INTSTATUS, |
1441 | val: intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)); |
1442 | intstatus &= ~(MASK_CEC_RINT | MASK_CEC_TINT); |
1443 | } |
1444 | #endif |
1445 | |
1446 | if (intstatus & MASK_CSI_INT) { |
1447 | u32 csi_int = i2c_rd32(sd, CSI_INT); |
1448 | |
1449 | if (csi_int & MASK_INTER) |
1450 | tc358743_csi_err_int_handler(sd, handled); |
1451 | |
1452 | i2c_wr16(sd, INTSTATUS, MASK_CSI_INT); |
1453 | } |
1454 | |
1455 | intstatus = i2c_rd16(sd, INTSTATUS); |
1456 | if (intstatus) { |
1457 | v4l2_dbg(1, debug, sd, |
1458 | "%s: Unhandled IntStatus interrupts: 0x%02x\n" , |
1459 | __func__, intstatus); |
1460 | } |
1461 | |
1462 | return 0; |
1463 | } |
1464 | |
1465 | static irqreturn_t tc358743_irq_handler(int irq, void *dev_id) |
1466 | { |
1467 | struct tc358743_state *state = dev_id; |
1468 | bool handled = false; |
1469 | |
1470 | tc358743_isr(sd: &state->sd, status: 0, handled: &handled); |
1471 | |
1472 | return handled ? IRQ_HANDLED : IRQ_NONE; |
1473 | } |
1474 | |
1475 | static void tc358743_irq_poll_timer(struct timer_list *t) |
1476 | { |
1477 | struct tc358743_state *state = from_timer(state, t, timer); |
1478 | unsigned int msecs; |
1479 | |
1480 | schedule_work(work: &state->work_i2c_poll); |
1481 | /* |
1482 | * If CEC is present, then we need to poll more frequently, |
1483 | * otherwise we will miss CEC messages. |
1484 | */ |
1485 | msecs = state->cec_adap ? POLL_INTERVAL_CEC_MS : POLL_INTERVAL_MS; |
1486 | mod_timer(timer: &state->timer, expires: jiffies + msecs_to_jiffies(m: msecs)); |
1487 | } |
1488 | |
1489 | static void tc358743_work_i2c_poll(struct work_struct *work) |
1490 | { |
1491 | struct tc358743_state *state = container_of(work, |
1492 | struct tc358743_state, work_i2c_poll); |
1493 | bool handled; |
1494 | |
1495 | tc358743_isr(sd: &state->sd, status: 0, handled: &handled); |
1496 | } |
1497 | |
1498 | static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, |
1499 | struct v4l2_event_subscription *sub) |
1500 | { |
1501 | switch (sub->type) { |
1502 | case V4L2_EVENT_SOURCE_CHANGE: |
1503 | return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); |
1504 | case V4L2_EVENT_CTRL: |
1505 | return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); |
1506 | default: |
1507 | return -EINVAL; |
1508 | } |
1509 | } |
1510 | |
1511 | /* --------------- VIDEO OPS --------------- */ |
1512 | |
1513 | static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status) |
1514 | { |
1515 | *status = 0; |
1516 | *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; |
1517 | *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0; |
1518 | |
1519 | v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n" , __func__, *status); |
1520 | |
1521 | return 0; |
1522 | } |
1523 | |
1524 | static int tc358743_s_dv_timings(struct v4l2_subdev *sd, |
1525 | struct v4l2_dv_timings *timings) |
1526 | { |
1527 | struct tc358743_state *state = to_state(sd); |
1528 | |
1529 | if (!timings) |
1530 | return -EINVAL; |
1531 | |
1532 | if (debug) |
1533 | v4l2_print_dv_timings(dev_prefix: sd->name, prefix: "tc358743_s_dv_timings: " , |
1534 | t: timings, detailed: false); |
1535 | |
1536 | if (v4l2_match_dv_timings(measured: &state->timings, standard: timings, pclock_delta: 0, match_reduced_fps: false)) { |
1537 | v4l2_dbg(1, debug, sd, "%s: no change\n" , __func__); |
1538 | return 0; |
1539 | } |
1540 | |
1541 | if (!v4l2_valid_dv_timings(t: timings, |
1542 | cap: &tc358743_timings_cap, NULL, NULL)) { |
1543 | v4l2_dbg(1, debug, sd, "%s: timings out of range\n" , __func__); |
1544 | return -ERANGE; |
1545 | } |
1546 | |
1547 | state->timings = *timings; |
1548 | |
1549 | enable_stream(sd, enable: false); |
1550 | tc358743_set_pll(sd); |
1551 | tc358743_set_csi(sd); |
1552 | |
1553 | return 0; |
1554 | } |
1555 | |
1556 | static int tc358743_g_dv_timings(struct v4l2_subdev *sd, |
1557 | struct v4l2_dv_timings *timings) |
1558 | { |
1559 | struct tc358743_state *state = to_state(sd); |
1560 | |
1561 | *timings = state->timings; |
1562 | |
1563 | return 0; |
1564 | } |
1565 | |
1566 | static int tc358743_enum_dv_timings(struct v4l2_subdev *sd, |
1567 | struct v4l2_enum_dv_timings *timings) |
1568 | { |
1569 | if (timings->pad != 0) |
1570 | return -EINVAL; |
1571 | |
1572 | return v4l2_enum_dv_timings_cap(t: timings, |
1573 | cap: &tc358743_timings_cap, NULL, NULL); |
1574 | } |
1575 | |
1576 | static int tc358743_query_dv_timings(struct v4l2_subdev *sd, |
1577 | struct v4l2_dv_timings *timings) |
1578 | { |
1579 | int ret; |
1580 | |
1581 | ret = tc358743_get_detected_timings(sd, timings); |
1582 | if (ret) |
1583 | return ret; |
1584 | |
1585 | if (debug) |
1586 | v4l2_print_dv_timings(dev_prefix: sd->name, prefix: "tc358743_query_dv_timings: " , |
1587 | t: timings, detailed: false); |
1588 | |
1589 | if (!v4l2_valid_dv_timings(t: timings, |
1590 | cap: &tc358743_timings_cap, NULL, NULL)) { |
1591 | v4l2_dbg(1, debug, sd, "%s: timings out of range\n" , __func__); |
1592 | return -ERANGE; |
1593 | } |
1594 | |
1595 | return 0; |
1596 | } |
1597 | |
1598 | static int tc358743_dv_timings_cap(struct v4l2_subdev *sd, |
1599 | struct v4l2_dv_timings_cap *cap) |
1600 | { |
1601 | if (cap->pad != 0) |
1602 | return -EINVAL; |
1603 | |
1604 | *cap = tc358743_timings_cap; |
1605 | |
1606 | return 0; |
1607 | } |
1608 | |
1609 | static int tc358743_get_mbus_config(struct v4l2_subdev *sd, |
1610 | unsigned int pad, |
1611 | struct v4l2_mbus_config *cfg) |
1612 | { |
1613 | struct tc358743_state *state = to_state(sd); |
1614 | |
1615 | cfg->type = V4L2_MBUS_CSI2_DPHY; |
1616 | |
1617 | /* Support for non-continuous CSI-2 clock is missing in the driver */ |
1618 | cfg->bus.mipi_csi2.flags = 0; |
1619 | cfg->bus.mipi_csi2.num_data_lanes = state->csi_lanes_in_use; |
1620 | |
1621 | return 0; |
1622 | } |
1623 | |
1624 | static int tc358743_s_stream(struct v4l2_subdev *sd, int enable) |
1625 | { |
1626 | enable_stream(sd, enable); |
1627 | if (!enable) { |
1628 | /* Put all lanes in LP-11 state (STOPSTATE) */ |
1629 | tc358743_set_csi(sd); |
1630 | } |
1631 | |
1632 | return 0; |
1633 | } |
1634 | |
1635 | /* --------------- PAD OPS --------------- */ |
1636 | |
1637 | static int tc358743_enum_mbus_code(struct v4l2_subdev *sd, |
1638 | struct v4l2_subdev_state *sd_state, |
1639 | struct v4l2_subdev_mbus_code_enum *code) |
1640 | { |
1641 | switch (code->index) { |
1642 | case 0: |
1643 | code->code = MEDIA_BUS_FMT_RGB888_1X24; |
1644 | break; |
1645 | case 1: |
1646 | code->code = MEDIA_BUS_FMT_UYVY8_1X16; |
1647 | break; |
1648 | default: |
1649 | return -EINVAL; |
1650 | } |
1651 | return 0; |
1652 | } |
1653 | |
1654 | static int tc358743_get_fmt(struct v4l2_subdev *sd, |
1655 | struct v4l2_subdev_state *sd_state, |
1656 | struct v4l2_subdev_format *format) |
1657 | { |
1658 | struct tc358743_state *state = to_state(sd); |
1659 | u8 vi_rep = i2c_rd8(sd, VI_REP); |
1660 | |
1661 | if (format->pad != 0) |
1662 | return -EINVAL; |
1663 | |
1664 | format->format.code = state->mbus_fmt_code; |
1665 | format->format.width = state->timings.bt.width; |
1666 | format->format.height = state->timings.bt.height; |
1667 | format->format.field = V4L2_FIELD_NONE; |
1668 | |
1669 | switch (vi_rep & MASK_VOUT_COLOR_SEL) { |
1670 | case MASK_VOUT_COLOR_RGB_FULL: |
1671 | case MASK_VOUT_COLOR_RGB_LIMITED: |
1672 | format->format.colorspace = V4L2_COLORSPACE_SRGB; |
1673 | break; |
1674 | case MASK_VOUT_COLOR_601_YCBCR_LIMITED: |
1675 | case MASK_VOUT_COLOR_601_YCBCR_FULL: |
1676 | format->format.colorspace = V4L2_COLORSPACE_SMPTE170M; |
1677 | break; |
1678 | case MASK_VOUT_COLOR_709_YCBCR_FULL: |
1679 | case MASK_VOUT_COLOR_709_YCBCR_LIMITED: |
1680 | format->format.colorspace = V4L2_COLORSPACE_REC709; |
1681 | break; |
1682 | default: |
1683 | format->format.colorspace = 0; |
1684 | break; |
1685 | } |
1686 | |
1687 | return 0; |
1688 | } |
1689 | |
1690 | static int tc358743_set_fmt(struct v4l2_subdev *sd, |
1691 | struct v4l2_subdev_state *sd_state, |
1692 | struct v4l2_subdev_format *format) |
1693 | { |
1694 | struct tc358743_state *state = to_state(sd); |
1695 | |
1696 | u32 code = format->format.code; /* is overwritten by get_fmt */ |
1697 | int ret = tc358743_get_fmt(sd, sd_state, format); |
1698 | |
1699 | format->format.code = code; |
1700 | |
1701 | if (ret) |
1702 | return ret; |
1703 | |
1704 | switch (code) { |
1705 | case MEDIA_BUS_FMT_RGB888_1X24: |
1706 | case MEDIA_BUS_FMT_UYVY8_1X16: |
1707 | break; |
1708 | default: |
1709 | return -EINVAL; |
1710 | } |
1711 | |
1712 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) |
1713 | return 0; |
1714 | |
1715 | state->mbus_fmt_code = format->format.code; |
1716 | |
1717 | enable_stream(sd, enable: false); |
1718 | tc358743_set_pll(sd); |
1719 | tc358743_set_csi(sd); |
1720 | tc358743_set_csi_color_space(sd); |
1721 | |
1722 | return 0; |
1723 | } |
1724 | |
1725 | static int tc358743_g_edid(struct v4l2_subdev *sd, |
1726 | struct v4l2_subdev_edid *edid) |
1727 | { |
1728 | struct tc358743_state *state = to_state(sd); |
1729 | |
1730 | memset(edid->reserved, 0, sizeof(edid->reserved)); |
1731 | |
1732 | if (edid->pad != 0) |
1733 | return -EINVAL; |
1734 | |
1735 | if (edid->start_block == 0 && edid->blocks == 0) { |
1736 | edid->blocks = state->edid_blocks_written; |
1737 | return 0; |
1738 | } |
1739 | |
1740 | if (state->edid_blocks_written == 0) |
1741 | return -ENODATA; |
1742 | |
1743 | if (edid->start_block >= state->edid_blocks_written || |
1744 | edid->blocks == 0) |
1745 | return -EINVAL; |
1746 | |
1747 | if (edid->start_block + edid->blocks > state->edid_blocks_written) |
1748 | edid->blocks = state->edid_blocks_written - edid->start_block; |
1749 | |
1750 | i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), values: edid->edid, |
1751 | n: edid->blocks * EDID_BLOCK_SIZE); |
1752 | |
1753 | return 0; |
1754 | } |
1755 | |
1756 | static int tc358743_s_edid(struct v4l2_subdev *sd, |
1757 | struct v4l2_subdev_edid *edid) |
1758 | { |
1759 | struct tc358743_state *state = to_state(sd); |
1760 | u16 edid_len = edid->blocks * EDID_BLOCK_SIZE; |
1761 | u16 pa; |
1762 | int err; |
1763 | int i; |
1764 | |
1765 | v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n" , |
1766 | __func__, edid->pad, edid->start_block, edid->blocks); |
1767 | |
1768 | memset(edid->reserved, 0, sizeof(edid->reserved)); |
1769 | |
1770 | if (edid->pad != 0) |
1771 | return -EINVAL; |
1772 | |
1773 | if (edid->start_block != 0) |
1774 | return -EINVAL; |
1775 | |
1776 | if (edid->blocks > EDID_NUM_BLOCKS_MAX) { |
1777 | edid->blocks = EDID_NUM_BLOCKS_MAX; |
1778 | return -E2BIG; |
1779 | } |
1780 | pa = cec_get_edid_phys_addr(edid: edid->edid, size: edid->blocks * 128, NULL); |
1781 | err = v4l2_phys_addr_validate(phys_addr: pa, parent: &pa, NULL); |
1782 | if (err) |
1783 | return err; |
1784 | |
1785 | cec_phys_addr_invalidate(adap: state->cec_adap); |
1786 | |
1787 | tc358743_disable_edid(sd); |
1788 | |
1789 | i2c_wr8(sd, EDID_LEN1, val: edid_len & 0xff); |
1790 | i2c_wr8(sd, EDID_LEN2, val: edid_len >> 8); |
1791 | |
1792 | if (edid->blocks == 0) { |
1793 | state->edid_blocks_written = 0; |
1794 | return 0; |
1795 | } |
1796 | |
1797 | for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE) |
1798 | i2c_wr(sd, EDID_RAM + i, values: edid->edid + i, EDID_BLOCK_SIZE); |
1799 | |
1800 | state->edid_blocks_written = edid->blocks; |
1801 | |
1802 | cec_s_phys_addr(adap: state->cec_adap, phys_addr: pa, block: false); |
1803 | |
1804 | if (tx_5v_power_present(sd)) |
1805 | tc358743_enable_edid(sd); |
1806 | |
1807 | return 0; |
1808 | } |
1809 | |
1810 | /* -------------------------------------------------------------------------- */ |
1811 | |
1812 | static const struct v4l2_subdev_core_ops tc358743_core_ops = { |
1813 | .log_status = tc358743_log_status, |
1814 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1815 | .g_register = tc358743_g_register, |
1816 | .s_register = tc358743_s_register, |
1817 | #endif |
1818 | .interrupt_service_routine = tc358743_isr, |
1819 | .subscribe_event = tc358743_subscribe_event, |
1820 | .unsubscribe_event = v4l2_event_subdev_unsubscribe, |
1821 | }; |
1822 | |
1823 | static const struct v4l2_subdev_video_ops tc358743_video_ops = { |
1824 | .g_input_status = tc358743_g_input_status, |
1825 | .s_dv_timings = tc358743_s_dv_timings, |
1826 | .g_dv_timings = tc358743_g_dv_timings, |
1827 | .query_dv_timings = tc358743_query_dv_timings, |
1828 | .s_stream = tc358743_s_stream, |
1829 | }; |
1830 | |
1831 | static const struct v4l2_subdev_pad_ops tc358743_pad_ops = { |
1832 | .enum_mbus_code = tc358743_enum_mbus_code, |
1833 | .set_fmt = tc358743_set_fmt, |
1834 | .get_fmt = tc358743_get_fmt, |
1835 | .get_edid = tc358743_g_edid, |
1836 | .set_edid = tc358743_s_edid, |
1837 | .enum_dv_timings = tc358743_enum_dv_timings, |
1838 | .dv_timings_cap = tc358743_dv_timings_cap, |
1839 | .get_mbus_config = tc358743_get_mbus_config, |
1840 | }; |
1841 | |
1842 | static const struct v4l2_subdev_ops tc358743_ops = { |
1843 | .core = &tc358743_core_ops, |
1844 | .video = &tc358743_video_ops, |
1845 | .pad = &tc358743_pad_ops, |
1846 | }; |
1847 | |
1848 | /* --------------- CUSTOM CTRLS --------------- */ |
1849 | |
1850 | static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = { |
1851 | .id = TC358743_CID_AUDIO_SAMPLING_RATE, |
1852 | .name = "Audio sampling rate" , |
1853 | .type = V4L2_CTRL_TYPE_INTEGER, |
1854 | .min = 0, |
1855 | .max = 768000, |
1856 | .step = 1, |
1857 | .def = 0, |
1858 | .flags = V4L2_CTRL_FLAG_READ_ONLY, |
1859 | }; |
1860 | |
1861 | static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = { |
1862 | .id = TC358743_CID_AUDIO_PRESENT, |
1863 | .name = "Audio present" , |
1864 | .type = V4L2_CTRL_TYPE_BOOLEAN, |
1865 | .min = 0, |
1866 | .max = 1, |
1867 | .step = 1, |
1868 | .def = 0, |
1869 | .flags = V4L2_CTRL_FLAG_READ_ONLY, |
1870 | }; |
1871 | |
1872 | /* --------------- PROBE / REMOVE --------------- */ |
1873 | |
1874 | #ifdef CONFIG_OF |
1875 | static void tc358743_gpio_reset(struct tc358743_state *state) |
1876 | { |
1877 | usleep_range(min: 5000, max: 10000); |
1878 | gpiod_set_value(desc: state->reset_gpio, value: 1); |
1879 | usleep_range(min: 1000, max: 2000); |
1880 | gpiod_set_value(desc: state->reset_gpio, value: 0); |
1881 | msleep(msecs: 20); |
1882 | } |
1883 | |
1884 | static int tc358743_probe_of(struct tc358743_state *state) |
1885 | { |
1886 | struct device *dev = &state->i2c_client->dev; |
1887 | struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 }; |
1888 | struct device_node *ep; |
1889 | struct clk *refclk; |
1890 | u32 bps_pr_lane; |
1891 | int ret; |
1892 | |
1893 | refclk = devm_clk_get(dev, id: "refclk" ); |
1894 | if (IS_ERR(ptr: refclk)) |
1895 | return dev_err_probe(dev, err: PTR_ERR(ptr: refclk), |
1896 | fmt: "failed to get refclk\n" ); |
1897 | |
1898 | ep = of_graph_get_endpoint_by_regs(parent: dev->of_node, port_reg: 0, reg: -1); |
1899 | if (!ep) { |
1900 | dev_err(dev, "missing endpoint node\n" ); |
1901 | return -EINVAL; |
1902 | } |
1903 | |
1904 | ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), vep: &endpoint); |
1905 | if (ret) { |
1906 | dev_err(dev, "failed to parse endpoint\n" ); |
1907 | goto put_node; |
1908 | } |
1909 | |
1910 | if (endpoint.bus_type != V4L2_MBUS_CSI2_DPHY || |
1911 | endpoint.bus.mipi_csi2.num_data_lanes == 0 || |
1912 | endpoint.nr_of_link_frequencies == 0) { |
1913 | dev_err(dev, "missing CSI-2 properties in endpoint\n" ); |
1914 | ret = -EINVAL; |
1915 | goto free_endpoint; |
1916 | } |
1917 | |
1918 | if (endpoint.bus.mipi_csi2.num_data_lanes > 4) { |
1919 | dev_err(dev, "invalid number of lanes\n" ); |
1920 | ret = -EINVAL; |
1921 | goto free_endpoint; |
1922 | } |
1923 | |
1924 | state->bus = endpoint.bus.mipi_csi2; |
1925 | |
1926 | ret = clk_prepare_enable(clk: refclk); |
1927 | if (ret) { |
1928 | dev_err(dev, "Failed! to enable clock\n" ); |
1929 | goto free_endpoint; |
1930 | } |
1931 | |
1932 | state->pdata.refclk_hz = clk_get_rate(clk: refclk); |
1933 | state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS; |
1934 | state->pdata.enable_hdcp = false; |
1935 | /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */ |
1936 | state->pdata.fifo_level = 16; |
1937 | /* |
1938 | * The PLL input clock is obtained by dividing refclk by pll_prd. |
1939 | * It must be between 6 MHz and 40 MHz, lower frequency is better. |
1940 | */ |
1941 | switch (state->pdata.refclk_hz) { |
1942 | case 26000000: |
1943 | case 27000000: |
1944 | case 42000000: |
1945 | state->pdata.pll_prd = state->pdata.refclk_hz / 6000000; |
1946 | break; |
1947 | default: |
1948 | dev_err(dev, "unsupported refclk rate: %u Hz\n" , |
1949 | state->pdata.refclk_hz); |
1950 | goto disable_clk; |
1951 | } |
1952 | |
1953 | /* |
1954 | * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps. |
1955 | * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60. |
1956 | */ |
1957 | bps_pr_lane = 2 * endpoint.link_frequencies[0]; |
1958 | if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) { |
1959 | dev_err(dev, "unsupported bps per lane: %u bps\n" , bps_pr_lane); |
1960 | ret = -EINVAL; |
1961 | goto disable_clk; |
1962 | } |
1963 | |
1964 | /* The CSI speed per lane is refclk / pll_prd * pll_fbd */ |
1965 | state->pdata.pll_fbd = bps_pr_lane / |
1966 | state->pdata.refclk_hz * state->pdata.pll_prd; |
1967 | |
1968 | /* |
1969 | * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz |
1970 | * link frequency). In principle it should be possible to calculate |
1971 | * them based on link frequency and resolution. |
1972 | */ |
1973 | if (bps_pr_lane != 594000000U) |
1974 | dev_warn(dev, "untested bps per lane: %u bps\n" , bps_pr_lane); |
1975 | state->pdata.lineinitcnt = 0xe80; |
1976 | state->pdata.lptxtimecnt = 0x003; |
1977 | /* tclk-preparecnt: 3, tclk-zerocnt: 20 */ |
1978 | state->pdata.tclk_headercnt = 0x1403; |
1979 | state->pdata.tclk_trailcnt = 0x00; |
1980 | /* ths-preparecnt: 3, ths-zerocnt: 1 */ |
1981 | state->pdata.ths_headercnt = 0x0103; |
1982 | state->pdata.twakeup = 0x4882; |
1983 | state->pdata.tclk_postcnt = 0x008; |
1984 | state->pdata.ths_trailcnt = 0x2; |
1985 | state->pdata.hstxvregcnt = 0; |
1986 | |
1987 | state->reset_gpio = devm_gpiod_get_optional(dev, con_id: "reset" , |
1988 | flags: GPIOD_OUT_LOW); |
1989 | if (IS_ERR(ptr: state->reset_gpio)) { |
1990 | dev_err(dev, "failed to get reset gpio\n" ); |
1991 | ret = PTR_ERR(ptr: state->reset_gpio); |
1992 | goto disable_clk; |
1993 | } |
1994 | |
1995 | if (state->reset_gpio) |
1996 | tc358743_gpio_reset(state); |
1997 | |
1998 | ret = 0; |
1999 | goto free_endpoint; |
2000 | |
2001 | disable_clk: |
2002 | clk_disable_unprepare(clk: refclk); |
2003 | free_endpoint: |
2004 | v4l2_fwnode_endpoint_free(vep: &endpoint); |
2005 | put_node: |
2006 | of_node_put(node: ep); |
2007 | return ret; |
2008 | } |
2009 | #else |
2010 | static inline int tc358743_probe_of(struct tc358743_state *state) |
2011 | { |
2012 | return -ENODEV; |
2013 | } |
2014 | #endif |
2015 | |
2016 | static int tc358743_probe(struct i2c_client *client) |
2017 | { |
2018 | static struct v4l2_dv_timings default_timing = |
2019 | V4L2_DV_BT_CEA_640X480P59_94; |
2020 | struct tc358743_state *state; |
2021 | struct tc358743_platform_data *pdata = client->dev.platform_data; |
2022 | struct v4l2_subdev *sd; |
2023 | u16 irq_mask = MASK_HDMI_MSK | MASK_CSI_MSK; |
2024 | int err; |
2025 | |
2026 | if (!i2c_check_functionality(adap: client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) |
2027 | return -EIO; |
2028 | v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n" , |
2029 | client->addr << 1, client->adapter->name); |
2030 | |
2031 | state = devm_kzalloc(dev: &client->dev, size: sizeof(struct tc358743_state), |
2032 | GFP_KERNEL); |
2033 | if (!state) |
2034 | return -ENOMEM; |
2035 | |
2036 | state->i2c_client = client; |
2037 | |
2038 | /* platform data */ |
2039 | if (pdata) { |
2040 | state->pdata = *pdata; |
2041 | state->bus.flags = 0; |
2042 | } else { |
2043 | err = tc358743_probe_of(state); |
2044 | if (err == -ENODEV) |
2045 | v4l_err(client, "No platform data!\n" ); |
2046 | if (err) |
2047 | return err; |
2048 | } |
2049 | |
2050 | sd = &state->sd; |
2051 | v4l2_i2c_subdev_init(sd, client, ops: &tc358743_ops); |
2052 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; |
2053 | |
2054 | /* i2c access */ |
2055 | if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) { |
2056 | v4l2_info(sd, "not a TC358743 on address 0x%x\n" , |
2057 | client->addr << 1); |
2058 | return -ENODEV; |
2059 | } |
2060 | |
2061 | /* control handlers */ |
2062 | v4l2_ctrl_handler_init(&state->hdl, 3); |
2063 | |
2064 | state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl: &state->hdl, NULL, |
2065 | V4L2_CID_DV_RX_POWER_PRESENT, min: 0, max: 1, step: 0, def: 0); |
2066 | |
2067 | /* custom controls */ |
2068 | state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(hdl: &state->hdl, |
2069 | cfg: &tc358743_ctrl_audio_sampling_rate, NULL); |
2070 | |
2071 | state->audio_present_ctrl = v4l2_ctrl_new_custom(hdl: &state->hdl, |
2072 | cfg: &tc358743_ctrl_audio_present, NULL); |
2073 | |
2074 | sd->ctrl_handler = &state->hdl; |
2075 | if (state->hdl.error) { |
2076 | err = state->hdl.error; |
2077 | goto err_hdl; |
2078 | } |
2079 | |
2080 | if (tc358743_update_controls(sd)) { |
2081 | err = -ENODEV; |
2082 | goto err_hdl; |
2083 | } |
2084 | |
2085 | state->pad.flags = MEDIA_PAD_FL_SOURCE; |
2086 | sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; |
2087 | err = media_entity_pads_init(entity: &sd->entity, num_pads: 1, pads: &state->pad); |
2088 | if (err < 0) |
2089 | goto err_hdl; |
2090 | |
2091 | state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24; |
2092 | |
2093 | sd->dev = &client->dev; |
2094 | |
2095 | mutex_init(&state->confctl_mutex); |
2096 | |
2097 | INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, |
2098 | tc358743_delayed_work_enable_hotplug); |
2099 | |
2100 | #ifdef CONFIG_VIDEO_TC358743_CEC |
2101 | state->cec_adap = cec_allocate_adapter(ops: &tc358743_cec_adap_ops, |
2102 | priv: state, name: dev_name(dev: &client->dev), |
2103 | CEC_CAP_DEFAULTS | CEC_CAP_MONITOR_ALL, CEC_MAX_LOG_ADDRS); |
2104 | if (IS_ERR(ptr: state->cec_adap)) { |
2105 | err = PTR_ERR(ptr: state->cec_adap); |
2106 | goto err_hdl; |
2107 | } |
2108 | irq_mask |= MASK_CEC_RMSK | MASK_CEC_TMSK; |
2109 | #endif |
2110 | |
2111 | tc358743_initial_setup(sd); |
2112 | |
2113 | tc358743_s_dv_timings(sd, timings: &default_timing); |
2114 | |
2115 | tc358743_set_csi_color_space(sd); |
2116 | |
2117 | tc358743_init_interrupts(sd); |
2118 | |
2119 | if (state->i2c_client->irq) { |
2120 | err = devm_request_threaded_irq(dev: &client->dev, |
2121 | irq: state->i2c_client->irq, |
2122 | NULL, thread_fn: tc358743_irq_handler, |
2123 | IRQF_TRIGGER_HIGH | IRQF_ONESHOT, |
2124 | devname: "tc358743" , dev_id: state); |
2125 | if (err) |
2126 | goto err_work_queues; |
2127 | } else { |
2128 | INIT_WORK(&state->work_i2c_poll, |
2129 | tc358743_work_i2c_poll); |
2130 | timer_setup(&state->timer, tc358743_irq_poll_timer, 0); |
2131 | state->timer.expires = jiffies + |
2132 | msecs_to_jiffies(POLL_INTERVAL_MS); |
2133 | add_timer(timer: &state->timer); |
2134 | } |
2135 | |
2136 | err = cec_register_adapter(adap: state->cec_adap, parent: &client->dev); |
2137 | if (err < 0) { |
2138 | pr_err("%s: failed to register the cec device\n" , __func__); |
2139 | cec_delete_adapter(adap: state->cec_adap); |
2140 | state->cec_adap = NULL; |
2141 | goto err_work_queues; |
2142 | } |
2143 | |
2144 | tc358743_enable_interrupts(sd, cable_connected: tx_5v_power_present(sd)); |
2145 | i2c_wr16(sd, INTMASK, val: ~irq_mask); |
2146 | |
2147 | err = v4l2_ctrl_handler_setup(hdl: sd->ctrl_handler); |
2148 | if (err) |
2149 | goto err_work_queues; |
2150 | |
2151 | err = v4l2_async_register_subdev(sd); |
2152 | if (err < 0) |
2153 | goto err_work_queues; |
2154 | |
2155 | v4l2_info(sd, "%s found @ 0x%x (%s)\n" , client->name, |
2156 | client->addr << 1, client->adapter->name); |
2157 | |
2158 | return 0; |
2159 | |
2160 | err_work_queues: |
2161 | cec_unregister_adapter(adap: state->cec_adap); |
2162 | if (!state->i2c_client->irq) |
2163 | flush_work(work: &state->work_i2c_poll); |
2164 | cancel_delayed_work(dwork: &state->delayed_work_enable_hotplug); |
2165 | mutex_destroy(lock: &state->confctl_mutex); |
2166 | err_hdl: |
2167 | media_entity_cleanup(entity: &sd->entity); |
2168 | v4l2_ctrl_handler_free(hdl: &state->hdl); |
2169 | return err; |
2170 | } |
2171 | |
2172 | static void tc358743_remove(struct i2c_client *client) |
2173 | { |
2174 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
2175 | struct tc358743_state *state = to_state(sd); |
2176 | |
2177 | if (!state->i2c_client->irq) { |
2178 | del_timer_sync(timer: &state->timer); |
2179 | flush_work(work: &state->work_i2c_poll); |
2180 | } |
2181 | cancel_delayed_work_sync(dwork: &state->delayed_work_enable_hotplug); |
2182 | cec_unregister_adapter(adap: state->cec_adap); |
2183 | v4l2_async_unregister_subdev(sd); |
2184 | v4l2_device_unregister_subdev(sd); |
2185 | mutex_destroy(lock: &state->confctl_mutex); |
2186 | media_entity_cleanup(entity: &sd->entity); |
2187 | v4l2_ctrl_handler_free(hdl: &state->hdl); |
2188 | } |
2189 | |
2190 | static const struct i2c_device_id tc358743_id[] = { |
2191 | {"tc358743" , 0}, |
2192 | {} |
2193 | }; |
2194 | |
2195 | MODULE_DEVICE_TABLE(i2c, tc358743_id); |
2196 | |
2197 | #if IS_ENABLED(CONFIG_OF) |
2198 | static const struct of_device_id tc358743_of_match[] = { |
2199 | { .compatible = "toshiba,tc358743" }, |
2200 | {}, |
2201 | }; |
2202 | MODULE_DEVICE_TABLE(of, tc358743_of_match); |
2203 | #endif |
2204 | |
2205 | static struct i2c_driver tc358743_driver = { |
2206 | .driver = { |
2207 | .name = "tc358743" , |
2208 | .of_match_table = of_match_ptr(tc358743_of_match), |
2209 | }, |
2210 | .probe = tc358743_probe, |
2211 | .remove = tc358743_remove, |
2212 | .id_table = tc358743_id, |
2213 | }; |
2214 | |
2215 | module_i2c_driver(tc358743_driver); |
2216 | |