1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Microchip Image Sensor Controller (ISC) driver header file
4 *
5 * Copyright (C) 2016-2019 Microchip Technology, Inc.
6 *
7 * Author: Songjun Wu
8 * Author: Eugen Hristev <eugen.hristev@microchip.com>
9 *
10 */
11#ifndef _MICROCHIP_ISC_H_
12
13#include <linux/clk-provider.h>
14#include <linux/platform_device.h>
15
16#include <media/v4l2-ctrls.h>
17#include <media/v4l2-device.h>
18#include <media/videobuf2-dma-contig.h>
19
20#define ISC_CLK_MAX_DIV 255
21
22enum isc_clk_id {
23 ISC_ISPCK = 0,
24 ISC_MCK = 1,
25};
26
27struct isc_clk {
28 struct clk_hw hw;
29 struct clk *clk;
30 struct regmap *regmap;
31 spinlock_t lock; /* serialize access to clock registers */
32 u8 id;
33 u8 parent_id;
34 u32 div;
35 struct device *dev;
36};
37
38#define to_isc_clk(v) container_of(v, struct isc_clk, hw)
39
40struct isc_buffer {
41 struct vb2_v4l2_buffer vb;
42 struct list_head list;
43};
44
45struct isc_subdev_entity {
46 struct v4l2_subdev *sd;
47 struct v4l2_async_connection *asd;
48 struct device_node *epn;
49 struct v4l2_async_notifier notifier;
50
51 u32 pfe_cfg0;
52
53 struct list_head list;
54};
55
56/*
57 * struct isc_format - ISC media bus format information
58 This structure represents the interface between the ISC
59 and the sensor. It's the input format received by
60 the ISC.
61 * @fourcc: Fourcc code for this format
62 * @mbus_code: V4L2 media bus format code.
63 * @cfa_baycfg: If this format is RAW BAYER, indicate the type of bayer.
64 this is either BGBG, RGRG, etc.
65 * @pfe_cfg0_bps: Number of hardware data lines connected to the ISC
66 * @raw: If the format is raw bayer.
67 */
68
69struct isc_format {
70 u32 fourcc;
71 u32 mbus_code;
72 u32 cfa_baycfg;
73 u32 pfe_cfg0_bps;
74
75 bool raw;
76};
77
78/* Pipeline bitmap */
79#define DPC_DPCENABLE BIT(0)
80#define DPC_GDCENABLE BIT(1)
81#define DPC_BLCENABLE BIT(2)
82#define WB_ENABLE BIT(3)
83#define CFA_ENABLE BIT(4)
84#define CC_ENABLE BIT(5)
85#define GAM_ENABLE BIT(6)
86#define GAM_BENABLE BIT(7)
87#define GAM_GENABLE BIT(8)
88#define GAM_RENABLE BIT(9)
89#define VHXS_ENABLE BIT(10)
90#define CSC_ENABLE BIT(11)
91#define CBC_ENABLE BIT(12)
92#define SUB422_ENABLE BIT(13)
93#define SUB420_ENABLE BIT(14)
94
95#define GAM_ENABLES (GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE)
96
97/*
98 * struct fmt_config - ISC format configuration and internal pipeline
99 This structure represents the internal configuration
100 of the ISC.
101 It also holds the format that ISC will present to v4l2.
102 * @sd_format: Pointer to an isc_format struct that holds the sensor
103 configuration.
104 * @fourcc: Fourcc code for this format.
105 * @bpp: Bytes per pixel in the current format.
106 * @bpp_v4l2: Bytes per pixel in the current format, for v4l2.
107 This differs from 'bpp' in the sense that in planar
108 formats, it refers only to the first plane.
109 * @rlp_cfg_mode: Configuration of the RLP (rounding, limiting packaging)
110 * @dcfg_imode: Configuration of the input of the DMA module
111 * @dctrl_dview: Configuration of the output of the DMA module
112 * @bits_pipeline: Configuration of the pipeline, which modules are enabled
113 */
114struct fmt_config {
115 struct isc_format *sd_format;
116
117 u32 fourcc;
118 u8 bpp;
119 u8 bpp_v4l2;
120
121 u32 rlp_cfg_mode;
122 u32 dcfg_imode;
123 u32 dctrl_dview;
124
125 u32 bits_pipeline;
126};
127
128#define HIST_ENTRIES 512
129#define HIST_BAYER (ISC_HIS_CFG_MODE_B + 1)
130
131enum{
132 HIST_INIT = 0,
133 HIST_ENABLED,
134 HIST_DISABLED,
135};
136
137struct isc_ctrls {
138 struct v4l2_ctrl_handler handler;
139
140 u32 brightness;
141 u32 contrast;
142 u8 gamma_index;
143#define ISC_WB_NONE 0
144#define ISC_WB_AUTO 1
145#define ISC_WB_ONETIME 2
146 u8 awb;
147
148 /* one for each component : GR, R, GB, B */
149 u32 gain[HIST_BAYER];
150 s32 offset[HIST_BAYER];
151
152 u32 hist_entry[HIST_ENTRIES];
153 u32 hist_count[HIST_BAYER];
154 u8 hist_id;
155 u8 hist_stat;
156#define HIST_MIN_INDEX 0
157#define HIST_MAX_INDEX 1
158 u32 hist_minmax[HIST_BAYER][2];
159};
160
161#define ISC_PIPE_LINE_NODE_NUM 15
162
163/*
164 * struct isc_reg_offsets - ISC device register offsets
165 * @csc: Offset for the CSC register
166 * @cbc: Offset for the CBC register
167 * @sub422: Offset for the SUB422 register
168 * @sub420: Offset for the SUB420 register
169 * @rlp: Offset for the RLP register
170 * @his: Offset for the HIS related registers
171 * @dma: Offset for the DMA related registers
172 * @version: Offset for the version register
173 * @his_entry: Offset for the HIS entries registers
174 */
175struct isc_reg_offsets {
176 u32 csc;
177 u32 cbc;
178 u32 sub422;
179 u32 sub420;
180 u32 rlp;
181 u32 his;
182 u32 dma;
183 u32 version;
184 u32 his_entry;
185};
186
187enum isc_mc_pads {
188 ISC_PAD_SINK = 0,
189 ISC_PADS_NUM = 1,
190};
191
192enum isc_scaler_pads {
193 ISC_SCALER_PAD_SINK = 0,
194 ISC_SCALER_PAD_SOURCE = 1,
195 ISC_SCALER_PADS_NUM = 2,
196};
197
198/*
199 * struct isc_device - ISC device driver data/config struct
200 * @regmap: Register map
201 * @hclock: Hclock clock input (refer datasheet)
202 * @ispck: iscpck clock (refer datasheet)
203 * @isc_clks: ISC clocks
204 * @ispck_required: ISC requires ISP Clock initialization
205 * @dcfg: DMA master configuration, architecture dependent
206 *
207 * @dev: Registered device driver
208 * @v4l2_dev: v4l2 registered device
209 * @video_dev: registered video device
210 *
211 * @vb2_vidq: video buffer 2 video queue
212 * @dma_queue_lock: lock to serialize the dma buffer queue
213 * @dma_queue: the queue for dma buffers
214 * @cur_frm: current isc frame/buffer
215 * @sequence: current frame number
216 * @stop: true if isc is not streaming, false if streaming
217 * @comp: completion reference that signals frame completion
218 *
219 * @fmt: current v42l format
220 * @try_fmt: current v4l2 try format
221 *
222 * @config: current ISC format configuration
223 * @try_config: the current ISC try format , not yet activated
224 *
225 * @ctrls: holds information about ISC controls
226 * @do_wb_ctrl: control regarding the DO_WHITE_BALANCE button
227 * @awb_work: workqueue reference for autowhitebalance histogram
228 * analysis
229 *
230 * @lock: lock for serializing userspace file operations
231 * with ISC operations
232 * @awb_mutex: serialize access to streaming status from awb work queue
233 * @awb_lock: lock for serializing awb work queue operations
234 * with DMA/buffer operations
235 *
236 * @pipeline: configuration of the ISC pipeline
237 *
238 * @current_subdev: current subdevice: the sensor
239 * @subdev_entities: list of subdevice entitites
240 *
241 * @gamma_table: pointer to the table with gamma values, has
242 * gamma_max sets of GAMMA_ENTRIES entries each
243 * @gamma_max: maximum number of sets of inside the gamma_table
244 *
245 * @max_width: maximum frame width, dependent on the internal RAM
246 * @max_height: maximum frame height, dependent on the internal RAM
247 *
248 * @config_dpc: pointer to a function that initializes product
249 * specific DPC module
250 * @config_csc: pointer to a function that initializes product
251 * specific CSC module
252 * @config_cbc: pointer to a function that initializes product
253 * specific CBC module
254 * @config_cc: pointer to a function that initializes product
255 * specific CC module
256 * @config_gam: pointer to a function that initializes product
257 * specific GAMMA module
258 * @config_rlp: pointer to a function that initializes product
259 * specific RLP module
260 * @config_ctrls: pointer to a functoin that initializes product
261 * specific v4l2 controls.
262 *
263 * @adapt_pipeline: pointer to a function that adapts the pipeline bits
264 * to the product specific pipeline
265 *
266 * @offsets: struct holding the product specific register offsets
267 * @controller_formats: pointer to the array of possible formats that the
268 * controller can output
269 * @formats_list: pointer to the array of possible formats that can
270 * be used as an input to the controller
271 * @controller_formats_size: size of controller_formats array
272 * @formats_list_size: size of formats_list array
273 * @pads: media controller pads for isc video entity
274 * @mdev: media device that is registered by the isc
275 * @mpipe: media device pipeline used by the isc
276 * @remote_pad: remote pad on the connected subdevice
277 * @scaler_sd: subdevice for the scaler that isc registers
278 * @scaler_pads: media controller pads for the scaler subdevice
279 * @scaler_format: current format for the scaler subdevice
280 */
281struct isc_device {
282 struct regmap *regmap;
283 struct clk *hclock;
284 struct clk *ispck;
285 struct isc_clk isc_clks[2];
286 bool ispck_required;
287 u32 dcfg;
288
289 struct device *dev;
290 struct v4l2_device v4l2_dev;
291 struct video_device video_dev;
292
293 struct vb2_queue vb2_vidq;
294 spinlock_t dma_queue_lock;
295 struct list_head dma_queue;
296 struct isc_buffer *cur_frm;
297 unsigned int sequence;
298 bool stop;
299 struct completion comp;
300
301 struct v4l2_format fmt;
302 struct v4l2_format try_fmt;
303
304 struct fmt_config config;
305 struct fmt_config try_config;
306
307 struct isc_ctrls ctrls;
308 struct work_struct awb_work;
309
310 struct mutex lock;
311 struct mutex awb_mutex;
312 spinlock_t awb_lock;
313
314 struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM];
315
316 struct isc_subdev_entity *current_subdev;
317 struct list_head subdev_entities;
318
319 struct {
320#define ISC_CTRL_DO_WB 1
321#define ISC_CTRL_R_GAIN 2
322#define ISC_CTRL_B_GAIN 3
323#define ISC_CTRL_GR_GAIN 4
324#define ISC_CTRL_GB_GAIN 5
325#define ISC_CTRL_R_OFF 6
326#define ISC_CTRL_B_OFF 7
327#define ISC_CTRL_GR_OFF 8
328#define ISC_CTRL_GB_OFF 9
329 struct v4l2_ctrl *awb_ctrl;
330 struct v4l2_ctrl *do_wb_ctrl;
331 struct v4l2_ctrl *r_gain_ctrl;
332 struct v4l2_ctrl *b_gain_ctrl;
333 struct v4l2_ctrl *gr_gain_ctrl;
334 struct v4l2_ctrl *gb_gain_ctrl;
335 struct v4l2_ctrl *r_off_ctrl;
336 struct v4l2_ctrl *b_off_ctrl;
337 struct v4l2_ctrl *gr_off_ctrl;
338 struct v4l2_ctrl *gb_off_ctrl;
339 };
340
341#define GAMMA_ENTRIES 64
342 /* pointer to the defined gamma table */
343 const u32 (*gamma_table)[GAMMA_ENTRIES];
344 u32 gamma_max;
345
346 u32 max_width;
347 u32 max_height;
348
349 struct {
350 void (*config_dpc)(struct isc_device *isc);
351 void (*config_csc)(struct isc_device *isc);
352 void (*config_cbc)(struct isc_device *isc);
353 void (*config_cc)(struct isc_device *isc);
354 void (*config_gam)(struct isc_device *isc);
355 void (*config_rlp)(struct isc_device *isc);
356
357 void (*config_ctrls)(struct isc_device *isc,
358 const struct v4l2_ctrl_ops *ops);
359
360 void (*adapt_pipeline)(struct isc_device *isc);
361 };
362
363 struct isc_reg_offsets offsets;
364 const struct isc_format *controller_formats;
365 struct isc_format *formats_list;
366 u32 controller_formats_size;
367 u32 formats_list_size;
368
369 struct {
370 struct media_pad pads[ISC_PADS_NUM];
371 struct media_device mdev;
372 struct media_pipeline mpipe;
373
374 u32 remote_pad;
375 };
376
377 struct {
378 struct v4l2_subdev scaler_sd;
379 struct media_pad scaler_pads[ISC_SCALER_PADS_NUM];
380 struct v4l2_mbus_framefmt scaler_format[ISC_SCALER_PADS_NUM];
381 };
382};
383
384extern const struct regmap_config microchip_isc_regmap_config;
385extern const struct v4l2_async_notifier_operations microchip_isc_async_ops;
386
387irqreturn_t microchip_isc_interrupt(int irq, void *dev_id);
388int microchip_isc_pipeline_init(struct isc_device *isc);
389int microchip_isc_clk_init(struct isc_device *isc);
390void microchip_isc_subdev_cleanup(struct isc_device *isc);
391void microchip_isc_clk_cleanup(struct isc_device *isc);
392
393int isc_scaler_link(struct isc_device *isc);
394int isc_scaler_init(struct isc_device *isc);
395int isc_mc_init(struct isc_device *isc, u32 ver);
396void isc_mc_cleanup(struct isc_device *isc);
397
398struct isc_format *isc_find_format_by_code(struct isc_device *isc,
399 unsigned int code, int *index);
400#endif
401

source code of linux/drivers/media/platform/microchip/microchip-isc.h