1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for Xilinx MIPI CSI-2 Rx Subsystem
4 *
5 * Copyright (C) 2016 - 2020 Xilinx, Inc.
6 *
7 * Contacts: Vishal Sagar <vishal.sagar@xilinx.com>
8 *
9 */
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/gpio/consumer.h>
13#include <linux/interrupt.h>
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <linux/of.h>
17#include <linux/of_irq.h>
18#include <linux/platform_device.h>
19#include <linux/v4l2-subdev.h>
20#include <media/media-entity.h>
21#include <media/mipi-csi2.h>
22#include <media/v4l2-common.h>
23#include <media/v4l2-ctrls.h>
24#include <media/v4l2-fwnode.h>
25#include <media/v4l2-subdev.h>
26#include "xilinx-vip.h"
27
28/* Register register map */
29#define XCSI_CCR_OFFSET 0x00
30#define XCSI_CCR_SOFTRESET BIT(1)
31#define XCSI_CCR_ENABLE BIT(0)
32
33#define XCSI_PCR_OFFSET 0x04
34#define XCSI_PCR_MAXLANES_MASK GENMASK(4, 3)
35#define XCSI_PCR_ACTLANES_MASK GENMASK(1, 0)
36
37#define XCSI_CSR_OFFSET 0x10
38#define XCSI_CSR_PKTCNT GENMASK(31, 16)
39#define XCSI_CSR_SPFIFOFULL BIT(3)
40#define XCSI_CSR_SPFIFONE BIT(2)
41#define XCSI_CSR_SLBF BIT(1)
42#define XCSI_CSR_RIPCD BIT(0)
43
44#define XCSI_GIER_OFFSET 0x20
45#define XCSI_GIER_GIE BIT(0)
46
47#define XCSI_ISR_OFFSET 0x24
48#define XCSI_IER_OFFSET 0x28
49
50#define XCSI_ISR_FR BIT(31)
51#define XCSI_ISR_VCXFE BIT(30)
52#define XCSI_ISR_WCC BIT(22)
53#define XCSI_ISR_ILC BIT(21)
54#define XCSI_ISR_SPFIFOF BIT(20)
55#define XCSI_ISR_SPFIFONE BIT(19)
56#define XCSI_ISR_SLBF BIT(18)
57#define XCSI_ISR_STOP BIT(17)
58#define XCSI_ISR_SOTERR BIT(13)
59#define XCSI_ISR_SOTSYNCERR BIT(12)
60#define XCSI_ISR_ECC2BERR BIT(11)
61#define XCSI_ISR_ECC1BERR BIT(10)
62#define XCSI_ISR_CRCERR BIT(9)
63#define XCSI_ISR_DATAIDERR BIT(8)
64#define XCSI_ISR_VC3FSYNCERR BIT(7)
65#define XCSI_ISR_VC3FLVLERR BIT(6)
66#define XCSI_ISR_VC2FSYNCERR BIT(5)
67#define XCSI_ISR_VC2FLVLERR BIT(4)
68#define XCSI_ISR_VC1FSYNCERR BIT(3)
69#define XCSI_ISR_VC1FLVLERR BIT(2)
70#define XCSI_ISR_VC0FSYNCERR BIT(1)
71#define XCSI_ISR_VC0FLVLERR BIT(0)
72
73#define XCSI_ISR_ALLINTR_MASK (0xc07e3fff)
74
75/*
76 * Removed VCXFE mask as it doesn't exist in IER
77 * Removed STOP state irq as this will keep driver in irq handler only
78 */
79#define XCSI_IER_INTR_MASK (XCSI_ISR_ALLINTR_MASK &\
80 ~(XCSI_ISR_STOP | XCSI_ISR_VCXFE))
81
82#define XCSI_SPKTR_OFFSET 0x30
83#define XCSI_SPKTR_DATA GENMASK(23, 8)
84#define XCSI_SPKTR_VC GENMASK(7, 6)
85#define XCSI_SPKTR_DT GENMASK(5, 0)
86#define XCSI_SPKT_FIFO_DEPTH 31
87
88#define XCSI_VCXR_OFFSET 0x34
89#define XCSI_VCXR_VCERR GENMASK(23, 0)
90#define XCSI_VCXR_FSYNCERR BIT(1)
91#define XCSI_VCXR_FLVLERR BIT(0)
92
93#define XCSI_CLKINFR_OFFSET 0x3C
94#define XCSI_CLKINFR_STOP BIT(1)
95
96#define XCSI_DLXINFR_OFFSET 0x40
97#define XCSI_DLXINFR_STOP BIT(5)
98#define XCSI_DLXINFR_SOTERR BIT(1)
99#define XCSI_DLXINFR_SOTSYNCERR BIT(0)
100#define XCSI_MAXDL_COUNT 0x4
101
102#define XCSI_VCXINF1R_OFFSET 0x60
103#define XCSI_VCXINF1R_LINECOUNT GENMASK(31, 16)
104#define XCSI_VCXINF1R_LINECOUNT_SHIFT 16
105#define XCSI_VCXINF1R_BYTECOUNT GENMASK(15, 0)
106
107#define XCSI_VCXINF2R_OFFSET 0x64
108#define XCSI_VCXINF2R_DT GENMASK(5, 0)
109#define XCSI_MAXVCX_COUNT 16
110
111/*
112 * Sink pad connected to sensor source pad.
113 * Source pad connected to next module like demosaic.
114 */
115#define XCSI_MEDIA_PADS 2
116#define XCSI_DEFAULT_WIDTH 1920
117#define XCSI_DEFAULT_HEIGHT 1080
118
119#define XCSI_VCX_START 4
120#define XCSI_MAX_VC 4
121#define XCSI_MAX_VCX 16
122
123#define XCSI_NEXTREG_OFFSET 4
124
125/* There are 2 events frame sync and frame level error per VC */
126#define XCSI_VCX_NUM_EVENTS ((XCSI_MAX_VCX - XCSI_MAX_VC) * 2)
127
128/**
129 * struct xcsi2rxss_event - Event log structure
130 * @mask: Event mask
131 * @name: Name of the event
132 */
133struct xcsi2rxss_event {
134 u32 mask;
135 const char *name;
136};
137
138static const struct xcsi2rxss_event xcsi2rxss_events[] = {
139 { XCSI_ISR_FR, "Frame Received" },
140 { XCSI_ISR_VCXFE, "VCX Frame Errors" },
141 { XCSI_ISR_WCC, "Word Count Errors" },
142 { XCSI_ISR_ILC, "Invalid Lane Count Error" },
143 { XCSI_ISR_SPFIFOF, "Short Packet FIFO OverFlow Error" },
144 { XCSI_ISR_SPFIFONE, "Short Packet FIFO Not Empty" },
145 { XCSI_ISR_SLBF, "Streamline Buffer Full Error" },
146 { XCSI_ISR_STOP, "Lane Stop State" },
147 { XCSI_ISR_SOTERR, "SOT Error" },
148 { XCSI_ISR_SOTSYNCERR, "SOT Sync Error" },
149 { XCSI_ISR_ECC2BERR, "2 Bit ECC Unrecoverable Error" },
150 { XCSI_ISR_ECC1BERR, "1 Bit ECC Recoverable Error" },
151 { XCSI_ISR_CRCERR, "CRC Error" },
152 { XCSI_ISR_DATAIDERR, "Data Id Error" },
153 { XCSI_ISR_VC3FSYNCERR, "Virtual Channel 3 Frame Sync Error" },
154 { XCSI_ISR_VC3FLVLERR, "Virtual Channel 3 Frame Level Error" },
155 { XCSI_ISR_VC2FSYNCERR, "Virtual Channel 2 Frame Sync Error" },
156 { XCSI_ISR_VC2FLVLERR, "Virtual Channel 2 Frame Level Error" },
157 { XCSI_ISR_VC1FSYNCERR, "Virtual Channel 1 Frame Sync Error" },
158 { XCSI_ISR_VC1FLVLERR, "Virtual Channel 1 Frame Level Error" },
159 { XCSI_ISR_VC0FSYNCERR, "Virtual Channel 0 Frame Sync Error" },
160 { XCSI_ISR_VC0FLVLERR, "Virtual Channel 0 Frame Level Error" }
161};
162
163#define XCSI_NUM_EVENTS ARRAY_SIZE(xcsi2rxss_events)
164
165/*
166 * This table provides a mapping between CSI-2 Data type
167 * and media bus formats
168 */
169static const u32 xcsi2dt_mbus_lut[][2] = {
170 { MIPI_CSI2_DT_YUV422_8B, MEDIA_BUS_FMT_UYVY8_1X16 },
171 { MIPI_CSI2_DT_YUV422_10B, MEDIA_BUS_FMT_UYVY10_1X20 },
172 { MIPI_CSI2_DT_RGB444, 0 },
173 { MIPI_CSI2_DT_RGB555, 0 },
174 { MIPI_CSI2_DT_RGB565, 0 },
175 { MIPI_CSI2_DT_RGB666, 0 },
176 { MIPI_CSI2_DT_RGB888, MEDIA_BUS_FMT_RBG888_1X24 },
177 { MIPI_CSI2_DT_RAW6, 0 },
178 { MIPI_CSI2_DT_RAW7, 0 },
179 { MIPI_CSI2_DT_RAW8, MEDIA_BUS_FMT_SRGGB8_1X8 },
180 { MIPI_CSI2_DT_RAW8, MEDIA_BUS_FMT_SBGGR8_1X8 },
181 { MIPI_CSI2_DT_RAW8, MEDIA_BUS_FMT_SGBRG8_1X8 },
182 { MIPI_CSI2_DT_RAW8, MEDIA_BUS_FMT_SGRBG8_1X8 },
183 { MIPI_CSI2_DT_RAW10, MEDIA_BUS_FMT_SRGGB10_1X10 },
184 { MIPI_CSI2_DT_RAW10, MEDIA_BUS_FMT_SBGGR10_1X10 },
185 { MIPI_CSI2_DT_RAW10, MEDIA_BUS_FMT_SGBRG10_1X10 },
186 { MIPI_CSI2_DT_RAW10, MEDIA_BUS_FMT_SGRBG10_1X10 },
187 { MIPI_CSI2_DT_RAW12, MEDIA_BUS_FMT_SRGGB12_1X12 },
188 { MIPI_CSI2_DT_RAW12, MEDIA_BUS_FMT_SBGGR12_1X12 },
189 { MIPI_CSI2_DT_RAW12, MEDIA_BUS_FMT_SGBRG12_1X12 },
190 { MIPI_CSI2_DT_RAW12, MEDIA_BUS_FMT_SGRBG12_1X12 },
191 { MIPI_CSI2_DT_RAW12, MEDIA_BUS_FMT_Y12_1X12 },
192 { MIPI_CSI2_DT_RAW16, MEDIA_BUS_FMT_SRGGB16_1X16 },
193 { MIPI_CSI2_DT_RAW16, MEDIA_BUS_FMT_SBGGR16_1X16 },
194 { MIPI_CSI2_DT_RAW16, MEDIA_BUS_FMT_SGBRG16_1X16 },
195 { MIPI_CSI2_DT_RAW16, MEDIA_BUS_FMT_SGRBG16_1X16 },
196 { MIPI_CSI2_DT_RAW20, 0 },
197};
198
199/**
200 * struct xcsi2rxss_state - CSI-2 Rx Subsystem device structure
201 * @subdev: The v4l2 subdev structure
202 * @format: Active V4L2 formats on each pad
203 * @default_format: Default V4L2 format
204 * @events: counter for events
205 * @vcx_events: counter for vcx_events
206 * @dev: Platform structure
207 * @rsubdev: Remote subdev connected to sink pad
208 * @rst_gpio: reset to video_aresetn
209 * @clks: array of clocks
210 * @iomem: Base address of subsystem
211 * @max_num_lanes: Maximum number of lanes present
212 * @datatype: Data type filter
213 * @lock: mutex for accessing this structure
214 * @pads: media pads
215 * @streaming: Flag for storing streaming state
216 * @enable_active_lanes: If number of active lanes can be modified
217 * @en_vcx: If more than 4 VC are enabled
218 *
219 * This structure contains the device driver related parameters
220 */
221struct xcsi2rxss_state {
222 struct v4l2_subdev subdev;
223 struct v4l2_mbus_framefmt format;
224 struct v4l2_mbus_framefmt default_format;
225 u32 events[XCSI_NUM_EVENTS];
226 u32 vcx_events[XCSI_VCX_NUM_EVENTS];
227 struct device *dev;
228 struct v4l2_subdev *rsubdev;
229 struct gpio_desc *rst_gpio;
230 struct clk_bulk_data *clks;
231 void __iomem *iomem;
232 u32 max_num_lanes;
233 u32 datatype;
234 /* used to protect access to this struct */
235 struct mutex lock;
236 struct media_pad pads[XCSI_MEDIA_PADS];
237 bool streaming;
238 bool enable_active_lanes;
239 bool en_vcx;
240};
241
242static const struct clk_bulk_data xcsi2rxss_clks[] = {
243 { .id = "lite_aclk" },
244 { .id = "video_aclk" },
245};
246
247static inline struct xcsi2rxss_state *
248to_xcsi2rxssstate(struct v4l2_subdev *subdev)
249{
250 return container_of(subdev, struct xcsi2rxss_state, subdev);
251}
252
253/*
254 * Register related operations
255 */
256static inline u32 xcsi2rxss_read(struct xcsi2rxss_state *xcsi2rxss, u32 addr)
257{
258 return ioread32(xcsi2rxss->iomem + addr);
259}
260
261static inline void xcsi2rxss_write(struct xcsi2rxss_state *xcsi2rxss, u32 addr,
262 u32 value)
263{
264 iowrite32(value, xcsi2rxss->iomem + addr);
265}
266
267static inline void xcsi2rxss_clr(struct xcsi2rxss_state *xcsi2rxss, u32 addr,
268 u32 clr)
269{
270 xcsi2rxss_write(xcsi2rxss, addr,
271 value: xcsi2rxss_read(xcsi2rxss, addr) & ~clr);
272}
273
274static inline void xcsi2rxss_set(struct xcsi2rxss_state *xcsi2rxss, u32 addr,
275 u32 set)
276{
277 xcsi2rxss_write(xcsi2rxss, addr, value: xcsi2rxss_read(xcsi2rxss, addr) | set);
278}
279
280/*
281 * This function returns the nth mbus for a data type.
282 * In case of error, mbus code returned is 0.
283 */
284static u32 xcsi2rxss_get_nth_mbus(u32 dt, u32 n)
285{
286 unsigned int i;
287
288 for (i = 0; i < ARRAY_SIZE(xcsi2dt_mbus_lut); i++) {
289 if (xcsi2dt_mbus_lut[i][0] == dt) {
290 if (n-- == 0)
291 return xcsi2dt_mbus_lut[i][1];
292 }
293 }
294
295 return 0;
296}
297
298/* This returns the data type for a media bus format else 0 */
299static u32 xcsi2rxss_get_dt(u32 mbus)
300{
301 unsigned int i;
302
303 for (i = 0; i < ARRAY_SIZE(xcsi2dt_mbus_lut); i++) {
304 if (xcsi2dt_mbus_lut[i][1] == mbus)
305 return xcsi2dt_mbus_lut[i][0];
306 }
307
308 return 0;
309}
310
311/**
312 * xcsi2rxss_soft_reset - Does a soft reset of the MIPI CSI-2 Rx Subsystem
313 * @state: Xilinx CSI-2 Rx Subsystem structure pointer
314 *
315 * Core takes less than 100 video clock cycles to reset.
316 * So a larger timeout value is chosen for margin.
317 *
318 * Return: 0 - on success OR -ETIME if reset times out
319 */
320static int xcsi2rxss_soft_reset(struct xcsi2rxss_state *state)
321{
322 u32 timeout = 1000; /* us */
323
324 xcsi2rxss_set(xcsi2rxss: state, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET);
325
326 while (xcsi2rxss_read(xcsi2rxss: state, XCSI_CSR_OFFSET) & XCSI_CSR_RIPCD) {
327 if (timeout == 0) {
328 dev_err(state->dev, "soft reset timed out!\n");
329 return -ETIME;
330 }
331
332 timeout--;
333 udelay(usec: 1);
334 }
335
336 xcsi2rxss_clr(xcsi2rxss: state, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET);
337 return 0;
338}
339
340static void xcsi2rxss_hard_reset(struct xcsi2rxss_state *state)
341{
342 if (!state->rst_gpio)
343 return;
344
345 /* minimum of 40 dphy_clk_200M cycles */
346 gpiod_set_value_cansleep(desc: state->rst_gpio, value: 1);
347 usleep_range(min: 1, max: 2);
348 gpiod_set_value_cansleep(desc: state->rst_gpio, value: 0);
349}
350
351static void xcsi2rxss_reset_event_counters(struct xcsi2rxss_state *state)
352{
353 unsigned int i;
354
355 for (i = 0; i < XCSI_NUM_EVENTS; i++)
356 state->events[i] = 0;
357
358 for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++)
359 state->vcx_events[i] = 0;
360}
361
362/* Print event counters */
363static void xcsi2rxss_log_counters(struct xcsi2rxss_state *state)
364{
365 struct device *dev = state->dev;
366 unsigned int i;
367
368 for (i = 0; i < XCSI_NUM_EVENTS; i++) {
369 if (state->events[i] > 0) {
370 dev_info(dev, "%s events: %d\n",
371 xcsi2rxss_events[i].name,
372 state->events[i]);
373 }
374 }
375
376 if (state->en_vcx) {
377 for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++) {
378 if (state->vcx_events[i] > 0) {
379 dev_info(dev,
380 "VC %d Frame %s err vcx events: %d\n",
381 (i / 2) + XCSI_VCX_START,
382 i & 1 ? "Sync" : "Level",
383 state->vcx_events[i]);
384 }
385 }
386 }
387}
388
389static int xcsi2rxss_log_status(struct v4l2_subdev *sd)
390{
391 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(subdev: sd);
392 struct device *dev = xcsi2rxss->dev;
393 u32 reg, data;
394 unsigned int i, max_vc;
395
396 mutex_lock(&xcsi2rxss->lock);
397
398 xcsi2rxss_log_counters(state: xcsi2rxss);
399
400 dev_info(dev, "***** Core Status *****\n");
401 data = xcsi2rxss_read(xcsi2rxss, XCSI_CSR_OFFSET);
402 dev_info(dev, "Short Packet FIFO Full = %s\n",
403 data & XCSI_CSR_SPFIFOFULL ? "true" : "false");
404 dev_info(dev, "Short Packet FIFO Not Empty = %s\n",
405 data & XCSI_CSR_SPFIFONE ? "true" : "false");
406 dev_info(dev, "Stream line buffer full = %s\n",
407 data & XCSI_CSR_SLBF ? "true" : "false");
408 dev_info(dev, "Soft reset/Core disable in progress = %s\n",
409 data & XCSI_CSR_RIPCD ? "true" : "false");
410
411 /* Clk & Lane Info */
412 dev_info(dev, "******** Clock Lane Info *********\n");
413 data = xcsi2rxss_read(xcsi2rxss, XCSI_CLKINFR_OFFSET);
414 dev_info(dev, "Clock Lane in Stop State = %s\n",
415 data & XCSI_CLKINFR_STOP ? "true" : "false");
416
417 dev_info(dev, "******** Data Lane Info *********\n");
418 dev_info(dev, "Lane\tSoT Error\tSoT Sync Error\tStop State\n");
419 reg = XCSI_DLXINFR_OFFSET;
420 for (i = 0; i < XCSI_MAXDL_COUNT; i++) {
421 data = xcsi2rxss_read(xcsi2rxss, addr: reg);
422
423 dev_info(dev, "%d\t%s\t\t%s\t\t%s\n", i,
424 data & XCSI_DLXINFR_SOTERR ? "true" : "false",
425 data & XCSI_DLXINFR_SOTSYNCERR ? "true" : "false",
426 data & XCSI_DLXINFR_STOP ? "true" : "false");
427
428 reg += XCSI_NEXTREG_OFFSET;
429 }
430
431 /* Virtual Channel Image Information */
432 dev_info(dev, "********** Virtual Channel Info ************\n");
433 dev_info(dev, "VC\tLine Count\tByte Count\tData Type\n");
434 if (xcsi2rxss->en_vcx)
435 max_vc = XCSI_MAX_VCX;
436 else
437 max_vc = XCSI_MAX_VC;
438
439 reg = XCSI_VCXINF1R_OFFSET;
440 for (i = 0; i < max_vc; i++) {
441 u32 line_count, byte_count, data_type;
442
443 /* Get line and byte count from VCXINFR1 Register */
444 data = xcsi2rxss_read(xcsi2rxss, addr: reg);
445 byte_count = data & XCSI_VCXINF1R_BYTECOUNT;
446 line_count = data & XCSI_VCXINF1R_LINECOUNT;
447 line_count >>= XCSI_VCXINF1R_LINECOUNT_SHIFT;
448
449 /* Get data type from VCXINFR2 Register */
450 reg += XCSI_NEXTREG_OFFSET;
451 data = xcsi2rxss_read(xcsi2rxss, addr: reg);
452 data_type = data & XCSI_VCXINF2R_DT;
453
454 dev_info(dev, "%d\t%d\t\t%d\t\t0x%x\n", i, line_count,
455 byte_count, data_type);
456
457 /* Move to next pair of VC Info registers */
458 reg += XCSI_NEXTREG_OFFSET;
459 }
460
461 mutex_unlock(lock: &xcsi2rxss->lock);
462
463 return 0;
464}
465
466static struct v4l2_subdev *xcsi2rxss_get_remote_subdev(struct media_pad *local)
467{
468 struct media_pad *remote;
469
470 remote = media_pad_remote_pad_first(pad: local);
471 if (!remote || !is_media_entity_v4l2_subdev(entity: remote->entity))
472 return NULL;
473
474 return media_entity_to_v4l2_subdev(remote->entity);
475}
476
477static int xcsi2rxss_start_stream(struct xcsi2rxss_state *state)
478{
479 int ret = 0;
480
481 /* enable core */
482 xcsi2rxss_set(xcsi2rxss: state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
483
484 ret = xcsi2rxss_soft_reset(state);
485 if (ret) {
486 state->streaming = false;
487 return ret;
488 }
489
490 /* enable interrupts */
491 xcsi2rxss_clr(xcsi2rxss: state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
492 xcsi2rxss_write(xcsi2rxss: state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
493 xcsi2rxss_set(xcsi2rxss: state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
494
495 state->streaming = true;
496
497 state->rsubdev =
498 xcsi2rxss_get_remote_subdev(local: &state->pads[XVIP_PAD_SINK]);
499
500 ret = v4l2_subdev_call(state->rsubdev, video, s_stream, 1);
501 if (ret) {
502 /* disable interrupts */
503 xcsi2rxss_clr(xcsi2rxss: state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
504 xcsi2rxss_clr(xcsi2rxss: state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
505
506 /* disable core */
507 xcsi2rxss_clr(xcsi2rxss: state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
508 state->streaming = false;
509 }
510
511 return ret;
512}
513
514static void xcsi2rxss_stop_stream(struct xcsi2rxss_state *state)
515{
516 v4l2_subdev_call(state->rsubdev, video, s_stream, 0);
517
518 /* disable interrupts */
519 xcsi2rxss_clr(xcsi2rxss: state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
520 xcsi2rxss_clr(xcsi2rxss: state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
521
522 /* disable core */
523 xcsi2rxss_clr(xcsi2rxss: state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
524 state->streaming = false;
525}
526
527/**
528 * xcsi2rxss_irq_handler - Interrupt handler for CSI-2
529 * @irq: IRQ number
530 * @data: Pointer to device state
531 *
532 * In the interrupt handler, a list of event counters are updated for
533 * corresponding interrupts. This is useful to get status / debug.
534 *
535 * Return: IRQ_HANDLED after handling interrupts
536 */
537static irqreturn_t xcsi2rxss_irq_handler(int irq, void *data)
538{
539 struct xcsi2rxss_state *state = (struct xcsi2rxss_state *)data;
540 struct device *dev = state->dev;
541 u32 status;
542
543 status = xcsi2rxss_read(xcsi2rxss: state, XCSI_ISR_OFFSET) & XCSI_ISR_ALLINTR_MASK;
544 xcsi2rxss_write(xcsi2rxss: state, XCSI_ISR_OFFSET, value: status);
545
546 /* Received a short packet */
547 if (status & XCSI_ISR_SPFIFONE) {
548 u32 count = 0;
549
550 /*
551 * Drain generic short packet FIFO by reading max 31
552 * (fifo depth) short packets from fifo or till fifo is empty.
553 */
554 for (count = 0; count < XCSI_SPKT_FIFO_DEPTH; ++count) {
555 u32 spfifostat, spkt;
556
557 spkt = xcsi2rxss_read(xcsi2rxss: state, XCSI_SPKTR_OFFSET);
558 dev_dbg(dev, "Short packet = 0x%08x\n", spkt);
559 spfifostat = xcsi2rxss_read(xcsi2rxss: state, XCSI_ISR_OFFSET);
560 spfifostat &= XCSI_ISR_SPFIFONE;
561 if (!spfifostat)
562 break;
563 xcsi2rxss_write(xcsi2rxss: state, XCSI_ISR_OFFSET, value: spfifostat);
564 }
565 }
566
567 /* Short packet FIFO overflow */
568 if (status & XCSI_ISR_SPFIFOF)
569 dev_dbg_ratelimited(dev, "Short packet FIFO overflowed\n");
570
571 /*
572 * Stream line buffer full
573 * This means there is a backpressure from downstream IP
574 */
575 if (status & XCSI_ISR_SLBF) {
576 dev_alert_ratelimited(dev, "Stream Line Buffer Full!\n");
577
578 /* disable interrupts */
579 xcsi2rxss_clr(xcsi2rxss: state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
580 xcsi2rxss_clr(xcsi2rxss: state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
581
582 /* disable core */
583 xcsi2rxss_clr(xcsi2rxss: state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
584
585 /*
586 * The IP needs to be hard reset before it can be used now.
587 * This will be done in streamoff.
588 */
589
590 /*
591 * TODO: Notify the whole pipeline with v4l2_subdev_notify() to
592 * inform userspace.
593 */
594 }
595
596 /* Increment event counters */
597 if (status & XCSI_ISR_ALLINTR_MASK) {
598 unsigned int i;
599
600 for (i = 0; i < XCSI_NUM_EVENTS; i++) {
601 if (!(status & xcsi2rxss_events[i].mask))
602 continue;
603 state->events[i]++;
604 dev_dbg_ratelimited(dev, "%s: %u\n",
605 xcsi2rxss_events[i].name,
606 state->events[i]);
607 }
608
609 if (status & XCSI_ISR_VCXFE && state->en_vcx) {
610 u32 vcxstatus;
611
612 vcxstatus = xcsi2rxss_read(xcsi2rxss: state, XCSI_VCXR_OFFSET);
613 vcxstatus &= XCSI_VCXR_VCERR;
614 for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++) {
615 if (!(vcxstatus & BIT(i)))
616 continue;
617 state->vcx_events[i]++;
618 }
619 xcsi2rxss_write(xcsi2rxss: state, XCSI_VCXR_OFFSET, value: vcxstatus);
620 }
621 }
622
623 return IRQ_HANDLED;
624}
625
626static int xcsi2rxss_s_stream(struct v4l2_subdev *sd, int enable)
627{
628 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(subdev: sd);
629 int ret = 0;
630
631 mutex_lock(&xcsi2rxss->lock);
632
633 if (enable == xcsi2rxss->streaming)
634 goto stream_done;
635
636 if (enable) {
637 xcsi2rxss_reset_event_counters(state: xcsi2rxss);
638 ret = xcsi2rxss_start_stream(state: xcsi2rxss);
639 } else {
640 xcsi2rxss_stop_stream(state: xcsi2rxss);
641 xcsi2rxss_hard_reset(state: xcsi2rxss);
642 }
643
644stream_done:
645 mutex_unlock(lock: &xcsi2rxss->lock);
646 return ret;
647}
648
649static struct v4l2_mbus_framefmt *
650__xcsi2rxss_get_pad_format(struct xcsi2rxss_state *xcsi2rxss,
651 struct v4l2_subdev_state *sd_state,
652 unsigned int pad, u32 which)
653{
654 switch (which) {
655 case V4L2_SUBDEV_FORMAT_TRY:
656 return v4l2_subdev_state_get_format(sd_state, pad);
657 case V4L2_SUBDEV_FORMAT_ACTIVE:
658 return &xcsi2rxss->format;
659 default:
660 return NULL;
661 }
662}
663
664static int xcsi2rxss_init_state(struct v4l2_subdev *sd,
665 struct v4l2_subdev_state *sd_state)
666{
667 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(subdev: sd);
668 struct v4l2_mbus_framefmt *format;
669 unsigned int i;
670
671 mutex_lock(&xcsi2rxss->lock);
672 for (i = 0; i < XCSI_MEDIA_PADS; i++) {
673 format = v4l2_subdev_state_get_format(sd_state, i);
674 *format = xcsi2rxss->default_format;
675 }
676 mutex_unlock(lock: &xcsi2rxss->lock);
677
678 return 0;
679}
680
681static int xcsi2rxss_get_format(struct v4l2_subdev *sd,
682 struct v4l2_subdev_state *sd_state,
683 struct v4l2_subdev_format *fmt)
684{
685 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(subdev: sd);
686
687 mutex_lock(&xcsi2rxss->lock);
688 fmt->format = *__xcsi2rxss_get_pad_format(xcsi2rxss, sd_state,
689 pad: fmt->pad,
690 which: fmt->which);
691 mutex_unlock(lock: &xcsi2rxss->lock);
692
693 return 0;
694}
695
696static int xcsi2rxss_set_format(struct v4l2_subdev *sd,
697 struct v4l2_subdev_state *sd_state,
698 struct v4l2_subdev_format *fmt)
699{
700 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(subdev: sd);
701 struct v4l2_mbus_framefmt *__format;
702 u32 dt;
703
704 mutex_lock(&xcsi2rxss->lock);
705
706 /*
707 * Only the format->code parameter matters for CSI as the
708 * CSI format cannot be changed at runtime.
709 * Ensure that format to set is copied to over to CSI pad format
710 */
711 __format = __xcsi2rxss_get_pad_format(xcsi2rxss, sd_state,
712 pad: fmt->pad, which: fmt->which);
713
714 /* only sink pad format can be updated */
715 if (fmt->pad == XVIP_PAD_SOURCE) {
716 fmt->format = *__format;
717 mutex_unlock(lock: &xcsi2rxss->lock);
718 return 0;
719 }
720
721 /*
722 * RAW8 is supported in all datatypes. So if requested media bus format
723 * is of RAW8 type, then allow to be set. In case core is configured to
724 * other RAW, YUV422 8/10 or RGB888, set appropriate media bus format.
725 */
726 dt = xcsi2rxss_get_dt(mbus: fmt->format.code);
727 if (dt != xcsi2rxss->datatype && dt != MIPI_CSI2_DT_RAW8) {
728 dev_dbg(xcsi2rxss->dev, "Unsupported media bus format");
729 /* set the default format for the data type */
730 fmt->format.code = xcsi2rxss_get_nth_mbus(dt: xcsi2rxss->datatype,
731 n: 0);
732 }
733
734 *__format = fmt->format;
735 mutex_unlock(lock: &xcsi2rxss->lock);
736
737 return 0;
738}
739
740static int xcsi2rxss_enum_mbus_code(struct v4l2_subdev *sd,
741 struct v4l2_subdev_state *sd_state,
742 struct v4l2_subdev_mbus_code_enum *code)
743{
744 struct xcsi2rxss_state *state = to_xcsi2rxssstate(subdev: sd);
745 u32 dt, n;
746 int ret = 0;
747
748 /* RAW8 dt packets are available in all DT configurations */
749 if (code->index < 4) {
750 n = code->index;
751 dt = MIPI_CSI2_DT_RAW8;
752 } else if (state->datatype != MIPI_CSI2_DT_RAW8) {
753 n = code->index - 4;
754 dt = state->datatype;
755 } else {
756 return -EINVAL;
757 }
758
759 code->code = xcsi2rxss_get_nth_mbus(dt, n);
760 if (!code->code)
761 ret = -EINVAL;
762
763 return ret;
764}
765
766/* -----------------------------------------------------------------------------
767 * Media Operations
768 */
769
770static const struct media_entity_operations xcsi2rxss_media_ops = {
771 .link_validate = v4l2_subdev_link_validate
772};
773
774static const struct v4l2_subdev_core_ops xcsi2rxss_core_ops = {
775 .log_status = xcsi2rxss_log_status,
776};
777
778static const struct v4l2_subdev_video_ops xcsi2rxss_video_ops = {
779 .s_stream = xcsi2rxss_s_stream
780};
781
782static const struct v4l2_subdev_pad_ops xcsi2rxss_pad_ops = {
783 .get_fmt = xcsi2rxss_get_format,
784 .set_fmt = xcsi2rxss_set_format,
785 .enum_mbus_code = xcsi2rxss_enum_mbus_code,
786 .link_validate = v4l2_subdev_link_validate_default,
787};
788
789static const struct v4l2_subdev_ops xcsi2rxss_ops = {
790 .core = &xcsi2rxss_core_ops,
791 .video = &xcsi2rxss_video_ops,
792 .pad = &xcsi2rxss_pad_ops
793};
794
795static const struct v4l2_subdev_internal_ops xcsi2rxss_internal_ops = {
796 .init_state = xcsi2rxss_init_state,
797};
798
799static int xcsi2rxss_parse_of(struct xcsi2rxss_state *xcsi2rxss)
800{
801 struct device *dev = xcsi2rxss->dev;
802 struct device_node *node = dev->of_node;
803
804 struct fwnode_handle *ep;
805 struct v4l2_fwnode_endpoint vep = {
806 .bus_type = V4L2_MBUS_CSI2_DPHY
807 };
808 bool en_csi_v20, vfb;
809 int ret;
810
811 en_csi_v20 = of_property_read_bool(np: node, propname: "xlnx,en-csi-v2-0");
812 if (en_csi_v20)
813 xcsi2rxss->en_vcx = of_property_read_bool(np: node, propname: "xlnx,en-vcx");
814
815 xcsi2rxss->enable_active_lanes =
816 of_property_read_bool(np: node, propname: "xlnx,en-active-lanes");
817
818 ret = of_property_read_u32(np: node, propname: "xlnx,csi-pxl-format",
819 out_value: &xcsi2rxss->datatype);
820 if (ret < 0) {
821 dev_err(dev, "missing xlnx,csi-pxl-format property\n");
822 return ret;
823 }
824
825 switch (xcsi2rxss->datatype) {
826 case MIPI_CSI2_DT_YUV422_8B:
827 case MIPI_CSI2_DT_RGB444:
828 case MIPI_CSI2_DT_RGB555:
829 case MIPI_CSI2_DT_RGB565:
830 case MIPI_CSI2_DT_RGB666:
831 case MIPI_CSI2_DT_RGB888:
832 case MIPI_CSI2_DT_RAW6:
833 case MIPI_CSI2_DT_RAW7:
834 case MIPI_CSI2_DT_RAW8:
835 case MIPI_CSI2_DT_RAW10:
836 case MIPI_CSI2_DT_RAW12:
837 case MIPI_CSI2_DT_RAW14:
838 break;
839 case MIPI_CSI2_DT_YUV422_10B:
840 case MIPI_CSI2_DT_RAW16:
841 case MIPI_CSI2_DT_RAW20:
842 if (!en_csi_v20) {
843 ret = -EINVAL;
844 dev_dbg(dev, "enable csi v2 for this pixel format");
845 }
846 break;
847 default:
848 ret = -EINVAL;
849 }
850 if (ret < 0) {
851 dev_err(dev, "invalid csi-pxl-format property!\n");
852 return ret;
853 }
854
855 vfb = of_property_read_bool(np: node, propname: "xlnx,vfb");
856 if (!vfb) {
857 dev_err(dev, "operation without VFB is not supported\n");
858 return -EINVAL;
859 }
860
861 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
862 XVIP_PAD_SINK, endpoint: 0,
863 FWNODE_GRAPH_ENDPOINT_NEXT);
864 if (!ep) {
865 dev_err(dev, "no sink port found");
866 return -EINVAL;
867 }
868
869 ret = v4l2_fwnode_endpoint_parse(fwnode: ep, vep: &vep);
870 fwnode_handle_put(fwnode: ep);
871 if (ret) {
872 dev_err(dev, "error parsing sink port");
873 return ret;
874 }
875
876 dev_dbg(dev, "mipi number lanes = %d\n",
877 vep.bus.mipi_csi2.num_data_lanes);
878
879 xcsi2rxss->max_num_lanes = vep.bus.mipi_csi2.num_data_lanes;
880
881 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
882 XVIP_PAD_SOURCE, endpoint: 0,
883 FWNODE_GRAPH_ENDPOINT_NEXT);
884 if (!ep) {
885 dev_err(dev, "no source port found");
886 return -EINVAL;
887 }
888
889 fwnode_handle_put(fwnode: ep);
890
891 dev_dbg(dev, "vcx %s, %u data lanes (%s), data type 0x%02x\n",
892 xcsi2rxss->en_vcx ? "enabled" : "disabled",
893 xcsi2rxss->max_num_lanes,
894 xcsi2rxss->enable_active_lanes ? "dynamic" : "static",
895 xcsi2rxss->datatype);
896
897 return 0;
898}
899
900static int xcsi2rxss_probe(struct platform_device *pdev)
901{
902 struct v4l2_subdev *subdev;
903 struct xcsi2rxss_state *xcsi2rxss;
904 int num_clks = ARRAY_SIZE(xcsi2rxss_clks);
905 struct device *dev = &pdev->dev;
906 int irq, ret;
907
908 xcsi2rxss = devm_kzalloc(dev, size: sizeof(*xcsi2rxss), GFP_KERNEL);
909 if (!xcsi2rxss)
910 return -ENOMEM;
911
912 xcsi2rxss->dev = dev;
913
914 xcsi2rxss->clks = devm_kmemdup(dev, src: xcsi2rxss_clks,
915 len: sizeof(xcsi2rxss_clks), GFP_KERNEL);
916 if (!xcsi2rxss->clks)
917 return -ENOMEM;
918
919 /* Reset GPIO */
920 xcsi2rxss->rst_gpio = devm_gpiod_get_optional(dev, con_id: "video-reset",
921 flags: GPIOD_OUT_HIGH);
922 if (IS_ERR(ptr: xcsi2rxss->rst_gpio))
923 return dev_err_probe(dev, err: PTR_ERR(ptr: xcsi2rxss->rst_gpio),
924 fmt: "Video Reset GPIO not setup in DT\n");
925
926 ret = xcsi2rxss_parse_of(xcsi2rxss);
927 if (ret < 0)
928 return ret;
929
930 xcsi2rxss->iomem = devm_platform_ioremap_resource(pdev, index: 0);
931 if (IS_ERR(ptr: xcsi2rxss->iomem))
932 return PTR_ERR(ptr: xcsi2rxss->iomem);
933
934 irq = platform_get_irq(pdev, 0);
935 if (irq < 0)
936 return irq;
937
938 ret = devm_request_threaded_irq(dev, irq, NULL,
939 thread_fn: xcsi2rxss_irq_handler, IRQF_ONESHOT,
940 devname: dev_name(dev), dev_id: xcsi2rxss);
941 if (ret) {
942 dev_err(dev, "Err = %d Interrupt handler reg failed!\n", ret);
943 return ret;
944 }
945
946 ret = clk_bulk_get(dev, num_clks, clks: xcsi2rxss->clks);
947 if (ret)
948 return ret;
949
950 /* TODO: Enable/disable clocks at stream on/off time. */
951 ret = clk_bulk_prepare_enable(num_clks, clks: xcsi2rxss->clks);
952 if (ret)
953 goto err_clk_put;
954
955 mutex_init(&xcsi2rxss->lock);
956
957 xcsi2rxss_hard_reset(state: xcsi2rxss);
958 xcsi2rxss_soft_reset(state: xcsi2rxss);
959
960 /* Initialize V4L2 subdevice and media entity */
961 xcsi2rxss->pads[XVIP_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
962 xcsi2rxss->pads[XVIP_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
963
964 /* Initialize the default format */
965 xcsi2rxss->default_format.code =
966 xcsi2rxss_get_nth_mbus(dt: xcsi2rxss->datatype, n: 0);
967 xcsi2rxss->default_format.field = V4L2_FIELD_NONE;
968 xcsi2rxss->default_format.colorspace = V4L2_COLORSPACE_SRGB;
969 xcsi2rxss->default_format.width = XCSI_DEFAULT_WIDTH;
970 xcsi2rxss->default_format.height = XCSI_DEFAULT_HEIGHT;
971 xcsi2rxss->format = xcsi2rxss->default_format;
972
973 /* Initialize V4L2 subdevice and media entity */
974 subdev = &xcsi2rxss->subdev;
975 v4l2_subdev_init(sd: subdev, ops: &xcsi2rxss_ops);
976 subdev->internal_ops = &xcsi2rxss_internal_ops;
977 subdev->dev = dev;
978 strscpy(subdev->name, dev_name(dev), sizeof(subdev->name));
979 subdev->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE;
980 subdev->entity.ops = &xcsi2rxss_media_ops;
981 v4l2_set_subdevdata(sd: subdev, p: xcsi2rxss);
982
983 ret = media_entity_pads_init(entity: &subdev->entity, XCSI_MEDIA_PADS,
984 pads: xcsi2rxss->pads);
985 if (ret < 0)
986 goto error;
987
988 platform_set_drvdata(pdev, data: xcsi2rxss);
989
990 ret = v4l2_async_register_subdev(subdev);
991 if (ret < 0) {
992 dev_err(dev, "failed to register subdev\n");
993 goto error;
994 }
995
996 return 0;
997error:
998 media_entity_cleanup(entity: &subdev->entity);
999 mutex_destroy(lock: &xcsi2rxss->lock);
1000 clk_bulk_disable_unprepare(num_clks, clks: xcsi2rxss->clks);
1001err_clk_put:
1002 clk_bulk_put(num_clks, clks: xcsi2rxss->clks);
1003 return ret;
1004}
1005
1006static void xcsi2rxss_remove(struct platform_device *pdev)
1007{
1008 struct xcsi2rxss_state *xcsi2rxss = platform_get_drvdata(pdev);
1009 struct v4l2_subdev *subdev = &xcsi2rxss->subdev;
1010 int num_clks = ARRAY_SIZE(xcsi2rxss_clks);
1011
1012 v4l2_async_unregister_subdev(sd: subdev);
1013 media_entity_cleanup(entity: &subdev->entity);
1014 mutex_destroy(lock: &xcsi2rxss->lock);
1015 clk_bulk_disable_unprepare(num_clks, clks: xcsi2rxss->clks);
1016 clk_bulk_put(num_clks, clks: xcsi2rxss->clks);
1017}
1018
1019static const struct of_device_id xcsi2rxss_of_id_table[] = {
1020 { .compatible = "xlnx,mipi-csi2-rx-subsystem-5.0", },
1021 { }
1022};
1023MODULE_DEVICE_TABLE(of, xcsi2rxss_of_id_table);
1024
1025static struct platform_driver xcsi2rxss_driver = {
1026 .driver = {
1027 .name = "xilinx-csi2rxss",
1028 .of_match_table = xcsi2rxss_of_id_table,
1029 },
1030 .probe = xcsi2rxss_probe,
1031 .remove = xcsi2rxss_remove,
1032};
1033
1034module_platform_driver(xcsi2rxss_driver);
1035
1036MODULE_AUTHOR("Vishal Sagar <vsagar@xilinx.com>");
1037MODULE_DESCRIPTION("Xilinx MIPI CSI-2 Rx Subsystem Driver");
1038MODULE_LICENSE("GPL v2");
1039

source code of linux/drivers/media/platform/xilinx/xilinx-csi2rxss.c