| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef FS_ENET_FEC_H |
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| 3 | #define FS_ENET_FEC_H |
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| 4 | |
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| 5 | #define FEC_MAX_MULTICAST_ADDRS 64 |
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| 6 | |
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| 7 | /* Interrupt events/masks. |
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| 8 | */ |
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| 9 | #define FEC_ENET_HBERR 0x80000000U /* Heartbeat error */ |
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| 10 | #define FEC_ENET_BABR 0x40000000U /* Babbling receiver */ |
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| 11 | #define FEC_ENET_BABT 0x20000000U /* Babbling transmitter */ |
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| 12 | #define FEC_ENET_GRA 0x10000000U /* Graceful stop complete */ |
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| 13 | #define FEC_ENET_TXF 0x08000000U /* Full frame transmitted */ |
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| 14 | #define FEC_ENET_TXB 0x04000000U /* A buffer was transmitted */ |
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| 15 | #define FEC_ENET_RXF 0x02000000U /* Full frame received */ |
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| 16 | #define FEC_ENET_RXB 0x01000000U /* A buffer was received */ |
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| 17 | #define FEC_ENET_MII 0x00800000U /* MII interrupt */ |
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| 18 | #define FEC_ENET_EBERR 0x00400000U /* SDMA bus error */ |
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| 19 | |
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| 20 | #define FEC_ECNTRL_PINMUX 0x00000004 |
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| 21 | #define FEC_ECNTRL_ETHER_EN 0x00000002 |
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| 22 | #define FEC_ECNTRL_RESET 0x00000001 |
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| 23 | |
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| 24 | /* RMII mode enabled only when MII_MODE bit is set too. */ |
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| 25 | #define FEC_RCNTRL_RMII_MODE (0x00000100 | \ |
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| 26 | FEC_RCNTRL_MII_MODE | FEC_RCNTRL_FCE) |
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| 27 | #define FEC_RCNTRL_FCE 0x00000020 |
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| 28 | #define FEC_RCNTRL_BC_REJ 0x00000010 |
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| 29 | #define FEC_RCNTRL_PROM 0x00000008 |
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| 30 | #define FEC_RCNTRL_MII_MODE 0x00000004 |
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| 31 | #define FEC_RCNTRL_DRT 0x00000002 |
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| 32 | #define FEC_RCNTRL_LOOP 0x00000001 |
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| 33 | |
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| 34 | #define FEC_TCNTRL_FDEN 0x00000004 |
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| 35 | #define FEC_TCNTRL_HBC 0x00000002 |
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| 36 | #define FEC_TCNTRL_GTS 0x00000001 |
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| 37 | |
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| 38 | /* |
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| 39 | * Delay to wait for FEC reset command to complete (in us) |
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| 40 | */ |
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| 41 | #define FEC_RESET_DELAY 50 |
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| 42 | #endif |
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| 43 | |
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